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1.1 root 1: ;; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
9: ;;- Machine descrption for GNU compiler
10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
16: ;; GNU CC is distributed in the hope that it will be useful,
17: ;; but WITHOUT ANY WARRANTY. No author or distributor
18: ;; accepts responsibility to anyone for the consequences of using it
19: ;; or for whether it serves any particular purpose or works at all,
20: ;; unless he says so in writing. Refer to the GNU CC General Public
21: ;; License for full details.
22:
23: ;; Everyone is granted permission to copy, modify and redistribute
24: ;; GNU CC, but only under the conditions described in the
25: ;; GNU CC General Public License. A copy of this license is
26: ;; supposed to have been given to you along with GNU CC so you
27: ;; can know your rights and responsibilities. It should be in a
28: ;; file named COPYING. Among other things, the copyright notice
29: ;; and this notice must be preserved on all copies.
30:
31:
32: ;;- Instruction patterns. When multiple patterns apply,
33: ;;- the first one in the file is chosen.
34: ;;-
35: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
36: ;;-
37: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
38: ;;- updates for most instructions.
39:
40: ; tstsi is first test insn so that it is the one to match
41: ; a constant argument.
42:
43: (define_insn "tstsi"
44: [(set (cc0)
45: (match_operand:SI 0 "general_operand" "rmn"))]
46: ""
47: "*
1.1.1.2 root 48: { cc_status.flags |= CC_REVERSED;
49: operands[1] = const0_rtx;
50: return \"cmpqd %1,%0\"; }")
1.1 root 51:
52: (define_insn "tsthi"
53: [(set (cc0)
54: (match_operand:HI 0 "general_operand" "g"))]
55: ""
56: "*
1.1.1.2 root 57: { cc_status.flags |= CC_REVERSED;
58: operands[1] = const0_rtx;
59: return \"cmpqw %1,%0\"; }")
1.1 root 60:
61: (define_insn "tstqi"
62: [(set (cc0)
63: (match_operand:QI 0 "general_operand" "g"))]
64: ""
65: "*
1.1.1.2 root 66: { cc_status.flags |= CC_REVERSED;
67: operands[1] = const0_rtx;
68: return \"cmpqb %1,%0\"; }")
1.1 root 69:
70: (define_insn "tstdf"
71: [(set (cc0)
72: (match_operand:DF 0 "general_operand" "fmF"))]
73: "TARGET_32081"
74: "*
1.1.1.2 root 75: { cc_status.flags |= CC_REVERSED;
76: operands[1] = dconst0_rtx;
77: return \"cmpl %1,%0\"; }")
1.1 root 78:
79: (define_insn "tstsf"
80: [(set (cc0)
81: (match_operand:SF 0 "general_operand" "fmF"))]
82: "TARGET_32081"
83: "*
1.1.1.2 root 84: { cc_status.flags |= CC_REVERSED;
85: operands[1] = fconst0_rtx;
86: return \"cmpf %1,%0\"; }")
1.1 root 87:
88: (define_insn "cmpdf"
89: [(set (cc0)
90: (minus (match_operand:DF 0 "general_operand" "fmF")
91: (match_operand:DF 1 "general_operand" "fmF")))]
92: "TARGET_32081"
93: "cmpl %0,%1")
94:
95: (define_insn "cmpsf"
96: [(set (cc0)
97: (minus (match_operand:SF 0 "general_operand" "fmF")
98: (match_operand:SF 1 "general_operand" "fmF")))]
99: "TARGET_32081"
100: "cmpf %0,%1")
101:
102: (define_insn "cmpsi"
103: [(set (cc0)
104: (minus (match_operand:SI 0 "general_operand" "rmn")
105: (match_operand:SI 1 "general_operand" "rmn")))]
106: ""
107: "*
108: {
109: if (GET_CODE (operands[1]) == CONST_INT)
110: {
111: int i = INTVAL (operands[1]);
112: if (i <= 7 && i >= -8)
113: {
114: cc_status.flags |= CC_REVERSED;
115: return \"cmpqd %1,%0\";
116: }
117: }
118: cc_status.flags &= ~CC_REVERSED;
119: if (GET_CODE (operands[0]) == CONST_INT)
120: {
121: int i = INTVAL (operands[0]);
122: if (i <= 7 && i >= -8)
123: return \"cmpqd %0,%1\";
124: }
125: return \"cmpd %0,%1\";
126: }")
127:
128: (define_insn "cmphi"
129: [(set (cc0)
130: (minus (match_operand:HI 0 "general_operand" "g")
131: (match_operand:HI 1 "general_operand" "g")))]
132: ""
133: "*
134: {
135: if (GET_CODE (operands[1]) == CONST_INT)
136: {
137: short i = INTVAL (operands[1]);
138: if (i <= 7 && i >= -8)
139: {
140: cc_status.flags |= CC_REVERSED;
141: if (INTVAL (operands[1]) > 7)
142: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
143: return \"cmpqw %1,%0\";
144: }
145: }
146: cc_status.flags &= ~CC_REVERSED;
147: if (GET_CODE (operands[0]) == CONST_INT)
148: {
149: short i = INTVAL (operands[0]);
150: if (i <= 7 && i >= -8)
151: {
152: if (INTVAL (operands[0]) > 7)
153: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
154: return \"cmpqw %0,%1\";
155: }
156: }
157: return \"cmpw %0,%1\";
158: }")
159:
160: (define_insn "cmpqi"
161: [(set (cc0)
162: (minus (match_operand:QI 0 "general_operand" "g")
163: (match_operand:QI 1 "general_operand" "g")))]
164: ""
165: "*
166: {
167: if (GET_CODE (operands[1]) == CONST_INT)
168: {
169: char i = INTVAL (operands[1]);
170: if (i <= 7 && i >= -8)
171: {
172: cc_status.flags |= CC_REVERSED;
173: if (INTVAL (operands[1]) > 7)
174: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
175: return \"cmpqb %1,%0\";
176: }
177: }
178: cc_status.flags &= ~CC_REVERSED;
179: if (GET_CODE (operands[0]) == CONST_INT)
180: {
181: char i = INTVAL (operands[0]);
182: if (i <= 7 && i >= -8)
183: {
184: if (INTVAL (operands[0]) > 7)
185: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
186: return \"cmpqb %0,%1\";
187: }
188: }
189: return \"cmpb %0,%1\";
190: }")
191:
192: (define_insn "movdf"
1.1.1.8 root 193: [(set (match_operand:DF 0 "general_operand" "=&fg<")
1.1 root 194: (match_operand:DF 1 "general_operand" "fFg"))]
195: ""
196: "*
197: {
198: if (FP_REG_P (operands[0]))
199: {
200: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
201: return \"movl %1,%0\";
202: if (REG_P (operands[1]))
203: {
204: rtx xoperands[2];
205: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
206: output_asm_insn (\"movd %1,tos\", xoperands);
207: output_asm_insn (\"movd %1,tos\", operands);
208: return \"movl tos,%0\";
209: }
210: return \"movl %1,%0\";
211: }
212: else if (FP_REG_P (operands[1]))
213: {
214: if (REG_P (operands[0]))
215: {
216: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
217: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
218: return \"movd tos,%0\";
219: }
220: else
221: return \"movl %1,%0\";
222: }
223: return output_move_double (operands);
224: }")
225:
226: (define_insn "movsf"
227: [(set (match_operand:SF 0 "general_operand" "=fg<")
228: (match_operand:SF 1 "general_operand" "fFg"))]
229: ""
230: "*
231: {
232: if (FP_REG_P (operands[0]))
233: {
234: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
235: return \"movd %1,tos\;movf tos,%0\";
236: else
237: return \"movf %1,%0\";
238: }
239: else if (FP_REG_P (operands[1]))
240: {
241: if (REG_P (operands[0]))
242: return \"movf %1,tos\;movd tos,%0\";
243: return \"movf %1,%0\";
244: }
245: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
246: {
247: /* Is there a better machine-independent way to to this? */
248: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]));
249: return \"movd %1,%0\";
250: }
251: else return \"movd %1,%0\";
252: }")
253:
254: (define_insn ""
255: [(set (match_operand:TI 0 "memory_operand" "=m")
256: (match_operand:TI 1 "memory_operand" "m"))]
257: ""
258: "movmd %1,%0,4")
259:
260: (define_insn "movdi"
1.1.1.8 root 261: [(set (match_operand:DI 0 "general_operand" "=&g<")
1.1.1.3 root 262: (match_operand:DI 1 "general_operand" "gF"))]
1.1 root 263: ""
264: "* return output_move_double (operands); ")
265:
1.1.1.9 ! root 266: ;; This special case must precede movsi.
! 267: (define_insn ""
! 268: [(set (reg:SI 17)
! 269: (match_operand:SI 0 "general_operand" "rmn"))]
! 270: ""
! 271: "lprd sp,%0")
! 272:
1.1 root 273: (define_insn "movsi"
274: [(set (match_operand:SI 0 "general_operand" "=g<")
275: (match_operand:SI 1 "general_operand" "gx"))]
276: ""
277: "*
278: { if (GET_CODE (operands[1]) == CONST_INT)
279: {
280: int i = INTVAL (operands[1]);
281: if (i <= 7 && i >= -8)
282: return \"movqd %1,%0\";
283: if (i < 0x4000 && i >= -0x4000)
1.1.1.4 root 284: #ifdef GNX_V3
285: return \"addr %c1,%0\";
286: #else
1.1.1.2 root 287: return \"addr @%c1,%0\";
1.1.1.4 root 288: #endif
1.1 root 289: return \"movd %1,%0\";
290: }
291: else if (GET_CODE (operands[1]) == REG)
292: if (REGNO (operands[1]) < 16)
293: return \"movd %1,%0\";
294: else if (REGNO (operands[1]) == 16)
295: return \"addr 0(fp),%0\";
296: else return \"addr tos,%0\";
297: else if (GET_CODE (operands[1]) == MEM)
298: return \"movd %1,%0\";
1.1.1.2 root 299: /* Check if this effective address can be
300: calculated faster by pulling it apart. */
301: if (REG_P (operands[0])
302: && GET_CODE (operands[1]) == MULT
303: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
304: && (INTVAL (XEXP (operands[1], 1)) == 2
305: || INTVAL (XEXP (operands[1], 1)) == 4))
306: {
307: rtx xoperands[3];
308: xoperands[0] = operands[0];
309: xoperands[1] = XEXP (operands[1], 0);
310: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
311: return output_shift_insn (xoperands);
312: }
1.1 root 313: return \"addr %a1,%0\";
314: }")
315:
316: (define_insn "movhi"
317: [(set (match_operand:HI 0 "general_operand" "=g<")
318: (match_operand:HI 1 "general_operand" "g"))]
319: ""
320: "*
321: {
322: if (GET_CODE (operands[1]) == CONST_INT)
323: {
324: short i = INTVAL (operands[1]);
325: if (i <= 7 && i >= -8)
326: {
327: if (INTVAL (operands[1]) > 7)
328: operands[1] =
329: gen_rtx (CONST_INT, VOIDmode, i);
330: return \"movqw %1,%0\";
331: }
332: }
333: return \"movw %1,%0\";
334: }")
335:
336: (define_insn "movstricthi"
337: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
338: (match_operand:HI 1 "general_operand" "g"))]
339: ""
340: "*
341: {
342: if (GET_CODE (operands[1]) == CONST_INT
343: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
344: return \"movqw %1,%0\";
345: return \"movw %1,%0\";
346: }")
347:
348: (define_insn "movqi"
349: [(set (match_operand:QI 0 "general_operand" "=g<")
350: (match_operand:QI 1 "general_operand" "g"))]
351: ""
352: "*
353: { if (GET_CODE (operands[1]) == CONST_INT)
354: {
355: char char_val = (char)INTVAL (operands[1]);
356: if (char_val <= 7 && char_val >= -8)
357: {
358: if (INTVAL (operands[1]) > 7)
359: operands[1] =
360: gen_rtx (CONST_INT, VOIDmode, char_val);
361: return \"movqb %1,%0\";
362: }
363: }
364: return \"movb %1,%0\";
365: }")
366:
367: (define_insn "movstrictqi"
368: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
369: (match_operand:QI 1 "general_operand" "g"))]
370: ""
371: "*
372: {
373: if (GET_CODE (operands[1]) == CONST_INT
374: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
375: return \"movqb %1,%0\";
376: return \"movb %1,%0\";
377: }")
378:
379: ;; The definition of this insn does not really explain what it does,
380: ;; but it should suffice
381: ;; that anything generated as this insn will be recognized as one
382: ;; and that it won't successfully combine with anything.
383: (define_insn "movstrsi"
384: [(set (match_operand:BLK 0 "general_operand" "=g")
385: (match_operand:BLK 1 "general_operand" "g"))
386: (use (match_operand:SI 2 "general_operand" "rmn"))
387: (clobber (reg:SI 0))
388: (clobber (reg:SI 1))
389: (clobber (reg:SI 2))]
390: ""
391: "*
392: {
393: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
394: abort ();
395: operands[0] = XEXP (operands[0], 0);
396: operands[1] = XEXP (operands[1], 0);
397: if (GET_CODE (operands[0]) == MEM)
398: if (GET_CODE (operands[1]) == MEM)
399: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
400: else
401: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
402: else if (GET_CODE (operands[1]) == MEM)
403: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
404: else
405: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
406:
407: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
408: {
409: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
410: if ((unsigned) INTVAL (operands[2]) <= 7)
411: return \"movqd %2,r0\;movsd\";
412: else
413: return \"movd %2,r0\;movsd\";
414: }
415: else
416: {
417: return \"movd %2,r0\;movsb\";
418: }
419: }")
420:
421: ;; Extension and truncation insns.
422: ;; Those for integer source operand
423: ;; are ordered widest source type first.
424:
425: (define_insn "truncsiqi2"
426: [(set (match_operand:QI 0 "general_operand" "=g<")
1.1.1.2 root 427: (truncate:QI (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 428: ""
429: "movb %1,%0")
430:
431: (define_insn "truncsihi2"
432: [(set (match_operand:HI 0 "general_operand" "=g<")
1.1.1.2 root 433: (truncate:HI (match_operand:SI 1 "general_operand" "rmn")))]
1.1 root 434: ""
435: "movw %1,%0")
436:
437: (define_insn "trunchiqi2"
438: [(set (match_operand:QI 0 "general_operand" "=g<")
439: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
440: ""
441: "movb %1,%0")
442:
443: (define_insn "extendhisi2"
444: [(set (match_operand:SI 0 "general_operand" "=g<")
445: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
446: ""
447: "movxwd %1,%0")
448:
449: (define_insn "extendqihi2"
450: [(set (match_operand:HI 0 "general_operand" "=g<")
451: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
452: ""
453: "movxbw %1,%0")
454:
455: (define_insn "extendqisi2"
456: [(set (match_operand:SI 0 "general_operand" "=g<")
457: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
458: ""
459: "movxbd %1,%0")
460:
461: (define_insn "extendsfdf2"
462: [(set (match_operand:DF 0 "general_operand" "=fm<")
463: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
464: "TARGET_32081"
465: "movfl %1,%0")
466:
467: (define_insn "truncdfsf2"
468: [(set (match_operand:SF 0 "general_operand" "=fm<")
469: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
470: "TARGET_32081"
471: "movlf %1,%0")
472:
473: (define_insn "zero_extendhisi2"
474: [(set (match_operand:SI 0 "general_operand" "=g<")
475: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
476: ""
477: "movzwd %1,%0")
478:
479: (define_insn "zero_extendqihi2"
480: [(set (match_operand:HI 0 "general_operand" "=g<")
481: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
482: ""
483: "movzbw %1,%0")
484:
485: (define_insn "zero_extendqisi2"
486: [(set (match_operand:SI 0 "general_operand" "=g<")
487: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
488: ""
489: "movzbd %1,%0")
490:
491: ;; Fix-to-float conversion insns.
492: ;; Note that the ones that start with SImode come first.
493: ;; That is so that an operand that is a CONST_INT
494: ;; (and therefore lacks a specific machine mode).
495: ;; will be recognized as SImode (which is always valid)
496: ;; rather than as QImode or HImode.
497:
498: ;; Rumor has it that the National part does not correctly convert
499: ;; constant ints to floats. This conversion is therefore disabled.
500: ;; A register must be used to perform the conversion.
501:
502: (define_insn "floatsisf2"
503: [(set (match_operand:SF 0 "general_operand" "=fm<")
504: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
505: "TARGET_32081"
506: "movdf %1,%0")
507:
508: (define_insn "floatsidf2"
509: [(set (match_operand:DF 0 "general_operand" "=fm<")
510: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
511: "TARGET_32081"
512: "movdl %1,%0")
513:
514: (define_insn "floathisf2"
515: [(set (match_operand:SF 0 "general_operand" "=fm<")
516: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
517: "TARGET_32081"
518: "movwf %1,%0")
519:
520: (define_insn "floathidf2"
521: [(set (match_operand:DF 0 "general_operand" "=fm<")
522: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
523: "TARGET_32081"
524: "movwl %1,%0")
525:
526: (define_insn "floatqisf2"
527: [(set (match_operand:SF 0 "general_operand" "=fm<")
528: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
529: "TARGET_32081"
530: "movbf %1,%0")
531:
1.1.1.3 root 532: ; Some assemblers warn that this insn doesn't work.
533: ; Maybe they know something we don't.
534: ;(define_insn "floatqidf2"
535: ; [(set (match_operand:DF 0 "general_operand" "=fm<")
536: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
537: ; "TARGET_32081"
538: ; "movbl %1,%0")
1.1 root 539:
540: ;; Float-to-fix conversion insns.
541: ;; The sequent compiler always generates "trunc" insns.
542:
543: (define_insn "fixsfqi2"
544: [(set (match_operand:QI 0 "general_operand" "=g<")
545: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
546: "TARGET_32081"
547: "truncfb %1,%0")
548:
549: (define_insn "fixsfhi2"
550: [(set (match_operand:HI 0 "general_operand" "=g<")
551: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
552: "TARGET_32081"
553: "truncfw %1,%0")
554:
555: (define_insn "fixsfsi2"
556: [(set (match_operand:SI 0 "general_operand" "=g<")
557: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
558: "TARGET_32081"
559: "truncfd %1,%0")
560:
561: (define_insn "fixdfqi2"
562: [(set (match_operand:QI 0 "general_operand" "=g<")
563: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
564: "TARGET_32081"
565: "trunclb %1,%0")
566:
567: (define_insn "fixdfhi2"
568: [(set (match_operand:HI 0 "general_operand" "=g<")
569: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
570: "TARGET_32081"
571: "trunclw %1,%0")
572:
573: (define_insn "fixdfsi2"
574: [(set (match_operand:SI 0 "general_operand" "=g<")
575: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
576: "TARGET_32081"
577: "truncld %1,%0")
578:
579: ;; Unsigned
580:
581: (define_insn "fixunssfqi2"
582: [(set (match_operand:QI 0 "general_operand" "=g<")
583: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
584: "TARGET_32081"
585: "truncfb %1,%0")
586:
587: (define_insn "fixunssfhi2"
588: [(set (match_operand:HI 0 "general_operand" "=g<")
589: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
590: "TARGET_32081"
591: "truncfw %1,%0")
592:
593: (define_insn "fixunssfsi2"
594: [(set (match_operand:SI 0 "general_operand" "=g<")
595: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
596: "TARGET_32081"
597: "truncfd %1,%0")
598:
599: (define_insn "fixunsdfqi2"
600: [(set (match_operand:QI 0 "general_operand" "=g<")
601: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
602: "TARGET_32081"
603: "trunclb %1,%0")
604:
605: (define_insn "fixunsdfhi2"
606: [(set (match_operand:HI 0 "general_operand" "=g<")
607: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
608: "TARGET_32081"
609: "trunclw %1,%0")
610:
611: (define_insn "fixunsdfsi2"
612: [(set (match_operand:SI 0 "general_operand" "=g<")
613: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
614: "TARGET_32081"
615: "truncld %1,%0")
616:
617: ;;; These are not yet used by GCC
618: (define_insn "fix_truncsfqi2"
619: [(set (match_operand:QI 0 "general_operand" "=g<")
620: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
621: "TARGET_32081"
622: "truncfb %1,%0")
623:
624: (define_insn "fix_truncsfhi2"
625: [(set (match_operand:HI 0 "general_operand" "=g<")
626: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
627: "TARGET_32081"
628: "truncfw %1,%0")
629:
630: (define_insn "fix_truncsfsi2"
631: [(set (match_operand:SI 0 "general_operand" "=g<")
632: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
633: "TARGET_32081"
634: "truncfd %1,%0")
635:
636: (define_insn "fix_truncdfqi2"
637: [(set (match_operand:QI 0 "general_operand" "=g<")
638: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
639: "TARGET_32081"
640: "trunclb %1,%0")
641:
642: (define_insn "fix_truncdfhi2"
643: [(set (match_operand:HI 0 "general_operand" "=g<")
644: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
645: "TARGET_32081"
646: "trunclw %1,%0")
647:
648: (define_insn "fix_truncdfsi2"
649: [(set (match_operand:SI 0 "general_operand" "=g<")
650: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
651: "TARGET_32081"
652: "truncld %1,%0")
653:
654: ;;- All kinds of add instructions.
655:
656: (define_insn "adddf3"
657: [(set (match_operand:DF 0 "general_operand" "=fm")
658: (plus:DF (match_operand:DF 1 "general_operand" "%0")
659: (match_operand:DF 2 "general_operand" "fmF")))]
660: "TARGET_32081"
661: "addl %2,%0")
662:
663:
664: (define_insn "addsf3"
665: [(set (match_operand:SF 0 "general_operand" "=fm")
666: (plus:SF (match_operand:SF 1 "general_operand" "%0")
667: (match_operand:SF 2 "general_operand" "fmF")))]
668: "TARGET_32081"
669: "addf %2,%0")
670:
671: (define_insn ""
672: [(set (reg:SI 17)
673: (plus:SI (reg:SI 17)
674: (match_operand:SI 0 "immediate_operand" "i")))]
675: "GET_CODE (operands[0]) == CONST_INT"
676: "*
677: {
1.1.1.6 root 678: #if defined(ns32532)
679: if (INTVAL(operands[0]) == 8)
680: return \"cmpd tos,tos # adjsp -8\";
681: #endif
682: #if defined(ns32532) || defined(ns32332)
683: if (INTVAL(operands[0]) == 4)
684: return \"cmpqd %$0,tos # adjsp -4\";
685: #endif
1.1 root 686: if (INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
687: return \"adjspb %$%n0\";
688: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
689: return \"adjspw %$%n0\";
690: return \"adjspd %$%n0\";
691: }")
692:
693: (define_insn ""
694: [(set (match_operand:SI 0 "general_operand" "=g<")
695: (plus:SI (reg:SI 16)
696: (match_operand:SI 1 "immediate_operand" "i")))]
697: "GET_CODE (operands[1]) == CONST_INT"
1.1.1.2 root 698: "addr %c1(fp),%0")
1.1 root 699:
700: (define_insn ""
701: [(set (match_operand:SI 0 "general_operand" "=g<")
702: (plus:SI (reg:SI 17)
703: (match_operand:SI 1 "immediate_operand" "i")))]
704: "GET_CODE (operands[1]) == CONST_INT"
1.1.1.2 root 705: "addr %c1(sp),%0")
1.1 root 706:
707: (define_insn "addsi3"
1.1.1.9 ! root 708: [(set (match_operand:SI 0 "general_operand" "=g,=g<")
! 709: (plus:SI (match_operand:SI 1 "general_operand" "%0,%r")
! 710: (match_operand:SI 2 "general_operand" "rmn,n")))]
1.1 root 711: ""
712: "*
713: {
1.1.1.9 ! root 714: if (which_alternative == 1)
! 715: return \"addr %c2(%1),%0\";
1.1 root 716: if (GET_CODE (operands[2]) == CONST_INT)
717: {
718: int i = INTVAL (operands[2]);
719:
720: if (i <= 7 && i >= -8)
721: return \"addqd %2,%0\";
722: else if (GET_CODE (operands[0]) == REG
723: && i < 0x4000 && i >= -0x4000)
1.1.1.2 root 724: return \"addr %c2(%0),%0\";
1.1 root 725: }
726: return \"addd %2,%0\";
727: }")
728:
729: (define_insn "addhi3"
730: [(set (match_operand:HI 0 "general_operand" "=g")
731: (plus:HI (match_operand:HI 1 "general_operand" "%0")
732: (match_operand:HI 2 "general_operand" "g")))]
733: ""
734: "*
735: { if (GET_CODE (operands[2]) == CONST_INT)
736: {
737: int i = INTVAL (operands[2]);
738: if (i <= 7 && i >= -8)
739: return \"addqw %2,%0\";
740: }
741: return \"addw %2,%0\";
742: }")
743:
744: (define_insn ""
745: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
746: (plus:HI (match_operand:HI 1 "general_operand" "0")
747: (match_operand:HI 2 "general_operand" "g")))]
748: ""
749: "*
750: {
751: if (GET_CODE (operands[1]) == CONST_INT
752: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
753: return \"addqw %1,%0\";
754: return \"addw %1,%0\";
755: }")
756:
757: (define_insn "addqi3"
758: [(set (match_operand:QI 0 "general_operand" "=g")
759: (plus:QI (match_operand:QI 1 "general_operand" "%0")
760: (match_operand:QI 2 "general_operand" "g")))]
761: ""
762: "*
763: { if (GET_CODE (operands[2]) == CONST_INT)
764: {
765: int i = INTVAL (operands[2]);
766: if (i <= 7 && i >= -8)
767: return \"addqb %2,%0\";
768: }
769: return \"addb %2,%0\";
770: }")
771:
772: (define_insn ""
773: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
774: (plus:QI (match_operand:QI 1 "general_operand" "0")
775: (match_operand:QI 2 "general_operand" "g")))]
776: ""
777: "*
778: {
779: if (GET_CODE (operands[1]) == CONST_INT
780: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
781: return \"addqb %1,%0\";
782: return \"addb %1,%0\";
783: }")
784:
785: ;;- All kinds of subtract instructions.
786:
787: (define_insn "subdf3"
788: [(set (match_operand:DF 0 "general_operand" "=fm")
789: (minus:DF (match_operand:DF 1 "general_operand" "0")
790: (match_operand:DF 2 "general_operand" "fmF")))]
791: "TARGET_32081"
792: "subl %2,%0")
793:
794: (define_insn "subsf3"
795: [(set (match_operand:SF 0 "general_operand" "=fm")
796: (minus:SF (match_operand:SF 1 "general_operand" "0")
797: (match_operand:SF 2 "general_operand" "fmF")))]
798: "TARGET_32081"
799: "subf %2,%0")
800:
801: (define_insn ""
802: [(set (reg:SI 17)
803: (minus:SI (reg:SI 17)
804: (match_operand:SI 0 "immediate_operand" "i")))]
805: "GET_CODE (operands[0]) == CONST_INT"
806: "*
807: {
808: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
809: && INTVAL(operands[0]) > -64)
810: return \"adjspb %0\";
811: return \"adjspd %0\";
812: }")
813:
814: (define_insn "subsi3"
815: [(set (match_operand:SI 0 "general_operand" "=g")
816: (minus:SI (match_operand:SI 1 "general_operand" "0")
817: (match_operand:SI 2 "general_operand" "rmn")))]
818: ""
819: "*
820: { if (GET_CODE (operands[2]) == CONST_INT)
821: {
822: int i = INTVAL (operands[2]);
823:
824: if (i <= 8 && i >= -7)
825: return \"addqd %$%n2,%0\";
826: }
827: return \"subd %2,%0\";
828: }")
829:
830: (define_insn "subhi3"
831: [(set (match_operand:HI 0 "general_operand" "=g")
832: (minus:HI (match_operand:HI 1 "general_operand" "0")
833: (match_operand:HI 2 "general_operand" "g")))]
834: ""
835: "*
836: { if (GET_CODE (operands[2]) == CONST_INT)
837: {
838: int i = INTVAL (operands[2]);
839:
840: if (i <= 8 && i >= -7)
841: return \"addqw %$%n2,%0\";
842: }
843: return \"subw %2,%0\";
844: }")
845:
846: (define_insn ""
847: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
848: (minus:HI (match_operand:HI 1 "general_operand" "0")
849: (match_operand:HI 2 "general_operand" "g")))]
850: ""
851: "*
852: {
853: if (GET_CODE (operands[1]) == CONST_INT
854: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
855: return \"addqw %$%n1,%0\";
856: return \"subw %1,%0\";
857: }")
858:
859: (define_insn "subqi3"
860: [(set (match_operand:QI 0 "general_operand" "=g")
861: (minus:QI (match_operand:QI 1 "general_operand" "0")
862: (match_operand:QI 2 "general_operand" "g")))]
863: ""
864: "*
865: { if (GET_CODE (operands[2]) == CONST_INT)
866: {
867: int i = INTVAL (operands[2]);
868:
869: if (i <= 8 && i >= -7)
870: return \"addqb %$%n2,%0\";
871: }
872: return \"subb %2,%0\";
873: }")
874:
875: (define_insn ""
876: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
877: (minus:QI (match_operand:QI 1 "general_operand" "0")
878: (match_operand:QI 2 "general_operand" "g")))]
879: ""
880: "*
881: {
882: if (GET_CODE (operands[1]) == CONST_INT
883: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
884: return \"addqb %$%n1,%0\";
885: return \"subb %1,%0\";
886: }")
887:
888: ;;- Multiply instructions.
889:
890: (define_insn "muldf3"
891: [(set (match_operand:DF 0 "general_operand" "=fm")
892: (mult:DF (match_operand:DF 1 "general_operand" "%0")
893: (match_operand:DF 2 "general_operand" "fmF")))]
894: "TARGET_32081"
895: "mull %2,%0")
896:
897: (define_insn "mulsf3"
898: [(set (match_operand:SF 0 "general_operand" "=fm")
899: (mult:SF (match_operand:SF 1 "general_operand" "%0")
900: (match_operand:SF 2 "general_operand" "fmF")))]
901: "TARGET_32081"
902: "mulf %2,%0")
903:
904: (define_insn "mulsi3"
905: [(set (match_operand:SI 0 "general_operand" "=g")
906: (mult:SI (match_operand:SI 1 "general_operand" "%0")
907: (match_operand:SI 2 "general_operand" "rmn")))]
908: ""
909: "muld %2,%0")
910:
911: (define_insn "mulhi3"
912: [(set (match_operand:HI 0 "general_operand" "=g")
913: (mult:HI (match_operand:HI 1 "general_operand" "%0")
914: (match_operand:HI 2 "general_operand" "g")))]
915: ""
916: "mulw %2,%0")
917:
918: (define_insn "mulqi3"
919: [(set (match_operand:QI 0 "general_operand" "=g")
920: (mult:QI (match_operand:QI 1 "general_operand" "%0")
921: (match_operand:QI 2 "general_operand" "g")))]
922: ""
923: "mulb %2,%0")
924:
925: (define_insn "umulsi3"
926: [(set (match_operand:SI 0 "general_operand" "=g")
927: (umult:SI (match_operand:SI 1 "general_operand" "%0")
1.1.1.2 root 928: (match_operand:SI 2 "general_operand" "rmn")))]
1.1 root 929: ""
930: "muld %2,%0")
931:
932: (define_insn "umulhi3"
933: [(set (match_operand:HI 0 "general_operand" "=g")
934: (umult:HI (match_operand:HI 1 "general_operand" "%0")
935: (match_operand:HI 2 "general_operand" "g")))]
936: ""
937: "mulw %2,%0")
938:
939: (define_insn "umulqi3"
940: [(set (match_operand:QI 0 "general_operand" "=g")
941: (umult:QI (match_operand:QI 1 "general_operand" "%0")
942: (match_operand:QI 2 "general_operand" "g")))]
943: ""
944: "mulb %2,%0")
945:
946: (define_insn "umulsidi3"
947: [(set (match_operand:DI 0 "general_operand" "=g")
948: (umult:DI (match_operand:SI 1 "general_operand" "0")
949: (match_operand:SI 2 "general_operand" "rmn")))]
950: ""
951: "meid %2,%0")
952:
953: ;;- Divide instructions.
954:
955: (define_insn "divdf3"
956: [(set (match_operand:DF 0 "general_operand" "=fm")
957: (div:DF (match_operand:DF 1 "general_operand" "0")
958: (match_operand:DF 2 "general_operand" "fmF")))]
959: "TARGET_32081"
960: "divl %2,%0")
961:
962: (define_insn "divsf3"
963: [(set (match_operand:SF 0 "general_operand" "=fm")
964: (div:SF (match_operand:SF 1 "general_operand" "0")
965: (match_operand:SF 2 "general_operand" "fmF")))]
966: "TARGET_32081"
967: "divf %2,%0")
968:
969: (define_insn "divsi3"
970: [(set (match_operand:SI 0 "general_operand" "=g")
971: (div:SI (match_operand:SI 1 "general_operand" "0")
972: (match_operand:SI 2 "general_operand" "rmn")))]
973: ""
974: "quod %2,%0")
975:
976: (define_insn "divhi3"
977: [(set (match_operand:HI 0 "general_operand" "=g")
978: (div:HI (match_operand:HI 1 "general_operand" "0")
979: (match_operand:HI 2 "general_operand" "g")))]
980: ""
981: "quow %2,%0")
982:
983: (define_insn "divqi3"
984: [(set (match_operand:QI 0 "general_operand" "=g")
985: (div:QI (match_operand:QI 1 "general_operand" "0")
986: (match_operand:QI 2 "general_operand" "g")))]
987: ""
988: "quob %2,%0")
989:
990: (define_insn "udivsi3"
991: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 992: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 993: (match_operand:SI 2 "general_operand" "rmn")))]
994: ""
995: "*
996: {
997: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
998: return \"deid %2,%0\;movd %1,%0\";
999: }")
1000:
1001: (define_insn "udivhi3"
1002: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 root 1003: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1004: (match_operand:HI 2 "general_operand" "g")))]
1005: ""
1006: "*
1007: {
1008: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
1009: return \"deiw %2,%0\;movw %1,%0\";
1010: }")
1011:
1012: (define_insn "udivqi3"
1013: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.2 root 1014: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1015: (match_operand:QI 2 "general_operand" "g")))]
1016: ""
1017: "*
1018: {
1019: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1020: return \"deib %2,%0\;movb %1,%0\";
1021: }")
1022:
1023: ;; Remainder instructions.
1024:
1025: (define_insn "modsi3"
1026: [(set (match_operand:SI 0 "general_operand" "=g")
1027: (mod:SI (match_operand:SI 1 "general_operand" "0")
1028: (match_operand:SI 2 "general_operand" "rmn")))]
1029: ""
1030: "remd %2,%0")
1031:
1032: (define_insn "modhi3"
1033: [(set (match_operand:HI 0 "general_operand" "=g")
1034: (mod:HI (match_operand:HI 1 "general_operand" "0")
1035: (match_operand:HI 2 "general_operand" "g")))]
1036: ""
1037: "remw %2,%0")
1038:
1039: (define_insn "modqi3"
1040: [(set (match_operand:QI 0 "general_operand" "=g")
1041: (mod:QI (match_operand:QI 1 "general_operand" "0")
1042: (match_operand:QI 2 "general_operand" "g")))]
1043: ""
1044: "remb %2,%0")
1045:
1046: (define_insn "umodsi3"
1047: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 1048: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1049: (match_operand:SI 2 "general_operand" "rmn")))]
1050: ""
1051: "deid %2,%0")
1052:
1053: (define_insn "umodhi3"
1054: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 root 1055: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1056: (match_operand:HI 2 "general_operand" "g")))]
1057: ""
1058: "deiw %2,%0")
1059:
1060: (define_insn "umodqi3"
1061: [(set (match_operand:QI 0 "register_operand" "=r")
1.1.1.2 root 1062: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1.1 root 1063: (match_operand:QI 2 "general_operand" "g")))]
1064: ""
1065: "deib %2,%0")
1066:
1067: ; This isn't be usable in its current form.
1068: ;(define_insn "udivmoddisi4"
1069: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1070: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1071: ; (match_operand:SI 2 "general_operand" "rmn")))
1072: ; (set (subreg:SI (match_dup 0) 0)
1073: ; (umod:SI (match_dup 1) (match_dup 2)))]
1074: ; ""
1075: ; "deid %2,%0")
1076:
1077: ;;- Logical Instructions: AND
1078:
1079: (define_insn "andsi3"
1080: [(set (match_operand:SI 0 "general_operand" "=g")
1081: (and:SI (match_operand:SI 1 "general_operand" "%0")
1082: (match_operand:SI 2 "general_operand" "rmn")))]
1083: ""
1084: "*
1085: {
1.1.1.9 ! root 1086: if (GET_CODE (operands[2]) == CONST_INT)
! 1087: {
! 1088: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
! 1089: {
! 1090: if (INTVAL (operands[2]) == 0xffffff00)
! 1091: return \"movqb %$0,%0\";
! 1092: else
! 1093: {
! 1094: operands[2] = gen_rtx (CONST_INT, VOIDmode,
! 1095: INTVAL (operands[2]) & 0xff);
! 1096: return \"andb %2,%0\";
! 1097: }
! 1098: }
! 1099: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
! 1100: {
! 1101: if (INTVAL (operands[2]) == 0xffff0000)
! 1102: return \"movqw %$0,%0\";
! 1103: else
! 1104: {
! 1105: operands[2] = gen_rtx (CONST_INT, VOIDmode,
! 1106: INTVAL (operands[2]) & 0xffff);
! 1107: return \"andw %2,%0\";
! 1108: }
! 1109: }
! 1110: }
1.1 root 1111: }
1112: return \"andd %2,%0\";
1113: }")
1114:
1115: (define_insn "andhi3"
1116: [(set (match_operand:HI 0 "general_operand" "=g")
1117: (and:HI (match_operand:HI 1 "general_operand" "%0")
1118: (match_operand:HI 2 "general_operand" "g")))]
1119: ""
1120: "*
1121: {
1122: if (GET_CODE (operands[2]) == CONST_INT
1123: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1.1.1.9 ! root 1124: {
! 1125: if (INTVAL (operands[2]) == 0xffffff00)
! 1126: return \"movqb %$0,%0\";
! 1127: else
! 1128: {
! 1129: operands[2] = gen_rtx (CONST_INT, VOIDmode,
! 1130: INTVAL (operands[2]) & 0xff);
! 1131: return \"andb %2,%0\";
! 1132: }
1.1 root 1133: }
1134: return \"andw %2,%0\";
1135: }")
1136:
1137: (define_insn "andqi3"
1138: [(set (match_operand:QI 0 "general_operand" "=g")
1139: (and:QI (match_operand:QI 1 "general_operand" "%0")
1140: (match_operand:QI 2 "general_operand" "g")))]
1141: ""
1142: "andb %2,%0")
1143:
1144: (define_insn "andcbsi3"
1145: [(set (match_operand:SI 0 "general_operand" "=g")
1146: (and:SI (match_operand:SI 1 "general_operand" "0")
1147: (not:SI (match_operand:SI 2 "general_operand" "rmn"))))]
1148: ""
1149: "*
1150: {
1151: if (GET_CODE (operands[2]) == CONST_INT)
1152: {
1153: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1154: return \"bicb %2,%0\";
1155: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1156: return \"bicw %2,%0\";
1157: }
1158: return \"bicd %2,%0\";
1159: }")
1160:
1161: (define_insn ""
1162: [(set (match_operand:SI 0 "general_operand" "=g")
1163: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1164: (match_operand:SI 2 "general_operand" "0")))]
1165: ""
1166: "*
1167: {
1168: if (GET_CODE (operands[1]) == CONST_INT)
1169: {
1170: if ((INTVAL (operands[1]) & 0xffffff00) == 0)
1171: return \"bicb %1,%0\";
1172: if ((INTVAL (operands[1]) & 0xffff0000) == 0)
1173: return \"bicw %1,%0\";
1174: }
1175: return \"bicd %1,%0\";
1176: }")
1177:
1178: (define_insn "andcbhi3"
1179: [(set (match_operand:HI 0 "general_operand" "=g")
1180: (and:HI (match_operand:HI 1 "general_operand" "%0")
1181: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
1182: ""
1183: "*
1184: {
1185: if (GET_CODE (operands[2]) == CONST_INT
1186: && (INTVAL (operands[2]) & 0xffffff00) == 0)
1187: return \"bicb %2,%0\";
1188: return \"bicw %2,%0\";
1189: }")
1190:
1191: (define_insn ""
1192: [(set (match_operand:HI 0 "general_operand" "=g")
1193: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1194: (match_operand:HI 2 "general_operand" "0")))]
1195: ""
1196: "*
1197: {
1198: if (GET_CODE (operands[1]) == CONST_INT
1199: && (INTVAL (operands[1]) & 0xffffff00) == 0)
1200: return \"bicb %1,%0\";
1201: return \"bicw %1,%0\";
1202: }")
1203:
1204: (define_insn "andcbqi3"
1205: [(set (match_operand:QI 0 "general_operand" "=g")
1206: (and:QI (match_operand:QI 1 "general_operand" "%0")
1207: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
1208: ""
1209: "bicb %2,%0")
1210:
1211: (define_insn ""
1212: [(set (match_operand:QI 0 "general_operand" "=g")
1213: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1214: (match_operand:QI 2 "general_operand" "0")))]
1215: ""
1216: "bicb %1,%0")
1217:
1218: ;;- Bit set instructions.
1219:
1220: (define_insn "iorsi3"
1221: [(set (match_operand:SI 0 "general_operand" "=g")
1222: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1223: (match_operand:SI 2 "general_operand" "rmn")))]
1224: ""
1225: "*
1226: {
1227: if (GET_CODE (operands[2]) == CONST_INT) {
1228: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1229: return \"orb %2,%0\";
1230: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1231: return \"orw %2,%0\";
1232: }
1233: return \"ord %2,%0\";
1234: }")
1235:
1236: (define_insn "iorhi3"
1237: [(set (match_operand:HI 0 "general_operand" "=g")
1238: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1239: (match_operand:HI 2 "general_operand" "g")))]
1240: ""
1241: "*
1242: {
1243: if (GET_CODE(operands[2]) == CONST_INT &&
1244: (INTVAL(operands[2]) & 0xffffff00) == 0)
1245: return \"orb %2,%0\";
1246: return \"orw %2,%0\";
1247: }")
1248:
1249: (define_insn "iorqi3"
1250: [(set (match_operand:QI 0 "general_operand" "=g")
1251: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1252: (match_operand:QI 2 "general_operand" "g")))]
1253: ""
1254: "orb %2,%0")
1255:
1256: ;;- xor instructions.
1257:
1258: (define_insn "xorsi3"
1259: [(set (match_operand:SI 0 "general_operand" "=g")
1260: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1261: (match_operand:SI 2 "general_operand" "rmn")))]
1262: ""
1263: "*
1264: {
1265: if (GET_CODE (operands[2]) == CONST_INT) {
1266: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1267: return \"xorb %2,%0\";
1268: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1269: return \"xorw %2,%0\";
1270: }
1271: return \"xord %2,%0\";
1272: }")
1273:
1274: (define_insn "xorhi3"
1275: [(set (match_operand:HI 0 "general_operand" "=g")
1276: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1277: (match_operand:HI 2 "general_operand" "g")))]
1278: ""
1279: "*
1280: {
1281: if (GET_CODE(operands[2]) == CONST_INT &&
1282: (INTVAL(operands[2]) & 0xffffff00) == 0)
1283: return \"xorb %2,%0\";
1284: return \"xorw %2,%0\";
1285: }")
1286:
1287: (define_insn "xorqi3"
1288: [(set (match_operand:QI 0 "general_operand" "=g")
1289: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1290: (match_operand:QI 2 "general_operand" "g")))]
1291: ""
1292: "xorb %2,%0")
1293:
1294: (define_insn "negdf2"
1295: [(set (match_operand:DF 0 "general_operand" "=fm<")
1296: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1297: "TARGET_32081"
1298: "negl %1,%0")
1299:
1300: (define_insn "negsf2"
1301: [(set (match_operand:SF 0 "general_operand" "=fm<")
1302: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1303: "TARGET_32081"
1304: "negf %1,%0")
1305:
1306: (define_insn "negsi2"
1307: [(set (match_operand:SI 0 "general_operand" "=g<")
1308: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1309: ""
1310: "negd %1,%0")
1311:
1312: (define_insn "neghi2"
1313: [(set (match_operand:HI 0 "general_operand" "=g<")
1314: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1315: ""
1316: "negw %1,%0")
1317:
1318: (define_insn "negqi2"
1319: [(set (match_operand:QI 0 "general_operand" "=g<")
1320: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1321: ""
1322: "negb %1,%0")
1323:
1324: (define_insn "one_cmplsi2"
1325: [(set (match_operand:SI 0 "general_operand" "=g<")
1326: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1327: ""
1328: "comd %1,%0")
1329:
1330: (define_insn "one_cmplhi2"
1331: [(set (match_operand:HI 0 "general_operand" "=g<")
1332: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1333: ""
1334: "comw %1,%0")
1335:
1336: (define_insn "one_cmplqi2"
1337: [(set (match_operand:QI 0 "general_operand" "=g<")
1338: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1339: ""
1340: "comb %1,%0")
1341:
1342: ;; arithmetic left and right shift operations
1343:
1344: (define_insn "ashlsi3"
1345: [(set (match_operand:SI 0 "general_operand" "=g,g")
1346: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1347: (match_operand:SI 2 "general_operand" "I,rmn")))]
1348: ""
1.1.1.2 root 1349: "* output_shift_insn (operands);")
1.1 root 1350:
1351: (define_insn ""
1352: [(set (match_operand:SI 0 "general_operand" "=g")
1353: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1354: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1355: (const_int 31))))]
1356: ""
1357: "ashd %2,%0")
1358:
1359: (define_insn "ashlhi3"
1360: [(set (match_operand:HI 0 "general_operand" "=g")
1361: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1362: (match_operand:SI 2 "general_operand" "rmn")))]
1363: ""
1364: "*
1365: { if (GET_CODE (operands[2]) == CONST_INT)
1366: if (INTVAL (operands[2]) == 1)
1367: return \"addw %1,%0\";
1368: else if (INTVAL (operands[2]) == 2)
1369: return \"addw %1,%0\;addw %0,%0\";
1370: return \"ashw %2,%0\";
1371: }")
1372:
1373: (define_insn "ashlqi3"
1374: [(set (match_operand:QI 0 "general_operand" "=g")
1375: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1376: (match_operand:SI 2 "general_operand" "rmn")))]
1377: ""
1378: "*
1379: { if (GET_CODE (operands[2]) == CONST_INT)
1380: if (INTVAL (operands[2]) == 1)
1381: return \"addb %1,%0\";
1382: else if (INTVAL (operands[2]) == 2)
1383: return \"addb %1,%0\;addb %0,%0\";
1384: return \"ashb %2,%0\";
1385: }")
1386:
1.1.1.6 root 1387: ;; Arithmetic right shift on the 32k works by negating the shift count.
1388: (define_expand "ashrsi3"
1389: [(set (match_operand:SI 0 "general_operand" "=g")
1390: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1391: (match_operand:SI 2 "general_operand" "g")))]
1392: ""
1393: "
1394: {
1.1.1.7 root 1395: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1396: }")
1397:
1398: (define_expand "ashrhi3"
1399: [(set (match_operand:HI 0 "general_operand" "=g")
1400: (ashift:HI (match_operand:HI 1 "general_operand" "g")
1401: (match_operand:SI 2 "general_operand" "g")))]
1402: ""
1403: "
1404: {
1.1.1.7 root 1405: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1406: }")
1407:
1408: (define_expand "ashrqi3"
1409: [(set (match_operand:QI 0 "general_operand" "=g")
1410: (ashift:QI (match_operand:QI 1 "general_operand" "g")
1411: (match_operand:SI 2 "general_operand" "g")))]
1412: ""
1413: "
1414: {
1.1.1.7 root 1415: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1416: }")
1417:
1.1 root 1418: ;; logical shift instructions
1419:
1420: (define_insn "lshlsi3"
1421: [(set (match_operand:SI 0 "general_operand" "=g")
1422: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1423: (match_operand:SI 2 "general_operand" "rmn")))]
1424: ""
1425: "lshd %2,%0")
1426:
1427: (define_insn ""
1428: [(set (match_operand:SI 0 "general_operand" "=g")
1429: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1430: (and:SI (match_operand:SI 2 "general_operand" "rmn")
1431: (const_int 31))))]
1432: ""
1433: "lshd %2,%0")
1434:
1435: (define_insn "lshlhi3"
1436: [(set (match_operand:HI 0 "general_operand" "=g")
1437: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1438: (match_operand:SI 2 "general_operand" "rmn")))]
1439: ""
1440: "lshw %2,%0")
1441:
1442: (define_insn "lshlqi3"
1443: [(set (match_operand:QI 0 "general_operand" "=g")
1444: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1445: (match_operand:SI 2 "general_operand" "rmn")))]
1446: ""
1447: "lshb %2,%0")
1448:
1.1.1.6 root 1449: ;; Logical right shift on the 32k works by negating the shift count.
1450: (define_expand "lshrsi3"
1451: [(set (match_operand:SI 0 "general_operand" "=g")
1452: (lshift:SI (match_operand:SI 1 "general_operand" "g")
1453: (match_operand:SI 2 "general_operand" "g")))]
1454: ""
1455: "
1456: {
1.1.1.7 root 1457: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1458: }")
1459:
1460: (define_expand "lshrhi3"
1461: [(set (match_operand:HI 0 "general_operand" "=g")
1462: (lshift:HI (match_operand:HI 1 "general_operand" "g")
1463: (match_operand:SI 2 "general_operand" "g")))]
1464: ""
1465: "
1466: {
1.1.1.7 root 1467: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1468: }")
1469:
1470: (define_expand "lshrqi3"
1471: [(set (match_operand:QI 0 "general_operand" "=g")
1472: (lshift:QI (match_operand:QI 1 "general_operand" "g")
1473: (match_operand:SI 2 "general_operand" "g")))]
1474: ""
1475: "
1476: {
1.1.1.7 root 1477: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1478: }")
1479:
1.1 root 1480: ;; Rotate instructions
1481:
1482: (define_insn "rotlsi3"
1483: [(set (match_operand:SI 0 "general_operand" "=g")
1484: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1485: (match_operand:SI 2 "general_operand" "rmn")))]
1486: ""
1487: "rotd %2,%0")
1488:
1489: (define_insn "rotlhi3"
1490: [(set (match_operand:HI 0 "general_operand" "=g")
1491: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1492: (match_operand:SI 2 "general_operand" "rmn")))]
1493: ""
1494: "rotw %2,%0")
1495:
1496: (define_insn "rotlqi3"
1497: [(set (match_operand:QI 0 "general_operand" "=g")
1498: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1499: (match_operand:SI 2 "general_operand" "rmn")))]
1500: ""
1501: "rotb %2,%0")
1.1.1.6 root 1502:
1503: ;; Right rotate on the 32k works by negating the shift count.
1504: (define_expand "rotrsi3"
1505: [(set (match_operand:SI 0 "general_operand" "=g")
1506: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1507: (match_operand:SI 2 "general_operand" "g")))]
1508: ""
1509: "
1510: {
1.1.1.7 root 1511: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1512: }")
1513:
1514: (define_expand "rotrhi3"
1515: [(set (match_operand:HI 0 "general_operand" "=g")
1516: (rotate:HI (match_operand:HI 1 "general_operand" "g")
1517: (match_operand:SI 2 "general_operand" "g")))]
1518: ""
1519: "
1520: {
1.1.1.7 root 1521: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1522: }")
1523:
1524: (define_expand "rotrqi3"
1525: [(set (match_operand:QI 0 "general_operand" "=g")
1526: (rotate:QI (match_operand:QI 1 "general_operand" "g")
1527: (match_operand:SI 2 "general_operand" "g")))]
1528: ""
1529: "
1530: {
1.1.1.7 root 1531: operands[2] = negate_rtx (SImode, operands[2]);
1.1.1.6 root 1532: }")
1.1 root 1533:
1534: ;;- load or push effective address
1535: ;; These come after the move, add, and multiply patterns
1536: ;; because we don't want pushl $1 turned into pushad 1.
1537:
1538: (define_insn ""
1539: [(set (match_operand:SI 0 "general_operand" "=g<")
1540: (match_operand:QI 1 "address_operand" "p"))]
1541: ""
1.1.1.2 root 1542: "*
1543: {
1544: if (REG_P (operands[0])
1545: && GET_CODE (operands[1]) == MULT
1546: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1547: && (INTVAL (XEXP (operands[1], 1)) == 2
1548: || INTVAL (XEXP (operands[1], 1)) == 4))
1549: {
1550: rtx xoperands[3];
1551: xoperands[0] = operands[0];
1552: xoperands[1] = XEXP (operands[1], 0);
1553: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1554: return output_shift_insn (xoperands);
1555: }
1556: return \"addr %a1,%0\";
1557: }")
1.1 root 1558:
1559: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1560: ;;; but slower then using power-of-2 shifts if we can use them
1561: ;
1562: ;(define_insn ""
1563: ; [(set (match_operand:SI 0 "register_operand" "=r")
1564: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1565: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1566: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1567: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1568: ; "indexd %0,%3,%1")
1569: ;
1570: ;(define_insn ""
1571: ; [(set (match_operand:SI 0 "register_operand" "=r")
1572: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1573: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1574: ; (match_operand:SI 3 "general_operand" "rmn")))]
1575: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1576: ; "indexd %0,%2,%3")
1577:
1578: ;; Set, Clear, and Invert bit
1579:
1580: (define_insn ""
1581: [(set (match_operand:SI 0 "general_operand" "=g")
1582: (ior:SI
1583: (ashift:SI (const_int 1)
1584: (match_operand:SI 1 "general_operand" "rmn"))
1585: (match_dup 0)))]
1586: ""
1587: "sbitd %1,%0")
1588:
1589: (define_insn ""
1590: [(set (match_operand:SI 0 "general_operand" "=g")
1591: (ior:SI
1592: (match_dup 0)
1593: (ashift:SI (const_int 1)
1594: (match_operand:SI 1 "general_operand" "rmn"))))]
1595: ""
1596: "sbitd %1,%0")
1597:
1598: (define_insn ""
1599: [(set (match_operand:QI 0 "general_operand" "=g")
1600: (ior:QI
1601: (subreg:QI
1602: (ashift:SI (const_int 1)
1603: (match_operand:QI 1 "general_operand" "rmn")) 0)
1604: (match_dup 0)))]
1605: ""
1606: "sbitb %1,%0")
1607:
1608: (define_insn ""
1609: [(set (match_operand:QI 0 "general_operand" "=g")
1610: (ior:QI
1611: (match_dup 0)
1612: (subreg:QI
1613: (ashift:SI (const_int 1)
1614: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1615: ""
1616: "sbitb %1,%0")
1617:
1618: (define_insn ""
1619: [(set (match_operand:SI 0 "general_operand" "=g")
1620: (and:SI
1621: (not:SI
1622: (ashift:SI (const_int 1)
1623: (match_operand:SI 1 "general_operand" "rmn")))
1624: (match_dup 0)))]
1625: ""
1626: "cbitd %1,%0")
1627:
1628: (define_insn ""
1629: [(set (match_operand:SI 0 "general_operand" "=g")
1630: (and:SI
1631: (match_dup 0)
1632: (not:SI
1633: (ashift:SI (const_int 1)
1634: (match_operand:SI 1 "general_operand" "rmn")))))]
1635: ""
1636: "cbitd %1,%0")
1637:
1638: (define_insn ""
1639: [(set (match_operand:QI 0 "general_operand" "=g")
1640: (and:QI
1641: (subreg:QI
1642: (not:SI
1643: (ashift:SI (const_int 1)
1644: (match_operand:QI 1 "general_operand" "rmn"))) 0)
1645: (match_dup 0)))]
1646: ""
1647: "cbitb %1,%0")
1648:
1649: (define_insn ""
1650: [(set (match_operand:QI 0 "general_operand" "=g")
1651: (and:QI
1652: (match_dup 0)
1653: (subreg:QI
1654: (not:SI
1655: (ashift:SI (const_int 1)
1656: (match_operand:QI 1 "general_operand" "rmn"))) 0)))]
1657: ""
1658: "cbitb %1,%0")
1659:
1660: (define_insn ""
1661: [(set (match_operand:SI 0 "general_operand" "=g")
1662: (xor:SI
1663: (ashift:SI (const_int 1)
1664: (match_operand:SI 1 "general_operand" "rmn"))
1665: (match_dup 0)))]
1666: ""
1667: "ibitd %1,%0")
1668:
1669: (define_insn ""
1670: [(set (match_operand:SI 0 "general_operand" "=g")
1671: (xor:SI
1672: (match_dup 0)
1673: (ashift:SI (const_int 1)
1674: (match_operand:SI 1 "general_operand" "rmn"))))]
1675: ""
1676: "ibitd %1,%0")
1677:
1678: (define_insn ""
1679: [(set (match_operand:QI 0 "general_operand" "=g")
1680: (xor:QI
1681: (subreg:QI
1682: (ashift:SI (const_int 1)
1683: (match_operand:QI 1 "general_operand" "rmn")) 0)
1684: (match_dup 0)))]
1685: ""
1686: "ibitb %1,%0")
1687:
1688: (define_insn ""
1689: [(set (match_operand:QI 0 "general_operand" "=g")
1690: (xor:QI
1691: (match_dup 0)
1692: (subreg:QI
1693: (ashift:SI (const_int 1)
1694: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1695: ""
1696: "ibitb %1,%0")
1697:
1698: ;; Recognize jbs and jbc instructions.
1699:
1700: (define_insn ""
1701: [(set (cc0)
1.1.1.7 root 1702: (zero_extract (match_operand:SI 0 "general_operand" "rm")
1.1 root 1703: (const_int 1)
1704: (match_operand:SI 1 "general_operand" "rmn")))]
1705: ""
1706: "*
1707: { cc_status.flags = CC_Z_IN_F;
1708: return \"tbitd %1,%0\";
1709: }")
1710:
1711: (define_insn ""
1712: [(set (cc0)
1.1.1.7 root 1713: (minus (zero_extract (match_operand:SI 0 "general_operand" "rm")
1.1 root 1714: (const_int 1)
1715: (match_operand:SI 1 "general_operand" "rmn"))
1716: (const_int 1)))]
1717: ""
1718: "*
1719: { cc_status.flags = CC_Z_IN_NOT_F;
1720: return \"tbitd %1,%0\";
1721: }")
1722:
1723: (define_insn ""
1724: [(set (cc0)
1725: (zero_extract (match_operand:HI 0 "general_operand" "g")
1726: (const_int 1)
1727: (match_operand:HI 1 "general_operand" "g")))]
1728: ""
1729: "*
1730: { cc_status.flags = CC_Z_IN_F;
1731: return \"tbitw %1,%0\";
1732: }")
1733:
1734: (define_insn ""
1735: [(set (cc0)
1736: (minus (zero_extract (match_operand:HI 0 "general_operand" "g")
1737: (const_int 1)
1738: (match_operand:HI 1 "general_operand" "rmn"))
1739: (const_int 1)))]
1740: ""
1741: "*
1742: { cc_status.flags = CC_Z_IN_NOT_F;
1743: return \"tbitw %1,%0\";
1744: }")
1745:
1746: (define_insn ""
1747: [(set (cc0)
1748: (zero_extract (match_operand:QI 0 "general_operand" "g")
1749: (const_int 1)
1750: (match_operand:QI 1 "general_operand" "g")))]
1751: ""
1752: "*
1753: { cc_status.flags = CC_Z_IN_F;
1754: return \"tbitb %1,%0\";
1755: }")
1756:
1757: (define_insn ""
1758: [(set (cc0)
1759: (minus (zero_extract:SI (match_operand:QI 0 "general_operand" "g")
1760: (const_int 1)
1761: (match_operand:QI 1 "general_operand" "rmn"))
1762: (const_int 1)))]
1763: ""
1764: "*
1765: { cc_status.flags = CC_Z_IN_NOT_F;
1766: return \"tbitb %1,%0\";
1767: }")
1768:
1769: (define_insn ""
1770: [(set (cc0)
1.1.1.7 root 1771: (and:SI (match_operand:SI 0 "general_operand" "rm")
1.1 root 1772: (match_operand:SI 1 "immediate_operand" "i")))]
1773: "GET_CODE (operands[1]) == CONST_INT
1774: && exact_log2 (INTVAL (operands[1])) >= 0"
1775: "*
1776: {
1777: operands[1]
1778: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1779: cc_status.flags = CC_Z_IN_F;
1780: return \"tbitd %1,%0\";
1781: }")
1782:
1783: ;; extract(base, width, offset)
1784: ;; Signed bitfield extraction is not supported in hardware on the
1785: ;; NS 32032. It is therefore better to let GCC figure out a
1786: ;; good strategy for generating the proper instruction sequence
1787: ;; and represent it as rtl.
1788:
1.1.1.2 root 1789: ;; Optimize the case of extracting a byte or word from a register.
1790: ;; Otherwise we must load a register with the offset of the
1791: ;; chunk we want, and perform an extract insn (each of which
1792: ;; is very expensive). Since we use the stack to do our bit-twiddling
1793: ;; we cannot use it for a destination. Perhaps things are fast
1794: ;; enough on the 32532 that such hacks are not needed.
1795:
1796: (define_insn ""
1797: [(set (match_operand:SI 0 "general_operand" "=ro")
1798: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1.1 root 1799: (match_operand:SI 2 "const_int" "i")
1.1.1.2 root 1800: (match_operand:SI 3 "const_int" "i")))]
1801: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1802: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1803: "*
1804: {
1805: output_asm_insn (\"movd %1,tos\", operands);
1806: if (INTVAL (operands[2]) == 16)
1807: {
1808: if (INTVAL (operands[3]) == 8)
1809: output_asm_insn (\"movzwd 1(sp),%0\", operands);
1810: else
1811: output_asm_insn (\"movzwd 2(sp),%0\", operands);
1812: }
1813: else
1814: {
1815: if (INTVAL (operands[3]) == 8)
1816: output_asm_insn (\"movzbd 1(sp),%0\", operands);
1817: else if (INTVAL (operands[3]) == 16)
1818: output_asm_insn (\"movzbd 2(sp),%0\", operands);
1819: else
1820: output_asm_insn (\"movzbd 3(sp),%0\", operands);
1821: }
1.1.1.6 root 1822: #if defined(ns32532) || defined(ns32332)
1823: return \"cmpqd %$0,tos # adjsp -4\";
1824: #else
1.1.1.2 root 1825: return \"adjspb %$-4\";
1.1.1.6 root 1826: #endif
1.1.1.2 root 1827: }")
1828:
1829: (define_insn ""
1830: [(set (match_operand:SI 0 "general_operand" "=ro")
1831: (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
1832: (match_operand:SI 2 "const_int" "i")
1833: (match_operand:SI 3 "const_int" "i")))]
1834: "INTVAL (operands[2]) == 8 && INTVAL (operands[3]) == 8"
1835: "movw %1,tos\;movzbd 1(sp),%0\;adjspb %$-2")
1836:
1837: (define_insn "extzv"
1838: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1839: (zero_extract:SI (match_operand:SI 1 "general_operand" "rm,o")
1840: (match_operand:SI 2 "const_int" "i,i")
1841: (match_operand:SI 3 "general_operand" "rK,n")))]
1.1 root 1842: ""
1843: "*
1844: { if (GET_CODE (operands[3]) == CONST_INT)
1.1.1.2 root 1845: {
1846: if (INTVAL (operands[3]) >= 8)
1.1.1.7 root 1847: operands[1] = adj_offsetable_operand (operands[1],
1848: INTVAL (operands[3]) >> 3);
1.1.1.2 root 1849: return \"extsd %1,%0,%3,%2\";
1850: }
1.1 root 1851: else return \"extd %3,%1,%0,%2\";
1852: }")
1853:
1854: (define_insn ""
1.1.1.2 root 1855: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1856: (zero_extract:SI (match_operand:HI 1 "general_operand" "rm,o")
1857: (match_operand:SI 2 "const_int" "i,i")
1858: (match_operand:SI 3 "general_operand" "rK,n")))]
1.1 root 1859: ""
1860: "*
1861: { if (GET_CODE (operands[3]) == CONST_INT)
1.1.1.2 root 1862: {
1863: if (INTVAL (operands[3]) >= 8)
1.1.1.7 root 1864: operands[1] = adj_offsetable_operand (operands[1],
1865: INTVAL (operands[3]) >> 3);
1.1.1.2 root 1866: return \"extsd %1,%0,%3,%2\";
1867: }
1.1 root 1868: else return \"extd %3,%1,%0,%2\";
1869: }")
1870:
1871: (define_insn ""
1872: [(set (match_operand:SI 0 "general_operand" "=g<")
1873: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1874: (match_operand:SI 2 "const_int" "i")
1.1.1.2 root 1875: (match_operand:SI 3 "general_operand" "rn")))]
1.1 root 1876: ""
1877: "*
1878: { if (GET_CODE (operands[3]) == CONST_INT)
1879: return \"extsd %1,%0,%3,%2\";
1880: else return \"extd %3,%1,%0,%2\";
1881: }")
1882:
1883: (define_insn "insv"
1.1.1.4 root 1884: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g,o")
1.1.1.2 root 1885: (match_operand:SI 1 "const_int" "i,i")
1886: (match_operand:SI 2 "general_operand" "rK,n"))
1887: (match_operand:SI 3 "general_operand" "rm,rm"))]
1.1 root 1888: ""
1889: "*
1890: { if (GET_CODE (operands[2]) == CONST_INT)
1.1.1.2 root 1891: {
1.1.1.4 root 1892: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
1893: {
1894: operands[0] = adj_offsetable_operand (operands[0],
1895: INTVAL (operands[2]) / 8);
1896: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1897: }
1.1.1.2 root 1898: if (INTVAL (operands[1]) <= 8)
1899: return \"inssb %3,%0,%2,%1\";
1900: else if (INTVAL (operands[1]) <= 16)
1901: return \"inssw %3,%0,%2,%1\";
1902: else
1903: return \"inssd %3,%0,%2,%1\";
1904: }
1905: return \"insd %2,%3,%0,%1\";
1.1 root 1906: }")
1907:
1908: (define_insn ""
1.1.1.4 root 1909: [(set (zero_extract:SI (match_operand:HI 0 "general_operand" "+g,o")
1.1.1.2 root 1910: (match_operand:SI 1 "const_int" "i,i")
1911: (match_operand:SI 2 "general_operand" "rK,n"))
1912: (match_operand:SI 3 "general_operand" "rm,rm"))]
1.1 root 1913: ""
1914: "*
1915: { if (GET_CODE (operands[2]) == CONST_INT)
1.1.1.2 root 1916: {
1.1.1.4 root 1917: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
1918: {
1919: operands[0] = adj_offsetable_operand (operands[0],
1920: INTVAL (operands[2]) / 8);
1921: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1922: }
1.1.1.2 root 1923: if (INTVAL (operands[1]) <= 8)
1924: return \"inssb %3,%0,%2,%1\";
1925: else if (INTVAL (operands[1]) <= 16)
1926: return \"inssw %3,%0,%2,%1\";
1927: else
1928: return \"inssd %3,%0,%2,%1\";
1929: }
1930: return \"insd %2,%3,%0,%1\";
1.1 root 1931: }")
1932:
1933: (define_insn ""
1934: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g")
1935: (match_operand:SI 1 "const_int" "i")
1.1.1.2 root 1936: (match_operand:SI 2 "general_operand" "rn"))
1937: (match_operand:SI 3 "general_operand" "rm"))]
1.1 root 1938: ""
1939: "*
1940: { if (GET_CODE (operands[2]) == CONST_INT)
1941: if (INTVAL (operands[1]) <= 8)
1942: return \"inssb %3,%0,%2,%1\";
1943: else if (INTVAL (operands[1]) <= 16)
1944: return \"inssw %3,%0,%2,%1\";
1945: else
1946: return \"inssd %3,%0,%2,%1\";
1.1.1.2 root 1947: return \"insd %2,%3,%0,%1\";
1.1 root 1948: }")
1949:
1950:
1951: (define_insn "jump"
1952: [(set (pc)
1953: (label_ref (match_operand 0 "" "")))]
1954: ""
1955: "br %l0")
1956:
1957: (define_insn "beq"
1958: [(set (pc)
1959: (if_then_else (eq (cc0)
1960: (const_int 0))
1961: (label_ref (match_operand 0 "" ""))
1962: (pc)))]
1963: ""
1964: "*
1965: { if (cc_prev_status.flags & CC_Z_IN_F)
1966: return \"bfc %l0\";
1967: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1968: return \"bfs %l0\";
1969: else return \"beq %l0\";
1970: }")
1971:
1972: (define_insn "bne"
1973: [(set (pc)
1974: (if_then_else (ne (cc0)
1975: (const_int 0))
1976: (label_ref (match_operand 0 "" ""))
1977: (pc)))]
1978: ""
1979: "*
1980: { if (cc_prev_status.flags & CC_Z_IN_F)
1981: return \"bfs %l0\";
1982: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1983: return \"bfc %l0\";
1984: else return \"bne %l0\";
1985: }")
1986:
1987: (define_insn "bgt"
1988: [(set (pc)
1989: (if_then_else (gt (cc0)
1990: (const_int 0))
1991: (label_ref (match_operand 0 "" ""))
1992: (pc)))]
1993: ""
1994: "bgt %l0")
1995:
1996: (define_insn "bgtu"
1997: [(set (pc)
1998: (if_then_else (gtu (cc0)
1999: (const_int 0))
2000: (label_ref (match_operand 0 "" ""))
2001: (pc)))]
2002: ""
2003: "bhi %l0")
2004:
2005: (define_insn "blt"
2006: [(set (pc)
2007: (if_then_else (lt (cc0)
2008: (const_int 0))
2009: (label_ref (match_operand 0 "" ""))
2010: (pc)))]
2011: ""
2012: "blt %l0")
2013:
2014: (define_insn "bltu"
2015: [(set (pc)
2016: (if_then_else (ltu (cc0)
2017: (const_int 0))
2018: (label_ref (match_operand 0 "" ""))
2019: (pc)))]
2020: ""
2021: "blo %l0")
2022:
2023: (define_insn "bge"
2024: [(set (pc)
2025: (if_then_else (ge (cc0)
2026: (const_int 0))
2027: (label_ref (match_operand 0 "" ""))
2028: (pc)))]
2029: ""
2030: "bge %l0")
2031:
2032: (define_insn "bgeu"
2033: [(set (pc)
2034: (if_then_else (geu (cc0)
2035: (const_int 0))
2036: (label_ref (match_operand 0 "" ""))
2037: (pc)))]
2038: ""
2039: "bhs %l0")
2040:
2041: (define_insn "ble"
2042: [(set (pc)
2043: (if_then_else (le (cc0)
2044: (const_int 0))
2045: (label_ref (match_operand 0 "" ""))
2046: (pc)))]
2047: ""
2048: "ble %l0")
2049:
2050: (define_insn "bleu"
2051: [(set (pc)
2052: (if_then_else (leu (cc0)
2053: (const_int 0))
2054: (label_ref (match_operand 0 "" ""))
2055: (pc)))]
2056: ""
2057: "bls %l0")
2058:
2059: (define_insn ""
2060: [(set (pc)
2061: (if_then_else (eq (cc0)
2062: (const_int 0))
2063: (pc)
2064: (label_ref (match_operand 0 "" ""))))]
2065: ""
2066: "*
2067: { if (cc_prev_status.flags & CC_Z_IN_F)
2068: return \"bfs %l0\";
2069: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2070: return \"bfc %l0\";
2071: else return \"bne %l0\";
2072: }")
2073:
2074: (define_insn ""
2075: [(set (pc)
2076: (if_then_else (ne (cc0)
2077: (const_int 0))
2078: (pc)
2079: (label_ref (match_operand 0 "" ""))))]
2080: ""
2081: "*
2082: { if (cc_prev_status.flags & CC_Z_IN_F)
2083: return \"bfc %l0\";
2084: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2085: return \"bfs %l0\";
2086: else return \"beq %l0\";
2087: }")
2088:
2089: (define_insn ""
2090: [(set (pc)
2091: (if_then_else (gt (cc0)
2092: (const_int 0))
2093: (pc)
2094: (label_ref (match_operand 0 "" ""))))]
2095: ""
2096: "ble %l0")
2097:
2098: (define_insn ""
2099: [(set (pc)
2100: (if_then_else (gtu (cc0)
2101: (const_int 0))
2102: (pc)
2103: (label_ref (match_operand 0 "" ""))))]
2104: ""
2105: "bls %l0")
2106:
2107: (define_insn ""
2108: [(set (pc)
2109: (if_then_else (lt (cc0)
2110: (const_int 0))
2111: (pc)
2112: (label_ref (match_operand 0 "" ""))))]
2113: ""
2114: "bge %l0")
2115:
2116: (define_insn ""
2117: [(set (pc)
2118: (if_then_else (ltu (cc0)
2119: (const_int 0))
2120: (pc)
2121: (label_ref (match_operand 0 "" ""))))]
2122: ""
2123: "bhs %l0")
2124:
2125: (define_insn ""
2126: [(set (pc)
2127: (if_then_else (ge (cc0)
2128: (const_int 0))
2129: (pc)
2130: (label_ref (match_operand 0 "" ""))))]
2131: ""
2132: "blt %l0")
2133:
2134: (define_insn ""
2135: [(set (pc)
2136: (if_then_else (geu (cc0)
2137: (const_int 0))
2138: (pc)
2139: (label_ref (match_operand 0 "" ""))))]
2140: ""
2141: "blo %l0")
2142:
2143: (define_insn ""
2144: [(set (pc)
2145: (if_then_else (le (cc0)
2146: (const_int 0))
2147: (pc)
2148: (label_ref (match_operand 0 "" ""))))]
2149: ""
2150: "bgt %l0")
2151:
2152: (define_insn ""
2153: [(set (pc)
2154: (if_then_else (leu (cc0)
2155: (const_int 0))
2156: (pc)
2157: (label_ref (match_operand 0 "" ""))))]
2158: ""
2159: "bhi %l0")
2160:
2161: ;; Subtract-and-jump and Add-and-jump insns.
2162: ;; These can actually be used for adding numbers in the range -8 to 7
2163:
2164: (define_insn ""
2165: [(set (pc)
2166: (if_then_else
2167: (ne (minus:SI (match_operand:SI 0 "general_operand" "+g")
2168: (match_operand:SI 1 "general_operand" "i"))
2169: (const_int 0))
2170: (label_ref (match_operand 2 "" ""))
2171: (pc)))
2172: (set (match_dup 0)
2173: (minus:SI (match_dup 0)
2174: (match_dup 1)))]
2175: "GET_CODE (operands[1]) == CONST_INT
2176: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2177: "acbd %$%n1,%0,%l2")
2178:
2179: (define_insn ""
2180: [(set (pc)
2181: (if_then_else
2182: (ne (plus:SI (match_operand:SI 0 "general_operand" "+g")
2183: (match_operand:SI 1 "general_operand" "i"))
2184: (const_int 0))
2185: (label_ref (match_operand 2 "" ""))
2186: (pc)))
2187: (set (match_dup 0)
2188: (plus:SI (match_dup 0)
2189: (match_dup 1)))]
2190: "GET_CODE (operands[1]) == CONST_INT
2191: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2192: "acbd %1,%0,%l2")
2193:
2194: ;; Reversed
2195:
2196: (define_insn ""
2197: [(set (pc)
2198: (if_then_else
2199: (eq (minus:SI (match_operand:SI 0 "general_operand" "+g")
2200: (match_operand:SI 1 "general_operand" "i"))
2201: (const_int 0))
2202: (pc)
2203: (label_ref (match_operand 2 "" ""))))
2204: (set (match_dup 0)
2205: (minus:SI (match_dup 0)
2206: (match_dup 1)))]
2207: "GET_CODE (operands[1]) == CONST_INT
2208: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2209: "acbd %$%n1,%0,%l2")
2210:
2211: (define_insn ""
2212: [(set (pc)
2213: (if_then_else
2214: (eq (plus:SI (match_operand:SI 0 "general_operand" "+g")
2215: (match_operand:SI 1 "general_operand" "i"))
2216: (const_int 0))
2217: (pc)
2218: (label_ref (match_operand 2 "" ""))))
2219: (set (match_dup 0)
2220: (plus:SI (match_dup 0)
2221: (match_dup 1)))]
2222: "GET_CODE (operands[1]) == CONST_INT
2223: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2224: "acbd %1,%0,%l2")
2225:
2226: (define_insn "call"
2227: [(call (match_operand:QI 0 "general_operand" "g")
2228: (match_operand:QI 1 "general_operand" "g"))]
2229: ""
2230: "*
2231: {
2232: if (GET_CODE (operands[0]) == MEM)
2233: {
2234: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
1.1.1.4 root 2235: #ifdef GNX_V3
2236: return \"bsr %0\";
2237: #else
1.1.1.2 root 2238: return \"bsr %?%a0\";
1.1.1.4 root 2239: #endif
1.1 root 2240: if (GET_CODE (XEXP (operands[0], 0)) == REG)
1.1.1.4 root 2241: #ifdef GNX_V3
2242: return \"jsr %0\";
2243: #else
1.1 root 2244: return \"jsr %a0\";
1.1.1.4 root 2245: #endif
1.1 root 2246: }
2247: return \"jsr %0\";
2248: }")
2249:
2250: (define_insn "call_value"
2251: [(set (match_operand 0 "" "fg")
2252: (call (match_operand:QI 1 "general_operand" "g")
2253: (match_operand:QI 2 "general_operand" "g")))]
2254: ""
2255: "*
2256: {
2257: if (GET_CODE (operands[1]) == MEM)
2258: {
2259: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
1.1.1.4 root 2260: #ifdef GNX_V3
2261: return \"bsr %1\";
2262: #else
1.1.1.2 root 2263: return \"bsr %?%a1\";
1.1.1.4 root 2264: #endif
1.1 root 2265: if (GET_CODE (XEXP (operands[1], 0)) == REG)
1.1.1.4 root 2266: #ifdef GNX_V3
2267: return \"jsr %1\";
2268: #else
1.1 root 2269: return \"jsr %a1\";
1.1.1.4 root 2270: #endif
1.1 root 2271: }
2272: return \"jsr %1\";
2273: }")
2274:
2275: (define_insn "return"
2276: [(return)]
1.1.1.5 root 2277: "0"
1.1 root 2278: "ret 0")
2279:
2280: (define_insn "abssf2"
2281: [(set (match_operand:SF 0 "general_operand" "=fm<")
2282: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2283: "TARGET_32081"
2284: "absf %1,%0")
2285:
2286: (define_insn "absdf2"
2287: [(set (match_operand:DF 0 "general_operand" "=fm<")
2288: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2289: "TARGET_32081"
2290: "absl %1,%0")
2291:
2292: (define_insn "abssi2"
2293: [(set (match_operand:SI 0 "general_operand" "=g<")
2294: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2295: ""
2296: "absd %1,%0")
2297:
2298: (define_insn "abshi2"
2299: [(set (match_operand:HI 0 "general_operand" "=g<")
2300: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2301: ""
2302: "absw %1,%0")
2303:
2304: (define_insn "absqi2"
2305: [(set (match_operand:QI 0 "general_operand" "=g<")
2306: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2307: ""
2308: "absb %1,%0")
2309:
2310: ;;(define_insn "tablejump"
2311: ;; [(set (pc)
2312: ;; (plus:SI (match_operand:SI 0 "general_operand" "g")
2313: ;; (pc)))]
2314: ;; ""
2315: ;; "cased %0")
2316:
2317: (define_insn "tablejump"
2318: [(set (pc)
2319: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g")))
2320: (use (label_ref (match_operand 1 "" "")))]
2321: ""
2322: "*
2323: {
2324: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2325: CODE_LABEL_NUMBER (operands[1]));
2326: return \"casew %0\";
2327: }")
2328:
2329: ;;(define_insn ""
2330: ;; [(set (pc)
2331: ;; (plus:SI (match_operand:QI 0 "general_operand" "g")
2332: ;; (pc)))]
2333: ;; ""
2334: ;; "caseb %0")
2335:
2336: ;; Scondi instructions
2337: (define_insn "seq"
2338: [(set (match_operand:SI 0 "general_operand" "=g<")
2339: (eq (cc0) (const_int 0)))]
2340: ""
2341: "*
2342: { if (cc_prev_status.flags & CC_Z_IN_F)
2343: return \"sfcd %0\";
2344: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2345: return \"sfsd %0\";
2346: else return \"seqd %0\";
2347: }")
2348:
2349: (define_insn ""
2350: [(set (match_operand:HI 0 "general_operand" "=g<")
2351: (eq (cc0) (const_int 0)))]
2352: ""
2353: "*
2354: { if (cc_prev_status.flags & CC_Z_IN_F)
2355: return \"sfcw %0\";
2356: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2357: return \"sfsw %0\";
2358: else return \"seqw %0\";
2359: }")
2360:
2361: (define_insn ""
2362: [(set (match_operand:QI 0 "general_operand" "=g<")
2363: (eq (cc0) (const_int 0)))]
2364: ""
2365: "*
2366: { if (cc_prev_status.flags & CC_Z_IN_F)
2367: return \"sfcb %0\";
2368: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2369: return \"sfsb %0\";
2370: else return \"seqb %0\";
2371: }")
2372:
2373: (define_insn "sne"
2374: [(set (match_operand:SI 0 "general_operand" "=g<")
2375: (ne (cc0) (const_int 0)))]
2376: ""
2377: "*
2378: { if (cc_prev_status.flags & CC_Z_IN_F)
2379: return \"sfsd %0\";
2380: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2381: return \"sfcd %0\";
2382: else return \"sned %0\";
2383: }")
2384:
2385: (define_insn ""
2386: [(set (match_operand:HI 0 "general_operand" "=g<")
2387: (ne (cc0) (const_int 0)))]
2388: ""
2389: "*
2390: { if (cc_prev_status.flags & CC_Z_IN_F)
2391: return \"sfsw %0\";
2392: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2393: return \"sfcw %0\";
2394: else return \"snew %0\";
2395: }")
2396:
2397: (define_insn ""
2398: [(set (match_operand:QI 0 "general_operand" "=g<")
2399: (ne (cc0) (const_int 0)))]
2400: ""
2401: "*
2402: { if (cc_prev_status.flags & CC_Z_IN_F)
2403: return \"sfsb %0\";
2404: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2405: return \"sfcb %0\";
2406: else return \"sneb %0\";
2407: }")
2408:
2409: (define_insn "sgt"
2410: [(set (match_operand:SI 0 "general_operand" "=g<")
2411: (gt (cc0) (const_int 0)))]
2412: ""
2413: "sgtd %0")
2414:
2415: (define_insn ""
2416: [(set (match_operand:HI 0 "general_operand" "=g<")
2417: (gt (cc0) (const_int 0)))]
2418: ""
2419: "sgtw %0")
2420:
2421: (define_insn ""
2422: [(set (match_operand:QI 0 "general_operand" "=g<")
2423: (gt (cc0) (const_int 0)))]
2424: ""
2425: "sgtb %0")
2426:
2427: (define_insn "sgtu"
2428: [(set (match_operand:SI 0 "general_operand" "=g<")
2429: (gtu (cc0) (const_int 0)))]
2430: ""
2431: "shid %0")
2432:
2433: (define_insn ""
2434: [(set (match_operand:HI 0 "general_operand" "=g<")
2435: (gtu (cc0) (const_int 0)))]
2436: ""
2437: "shiw %0")
2438:
2439: (define_insn ""
2440: [(set (match_operand:QI 0 "general_operand" "=g<")
2441: (gtu (cc0) (const_int 0)))]
2442: ""
2443: "shib %0")
2444:
2445: (define_insn "slt"
2446: [(set (match_operand:SI 0 "general_operand" "=g<")
2447: (lt (cc0) (const_int 0)))]
2448: ""
2449: "sltd %0")
2450:
2451: (define_insn ""
2452: [(set (match_operand:HI 0 "general_operand" "=g<")
2453: (lt (cc0) (const_int 0)))]
2454: ""
2455: "sltw %0")
2456:
2457: (define_insn ""
2458: [(set (match_operand:QI 0 "general_operand" "=g<")
2459: (lt (cc0) (const_int 0)))]
2460: ""
2461: "sltb %0")
2462:
2463: (define_insn "sltu"
2464: [(set (match_operand:SI 0 "general_operand" "=g<")
2465: (ltu (cc0) (const_int 0)))]
2466: ""
2467: "slod %0")
2468:
2469: (define_insn ""
2470: [(set (match_operand:HI 0 "general_operand" "=g<")
2471: (ltu (cc0) (const_int 0)))]
2472: ""
2473: "slow %0")
2474:
2475: (define_insn ""
2476: [(set (match_operand:QI 0 "general_operand" "=g<")
2477: (ltu (cc0) (const_int 0)))]
2478: ""
2479: "slob %0")
2480:
2481: (define_insn "sge"
2482: [(set (match_operand:SI 0 "general_operand" "=g<")
2483: (ge (cc0) (const_int 0)))]
2484: ""
2485: "sged %0")
2486:
2487: (define_insn ""
2488: [(set (match_operand:HI 0 "general_operand" "=g<")
2489: (ge (cc0) (const_int 0)))]
2490: ""
2491: "sgew %0")
2492:
2493: (define_insn ""
2494: [(set (match_operand:QI 0 "general_operand" "=g<")
2495: (ge (cc0) (const_int 0)))]
2496: ""
2497: "sgeb %0")
2498:
2499: (define_insn "sgeu"
2500: [(set (match_operand:SI 0 "general_operand" "=g<")
2501: (geu (cc0) (const_int 0)))]
2502: ""
2503: "shsd %0")
2504:
2505: (define_insn ""
2506: [(set (match_operand:HI 0 "general_operand" "=g<")
2507: (geu (cc0) (const_int 0)))]
2508: ""
2509: "shsw %0")
2510:
2511: (define_insn ""
2512: [(set (match_operand:QI 0 "general_operand" "=g<")
2513: (geu (cc0) (const_int 0)))]
2514: ""
2515: "shsb %0")
2516:
2517: (define_insn "sle"
2518: [(set (match_operand:SI 0 "general_operand" "=g<")
2519: (le (cc0) (const_int 0)))]
2520: ""
2521: "sled %0")
2522:
2523: (define_insn ""
2524: [(set (match_operand:HI 0 "general_operand" "=g<")
2525: (le (cc0) (const_int 0)))]
2526: ""
2527: "slew %0")
2528:
2529: (define_insn ""
2530: [(set (match_operand:QI 0 "general_operand" "=g<")
2531: (le (cc0) (const_int 0)))]
2532: ""
2533: "sleb %0")
2534:
2535: (define_insn "sleu"
2536: [(set (match_operand:SI 0 "general_operand" "=g<")
2537: (leu (cc0) (const_int 0)))]
2538: ""
2539: "slsd %0")
2540:
2541: (define_insn ""
2542: [(set (match_operand:HI 0 "general_operand" "=g<")
2543: (leu (cc0) (const_int 0)))]
2544: ""
2545: "slsw %0")
2546:
2547: (define_insn ""
2548: [(set (match_operand:QI 0 "general_operand" "=g<")
2549: (leu (cc0) (const_int 0)))]
2550: ""
2551: "slsb %0")
2552:
2553: ;;- Local variables:
2554: ;;- mode:emacs-lisp
2555: ;;- comment-start: ";;- "
2556: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2557: ;;- eval: (modify-syntax-entry ?[ "(]")
2558: ;;- eval: (modify-syntax-entry ?] ")[")
2559: ;;- eval: (modify-syntax-entry ?{ "(}")
2560: ;;- eval: (modify-syntax-entry ?} "){")
2561: ;;- End:
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