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1.1 root 1: /* Subroutines for insn-output.c for Motorola 68000 family.
2: Copyright (C) 1987 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is distributed in the hope that it will be useful,
7: but WITHOUT ANY WARRANTY. No author or distributor
8: accepts responsibility to anyone for the consequences of using it
9: or for whether it serves any particular purpose or works at all,
10: unless he says so in writing. Refer to the GNU CC General Public
11: License for full details.
12:
13: Everyone is granted permission to copy, modify and redistribute
14: GNU CC, but only under the conditions described in the
15: GNU CC General Public License. A copy of this license is
16: supposed to have been given to you along with GNU CC so you
17: can know your rights and responsibilities. It should be in a
18: file named COPYING. Among other things, the copyright notice
19: and this notice must be preserved on all copies. */
20:
21:
22: /* Some output-actions in m68k.md need these. */
23: #include <stdio.h>
24: extern FILE *asm_out_file;
25:
1.1.1.2 ! root 26: /* Index into this array by (register number >> 3) to find the
! 27: smallest class which contains that register. */
! 28: enum reg_class regno_reg_class[]
! 29: = { DATA_REGS, ADDR_REGS, FP_REGS,
! 30: LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS };
! 31:
1.1 root 32: static rtx find_addr_reg ();
33:
34: char *
35: output_btst (operands, countop, dataop, insn, signpos)
36: rtx *operands;
37: rtx countop, dataop;
38: rtx insn;
39: int signpos;
40: {
41: operands[0] = countop;
42: operands[1] = dataop;
43: if (GET_CODE (countop) == CONST_INT)
44: {
45: register int count = INTVAL (countop);
46: if (count == signpos)
47: cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
48: else
49: cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
50:
51: if (count == 31
52: && next_insn_tests_no_inequality (insn))
53: return "tst%.l %1";
54: if (count == 15
55: && next_insn_tests_no_inequality (insn))
56: return "tst%.w %1";
57: if (count == 7
58: && next_insn_tests_no_inequality (insn))
59: return "tst%.b %1";
60:
61: cc_status.flags = CC_NOT_NEGATIVE;
62: }
63: return "btst %0,%1";
64: }
65:
66: /* Return the best assembler insn template
67: for moving operands[1] into operands[0] as a fullword. */
68:
69: static char *
70: singlemove_string (operands)
71: rtx *operands;
72: {
1.1.1.2 ! root 73: if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
! 74: return "fpmoves %1,%0";
1.1 root 75: if (operands[1] != const0_rtx)
76: return "move%.l %1,%0";
77: if (! ADDRESS_REG_P (operands[0]))
78: return "clr%.l %0";
79: return "sub%.l %0,%0";
80: }
81:
82: /* Output assembler code to perform a doubleword move insn
83: with operands OPERANDS. */
84:
85: char *
86: output_move_double (operands)
87: rtx *operands;
88: {
89: enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
90: rtx latehalf[2];
91: rtx addreg0 = 0, addreg1 = 0;
92:
93: /* First classify both operands. */
94:
95: if (REG_P (operands[0]))
96: optype0 = REGOP;
97: else if (offsetable_memref_p (operands[0]))
98: optype0 = OFFSOP;
99: else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
100: optype0 = POPOP;
101: else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
102: optype0 = PUSHOP;
103: else if (GET_CODE (operands[0]) == MEM)
104: optype0 = MEMOP;
105: else
106: optype0 = RNDOP;
107:
108: if (REG_P (operands[1]))
109: optype1 = REGOP;
110: else if (CONSTANT_P (operands[1])
111: || GET_CODE (operands[1]) == CONST_DOUBLE)
112: optype1 = CNSTOP;
113: else if (offsetable_memref_p (operands[1]))
114: optype1 = OFFSOP;
115: else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
116: optype1 = POPOP;
117: else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
118: optype1 = PUSHOP;
119: else if (GET_CODE (operands[1]) == MEM)
120: optype1 = MEMOP;
121: else
122: optype1 = RNDOP;
123:
124: /* Check for the cases that the operand constraints are not
125: supposed to allow to happen. Abort if we get one,
126: because generating code for these cases is painful. */
127:
128: if (optype0 == RNDOP || optype1 == RNDOP)
129: abort ();
130:
131: /* If one operand is decrementing and one is incrementing
132: decrement the former register explicitly
133: and change that operand into ordinary indexing. */
134:
135: if (optype0 == PUSHOP && optype1 == POPOP)
136: {
137: operands[0] = XEXP (XEXP (operands[0], 0), 0);
138: output_asm_insn ("subq%.l %#8,%0", operands);
139: operands[0] = gen_rtx (MEM, DImode, operands[0]);
140: optype0 = OFFSOP;
141: }
142: if (optype0 == POPOP && optype1 == PUSHOP)
143: {
144: operands[1] = XEXP (XEXP (operands[1], 0), 0);
145: output_asm_insn ("subq%.l %#8,%1", operands);
146: operands[1] = gen_rtx (MEM, DImode, operands[1]);
147: optype1 = OFFSOP;
148: }
149:
150: /* If an operand is an unoffsettable memory ref, find a register
151: we can increment temporarily to make it refer to the second word. */
152:
153: if (optype0 == MEMOP)
154: addreg0 = find_addr_reg (operands[0]);
155:
156: if (optype1 == MEMOP)
157: addreg1 = find_addr_reg (operands[1]);
158:
159: /* Ok, we can do one word at a time.
160: Normally we do the low-numbered word first,
161: but if either operand is autodecrementing then we
162: do the high-numbered word first.
163:
164: In either case, set up in LATEHALF the operands to use
165: for the high-numbered word and in some cases alter the
166: operands in OPERANDS to be suitable for the low-numbered word. */
167:
168: if (optype0 == REGOP)
169: latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
170: else if (optype0 == OFFSOP)
171: latehalf[0] = adj_offsetable_operand (operands[0], 4);
172: else
173: latehalf[0] = operands[0];
174:
175: if (optype1 == REGOP)
176: latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
177: else if (optype1 == OFFSOP)
178: latehalf[1] = adj_offsetable_operand (operands[1], 4);
179: else if (optype1 == CNSTOP)
180: {
181: if (CONSTANT_P (operands[1]))
182: latehalf[1] = const0_rtx;
183: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
184: {
185: latehalf[1] = gen_rtx (CONST_INT, VOIDmode, XINT (operands[1], 1));
186: operands[1] = gen_rtx (CONST_INT, VOIDmode, XINT (operands[1], 0));
187: }
188: }
189: else
190: latehalf[1] = operands[1];
191:
192: /* If insn is effectively movd N(sp),-(sp) then we will do the
193: high word first. We should use the adjusted operand 1 (which is N+4(sp))
194: for the low word as well, to compensate for the first decrement of sp. */
195: if (optype0 == PUSHOP
196: && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
197: && reg_mentioned_p (XEXP (XEXP (operands[0], 0), 0), operands[1]))
198: operands[1] = latehalf[1];
199:
200: /* If one or both operands autodecrementing,
201: do the two words, high-numbered first. */
202:
203: /* Likewise, the first move would clobber the source of the second one,
204: do them in the other order. This happens only for registers;
205: such overlap can't happen in memory unless the user explicitly
206: sets it up, and that is an undefined circumstance. */
207:
208: if (optype0 == PUSHOP || optype1 == PUSHOP
209: || (optype0 == REGOP && optype1 == REGOP
210: && REGNO (operands[0]) == REGNO (latehalf[1])))
211: {
212: /* Make any unoffsetable addresses point at high-numbered word. */
213: if (addreg0)
214: output_asm_insn ("addql %#4,%0", &addreg0);
215: if (addreg1)
216: output_asm_insn ("addql %#4,%0", &addreg1);
217:
218: /* Do that word. */
219: output_asm_insn (singlemove_string (latehalf), latehalf);
220:
221: /* Undo the adds we just did. */
222: if (addreg0)
223: output_asm_insn ("subql %#4,%0", &addreg0);
224: if (addreg1)
225: output_asm_insn ("subql %#4,%0", &addreg1);
226:
227: /* Do low-numbered word. */
228: return singlemove_string (operands);
229: }
230:
231: /* Normal case: do the two words, low-numbered first. */
232:
233: output_asm_insn (singlemove_string (operands), operands);
234:
235: /* Make any unoffsetable addresses point at high-numbered word. */
236: if (addreg0)
237: output_asm_insn ("addql %#4,%0", &addreg0);
238: if (addreg1)
239: output_asm_insn ("addql %#4,%0", &addreg1);
240:
241: /* Do that word. */
242: output_asm_insn (singlemove_string (latehalf), latehalf);
243:
244: /* Undo the adds we just did. */
245: if (addreg0)
246: output_asm_insn ("subql %#4,%0", &addreg0);
247: if (addreg1)
248: output_asm_insn ("subql %#4,%0", &addreg1);
249:
250: return "";
251: }
252:
253: /* Return a REG that occurs in ADDR with coefficient 1.
254: ADDR can be effectively incremented by incrementing REG. */
255:
256: static rtx
257: find_addr_reg (addr)
258: rtx addr;
259: {
260: while (GET_CODE (addr) == PLUS)
261: {
262: if (GET_CODE (XEXP (addr, 0)) == REG)
263: addr = XEXP (addr, 0);
264: if (GET_CODE (XEXP (addr, 1)) == REG)
265: addr = XEXP (addr, 1);
266: if (CONSTANT_P (XEXP (addr, 0)))
267: addr = XEXP (addr, 1);
268: if (CONSTANT_P (XEXP (addr, 1)))
269: addr = XEXP (addr, 0);
270: }
271: if (GET_CODE (addr) == REG)
272: return addr;
273: return 0;
274: }
275:
276: char *
277: output_move_const_double (operands)
278: rtx *operands;
279: {
1.1.1.2 ! root 280: if (TARGET_FPA && FPA_REG_P(operands[0]))
! 281: {
! 282: int code = standard_SunFPA_constant_p (operands[1]);
1.1 root 283:
1.1.1.2 ! root 284: if (code != 0)
! 285: {
! 286: static char buf[40];
! 287:
! 288: sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff);
! 289: return buf;
! 290: }
! 291: return "fpmove%.d %1,%0";
! 292: }
! 293: else
1.1 root 294: {
1.1.1.2 ! root 295: int code = standard_68881_constant_p (operands[1]);
1.1 root 296:
1.1.1.2 ! root 297: if (code != 0)
! 298: {
! 299: static char buf[40];
! 300:
! 301: sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
! 302: return buf;
! 303: }
! 304: return "fmove%.d %1,%0";
1.1 root 305: }
306: }
307:
308: char *
309: output_move_const_single (operands)
310: rtx *operands;
311: {
1.1.1.2 ! root 312: if (TARGET_FPA)
! 313: {
! 314: int code = standard_SunFPA_constant_p (operands[1]);
! 315:
! 316: if (code != 0)
! 317: {
! 318: static char buf[40];
1.1 root 319:
1.1.1.2 ! root 320: sprintf (buf, "fpmove%%.s %%%d,%%0", code & 0x1ff);
! 321: return buf;
! 322: }
! 323: return "fpmove%.s %1,%0";
! 324: }
! 325: else
1.1 root 326: {
1.1.1.2 ! root 327: int code = standard_68881_constant_p (operands[1]);
! 328:
! 329: if (code != 0)
! 330: {
! 331: static char buf[40];
1.1 root 332:
1.1.1.2 ! root 333: sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
! 334: return buf;
! 335: }
! 336: return "fmove%.s %f1,%0";
1.1 root 337: }
338: }
339:
340: /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
341: from the "fmovecr" instruction.
342: The value, anded with 0xff, gives the code to use in fmovecr
343: to get the desired constant. */
344:
345: int
346: standard_68881_constant_p (x)
347: rtx x;
348: {
349: union {double d; int i[2];} u;
350: register double d;
351: u.i[0] = XINT (x, 0);
352: u.i[1] = XINT (x, 1);
353: d = u.d;
354:
355: if (d == 0)
356: return 0x0f;
357: /* Note: there are various other constants available
358: but it is a nuisance to put in their values here. */
359: if (d == 1)
360: return 0x32;
361: if (d == 10)
362: return 0x33;
363: if (d == 100)
364: return 0x34;
365: if (d == 10000)
366: return 0x35;
367: if (d == 1e8)
368: return 0x36;
369: if (GET_MODE (x) == SFmode)
370: return 0;
371: if (d == 1e16)
372: return 0x37;
373: /* larger powers of ten in the constants ram are not used
374: because they are not equal to a `double' C constant. */
375: return 0;
376: }
1.1.1.2 ! root 377:
! 378: /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
! 379: from the Sun FPA's constant RAM.
! 380: The value returned, anded with 0x1ff, gives the code to use in fpmove
! 381: to get the desired constant. */
! 382: #define S_E (2.718281745910644531)
! 383: #define D_E (2.718281828459045091)
! 384: #define S_PI (3.141592741012573242)
! 385: #define D_PI (3.141592653589793116)
! 386: #define S_SQRT2 (1.414213538169860840)
! 387: #define D_SQRT2 (1.414213562373095145)
! 388: #define S_LOG2ofE (1.442695021629333496)
! 389: #define D_LOG2ofE (1.442695040888963387)
! 390: #define S_LOG2of10 (3.321928024291992188)
! 391: #define D_LOG2of10 (3.321928024887362182)
! 392: #define S_LOGEof2 (0.6931471824645996094)
! 393: #define D_LOGEof2 (0.6931471805599452862)
! 394: #define S_LOGEof10 (2.302585124969482442)
! 395: #define D_LOGEof10 (2.302585092994045901)
! 396: #define S_LOG10of2 (0.3010300099849700928)
! 397: #define D_LOG10of2 (0.3010299956639811980)
! 398: #define S_LOG10ofE (0.4342944920063018799)
! 399: #define D_LOG10ofE (0.4342944819032518167)
! 400:
! 401: int
! 402: standard_SunFPA_constant_p (x)
! 403: rtx x;
! 404: {
! 405: union {double d; int i[2];} u;
! 406: register double d;
! 407: u.i[0] = XINT (x, 0);
! 408: u.i[1] = XINT (x, 1);
! 409: d = u.d;
! 410:
! 411: if (d == 0.0)
! 412: return 0x200; /* 0 once 0x1ff is anded with it */
! 413: if (d == 1.0)
! 414: return 0xe;
! 415: if (d == 0.5)
! 416: return 0xf;
! 417: if (d == -1.0)
! 418: return 0x10;
! 419: if (d == 2.0)
! 420: return 0x11;
! 421: if (d == 3.0)
! 422: return 0xB1;
! 423: if (d == 4.0)
! 424: return 0x12;
! 425: if (d == 8.0)
! 426: return 0x13;
! 427: if (d == 0.25)
! 428: return 0x15;
! 429: if (d == 0.125)
! 430: return 0x16;
! 431: if (d == 10.0)
! 432: return 0x17;
! 433: if (d == -(1.0/2.0))
! 434: return 0x2E;
! 435:
! 436: /*
! 437: * Stuff that looks different if it's single or double
! 438: */
! 439: if (GET_MODE(x) == SFmode)
! 440: {
! 441: if (d == S_E)
! 442: return 0x8;
! 443: if (d == (2*S_PI))
! 444: return 0x9;
! 445: if (d == S_PI)
! 446: return 0xA;
! 447: if (d == (S_PI / 2.0))
! 448: return 0xB;
! 449: if (d == S_SQRT2)
! 450: return 0xC;
! 451: if (d == (1.0 / S_SQRT2))
! 452: return 0xD;
! 453: /* Large powers of 10 in the constant
! 454: ram are not used because they are
! 455: not equal to a C double constant */
! 456: if (d == -(S_PI / 2.0))
! 457: return 0x27;
! 458: if (d == S_LOG2ofE)
! 459: return 0x28;
! 460: if (d == S_LOG2of10)
! 461: return 0x29;
! 462: if (d == S_LOGEof2)
! 463: return 0x2A;
! 464: if (d == S_LOGEof10)
! 465: return 0x2B;
! 466: if (d == S_LOG10of2)
! 467: return 0x2C;
! 468: if (d == S_LOG10ofE)
! 469: return 0x2D;
! 470: }
! 471: else
! 472: {
! 473: if (d == D_E)
! 474: return 0x8;
! 475: if (d == (2*D_PI))
! 476: return 0x9;
! 477: if (d == D_PI)
! 478: return 0xA;
! 479: if (d == (D_PI / 2.0))
! 480: return 0xB;
! 481: if (d == D_SQRT2)
! 482: return 0xC;
! 483: if (d == (1.0 / D_SQRT2))
! 484: return 0xD;
! 485: /* Large powers of 10 in the constant
! 486: ram are not used because they are
! 487: not equal to a C double constant */
! 488: if (d == -(D_PI / 2.0))
! 489: return 0x27;
! 490: if (d == D_LOG2ofE)
! 491: return 0x28;
! 492: if (d == D_LOG2of10)
! 493: return 0x29;
! 494: if (d == D_LOGEof2)
! 495: return 0x2A;
! 496: if (d == D_LOGEof10)
! 497: return 0x2B;
! 498: if (d == D_LOG10of2)
! 499: return 0x2C;
! 500: if (d == D_LOG10ofE)
! 501: return 0x2D;
! 502: }
! 503: return 0x0;
! 504: }
! 505:
! 506: #undef S_E
! 507: #undef D_E
! 508: #undef S_PI
! 509: #undef D_PI
! 510: #undef S_SQRT2
! 511: #undef D_SQRT2
! 512: #undef S_LOG2ofE
! 513: #undef D_LOG2ofE
! 514: #undef S_LOG2of10
! 515: #undef D_LOG2of10
! 516: #undef S_LOGEof2
! 517: #undef D_LOGEof2
! 518: #undef S_LOGEof10
! 519: #undef D_LOGEof10
! 520: #undef S_LOG10of2
! 521: #undef D_LOG10of2
! 522: #undef S_LOG10ofE
! 523: #undef D_LOG10ofE
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