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1.1 root 1: /* Subroutines for insn-output.c for Motorola 68000 family.
2: Copyright (C) 1987 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is distributed in the hope that it will be useful,
7: but WITHOUT ANY WARRANTY. No author or distributor
8: accepts responsibility to anyone for the consequences of using it
9: or for whether it serves any particular purpose or works at all,
10: unless he says so in writing. Refer to the GNU CC General Public
11: License for full details.
12:
13: Everyone is granted permission to copy, modify and redistribute
14: GNU CC, but only under the conditions described in the
15: GNU CC General Public License. A copy of this license is
16: supposed to have been given to you along with GNU CC so you
17: can know your rights and responsibilities. It should be in a
18: file named COPYING. Among other things, the copyright notice
19: and this notice must be preserved on all copies. */
20:
21:
22: /* Some output-actions in m68k.md need these. */
23: #include <stdio.h>
24: extern FILE *asm_out_file;
25:
1.1.1.2 root 26: /* Index into this array by (register number >> 3) to find the
27: smallest class which contains that register. */
28: enum reg_class regno_reg_class[]
29: = { DATA_REGS, ADDR_REGS, FP_REGS,
30: LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS };
31:
1.1 root 32: static rtx find_addr_reg ();
33:
34: char *
35: output_btst (operands, countop, dataop, insn, signpos)
36: rtx *operands;
37: rtx countop, dataop;
38: rtx insn;
39: int signpos;
40: {
41: operands[0] = countop;
42: operands[1] = dataop;
43: if (GET_CODE (countop) == CONST_INT)
44: {
45: register int count = INTVAL (countop);
46: if (count == signpos)
47: cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
48: else
49: cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
50:
51: if (count == 31
1.1.1.4 root 52: && next_insns_test_no_inequality (insn))
1.1 root 53: return "tst%.l %1";
54: if (count == 15
1.1.1.4 root 55: && next_insns_test_no_inequality (insn))
1.1 root 56: return "tst%.w %1";
57: if (count == 7
1.1.1.4 root 58: && next_insns_test_no_inequality (insn))
1.1 root 59: return "tst%.b %1";
60:
61: cc_status.flags = CC_NOT_NEGATIVE;
62: }
63: return "btst %0,%1";
64: }
65:
66: /* Return the best assembler insn template
67: for moving operands[1] into operands[0] as a fullword. */
68:
69: static char *
70: singlemove_string (operands)
71: rtx *operands;
72: {
1.1.1.2 root 73: if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
74: return "fpmoves %1,%0";
1.1 root 75: if (operands[1] != const0_rtx)
76: return "move%.l %1,%0";
77: if (! ADDRESS_REG_P (operands[0]))
78: return "clr%.l %0";
79: return "sub%.l %0,%0";
80: }
81:
82: /* Output assembler code to perform a doubleword move insn
83: with operands OPERANDS. */
84:
85: char *
86: output_move_double (operands)
87: rtx *operands;
88: {
89: enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
90: rtx latehalf[2];
91: rtx addreg0 = 0, addreg1 = 0;
92:
93: /* First classify both operands. */
94:
95: if (REG_P (operands[0]))
96: optype0 = REGOP;
97: else if (offsetable_memref_p (operands[0]))
98: optype0 = OFFSOP;
99: else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
100: optype0 = POPOP;
101: else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
102: optype0 = PUSHOP;
103: else if (GET_CODE (operands[0]) == MEM)
104: optype0 = MEMOP;
105: else
106: optype0 = RNDOP;
107:
108: if (REG_P (operands[1]))
109: optype1 = REGOP;
110: else if (CONSTANT_P (operands[1])
111: || GET_CODE (operands[1]) == CONST_DOUBLE)
112: optype1 = CNSTOP;
113: else if (offsetable_memref_p (operands[1]))
114: optype1 = OFFSOP;
115: else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
116: optype1 = POPOP;
117: else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
118: optype1 = PUSHOP;
119: else if (GET_CODE (operands[1]) == MEM)
120: optype1 = MEMOP;
121: else
122: optype1 = RNDOP;
123:
124: /* Check for the cases that the operand constraints are not
125: supposed to allow to happen. Abort if we get one,
126: because generating code for these cases is painful. */
127:
128: if (optype0 == RNDOP || optype1 == RNDOP)
129: abort ();
130:
131: /* If one operand is decrementing and one is incrementing
132: decrement the former register explicitly
133: and change that operand into ordinary indexing. */
134:
135: if (optype0 == PUSHOP && optype1 == POPOP)
136: {
137: operands[0] = XEXP (XEXP (operands[0], 0), 0);
138: output_asm_insn ("subq%.l %#8,%0", operands);
139: operands[0] = gen_rtx (MEM, DImode, operands[0]);
140: optype0 = OFFSOP;
141: }
142: if (optype0 == POPOP && optype1 == PUSHOP)
143: {
144: operands[1] = XEXP (XEXP (operands[1], 0), 0);
145: output_asm_insn ("subq%.l %#8,%1", operands);
146: operands[1] = gen_rtx (MEM, DImode, operands[1]);
147: optype1 = OFFSOP;
148: }
149:
150: /* If an operand is an unoffsettable memory ref, find a register
151: we can increment temporarily to make it refer to the second word. */
152:
153: if (optype0 == MEMOP)
154: addreg0 = find_addr_reg (operands[0]);
155:
156: if (optype1 == MEMOP)
157: addreg1 = find_addr_reg (operands[1]);
158:
159: /* Ok, we can do one word at a time.
160: Normally we do the low-numbered word first,
161: but if either operand is autodecrementing then we
162: do the high-numbered word first.
163:
164: In either case, set up in LATEHALF the operands to use
165: for the high-numbered word and in some cases alter the
166: operands in OPERANDS to be suitable for the low-numbered word. */
167:
168: if (optype0 == REGOP)
169: latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
170: else if (optype0 == OFFSOP)
171: latehalf[0] = adj_offsetable_operand (operands[0], 4);
172: else
173: latehalf[0] = operands[0];
174:
175: if (optype1 == REGOP)
176: latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
177: else if (optype1 == OFFSOP)
178: latehalf[1] = adj_offsetable_operand (operands[1], 4);
179: else if (optype1 == CNSTOP)
180: {
181: if (CONSTANT_P (operands[1]))
182: latehalf[1] = const0_rtx;
183: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
184: {
1.1.1.6 ! root 185: latehalf[1] = gen_rtx (CONST_INT, VOIDmode,
! 186: CONST_DOUBLE_HIGH (operands[1]));
! 187: operands[1] = gen_rtx (CONST_INT, VOIDmode,
! 188: CONST_DOUBLE_LOW (operands[1]));
1.1 root 189: }
190: }
191: else
192: latehalf[1] = operands[1];
193:
194: /* If insn is effectively movd N(sp),-(sp) then we will do the
195: high word first. We should use the adjusted operand 1 (which is N+4(sp))
196: for the low word as well, to compensate for the first decrement of sp. */
197: if (optype0 == PUSHOP
198: && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1.1.1.3 root 199: && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
1.1 root 200: operands[1] = latehalf[1];
201:
202: /* If one or both operands autodecrementing,
203: do the two words, high-numbered first. */
204:
205: /* Likewise, the first move would clobber the source of the second one,
206: do them in the other order. This happens only for registers;
207: such overlap can't happen in memory unless the user explicitly
208: sets it up, and that is an undefined circumstance. */
209:
210: if (optype0 == PUSHOP || optype1 == PUSHOP
211: || (optype0 == REGOP && optype1 == REGOP
212: && REGNO (operands[0]) == REGNO (latehalf[1])))
213: {
214: /* Make any unoffsetable addresses point at high-numbered word. */
215: if (addreg0)
216: output_asm_insn ("addql %#4,%0", &addreg0);
217: if (addreg1)
218: output_asm_insn ("addql %#4,%0", &addreg1);
219:
220: /* Do that word. */
221: output_asm_insn (singlemove_string (latehalf), latehalf);
222:
223: /* Undo the adds we just did. */
224: if (addreg0)
225: output_asm_insn ("subql %#4,%0", &addreg0);
226: if (addreg1)
227: output_asm_insn ("subql %#4,%0", &addreg1);
228:
229: /* Do low-numbered word. */
230: return singlemove_string (operands);
231: }
232:
233: /* Normal case: do the two words, low-numbered first. */
234:
235: output_asm_insn (singlemove_string (operands), operands);
236:
237: /* Make any unoffsetable addresses point at high-numbered word. */
238: if (addreg0)
239: output_asm_insn ("addql %#4,%0", &addreg0);
240: if (addreg1)
241: output_asm_insn ("addql %#4,%0", &addreg1);
242:
243: /* Do that word. */
244: output_asm_insn (singlemove_string (latehalf), latehalf);
245:
246: /* Undo the adds we just did. */
247: if (addreg0)
248: output_asm_insn ("subql %#4,%0", &addreg0);
249: if (addreg1)
250: output_asm_insn ("subql %#4,%0", &addreg1);
251:
252: return "";
253: }
254:
255: /* Return a REG that occurs in ADDR with coefficient 1.
256: ADDR can be effectively incremented by incrementing REG. */
257:
258: static rtx
259: find_addr_reg (addr)
260: rtx addr;
261: {
262: while (GET_CODE (addr) == PLUS)
263: {
264: if (GET_CODE (XEXP (addr, 0)) == REG)
265: addr = XEXP (addr, 0);
266: if (GET_CODE (XEXP (addr, 1)) == REG)
267: addr = XEXP (addr, 1);
268: if (CONSTANT_P (XEXP (addr, 0)))
269: addr = XEXP (addr, 1);
270: if (CONSTANT_P (XEXP (addr, 1)))
271: addr = XEXP (addr, 0);
272: }
273: if (GET_CODE (addr) == REG)
274: return addr;
275: return 0;
276: }
277:
278: char *
279: output_move_const_double (operands)
280: rtx *operands;
281: {
1.1.1.2 root 282: if (TARGET_FPA && FPA_REG_P(operands[0]))
283: {
1.1.1.5 root 284: int code = standard_sun_fpa_constant_p (operands[1]);
1.1 root 285:
1.1.1.2 root 286: if (code != 0)
287: {
288: static char buf[40];
289:
290: sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff);
291: return buf;
292: }
293: return "fpmove%.d %1,%0";
294: }
295: else
1.1 root 296: {
1.1.1.2 root 297: int code = standard_68881_constant_p (operands[1]);
1.1 root 298:
1.1.1.2 root 299: if (code != 0)
300: {
301: static char buf[40];
302:
303: sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
304: return buf;
305: }
306: return "fmove%.d %1,%0";
1.1 root 307: }
308: }
309:
310: char *
311: output_move_const_single (operands)
312: rtx *operands;
313: {
1.1.1.2 root 314: if (TARGET_FPA)
315: {
1.1.1.5 root 316: int code = standard_sun_fpa_constant_p (operands[1]);
1.1.1.2 root 317:
318: if (code != 0)
319: {
320: static char buf[40];
1.1 root 321:
1.1.1.5 root 322: sprintf (buf, "fpmove%%.s %%%%%d,%%0", code & 0x1ff);
1.1.1.2 root 323: return buf;
324: }
325: return "fpmove%.s %1,%0";
326: }
327: else
1.1 root 328: {
1.1.1.2 root 329: int code = standard_68881_constant_p (operands[1]);
330:
331: if (code != 0)
332: {
333: static char buf[40];
1.1 root 334:
1.1.1.2 root 335: sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
336: return buf;
337: }
338: return "fmove%.s %f1,%0";
1.1 root 339: }
340: }
341:
342: /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
343: from the "fmovecr" instruction.
344: The value, anded with 0xff, gives the code to use in fmovecr
345: to get the desired constant. */
346:
347: int
348: standard_68881_constant_p (x)
349: rtx x;
350: {
351: union {double d; int i[2];} u;
352: register double d;
1.1.1.6 ! root 353: u.i[0] = CONST_DOUBLE_LOW (x);
! 354: u.i[1] = CONST_DOUBLE_HIGH (x);
1.1 root 355: d = u.d;
356:
357: if (d == 0)
358: return 0x0f;
359: /* Note: there are various other constants available
360: but it is a nuisance to put in their values here. */
361: if (d == 1)
362: return 0x32;
363: if (d == 10)
364: return 0x33;
365: if (d == 100)
366: return 0x34;
367: if (d == 10000)
368: return 0x35;
369: if (d == 1e8)
370: return 0x36;
371: if (GET_MODE (x) == SFmode)
372: return 0;
373: if (d == 1e16)
374: return 0x37;
375: /* larger powers of ten in the constants ram are not used
376: because they are not equal to a `double' C constant. */
377: return 0;
378: }
1.1.1.2 root 379:
380: /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
381: from the Sun FPA's constant RAM.
382: The value returned, anded with 0x1ff, gives the code to use in fpmove
383: to get the desired constant. */
384: #define S_E (2.718281745910644531)
385: #define D_E (2.718281828459045091)
386: #define S_PI (3.141592741012573242)
387: #define D_PI (3.141592653589793116)
388: #define S_SQRT2 (1.414213538169860840)
389: #define D_SQRT2 (1.414213562373095145)
390: #define S_LOG2ofE (1.442695021629333496)
391: #define D_LOG2ofE (1.442695040888963387)
392: #define S_LOG2of10 (3.321928024291992188)
393: #define D_LOG2of10 (3.321928024887362182)
394: #define S_LOGEof2 (0.6931471824645996094)
395: #define D_LOGEof2 (0.6931471805599452862)
396: #define S_LOGEof10 (2.302585124969482442)
397: #define D_LOGEof10 (2.302585092994045901)
398: #define S_LOG10of2 (0.3010300099849700928)
399: #define D_LOG10of2 (0.3010299956639811980)
400: #define S_LOG10ofE (0.4342944920063018799)
401: #define D_LOG10ofE (0.4342944819032518167)
402:
403: int
1.1.1.5 root 404: standard_sun_fpa_constant_p (x)
1.1.1.2 root 405: rtx x;
406: {
407: union {double d; int i[2];} u;
408: register double d;
1.1.1.6 ! root 409: u.i[0] = CONST_DOUBLE_LOW (x);
! 410: u.i[1] = CONST_DOUBLE_HIGH (x);
1.1.1.2 root 411: d = u.d;
412:
413: if (d == 0.0)
414: return 0x200; /* 0 once 0x1ff is anded with it */
415: if (d == 1.0)
416: return 0xe;
417: if (d == 0.5)
418: return 0xf;
419: if (d == -1.0)
420: return 0x10;
421: if (d == 2.0)
422: return 0x11;
423: if (d == 3.0)
424: return 0xB1;
425: if (d == 4.0)
426: return 0x12;
427: if (d == 8.0)
428: return 0x13;
429: if (d == 0.25)
430: return 0x15;
431: if (d == 0.125)
432: return 0x16;
433: if (d == 10.0)
434: return 0x17;
435: if (d == -(1.0/2.0))
436: return 0x2E;
437:
438: /*
439: * Stuff that looks different if it's single or double
440: */
441: if (GET_MODE(x) == SFmode)
442: {
443: if (d == S_E)
444: return 0x8;
445: if (d == (2*S_PI))
446: return 0x9;
447: if (d == S_PI)
448: return 0xA;
449: if (d == (S_PI / 2.0))
450: return 0xB;
451: if (d == S_SQRT2)
452: return 0xC;
453: if (d == (1.0 / S_SQRT2))
454: return 0xD;
455: /* Large powers of 10 in the constant
456: ram are not used because they are
457: not equal to a C double constant */
458: if (d == -(S_PI / 2.0))
459: return 0x27;
460: if (d == S_LOG2ofE)
461: return 0x28;
462: if (d == S_LOG2of10)
463: return 0x29;
464: if (d == S_LOGEof2)
465: return 0x2A;
466: if (d == S_LOGEof10)
467: return 0x2B;
468: if (d == S_LOG10of2)
469: return 0x2C;
470: if (d == S_LOG10ofE)
471: return 0x2D;
472: }
473: else
474: {
475: if (d == D_E)
476: return 0x8;
477: if (d == (2*D_PI))
478: return 0x9;
479: if (d == D_PI)
480: return 0xA;
481: if (d == (D_PI / 2.0))
482: return 0xB;
483: if (d == D_SQRT2)
484: return 0xC;
485: if (d == (1.0 / D_SQRT2))
486: return 0xD;
487: /* Large powers of 10 in the constant
488: ram are not used because they are
489: not equal to a C double constant */
490: if (d == -(D_PI / 2.0))
491: return 0x27;
492: if (d == D_LOG2ofE)
493: return 0x28;
494: if (d == D_LOG2of10)
495: return 0x29;
496: if (d == D_LOGEof2)
497: return 0x2A;
498: if (d == D_LOGEof10)
499: return 0x2B;
500: if (d == D_LOG10of2)
501: return 0x2C;
502: if (d == D_LOG10ofE)
503: return 0x2D;
504: }
505: return 0x0;
506: }
507:
508: #undef S_E
509: #undef D_E
510: #undef S_PI
511: #undef D_PI
512: #undef S_SQRT2
513: #undef D_SQRT2
514: #undef S_LOG2ofE
515: #undef D_LOG2ofE
516: #undef S_LOG2of10
517: #undef D_LOG2of10
518: #undef S_LOGEof2
519: #undef D_LOGEof2
520: #undef S_LOGEof10
521: #undef D_LOGEof10
522: #undef S_LOG10of2
523: #undef D_LOG10of2
524: #undef S_LOG10ofE
525: #undef D_LOG10ofE
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