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1.1 root 1: /* Register to Stack convert for GNU compiler.
2: Copyright (C) 1992 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20: /* This pass converts stack-like registers from the "flat register
21: file" model that gcc uses, to a stack convention that the 387 uses.
22:
23: * The form of the input:
24:
25: On input, the function consists of insn that have had their
26: registers fully allocated to a set of "virtual" registers. Note that
27: the word "virtual" is used differently here than elsewhere in gcc: for
28: each virtual stack reg, there is a hard reg, but the mapping between
29: them is not known until this pass is run. On output, hard register
30: numbers have been substituted, and various pop and exchange insns have
31: been emitted. The hard register numbers and the virtual register
32: numbers completely overlap - before this pass, all stack register
33: numbers are virtual, and afterward they are all hard.
34:
35: The virtual registers can be manipulated normally by gcc, and their
36: semantics are the same as for normal registers. After the hard
37: register numbers are substituted, the semantics of an insn containing
38: stack-like regs are not the same as for an insn with normal regs: for
39: instance, it is not safe to delete an insn that appears to be a no-op
40: move. In general, no insn containing hard regs should be changed
41: after this pass is done.
42:
43: * The form of the output:
44:
45: After this pass, hard register numbers represent the distance from
46: the current top of stack to the desired register. A reference to
47: FIRST_STACK_REG references the top of stack, FIRST_STACK_REG + 1,
48: represents the register just below that, and so forth. Also, REG_DEAD
49: notes indicate whether or not a stack register should be popped.
50:
51: A "swap" insn looks like a parallel of two patterns, where each
52: pattern is a SET: one sets A to B, the other B to A.
53:
54: A "push" or "load" insn is a SET whose SET_DEST is FIRST_STACK_REG
55: and whose SET_DEST is REG or MEM. Any other SET_DEST, such as PLUS,
56: will replace the existing stack top, not push a new value.
57:
58: A store insn is a SET whose SET_DEST is FIRST_STACK_REG, and whose
59: SET_SRC is REG or MEM.
60:
1.1.1.2 root 61: The case where the SET_SRC and SET_DEST are both FIRST_STACK_REG
1.1 root 62: appears ambiguous. As a special case, the presence of a REG_DEAD note
63: for FIRST_STACK_REG differentiates between a load insn and a pop.
64:
65: If a REG_DEAD is present, the insn represents a "pop" that discards
66: the top of the register stack. If there is no REG_DEAD note, then the
67: insn represents a "dup" or a push of the current top of stack onto the
68: stack.
69:
70: * Methodology:
71:
72: Existing REG_DEAD and REG_UNUSED notes for stack registers are
73: deleted and recreated from scratch. REG_DEAD is never created for a
74: SET_DEST, only REG_UNUSED.
75:
76: Before life analysis, the mode of each insn is set based on whether
77: or not any stack registers are mentioned within that insn. VOIDmode
78: means that no regs are mentioned anyway, and QImode means that at
79: least one pattern within the insn mentions stack registers. This
80: information is valid until after reg_to_stack returns, and is used
81: from jump_optimize.
82:
83: * asm_operands:
84:
85: There are several rules on the usage of stack-like regs in
86: asm_operands insns. These rules apply only to the operands that are
87: stack-like regs:
88:
89: 1. Given a set of input regs that die in an asm_operands, it is
90: necessary to know which are implicitly popped by the asm, and
91: which must be explicitly popped by gcc.
92:
93: An input reg that is implicitly popped by the asm must be
94: explicitly clobbered, unless it is constrained to match an
95: output operand.
96:
97: 2. For any input reg that is implicitly popped by an asm, it is
98: necessary to know how to adjust the stack to compensate for the pop.
99: If any non-popped input is closer to the top of the reg-stack than
100: the implicitly popped reg, it would not be possible to know what the
101: stack looked like - it's not clear how the rest of the stack "slides
102: up".
103:
104: All implicitly popped input regs must be closer to the top of
105: the reg-stack than any input that is not implicitly popped.
106:
107: 3. It is possible that if an input dies in an insn, reload might
108: use the input reg for an output reload. Consider this example:
109:
110: asm ("foo" : "=t" (a) : "f" (b));
111:
112: This asm says that input B is not popped by the asm, and that
113: the asm pushes a result onto the reg-stack, ie, the stack is one
114: deeper after the asm than it was before. But, it is possible that
115: reload will think that it can use the same reg for both the input and
116: the output, if input B dies in this insn.
117:
118: If any input operand uses the "f" constraint, all output reg
119: constraints must use the "&" earlyclobber.
120:
121: The asm above would be written as
122:
123: asm ("foo" : "=&t" (a) : "f" (b));
124:
125: 4. Some operands need to be in particular places on the stack. All
126: output operands fall in this category - there is no other way to
127: know which regs the outputs appear in unless the user indicates
128: this in the constraints.
129:
130: Output operands must specifically indicate which reg an output
131: appears in after an asm. "=f" is not allowed: the operand
132: constraints must select a class with a single reg.
133:
134: 5. Output operands may not be "inserted" between existing stack regs.
135: Since no 387 opcode uses a read/write operand, all output operands
136: are dead before the asm_operands, and are pushed by the asm_operands.
137: It makes no sense to push anywhere but the top of the reg-stack.
138:
139: Output operands must start at the top of the reg-stack: output
140: operands may not "skip" a reg.
141:
142: 6. Some asm statements may need extra stack space for internal
143: calculations. This can be guaranteed by clobbering stack registers
144: unrelated to the inputs and outputs.
145:
146: Here are a couple of reasonable asms to want to write. This asm
147: takes one input, which is internally popped, and produces two outputs.
148:
149: asm ("fsincos" : "=t" (cos), "=u" (sin) : "0" (inp));
150:
151: This asm takes two inputs, which are popped by the fyl2xp1 opcode,
152: and replaces them with one output. The user must code the "st(1)"
153: clobber for reg-stack.c to know that fyl2xp1 pops both inputs.
154:
155: asm ("fyl2xp1" : "=t" (result) : "0" (x), "u" (y) : "st(1)");
156:
157: */
158:
159: #include <stdio.h>
160: #include "config.h"
161: #include "tree.h"
162: #include "rtl.h"
163: #include "insn-config.h"
164: #include "regs.h"
165: #include "hard-reg-set.h"
166: #include "flags.h"
167:
168: #ifdef STACK_REGS
169:
170: #define REG_STACK_SIZE (LAST_STACK_REG - FIRST_STACK_REG + 1)
171:
172: /* True if the current function returns a real value. */
173: static int current_function_returns_real;
174:
175: /* This is the basic stack record. TOP is an index into REG[] such
176: that REG[TOP] is the top of stack. If TOP is -1 the stack is empty.
177:
178: If TOP is -2 the stack is not yet initialized: reg_set indicates
179: which registers are live. Stack initialization consists of placing
180: each live reg in array `reg' and setting `top' appropriately. */
181:
182: typedef struct stack_def
183: {
184: int top; /* index to top stack element */
185: HARD_REG_SET reg_set; /* set of live registers */
186: char reg[REG_STACK_SIZE]; /* register - stack mapping */
187: } *stack;
188:
189: /* highest instruction uid */
190: static int max_uid = 0;
191:
192: /* Number of basic blocks in the current function. */
193: static int blocks;
194:
195: /* Element N is first insn in basic block N.
196: This info lasts until we finish compiling the function. */
197: static rtx *block_begin;
198:
199: /* Element N is last insn in basic block N.
200: This info lasts until we finish compiling the function. */
201: static rtx *block_end;
202:
203: /* Element N is nonzero if control can drop into basic block N */
204: static char *block_drops_in;
205:
206: /* Element N says all about the stack at entry block N */
207: static stack block_stack_in;
208:
209: /* Element N says all about the stack life at the end of block N */
210: static HARD_REG_SET *block_out_reg_set;
211:
212: /* This is where the BLOCK_NUM values are really stored. This is set
213: up by find_blocks and used there and in life_analysis. It can be used
214: later, but only to look up an insn that is the head or tail of some
215: block. life_analysis and the stack register conversion process can
216: add insns within a block. */
217: static short *block_number;
218:
219: /* This is the register file for all register after conversion */
220: static rtx FP_mode_reg[FIRST_PSEUDO_REGISTER][(int) MAX_MACHINE_MODE];
221:
222: /* Get the basic block number of an insn. See note at block_number
223: definition are validity of this information. */
224:
225: #define BLOCK_NUM(INSN) \
226: (((INSN_UID (INSN) > max_uid) \
227: ? (short *)(abort() , 0) \
228: : block_number)[INSN_UID (INSN)])
229:
230: extern rtx gen_jump ();
231: extern rtx gen_movdf ();
232: extern rtx find_regno_note ();
233: extern rtx emit_jump_insn_before ();
234: extern rtx emit_label_after ();
235:
236: /* Forward declarations */
237:
238: static void find_blocks ();
239: static void stack_reg_life_analysis ();
240: static void change_stack ();
241: static void convert_regs ();
242: static void dump_stack_info ();
243:
244: /* Return non-zero if any stack register is mentioned somewhere within PAT. */
245:
246: int
247: stack_regs_mentioned_p (pat)
248: register rtx pat;
249: {
250: register char *fmt;
251: register int i;
252:
253: if (STACK_REG_P (pat))
254: return 1;
255:
256: fmt = GET_RTX_FORMAT (GET_CODE (pat));
257: for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
258: {
259: if (fmt[i] == 'E')
260: {
261: register int j;
262:
263: for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
264: if (stack_regs_mentioned_p (XVECEXP (pat, i, j)))
265: return 1;
266: }
267: else if (fmt[i] == 'e' && stack_regs_mentioned_p (XEXP (pat, i)))
268: return 1;
269: }
270:
271: return 0;
272: }
273:
274: /* Convert register usage from "flat" register file usage to a "stack
275: register file. FIRST is the first insn in the function, FILE is the
276: dump file, if used.
277:
278: First compute the beginning and end of each basic block. Do a
279: register life analysis on the stack registers, recording the result
280: for the head and tail of each basic block. The convert each insn one
281: by one. Run a last jump_optimize() pass, if optimizing, to eliminate
282: any cross-jumping created when the converter inserts pop insns.*/
283:
284: void
285: reg_to_stack (first, file)
286: rtx first;
287: FILE *file;
288: {
289: register rtx insn;
290: register int i;
291: int stack_reg_seen = 0;
292: enum machine_mode mode;
293:
294: current_function_returns_real
295: = TREE_CODE (TREE_TYPE (DECL_RESULT (current_function_decl))) == REAL_TYPE;
296:
297: for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode;
298: mode = GET_MODE_WIDER_MODE (mode))
299: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
300: FP_mode_reg[i][(int) mode] = gen_rtx (REG, mode, i);
301:
302: /* Count the basic blocks. Also find maximum insn uid. */
303: {
304: register RTX_CODE prev_code = JUMP_INSN;
305: register RTX_CODE code;
306:
307: max_uid = 0;
308: blocks = 0;
309: for (insn = first; insn; insn = NEXT_INSN (insn))
310: {
311: /* Note that this loop must select the same block boundaries
312: as code in find_blocks. */
313:
314: if (INSN_UID (insn) > max_uid)
315: max_uid = INSN_UID (insn);
316:
317: code = GET_CODE (insn);
318:
319: if (code == CODE_LABEL
320: || (prev_code != INSN
321: && prev_code != CALL_INSN
322: && prev_code != CODE_LABEL
323: && (code == INSN || code == CALL_INSN || code == JUMP_INSN)))
324: blocks++;
325:
326: /* Remember whether or not this insn mentions an FP regs.
327: Check JUMP_INSNs too, in case someone creates a funny PARALLEL. */
328:
329: if ((GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
330: || GET_CODE (insn) == JUMP_INSN)
331: && stack_regs_mentioned_p (PATTERN (insn)))
332: {
333: stack_reg_seen = 1;
334: PUT_MODE (insn, QImode);
335: }
336: else
337: PUT_MODE (insn, VOIDmode);
338:
339: if (code != NOTE)
340: prev_code = code;
341: }
342: }
343:
344: /* If no stack register reference exists in this insn, there isn't
345: anything to convert. */
346:
347: if (! stack_reg_seen)
348: return;
349:
350: /* If there are stack registers, there must be at least one block. */
351:
352: if (! blocks)
353: abort ();
354:
355: /* Allocate some tables that last till end of compiling this function
356: and some needed only in find_blocks and life_analysis. */
357:
358: block_begin = (rtx *) alloca (blocks * sizeof (rtx));
359: block_end = (rtx *) alloca (blocks * sizeof (rtx));
360: block_drops_in = (char *) alloca (blocks);
361:
362: block_stack_in = (stack) alloca (blocks * sizeof (struct stack_def));
363: block_out_reg_set = (HARD_REG_SET *) alloca (blocks * sizeof (HARD_REG_SET));
364: bzero (block_stack_in, blocks * sizeof (struct stack_def));
365: bzero (block_out_reg_set, blocks * sizeof (HARD_REG_SET));
366:
367: block_number = (short *) alloca ((max_uid + 1) * sizeof (short));
368:
369: find_blocks (first);
370: stack_reg_life_analysis (first);
371:
372: /* Dump the life analysis debug information before jump
373: optimization, as that will destroy the LABEL_REFS we keep the
374: information in. */
375:
376: if (file)
377: dump_stack_info (file);
378:
379: convert_regs ();
380:
381: if (optimize)
382: jump_optimize (first, 2, 0, 0);
383: }
384:
385: /* Check PAT, which is in INSN, for LABEL_REFs. Add INSN to the
386: label's chain of references, and note which insn contains each
387: reference. */
388:
389: static void
390: record_label_references (insn, pat)
391: rtx insn, pat;
392: {
393: register enum rtx_code code = GET_CODE (pat);
394: register int i;
395: register char *fmt;
396:
397: if (code == LABEL_REF)
398: {
399: register rtx label = XEXP (pat, 0);
400: register rtx ref;
401:
402: if (GET_CODE (label) != CODE_LABEL)
403: abort ();
404:
405: /* Don't make a duplicate in the code_label's chain. */
406:
407: for (ref = LABEL_REFS (label); ref != label; ref = LABEL_NEXTREF (ref))
408: if (CONTAINING_INSN (ref) == insn)
409: return;
410:
411: CONTAINING_INSN (pat) = insn;
412: LABEL_NEXTREF (pat) = LABEL_REFS (label);
413: LABEL_REFS (label) = pat;
414:
415: return;
416: }
417:
418: fmt = GET_RTX_FORMAT (code);
419: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
420: {
421: if (fmt[i] == 'e')
422: record_label_references (insn, XEXP (pat, i));
423: if (fmt[i] == 'E')
424: {
425: register int j;
426: for (j = 0; j < XVECLEN (pat, i); j++)
427: record_label_references (insn, XVECEXP (pat, i, j));
428: }
429: }
430: }
431:
432: /* Return a pointer to the REG expression within PAT. If PAT is not a
433: REG, possible enclosed by a conversion rtx, return the inner part of
434: PAT that stopped the search. */
435:
436: static rtx *
437: get_true_reg (pat)
438: rtx *pat;
439: {
440: while (GET_CODE (*pat) == SUBREG
441: || GET_CODE (*pat) == FLOAT
442: || GET_CODE (*pat) == FIX
443: || GET_CODE (*pat) == FLOAT_EXTEND
444: || GET_CODE (*pat) == FLOAT_TRUNCATE)
445: pat = & XEXP (*pat, 0);
446:
447: return pat;
448: }
449:
450: /* If REG is a stack register that is marked dead in REGSTACK, then
451: record that it is now live. If REG is not DEST, add a death note to
452: INSN if there isn't one already. If DEST is not a reg, it is safe to
453: assume that it does not mention a reg anywhere within. */
454:
455: static void
456: record_note_if_dead (insn, regstack, reg, dest)
457: rtx insn;
458: stack regstack;
459: rtx reg, dest;
460: {
461: reg = * get_true_reg (& reg);
462:
463: if (STACK_REG_P (reg))
464: {
465: if (! TEST_HARD_REG_BIT (regstack->reg_set, REGNO (reg)))
466: {
467: if ((! REG_P (dest) || REGNO (dest) != REGNO (reg))
468: && ! find_regno_note (insn, REG_DEAD, REGNO (reg)))
469: REG_NOTES (insn) = gen_rtx (EXPR_LIST,
470: REG_DEAD, reg, REG_NOTES (insn));
471:
472: SET_HARD_REG_BIT (regstack->reg_set, REGNO (reg));
473: }
474: }
475: else
476: if (stack_regs_mentioned_p (reg))
477: abort ();
478: }
479:
480: /* Scan the OPERANDS and OPERAND_CONSTRAINTS of an asm_operands.
481: N_OPERANDS is the total number of operands. Return which alternative
482: matched, or -1 is no alternative matches.
483:
484: OPERAND_MATCHES is an array which indicates which operand this
485: operand matches due to the constraints, or -1 if no match is required.
486: If two operands match by coincidence, but are not required to match by
487: the constraints, -1 is returned.
488:
489: OPERAND_CLASS is an array which indicates the smallest class
490: required by the constraints. If the alternative that matches calls
491: for some class `class', and the operand matches a subclass of `class',
492: OPERAND_CLASS is set to `class' as required by the constraints, not to
493: the subclass. If an alternative allows more than one class,
494: OPERAND_CLASS is set to the smallest class that is a union of the
495: allowed classes. */
496:
497: static int
498: constrain_asm_operands (n_operands, operands, operand_constraints,
499: operand_matches, operand_class)
500: int n_operands;
501: rtx *operands;
502: char **operand_constraints;
503: int *operand_matches;
504: enum reg_class *operand_class;
505: {
506: char **constraints = (char **) alloca (n_operands * sizeof (char *));
507: char *q;
508: int this_alternative, this_operand;
509: int n_alternatives;
510: int j;
511:
512: for (j = 0; j < n_operands; j++)
513: constraints[j] = operand_constraints[j];
514:
515: /* Compute the number of alternatives in the operands. reload has
516: already guaranteed that all operands have the same number of
517: alternatives. */
518:
519: n_alternatives = 1;
520: for (q = constraints[0]; *q; q++)
521: n_alternatives += (*q == ',');
522:
523: this_alternative = 0;
524: while (this_alternative < n_alternatives)
525: {
526: int lose = 0;
527: int i;
528:
529: /* No operands match, no narrow class requirements yet. */
530: for (i = 0; i < n_operands; i++)
531: {
532: operand_matches[i] = -1;
533: operand_class[i] = NO_REGS;
534: }
535:
536: for (this_operand = 0; this_operand < n_operands; this_operand++)
537: {
538: rtx op = operands[this_operand];
539: enum machine_mode mode = GET_MODE (op);
540: char *p = constraints[this_operand];
541: int offset = 0;
542: int win = 0;
543: int c;
544:
545: if (GET_CODE (op) == SUBREG)
546: {
547: if (GET_CODE (SUBREG_REG (op)) == REG
548: && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
549: offset = SUBREG_WORD (op);
550: op = SUBREG_REG (op);
551: }
552:
553: /* An empty constraint or empty alternative
554: allows anything which matched the pattern. */
555: if (*p == 0 || *p == ',')
556: win = 1;
557:
558: while (*p && (c = *p++) != ',')
559: switch (c)
560: {
561: case '=':
562: case '+':
563: case '?':
564: case '&':
565: case '!':
566: case '*':
567: case '%':
568: /* Ignore these. */
569: break;
570:
1.1.1.3 ! root 571: case '#':
! 572: /* Ignore rest of this alternative. */
! 573: while (*p && *p != ',') p++;
! 574: break;
! 575:
1.1 root 576: case '0':
577: case '1':
578: case '2':
579: case '3':
580: case '4':
581: case '5':
582: /* This operand must be the same as a previous one.
583: This kind of constraint is used for instructions such
584: as add when they take only two operands.
585:
586: Note that the lower-numbered operand is passed first. */
587:
588: if (operands_match_p (operands[c - '0'],
589: operands[this_operand]))
590: {
591: operand_matches[this_operand] = c - '0';
592: win = 1;
593: }
594: break;
595:
596: case 'p':
597: /* p is used for address_operands. Since this is an asm,
598: just to make sure that the operand is valid for Pmode. */
599:
600: if (strict_memory_address_p (Pmode, op))
601: win = 1;
602: break;
603:
604: case 'g':
605: /* Anything goes unless it is a REG and really has a hard reg
606: but the hard reg is not in the class GENERAL_REGS. */
607: if (GENERAL_REGS == ALL_REGS
608: || GET_CODE (op) != REG
609: || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
610: {
611: if (GET_CODE (op) == REG)
612: operand_class[this_operand]
613: = reg_class_subunion[(int) operand_class[this_operand]][(int) GENERAL_REGS];
614: win = 1;
615: }
616: break;
617:
618: case 'r':
619: if (GET_CODE (op) == REG
620: && (GENERAL_REGS == ALL_REGS
621: || reg_fits_class_p (op, GENERAL_REGS, offset, mode)))
622: {
623: operand_class[this_operand]
624: = reg_class_subunion[(int) operand_class[this_operand]][(int) GENERAL_REGS];
625: win = 1;
626: }
627: break;
628:
629: case 'X':
630: /* This is used for a MATCH_SCRATCH in the cases when we
631: don't actually need anything. So anything goes any time. */
632: win = 1;
633: break;
634:
635: case 'm':
636: if (GET_CODE (op) == MEM)
637: win = 1;
638: break;
639:
640: case '<':
641: if (GET_CODE (op) == MEM
642: && (GET_CODE (XEXP (op, 0)) == PRE_DEC
643: || GET_CODE (XEXP (op, 0)) == POST_DEC))
644: win = 1;
645: break;
646:
647: case '>':
648: if (GET_CODE (op) == MEM
649: && (GET_CODE (XEXP (op, 0)) == PRE_INC
650: || GET_CODE (XEXP (op, 0)) == POST_INC))
651: win = 1;
652: break;
653:
654: case 'E':
655: /* Match any CONST_DOUBLE, but only if
656: we can examine the bits of it reliably. */
657: if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
658: || HOST_BITS_PER_INT != BITS_PER_WORD)
659: && GET_CODE (op) != VOIDmode && ! flag_pretend_float)
660: break;
661: if (GET_CODE (op) == CONST_DOUBLE)
662: win = 1;
663: break;
664:
665: case 'F':
666: if (GET_CODE (op) == CONST_DOUBLE)
667: win = 1;
668: break;
669:
670: case 'G':
671: case 'H':
672: if (GET_CODE (op) == CONST_DOUBLE
673: && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
674: win = 1;
675: break;
676:
677: case 's':
678: if (GET_CODE (op) == CONST_INT
679: || (GET_CODE (op) == CONST_DOUBLE
680: && GET_MODE (op) == VOIDmode))
681: break;
682: /* Fall through */
683: case 'i':
684: if (CONSTANT_P (op))
685: win = 1;
686: break;
687:
688: case 'n':
689: if (GET_CODE (op) == CONST_INT
690: || (GET_CODE (op) == CONST_DOUBLE
691: && GET_MODE (op) == VOIDmode))
692: win = 1;
693: break;
694:
695: case 'I':
696: case 'J':
697: case 'K':
698: case 'L':
699: case 'M':
700: case 'N':
701: case 'O':
702: case 'P':
703: if (GET_CODE (op) == CONST_INT
704: && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
705: win = 1;
706: break;
707:
708: #ifdef EXTRA_CONSTRAINT
709: case 'Q':
710: case 'R':
711: case 'S':
712: case 'T':
713: case 'U':
714: if (EXTRA_CONSTRAINT (op, c))
715: win = 1;
716: break;
717: #endif
718:
719: case 'V':
720: if (GET_CODE (op) == MEM && ! offsettable_memref_p (op))
721: win = 1;
722: break;
723:
724: case 'o':
725: if (offsettable_memref_p (op))
726: win = 1;
727: break;
728:
729: default:
730: if (GET_CODE (op) == REG
731: && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c),
732: offset, mode))
733: {
734: operand_class[this_operand]
735: = reg_class_subunion[(int)operand_class[this_operand]][(int) REG_CLASS_FROM_LETTER (c)];
736: win = 1;
737: }
738: }
739:
740: constraints[this_operand] = p;
741: /* If this operand did not win somehow,
742: this alternative loses. */
743: if (! win)
744: lose = 1;
745: }
746: /* This alternative won; the operands are ok.
747: Change whichever operands this alternative says to change. */
748: if (! lose)
749: break;
750:
751: this_alternative++;
752: }
753:
754: /* For operands constrained to match another operand, copy the other
755: operand's class to this operand's class. */
756: for (j = 0; j < n_operands; j++)
757: if (operand_matches[j] >= 0)
758: operand_class[j] = operand_class[operand_matches[j]];
759:
760: return this_alternative == n_alternatives ? -1 : this_alternative;
761: }
762:
763: /* Record the life info of each stack reg in INSN, updating REGSTACK.
764: N_INPUTS is the number of inputs; N_OUTPUTS the outputs. CONSTRAINTS
765: is an array of the constraint strings used in the asm statement.
766: OPERANDS is an array of all operands for the insn, and is assumed to
767: contain all output operands, then all inputs operands.
768:
769: There are many rules that an asm statement for stack-like regs must
770: follow. Those rules are explained at the top of this file: the rule
771: numbers below refer to that explanation. */
772:
773: static void
774: record_asm_reg_life (insn, regstack, operands, constraints,
775: n_inputs, n_outputs)
776: rtx insn;
777: stack regstack;
778: rtx *operands;
779: char **constraints;
780: int n_inputs, n_outputs;
781: {
782: int i;
783: int n_operands = n_inputs + n_outputs;
784: int first_input = n_outputs;
785: int n_clobbers;
786: int malformed_asm = 0;
787: rtx body = PATTERN (insn);
788:
789: int *operand_matches = (int *) alloca (n_operands * sizeof (int *));
790:
791: enum reg_class *operand_class
792: = (enum reg_class *) alloca (n_operands * sizeof (enum reg_class *));
793:
794: int reg_used_as_output[FIRST_PSEUDO_REGISTER];
795: int implicitly_dies[FIRST_PSEUDO_REGISTER];
796:
797: rtx *clobber_reg;
798:
799: /* Find out what the constraints required. If no constraint
800: alternative matches, that is a compiler bug: we should have caught
801: such an insn during reload. */
802: i = constrain_asm_operands (n_operands, operands, constraints,
803: operand_matches, operand_class);
804: if (i < 0)
805: abort ();
806:
807: /* Strip SUBREGs here to make the following code simpler. */
808: for (i = 0; i < n_operands; i++)
809: if (GET_CODE (operands[i]) == SUBREG
810: && GET_CODE (SUBREG_REG (operands[i])) == REG)
811: operands[i] = SUBREG_REG (operands[i]);
812:
813: /* Set up CLOBBER_REG. */
814:
815: n_clobbers = 0;
816:
817: if (GET_CODE (body) == PARALLEL)
1.1.1.2 root 818: {
819: clobber_reg = (rtx *) alloca (XVECLEN (body, 0) * sizeof (rtx *));
1.1 root 820:
1.1.1.2 root 821: for (i = 0; i < XVECLEN (body, 0); i++)
822: if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
823: {
824: rtx clobber = XVECEXP (body, 0, i);
825: rtx reg = XEXP (clobber, 0);
1.1 root 826:
1.1.1.2 root 827: if (GET_CODE (reg) == SUBREG && GET_CODE (SUBREG_REG (reg)) == REG)
828: reg = SUBREG_REG (reg);
829:
830: if (STACK_REG_P (reg))
831: {
832: clobber_reg[n_clobbers] = reg;
833: n_clobbers++;
834: }
835: }
836: }
1.1 root 837:
838: /* Enforce rule #4: Output operands must specifically indicate which
839: reg an output appears in after an asm. "=f" is not allowed: the
840: operand constraints must select a class with a single reg.
841:
842: Also enforce rule #5: Output operands must start at the top of
843: the reg-stack: output operands may not "skip" a reg. */
844:
845: bzero (reg_used_as_output, sizeof (reg_used_as_output));
846: for (i = 0; i < n_outputs; i++)
847: if (STACK_REG_P (operands[i]))
848: if (reg_class_size[operand_class[i]] != 1)
849: {
850: error_for_asm
851: (insn, "Output constraint %d must specify a single register", i);
852: malformed_asm = 1;
853: }
854: else
855: reg_used_as_output[REGNO (operands[i])] = 1;
856:
857:
858: /* Search for first non-popped reg. */
859: for (i = FIRST_STACK_REG; i < LAST_STACK_REG + 1; i++)
860: if (! reg_used_as_output[i])
861: break;
862:
863: /* If there are any other popped regs, that's an error. */
864: for (; i < LAST_STACK_REG + 1; i++)
865: if (reg_used_as_output[i])
866: break;
867:
868: if (i != LAST_STACK_REG + 1)
869: {
870: error_for_asm (insn, "Output regs must be grouped at top of stack");
871: malformed_asm = 1;
872: }
873:
874: /* Enforce rule #2: All implicitly popped input regs must be closer
875: to the top of the reg-stack than any input that is not implicitly
876: popped. */
877:
878: bzero (implicitly_dies, sizeof (implicitly_dies));
879: for (i = first_input; i < first_input + n_inputs; i++)
880: if (STACK_REG_P (operands[i]))
881: {
882: /* An input reg is implicitly popped if it is tied to an
883: output, or if there is a CLOBBER for it. */
884: int j;
885:
886: for (j = 0; j < n_clobbers; j++)
887: if (operands_match_p (clobber_reg[j], operands[i]))
888: break;
889:
890: if (j < n_clobbers || operand_matches[i] >= 0)
891: implicitly_dies[REGNO (operands[i])] = 1;
892: }
893:
894: /* Search for first non-popped reg. */
895: for (i = FIRST_STACK_REG; i < LAST_STACK_REG + 1; i++)
896: if (! implicitly_dies[i])
897: break;
898:
899: /* If there are any other popped regs, that's an error. */
900: for (; i < LAST_STACK_REG + 1; i++)
901: if (implicitly_dies[i])
902: break;
903:
904: if (i != LAST_STACK_REG + 1)
905: {
906: error_for_asm (insn,
907: "Implicitly popped regs must be grouped at top of stack");
908: malformed_asm = 1;
909: }
910:
911: /* Enfore rule #3: If any input operand uses the "f" constraint, all
912: output constraints must use the "&" earlyclobber.
913:
914: ??? Detect this more deterministically by having constraint_asm_operands
915: record any earlyclobber. */
916:
917: for (i = first_input; i < first_input + n_inputs; i++)
918: if (operand_matches[i] == -1)
919: {
920: int j;
921:
922: for (j = 0; j < n_outputs; j++)
923: if (operands_match_p (operands[j], operands[i]))
924: {
925: error_for_asm (insn,
926: "Output operand %d must use `&' constraint", j);
927: malformed_asm = 1;
928: }
929: }
930:
931: if (malformed_asm)
932: {
933: /* Avoid further trouble with this insn. */
934: PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
935: PUT_MODE (insn, VOIDmode);
936: return;
937: }
938:
939: /* Process all outputs */
940: for (i = 0; i < n_outputs; i++)
941: {
942: rtx op = operands[i];
943:
944: if (! STACK_REG_P (op))
945: if (stack_regs_mentioned_p (op))
946: abort ();
947: else
948: continue;
949:
950: /* Each destination is dead before this insn. If the
951: destination is not used after this insn, record this with
952: REG_UNUSED. */
953:
954: if (! TEST_HARD_REG_BIT (regstack->reg_set, REGNO (op)))
955: REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_UNUSED, op,
956: REG_NOTES (insn));
957:
958: CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (op));
959: }
960:
961: /* Process all inputs */
962: for (i = first_input; i < first_input + n_inputs; i++)
963: {
964: if (! STACK_REG_P (operands[i]))
965: if (stack_regs_mentioned_p (operands[i]))
966: abort ();
967: else
968: continue;
969:
970: /* If an input is dead after the insn, record a death note.
971: But don't record a death note if there is already a death note,
972: or if the input is also an output. */
973:
974: if (! TEST_HARD_REG_BIT (regstack->reg_set, REGNO (operands[i]))
975: && operand_matches[i] == -1
976: && ! find_regno_note (insn, REG_DEAD, REGNO (operands[i])))
977: REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_DEAD, operands[i],
978: REG_NOTES (insn));
979:
980: SET_HARD_REG_BIT (regstack->reg_set, REGNO (operands[i]));
981: }
982: }
983:
984: /* Scan PAT, which is part of INSN, and record the life & death of
985: stack registers in REGSTACK. If a register was dead, but is an input
986: operand in this insn, then mark the register live and record a death
987: note.
988:
989: If a register is dead after this insn, but is an output operand in
990: this insn, record a REG_UNUSED note.
991:
992: This function does not know about SET_DESTs that are both input and
993: output (such as ZERO_EXTRACT) - this cannot happen on a 387. */
994:
995: static void
996: record_reg_life_pat (insn, regstack, pat)
997: rtx insn;
998: stack regstack;
999: rtx pat;
1000: {
1001: rtx src, dest;
1002:
1003: /* We should have already handled any asm. */
1004: if (GET_CODE (pat) == ASM_INPUT || GET_CODE (pat) == ASM_OPERANDS)
1005: abort ();
1006:
1007: if (GET_CODE (pat) != SET)
1008: return;
1009:
1010: dest = * get_true_reg (& SET_DEST (pat));
1011:
1012: /* The destination is dead before this insn. If the destination is
1013: not used after this insn, record this with REG_UNUSED. */
1014:
1015: if (STACK_REG_P (dest))
1016: {
1017: /* ??? This check is unnecessary. */
1018:
1019: if (find_regno_note (insn, REG_UNUSED, REGNO (dest)))
1020: abort ();
1021:
1022: if (! TEST_HARD_REG_BIT (regstack->reg_set, REGNO (dest)))
1023: REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_UNUSED, dest,
1024: REG_NOTES (insn));
1025:
1026: CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (dest));
1027: }
1028: else
1029: if (dest != cc0_rtx && stack_regs_mentioned_p (dest))
1030: abort ();
1031:
1032: src = * get_true_reg (& SET_SRC (pat));
1033:
1034: switch (GET_CODE (src))
1035: {
1036: /* ??? get_true_reg will make some of these cases redundant. */
1037:
1038: case PLUS:
1039: case MINUS:
1040: case MULT:
1041: case DIV:
1042: case COMPARE:
1043: record_note_if_dead (insn, regstack, XEXP (src, 0), dest);
1044: record_note_if_dead (insn, regstack, XEXP (src, 1), dest);
1045: break;
1046:
1047: case ABS:
1048: case NEG:
1049: case SQRT:
1050: case FLOAT_EXTEND:
1051: case FLOAT_TRUNCATE:
1052: case FLOAT:
1053: case UNSIGNED_FLOAT:
1054: record_note_if_dead (insn, regstack, XEXP (src, 0), dest);
1055: break;
1056:
1057: case UNSIGNED_FIX:
1058: case FIX:
1059: src = XEXP (src, 0);
1060: if (GET_CODE (src) == FIX)
1061: record_note_if_dead (insn, regstack, XEXP (src, 0), dest);
1062: else
1063: record_note_if_dead (insn, regstack, src, dest);
1064: break;
1065:
1066: case ASM_OPERANDS:
1067: case ASM_INPUT:
1068: abort (); /* we should have caught this already. */
1069: break;
1070:
1071: case REG:
1072: record_note_if_dead (insn, regstack, src, dest);
1073: break;
1074:
1075: default:
1076: /* If a stack register appears in the src RTL, it is a bug, and
1077: code should be added above to handle it. */
1078:
1079: if (stack_regs_mentioned_p (src))
1080: abort ();
1081: }
1082: }
1083:
1084: /* Calculate the number of inputs and outputs in BODY, an
1085: asm_operands. N_OPERANDS is the total number of operands, and
1086: N_INPUTS and N_OUTPUTS are pointers to ints into which the results are
1087: placed. */
1088:
1089: static void
1090: get_asm_operand_lengths (body, n_operands, n_inputs, n_outputs)
1091: rtx body;
1092: int n_operands;
1093: int *n_inputs, *n_outputs;
1094: {
1095: if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1096: *n_inputs = ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body));
1097:
1098: else if (GET_CODE (body) == ASM_OPERANDS)
1099: *n_inputs = ASM_OPERANDS_INPUT_LENGTH (body);
1100:
1101: else if (GET_CODE (body) == PARALLEL
1102: && GET_CODE (XVECEXP (body, 0, 0)) == SET)
1103: *n_inputs = ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0)));
1104:
1105: else if (GET_CODE (body) == PARALLEL
1106: && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1107: *n_inputs = ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0));
1108: else
1109: abort ();
1110:
1111: *n_outputs = n_operands - *n_inputs;
1112: }
1113:
1114: /* Scan INSN, which is in BLOCK, and record the life & death of stack
1115: registers in REGSTACK. This function is called to process insns from
1116: the last insn in a block to the first. The actual scanning is done in
1117: record_reg_life_pat.
1118:
1119: If a register is live after a CALL_INSN, but is not a value return
1120: register for that CALL_INSN, then code is emitted to initialize that
1121: register. The block_end[] data is kept accurate.
1122:
1123: Existing death and unset notes for stack registers are deleted
1124: before processing the insn. */
1125:
1126: static void
1127: record_reg_life (insn, block, regstack)
1128: rtx insn;
1129: int block;
1130: stack regstack;
1131: {
1132: rtx note, *note_link;
1133: int n_operands;
1134:
1135: if ((GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
1136: || INSN_DELETED_P (insn))
1137: return;
1138:
1139: /* Strip death notes for stack regs from this insn */
1140:
1141: note_link = ®_NOTES(insn);
1142: for (note = *note_link; note; note = XEXP (note, 1))
1143: if (STACK_REG_P (XEXP (note, 0))
1144: && (REG_NOTE_KIND (note) == REG_DEAD
1145: || REG_NOTE_KIND (note) == REG_UNUSED))
1146: *note_link = XEXP (note, 1);
1147: else
1148: note_link = &XEXP (note, 1);
1149:
1150: /* Process all patterns in the insn. */
1151:
1152: n_operands = asm_noperands (PATTERN (insn));
1153: if (n_operands >= 0)
1154: {
1155: /* This insn is an `asm' with operands. Decode the operands,
1156: decide how many are inputs, and record the life information. */
1157:
1158: rtx operands[MAX_RECOG_OPERANDS];
1159: rtx body = PATTERN (insn);
1160: int n_inputs, n_outputs;
1161: char **constraints = (char **) alloca (n_operands * sizeof (char *));
1162:
1163: decode_asm_operands (body, operands, 0, constraints, 0);
1164: get_asm_operand_lengths (body, n_operands, &n_inputs, &n_outputs);
1165: record_asm_reg_life (insn, regstack, operands, constraints,
1166: n_inputs, n_outputs);
1167: return;
1168: }
1169:
1170: if (GET_CODE (PATTERN (insn)) == PARALLEL)
1171: {
1172: register int i;
1173:
1174: for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1175: record_reg_life_pat (insn, regstack, XVECEXP (PATTERN (insn), 0, i));
1176: }
1177: else if (GET_MODE (insn) == QImode)
1178: record_reg_life_pat (insn, regstack, PATTERN (insn));
1179:
1180: /* There might be a reg that is live after a function call.
1181: Initialize it to zero so that the program does not crash. See comment
1182: towards the end of stack_reg_life_analysis(). */
1183:
1184: if (GET_CODE (insn) == CALL_INSN)
1185: {
1186: int reg = FIRST_FLOAT_REG;
1187:
1188: /* If a stack reg is mentioned in a CALL_INSN, it must be as the
1189: return value; conversely, if a float is returned, a stack reg
1190: must be mentioned. */
1191:
1192: if (stack_regs_mentioned_p (PATTERN (insn)))
1193: reg++;
1194:
1195: for (; reg <= LAST_STACK_REG; reg++)
1196: if (TEST_HARD_REG_BIT (regstack->reg_set, reg))
1197: {
1198: rtx init, pat;
1199:
1200: /* The insn will use virtual register numbers, and so
1201: convert_regs is expected to process these. But BLOCK_NUM
1202: cannot be used on these insns, because they do not appear in
1203: block_number[]. */
1204:
1205: pat = gen_rtx (SET, VOIDmode, FP_mode_reg[reg][(int) DFmode],
1206: CONST0_RTX (DFmode));
1207: init = emit_insn_after (pat, insn);
1208: PUT_MODE (init, QImode);
1209:
1210: CLEAR_HARD_REG_BIT (regstack->reg_set, reg);
1211:
1212: /* If the CALL_INSN was the end of a block, move the
1213: block_end to point to the new insn. */
1214:
1215: if (block_end[block] == insn)
1216: block_end[block] = init;
1217: }
1218:
1219: /* Some regs do not survive a CALL */
1220:
1221: AND_COMPL_HARD_REG_SET (regstack->reg_set, call_used_reg_set);
1222: }
1223: }
1224:
1225: /* Find all basic blocks of the function, which starts with FIRST.
1226: For each JUMP_INSN, build the chain of LABEL_REFS on each CODE_LABEL. */
1227:
1228: static void
1229: find_blocks (first)
1230: rtx first;
1231: {
1232: register rtx insn;
1233: register int block;
1234: register RTX_CODE prev_code = BARRIER;
1235: register RTX_CODE code;
1236:
1237: /* Record where all the blocks start and end.
1238: Record which basic blocks control can drop in to. */
1239:
1240: block = -1;
1241: for (insn = first; insn; insn = NEXT_INSN (insn))
1242: {
1243: /* Note that this loop must select the same block boundaries
1244: as code in reg_to_stack. */
1245:
1246: code = GET_CODE (insn);
1247:
1248: if (code == CODE_LABEL
1249: || (prev_code != INSN
1250: && prev_code != CALL_INSN
1251: && prev_code != CODE_LABEL
1252: && (code == INSN || code == CALL_INSN || code == JUMP_INSN)))
1253: {
1254: block_begin[++block] = insn;
1255: block_end[block] = insn;
1256: block_drops_in[block] = prev_code != BARRIER;
1257: }
1258: else if (code == INSN || code == CALL_INSN || code == JUMP_INSN)
1259: block_end[block] = insn;
1260:
1261: BLOCK_NUM (insn) = block;
1262:
1263: if (code == CODE_LABEL)
1264: LABEL_REFS (insn) = insn; /* delete old chain */
1265:
1266: if (code != NOTE)
1267: prev_code = code;
1268: }
1269:
1270: if (block + 1 != blocks)
1271: abort ();
1272:
1.1.1.3 ! root 1273: /* generate all label references to the corresponding jump insn */
1.1 root 1274: for (block = 0; block < blocks; block++)
1275: {
1276: insn = block_end[block];
1277:
1278: if (GET_CODE (insn) == JUMP_INSN)
1279: record_label_references (insn, PATTERN (insn));
1280: }
1281: }
1282:
1283: /* Determine the which registers are live at the start of each basic
1284: block of the function whose first insn is FIRST.
1285:
1286: First, if the function returns a real_type, mark the function
1287: return type as live at each return point, as the RTL may not give any
1288: hint that the register is live.
1289:
1290: Then, start with the last block and work back to the first block.
1291: Similarly, work backwards within each block, insn by insn, recording
1292: which regs are die and which are used (and therefore live) in the
1293: hard reg set of block_stack_in[].
1294:
1295: After processing each basic block, if there is a label at the start
1296: of the block, propagate the live registers to all jumps to this block.
1297:
1298: As a special case, if there are regs live in this block, that are
1299: not live in a block containing a jump to this label, and the block
1300: containing the jump has already been processed, we must propagate this
1301: block's entry register life back to the block containing the jump, and
1302: restart life analysis from there.
1303:
1304: In the worst case, this function may traverse the insns
1305: REG_STACK_SIZE times. This is necessary, since a jump towards the end
1306: of the insns may not know that a reg is live at a target that is early
1307: in the insns. So we back up and start over with the new reg live.
1308:
1309: If there are registers that are live at the start of the function,
1310: insns are emitted to initialize these registers. Something similar is
1311: done after CALL_INSNs in record_reg_life. */
1312:
1313: static void
1314: stack_reg_life_analysis (first)
1315: rtx first;
1316: {
1317: int reg, block;
1318: struct stack_def regstack;
1319:
1320: if (current_function_returns_real)
1321: {
1322: /* Find all RETURN insns and mark them. */
1323:
1324: for (block = blocks - 1; block >= 0; block--)
1325: if (GET_CODE (block_end[block]) == JUMP_INSN
1326: && GET_CODE (PATTERN (block_end[block])) == RETURN)
1327: SET_HARD_REG_BIT (block_out_reg_set[block], FIRST_STACK_REG);
1328:
1329: /* Mark of the end of last block if we "fall off" the end of the
1330: function into the epilogue. */
1331:
1332: if (GET_CODE (block_end[blocks-1]) != JUMP_INSN
1333: || GET_CODE (PATTERN (block_end[blocks-1])) == RETURN)
1334: SET_HARD_REG_BIT (block_out_reg_set[blocks-1], FIRST_STACK_REG);
1335: }
1336:
1337: /* now scan all blocks backward for stack register use */
1338:
1339: block = blocks - 1;
1340: while (block >= 0)
1341: {
1342: register rtx insn, prev;
1343:
1344: /* current register status at last instruction */
1345:
1346: COPY_HARD_REG_SET (regstack.reg_set, block_out_reg_set[block]);
1347:
1348: prev = block_end[block];
1349: do
1350: {
1351: insn = prev;
1352: prev = PREV_INSN (insn);
1353:
1354: /* If the insn is a CALL_INSN, we need to ensure that
1355: everything dies. But otherwise don't process unless there
1356: are some stack regs present. */
1357:
1358: if (GET_MODE (insn) == QImode || GET_CODE (insn) == CALL_INSN)
1359: record_reg_life (insn, block, ®stack);
1360:
1361: } while (insn != block_begin[block]);
1362:
1363: /* Set the state at the start of the block. Mark that no
1364: register mapping information known yet. */
1365:
1366: COPY_HARD_REG_SET (block_stack_in[block].reg_set, regstack.reg_set);
1367: block_stack_in[block].top = -2;
1368:
1369: /* If there is a label, propagate our register life to all jumps
1370: to this label. */
1371:
1372: if (GET_CODE (insn) == CODE_LABEL)
1373: {
1374: register rtx label;
1375: int must_restart = 0;
1376:
1377: for (label = LABEL_REFS (insn); label != insn;
1378: label = LABEL_NEXTREF (label))
1379: {
1380: int jump_block = BLOCK_NUM (CONTAINING_INSN (label));
1381:
1382: if (jump_block < block)
1383: IOR_HARD_REG_SET (block_out_reg_set[jump_block],
1384: block_stack_in[block].reg_set);
1385: else
1386: {
1387: /* The block containing the jump has already been
1388: processed. If there are registers that were not known
1389: to be live then, but are live now, we must back up
1390: and restart life analysis from that point with the new
1391: life information. */
1392:
1393: GO_IF_HARD_REG_SUBSET (block_stack_in[block].reg_set,
1394: block_out_reg_set[jump_block],
1395: win);
1396:
1397: IOR_HARD_REG_SET (block_out_reg_set[jump_block],
1398: block_stack_in[block].reg_set);
1399:
1400: block = jump_block;
1401: must_restart = 1;
1402:
1403: win:
1404: ;
1405: }
1406: }
1407: if (must_restart)
1408: continue;
1409: }
1410:
1411: if (block_drops_in[block])
1412: IOR_HARD_REG_SET (block_out_reg_set[block-1],
1413: block_stack_in[block].reg_set);
1414:
1415: block -= 1;
1416: }
1417:
1418: {
1419: /* If any reg is live at the start of the first block of a
1420: function, then we must guarantee that the reg holds some value by
1421: generating our own "load" of that register. Otherwise a 387 would
1422: fault trying to access an empty register. */
1423:
1424: HARD_REG_SET empty_regs;
1425: CLEAR_HARD_REG_SET (empty_regs);
1426: GO_IF_HARD_REG_SUBSET (block_stack_in[0].reg_set, empty_regs,
1427: no_live_regs);
1428: }
1429:
1430: /* Load zero into each live register. The fact that a register
1431: appears live at the function start does not necessarily imply an error
1432: in the user program: it merely means that we could not determine that
1433: there wasn't such an error, just as -Wunused sometimes gives
1434: "incorrect" warnings. In those cases, these initializations will do
1435: no harm.
1436:
1437: Note that we are inserting virtual register references here:
1438: these insns must be processed by convert_regs later. Also, these
1439: insns will not be in block_number, so BLOCK_NUM() will fail for them. */
1440:
1441: for (reg = LAST_STACK_REG; reg >= FIRST_STACK_REG; reg--)
1442: if (TEST_HARD_REG_BIT (block_stack_in[0].reg_set, reg))
1443: {
1444: rtx init_rtx;
1445:
1446: init_rtx = gen_rtx (SET, VOIDmode, FP_mode_reg[reg][(int) DFmode],
1447: CONST0_RTX (DFmode));
1448: block_begin[0] = emit_insn_after (init_rtx, first);
1449: PUT_MODE (block_begin[0], QImode);
1450:
1451: CLEAR_HARD_REG_BIT (block_stack_in[0].reg_set, reg);
1452: }
1453:
1454: no_live_regs:
1455: ;
1456: }
1457:
1458: /*****************************************************************************
1.1.1.2 root 1459: This section deals with stack register substitution, and forms the second
1.1 root 1460: pass over the RTL.
1461: *****************************************************************************/
1462:
1463: /* Replace REG, which is a pointer to a stack reg RTX, with an RTX for
1464: the desired hard REGNO. */
1465:
1466: static void
1467: replace_reg (reg, regno)
1468: rtx *reg;
1469: int regno;
1470: {
1471: if (regno < FIRST_STACK_REG || regno > LAST_STACK_REG
1472: || ! STACK_REG_P (*reg))
1473: abort ();
1474:
1475: if (GET_MODE_CLASS (GET_MODE (*reg)) != MODE_FLOAT)
1476: abort ();
1477:
1478: *reg = FP_mode_reg[regno][(int) GET_MODE (*reg)];
1479: }
1480:
1481: /* Remove a note of type NOTE, which must be found, for register
1482: number REGNO from INSN. Remove only one such note. */
1483:
1484: static void
1485: remove_regno_note (insn, note, regno)
1486: rtx insn;
1487: enum reg_note note;
1488: int regno;
1489: {
1490: register rtx *note_link, this;
1491:
1492: note_link = ®_NOTES(insn);
1493: for (this = *note_link; this; this = XEXP (this, 1))
1494: if (REG_NOTE_KIND (this) == note
1495: && REG_P (XEXP (this, 0)) && REGNO (XEXP (this, 0)) == regno)
1496: {
1497: *note_link = XEXP (this, 1);
1498: return;
1499: }
1500: else
1501: note_link = &XEXP (this, 1);
1502:
1503: abort ();
1504: }
1505:
1506: /* Find the hard register number of virtual register REG in REGSTACK.
1507: The hard register number is relative to the top of the stack. -1 is
1508: returned if the register is not found. */
1509:
1510: static int
1511: get_hard_regnum (regstack, reg)
1512: stack regstack;
1513: rtx reg;
1514: {
1515: int i;
1516:
1517: if (! STACK_REG_P (reg))
1518: abort ();
1519:
1520: for (i = regstack->top; i >= 0; i--)
1521: if (regstack->reg[i] == REGNO (reg))
1522: break;
1523:
1524: return i >= 0 ? (FIRST_STACK_REG + regstack->top - i) : -1;
1525: }
1526:
1527: /* Delete INSN from the RTL. Mark the insn, but don't remove it from
1528: the chain of insns. Doing so could confuse block_begin and block_end
1529: if this were the only insn in the block. */
1530:
1531: static void
1532: delete_insn_for_stacker (insn)
1533: rtx insn;
1534: {
1535: PUT_CODE (insn, NOTE);
1536: NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1537: NOTE_SOURCE_FILE (insn) = 0;
1538: INSN_DELETED_P (insn) = 1;
1539: }
1540:
1541: /* Emit an insn to pop virtual register REG before or after INSN.
1542: REGSTACK is the stack state after INSN and is updated to reflect this
1543: pop. WHEN is either emit_insn_before or emit_insn_after. A pop insn
1544: is represented as a SET whose destination is the register to be popped
1545: and source is the top of stack. A death note for the top of stack
1546: cases the movdf pattern to pop. */
1547:
1548: static rtx
1549: emit_pop_insn (insn, regstack, reg, when)
1550: rtx insn;
1551: stack regstack;
1552: rtx reg;
1553: rtx (*when)();
1554: {
1555: rtx pop_insn, pop_rtx;
1556: int hard_regno;
1557:
1558: hard_regno = get_hard_regnum (regstack, reg);
1559:
1560: if (hard_regno < FIRST_STACK_REG)
1561: abort ();
1562:
1563: pop_rtx = gen_rtx (SET, VOIDmode, FP_mode_reg[hard_regno][(int) DFmode],
1564: FP_mode_reg[FIRST_STACK_REG][(int) DFmode]);
1565:
1566: pop_insn = (*when) (pop_rtx, insn);
1567: PUT_MODE (pop_insn, VOIDmode);
1568:
1569: REG_NOTES (pop_insn) = gen_rtx (EXPR_LIST, REG_DEAD,
1570: FP_mode_reg[FIRST_STACK_REG][(int) DFmode],
1571: REG_NOTES (pop_insn));
1572:
1573: regstack->reg[regstack->top - (hard_regno - FIRST_STACK_REG)]
1574: = regstack->reg[regstack->top];
1575: regstack->top -= 1;
1576: CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (reg));
1577:
1578: return pop_insn;
1579: }
1580:
1581: /* Emit an insn before or after INSN to swap virtual register REG with the
1582: top of stack. WHEN should be `emit_insn_before' or `emit_insn_before'
1583: REGSTACK is the stack state before the swap, and is updated to reflect
1584: the swap. A swap insn is represented as a PARALLEL of two patterns:
1585: each pattern moves one reg to the other.
1586:
1587: If REG is already at the top of the stack, no insn is emitted. */
1588:
1589: static void
1590: emit_hard_swap_insn (insn, regstack, hard_regno, when)
1591: rtx insn;
1592: stack regstack;
1593: int hard_regno;
1594: rtx (*when)();
1595: {
1596: rtx gen_swapdf();
1597: rtx swap_rtx, swap_insn;
1598: int tmp, other;
1599:
1600: if (hard_regno == FIRST_STACK_REG)
1601: return;
1602:
1603: swap_rtx = gen_swapdf (FP_mode_reg[hard_regno][(int) DFmode],
1604: FP_mode_reg[FIRST_STACK_REG][(int) DFmode]);
1605: swap_insn = (*when) (swap_rtx, insn);
1606: PUT_MODE (swap_insn, VOIDmode);
1607:
1608: other = regstack->top - (hard_regno - FIRST_STACK_REG);
1609:
1610: tmp = regstack->reg[other];
1611: regstack->reg[other] = regstack->reg[regstack->top];
1612: regstack->reg[regstack->top] = tmp;
1613: }
1614:
1615: /* Emit an insn before or after INSN to swap virtual register REG with the
1616: top of stack. See comments before emit_hard_swap_insn. */
1617:
1618: static void
1619: emit_swap_insn (insn, regstack, reg, when)
1620: rtx insn;
1621: stack regstack;
1622: rtx reg;
1623: rtx (*when)();
1624: {
1625: int hard_regno;
1626:
1627: hard_regno = get_hard_regnum (regstack, reg);
1628: if (hard_regno < FIRST_STACK_REG)
1629: abort ();
1630:
1631: emit_hard_swap_insn (insn, regstack, hard_regno, when);
1632: }
1633:
1634: /* Handle a move to or from a stack register in PAT, which is in INSN.
1635: REGSTACK is the current stack. */
1636:
1637: static void
1638: move_for_stack_reg (insn, regstack, pat)
1639: rtx insn;
1640: stack regstack;
1641: rtx pat;
1642: {
1643: rtx *src = get_true_reg (&SET_SRC (pat));
1644: rtx *dest = get_true_reg (&SET_DEST (pat));
1645: rtx note;
1646:
1647: if (STACK_REG_P (*src) && STACK_REG_P (*dest))
1648: {
1649: /* Write from one stack reg to another. If SRC dies here, then
1650: just change the register mapping and delete the insn. */
1651:
1652: note = find_regno_note (insn, REG_DEAD, REGNO (*src));
1653: if (note)
1654: {
1655: int i;
1656:
1657: /* If this is a no-op move, there must not be a REG_DEAD note. */
1658: if (REGNO (*src) == REGNO (*dest))
1659: abort ();
1660:
1661: for (i = regstack->top; i >= 0; i--)
1662: if (regstack->reg[i] == REGNO (*src))
1663: break;
1664:
1665: /* The source must be live, and the dest must be dead. */
1666: if (i < 0 || get_hard_regnum (regstack, *dest) >= FIRST_STACK_REG)
1667: abort ();
1668:
1669: /* It is possible that the dest is unused after this insn.
1670: If so, just pop the src. */
1671:
1672: if (find_regno_note (insn, REG_UNUSED, REGNO (*dest)))
1673: {
1674: emit_pop_insn (insn, regstack, *src, emit_insn_after);
1675:
1676: delete_insn_for_stacker (insn);
1677: return;
1678: }
1679:
1680: regstack->reg[i] = REGNO (*dest);
1681:
1682: SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest));
1683: CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (*src));
1684:
1685: delete_insn_for_stacker (insn);
1686:
1687: return;
1688: }
1689:
1690: /* The source reg does not die. */
1691:
1692: /* If this appears to be a no-op move, delete it, or else it
1693: will confuse the machine description output patterns. But if
1694: it is REG_UNUSED, we must pop the reg now, as per-insn processing
1695: for REG_UNUSED will not work for deleted insns. */
1696:
1697: if (REGNO (*src) == REGNO (*dest))
1698: {
1699: if (find_regno_note (insn, REG_UNUSED, REGNO (*dest)))
1700: emit_pop_insn (insn, regstack, *dest, emit_insn_after);
1701:
1702: delete_insn_for_stacker (insn);
1703: return;
1704: }
1705:
1706: /* The destination ought to be dead */
1707: if (get_hard_regnum (regstack, *dest) >= FIRST_STACK_REG)
1708: abort ();
1709:
1710: replace_reg (src, get_hard_regnum (regstack, *src));
1711:
1712: regstack->reg[++regstack->top] = REGNO (*dest);
1713: SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest));
1714: replace_reg (dest, FIRST_STACK_REG);
1715: }
1716: else if (STACK_REG_P (*src))
1717: {
1718: /* Save from a stack reg to MEM, or possibly integer reg. Since
1719: only top of stack may be saved, emit an exchange first if
1720: needs be. */
1721:
1722: emit_swap_insn (insn, regstack, *src, emit_insn_before);
1723:
1724: note = find_regno_note (insn, REG_DEAD, REGNO (*src));
1725: if (note)
1726: {
1727: replace_reg (&XEXP (note, 0), FIRST_STACK_REG);
1728: regstack->top--;
1729: CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (*src));
1730: }
1731:
1732: replace_reg (src, FIRST_STACK_REG);
1733: }
1734: else if (STACK_REG_P (*dest))
1735: {
1736: /* Load from MEM, or possibly integer REG or constant, into the
1737: stack regs. The actual target is always the top of the
1738: stack. The stack mapping is changed to reflect that DEST is
1739: now at top of stack. */
1740:
1741: /* The destination ought to be dead */
1742: if (get_hard_regnum (regstack, *dest) >= FIRST_STACK_REG)
1743: abort ();
1744:
1745: if (regstack->top >= REG_STACK_SIZE)
1746: abort ();
1747:
1748: regstack->reg[++regstack->top] = REGNO (*dest);
1749: SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest));
1750: replace_reg (dest, FIRST_STACK_REG);
1751: }
1752: else
1753: abort ();
1754: }
1755:
1756: /* Handle a comparison. Special care needs to be taken to avoid
1757: causing comparisons that a 387 cannot do correctly, such as EQ.
1758:
1759: Also, a pop insn may need to be emitted. The 387 does have an
1760: `fcompp' insn that can pop two regs, but it is sometimes too expensive
1761: to do this - a `fcomp' followed by a `fstpl %st(0)' may be easier to
1762: set up. */
1763:
1764: static void
1765: compare_for_stack_reg (insn, regstack, pat)
1766: rtx insn;
1767: stack regstack;
1768: rtx pat;
1769: {
1770: rtx *src1, *src2;
1771: rtx src1_note, src2_note;
1772:
1773: src1 = get_true_reg (&XEXP (SET_SRC (pat), 0));
1774: src2 = get_true_reg (&XEXP (SET_SRC (pat), 1));
1775:
1776: /* The first argument must always be a stack reg. */
1777: /* ??? why? */
1778:
1779: if (! STACK_REG_P (*src1))
1780: abort ();
1781:
1782: /* We will fix any death note later. */
1783:
1784: src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1));
1785:
1786: if (STACK_REG_P (*src2))
1787: src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2));
1788: else
1789: src2_note = 0;
1790:
1791: emit_swap_insn (insn, regstack, *src1, emit_insn_before);
1792:
1793: replace_reg (src1, FIRST_STACK_REG);
1794:
1795: if (STACK_REG_P (*src2))
1796: replace_reg (src2, get_hard_regnum (regstack, *src2));
1797:
1798: if (src1_note)
1799: {
1800: CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (XEXP (src1_note, 0)));
1801: replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG);
1802: regstack->top--;
1803: }
1804:
1805: /* If the second operand dies, handle that. But if the operands are
1806: the same stack register, don't bother, because only one death is
1807: needed, and it was just handled. */
1808:
1809: if (src2_note
1810: && ! (STACK_REG_P (*src1)
1811: && STACK_REG_P (*src2)
1812: && REGNO (*src1) == REGNO (*src2)))
1813: {
1814: /* As a special case, two regs may die in this insn if src2 is
1815: next to top of stack and the top of stack also dies. Since
1816: we have already popped src1, "next to top of stack" is really
1817: at top (FIRST_STACK_REG) now. */
1818:
1819: if (get_hard_regnum (regstack, XEXP (src2_note, 0)) == FIRST_STACK_REG
1820: && src1_note)
1821: {
1822: CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (XEXP (src2_note, 0)));
1823: replace_reg (&XEXP (src2_note, 0), FIRST_STACK_REG + 1);
1824: regstack->top--;
1825: }
1826: else
1827: {
1828: /* The 386 can only represent death of the first operand in
1829: the case handled above. In all other cases, emit a separate
1830: pop and remove the death note from here. */
1831:
1.1.1.3 ! root 1832: link_cc0_insns (insn);
! 1833:
1.1 root 1834: remove_regno_note (insn, REG_DEAD, REGNO (XEXP (src2_note, 0)));
1835:
1836: emit_pop_insn (insn, regstack, XEXP (src2_note, 0),
1837: emit_insn_after);
1838: }
1839: }
1840: }
1841:
1842: /* Substitute new registers in PAT, which is part of INSN. REGSTACK
1843: is the current register layout. */
1844:
1845: static void
1846: subst_stack_regs_pat (insn, regstack, pat)
1847: rtx insn;
1848: stack regstack;
1849: rtx pat;
1850: {
1851: rtx *dest, *src;
1852: rtx *src1 = 0, *src2;
1853: rtx src1_note, src2_note;
1854:
1855: if (GET_CODE (pat) != SET)
1856: return;
1857:
1858: dest = get_true_reg (&SET_DEST (pat));
1859: src = get_true_reg (&SET_SRC (pat));
1860:
1861: /* See if this is a `movM' pattern, and handle elsewhere if so. */
1862:
1863: if (*dest != cc0_rtx
1864: && (STACK_REG_P (*src)
1865: || (STACK_REG_P (*dest)
1866: && (GET_CODE (*src) == REG || GET_CODE (*src) == MEM
1867: || GET_CODE (*src) == CONST_DOUBLE))))
1868: move_for_stack_reg (insn, regstack, pat);
1869: else
1870: switch (GET_CODE (SET_SRC (pat)))
1871: {
1872: case COMPARE:
1873: compare_for_stack_reg (insn, regstack, pat);
1874: break;
1875:
1876: case CALL:
1877: regstack->reg[++regstack->top] = REGNO (*dest);
1878: SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest));
1879: replace_reg (dest, FIRST_STACK_REG);
1880: break;
1881:
1882: case REG:
1883: /* This is a `tstM2' case. */
1884: if (*dest != cc0_rtx)
1885: abort ();
1886:
1887: src1 = src;
1888:
1889: /* Fall through. */
1890:
1891: case SQRT:
1892: case ABS:
1893: case NEG:
1894: /* These insns only operate on the top of the stack. DEST might
1895: be cc0_rtx if we're processing a tstM pattern. Also, it's
1896: possible that the tstM case results in a REG_DEAD note on the
1897: source. */
1898:
1899: if (src1 == 0)
1900: src1 = get_true_reg (&XEXP (SET_SRC (pat), 0));
1901:
1902: emit_swap_insn (insn, regstack, *src1, emit_insn_before);
1903:
1904: src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1));
1905:
1906: if (STACK_REG_P (*dest))
1907: replace_reg (dest, FIRST_STACK_REG);
1908:
1909: if (src1_note)
1910: {
1911: replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG);
1912: regstack->top--;
1913: CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (*src1));
1914: }
1915:
1916: replace_reg (src1, FIRST_STACK_REG);
1917:
1918: break;
1919:
1920: case MINUS:
1921: case DIV:
1922: /* On i386, reversed forms of subM3 and divM3 exist for
1923: MODE_FLOAT, so the same code that works for addM3 and mulM3
1924: can be used. */
1925: case MULT:
1926: case PLUS:
1927: /* These insns can accept the top of stack as a destination
1928: from a stack reg or mem, or can use the top of stack as a
1929: source and some other stack register (possibly top of stack)
1930: as a destination. */
1931:
1932: src1 = get_true_reg (&XEXP (SET_SRC (pat), 0));
1933: src2 = get_true_reg (&XEXP (SET_SRC (pat), 1));
1934:
1935: /* We will fix any death note later. */
1936:
1937: if (STACK_REG_P (*src1))
1938: src1_note = find_regno_note (insn, REG_DEAD, REGNO (*src1));
1939: else
1940: src1_note = 0;
1941: if (STACK_REG_P (*src2))
1942: src2_note = find_regno_note (insn, REG_DEAD, REGNO (*src2));
1943: else
1944: src2_note = 0;
1945:
1946: /* If either operand is not a stack register, then the dest
1947: must be top of stack. */
1948:
1949: if (! STACK_REG_P (*src1) || ! STACK_REG_P (*src2))
1950: emit_swap_insn (insn, regstack, *dest, emit_insn_before);
1951: else
1952: {
1953: /* Both operands are REG. If neither operand is already
1954: at the top of stack, choose to make the one that is the dest
1955: the new top of stack.
1956:
1957: ??? A later optimization here would be to look forward
1958: in the insns and see which source reg will be needed at top
1959: of stack soonest. */
1960:
1961: int src1_hard_regnum, src2_hard_regnum;
1962:
1963: src1_hard_regnum = get_hard_regnum (regstack, *src1);
1964: src2_hard_regnum = get_hard_regnum (regstack, *src2);
1965: if (src1_hard_regnum == -1 || src2_hard_regnum == -1)
1966: abort ();
1967:
1968: if (src1_hard_regnum != FIRST_STACK_REG
1969: && src2_hard_regnum != FIRST_STACK_REG)
1970: emit_swap_insn (insn, regstack, *dest, emit_insn_before);
1971: }
1972:
1973: if (STACK_REG_P (*src1))
1974: replace_reg (src1, get_hard_regnum (regstack, *src1));
1975: if (STACK_REG_P (*src2))
1976: replace_reg (src2, get_hard_regnum (regstack, *src2));
1977:
1978: if (src1_note)
1979: {
1980: /* If the register that dies is at the top of stack, then
1981: the destination is somewhere else - merely substitute it.
1982: But if the reg that dies is not at top of stack, then
1983: move the top of stack to the dead reg, as though we had
1984: done the insn and then a store-with-pop. */
1985:
1986: if (REGNO (XEXP (src1_note, 0)) == regstack->reg[regstack->top])
1987: {
1988: SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest));
1989: replace_reg (dest, get_hard_regnum (regstack, *dest));
1990: }
1991: else
1992: {
1993: int regno = get_hard_regnum (regstack, XEXP (src1_note, 0));
1994:
1995: SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest));
1996: replace_reg (dest, regno);
1997:
1998: regstack->reg[regstack->top - (regno - FIRST_STACK_REG)]
1999: = regstack->reg[regstack->top];
2000: }
2001:
2002: CLEAR_HARD_REG_BIT (regstack->reg_set,
2003: REGNO (XEXP (src1_note, 0)));
2004: replace_reg (&XEXP (src1_note, 0), FIRST_STACK_REG);
2005: regstack->top--;
2006: }
2007: else if (src2_note)
2008: {
2009: if (REGNO (XEXP (src2_note, 0)) == regstack->reg[regstack->top])
2010: {
2011: SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest));
2012: replace_reg (dest, get_hard_regnum (regstack, *dest));
2013: }
2014: else
2015: {
2016: int regno = get_hard_regnum (regstack, XEXP (src2_note, 0));
2017:
2018: SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest));
2019: replace_reg (dest, regno);
2020:
2021: regstack->reg[regstack->top - (regno - FIRST_STACK_REG)]
2022: = regstack->reg[regstack->top];
2023: }
2024:
2025: CLEAR_HARD_REG_BIT (regstack->reg_set,
2026: REGNO (XEXP (src2_note, 0)));
2027: replace_reg (&XEXP (src2_note, 0), FIRST_STACK_REG);
2028: regstack->top--;
2029: }
2030: else
2031: {
2032: SET_HARD_REG_BIT (regstack->reg_set, REGNO (*dest));
2033: replace_reg (dest, get_hard_regnum (regstack, *dest));
2034: }
2035:
2036: break;
2037:
2038: default:
2039: abort ();
2040: }
2041: }
2042:
2043: /* Substitute hard regnums for any stack regs in INSN, which has
2044: N_INPUTS inputs and N_OUTPUTS outputs. REGSTACK is the stack info
1.1.1.3 ! root 2045: before the insn, and is updated with changes made here. CONSTRAINTS is
1.1 root 2046: an array of the constraint strings used in the asm statement.
2047:
2048: OPERANDS is an array of the operands, and OPERANDS_LOC is a
2049: parallel array of where the operands were found. The output operands
1.1.1.3 ! root 2050: all precede the input operands.
1.1 root 2051:
2052: There are several requirements and assumptions about the use of
2053: stack-like regs in asm statements. These rules are enforced by
2054: record_asm_stack_regs; see comments there for details. Any
2055: asm_operands left in the RTL at this point may be assume to meet the
2056: requirements, since record_asm_stack_regs removes any problem asm. */
2057:
2058: static void
2059: subst_asm_stack_regs (insn, regstack, operands, operands_loc, constraints,
2060: n_inputs, n_outputs)
2061: rtx insn;
2062: stack regstack;
2063: rtx *operands, **operands_loc;
2064: char **constraints;
2065: int n_inputs, n_outputs;
2066: {
2067: int n_operands = n_inputs + n_outputs;
2068: int first_input = n_outputs;
2069: rtx body = PATTERN (insn);
2070:
2071: int *operand_matches = (int *) alloca (n_operands * sizeof (int *));
2072: enum reg_class *operand_class
2073: = (enum reg_class *) alloca (n_operands * sizeof (enum reg_class *));
2074:
2075: rtx *note_reg; /* Array of note contents */
2076: rtx **note_loc; /* Address of REG field of each note */
2077: enum reg_note *note_kind; /* The type of each note */
2078:
2079: rtx *clobber_reg;
2080: rtx **clobber_loc;
2081:
2082: struct stack_def temp_stack;
2083: int n_notes;
2084: int n_clobbers;
2085: rtx note;
2086: int i;
2087:
2088: /* Find out what the constraints required. If no constraint
2089: alternative matches, that is a compiler bug: we should have caught
2090: such an insn during the life analysis pass (and reload should have
2091: caught it regardless). */
2092:
2093: i = constrain_asm_operands (n_operands, operands, constraints,
2094: operand_matches, operand_class);
2095: if (i < 0)
2096: abort ();
2097:
2098: /* Strip SUBREGs here to make the following code simpler. */
2099: for (i = 0; i < n_operands; i++)
2100: if (GET_CODE (operands[i]) == SUBREG
2101: && GET_CODE (SUBREG_REG (operands[i])) == REG)
2102: {
2103: operands_loc[i] = & SUBREG_REG (operands[i]);
2104: operands[i] = SUBREG_REG (operands[i]);
2105: }
2106:
2107: /* Set up NOTE_REG, NOTE_LOC and NOTE_KIND. */
2108:
2109: for (i = 0, note = REG_NOTES (insn); note; note = XEXP (note, 1))
2110: i++;
2111:
2112: note_reg = (rtx *) alloca (i * sizeof (rtx));
2113: note_loc = (rtx **) alloca (i * sizeof (rtx *));
2114: note_kind = (enum reg_note *) alloca (i * sizeof (enum reg_note));
2115:
2116: n_notes = 0;
2117: for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
2118: {
2119: rtx reg = XEXP (note, 0);
2120: rtx *loc = & XEXP (note, 0);
2121:
2122: if (GET_CODE (reg) == SUBREG && GET_CODE (SUBREG_REG (reg)) == REG)
2123: {
2124: loc = & SUBREG_REG (reg);
2125: reg = SUBREG_REG (reg);
2126: }
2127:
2128: if (STACK_REG_P (reg)
2129: && (REG_NOTE_KIND (note) == REG_DEAD
2130: || REG_NOTE_KIND (note) == REG_UNUSED))
2131: {
2132: note_reg[n_notes] = reg;
2133: note_loc[n_notes] = loc;
2134: note_kind[n_notes] = REG_NOTE_KIND (note);
2135: n_notes++;
2136: }
2137: }
2138:
2139: /* Set up CLOBBER_REG and CLOBBER_LOC. */
2140:
2141: n_clobbers = 0;
2142:
2143: if (GET_CODE (body) == PARALLEL)
1.1.1.2 root 2144: {
2145: clobber_reg = (rtx *) alloca (XVECLEN (body, 0) * sizeof (rtx *));
2146: clobber_loc = (rtx **) alloca (XVECLEN (body, 0) * sizeof (rtx **));
1.1 root 2147:
1.1.1.2 root 2148: for (i = 0; i < XVECLEN (body, 0); i++)
2149: if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
2150: {
2151: rtx clobber = XVECEXP (body, 0, i);
2152: rtx reg = XEXP (clobber, 0);
2153: rtx *loc = & XEXP (clobber, 0);
1.1 root 2154:
1.1.1.2 root 2155: if (GET_CODE (reg) == SUBREG && GET_CODE (SUBREG_REG (reg)) == REG)
2156: {
2157: loc = & SUBREG_REG (reg);
2158: reg = SUBREG_REG (reg);
2159: }
2160:
2161: if (STACK_REG_P (reg))
2162: {
2163: clobber_reg[n_clobbers] = reg;
2164: clobber_loc[n_clobbers] = loc;
2165: n_clobbers++;
2166: }
2167: }
2168: }
1.1 root 2169:
2170: bcopy (regstack, &temp_stack, sizeof (temp_stack));
2171:
2172: /* Put the input regs into the desired place in TEMP_STACK. */
2173:
2174: for (i = first_input; i < first_input + n_inputs; i++)
2175: if (STACK_REG_P (operands[i])
2176: && reg_class_subset_p (operand_class[i], FLOAT_REGS)
2177: && operand_class[i] != FLOAT_REGS)
2178: {
2179: /* If an operand needs to be in a particular reg in
2180: FLOAT_REGS, the constraint was either 't' or 'u'. Since
2181: these constraints are for single register classes, and reload
2182: guaranteed that operand[i] is already in that class, we can
2183: just use REGNO (operands[i]) to know which actual reg this
2184: operand needs to be in. */
2185:
2186: int regno = get_hard_regnum (&temp_stack, operands[i]);
2187:
2188: if (regno < 0)
2189: abort ();
2190:
2191: if (regno != REGNO (operands[i]))
2192: {
2193: /* operands[i] is not in the right place. Find it
2194: and swap it with whatever is already in I's place.
2195: K is where operands[i] is now. J is where it should
2196: be. */
2197: int j, k, temp;
2198:
2199: k = temp_stack.top - (regno - FIRST_STACK_REG);
2200: j = (temp_stack.top
2201: - (REGNO (operands[i]) - FIRST_STACK_REG));
2202:
2203: temp = temp_stack.reg[k];
2204: temp_stack.reg[k] = temp_stack.reg[j];
2205: temp_stack.reg[j] = temp;
2206: }
2207: }
2208:
2209: /* emit insns before INSN to make sure the reg-stack is in the right
2210: order. */
2211:
2212: change_stack (insn, regstack, &temp_stack, emit_insn_before);
2213:
2214: /* Make the needed input register substitutions. Do death notes and
2215: clobbers too, because these are for inputs, not outputs. */
2216:
2217: for (i = first_input; i < first_input + n_inputs; i++)
2218: if (STACK_REG_P (operands[i]))
2219: {
2220: int regnum = get_hard_regnum (regstack, operands[i]);
2221:
2222: if (regnum < 0)
2223: abort ();
2224:
2225: replace_reg (operands_loc[i], regnum);
2226: }
2227:
2228: for (i = 0; i < n_notes; i++)
2229: if (note_kind[i] == REG_DEAD)
2230: {
2231: int regnum = get_hard_regnum (regstack, note_reg[i]);
2232:
2233: if (regnum < 0)
2234: abort ();
2235:
2236: replace_reg (note_loc[i], regnum);
2237: }
2238:
2239: for (i = 0; i < n_clobbers; i++)
2240: {
2241: /* It's OK for a CLOBBER to reference a reg that is not live.
2242: Don't try to replace it in that case. */
2243: int regnum = get_hard_regnum (regstack, clobber_reg[i]);
2244:
2245: if (regnum >= 0)
2246: {
2247: /* Sigh - clobbers always have QImode. But replace_reg knows
2248: that these regs can't be MODE_INT and will abort. Just put
2249: the right reg there without calling replace_reg. */
2250:
2251: *clobber_loc[i] = FP_mode_reg[regnum][(int) DFmode];
2252: }
2253: }
2254:
2255: /* Now remove from REGSTACK any inputs that the asm implicitly popped. */
2256:
2257: for (i = first_input; i < first_input + n_inputs; i++)
2258: if (STACK_REG_P (operands[i]))
2259: {
2260: /* An input reg is implicitly popped if it is tied to an
2261: output, or if there is a CLOBBER for it. */
2262: int j;
2263:
2264: for (j = 0; j < n_clobbers; j++)
2265: if (operands_match_p (clobber_reg[j], operands[i]))
2266: break;
2267:
2268: if (j < n_clobbers || operand_matches[i] >= 0)
2269: {
2270: /* operands[i] might not be at the top of stack. But that's OK,
2271: because all we need to do is pop the right number of regs
2272: off of the top of the reg-stack. record_asm_stack_regs
2273: guaranteed that all implicitly popped regs were grouped
2274: at the top of the reg-stack. */
2275:
2276: CLEAR_HARD_REG_BIT (regstack->reg_set,
2277: regstack->reg[regstack->top]);
2278: regstack->top--;
2279: }
2280: }
2281:
2282: /* Now add to REGSTACK any outputs that the asm implicitly pushed.
2283: Note that there isn't any need to substitute register numbers.
2284: ??? Explain why this is true. */
2285:
2286: for (i = LAST_STACK_REG; i >= FIRST_STACK_REG; i--)
2287: {
2288: /* See if there is an output for this hard reg. */
2289: int j;
2290:
2291: for (j = 0; j < n_outputs; j++)
2292: if (STACK_REG_P (operands[j]) && REGNO (operands[j]) == i)
2293: {
2294: regstack->reg[++regstack->top] = i;
2295: SET_HARD_REG_BIT (regstack->reg_set, i);
2296: break;
2297: }
2298: }
2299:
2300: /* Now emit a pop insn for any REG_UNUSED output, or any REG_DEAD
2301: input that the asm didn't implicitly pop. If the asm didn't
1.1.1.2 root 2302: implicitly pop an input reg, that reg will still be live.
1.1 root 2303:
2304: Note that we can't use find_regno_note here: the register numbers
2305: in the death notes have already been substituted. */
2306:
1.1.1.2 root 2307: for (i = 0; i < n_outputs; i++)
2308: if (STACK_REG_P (operands[i]))
2309: {
2310: int j;
2311:
2312: for (j = 0; j < n_notes; j++)
2313: if (REGNO (operands[i]) == REGNO (note_reg[j])
2314: && note_kind[j] == REG_UNUSED)
2315: {
2316: insn = emit_pop_insn (insn, regstack, operands[i],
2317: emit_insn_after);
2318: break;
2319: }
2320: }
2321:
2322: for (i = first_input; i < first_input + n_inputs; i++)
1.1 root 2323: if (STACK_REG_P (operands[i]))
2324: {
2325: int j;
2326:
2327: for (j = 0; j < n_notes; j++)
2328: if (REGNO (operands[i]) == REGNO (note_reg[j])
1.1.1.2 root 2329: && note_kind[j] == REG_DEAD
2330: && TEST_HARD_REG_BIT (regstack->reg_set, REGNO (operands[i])))
1.1 root 2331: {
2332: insn = emit_pop_insn (insn, regstack, operands[i],
2333: emit_insn_after);
2334: break;
2335: }
2336: }
2337: }
2338:
2339: /* Substitute stack hard reg numbers for stack virtual registers in
2340: INSN. Non-stack register numbers are not changed. REGSTACK is the
2341: current stack content. Insns may be emitted as needed to arrange the
2342: stack for the 387 based on the contents of the insn. */
2343:
2344: static void
2345: subst_stack_regs (insn, regstack)
2346: rtx insn;
2347: stack regstack;
2348: {
2349: register rtx *note_link, note;
2350: register int i;
2351: int n_operands;
2352:
2353: if ((GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
2354: || INSN_DELETED_P (insn))
2355: return;
2356:
2357: /* The stack should be empty at a call. */
2358:
2359: if (GET_CODE (insn) == CALL_INSN)
2360: for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
2361: if (TEST_HARD_REG_BIT (regstack->reg_set, i))
2362: abort ();
2363:
2364: /* Do the actual substitution if any stack regs are mentioned.
2365: Since we only record whether entire insn mentions stack regs, and
2366: subst_stack_regs_pat only works for patterns that contain stack regs,
2367: we must check each pattern in a parallel here. A call_value_pop could
2368: fail otherwise. */
2369:
2370: if (GET_MODE (insn) == QImode)
2371: {
2372: n_operands = asm_noperands (PATTERN (insn));
2373: if (n_operands >= 0)
2374: {
2375: /* This insn is an `asm' with operands. Decode the operands,
2376: decide how many are inputs, and do register substitution.
2377: Any REG_UNUSED notes will be handled by subst_asm_stack_regs. */
2378:
2379: rtx operands[MAX_RECOG_OPERANDS];
2380: rtx *operands_loc[MAX_RECOG_OPERANDS];
2381: rtx body = PATTERN (insn);
2382: int n_inputs, n_outputs;
2383: char **constraints
2384: = (char **) alloca (n_operands * sizeof (char *));
2385:
2386: decode_asm_operands (body, operands, operands_loc, constraints, 0);
2387: get_asm_operand_lengths (body, n_operands, &n_inputs, &n_outputs);
2388: subst_asm_stack_regs (insn, regstack, operands, operands_loc,
2389: constraints, n_inputs, n_outputs);
2390: return;
2391: }
2392:
2393: if (GET_CODE (PATTERN (insn)) == PARALLEL)
2394: for (i = 0; i < XVECLEN (PATTERN (insn) , 0); i++)
2395: {
2396: if (stack_regs_mentioned_p (XVECEXP (PATTERN (insn), 0, i)))
2397: subst_stack_regs_pat (insn, regstack,
2398: XVECEXP (PATTERN (insn), 0, i));
2399: }
2400: else
2401: subst_stack_regs_pat (insn, regstack, PATTERN (insn));
2402: }
2403:
2404: /* subst_stack_regs_pat may have deleted a no-op insn. If so, any
2405: REG_UNUSED will already have been dealt with, so just return. */
2406:
2407: if (INSN_DELETED_P (insn))
2408: return;
2409:
2410: /* If there is a REG_UNUSED note on a stack register on this insn,
2411: the indicated reg must be popped. The REG_UNUSED note is removed,
2412: since the form of the newly emitted pop insn references the reg,
2413: making it no longer `unset'. */
2414:
2415: note_link = ®_NOTES(insn);
2416: for (note = *note_link; note; note = XEXP (note, 1))
2417: if (REG_NOTE_KIND (note) == REG_UNUSED && STACK_REG_P (XEXP (note, 0)))
2418: {
2419: *note_link = XEXP (note, 1);
2420: insn = emit_pop_insn (insn, regstack, XEXP (note, 0), emit_insn_after);
2421: }
2422: else
2423: note_link = &XEXP (note, 1);
2424: }
2425:
2426: /* Change the organization of the stack so that it fits a new basic
2427: block. Some registers might have to be popped, but there can never be
2428: a register live in the new block that is not now live.
2429:
2430: Insert any needed insns before or after INSN. WHEN is emit_insn_before
2431: or emit_insn_after. OLD is the original stack layout, and NEW is
2432: the desired form. OLD is updated to reflect the code emitted, ie, it
2433: will be the same as NEW upon return.
2434:
2435: This function will not preserve block_end[]. But that information
2436: is no longer needed once this has executed. */
2437:
2438: static void
2439: change_stack (insn, old, new, when)
2440: rtx insn;
2441: stack old;
2442: stack new;
2443: rtx (*when)();
2444: {
2445: int reg;
2446:
2447: /* We will be inserting new insns "backwards", by calling emit_insn_before.
2448: If we are to insert after INSN, find the next insn, and insert before
2449: it. */
2450:
2451: if (when == emit_insn_after)
2452: insn = NEXT_INSN (insn);
2453:
2454: /* Pop any registers that are not needed in the new block. */
2455:
2456: for (reg = old->top; reg >= 0; reg--)
2457: if (! TEST_HARD_REG_BIT (new->reg_set, old->reg[reg]))
2458: emit_pop_insn (insn, old, FP_mode_reg[old->reg[reg]][(int) DFmode],
2459: emit_insn_before);
2460:
2461: if (new->top == -2)
2462: {
2463: /* If the new block has never been processed, then it can inherit
2464: the old stack order. */
2465:
2466: new->top = old->top;
2467: bcopy (old->reg, new->reg, sizeof (new->reg));
2468: }
2469: else
2470: {
2471: /* This block has been entered before, and we must match the
2472: previously selected stack order. */
2473:
2474: /* By now, the only difference should be the order of the stack,
2475: not their depth or liveliness. */
2476:
2477: GO_IF_HARD_REG_EQUAL (old->reg_set, new->reg_set, win);
2478:
2479: abort ();
2480:
2481: win:
2482:
2483: if (old->top != new->top)
2484: abort ();
2485:
2486: /* Loop here emitting swaps until the stack is correct. The
2487: worst case number of swaps emitted is N + 2, where N is the
2488: depth of the stack. In some cases, the reg at the top of
2489: stack may be correct, but swapped anyway in order to fix
2490: other regs. But since we never swap any other reg away from
2491: its correct slot, this algorithm will converge. */
2492:
2493: do
2494: {
2495: /* Swap the reg at top of stack into the position it is
2496: supposed to be in, until the correct top of stack appears. */
2497:
2498: while (old->reg[old->top] != new->reg[new->top])
2499: {
2500: for (reg = new->top; reg >= 0; reg--)
2501: if (new->reg[reg] == old->reg[old->top])
2502: break;
2503:
2504: if (reg == -1)
2505: abort ();
2506:
2507: emit_swap_insn (insn, old,
2508: FP_mode_reg[old->reg[reg]][(int) DFmode],
2509: emit_insn_before);
2510: }
2511:
2512: /* See if any regs remain incorrect. If so, bring an
2513: incorrect reg to the top of stack, and let the while loop
2514: above fix it. */
2515:
2516: for (reg = new->top; reg >= 0; reg--)
2517: if (new->reg[reg] != old->reg[reg])
2518: {
2519: emit_swap_insn (insn, old,
2520: FP_mode_reg[old->reg[reg]][(int) DFmode],
2521: emit_insn_before);
2522: break;
2523: }
2524: } while (reg >= 0);
2525:
2526: /* At this point there must be no differences. */
2527:
2528: for (reg = old->top; reg >= 0; reg--)
2529: if (old->reg[reg] != new->reg[reg])
2530: abort ();
2531: }
2532: }
2533:
2534: /* Check PAT, which points to RTL in INSN, for a LABEL_REF. If it is
2535: found, ensure that a jump from INSN to the code_label to which the
2536: label_ref points ends up with the same stack as that at the
2537: code_label. Do this by inserting insns just before the code_label to
2538: pop and rotate the stack until it is in the correct order. REGSTACK
2539: is the order of the register stack in INSN.
2540:
2541: Any code that is emitted here must not be later processed as part
2542: of any block, as it will already contain hard register numbers. */
2543:
2544: static void
2545: goto_block_pat (insn, regstack, pat)
2546: rtx insn;
2547: stack regstack;
2548: rtx pat;
2549: {
2550: rtx label;
2551: rtx new_jump, new_label, new_barrier;
2552: rtx *ref;
2553: stack label_stack;
2554: struct stack_def temp_stack;
2555: int reg;
2556:
2557: if (GET_CODE (pat) != LABEL_REF)
2558: {
2559: int i, j;
2560: char *fmt = GET_RTX_FORMAT (GET_CODE (pat));
2561:
2562: for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
2563: {
2564: if (fmt[i] == 'e')
2565: goto_block_pat (insn, regstack, XEXP (pat, i));
2566: if (fmt[i] == 'E')
2567: for (j = 0; j < XVECLEN (pat, i); j++)
2568: goto_block_pat (insn, regstack, XVECEXP (pat, i, j));
2569: }
2570: return;
2571: }
2572:
2573: label = XEXP (pat, 0);
2574: if (GET_CODE (label) != CODE_LABEL)
2575: abort ();
2576:
2577: /* First, see if in fact anything needs to be done to the stack at all. */
2578:
2579: label_stack = &block_stack_in[BLOCK_NUM (label)];
2580:
2581: if (label_stack->top == -2)
2582: {
2583: /* If the target block hasn't had a stack order selected, then
2584: we need merely ensure that no pops are needed. */
2585:
2586: for (reg = regstack->top; reg >= 0; reg--)
2587: if (! TEST_HARD_REG_BIT (label_stack->reg_set, regstack->reg[reg]))
2588: break;
2589:
2590: if (reg == -1)
2591: {
2592: /* change_stack will not emit any code in this case. */
2593:
2594: change_stack (label, regstack, label_stack, emit_insn_after);
2595: return;
2596: }
2597: }
2598: else if (label_stack->top == regstack->top)
2599: {
2600: for (reg = label_stack->top; reg >= 0; reg--)
2601: if (label_stack->reg[reg] != regstack->reg[reg])
2602: break;
2603:
2604: if (reg == -1)
2605: return;
2606: }
2607:
2608: /* At least one insn will need to be inserted before label. Insert
2609: a jump around the code we are about to emit. Emit a label for the new
2610: code, and point the original insn at this new label. We can't use
2611: redirect_jump here, because we're using fld[4] of the code labels as
2612: LABEL_REF chains, no NUSES counters. */
2613:
2614: new_jump = emit_jump_insn_before (gen_jump (label), label);
2615: record_label_references (new_jump, PATTERN (new_jump));
2616: JUMP_LABEL (new_jump) = label;
2617:
2618: new_barrier = emit_barrier_after (new_jump);
2619:
2620: new_label = gen_label_rtx ();
2621: emit_label_after (new_label, new_barrier);
2622: LABEL_REFS (new_label) = new_label;
2623:
2624: /* The old label_ref will no longer point to the code_label if now uses,
2625: so strip the label_ref from the code_label's chain of references. */
2626:
2627: for (ref = &LABEL_REFS (label); *ref != label; ref = &LABEL_NEXTREF (*ref))
2628: if (*ref == pat)
2629: break;
2630:
2631: if (*ref == label)
2632: abort ();
2633:
2634: *ref = LABEL_NEXTREF (*ref);
2635:
2636: XEXP (pat, 0) = new_label;
2637: record_label_references (insn, PATTERN (insn));
2638:
2639: if (JUMP_LABEL (insn) == label)
2640: JUMP_LABEL (insn) = new_label;
2641:
2642: /* Now emit the needed code. */
2643:
2644: temp_stack = *regstack;
2645:
2646: change_stack (new_label, &temp_stack, label_stack, emit_insn_after);
2647: }
2648:
2649: /* Traverse all basic blocks in a function, converting the register
1.1.1.2 root 2650: references in each insn from the "flat" register file that gcc uses, to
1.1 root 2651: the stack-like registers the 387 uses. */
2652:
2653: static void
2654: convert_regs ()
2655: {
2656: register int block, reg;
2657: register rtx insn, next;
2658: struct stack_def regstack;
2659:
2660: for (block = 0; block < blocks; block++)
2661: {
2662: if (block_stack_in[block].top == -2)
2663: {
2664: /* This block has not been previously encountered. Choose a
2665: default mapping for any stack regs live on entry */
2666:
2667: block_stack_in[block].top = -1;
2668:
2669: for (reg = LAST_STACK_REG; reg >= FIRST_STACK_REG; reg--)
2670: if (TEST_HARD_REG_BIT (block_stack_in[block].reg_set, reg))
2671: block_stack_in[block].reg[++block_stack_in[block].top] = reg;
2672: }
2673:
2674: /* Process all insns in this block. Keep track of `next' here,
2675: so that we don't process any insns emitted while making
2676: substitutions in INSN. */
2677:
2678: next = block_begin[block];
2679: regstack = block_stack_in[block];
2680: do
2681: {
2682: insn = next;
2683: next = NEXT_INSN (insn);
2684:
2685: /* Don't bother processing unless there is a stack reg
2686: mentioned.
2687:
2688: ??? For now, process CALL_INSNs too to make sure that the
2689: stack regs are dead after a call. Remove this eventually. */
2690:
2691: if (GET_MODE (insn) == QImode || GET_CODE (insn) == CALL_INSN)
2692: subst_stack_regs (insn, ®stack);
2693:
2694: } while (insn != block_end[block]);
2695:
2696: /* Something failed if the stack life doesn't match. */
2697:
2698: GO_IF_HARD_REG_EQUAL (regstack.reg_set, block_out_reg_set[block], win);
2699:
2700: abort ();
2701:
2702: win:
2703:
2704: /* Adjust the stack of this block on exit to match the stack of
2705: the target block, or copy stack information into stack of
2706: jump target if the target block's stack order hasn't been set
2707: yet. */
2708:
2709: if (GET_CODE (insn) == JUMP_INSN)
2710: goto_block_pat (insn, ®stack, PATTERN (insn));
2711:
2712: /* Likewise handle the case where we fall into the next block. */
2713:
2714: if ((block < blocks - 1) && block_drops_in[block+1])
2715: change_stack (insn, ®stack, &block_stack_in[block+1],
2716: emit_insn_after);
2717: }
2718:
2719: /* If the last basic block is the end of a loop, and that loop has
2720: regs live at its start, then the last basic block will have regs live
2721: at its end that need to be popped before the function returns. */
2722:
2723: for (reg = regstack.top; reg >= 0; reg--)
2724: if (! current_function_returns_real
2725: || regstack.reg[reg] != FIRST_STACK_REG)
2726: insn = emit_pop_insn (insn, ®stack,
2727: FP_mode_reg[regstack.reg[reg]][(int) DFmode],
2728: emit_insn_after);
2729: }
2730:
2731: /* Check expression PAT, which is in INSN, for label references. if
2732: one is found, print the block number of destination to FILE. */
2733:
2734: static void
2735: print_blocks (file, insn, pat)
2736: FILE *file;
2737: rtx insn, pat;
2738: {
2739: register RTX_CODE code = GET_CODE (pat);
2740: register int i;
2741: register char *fmt;
2742:
2743: if (code == LABEL_REF)
2744: {
2745: register rtx label = XEXP (pat, 0);
2746:
2747: if (GET_CODE (label) != CODE_LABEL)
2748: abort ();
2749:
2750: fprintf (file, " %d", BLOCK_NUM (label));
2751:
2752: return;
2753: }
2754:
2755: fmt = GET_RTX_FORMAT (code);
2756: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2757: {
2758: if (fmt[i] == 'e')
2759: print_blocks (file, insn, XEXP (pat, i));
2760: if (fmt[i] == 'E')
2761: {
2762: register int j;
2763: for (j = 0; j < XVECLEN (pat, i); j++)
2764: print_blocks (file, insn, XVECEXP (pat, i, j));
2765: }
2766: }
2767: }
2768:
2769: /* Write information about stack registers and stack blocks into FILE.
2770: This is part of making a debugging dump. */
2771: static void
2772: dump_stack_info (file)
2773: FILE *file;
2774: {
2775: register int block;
2776:
2777: fprintf (file, "\n%d stack blocks.\n", blocks);
2778: for (block = 0; block < blocks; block++)
2779: {
2780: register rtx head, jump, end;
2781: register int regno;
2782:
2783: fprintf (file, "\nStack block %d: first insn %d, last %d.\n",
2784: block, INSN_UID (block_begin[block]),
2785: INSN_UID (block_end[block]));
2786:
2787: head = block_begin[block];
2788:
2789: fprintf (file, "Reached from blocks: ");
2790: if (GET_CODE (head) == CODE_LABEL)
2791: for (jump = LABEL_REFS (head);
2792: jump != head;
2793: jump = LABEL_NEXTREF (jump))
2794: {
2795: register int from_block = BLOCK_NUM (CONTAINING_INSN (jump));
2796: fprintf (file, " %d", from_block);
2797: }
2798: if (block_drops_in[block])
2799: fprintf (file, " previous");
2800:
2801: fprintf (file, "\nlive stack registers on block entry: ");
2802: for (regno = FIRST_STACK_REG; regno <= LAST_STACK_REG ; regno++)
2803: {
2804: if (TEST_HARD_REG_BIT (block_stack_in[block].reg_set, regno))
2805: fprintf (file, "%d ", regno);
2806: }
2807:
2808: fprintf (file, "\nlive stack registers on block exit: ");
2809: for (regno = FIRST_STACK_REG; regno <= LAST_STACK_REG ; regno++)
2810: {
2811: if (TEST_HARD_REG_BIT (block_out_reg_set[block], regno))
2812: fprintf (file, "%d ", regno);
2813: }
2814:
2815: end = block_end[block];
2816:
2817: fprintf (file, "\nJumps to blocks: ");
2818: if (GET_CODE (end) == JUMP_INSN)
2819: print_blocks (file, end, PATTERN (end));
2820:
2821: if (block + 1 < blocks && block_drops_in[block+1])
2822: fprintf (file, " next");
2823: else if (block + 1 == blocks
2824: || (GET_CODE (end) == JUMP_INSN
2825: && GET_CODE (PATTERN (end)) == RETURN))
2826: fprintf (file, " return");
2827:
2828: fprintf (file, "\n");
2829: }
2830: }
2831: #endif /* STACK_REGS */
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