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1.1 root 1: /* Compute register class preferences for pseudo-registers.
2: Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: /* This file contains two passes of the compiler: reg_scan and reg_class.
22: It also defines some tables of information about the hardware registers
23: and a function init_reg_sets to initialize the tables. */
24:
25: #include "config.h"
26: #include "rtl.h"
27: #include "hard-reg-set.h"
28: #include "flags.h"
29: #include "basic-block.h"
30: #include "regs.h"
31: #include "insn-config.h"
32: #include "recog.h"
33:
34: #ifndef REGISTER_MOVE_COST
35: #define REGISTER_MOVE_COST(x, y) 2
36: #endif
37:
38: #ifndef MEMORY_MOVE_COST
39: #define MEMORY_MOVE_COST(x) 2
40: #endif
41:
42: /* Register tables used by many passes. */
43:
44: /* Indexed by hard register number, contains 1 for registers
45: that are fixed use (stack pointer, pc, frame pointer, etc.).
46: These are the registers that cannot be used to allocate
47: a pseudo reg whose life does not cross calls. */
48:
49: char fixed_regs[FIRST_PSEUDO_REGISTER];
50:
51: /* Same info as a HARD_REG_SET. */
52:
53: HARD_REG_SET fixed_reg_set;
54:
55: /* Data for initializing the above. */
56:
57: static char initial_fixed_regs[] = FIXED_REGISTERS;
58:
59: /* Indexed by hard register number, contains 1 for registers
60: that are fixed use or are clobbered by function calls.
61: These are the registers that cannot be used to allocate
62: a pseudo reg whose life crosses calls. */
63:
64: char call_used_regs[FIRST_PSEUDO_REGISTER];
65:
66: /* Same info as a HARD_REG_SET. */
67:
68: HARD_REG_SET call_used_reg_set;
69:
70: /* Data for initializing the above. */
71:
72: static char initial_call_used_regs[] = CALL_USED_REGISTERS;
73:
74: /* Indexed by hard register number, contains 1 for registers that are
75: fixed use -- i.e. in fixed_regs -- or a function value return register
76: or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
77: registers that cannot hold quantities across calls even if we are
78: willing to save and restore them. */
79:
80: char call_fixed_regs[FIRST_PSEUDO_REGISTER];
81:
82: /* The same info as a HARD_REG_SET. */
83:
84: HARD_REG_SET call_fixed_reg_set;
85:
86: /* Number of non-fixed registers. */
87:
88: int n_non_fixed_regs;
89:
90: /* Indexed by hard register number, contains 1 for registers
91: that are being used for global register decls.
92: These must be exempt from ordinary flow analysis
93: and are also considered fixed. */
94:
95: char global_regs[FIRST_PSEUDO_REGISTER];
96:
97: /* Table of register numbers in the order in which to try to use them. */
98: #ifdef REG_ALLOC_ORDER
99: int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
100: #endif
101:
102: /* For each reg class, a HARD_REG_SET saying which registers are in it. */
103:
104: HARD_REG_SET reg_class_contents[] = REG_CLASS_CONTENTS;
105:
106: /* For each reg class, number of regs it contains. */
107:
108: int reg_class_size[N_REG_CLASSES];
109:
110: /* For each reg class, table listing all the containing classes. */
111:
112: enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
113:
114: /* For each reg class, table listing all the classes contained in it. */
115:
116: enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
117:
118: /* For each pair of reg classes,
119: a largest reg class contained in their union. */
120:
121: enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
122:
123: /* For each pair of reg classes,
124: the smallest reg class containing their union. */
125:
126: enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
127:
128: /* Array containing all of the register names */
129:
130: char *reg_names[] = REGISTER_NAMES;
131:
132:
133: /* Indexed by n, gives number of times (REG n) is set or clobbered.
134: This information remains valid for the rest of the compilation
135: of the current function; it is used to control register allocation.
136:
137: This information applies to both hard registers and pseudo registers,
138: unlike much of the information above. */
139:
140: short *reg_n_sets;
141:
142: /* Function called only once to initialize the above data on reg usage.
143: Once this is done, various switches may override. */
144:
145: void
146: init_reg_sets ()
147: {
148: register int i, j;
149:
150: bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
151: bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
152: bzero (global_regs, sizeof global_regs);
153:
154: /* Compute number of hard regs in each class. */
155:
156: bzero (reg_class_size, sizeof reg_class_size);
157: for (i = 0; i < N_REG_CLASSES; i++)
158: for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
159: if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
160: reg_class_size[i]++;
161:
162: /* Initialize the table of subunions.
163: reg_class_subunion[I][J] gets the largest-numbered reg-class
164: that is contained in the union of classes I and J. */
165:
166: for (i = 0; i < N_REG_CLASSES; i++)
167: {
168: for (j = 0; j < N_REG_CLASSES; j++)
169: {
170: #ifdef HARD_REG_SET
171: register /* Declare it register if it's a scalar. */
172: #endif
173: HARD_REG_SET c;
174: register int k;
175:
176: COPY_HARD_REG_SET (c, reg_class_contents[i]);
177: IOR_HARD_REG_SET (c, reg_class_contents[j]);
178: for (k = 0; k < N_REG_CLASSES; k++)
179: {
180: GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
181: subclass1);
182: continue;
183:
184: subclass1:
185: /* keep the largest subclass */ /* SPEE 900308 */
186: GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
187: reg_class_contents[(int) reg_class_subunion[i][j]],
188: subclass2);
189: reg_class_subunion[i][j] = (enum reg_class) k;
190: subclass2:
191: ;
192: }
193: }
194: }
195:
196: /* Initialize the table of superunions.
197: reg_class_superunion[I][J] gets the smallest-numbered reg-class
198: containing the union of classes I and J. */
199:
200: for (i = 0; i < N_REG_CLASSES; i++)
201: {
202: for (j = 0; j < N_REG_CLASSES; j++)
203: {
204: #ifdef HARD_REG_SET
205: register /* Declare it register if it's a scalar. */
206: #endif
207: HARD_REG_SET c;
208: register int k;
209:
210: COPY_HARD_REG_SET (c, reg_class_contents[i]);
211: IOR_HARD_REG_SET (c, reg_class_contents[j]);
212: for (k = 0; k < N_REG_CLASSES; k++)
213: GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
214:
215: superclass:
216: reg_class_superunion[i][j] = (enum reg_class) k;
217: }
218: }
219:
220: /* Initialize the tables of subclasses and superclasses of each reg class.
221: First clear the whole table, then add the elements as they are found. */
222:
223: for (i = 0; i < N_REG_CLASSES; i++)
224: {
225: for (j = 0; j < N_REG_CLASSES; j++)
226: {
227: reg_class_superclasses[i][j] = LIM_REG_CLASSES;
228: reg_class_subclasses[i][j] = LIM_REG_CLASSES;
229: }
230: }
231:
232: for (i = 0; i < N_REG_CLASSES; i++)
233: {
234: if (i == (int) NO_REGS)
235: continue;
236:
237: for (j = i + 1; j < N_REG_CLASSES; j++)
238: {
239: enum reg_class *p;
240:
241: GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
242: subclass);
243: continue;
244: subclass:
245: /* Reg class I is a subclass of J.
246: Add J to the table of superclasses of I. */
247: p = ®_class_superclasses[i][0];
248: while (*p != LIM_REG_CLASSES) p++;
249: *p = (enum reg_class) j;
250: /* Add I to the table of superclasses of J. */
251: p = ®_class_subclasses[j][0];
252: while (*p != LIM_REG_CLASSES) p++;
253: *p = (enum reg_class) i;
254: }
255: }
256: }
257:
258: /* After switches have been processed, which perhaps alter
259: `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
260:
261: void
262: init_reg_sets_1 ()
263: {
264: register int i;
265:
266: /* This macro allows the fixed or call-used registers
267: to depend on target flags. */
268:
269: #ifdef CONDITIONAL_REGISTER_USAGE
270: CONDITIONAL_REGISTER_USAGE;
271: #endif
272:
273: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
274: if (global_regs[i])
275: {
276: if (call_used_regs[i] && ! fixed_regs[i])
277: warning ("call-clobbered register used for global register variable");
278: fixed_regs[i] = 1;
279: /* Prevent saving/restoring of this reg. */
280: call_used_regs[i] = 1;
281: }
282:
283: /* Initialize "constant" tables. */
284:
285: CLEAR_HARD_REG_SET (fixed_reg_set);
286: CLEAR_HARD_REG_SET (call_used_reg_set);
287: CLEAR_HARD_REG_SET (call_fixed_reg_set);
288:
289: bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
290: #ifdef STRUCT_VALUE_REGNUM
291: call_fixed_regs[STRUCT_VALUE_REGNUM] = 1;
292: #endif
293: #ifdef STATIC_CHAIN_REGNUM
294: call_fixed_regs[STATIC_CHAIN_REGNUM] = 1;
295: #endif
296:
297: n_non_fixed_regs = 0;
298:
299: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
300: {
301: if (FUNCTION_VALUE_REGNO_P (i))
302: call_fixed_regs[i] = 1;
303: if (fixed_regs[i])
304: SET_HARD_REG_BIT (fixed_reg_set, i);
305: else
306: n_non_fixed_regs++;
307:
308: if (call_used_regs[i])
309: SET_HARD_REG_BIT (call_used_reg_set, i);
310: if (call_fixed_regs[i])
311: SET_HARD_REG_BIT (call_fixed_reg_set, i);
312: }
313: }
314:
315: /* Specify the usage characteristics of the register named NAME.
316: It should be a fixed register if FIXED and a
317: call-used register if CALL_USED. */
318:
319: void
320: fix_register (name, fixed, call_used)
321: char *name;
322: int fixed, call_used;
323: {
324: int i;
325:
326: /* Decode the name and update the primary form of
327: the register info. */
328:
329: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
330: if (reg_names[i][0] && ! strcmp (reg_names[i], name))
331: {
332: fixed_regs[i] = fixed;
333: call_used_regs[i] = call_used;
334: break;
335: }
336:
337: if (i == FIRST_PSEUDO_REGISTER)
338: {
339: warning ("unknown register name: %s", name);
340: return;
341: }
342: }
343:
344: /* Now the data and code for the `regclass' pass, which happens
345: just before local-alloc. */
346:
347: /* savings[R].savings[CL] is twice the amount saved by putting register R
348: in class CL. This data is used within `regclass' and freed
349: when it is finished. */
350:
351: struct savings
352: {
353: short savings[N_REG_CLASSES];
354: short memcost;
355: short nrefs;
356: };
357:
358: static struct savings *savings;
359:
360: /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
361: This is available after `regclass' is run. */
362:
363: static char *prefclass;
364:
365: /* preferred_or_nothing[R] is nonzero if we should put pseudo number R
366: in memory if we can't get its perferred class.
367: This is available after `regclass' is run. */
368:
369: static char *preferred_or_nothing;
370:
371: /* Record the depth of loops that we are in, 1 for no loops. */
372:
373: static int loop_depth;
374:
375: void reg_class_record ();
376: void record_address_regs ();
377:
378:
379: /* Return the reg_class in which pseudo reg number REGNO is best allocated.
380: This function is sometimes called before the info has been computed.
381: When that happens, just return GENERAL_REGS, which is innocuous. */
382:
383: enum reg_class
384: reg_preferred_class (regno)
385: int regno;
386: {
387: if (prefclass == 0)
388: return GENERAL_REGS;
389: return (enum reg_class) prefclass[regno];
390: }
391:
392: int
393: reg_preferred_or_nothing (regno)
394: {
395: if (prefclass == 0)
396: return 0;
397: return preferred_or_nothing[regno];
398: }
399:
400: /* This prevents dump_flow_info from losing if called
401: before regclass is run. */
402:
403: void
404: regclass_init ()
405: {
406: prefclass = 0;
407: }
408:
409: /* This is a pass of the compiler that scans all instructions
410: and calculates the preferred class for each pseudo-register.
411: This information can be accessed later by calling `reg_preferred_class'.
412: This pass comes just before local register allocation. */
413:
414: void
415: regclass (f, nregs)
416: rtx f;
417: int nregs;
418: {
419: #ifdef REGISTER_CONSTRAINTS
420: register rtx insn;
421: register int i;
422:
423: init_recog ();
424:
425: /* Zero out our accumulation of the cost of each class for each reg. */
426:
427: savings = (struct savings *) alloca (nregs * sizeof (struct savings));
428: bzero (savings, nregs * sizeof (struct savings));
429:
430: loop_depth = 1;
431:
432: /* Scan the instructions and record each time it would
433: save code to put a certain register in a certain class. */
434:
435: for (insn = f; insn; insn = NEXT_INSN (insn))
436: {
437: if (GET_CODE (insn) == NOTE
438: && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
439: loop_depth++;
440: else if (GET_CODE (insn) == NOTE
441: && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
442: loop_depth--;
443: else if ((GET_CODE (insn) == INSN
444: && GET_CODE (PATTERN (insn)) != USE
445: && GET_CODE (PATTERN (insn)) != CLOBBER
446: && GET_CODE (PATTERN (insn)) != ASM_INPUT)
447: || (GET_CODE (insn) == JUMP_INSN
448: && GET_CODE (PATTERN (insn)) != ADDR_VEC
449: && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
450: || GET_CODE (insn) == CALL_INSN)
451: {
452: if (GET_CODE (insn) == INSN && asm_noperands (PATTERN (insn)) >= 0)
453: {
454: int noperands = asm_noperands (PATTERN (insn));
455: /* We don't use alloca because alloca would not free
456: any of the space until this function returns. */
457: rtx *operands = (rtx *) oballoc (noperands * sizeof (rtx));
458: char **constraints
459: = (char **) oballoc (noperands * sizeof (char *));
460:
461: decode_asm_operands (PATTERN (insn), operands, 0, constraints, 0);
462:
463: for (i = noperands - 1; i >= 0; i--)
464: reg_class_record (operands[i], i, constraints);
465:
466: obfree (operands);
467: }
468: else
469: {
470: int insn_code_number = recog_memoized (insn);
471: rtx set = single_set (insn);
472:
473: insn_extract (insn);
474:
475: for (i = insn_n_operands[insn_code_number] - 1; i >= 0; i--)
476: reg_class_record (recog_operand[i], i,
477: insn_operand_constraint[insn_code_number]);
478:
479: /* If this insn loads a parameter from its stack slot,
480: then it represents a savings, rather than a cost,
481: if the parameter is stored in memory. Record this fact. */
482: if (set != 0 && GET_CODE (SET_DEST (set)) == REG
483: && GET_CODE (SET_SRC (set)) == MEM)
484: {
485: rtx note = find_reg_note (insn, REG_EQUIV, 0);
486: if (note != 0 && GET_CODE (XEXP (note, 0)) == MEM)
487: savings[REGNO (SET_DEST (set))].memcost
488: -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)))
489: * loop_depth);
490: }
491:
492: /* Improve handling of two-address insns such as
493: (set X (ashift CONST Y)) where CONST must be made to match X.
494: Change it into two insns: (set X CONST) (set X (ashift X Y)).
495: If we left this for reloading, it would probably get three
496: insns because X and Y might go in the same place.
497: This prevents X and Y from receiving the same hard reg.
498:
499: We can only do this if the modes of operands 0 and 1 (which
500: might not be the same) are tieable. */
501:
502: if (optimize
503: && insn_n_operands[insn_code_number] >= 3
504: && insn_operand_constraint[insn_code_number][1][0] == '0'
505: && insn_operand_constraint[insn_code_number][1][1] == 0
506: && CONSTANT_P (recog_operand[1])
507: && ! rtx_equal_p (recog_operand[0], recog_operand[1])
508: && ! rtx_equal_p (recog_operand[0], recog_operand[2])
509: && GET_CODE (recog_operand[0]) == REG
510: && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
511: insn_operand_mode[insn_code_number][1]))
512: {
513: rtx previnsn = prev_real_insn (insn);
514: rtx dest
515: = gen_lowpart (insn_operand_mode[insn_code_number][1],
516: recog_operand[0]);
517: rtx newinsn
518: = emit_insn_before (gen_move_insn (dest, recog_operand[1]),
519: insn);
520:
521: /* If this insn was the start of a basic block,
522: include the new insn in that block. */
523: if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
524: {
525: int b;
526: for (b = 0; b < n_basic_blocks; b++)
527: if (insn == basic_block_head[b])
528: basic_block_head[b] = newinsn;
529: }
530:
531: /* This makes one more setting of new insns's destination. */
532: reg_n_sets[REGNO (recog_operand[0])]++;
533:
534: *recog_operand_loc[1] = recog_operand[0];
535: for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
536: if (recog_dup_num[i] == 1)
537: *recog_dup_loc[i] = recog_operand[0];
538: }
539: }
540: }
541: }
542:
543: /* Now for each register look at how desirable each class is
544: and find which class is preferred. Store that in `prefclass[REGNO]'. */
545:
546: prefclass = (char *) oballoc (nregs);
547:
548: preferred_or_nothing = (char *) oballoc (nregs);
549:
550: for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
551: {
552: register int best_savings = 0;
553: enum reg_class best = ALL_REGS;
554:
555: /* This is an enum reg_class, but we call it an int
556: to save lots of casts. */
557: register int class;
558: register struct savings *p = &savings[i];
559:
560: for (class = (int) ALL_REGS - 1; class > 0; class--)
561: {
562: if (p->savings[class] > best_savings)
563: {
564: best_savings = p->savings[class];
565: best = (enum reg_class) class;
566: }
567: else if (p->savings[class] == best_savings)
568: {
569: best = reg_class_subunion[(int)best][class];
570: }
571: }
572:
573: #if 0
574: /* Note that best_savings is twice number of places something
575: is saved. */
576: if ((best_savings - p->savings[(int) GENERAL_REGS]) * 5 < reg_n_refs[i])
577: prefclass[i] = (int) GENERAL_REGS;
578: else
579: prefclass[i] = (int) best;
580: #else
581: /* We cast to (int) because (char) hits bugs in some compilers. */
582: prefclass[i] = (int) best;
583: #endif
584:
585: /* reg_n_refs + p->memcost measures the cost of putting in memory.
586: If a GENERAL_REG is no better, don't even try for one.
587: Since savings and memcost are 2 * number of refs,
588: this effectively counts each memory operand not needing reloading
589: as costing 1/2 of a reload insn. */
590: if (reg_n_refs != 0)
591: preferred_or_nothing[i]
592: = ((best_savings - p->savings[(int) GENERAL_REGS])
593: >= p->nrefs + p->memcost);
594: }
595: #endif /* REGISTER_CONSTRAINTS */
596: }
597:
598: #ifdef REGISTER_CONSTRAINTS
599:
600: /* Scan an operand OP for register class preferences.
601: OPNO is the operand number, and CONSTRAINTS is the constraint
602: vector for the insn.
603:
604: Record the preferred register classes from the constraint for OP
605: if OP is a register. If OP is a memory reference, record suitable
606: preferences for registers used in the address. */
607:
608: void
609: reg_class_record (op, opno, constraints)
610: rtx op;
611: int opno;
612: char **constraints;
613: {
614: char *constraint = constraints[opno];
615: register char *p;
616: register enum reg_class class = NO_REGS;
617: char *next = 0;
618: int memok = 0;
619: int double_cost = 0;
620:
621: if (op == 0)
622: return;
623:
624: while (1)
625: {
626: if (GET_CODE (op) == SUBREG)
627: op = SUBREG_REG (op);
628: else break;
629: }
630:
631: /* Memory reference: scan the address. */
632:
633: if (GET_CODE (op) == MEM)
634: record_address_regs (XEXP (op, 0), 2, 0);
635:
636: if (GET_CODE (op) != REG)
637: {
638: /* If the constraint says the operand is supposed to BE an address,
639: scan it as one. */
640:
641: if (constraint != 0 && constraint[0] == 'p')
642: record_address_regs (op, 2, 0);
643: return;
644: }
645:
646: /* Operand is a register: examine the constraint for specified classes. */
647:
648: for (p = constraint; *p || next; p++)
649: {
650: enum reg_class new_class = NO_REGS;
651:
652: if (*p == 0)
653: {
654: p = next;
655: next = 0;
656: }
657: switch (*p)
658: {
659: case '=':
660: case '?':
661: case '#':
662: case '&':
663: case '!':
664: case '%':
665: case 'E':
666: case 'F':
667: case 'G':
668: case 'H':
669: case 'i':
670: case 'n':
671: case 's':
672: case 'p':
673: case ',':
674: case 'I':
675: case 'J':
676: case 'K':
677: case 'L':
678: case 'M':
679: case 'N':
680: case 'O':
681: case 'P':
682: #ifdef EXTRA_CONSTRAINT
683: case 'Q':
684: case 'R':
685: case 'S':
686: case 'T':
687: case 'U':
688: #endif
689: case 'V':
690: case 'X':
691: break;
692:
693: case '+':
694: /* An input-output operand is twice as costly if it loses. */
695: double_cost = 1;
696: break;
697:
698: case 'm':
699: case 'o':
700: memok = 1;
701: break;
702:
703: /* * means ignore following letter
704: when choosing register preferences. */
705: case '*':
706: p++;
707: break;
708:
709: case 'g':
710: case 'r':
711: new_class = GENERAL_REGS;
712: break;
713:
714: case '0':
715: case '1':
716: case '2':
717: case '3':
718: case '4':
719: /* If constraint says "match another operand",
720: use that operand's constraint to choose preferences. */
721: if (*p - '0' < opno)
722: {
723: opno = *p - '0';
724: next = constraints[opno];
725: }
726: break;
727:
728: default:
729: new_class = REG_CLASS_FROM_LETTER (*p);
730: break;
731: }
732:
733: /* If this object can fit into the class requested, compute the subunion
734: of the requested class and classes found so far. */
735: if (CLASS_MAX_NREGS (new_class, GET_MODE (op))
736: <= reg_class_size[(int) new_class])
737: class = reg_class_subunion[(int) class][(int) new_class];
738: }
739:
740: {
741: register int i;
742: register struct savings *pp;
743: register enum reg_class class1;
744: int cost = 2 * (1 + double_cost) * loop_depth;
745: pp = &savings[REGNO (op)];
746:
747: /* Increment the savings for this reg
748: for each class contained in the one the constraint asks for. */
749:
750: if (class != NO_REGS && class != ALL_REGS)
751: {
752: int extracost;
753:
754: pp->savings[(int) class] += cost;
755: for (i = 0; ; i++)
756: {
757: class1 = reg_class_subclasses[(int)class][i];
758: if (class1 == LIM_REG_CLASSES)
759: break;
760: pp->savings[(int) class1] += cost;
761: }
762: /* If it's slow to move data between this class and GENERAL_REGS,
763: record that fact. */
764: extracost = (REGISTER_MOVE_COST (class, GENERAL_REGS) - 2) * loop_depth;
765: if (extracost > 0)
766: {
767: /* Check that this class and GENERAL_REGS don't overlap.
768: REGISTER_MOVE_COST is meaningless if there is overlap. */
769: HARD_REG_SET temp;
770: COMPL_HARD_REG_SET (temp, reg_class_contents[(int) class]);
771: GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) GENERAL_REGS],
772: temp, label1);
773: /* Overlap. */
774: goto label2;
775:
776: label1: /* No overlap. */
777: /* Charge this extra cost to GENERAL_REGS
778: and all its subclasses (none of which overlap this class). */
779: extracost = extracost * cost / (2 * loop_depth);
780: pp->savings[(int) GENERAL_REGS] -= extracost;
781: for (i = 0; ; i++)
782: {
783: class1 = reg_class_subclasses[(int)GENERAL_REGS][i];
784: if (class1 == LIM_REG_CLASSES)
785: break;
786: pp->savings[(int) class1] -= extracost;
787: }
788:
789: label2: ;
790: }
791: }
792:
793: if (! memok)
794: pp->memcost += (MEMORY_MOVE_COST (GET_MODE (op)) * (1 + double_cost)
795: - 1) * loop_depth;
796: pp->nrefs += loop_depth;
797: }
798: }
799:
800: /* Record the pseudo registers we must reload into hard registers
801: in a subexpression of a memory address, X.
802: BCOST is the cost if X is a register and it fails to be in BASE_REG_CLASS.
803: ICOST is the cost if it fails to be in INDEX_REG_CLASS. */
804:
805: void
806: record_address_regs (x, bcost, icost)
807: rtx x;
808: int bcost, icost;
809: {
810: register enum rtx_code code = GET_CODE (x);
811:
812: switch (code)
813: {
814: case CONST_INT:
815: case CONST:
816: case CC0:
817: case PC:
818: case SYMBOL_REF:
819: case LABEL_REF:
820: return;
821:
822: case PLUS:
823: /* When we have an address that is a sum,
824: we must determine whether registers are "base" or "index" regs.
825: If there is a sum of two registers, we must choose one to be
826: the "base". Luckily, we can use the REGNO_POINTER_FLAG
827: to make a good choice most of the time. */
828: {
829: rtx arg0 = XEXP (x, 0);
830: rtx arg1 = XEXP (x, 1);
831: register enum rtx_code code0 = GET_CODE (arg0);
832: register enum rtx_code code1 = GET_CODE (arg1);
833: int icost0 = 0;
834: int icost1 = 0;
835: int suppress1 = 0;
836: int suppress0 = 0;
837:
838: /* Look inside subregs. */
839: while (code0 == SUBREG)
840: arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
841: while (code1 == SUBREG)
842: arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
843:
844: if (code0 == MULT || code1 == MEM)
845: icost0 = 2;
846: else if (code1 == MULT || code0 == MEM)
847: icost1 = 2;
848: else if (code0 == CONST_INT)
849: suppress0 = 1;
850: else if (code1 == CONST_INT)
851: suppress1 = 1;
852: else if (code0 == REG && code1 == REG)
853: {
854: if (REGNO_POINTER_FLAG (REGNO (arg0)))
855: icost1 = 2;
856: else if (REGNO_POINTER_FLAG (REGNO (arg1)))
857: icost0 = 2;
858: else
859: icost0 = icost1 = 1;
860: }
861: else if (code0 == REG)
862: {
863: if (code1 == PLUS
864: && ! REGNO_POINTER_FLAG (REGNO (arg0)))
865: icost0 = 2;
866: else
867: REGNO_POINTER_FLAG (REGNO (arg0)) = 1;
868: }
869: else if (code1 == REG)
870: {
871: if (code0 == PLUS
872: && ! REGNO_POINTER_FLAG (REGNO (arg1)))
873: icost1 = 2;
874: else
875: REGNO_POINTER_FLAG (REGNO (arg1)) = 1;
876: }
877:
878: /* ICOST0 determines whether we are treating operand 0
879: as a base register or as an index register.
880: SUPPRESS0 nonzero means it isn't a register at all.
881: ICOST1 and SUPPRESS1 are likewise for operand 1. */
882:
883: if (! suppress0)
884: record_address_regs (arg0, 2 - icost0, icost0);
885: if (! suppress1)
886: record_address_regs (arg1, 2 - icost1, icost1);
887: }
888: break;
889:
890: case POST_INC:
891: case PRE_INC:
892: case POST_DEC:
893: case PRE_DEC:
894: /* Double the importance of a pseudo register that is incremented
895: or decremented, since it would take two extra insns
896: if it ends up in the wrong place. */
897: record_address_regs (XEXP (x, 0), 2 * bcost, 2 * icost);
898: break;
899:
900: case REG:
901: {
902: register struct savings *pp;
903: register enum reg_class class, class1;
904: pp = &savings[REGNO (x)];
905: pp->nrefs += loop_depth;
906:
907: /* We have an address (or part of one) that is just one register. */
908:
909: /* Record BCOST worth of savings for classes contained
910: in BASE_REG_CLASS. */
911:
912: class = BASE_REG_CLASS;
913: if (class != NO_REGS && class != ALL_REGS)
914: {
915: register int i;
916: pp->savings[(int) class] += bcost * loop_depth;
917: for (i = 0; ; i++)
918: {
919: class1 = reg_class_subclasses[(int)class][i];
920: if (class1 == LIM_REG_CLASSES)
921: break;
922: pp->savings[(int) class1] += bcost * loop_depth;
923: }
924: }
925:
926: /* Record ICOST worth of savings for classes contained
927: in INDEX_REG_CLASS. */
928:
929: class = INDEX_REG_CLASS;
930: if (icost != 0 && class != NO_REGS && class != ALL_REGS)
931: {
932: register int i;
933: pp->savings[(int) class] += icost * loop_depth;
934: for (i = 0; ; i++)
935: {
936: class1 = reg_class_subclasses[(int)class][i];
937: if (class1 == LIM_REG_CLASSES)
938: break;
939: pp->savings[(int) class1] += icost * loop_depth;
940: }
941: }
942: }
943: break;
944:
945: default:
946: {
947: register char *fmt = GET_RTX_FORMAT (code);
948: register int i;
949: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
950: if (fmt[i] == 'e')
951: record_address_regs (XEXP (x, i), bcost, icost);
952: }
953: }
954: }
955: #endif /* REGISTER_CONSTRAINTS */
956:
957: /* This is the `regscan' pass of the compiler, run just before cse
958: and again just before loop.
959:
960: It finds the first and last use of each pseudo-register
961: and records them in the vectors regno_first_uid, regno_last_uid
962: and counts the number of sets in the vector reg_n_sets.
963:
964: REPEAT is nonzero the second time this is called. */
965:
966: /* Indexed by pseudo register number, gives uid of first insn using the reg
967: (as of the time reg_scan is called). */
968:
969: short *regno_first_uid;
970:
971: /* Indexed by pseudo register number, gives uid of last insn using the reg
972: (as of the time reg_scan is called). */
973:
974: short *regno_last_uid;
975:
976: /* Record the number of registers we used when we allocated the above two
977: tables. If we are called again with more than this, we must re-allocate
978: the tables. */
979:
980: static int highest_regno_in_uid_map;
981:
982: /* Maximum number of parallel sets and clobbers in any insn in this fn.
983: Always at least 3, since the combiner could put that many togetherm
984: and we want this to remain correct for all the remaining passes. */
985:
986: int max_parallel;
987:
988: void reg_scan_mark_refs ();
989:
990: void
991: reg_scan (f, nregs, repeat)
992: rtx f;
993: int nregs;
994: int repeat;
995: {
996: register rtx insn;
997:
998: if (!repeat || nregs > highest_regno_in_uid_map)
999: {
1000: /* Leave some spare space in case more regs are allocated. */
1001: highest_regno_in_uid_map = nregs + nregs / 20;
1002: regno_first_uid
1003: = (short *) oballoc (highest_regno_in_uid_map * sizeof (short));
1004: regno_last_uid
1005: = (short *) oballoc (highest_regno_in_uid_map * sizeof (short));
1006: reg_n_sets
1007: = (short *) oballoc (highest_regno_in_uid_map * sizeof (short));
1008: }
1009:
1010: bzero (regno_first_uid, highest_regno_in_uid_map * sizeof (short));
1011: bzero (regno_last_uid, highest_regno_in_uid_map * sizeof (short));
1012: bzero (reg_n_sets, highest_regno_in_uid_map * sizeof (short));
1013:
1014: max_parallel = 3;
1015:
1016: for (insn = f; insn; insn = NEXT_INSN (insn))
1017: if (GET_CODE (insn) == INSN
1018: || GET_CODE (insn) == CALL_INSN
1019: || GET_CODE (insn) == JUMP_INSN)
1020: {
1021: if (GET_CODE (PATTERN (insn)) == PARALLEL
1022: && XVECLEN (PATTERN (insn), 0) > max_parallel)
1023: max_parallel = XVECLEN (PATTERN (insn), 0);
1024: reg_scan_mark_refs (PATTERN (insn), INSN_UID (insn));
1025: }
1026: }
1027:
1028: void
1029: reg_scan_mark_refs (x, uid)
1030: rtx x;
1031: int uid;
1032: {
1033: register enum rtx_code code = GET_CODE (x);
1034: register rtx dest;
1035:
1036: switch (code)
1037: {
1038: case CONST_INT:
1039: case CONST:
1040: case CONST_DOUBLE:
1041: case CC0:
1042: case PC:
1043: case SYMBOL_REF:
1044: case LABEL_REF:
1045: case ADDR_VEC:
1046: case ADDR_DIFF_VEC:
1047: return;
1048:
1049: case REG:
1050: {
1051: register int regno = REGNO (x);
1052:
1053: regno_last_uid[regno] = uid;
1054: if (regno_first_uid[regno] == 0)
1055: regno_first_uid[regno] = uid;
1056: }
1057: break;
1058:
1059: case SET:
1060: /* Count a set of the destination if it is a register. */
1061: for (dest = SET_DEST (x);
1062: GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
1063: || GET_CODE (dest) == ZERO_EXTEND;
1064: dest = XEXP (dest, 0))
1065: ;
1066:
1067: if (GET_CODE (dest) == REG)
1068: reg_n_sets[REGNO (dest)]++;
1069:
1070: /* ... fall through ... */
1071:
1072: default:
1073: {
1074: register char *fmt = GET_RTX_FORMAT (code);
1075: register int i;
1076: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1077: {
1078: if (fmt[i] == 'e')
1079: reg_scan_mark_refs (XEXP (x, i), uid);
1080: else if (fmt[i] == 'E' && XVEC (x, i) != 0)
1081: {
1082: register int j;
1083: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1084: reg_scan_mark_refs (XVECEXP (x, i, j), uid);
1085: }
1086: }
1087: }
1088: }
1089: }
1090:
1091: /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
1092: is also in C2. */
1093:
1094: int
1095: reg_class_subset_p (c1, c2)
1096: register enum reg_class c1;
1097: register enum reg_class c2;
1098: {
1099: if (c1 == c2) return 1;
1100:
1101: if (c2 == ALL_REGS)
1102: win:
1103: return 1;
1104: GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
1105: reg_class_contents[(int)c2],
1106: win);
1107: return 0;
1108: }
1109:
1110: /* Return nonzero if there is a register that is in both C1 and C2. */
1111:
1112: int
1113: reg_classes_intersect_p (c1, c2)
1114: register enum reg_class c1;
1115: register enum reg_class c2;
1116: {
1117: #ifdef HARD_REG_SET
1118: register
1119: #endif
1120: HARD_REG_SET c;
1121:
1122: if (c1 == c2) return 1;
1123:
1124: if (c1 == ALL_REGS || c2 == ALL_REGS)
1125: return 1;
1126:
1127: COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1128: AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1129:
1130: GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
1131: return 1;
1132:
1133: lose:
1134: return 0;
1135: }
1136:
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