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1.1 root 1: /* Compute register class preferences for pseudo-registers.
2: Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: /* This file contains two passes of the compiler: reg_scan and reg_class.
22: It also defines some tables of information about the hardware registers
23: and a function init_reg_sets to initialize the tables. */
24:
25: #include "config.h"
26: #include "rtl.h"
27: #include "hard-reg-set.h"
28: #include "flags.h"
29: #include "basic-block.h"
30: #include "regs.h"
31: #include "insn-config.h"
32: #include "recog.h"
33:
34: #ifndef REGISTER_MOVE_COST
35: #define REGISTER_MOVE_COST(x, y) 2
36: #endif
37:
38: #ifndef MEMORY_MOVE_COST
39: #define MEMORY_MOVE_COST(x) 2
40: #endif
41:
42: /* Register tables used by many passes. */
43:
44: /* Indexed by hard register number, contains 1 for registers
45: that are fixed use (stack pointer, pc, frame pointer, etc.).
46: These are the registers that cannot be used to allocate
47: a pseudo reg whose life does not cross calls. */
48:
49: char fixed_regs[FIRST_PSEUDO_REGISTER];
50:
51: /* Same info as a HARD_REG_SET. */
52:
53: HARD_REG_SET fixed_reg_set;
54:
55: /* Data for initializing the above. */
56:
57: static char initial_fixed_regs[] = FIXED_REGISTERS;
58:
59: /* Indexed by hard register number, contains 1 for registers
60: that are fixed use or are clobbered by function calls.
61: These are the registers that cannot be used to allocate
62: a pseudo reg whose life crosses calls. */
63:
64: char call_used_regs[FIRST_PSEUDO_REGISTER];
65:
66: /* Same info as a HARD_REG_SET. */
67:
68: HARD_REG_SET call_used_reg_set;
69:
70: /* Data for initializing the above. */
71:
72: static char initial_call_used_regs[] = CALL_USED_REGISTERS;
73:
74: /* Indexed by hard register number, contains 1 for registers that are
75: fixed use -- i.e. in fixed_regs -- or a function value return register
76: or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
77: registers that cannot hold quantities across calls even if we are
78: willing to save and restore them. */
79:
80: char call_fixed_regs[FIRST_PSEUDO_REGISTER];
81:
82: /* The same info as a HARD_REG_SET. */
83:
84: HARD_REG_SET call_fixed_reg_set;
85:
86: /* Number of non-fixed registers. */
87:
88: int n_non_fixed_regs;
89:
90: /* Indexed by hard register number, contains 1 for registers
91: that are being used for global register decls.
92: These must be exempt from ordinary flow analysis
93: and are also considered fixed. */
94:
95: char global_regs[FIRST_PSEUDO_REGISTER];
96:
97: /* Table of register numbers in the order in which to try to use them. */
98: #ifdef REG_ALLOC_ORDER
99: int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
100: #endif
101:
102: /* For each reg class, a HARD_REG_SET saying which registers are in it. */
103:
104: HARD_REG_SET reg_class_contents[] = REG_CLASS_CONTENTS;
105:
106: /* For each reg class, number of regs it contains. */
107:
108: int reg_class_size[N_REG_CLASSES];
109:
110: /* For each reg class, table listing all the containing classes. */
111:
112: enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
113:
114: /* For each reg class, table listing all the classes contained in it. */
115:
116: enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
117:
118: /* For each pair of reg classes,
119: a largest reg class contained in their union. */
120:
121: enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
122:
123: /* For each pair of reg classes,
124: the smallest reg class containing their union. */
125:
126: enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
127:
128: /* Array containing all of the register names */
129:
130: char *reg_names[] = REGISTER_NAMES;
131:
132:
133: /* Indexed by n, gives number of times (REG n) is set or clobbered.
134: This information remains valid for the rest of the compilation
135: of the current function; it is used to control register allocation.
136:
137: This information applies to both hard registers and pseudo registers,
138: unlike much of the information above. */
139:
140: short *reg_n_sets;
141:
142: /* Function called only once to initialize the above data on reg usage.
143: Once this is done, various switches may override. */
144:
145: void
146: init_reg_sets ()
147: {
148: register int i, j;
149:
150: bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
151: bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
152: bzero (global_regs, sizeof global_regs);
153:
154: /* Compute number of hard regs in each class. */
155:
156: bzero (reg_class_size, sizeof reg_class_size);
157: for (i = 0; i < N_REG_CLASSES; i++)
158: for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
159: if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
160: reg_class_size[i]++;
161:
162: /* Initialize the table of subunions.
163: reg_class_subunion[I][J] gets the largest-numbered reg-class
164: that is contained in the union of classes I and J. */
165:
166: for (i = 0; i < N_REG_CLASSES; i++)
167: {
168: for (j = 0; j < N_REG_CLASSES; j++)
169: {
170: #ifdef HARD_REG_SET
171: register /* Declare it register if it's a scalar. */
172: #endif
173: HARD_REG_SET c;
174: register int k;
175:
176: COPY_HARD_REG_SET (c, reg_class_contents[i]);
177: IOR_HARD_REG_SET (c, reg_class_contents[j]);
178: for (k = 0; k < N_REG_CLASSES; k++)
179: {
180: GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
181: subclass1);
182: continue;
183:
184: subclass1:
185: /* keep the largest subclass */ /* SPEE 900308 */
186: GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
187: reg_class_contents[(int) reg_class_subunion[i][j]],
188: subclass2);
189: reg_class_subunion[i][j] = (enum reg_class) k;
190: subclass2:
191: ;
192: }
193: }
194: }
195:
196: /* Initialize the table of superunions.
197: reg_class_superunion[I][J] gets the smallest-numbered reg-class
198: containing the union of classes I and J. */
199:
200: for (i = 0; i < N_REG_CLASSES; i++)
201: {
202: for (j = 0; j < N_REG_CLASSES; j++)
203: {
204: #ifdef HARD_REG_SET
205: register /* Declare it register if it's a scalar. */
206: #endif
207: HARD_REG_SET c;
208: register int k;
209:
210: COPY_HARD_REG_SET (c, reg_class_contents[i]);
211: IOR_HARD_REG_SET (c, reg_class_contents[j]);
212: for (k = 0; k < N_REG_CLASSES; k++)
213: GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
214:
215: superclass:
216: reg_class_superunion[i][j] = (enum reg_class) k;
217: }
218: }
219:
220: /* Initialize the tables of subclasses and superclasses of each reg class.
221: First clear the whole table, then add the elements as they are found. */
222:
223: for (i = 0; i < N_REG_CLASSES; i++)
224: {
225: for (j = 0; j < N_REG_CLASSES; j++)
226: {
227: reg_class_superclasses[i][j] = LIM_REG_CLASSES;
228: reg_class_subclasses[i][j] = LIM_REG_CLASSES;
229: }
230: }
231:
232: for (i = 0; i < N_REG_CLASSES; i++)
233: {
234: if (i == (int) NO_REGS)
235: continue;
236:
237: for (j = i + 1; j < N_REG_CLASSES; j++)
238: {
239: enum reg_class *p;
240:
241: GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
242: subclass);
243: continue;
244: subclass:
245: /* Reg class I is a subclass of J.
246: Add J to the table of superclasses of I. */
247: p = ®_class_superclasses[i][0];
248: while (*p != LIM_REG_CLASSES) p++;
249: *p = (enum reg_class) j;
250: /* Add I to the table of superclasses of J. */
251: p = ®_class_subclasses[j][0];
252: while (*p != LIM_REG_CLASSES) p++;
253: *p = (enum reg_class) i;
254: }
255: }
256: }
257:
258: /* After switches have been processed, which perhaps alter
259: `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
260:
261: void
262: init_reg_sets_1 ()
263: {
264: register int i;
265:
266: /* This macro allows the fixed or call-used registers
267: to depend on target flags. */
268:
269: #ifdef CONDITIONAL_REGISTER_USAGE
270: CONDITIONAL_REGISTER_USAGE;
271: #endif
272:
273: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
274: if (global_regs[i])
275: {
276: if (call_used_regs[i] && ! fixed_regs[i])
277: warning ("call-clobbered register used for global register variable");
278: fixed_regs[i] = 1;
279: /* Prevent saving/restoring of this reg. */
280: call_used_regs[i] = 1;
281: }
282:
283: /* Initialize "constant" tables. */
284:
285: CLEAR_HARD_REG_SET (fixed_reg_set);
286: CLEAR_HARD_REG_SET (call_used_reg_set);
287: CLEAR_HARD_REG_SET (call_fixed_reg_set);
288:
289: bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
290: #ifdef STRUCT_VALUE_REGNUM
291: call_fixed_regs[STRUCT_VALUE_REGNUM] = 1;
292: #endif
293: #ifdef STATIC_CHAIN_REGNUM
294: call_fixed_regs[STATIC_CHAIN_REGNUM] = 1;
295: #endif
296:
297: n_non_fixed_regs = 0;
298:
299: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
300: {
301: if (FUNCTION_VALUE_REGNO_P (i))
302: call_fixed_regs[i] = 1;
303: if (fixed_regs[i])
304: SET_HARD_REG_BIT (fixed_reg_set, i);
305: else
306: n_non_fixed_regs++;
307:
308: if (call_used_regs[i])
309: SET_HARD_REG_BIT (call_used_reg_set, i);
310: if (call_fixed_regs[i])
311: SET_HARD_REG_BIT (call_fixed_reg_set, i);
312: }
313: }
314:
315: /* Specify the usage characteristics of the register named NAME.
316: It should be a fixed register if FIXED and a
317: call-used register if CALL_USED. */
318:
319: void
320: fix_register (name, fixed, call_used)
321: char *name;
322: int fixed, call_used;
323: {
324: int i;
325:
326: /* Decode the name and update the primary form of
327: the register info. */
328:
1.1.1.2 root 329: if ((i = decode_reg_name (name)) >= 0)
330: {
331: fixed_regs[i] = fixed;
332: call_used_regs[i] = call_used;
333: }
334: else
1.1 root 335: {
336: warning ("unknown register name: %s", name);
337: }
338: }
339:
340: /* Now the data and code for the `regclass' pass, which happens
341: just before local-alloc. */
342:
343: /* savings[R].savings[CL] is twice the amount saved by putting register R
344: in class CL. This data is used within `regclass' and freed
345: when it is finished. */
346:
347: struct savings
348: {
349: short savings[N_REG_CLASSES];
350: short memcost;
351: short nrefs;
352: };
353:
354: static struct savings *savings;
355:
356: /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
357: This is available after `regclass' is run. */
358:
359: static char *prefclass;
360:
361: /* preferred_or_nothing[R] is nonzero if we should put pseudo number R
1.1.1.3 ! root 362: in memory if we can't get its preferred class.
1.1 root 363: This is available after `regclass' is run. */
364:
365: static char *preferred_or_nothing;
366:
367: /* Record the depth of loops that we are in, 1 for no loops. */
368:
369: static int loop_depth;
370:
371: void reg_class_record ();
372: void record_address_regs ();
373:
374:
375: /* Return the reg_class in which pseudo reg number REGNO is best allocated.
376: This function is sometimes called before the info has been computed.
377: When that happens, just return GENERAL_REGS, which is innocuous. */
378:
379: enum reg_class
380: reg_preferred_class (regno)
381: int regno;
382: {
383: if (prefclass == 0)
384: return GENERAL_REGS;
385: return (enum reg_class) prefclass[regno];
386: }
387:
388: int
389: reg_preferred_or_nothing (regno)
390: {
391: if (prefclass == 0)
392: return 0;
393: return preferred_or_nothing[regno];
394: }
395:
396: /* This prevents dump_flow_info from losing if called
397: before regclass is run. */
398:
399: void
400: regclass_init ()
401: {
402: prefclass = 0;
403: }
404:
405: /* This is a pass of the compiler that scans all instructions
406: and calculates the preferred class for each pseudo-register.
407: This information can be accessed later by calling `reg_preferred_class'.
408: This pass comes just before local register allocation. */
409:
410: void
411: regclass (f, nregs)
412: rtx f;
413: int nregs;
414: {
415: #ifdef REGISTER_CONSTRAINTS
416: register rtx insn;
417: register int i;
418:
419: init_recog ();
420:
421: /* Zero out our accumulation of the cost of each class for each reg. */
422:
423: savings = (struct savings *) alloca (nregs * sizeof (struct savings));
424: bzero (savings, nregs * sizeof (struct savings));
425:
426: loop_depth = 1;
427:
428: /* Scan the instructions and record each time it would
429: save code to put a certain register in a certain class. */
430:
431: for (insn = f; insn; insn = NEXT_INSN (insn))
432: {
433: if (GET_CODE (insn) == NOTE
434: && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
435: loop_depth++;
436: else if (GET_CODE (insn) == NOTE
437: && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
438: loop_depth--;
439: else if ((GET_CODE (insn) == INSN
440: && GET_CODE (PATTERN (insn)) != USE
441: && GET_CODE (PATTERN (insn)) != CLOBBER
442: && GET_CODE (PATTERN (insn)) != ASM_INPUT)
443: || (GET_CODE (insn) == JUMP_INSN
444: && GET_CODE (PATTERN (insn)) != ADDR_VEC
445: && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
446: || GET_CODE (insn) == CALL_INSN)
447: {
448: if (GET_CODE (insn) == INSN && asm_noperands (PATTERN (insn)) >= 0)
449: {
450: int noperands = asm_noperands (PATTERN (insn));
451: /* We don't use alloca because alloca would not free
452: any of the space until this function returns. */
453: rtx *operands = (rtx *) oballoc (noperands * sizeof (rtx));
454: char **constraints
455: = (char **) oballoc (noperands * sizeof (char *));
456:
457: decode_asm_operands (PATTERN (insn), operands, 0, constraints, 0);
458:
459: for (i = noperands - 1; i >= 0; i--)
460: reg_class_record (operands[i], i, constraints);
461:
462: obfree (operands);
463: }
464: else
465: {
466: int insn_code_number = recog_memoized (insn);
467: rtx set = single_set (insn);
468:
469: insn_extract (insn);
470:
471: for (i = insn_n_operands[insn_code_number] - 1; i >= 0; i--)
472: reg_class_record (recog_operand[i], i,
473: insn_operand_constraint[insn_code_number]);
474:
475: /* If this insn loads a parameter from its stack slot,
476: then it represents a savings, rather than a cost,
477: if the parameter is stored in memory. Record this fact. */
478: if (set != 0 && GET_CODE (SET_DEST (set)) == REG
479: && GET_CODE (SET_SRC (set)) == MEM)
480: {
481: rtx note = find_reg_note (insn, REG_EQUIV, 0);
482: if (note != 0 && GET_CODE (XEXP (note, 0)) == MEM)
483: savings[REGNO (SET_DEST (set))].memcost
484: -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)))
485: * loop_depth);
486: }
487:
488: /* Improve handling of two-address insns such as
489: (set X (ashift CONST Y)) where CONST must be made to match X.
490: Change it into two insns: (set X CONST) (set X (ashift X Y)).
491: If we left this for reloading, it would probably get three
492: insns because X and Y might go in the same place.
493: This prevents X and Y from receiving the same hard reg.
494:
495: We can only do this if the modes of operands 0 and 1 (which
496: might not be the same) are tieable. */
497:
498: if (optimize
499: && insn_n_operands[insn_code_number] >= 3
500: && insn_operand_constraint[insn_code_number][1][0] == '0'
501: && insn_operand_constraint[insn_code_number][1][1] == 0
502: && CONSTANT_P (recog_operand[1])
503: && ! rtx_equal_p (recog_operand[0], recog_operand[1])
504: && ! rtx_equal_p (recog_operand[0], recog_operand[2])
505: && GET_CODE (recog_operand[0]) == REG
506: && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
507: insn_operand_mode[insn_code_number][1]))
508: {
509: rtx previnsn = prev_real_insn (insn);
510: rtx dest
511: = gen_lowpart (insn_operand_mode[insn_code_number][1],
512: recog_operand[0]);
513: rtx newinsn
514: = emit_insn_before (gen_move_insn (dest, recog_operand[1]),
515: insn);
516:
517: /* If this insn was the start of a basic block,
518: include the new insn in that block. */
519: if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
520: {
521: int b;
522: for (b = 0; b < n_basic_blocks; b++)
523: if (insn == basic_block_head[b])
524: basic_block_head[b] = newinsn;
525: }
526:
527: /* This makes one more setting of new insns's destination. */
528: reg_n_sets[REGNO (recog_operand[0])]++;
529:
530: *recog_operand_loc[1] = recog_operand[0];
531: for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
532: if (recog_dup_num[i] == 1)
533: *recog_dup_loc[i] = recog_operand[0];
534: }
535: }
536: }
537: }
538:
539: /* Now for each register look at how desirable each class is
540: and find which class is preferred. Store that in `prefclass[REGNO]'. */
541:
542: prefclass = (char *) oballoc (nregs);
543:
544: preferred_or_nothing = (char *) oballoc (nregs);
545:
546: for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
547: {
548: register int best_savings = 0;
549: enum reg_class best = ALL_REGS;
550:
551: /* This is an enum reg_class, but we call it an int
552: to save lots of casts. */
553: register int class;
554: register struct savings *p = &savings[i];
555:
556: for (class = (int) ALL_REGS - 1; class > 0; class--)
557: {
558: if (p->savings[class] > best_savings)
559: {
560: best_savings = p->savings[class];
561: best = (enum reg_class) class;
562: }
563: else if (p->savings[class] == best_savings)
564: {
565: best = reg_class_subunion[(int)best][class];
566: }
567: }
568:
569: #if 0
570: /* Note that best_savings is twice number of places something
571: is saved. */
572: if ((best_savings - p->savings[(int) GENERAL_REGS]) * 5 < reg_n_refs[i])
573: prefclass[i] = (int) GENERAL_REGS;
574: else
575: prefclass[i] = (int) best;
576: #else
577: /* We cast to (int) because (char) hits bugs in some compilers. */
578: prefclass[i] = (int) best;
579: #endif
580:
581: /* reg_n_refs + p->memcost measures the cost of putting in memory.
582: If a GENERAL_REG is no better, don't even try for one.
583: Since savings and memcost are 2 * number of refs,
584: this effectively counts each memory operand not needing reloading
585: as costing 1/2 of a reload insn. */
586: if (reg_n_refs != 0)
587: preferred_or_nothing[i]
588: = ((best_savings - p->savings[(int) GENERAL_REGS])
589: >= p->nrefs + p->memcost);
590: }
591: #endif /* REGISTER_CONSTRAINTS */
592: }
593:
594: #ifdef REGISTER_CONSTRAINTS
595:
596: /* Scan an operand OP for register class preferences.
597: OPNO is the operand number, and CONSTRAINTS is the constraint
598: vector for the insn.
599:
600: Record the preferred register classes from the constraint for OP
601: if OP is a register. If OP is a memory reference, record suitable
602: preferences for registers used in the address. */
603:
604: void
605: reg_class_record (op, opno, constraints)
606: rtx op;
607: int opno;
608: char **constraints;
609: {
610: char *constraint = constraints[opno];
611: register char *p;
612: register enum reg_class class = NO_REGS;
613: char *next = 0;
614: int memok = 0;
615: int double_cost = 0;
616:
617: if (op == 0)
618: return;
619:
620: while (1)
621: {
622: if (GET_CODE (op) == SUBREG)
623: op = SUBREG_REG (op);
624: else break;
625: }
626:
627: /* Memory reference: scan the address. */
628:
629: if (GET_CODE (op) == MEM)
630: record_address_regs (XEXP (op, 0), 2, 0);
631:
632: if (GET_CODE (op) != REG)
633: {
634: /* If the constraint says the operand is supposed to BE an address,
635: scan it as one. */
636:
637: if (constraint != 0 && constraint[0] == 'p')
638: record_address_regs (op, 2, 0);
639: return;
640: }
641:
642: /* Operand is a register: examine the constraint for specified classes. */
643:
644: for (p = constraint; *p || next; p++)
645: {
646: enum reg_class new_class = NO_REGS;
647:
648: if (*p == 0)
649: {
650: p = next;
651: next = 0;
652: }
653: switch (*p)
654: {
655: case '=':
656: case '?':
657: case '#':
658: case '&':
659: case '!':
660: case '%':
661: case 'E':
662: case 'F':
663: case 'G':
664: case 'H':
665: case 'i':
666: case 'n':
667: case 's':
668: case 'p':
669: case ',':
670: case 'I':
671: case 'J':
672: case 'K':
673: case 'L':
674: case 'M':
675: case 'N':
676: case 'O':
677: case 'P':
678: #ifdef EXTRA_CONSTRAINT
679: case 'Q':
680: case 'R':
681: case 'S':
682: case 'T':
683: case 'U':
684: #endif
685: case 'V':
686: case 'X':
687: break;
688:
689: case '+':
690: /* An input-output operand is twice as costly if it loses. */
691: double_cost = 1;
692: break;
693:
694: case 'm':
695: case 'o':
696: memok = 1;
697: break;
698:
699: /* * means ignore following letter
700: when choosing register preferences. */
701: case '*':
702: p++;
703: break;
704:
705: case 'g':
706: case 'r':
707: new_class = GENERAL_REGS;
708: break;
709:
710: case '0':
711: case '1':
712: case '2':
713: case '3':
714: case '4':
715: /* If constraint says "match another operand",
716: use that operand's constraint to choose preferences. */
717: if (*p - '0' < opno)
718: {
719: opno = *p - '0';
720: next = constraints[opno];
721: }
722: break;
723:
724: default:
725: new_class = REG_CLASS_FROM_LETTER (*p);
726: break;
727: }
728:
729: /* If this object can fit into the class requested, compute the subunion
730: of the requested class and classes found so far. */
731: if (CLASS_MAX_NREGS (new_class, GET_MODE (op))
732: <= reg_class_size[(int) new_class])
733: class = reg_class_subunion[(int) class][(int) new_class];
734: }
735:
736: {
737: register int i;
738: register struct savings *pp;
739: register enum reg_class class1;
740: int cost = 2 * (1 + double_cost) * loop_depth;
741: pp = &savings[REGNO (op)];
742:
743: /* Increment the savings for this reg
744: for each class contained in the one the constraint asks for. */
745:
746: if (class != NO_REGS && class != ALL_REGS)
747: {
748: int extracost;
749:
750: pp->savings[(int) class] += cost;
751: for (i = 0; ; i++)
752: {
753: class1 = reg_class_subclasses[(int)class][i];
754: if (class1 == LIM_REG_CLASSES)
755: break;
756: pp->savings[(int) class1] += cost;
757: }
758: /* If it's slow to move data between this class and GENERAL_REGS,
759: record that fact. */
760: extracost = (REGISTER_MOVE_COST (class, GENERAL_REGS) - 2) * loop_depth;
761: if (extracost > 0)
762: {
763: /* Check that this class and GENERAL_REGS don't overlap.
764: REGISTER_MOVE_COST is meaningless if there is overlap. */
765: HARD_REG_SET temp;
766: COMPL_HARD_REG_SET (temp, reg_class_contents[(int) class]);
767: GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) GENERAL_REGS],
768: temp, label1);
769: /* Overlap. */
770: goto label2;
771:
772: label1: /* No overlap. */
773: /* Charge this extra cost to GENERAL_REGS
774: and all its subclasses (none of which overlap this class). */
775: extracost = extracost * cost / (2 * loop_depth);
776: pp->savings[(int) GENERAL_REGS] -= extracost;
777: for (i = 0; ; i++)
778: {
779: class1 = reg_class_subclasses[(int)GENERAL_REGS][i];
780: if (class1 == LIM_REG_CLASSES)
781: break;
782: pp->savings[(int) class1] -= extracost;
783: }
784:
785: label2: ;
786: }
787: }
788:
789: if (! memok)
790: pp->memcost += (MEMORY_MOVE_COST (GET_MODE (op)) * (1 + double_cost)
791: - 1) * loop_depth;
792: pp->nrefs += loop_depth;
793: }
794: }
795:
796: /* Record the pseudo registers we must reload into hard registers
797: in a subexpression of a memory address, X.
798: BCOST is the cost if X is a register and it fails to be in BASE_REG_CLASS.
799: ICOST is the cost if it fails to be in INDEX_REG_CLASS. */
800:
801: void
802: record_address_regs (x, bcost, icost)
803: rtx x;
804: int bcost, icost;
805: {
806: register enum rtx_code code = GET_CODE (x);
807:
808: switch (code)
809: {
810: case CONST_INT:
811: case CONST:
812: case CC0:
813: case PC:
814: case SYMBOL_REF:
815: case LABEL_REF:
816: return;
817:
818: case PLUS:
819: /* When we have an address that is a sum,
820: we must determine whether registers are "base" or "index" regs.
821: If there is a sum of two registers, we must choose one to be
822: the "base". Luckily, we can use the REGNO_POINTER_FLAG
823: to make a good choice most of the time. */
824: {
825: rtx arg0 = XEXP (x, 0);
826: rtx arg1 = XEXP (x, 1);
827: register enum rtx_code code0 = GET_CODE (arg0);
828: register enum rtx_code code1 = GET_CODE (arg1);
829: int icost0 = 0;
830: int icost1 = 0;
831: int suppress1 = 0;
832: int suppress0 = 0;
833:
834: /* Look inside subregs. */
835: while (code0 == SUBREG)
836: arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
837: while (code1 == SUBREG)
838: arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
839:
840: if (code0 == MULT || code1 == MEM)
841: icost0 = 2;
842: else if (code1 == MULT || code0 == MEM)
843: icost1 = 2;
844: else if (code0 == CONST_INT)
845: suppress0 = 1;
846: else if (code1 == CONST_INT)
847: suppress1 = 1;
848: else if (code0 == REG && code1 == REG)
849: {
850: if (REGNO_POINTER_FLAG (REGNO (arg0)))
851: icost1 = 2;
852: else if (REGNO_POINTER_FLAG (REGNO (arg1)))
853: icost0 = 2;
854: else
855: icost0 = icost1 = 1;
856: }
857: else if (code0 == REG)
858: {
859: if (code1 == PLUS
860: && ! REGNO_POINTER_FLAG (REGNO (arg0)))
861: icost0 = 2;
862: else
863: REGNO_POINTER_FLAG (REGNO (arg0)) = 1;
864: }
865: else if (code1 == REG)
866: {
867: if (code0 == PLUS
868: && ! REGNO_POINTER_FLAG (REGNO (arg1)))
869: icost1 = 2;
870: else
871: REGNO_POINTER_FLAG (REGNO (arg1)) = 1;
872: }
873:
874: /* ICOST0 determines whether we are treating operand 0
875: as a base register or as an index register.
876: SUPPRESS0 nonzero means it isn't a register at all.
877: ICOST1 and SUPPRESS1 are likewise for operand 1. */
878:
879: if (! suppress0)
880: record_address_regs (arg0, 2 - icost0, icost0);
881: if (! suppress1)
882: record_address_regs (arg1, 2 - icost1, icost1);
883: }
884: break;
885:
886: case POST_INC:
887: case PRE_INC:
888: case POST_DEC:
889: case PRE_DEC:
890: /* Double the importance of a pseudo register that is incremented
891: or decremented, since it would take two extra insns
892: if it ends up in the wrong place. */
893: record_address_regs (XEXP (x, 0), 2 * bcost, 2 * icost);
894: break;
895:
896: case REG:
897: {
898: register struct savings *pp;
899: register enum reg_class class, class1;
900: pp = &savings[REGNO (x)];
901: pp->nrefs += loop_depth;
902:
903: /* We have an address (or part of one) that is just one register. */
904:
905: /* Record BCOST worth of savings for classes contained
906: in BASE_REG_CLASS. */
907:
908: class = BASE_REG_CLASS;
909: if (class != NO_REGS && class != ALL_REGS)
910: {
911: register int i;
912: pp->savings[(int) class] += bcost * loop_depth;
913: for (i = 0; ; i++)
914: {
915: class1 = reg_class_subclasses[(int)class][i];
916: if (class1 == LIM_REG_CLASSES)
917: break;
918: pp->savings[(int) class1] += bcost * loop_depth;
919: }
920: }
921:
922: /* Record ICOST worth of savings for classes contained
923: in INDEX_REG_CLASS. */
924:
925: class = INDEX_REG_CLASS;
926: if (icost != 0 && class != NO_REGS && class != ALL_REGS)
927: {
928: register int i;
929: pp->savings[(int) class] += icost * loop_depth;
930: for (i = 0; ; i++)
931: {
932: class1 = reg_class_subclasses[(int)class][i];
933: if (class1 == LIM_REG_CLASSES)
934: break;
935: pp->savings[(int) class1] += icost * loop_depth;
936: }
937: }
938: }
939: break;
940:
941: default:
942: {
943: register char *fmt = GET_RTX_FORMAT (code);
944: register int i;
945: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
946: if (fmt[i] == 'e')
947: record_address_regs (XEXP (x, i), bcost, icost);
948: }
949: }
950: }
951: #endif /* REGISTER_CONSTRAINTS */
952:
953: /* This is the `regscan' pass of the compiler, run just before cse
954: and again just before loop.
955:
956: It finds the first and last use of each pseudo-register
957: and records them in the vectors regno_first_uid, regno_last_uid
958: and counts the number of sets in the vector reg_n_sets.
959:
960: REPEAT is nonzero the second time this is called. */
961:
962: /* Indexed by pseudo register number, gives uid of first insn using the reg
963: (as of the time reg_scan is called). */
964:
965: short *regno_first_uid;
966:
967: /* Indexed by pseudo register number, gives uid of last insn using the reg
968: (as of the time reg_scan is called). */
969:
970: short *regno_last_uid;
971:
972: /* Record the number of registers we used when we allocated the above two
973: tables. If we are called again with more than this, we must re-allocate
974: the tables. */
975:
976: static int highest_regno_in_uid_map;
977:
978: /* Maximum number of parallel sets and clobbers in any insn in this fn.
979: Always at least 3, since the combiner could put that many togetherm
980: and we want this to remain correct for all the remaining passes. */
981:
982: int max_parallel;
983:
984: void reg_scan_mark_refs ();
985:
986: void
987: reg_scan (f, nregs, repeat)
988: rtx f;
989: int nregs;
990: int repeat;
991: {
992: register rtx insn;
993:
994: if (!repeat || nregs > highest_regno_in_uid_map)
995: {
996: /* Leave some spare space in case more regs are allocated. */
997: highest_regno_in_uid_map = nregs + nregs / 20;
998: regno_first_uid
999: = (short *) oballoc (highest_regno_in_uid_map * sizeof (short));
1000: regno_last_uid
1001: = (short *) oballoc (highest_regno_in_uid_map * sizeof (short));
1002: reg_n_sets
1003: = (short *) oballoc (highest_regno_in_uid_map * sizeof (short));
1004: }
1005:
1006: bzero (regno_first_uid, highest_regno_in_uid_map * sizeof (short));
1007: bzero (regno_last_uid, highest_regno_in_uid_map * sizeof (short));
1008: bzero (reg_n_sets, highest_regno_in_uid_map * sizeof (short));
1009:
1010: max_parallel = 3;
1011:
1012: for (insn = f; insn; insn = NEXT_INSN (insn))
1013: if (GET_CODE (insn) == INSN
1014: || GET_CODE (insn) == CALL_INSN
1015: || GET_CODE (insn) == JUMP_INSN)
1016: {
1017: if (GET_CODE (PATTERN (insn)) == PARALLEL
1018: && XVECLEN (PATTERN (insn), 0) > max_parallel)
1019: max_parallel = XVECLEN (PATTERN (insn), 0);
1020: reg_scan_mark_refs (PATTERN (insn), INSN_UID (insn));
1021: }
1022: }
1023:
1024: void
1025: reg_scan_mark_refs (x, uid)
1026: rtx x;
1027: int uid;
1028: {
1029: register enum rtx_code code = GET_CODE (x);
1030: register rtx dest;
1031:
1032: switch (code)
1033: {
1034: case CONST_INT:
1035: case CONST:
1036: case CONST_DOUBLE:
1037: case CC0:
1038: case PC:
1039: case SYMBOL_REF:
1040: case LABEL_REF:
1041: case ADDR_VEC:
1042: case ADDR_DIFF_VEC:
1043: return;
1044:
1045: case REG:
1046: {
1047: register int regno = REGNO (x);
1048:
1049: regno_last_uid[regno] = uid;
1050: if (regno_first_uid[regno] == 0)
1051: regno_first_uid[regno] = uid;
1052: }
1053: break;
1054:
1055: case SET:
1056: /* Count a set of the destination if it is a register. */
1057: for (dest = SET_DEST (x);
1058: GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
1059: || GET_CODE (dest) == ZERO_EXTEND;
1060: dest = XEXP (dest, 0))
1061: ;
1062:
1063: if (GET_CODE (dest) == REG)
1064: reg_n_sets[REGNO (dest)]++;
1065:
1066: /* ... fall through ... */
1067:
1068: default:
1069: {
1070: register char *fmt = GET_RTX_FORMAT (code);
1071: register int i;
1072: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1073: {
1074: if (fmt[i] == 'e')
1075: reg_scan_mark_refs (XEXP (x, i), uid);
1076: else if (fmt[i] == 'E' && XVEC (x, i) != 0)
1077: {
1078: register int j;
1079: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1080: reg_scan_mark_refs (XVECEXP (x, i, j), uid);
1081: }
1082: }
1083: }
1084: }
1085: }
1086:
1087: /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
1088: is also in C2. */
1089:
1090: int
1091: reg_class_subset_p (c1, c2)
1092: register enum reg_class c1;
1093: register enum reg_class c2;
1094: {
1095: if (c1 == c2) return 1;
1096:
1097: if (c2 == ALL_REGS)
1098: win:
1099: return 1;
1100: GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
1101: reg_class_contents[(int)c2],
1102: win);
1103: return 0;
1104: }
1105:
1106: /* Return nonzero if there is a register that is in both C1 and C2. */
1107:
1108: int
1109: reg_classes_intersect_p (c1, c2)
1110: register enum reg_class c1;
1111: register enum reg_class c2;
1112: {
1113: #ifdef HARD_REG_SET
1114: register
1115: #endif
1116: HARD_REG_SET c;
1117:
1118: if (c1 == c2) return 1;
1119:
1120: if (c1 == ALL_REGS || c2 == ALL_REGS)
1121: return 1;
1122:
1123: COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1124: AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1125:
1126: GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
1127: return 1;
1128:
1129: lose:
1130: return 0;
1131: }
1132:
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