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1.1 root 1: /* Compute register class preferences for pseudo-registers. 1.1.1.6 ! root 2: Copyright (C) 1987, 1988, 1991, 1992, 1993 Free Software Foundation, Inc. 1.1 root 3: 4: This file is part of GNU CC. 5: 6: GNU CC is free software; you can redistribute it and/or modify 7: it under the terms of the GNU General Public License as published by 8: the Free Software Foundation; either version 2, or (at your option) 9: any later version. 10: 11: GNU CC is distributed in the hope that it will be useful, 12: but WITHOUT ANY WARRANTY; without even the implied warranty of 13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14: GNU General Public License for more details. 15: 16: You should have received a copy of the GNU General Public License 17: along with GNU CC; see the file COPYING. If not, write to 18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 19: 20: 21: /* This file contains two passes of the compiler: reg_scan and reg_class. 22: It also defines some tables of information about the hardware registers 23: and a function init_reg_sets to initialize the tables. */ 24: 25: #include "config.h" 26: #include "rtl.h" 27: #include "hard-reg-set.h" 28: #include "flags.h" 29: #include "basic-block.h" 30: #include "regs.h" 31: #include "insn-config.h" 32: #include "recog.h" 1.1.1.4 root 33: #include "reload.h" 34: #include "real.h" 1.1.1.6 ! root 35: #include "bytecode.h" 1.1 root 36: 37: #ifndef REGISTER_MOVE_COST 38: #define REGISTER_MOVE_COST(x, y) 2 39: #endif 40: 41: #ifndef MEMORY_MOVE_COST 1.1.1.4 root 42: #define MEMORY_MOVE_COST(x) 4 43: #endif 44: 45: /* If we have auto-increment or auto-decrement and we can have secondary 46: reloads, we are not allowed to use classes requiring secondary 47: reloads for psuedos auto-incremented since reload can't handle it. */ 48: 49: #ifdef AUTO_INC_DEC 50: #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) 51: #define FORBIDDEN_INC_DEC_CLASSES 52: #endif 1.1 root 53: #endif 54: 55: /* Register tables used by many passes. */ 56: 57: /* Indexed by hard register number, contains 1 for registers 58: that are fixed use (stack pointer, pc, frame pointer, etc.). 59: These are the registers that cannot be used to allocate 60: a pseudo reg whose life does not cross calls. */ 61: 62: char fixed_regs[FIRST_PSEUDO_REGISTER]; 63: 64: /* Same info as a HARD_REG_SET. */ 65: 66: HARD_REG_SET fixed_reg_set; 67: 68: /* Data for initializing the above. */ 69: 70: static char initial_fixed_regs[] = FIXED_REGISTERS; 71: 72: /* Indexed by hard register number, contains 1 for registers 73: that are fixed use or are clobbered by function calls. 74: These are the registers that cannot be used to allocate 75: a pseudo reg whose life crosses calls. */ 76: 77: char call_used_regs[FIRST_PSEUDO_REGISTER]; 78: 79: /* Same info as a HARD_REG_SET. */ 80: 81: HARD_REG_SET call_used_reg_set; 82: 83: /* Data for initializing the above. */ 84: 85: static char initial_call_used_regs[] = CALL_USED_REGISTERS; 86: 87: /* Indexed by hard register number, contains 1 for registers that are 88: fixed use -- i.e. in fixed_regs -- or a function value return register 89: or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the 90: registers that cannot hold quantities across calls even if we are 91: willing to save and restore them. */ 92: 93: char call_fixed_regs[FIRST_PSEUDO_REGISTER]; 94: 95: /* The same info as a HARD_REG_SET. */ 96: 97: HARD_REG_SET call_fixed_reg_set; 98: 99: /* Number of non-fixed registers. */ 100: 101: int n_non_fixed_regs; 102: 103: /* Indexed by hard register number, contains 1 for registers 104: that are being used for global register decls. 105: These must be exempt from ordinary flow analysis 106: and are also considered fixed. */ 107: 108: char global_regs[FIRST_PSEUDO_REGISTER]; 109: 110: /* Table of register numbers in the order in which to try to use them. */ 111: #ifdef REG_ALLOC_ORDER 112: int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; 113: #endif 114: 115: /* For each reg class, a HARD_REG_SET saying which registers are in it. */ 116: 1.1.1.4 root 117: HARD_REG_SET reg_class_contents[N_REG_CLASSES]; 118: 1.1.1.5 root 119: /* The same information, but as an array of unsigned ints. We copy from 120: these unsigned ints to the table above. We do this so the tm.h files 121: do not have to be aware of the wordsize for machines with <= 64 regs. */ 1.1.1.4 root 122: 123: #define N_REG_INTS \ 124: ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) 125: 1.1.1.5 root 126: static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] 1.1.1.4 root 127: = REG_CLASS_CONTENTS; 1.1 root 128: 129: /* For each reg class, number of regs it contains. */ 130: 131: int reg_class_size[N_REG_CLASSES]; 132: 133: /* For each reg class, table listing all the containing classes. */ 134: 135: enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; 136: 137: /* For each reg class, table listing all the classes contained in it. */ 138: 139: enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; 140: 141: /* For each pair of reg classes, 142: a largest reg class contained in their union. */ 143: 144: enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; 145: 146: /* For each pair of reg classes, 147: the smallest reg class containing their union. */ 148: 149: enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; 150: 151: /* Array containing all of the register names */ 152: 153: char *reg_names[] = REGISTER_NAMES; 154: 155: /* Indexed by n, gives number of times (REG n) is set or clobbered. 156: This information remains valid for the rest of the compilation 157: of the current function; it is used to control register allocation. 158: 159: This information applies to both hard registers and pseudo registers, 160: unlike much of the information above. */ 161: 162: short *reg_n_sets; 163: 1.1.1.4 root 164: /* Maximum cost of moving from a register in one class to a register in 165: another class. Based on REGISTER_MOVE_COST. */ 166: 167: static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; 168: 169: /* Similar, but here we don't have to move if the first index is a subset 170: of the second so in that case the cost is zero. */ 171: 172: static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; 173: 174: #ifdef FORBIDDEN_INC_DEC_CLASSES 175: 176: /* These are the classes that regs which are auto-incremented or decremented 177: cannot be put in. */ 178: 179: static int forbidden_inc_dec_class[N_REG_CLASSES]; 180: 181: /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec 182: context. */ 183: 184: static char *in_inc_dec; 185: 186: #endif /* FORBIDDEN_INC_DEC_CLASSES */ 187: 1.1 root 188: /* Function called only once to initialize the above data on reg usage. 189: Once this is done, various switches may override. */ 190: 191: void 192: init_reg_sets () 193: { 194: register int i, j; 195: 1.1.1.4 root 196: /* First copy the register information from the initial int form into 197: the regsets. */ 198: 199: for (i = 0; i < N_REG_CLASSES; i++) 200: { 201: CLEAR_HARD_REG_SET (reg_class_contents[i]); 202: 203: for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 204: if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] 1.1.1.5 root 205: & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) 1.1.1.4 root 206: SET_HARD_REG_BIT (reg_class_contents[i], j); 207: } 208: 1.1 root 209: bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); 210: bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); 211: bzero (global_regs, sizeof global_regs); 212: 213: /* Compute number of hard regs in each class. */ 214: 215: bzero (reg_class_size, sizeof reg_class_size); 216: for (i = 0; i < N_REG_CLASSES; i++) 217: for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 218: if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 219: reg_class_size[i]++; 220: 221: /* Initialize the table of subunions. 222: reg_class_subunion[I][J] gets the largest-numbered reg-class 223: that is contained in the union of classes I and J. */ 224: 225: for (i = 0; i < N_REG_CLASSES; i++) 226: { 227: for (j = 0; j < N_REG_CLASSES; j++) 228: { 229: #ifdef HARD_REG_SET 230: register /* Declare it register if it's a scalar. */ 231: #endif 232: HARD_REG_SET c; 233: register int k; 234: 235: COPY_HARD_REG_SET (c, reg_class_contents[i]); 236: IOR_HARD_REG_SET (c, reg_class_contents[j]); 237: for (k = 0; k < N_REG_CLASSES; k++) 238: { 239: GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, 240: subclass1); 241: continue; 242: 243: subclass1: 244: /* keep the largest subclass */ /* SPEE 900308 */ 245: GO_IF_HARD_REG_SUBSET (reg_class_contents[k], 246: reg_class_contents[(int) reg_class_subunion[i][j]], 247: subclass2); 248: reg_class_subunion[i][j] = (enum reg_class) k; 249: subclass2: 250: ; 251: } 252: } 253: } 254: 255: /* Initialize the table of superunions. 256: reg_class_superunion[I][J] gets the smallest-numbered reg-class 257: containing the union of classes I and J. */ 258: 259: for (i = 0; i < N_REG_CLASSES; i++) 260: { 261: for (j = 0; j < N_REG_CLASSES; j++) 262: { 263: #ifdef HARD_REG_SET 264: register /* Declare it register if it's a scalar. */ 265: #endif 266: HARD_REG_SET c; 267: register int k; 268: 269: COPY_HARD_REG_SET (c, reg_class_contents[i]); 270: IOR_HARD_REG_SET (c, reg_class_contents[j]); 271: for (k = 0; k < N_REG_CLASSES; k++) 272: GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); 273: 274: superclass: 275: reg_class_superunion[i][j] = (enum reg_class) k; 276: } 277: } 278: 279: /* Initialize the tables of subclasses and superclasses of each reg class. 280: First clear the whole table, then add the elements as they are found. */ 281: 282: for (i = 0; i < N_REG_CLASSES; i++) 283: { 284: for (j = 0; j < N_REG_CLASSES; j++) 285: { 286: reg_class_superclasses[i][j] = LIM_REG_CLASSES; 287: reg_class_subclasses[i][j] = LIM_REG_CLASSES; 288: } 289: } 290: 291: for (i = 0; i < N_REG_CLASSES; i++) 292: { 293: if (i == (int) NO_REGS) 294: continue; 295: 296: for (j = i + 1; j < N_REG_CLASSES; j++) 297: { 298: enum reg_class *p; 299: 300: GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], 301: subclass); 302: continue; 303: subclass: 304: /* Reg class I is a subclass of J. 305: Add J to the table of superclasses of I. */ 306: p = ®_class_superclasses[i][0]; 307: while (*p != LIM_REG_CLASSES) p++; 308: *p = (enum reg_class) j; 309: /* Add I to the table of superclasses of J. */ 310: p = ®_class_subclasses[j][0]; 311: while (*p != LIM_REG_CLASSES) p++; 312: *p = (enum reg_class) i; 313: } 314: } 1.1.1.4 root 315: 316: /* Initialize the move cost table. Find every subset of each class 317: and take the maximum cost of moving any subset to any other. */ 318: 319: for (i = 0; i < N_REG_CLASSES; i++) 320: for (j = 0; j < N_REG_CLASSES; j++) 321: { 322: int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); 323: enum reg_class *p1, *p2; 324: 325: for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) 326: if (*p2 != i) 327: cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); 328: 329: for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) 330: { 331: if (*p1 != j) 332: cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); 333: 334: for (p2 = ®_class_subclasses[j][0]; 335: *p2 != LIM_REG_CLASSES; p2++) 336: if (*p1 != *p2) 337: cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); 338: } 339: 340: move_cost[i][j] = cost; 341: 342: if (reg_class_subset_p (i, j)) 343: cost = 0; 344: 345: may_move_cost[i][j] = cost; 346: } 1.1 root 347: } 348: 349: /* After switches have been processed, which perhaps alter 350: `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ 351: 352: void 353: init_reg_sets_1 () 354: { 355: register int i; 356: 357: /* This macro allows the fixed or call-used registers 358: to depend on target flags. */ 359: 360: #ifdef CONDITIONAL_REGISTER_USAGE 361: CONDITIONAL_REGISTER_USAGE; 362: #endif 363: 364: /* Initialize "constant" tables. */ 365: 366: CLEAR_HARD_REG_SET (fixed_reg_set); 367: CLEAR_HARD_REG_SET (call_used_reg_set); 368: CLEAR_HARD_REG_SET (call_fixed_reg_set); 369: 370: bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); 371: #ifdef STRUCT_VALUE_REGNUM 372: call_fixed_regs[STRUCT_VALUE_REGNUM] = 1; 373: #endif 374: #ifdef STATIC_CHAIN_REGNUM 375: call_fixed_regs[STATIC_CHAIN_REGNUM] = 1; 376: #endif 377: 378: n_non_fixed_regs = 0; 379: 380: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 381: { 382: if (FUNCTION_VALUE_REGNO_P (i)) 383: call_fixed_regs[i] = 1; 384: if (fixed_regs[i]) 385: SET_HARD_REG_BIT (fixed_reg_set, i); 386: else 387: n_non_fixed_regs++; 388: 389: if (call_used_regs[i]) 390: SET_HARD_REG_BIT (call_used_reg_set, i); 391: if (call_fixed_regs[i]) 392: SET_HARD_REG_BIT (call_fixed_reg_set, i); 393: } 394: } 395: 396: /* Specify the usage characteristics of the register named NAME. 397: It should be a fixed register if FIXED and a 398: call-used register if CALL_USED. */ 399: 400: void 401: fix_register (name, fixed, call_used) 402: char *name; 403: int fixed, call_used; 404: { 405: int i; 406: 1.1.1.6 ! root 407: if (output_bytecode) ! 408: { ! 409: warning ("request to mark `%s' as %s ignored by bytecode compiler", ! 410: name, call_used ? "call-used" : "fixed"); ! 411: return; ! 412: } ! 413: 1.1 root 414: /* Decode the name and update the primary form of 415: the register info. */ 416: 1.1.1.2 root 417: if ((i = decode_reg_name (name)) >= 0) 418: { 419: fixed_regs[i] = fixed; 420: call_used_regs[i] = call_used; 421: } 422: else 1.1 root 423: { 424: warning ("unknown register name: %s", name); 425: } 426: } 1.1.1.6 ! root 427: ! 428: /* Mark register number I as global. */ ! 429: ! 430: void ! 431: globalize_reg (i) ! 432: int i; ! 433: { ! 434: if (global_regs[i]) ! 435: { ! 436: warning ("register used for two global register variables"); ! 437: return; ! 438: } ! 439: ! 440: if (call_used_regs[i] && ! fixed_regs[i]) ! 441: warning ("call-clobbered register used for global register variable"); ! 442: ! 443: global_regs[i] = 1; ! 444: ! 445: /* If already fixed, nothing else to do. */ ! 446: if (fixed_regs[i]) ! 447: return; ! 448: ! 449: fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; ! 450: n_non_fixed_regs--; ! 451: ! 452: SET_HARD_REG_BIT (fixed_reg_set, i); ! 453: SET_HARD_REG_BIT (call_used_reg_set, i); ! 454: SET_HARD_REG_BIT (call_fixed_reg_set, i); ! 455: } 1.1 root 456: 457: /* Now the data and code for the `regclass' pass, which happens 458: just before local-alloc. */ 459: 1.1.1.4 root 460: /* The `costs' struct records the cost of using a hard register of each class 461: and of using memory for each pseudo. We use this data to set up 462: register class preferences. */ 1.1 root 463: 1.1.1.4 root 464: struct costs 1.1 root 465: { 1.1.1.4 root 466: int cost[N_REG_CLASSES]; 467: int mem_cost; 1.1 root 468: }; 469: 1.1.1.4 root 470: /* Record the cost of each class for each pseudo. */ 471: 472: static struct costs *costs; 473: 474: /* Record the same data by operand number, accumulated for each alternative 475: in an insn. The contribution to a pseudo is that of the minimum-cost 476: alternative. */ 477: 478: static struct costs op_costs[MAX_RECOG_OPERANDS]; 1.1 root 479: 480: /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. 481: This is available after `regclass' is run. */ 482: 483: static char *prefclass; 484: 1.1.1.4 root 485: /* altclass[R] is a register class that we should use for allocating 486: pseudo number R if no register in the preferred class is available. 487: If no register in this class is available, memory is preferred. 488: 489: It might appear to be more general to have a bitmask of classes here, 490: but since it is recommended that there be a class corresponding to the 491: union of most major pair of classes, that generality is not required. 492: 1.1 root 493: This is available after `regclass' is run. */ 494: 1.1.1.4 root 495: static char *altclass; 1.1 root 496: 1.1.1.4 root 497: /* Record the depth of loops that we are in. */ 1.1 root 498: 499: static int loop_depth; 500: 1.1.1.4 root 501: /* Account for the fact that insns within a loop are executed very commonly, 502: but don't keep doing this as loops go too deep. */ 503: 504: static int loop_cost; 505: 506: static int copy_cost (); 507: static void record_reg_classes (); 508: static void record_address_regs (); 1.1 root 509: 510: 511: /* Return the reg_class in which pseudo reg number REGNO is best allocated. 512: This function is sometimes called before the info has been computed. 513: When that happens, just return GENERAL_REGS, which is innocuous. */ 514: 515: enum reg_class 516: reg_preferred_class (regno) 517: int regno; 518: { 519: if (prefclass == 0) 520: return GENERAL_REGS; 521: return (enum reg_class) prefclass[regno]; 522: } 523: 1.1.1.4 root 524: enum reg_class 525: reg_alternate_class (regno) 1.1 root 526: { 527: if (prefclass == 0) 1.1.1.4 root 528: return ALL_REGS; 529: 530: return (enum reg_class) altclass[regno]; 1.1 root 531: } 532: 533: /* This prevents dump_flow_info from losing if called 534: before regclass is run. */ 535: 536: void 537: regclass_init () 538: { 539: prefclass = 0; 540: } 541: 542: /* This is a pass of the compiler that scans all instructions 543: and calculates the preferred class for each pseudo-register. 544: This information can be accessed later by calling `reg_preferred_class'. 545: This pass comes just before local register allocation. */ 546: 547: void 548: regclass (f, nregs) 549: rtx f; 550: int nregs; 551: { 552: #ifdef REGISTER_CONSTRAINTS 553: register rtx insn; 1.1.1.4 root 554: register int i, j; 555: struct costs init_cost; 556: rtx set; 557: int pass; 1.1 root 558: 559: init_recog (); 560: 1.1.1.4 root 561: costs = (struct costs *) alloca (nregs * sizeof (struct costs)); 1.1 root 562: 1.1.1.4 root 563: #ifdef FORBIDDEN_INC_DEC_CLASSES 1.1 root 564: 1.1.1.4 root 565: in_inc_dec = (char *) alloca (nregs); 1.1 root 566: 1.1.1.4 root 567: /* Initialize information about which register classes can be used for 568: pseudos that are auto-incremented or auto-decremented. It would 569: seem better to put this in init_reg_sets, but we need to be able 570: to allocate rtx, which we can't do that early. */ 1.1 root 571: 1.1.1.4 root 572: for (i = 0; i < N_REG_CLASSES; i++) 1.1 root 573: { 1.1.1.4 root 574: rtx r = gen_rtx (REG, VOIDmode, 0); 575: enum machine_mode m; 1.1 root 576: 1.1.1.4 root 577: for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 578: if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 579: { 580: REGNO (r) = j; 1.1 root 581: 1.1.1.4 root 582: for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; 1.1.1.5 root 583: m = (enum machine_mode) ((int) m + 1)) 1.1.1.4 root 584: if (HARD_REGNO_MODE_OK (j, m)) 585: { 586: PUT_MODE (r, m); 587: if (0 588: #ifdef SECONDARY_INPUT_RELOAD_CLASS 589: || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) 590: != NO_REGS) 591: #endif 592: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS 593: || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) 594: != NO_REGS) 595: #endif 596: ) 597: forbidden_inc_dec_class[i] = 1; 598: } 599: } 600: } 601: #endif /* FORBIDDEN_INC_DEC_CLASSES */ 1.1 root 602: 1.1.1.4 root 603: init_cost.mem_cost = 10000; 604: for (i = 0; i < N_REG_CLASSES; i++) 605: init_cost.cost[i] = 10000; 606: 607: /* Normally we scan the insns once and determine the best class to use for 608: each register. However, if -fexpensive_optimizations are on, we do so 609: twice, the second time using the tentative best classes to guide the 610: selection. */ 1.1 root 611: 1.1.1.4 root 612: for (pass = 0; pass <= flag_expensive_optimizations; pass++) 613: { 614: /* Zero out our accumulation of the cost of each class for each reg. */ 615: 616: bzero (costs, nregs * sizeof (struct costs)); 617: 618: #ifdef FORBIDDEN_INC_DEC_CLASSES 619: bzero (in_inc_dec, nregs); 620: #endif 1.1 root 621: 1.1.1.4 root 622: loop_depth = 0, loop_cost = 1; 623: 624: /* Scan the instructions and record each time it would 625: save code to put a certain register in a certain class. */ 626: 627: for (insn = f; insn; insn = NEXT_INSN (insn)) 628: { 629: char *constraints[MAX_RECOG_OPERANDS]; 630: enum machine_mode modes[MAX_RECOG_OPERANDS]; 631: int nalternatives; 632: int noperands; 633: 634: /* Show that an insn inside a loop is likely to be executed three 1.1.1.5 root 635: times more than insns outside a loop. This is much more aggressive 1.1.1.4 root 636: than the assumptions made elsewhere and is being tried as an 637: experiment. */ 638: 639: if (GET_CODE (insn) == NOTE 640: && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) 641: loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); 642: else if (GET_CODE (insn) == NOTE 643: && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) 644: loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); 645: 646: else if ((GET_CODE (insn) == INSN 647: && GET_CODE (PATTERN (insn)) != USE 648: && GET_CODE (PATTERN (insn)) != CLOBBER 649: && GET_CODE (PATTERN (insn)) != ASM_INPUT) 650: || (GET_CODE (insn) == JUMP_INSN 651: && GET_CODE (PATTERN (insn)) != ADDR_VEC 652: && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) 653: || GET_CODE (insn) == CALL_INSN) 654: { 655: if (GET_CODE (insn) == INSN 656: && (noperands = asm_noperands (PATTERN (insn))) >= 0) 1.1 root 657: { 1.1.1.4 root 658: decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR, 659: constraints, modes); 660: nalternatives = (noperands == 0 ? 0 661: : n_occurrences (',', constraints[0]) + 1); 1.1 root 662: } 1.1.1.4 root 663: else 1.1 root 664: { 1.1.1.4 root 665: int insn_code_number = recog_memoized (insn); 666: rtx note; 667: 668: set = single_set (insn); 669: insn_extract (insn); 1.1 root 670: 1.1.1.4 root 671: nalternatives = insn_n_alternatives[insn_code_number]; 672: noperands = insn_n_operands[insn_code_number]; 673: 674: /* If this insn loads a parameter from its stack slot, then 675: it represents a savings, rather than a cost, if the 676: parameter is stored in memory. Record this fact. */ 677: 678: if (set != 0 && GET_CODE (SET_DEST (set)) == REG 679: && GET_CODE (SET_SRC (set)) == MEM 680: && (note = find_reg_note (insn, REG_EQUIV, 681: NULL_RTX)) != 0 682: && GET_CODE (XEXP (note, 0)) == MEM) 683: { 684: costs[REGNO (SET_DEST (set))].mem_cost 685: -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set))) 686: * loop_cost); 687: record_address_regs (XEXP (SET_SRC (set), 0), 688: BASE_REG_CLASS, loop_cost * 2); 689: continue; 690: } 691: 692: /* Improve handling of two-address insns such as 693: (set X (ashift CONST Y)) where CONST must be made to 694: match X. Change it into two insns: (set X CONST) 695: (set X (ashift X Y)). If we left this for reloading, it 696: would probably get three insns because X and Y might go 697: in the same place. This prevents X and Y from receiving 698: the same hard reg. 699: 700: We can only do this if the modes of operands 0 and 1 701: (which might not be the same) are tieable and we only need 702: do this during our first pass. */ 703: 704: if (pass == 0 && optimize 705: && noperands >= 3 706: && insn_operand_constraint[insn_code_number][1][0] == '0' 707: && insn_operand_constraint[insn_code_number][1][1] == 0 708: && CONSTANT_P (recog_operand[1]) 709: && ! rtx_equal_p (recog_operand[0], recog_operand[1]) 710: && ! rtx_equal_p (recog_operand[0], recog_operand[2]) 711: && GET_CODE (recog_operand[0]) == REG 712: && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), 713: insn_operand_mode[insn_code_number][1])) 1.1 root 714: { 1.1.1.4 root 715: rtx previnsn = prev_real_insn (insn); 716: rtx dest 717: = gen_lowpart (insn_operand_mode[insn_code_number][1], 718: recog_operand[0]); 719: rtx newinsn 720: = emit_insn_before (gen_move_insn (dest, 721: recog_operand[1]), 722: insn); 723: 724: /* If this insn was the start of a basic block, 725: include the new insn in that block. 726: We need not check for code_label here; 727: while a basic block can start with a code_label, 728: INSN could not be at the beginning of that block. */ 729: if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) 730: { 731: int b; 732: for (b = 0; b < n_basic_blocks; b++) 733: if (insn == basic_block_head[b]) 734: basic_block_head[b] = newinsn; 735: } 736: 737: /* This makes one more setting of new insns's dest. */ 738: reg_n_sets[REGNO (recog_operand[0])]++; 739: 740: *recog_operand_loc[1] = recog_operand[0]; 741: for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) 742: if (recog_dup_num[i] == 1) 743: *recog_dup_loc[i] = recog_operand[0]; 744: 745: insn = PREV_INSN (newinsn); 746: continue; 1.1 root 747: } 748: 1.1.1.4 root 749: for (i = 0; i < noperands; i++) 750: { 751: constraints[i] 752: = insn_operand_constraint[insn_code_number][i]; 753: modes[i] = insn_operand_mode[insn_code_number][i]; 754: } 1.1 root 755: } 1.1.1.4 root 756: 757: /* If we get here, we are set up to record the costs of all the 758: operands for this insn. Start by initializing the costs. 759: Then handle any address registers. Finally record the desired 760: classes for any pseudos, doing it twice if some pair of 761: operands are commutative. */ 762: 763: for (i = 0; i < noperands; i++) 764: { 765: op_costs[i] = init_cost; 766: 767: if (GET_CODE (recog_operand[i]) == SUBREG) 768: recog_operand[i] = SUBREG_REG (recog_operand[i]); 769: 770: if (GET_CODE (recog_operand[i]) == MEM) 771: record_address_regs (XEXP (recog_operand[i], 0), 772: BASE_REG_CLASS, loop_cost * 2); 773: else if (constraints[i][0] == 'p') 774: record_address_regs (recog_operand[i], 775: BASE_REG_CLASS, loop_cost * 2); 776: } 777: 778: /* Check for commutative in a separate loop so everything will 1.1.1.6 ! root 779: have been initialized. We must do this even if one operand ! 780: is a constant--see addsi3 in m68k.md. */ 1.1.1.4 root 781: 782: for (i = 0; i < noperands - 1; i++) 1.1.1.6 ! root 783: if (constraints[i][0] == '%') 1.1.1.4 root 784: { 785: char *xconstraints[MAX_RECOG_OPERANDS]; 786: int j; 787: 788: /* Handle commutative operands by swapping the constraints. 789: We assume the modes are the same. */ 790: 791: for (j = 0; j < noperands; j++) 792: xconstraints[j] = constraints[j]; 793: 794: xconstraints[i] = constraints[i+1]; 795: xconstraints[i+1] = constraints[i]; 796: record_reg_classes (nalternatives, noperands, 797: recog_operand, modes, xconstraints, 798: insn); 799: } 800: 801: record_reg_classes (nalternatives, noperands, recog_operand, 802: modes, constraints, insn); 803: 804: /* Now add the cost for each operand to the total costs for 805: its register. */ 806: 807: for (i = 0; i < noperands; i++) 808: if (GET_CODE (recog_operand[i]) == REG 809: && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) 810: { 811: int regno = REGNO (recog_operand[i]); 812: struct costs *p = &costs[regno], *q = &op_costs[i]; 813: 814: p->mem_cost += q->mem_cost * loop_cost; 815: for (j = 0; j < N_REG_CLASSES; j++) 816: p->cost[j] += q->cost[j] * loop_cost; 817: } 1.1 root 818: } 819: } 820: 1.1.1.4 root 821: /* Now for each register look at how desirable each class is 822: and find which class is preferred. Store that in 823: `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register 824: class any of whose registers is better than memory. */ 1.1 root 825: 1.1.1.4 root 826: if (pass == 0) 827: { 828: prefclass = (char *) oballoc (nregs); 829: altclass = (char *) oballoc (nregs); 830: } 1.1 root 831: 1.1.1.4 root 832: for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) 1.1 root 833: { 1.1.1.4 root 834: register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; 835: enum reg_class best = ALL_REGS, alt = NO_REGS; 836: /* This is an enum reg_class, but we call it an int 837: to save lots of casts. */ 838: register int class; 839: register struct costs *p = &costs[i]; 840: 841: for (class = (int) ALL_REGS - 1; class > 0; class--) 1.1 root 842: { 1.1.1.4 root 843: /* Ignore classes that are too small for this operand or 844: invalid for a operand that was auto-incremented. */ 845: if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) 846: > reg_class_size[class] 847: #ifdef FORBIDDEN_INC_DEC_CLASSES 848: || (in_inc_dec[i] && forbidden_inc_dec_class[class]) 849: #endif 850: ) 851: ; 852: else if (p->cost[class] < best_cost) 853: { 854: best_cost = p->cost[class]; 855: best = (enum reg_class) class; 856: } 857: else if (p->cost[class] == best_cost) 858: best = reg_class_subunion[(int)best][class]; 1.1 root 859: } 860: 1.1.1.4 root 861: /* Record the alternate register class; i.e., a class for which 862: every register in it is better than using memory. If adding a 863: class would make a smaller class (i.e., no union of just those 864: classes exists), skip that class. The major unions of classes 865: should be provided as a register class. Don't do this if we 866: will be doing it again later. */ 867: 868: if (pass == 1 || ! flag_expensive_optimizations) 869: for (class = 0; class < N_REG_CLASSES; class++) 870: if (p->cost[class] < p->mem_cost 871: && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] 872: > reg_class_size[(int) alt]) 873: #ifdef FORBIDDEN_INC_DEC_CLASSES 874: && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1.1 root 875: #endif 1.1.1.4 root 876: ) 877: alt = reg_class_subunion[(int) alt][class]; 878: 879: /* If we don't add any classes, nothing to try. */ 880: if (alt == best) 881: alt = (int) NO_REGS; 882: 883: /* We cast to (int) because (char) hits bugs in some compilers. */ 884: prefclass[i] = (int) best; 885: altclass[i] = (int) alt; 886: } 1.1 root 887: } 888: #endif /* REGISTER_CONSTRAINTS */ 889: } 890: 891: #ifdef REGISTER_CONSTRAINTS 892: 1.1.1.4 root 893: /* Record the cost of using memory or registers of various classes for 894: the operands in INSN. 1.1 root 895: 1.1.1.4 root 896: N_ALTS is the number of alternatives. 1.1 root 897: 1.1.1.4 root 898: N_OPS is the number of operands. 1.1 root 899: 1.1.1.4 root 900: OPS is an array of the operands. 1.1 root 901: 1.1.1.4 root 902: MODES are the modes of the operands, in case any are VOIDmode. 1.1 root 903: 1.1.1.4 root 904: CONSTRAINTS are the constraints to use for the operands. This array 905: is modified by this procedure. 1.1 root 906: 1.1.1.4 root 907: This procedure works alternative by alternative. For each alternative 908: we assume that we will be able to allocate all pseudos to their ideal 909: register class and calculate the cost of using that alternative. Then 910: we compute for each operand that is a pseudo-register, the cost of 911: having the pseudo allocated to each register class and using it in that 912: alternative. To this cost is added the cost of the alternative. 1.1 root 913: 1.1.1.4 root 914: The cost of each class for this insn is its lowest cost among all the 915: alternatives. */ 916: 917: static void 918: record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) 919: int n_alts; 920: int n_ops; 921: rtx *ops; 922: enum machine_mode *modes; 923: char **constraints; 924: rtx insn; 925: { 926: int alt; 927: enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS]; 928: int i, j; 929: 930: /* By default, each operand is an input operand. */ 931: 932: for (i = 0; i < n_ops; i++) 933: op_types[i] = OP_READ; 1.1 root 934: 1.1.1.4 root 935: /* Process each alternative, each time minimizing an operand's cost with 936: the cost for each operand in that alternative. */ 1.1 root 937: 1.1.1.4 root 938: for (alt = 0; alt < n_alts; alt++) 1.1 root 939: { 1.1.1.4 root 940: struct costs this_op_costs[MAX_RECOG_OPERANDS]; 941: int alt_fail = 0; 942: int alt_cost = 0; 943: enum reg_class classes[MAX_RECOG_OPERANDS]; 944: int class; 1.1 root 945: 1.1.1.4 root 946: for (i = 0; i < n_ops; i++) 1.1 root 947: { 1.1.1.4 root 948: char *p = constraints[i]; 949: rtx op = ops[i]; 950: enum machine_mode mode = modes[i]; 951: int allows_mem = 0; 952: int win = 0; 953: char c; 954: 955: /* If this operand has no constraints at all, we can conclude 956: nothing about it since anything is valid. */ 957: 958: if (*p == 0) 1.1 root 959: { 1.1.1.4 root 960: if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 961: bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); 962: 963: continue; 1.1 root 964: } 965: 1.1.1.4 root 966: if (*p == '%') 967: p++; 1.1 root 968: 1.1.1.4 root 969: /* If this alternative is only relevant when this operand 970: matches a previous operand, we do different things depending 971: on whether this operand is a pseudo-reg or not. */ 972: 973: if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) 974: { 975: j = p[0] - '0'; 976: classes[i] = classes[j]; 1.1 root 977: 1.1.1.4 root 978: if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) 979: { 980: /* If this matches the other operand, we have no added 981: cost. */ 982: if (rtx_equal_p (ops[j], op)) 983: ; 984: 1.1.1.5 root 985: /* If we can put the other operand into a register, add to 986: the cost of this alternative the cost to copy this 987: operand to the register used for the other operand. */ 1.1.1.4 root 988: 1.1.1.5 root 989: if (classes[j] != NO_REGS) 990: alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; 1.1.1.4 root 991: } 992: else if (GET_CODE (ops[j]) != REG 993: || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) 994: { 995: /* This op is a pseudo but the one it matches is not. */ 996: 997: /* If we can't put the other operand into a register, this 998: alternative can't be used. */ 999: 1000: if (classes[j] == NO_REGS) 1001: alt_fail = 1; 1002: 1003: /* Otherwise, add to the cost of this alternative the cost 1004: to copy the other operand to the register used for this 1005: operand. */ 1.1 root 1006: 1.1.1.4 root 1007: else 1008: alt_cost += copy_cost (ops[j], mode, classes[j], 1); 1009: } 1010: else 1011: { 1012: /* The costs of this operand are the same as that of the 1013: other operand. However, if we cannot tie them, this 1014: alternative needs to do a copy, which is one 1015: instruction. */ 1016: 1017: this_op_costs[i] = this_op_costs[j]; 1.1.1.6 ! root 1018: if (REGNO (ops[i]) != REGNO (ops[j]) ! 1019: && ! find_reg_note (insn, REG_DEAD, op)) 1.1.1.4 root 1020: alt_cost += 2; 1021: 1022: /* This is in place of ordinary cost computation 1.1.1.6 ! root 1023: for this operand, so skip to the end of the ! 1024: alternative (should be just one character). */ ! 1025: while (*p && *p++ != ',') ! 1026: ; ! 1027: ! 1028: constraints[i] = p; 1.1.1.4 root 1029: continue; 1030: } 1031: } 1.1 root 1032: 1.1.1.4 root 1033: /* Scan all the constraint letters. See if the operand matches 1034: any of the constraints. Collect the valid register classes 1035: and see if this operand accepts memory. */ 1036: 1037: classes[i] = NO_REGS; 1038: while (*p && (c = *p++) != ',') 1039: switch (c) 1.1 root 1040: { 1.1.1.4 root 1041: case '=': 1042: op_types[i] = OP_WRITE; 1043: break; 1044: 1045: case '+': 1046: op_types[i] = OP_READ_WRITE; 1047: break; 1048: 1049: case '*': 1050: /* Ignore the next letter for this pass. */ 1051: p++; 1052: break; 1053: 1054: case '%': 1055: case '?': case '!': case '#': 1056: case '&': 1057: case '0': case '1': case '2': case '3': case '4': 1058: case 'p': 1059: break; 1060: 1061: case 'm': case 'o': case 'V': 1.1.1.5 root 1062: /* It doesn't seem worth distinguishing between offsettable 1.1.1.4 root 1063: and non-offsettable addresses here. */ 1064: allows_mem = 1; 1065: if (GET_CODE (op) == MEM) 1066: win = 1; 1067: break; 1068: 1069: case '<': 1070: if (GET_CODE (op) == MEM 1071: && (GET_CODE (XEXP (op, 0)) == PRE_DEC 1072: || GET_CODE (XEXP (op, 0)) == POST_DEC)) 1073: win = 1; 1074: break; 1075: 1076: case '>': 1077: if (GET_CODE (op) == MEM 1078: && (GET_CODE (XEXP (op, 0)) == PRE_INC 1079: || GET_CODE (XEXP (op, 0)) == POST_INC)) 1080: win = 1; 1081: break; 1082: 1083: case 'E': 1084: /* Match any floating double constant, but only if 1085: we can examine the bits of it reliably. */ 1086: if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT 1087: || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) 1088: && GET_MODE (op) != VOIDmode && ! flag_pretend_float) 1089: break; 1090: if (GET_CODE (op) == CONST_DOUBLE) 1091: win = 1; 1092: break; 1093: 1094: case 'F': 1095: if (GET_CODE (op) == CONST_DOUBLE) 1096: win = 1; 1097: break; 1098: 1099: case 'G': 1100: case 'H': 1101: if (GET_CODE (op) == CONST_DOUBLE 1102: && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) 1103: win = 1; 1104: break; 1105: 1106: case 's': 1107: if (GET_CODE (op) == CONST_INT 1108: || (GET_CODE (op) == CONST_DOUBLE 1109: && GET_MODE (op) == VOIDmode)) 1.1 root 1110: break; 1.1.1.4 root 1111: case 'i': 1112: if (CONSTANT_P (op) 1113: #ifdef LEGITIMATE_PIC_OPERAND_P 1114: && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1115: #endif 1116: ) 1117: win = 1; 1118: break; 1119: 1120: case 'n': 1121: if (GET_CODE (op) == CONST_INT 1122: || (GET_CODE (op) == CONST_DOUBLE 1123: && GET_MODE (op) == VOIDmode)) 1124: win = 1; 1125: break; 1126: 1127: case 'I': 1128: case 'J': 1129: case 'K': 1130: case 'L': 1131: case 'M': 1132: case 'N': 1133: case 'O': 1134: case 'P': 1135: if (GET_CODE (op) == CONST_INT 1136: && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) 1137: win = 1; 1138: break; 1139: 1140: case 'X': 1141: win = 1; 1142: break; 1143: 1144: #ifdef EXTRA_CONSTRAINT 1145: case 'Q': 1146: case 'R': 1147: case 'S': 1148: case 'T': 1149: case 'U': 1150: if (EXTRA_CONSTRAINT (op, c)) 1151: win = 1; 1152: break; 1153: #endif 1154: 1155: case 'g': 1156: if (GET_CODE (op) == MEM 1157: || (CONSTANT_P (op) 1158: #ifdef LEGITIMATE_PIC_OPERAND_P 1159: && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1160: #endif 1161: )) 1162: win = 1; 1163: allows_mem = 1; 1164: case 'r': 1165: classes[i] 1166: = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; 1167: break; 1168: 1169: default: 1170: classes[i] 1171: = reg_class_subunion[(int) classes[i]] 1172: [(int) REG_CLASS_FROM_LETTER (c)]; 1.1 root 1173: } 1174: 1.1.1.4 root 1175: constraints[i] = p; 1176: 1177: /* How we account for this operand now depends on whether it is a 1178: pseudo register or not. If it is, we first check if any 1179: register classes are valid. If not, we ignore this alternative, 1180: since we want to assume that all pseudos get allocated for 1181: register preferencing. If some register class is valid, compute 1182: the costs of moving the pseudo into that class. */ 1183: 1184: if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1185: { 1186: if (classes[i] == NO_REGS) 1187: alt_fail = 1; 1188: else 1189: { 1190: struct costs *pp = &this_op_costs[i]; 1191: 1192: for (class = 0; class < N_REG_CLASSES; class++) 1193: pp->cost[class] = may_move_cost[class][(int) classes[i]]; 1194: 1195: /* If the alternative actually allows memory, make things 1196: a bit cheaper since we won't need an extra insn to 1197: load it. */ 1198: 1199: pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem; 1200: 1201: /* If we have assigned a class to this register in our 1202: first pass, add a cost to this alternative corresponding 1203: to what we would add if this register were not in the 1204: appropriate class. */ 1205: 1206: if (prefclass) 1207: alt_cost 1208: += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]]; 1209: } 1210: } 1211: 1212: /* Otherwise, if this alternative wins, either because we 1213: have already determined that or if we have a hard register of 1214: the proper class, there is no cost for this alternative. */ 1215: 1216: else if (win 1217: || (GET_CODE (op) == REG 1218: && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) 1219: ; 1220: 1221: /* If registers are valid, the cost of this alternative includes 1222: copying the object to and/or from a register. */ 1223: 1224: else if (classes[i] != NO_REGS) 1225: { 1226: if (op_types[i] != OP_WRITE) 1227: alt_cost += copy_cost (op, mode, classes[i], 1); 1228: 1229: if (op_types[i] != OP_READ) 1230: alt_cost += copy_cost (op, mode, classes[i], 0); 1231: } 1232: 1233: /* The only other way this alternative can be used is if this is a 1234: constant that could be placed into memory. */ 1.1 root 1235: 1.1.1.4 root 1236: else if (CONSTANT_P (op) && allows_mem) 1237: alt_cost += MEMORY_MOVE_COST (mode); 1238: else 1239: alt_fail = 1; 1240: } 1241: 1242: if (alt_fail) 1243: continue; 1244: 1245: /* Finally, update the costs with the information we've calculated 1246: about this alternative. */ 1247: 1248: for (i = 0; i < n_ops; i++) 1249: if (GET_CODE (ops[i]) == REG 1250: && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1251: { 1252: struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; 1253: int scale = 1 + (op_types[i] == OP_READ_WRITE); 1254: 1255: pp->mem_cost = MIN (pp->mem_cost, 1256: (qq->mem_cost + alt_cost) * scale); 1257: 1258: for (class = 0; class < N_REG_CLASSES; class++) 1259: pp->cost[class] = MIN (pp->cost[class], 1260: (qq->cost[class] + alt_cost) * scale); 1261: } 1262: } 1.1 root 1263: } 1.1.1.4 root 1264: 1265: /* Compute the cost of loading X into (if TO_P is non-zero) or from (if 1266: TO_P is zero) a register of class CLASS in mode MODE. 1267: 1268: X must not be a pseudo. */ 1269: 1270: static int 1271: copy_cost (x, mode, class, to_p) 1272: rtx x; 1273: enum machine_mode mode; 1274: enum reg_class class; 1275: int to_p; 1276: { 1277: enum reg_class secondary_class = NO_REGS; 1278: 1279: /* If X is a SCRATCH, there is actually nothing to move since we are 1280: assuming optimal allocation. */ 1281: 1282: if (GET_CODE (x) == SCRATCH) 1283: return 0; 1284: 1285: /* Get the class we will actually use for a reload. */ 1286: class = PREFERRED_RELOAD_CLASS (x, class); 1287: 1288: #ifdef HAVE_SECONDARY_RELOADS 1289: /* If we need a secondary reload (we assume here that we are using 1290: the secondary reload as an intermediate, not a scratch register), the 1291: cost is that to load the input into the intermediate register, then 1292: to copy them. We use a special value of TO_P to avoid recursion. */ 1293: 1294: #ifdef SECONDARY_INPUT_RELOAD_CLASS 1295: if (to_p == 1) 1296: secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); 1297: #endif 1.1 root 1298: 1.1.1.4 root 1299: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1300: if (! to_p) 1301: secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); 1302: #endif 1303: 1304: if (secondary_class != NO_REGS) 1305: return (move_cost[(int) secondary_class][(int) class] 1306: + copy_cost (x, mode, secondary_class, 2)); 1307: #endif /* HAVE_SECONDARY_RELOADS */ 1308: 1309: /* For memory, use the memory move cost, for (hard) registers, use the 1310: cost to move between the register classes, and use 2 for everything 1311: else (constants). */ 1312: 1313: if (GET_CODE (x) == MEM || class == NO_REGS) 1314: return MEMORY_MOVE_COST (mode); 1315: 1316: else if (GET_CODE (x) == REG) 1317: return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; 1318: 1319: else 1320: /* If this is a constant, we may eventually want to call rtx_cost here. */ 1321: return 2; 1322: } 1323: 1.1 root 1324: /* Record the pseudo registers we must reload into hard registers 1325: in a subexpression of a memory address, X. 1326: 1.1.1.4 root 1327: CLASS is the class that the register needs to be in and is either 1328: BASE_REG_CLASS or INDEX_REG_CLASS. 1329: 1330: SCALE is twice the amount to multiply the cost by (it is twice so we 1331: can represent half-cost adjustments). */ 1332: 1333: static void 1334: record_address_regs (x, class, scale) 1.1 root 1335: rtx x; 1.1.1.4 root 1336: enum reg_class class; 1337: int scale; 1.1 root 1338: { 1339: register enum rtx_code code = GET_CODE (x); 1340: 1341: switch (code) 1342: { 1343: case CONST_INT: 1344: case CONST: 1345: case CC0: 1346: case PC: 1347: case SYMBOL_REF: 1348: case LABEL_REF: 1349: return; 1350: 1351: case PLUS: 1352: /* When we have an address that is a sum, 1353: we must determine whether registers are "base" or "index" regs. 1354: If there is a sum of two registers, we must choose one to be 1355: the "base". Luckily, we can use the REGNO_POINTER_FLAG 1.1.1.4 root 1356: to make a good choice most of the time. We only need to do this 1357: on machines that can have two registers in an address and where 1358: the base and index register classes are different. 1359: 1360: ??? This code used to set REGNO_POINTER_FLAG in some cases, but 1361: that seems bogus since it should only be set when we are sure 1362: the register is being used as a pointer. */ 1363: 1.1 root 1364: { 1365: rtx arg0 = XEXP (x, 0); 1366: rtx arg1 = XEXP (x, 1); 1367: register enum rtx_code code0 = GET_CODE (arg0); 1368: register enum rtx_code code1 = GET_CODE (arg1); 1369: 1370: /* Look inside subregs. */ 1.1.1.4 root 1371: if (code0 == SUBREG) 1.1 root 1372: arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); 1.1.1.4 root 1373: if (code1 == SUBREG) 1.1 root 1374: arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); 1375: 1.1.1.4 root 1376: /* If this machine only allows one register per address, it must 1377: be in the first operand. */ 1378: 1379: if (MAX_REGS_PER_ADDRESS == 1) 1380: record_address_regs (arg0, class, scale); 1381: 1382: /* If index and base registers are the same on this machine, just 1383: record registers in any non-constant operands. We assume here, 1384: as well as in the tests below, that all addresses are in 1385: canonical form. */ 1386: 1387: else if (INDEX_REG_CLASS == BASE_REG_CLASS) 1.1 root 1388: { 1.1.1.4 root 1389: record_address_regs (arg0, class, scale); 1390: if (! CONSTANT_P (arg1)) 1391: record_address_regs (arg1, class, scale); 1.1 root 1392: } 1.1.1.4 root 1393: 1394: /* If the second operand is a constant integer, it doesn't change 1395: what class the first operand must be. */ 1396: 1397: else if (code1 == CONST_INT || code1 == CONST_DOUBLE) 1398: record_address_regs (arg0, class, scale); 1399: 1400: /* If the second operand is a symbolic constant, the first operand 1401: must be an index register. */ 1402: 1403: else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) 1404: record_address_regs (arg0, INDEX_REG_CLASS, scale); 1405: 1406: /* If this the sum of two registers where the first is known to be a 1407: pointer, it must be a base register with the second an index. */ 1408: 1409: else if (code0 == REG && code1 == REG 1410: && REGNO_POINTER_FLAG (REGNO (arg0))) 1.1 root 1411: { 1.1.1.4 root 1412: record_address_regs (arg0, BASE_REG_CLASS, scale); 1413: record_address_regs (arg1, INDEX_REG_CLASS, scale); 1.1 root 1414: } 1.1.1.4 root 1415: 1416: /* If this is the sum of two registers and neither is known to 1417: be a pointer, count equal chances that each might be a base 1418: or index register. This case should be rare. */ 1419: 1420: else if (code0 == REG && code1 == REG 1421: && ! REGNO_POINTER_FLAG (REGNO (arg0)) 1422: && ! REGNO_POINTER_FLAG (REGNO (arg1))) 1.1 root 1423: { 1.1.1.4 root 1424: record_address_regs (arg0, BASE_REG_CLASS, scale / 2); 1425: record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); 1426: record_address_regs (arg1, BASE_REG_CLASS, scale / 2); 1427: record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); 1.1 root 1428: } 1429: 1.1.1.4 root 1430: /* In all other cases, the first operand is an index and the 1431: second is the base. */ 1432: 1433: else 1434: { 1435: record_address_regs (arg0, INDEX_REG_CLASS, scale); 1436: record_address_regs (arg1, BASE_REG_CLASS, scale); 1437: } 1.1 root 1438: } 1439: break; 1440: 1441: case POST_INC: 1442: case PRE_INC: 1443: case POST_DEC: 1444: case PRE_DEC: 1445: /* Double the importance of a pseudo register that is incremented 1446: or decremented, since it would take two extra insns 1.1.1.4 root 1447: if it ends up in the wrong place. If the operand is a pseudo, 1448: show it is being used in an INC_DEC context. */ 1449: 1450: #ifdef FORBIDDEN_INC_DEC_CLASSES 1451: if (GET_CODE (XEXP (x, 0)) == REG 1452: && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) 1453: in_inc_dec[REGNO (XEXP (x, 0))] = 1; 1454: #endif 1455: 1456: record_address_regs (XEXP (x, 0), class, 2 * scale); 1.1 root 1457: break; 1458: 1459: case REG: 1460: { 1.1.1.4 root 1461: register struct costs *pp = &costs[REGNO (x)]; 1462: register int i; 1.1 root 1463: 1.1.1.4 root 1464: pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2; 1.1 root 1465: 1.1.1.4 root 1466: for (i = 0; i < N_REG_CLASSES; i++) 1467: pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; 1.1 root 1468: } 1469: break; 1470: 1471: default: 1472: { 1473: register char *fmt = GET_RTX_FORMAT (code); 1474: register int i; 1475: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1476: if (fmt[i] == 'e') 1.1.1.4 root 1477: record_address_regs (XEXP (x, i), class, scale); 1.1 root 1478: } 1479: } 1480: } 1481: #endif /* REGISTER_CONSTRAINTS */ 1482: 1483: /* This is the `regscan' pass of the compiler, run just before cse 1484: and again just before loop. 1485: 1486: It finds the first and last use of each pseudo-register 1487: and records them in the vectors regno_first_uid, regno_last_uid 1488: and counts the number of sets in the vector reg_n_sets. 1489: 1490: REPEAT is nonzero the second time this is called. */ 1491: 1492: /* Indexed by pseudo register number, gives uid of first insn using the reg 1493: (as of the time reg_scan is called). */ 1494: 1.1.1.4 root 1495: int *regno_first_uid; 1.1 root 1496: 1497: /* Indexed by pseudo register number, gives uid of last insn using the reg 1498: (as of the time reg_scan is called). */ 1499: 1.1.1.4 root 1500: int *regno_last_uid; 1.1 root 1501: 1.1.1.6 ! root 1502: /* Indexed by pseudo register number, gives uid of last insn using the reg ! 1503: or mentioning it in a note (as of the time reg_scan is called). */ ! 1504: ! 1505: int *regno_last_note_uid; ! 1506: 1.1 root 1507: /* Record the number of registers we used when we allocated the above two 1508: tables. If we are called again with more than this, we must re-allocate 1509: the tables. */ 1510: 1511: static int highest_regno_in_uid_map; 1512: 1513: /* Maximum number of parallel sets and clobbers in any insn in this fn. 1514: Always at least 3, since the combiner could put that many togetherm 1515: and we want this to remain correct for all the remaining passes. */ 1516: 1517: int max_parallel; 1518: 1519: void reg_scan_mark_refs (); 1520: 1521: void 1522: reg_scan (f, nregs, repeat) 1523: rtx f; 1524: int nregs; 1525: int repeat; 1526: { 1527: register rtx insn; 1528: 1529: if (!repeat || nregs > highest_regno_in_uid_map) 1530: { 1531: /* Leave some spare space in case more regs are allocated. */ 1532: highest_regno_in_uid_map = nregs + nregs / 20; 1533: regno_first_uid 1.1.1.4 root 1534: = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); 1.1 root 1535: regno_last_uid 1.1.1.4 root 1536: = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); 1.1.1.6 ! root 1537: regno_last_note_uid ! 1538: = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); 1.1 root 1539: reg_n_sets 1540: = (short *) oballoc (highest_regno_in_uid_map * sizeof (short)); 1541: } 1542: 1.1.1.4 root 1543: bzero (regno_first_uid, highest_regno_in_uid_map * sizeof (int)); 1544: bzero (regno_last_uid, highest_regno_in_uid_map * sizeof (int)); 1.1.1.6 ! root 1545: bzero (regno_last_note_uid, highest_regno_in_uid_map * sizeof (int)); 1.1 root 1546: bzero (reg_n_sets, highest_regno_in_uid_map * sizeof (short)); 1547: 1548: max_parallel = 3; 1549: 1550: for (insn = f; insn; insn = NEXT_INSN (insn)) 1551: if (GET_CODE (insn) == INSN 1552: || GET_CODE (insn) == CALL_INSN 1553: || GET_CODE (insn) == JUMP_INSN) 1554: { 1555: if (GET_CODE (PATTERN (insn)) == PARALLEL 1556: && XVECLEN (PATTERN (insn), 0) > max_parallel) 1557: max_parallel = XVECLEN (PATTERN (insn), 0); 1.1.1.6 ! root 1558: reg_scan_mark_refs (PATTERN (insn), insn, 0); ! 1559: ! 1560: if (REG_NOTES (insn)) ! 1561: reg_scan_mark_refs (REG_NOTES (insn), insn, 1); 1.1 root 1562: } 1563: } 1564: 1.1.1.6 ! root 1565: /* X is the expression to scan. INSN is the insn it appears in. ! 1566: NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */ ! 1567: 1.1 root 1568: void 1.1.1.6 ! root 1569: reg_scan_mark_refs (x, insn, note_flag) 1.1 root 1570: rtx x; 1.1.1.5 root 1571: rtx insn; 1.1.1.6 ! root 1572: int note_flag; 1.1 root 1573: { 1574: register enum rtx_code code = GET_CODE (x); 1575: register rtx dest; 1.1.1.5 root 1576: register rtx note; 1.1 root 1577: 1578: switch (code) 1579: { 1580: case CONST_INT: 1581: case CONST: 1582: case CONST_DOUBLE: 1583: case CC0: 1584: case PC: 1585: case SYMBOL_REF: 1586: case LABEL_REF: 1587: case ADDR_VEC: 1588: case ADDR_DIFF_VEC: 1589: return; 1590: 1591: case REG: 1592: { 1593: register int regno = REGNO (x); 1594: 1.1.1.6 ! root 1595: regno_last_note_uid[regno] = INSN_UID (insn); ! 1596: if (!note_flag) ! 1597: regno_last_uid[regno] = INSN_UID (insn); 1.1 root 1598: if (regno_first_uid[regno] == 0) 1.1.1.5 root 1599: regno_first_uid[regno] = INSN_UID (insn); 1.1 root 1600: } 1601: break; 1602: 1.1.1.6 ! root 1603: case EXPR_LIST: ! 1604: if (XEXP (x, 0)) ! 1605: reg_scan_mark_refs (XEXP (x, 0), insn, note_flag); ! 1606: if (XEXP (x, 1)) ! 1607: reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); ! 1608: break; ! 1609: ! 1610: case INSN_LIST: ! 1611: if (XEXP (x, 1)) ! 1612: reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); ! 1613: break; ! 1614: 1.1 root 1615: case SET: 1616: /* Count a set of the destination if it is a register. */ 1617: for (dest = SET_DEST (x); 1618: GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART 1619: || GET_CODE (dest) == ZERO_EXTEND; 1620: dest = XEXP (dest, 0)) 1621: ; 1622: 1623: if (GET_CODE (dest) == REG) 1624: reg_n_sets[REGNO (dest)]++; 1625: 1.1.1.5 root 1626: /* If this is setting a pseudo from another pseudo or the sum of a 1627: pseudo and a constant integer and the other pseudo is known to be 1628: a pointer, set the destination to be a pointer as well. 1629: 1630: Likewise if it is setting the destination from an address or from a 1631: value equivalent to an address or to the sum of an address and 1632: something else. 1633: 1634: But don't do any of this if the pseudo corresponds to a user 1635: variable since it should have already been set as a pointer based 1636: on the type. */ 1637: 1638: if (GET_CODE (SET_DEST (x)) == REG 1639: && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER 1640: && ! REG_USERVAR_P (SET_DEST (x)) 1641: && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) 1642: && ((GET_CODE (SET_SRC (x)) == REG 1643: && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) 1644: || ((GET_CODE (SET_SRC (x)) == PLUS 1645: || GET_CODE (SET_SRC (x)) == LO_SUM) 1646: && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 1647: && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 1648: && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) 1649: || GET_CODE (SET_SRC (x)) == CONST 1650: || GET_CODE (SET_SRC (x)) == SYMBOL_REF 1651: || GET_CODE (SET_SRC (x)) == LABEL_REF 1652: || (GET_CODE (SET_SRC (x)) == HIGH 1653: && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST 1654: || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF 1655: || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) 1656: || ((GET_CODE (SET_SRC (x)) == PLUS 1657: || GET_CODE (SET_SRC (x)) == LO_SUM) 1658: && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST 1659: || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF 1660: || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) 1661: || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 1662: && (GET_CODE (XEXP (note, 0)) == CONST 1663: || GET_CODE (XEXP (note, 0)) == SYMBOL_REF 1664: || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) 1665: REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; 1666: 1.1 root 1667: /* ... fall through ... */ 1668: 1669: default: 1670: { 1671: register char *fmt = GET_RTX_FORMAT (code); 1672: register int i; 1673: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1674: { 1675: if (fmt[i] == 'e') 1.1.1.6 ! root 1676: reg_scan_mark_refs (XEXP (x, i), insn, note_flag); 1.1 root 1677: else if (fmt[i] == 'E' && XVEC (x, i) != 0) 1678: { 1679: register int j; 1680: for (j = XVECLEN (x, i) - 1; j >= 0; j--) 1.1.1.6 ! root 1681: reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag); 1.1 root 1682: } 1683: } 1684: } 1685: } 1686: } 1687: 1688: /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 1689: is also in C2. */ 1690: 1691: int 1692: reg_class_subset_p (c1, c2) 1693: register enum reg_class c1; 1694: register enum reg_class c2; 1695: { 1696: if (c1 == c2) return 1; 1697: 1698: if (c2 == ALL_REGS) 1699: win: 1700: return 1; 1701: GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], 1702: reg_class_contents[(int)c2], 1703: win); 1704: return 0; 1705: } 1706: 1707: /* Return nonzero if there is a register that is in both C1 and C2. */ 1708: 1709: int 1710: reg_classes_intersect_p (c1, c2) 1711: register enum reg_class c1; 1712: register enum reg_class c2; 1713: { 1714: #ifdef HARD_REG_SET 1715: register 1716: #endif 1717: HARD_REG_SET c; 1718: 1719: if (c1 == c2) return 1; 1720: 1721: if (c1 == ALL_REGS || c2 == ALL_REGS) 1722: return 1; 1723: 1724: COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); 1725: AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); 1726: 1727: GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); 1728: return 1; 1729: 1730: lose: 1731: return 0; 1732: } 1733:
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