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1.1 root 1: /* Compute register class preferences for pseudo-registers. 1.1.1.7 ! root 2: Copyright (C) 1987, 88, 91, 92, 93, 1994 Free Software Foundation, Inc. 1.1 root 3: 4: This file is part of GNU CC. 5: 6: GNU CC is free software; you can redistribute it and/or modify 7: it under the terms of the GNU General Public License as published by 8: the Free Software Foundation; either version 2, or (at your option) 9: any later version. 10: 11: GNU CC is distributed in the hope that it will be useful, 12: but WITHOUT ANY WARRANTY; without even the implied warranty of 13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14: GNU General Public License for more details. 15: 16: You should have received a copy of the GNU General Public License 17: along with GNU CC; see the file COPYING. If not, write to 18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 19: 20: 21: /* This file contains two passes of the compiler: reg_scan and reg_class. 22: It also defines some tables of information about the hardware registers 23: and a function init_reg_sets to initialize the tables. */ 24: 25: #include "config.h" 26: #include "rtl.h" 27: #include "hard-reg-set.h" 28: #include "flags.h" 29: #include "basic-block.h" 30: #include "regs.h" 31: #include "insn-config.h" 32: #include "recog.h" 1.1.1.4 root 33: #include "reload.h" 34: #include "real.h" 1.1.1.6 root 35: #include "bytecode.h" 1.1 root 36: 37: #ifndef REGISTER_MOVE_COST 38: #define REGISTER_MOVE_COST(x, y) 2 39: #endif 40: 41: #ifndef MEMORY_MOVE_COST 1.1.1.4 root 42: #define MEMORY_MOVE_COST(x) 4 43: #endif 44: 45: /* If we have auto-increment or auto-decrement and we can have secondary 46: reloads, we are not allowed to use classes requiring secondary 47: reloads for psuedos auto-incremented since reload can't handle it. */ 48: 49: #ifdef AUTO_INC_DEC 50: #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) 51: #define FORBIDDEN_INC_DEC_CLASSES 52: #endif 1.1 root 53: #endif 54: 55: /* Register tables used by many passes. */ 56: 57: /* Indexed by hard register number, contains 1 for registers 58: that are fixed use (stack pointer, pc, frame pointer, etc.). 59: These are the registers that cannot be used to allocate 60: a pseudo reg whose life does not cross calls. */ 61: 62: char fixed_regs[FIRST_PSEUDO_REGISTER]; 63: 64: /* Same info as a HARD_REG_SET. */ 65: 66: HARD_REG_SET fixed_reg_set; 67: 68: /* Data for initializing the above. */ 69: 70: static char initial_fixed_regs[] = FIXED_REGISTERS; 71: 72: /* Indexed by hard register number, contains 1 for registers 73: that are fixed use or are clobbered by function calls. 74: These are the registers that cannot be used to allocate 75: a pseudo reg whose life crosses calls. */ 76: 77: char call_used_regs[FIRST_PSEUDO_REGISTER]; 78: 79: /* Same info as a HARD_REG_SET. */ 80: 81: HARD_REG_SET call_used_reg_set; 82: 83: /* Data for initializing the above. */ 84: 85: static char initial_call_used_regs[] = CALL_USED_REGISTERS; 86: 87: /* Indexed by hard register number, contains 1 for registers that are 88: fixed use -- i.e. in fixed_regs -- or a function value return register 89: or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the 90: registers that cannot hold quantities across calls even if we are 91: willing to save and restore them. */ 92: 93: char call_fixed_regs[FIRST_PSEUDO_REGISTER]; 94: 95: /* The same info as a HARD_REG_SET. */ 96: 97: HARD_REG_SET call_fixed_reg_set; 98: 99: /* Number of non-fixed registers. */ 100: 101: int n_non_fixed_regs; 102: 103: /* Indexed by hard register number, contains 1 for registers 104: that are being used for global register decls. 105: These must be exempt from ordinary flow analysis 106: and are also considered fixed. */ 107: 108: char global_regs[FIRST_PSEUDO_REGISTER]; 109: 110: /* Table of register numbers in the order in which to try to use them. */ 111: #ifdef REG_ALLOC_ORDER 112: int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; 113: #endif 114: 115: /* For each reg class, a HARD_REG_SET saying which registers are in it. */ 116: 1.1.1.4 root 117: HARD_REG_SET reg_class_contents[N_REG_CLASSES]; 118: 1.1.1.5 root 119: /* The same information, but as an array of unsigned ints. We copy from 120: these unsigned ints to the table above. We do this so the tm.h files 121: do not have to be aware of the wordsize for machines with <= 64 regs. */ 1.1.1.4 root 122: 123: #define N_REG_INTS \ 124: ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT) 125: 1.1.1.5 root 126: static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] 1.1.1.4 root 127: = REG_CLASS_CONTENTS; 1.1 root 128: 129: /* For each reg class, number of regs it contains. */ 130: 131: int reg_class_size[N_REG_CLASSES]; 132: 133: /* For each reg class, table listing all the containing classes. */ 134: 135: enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; 136: 137: /* For each reg class, table listing all the classes contained in it. */ 138: 139: enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; 140: 141: /* For each pair of reg classes, 142: a largest reg class contained in their union. */ 143: 144: enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; 145: 146: /* For each pair of reg classes, 147: the smallest reg class containing their union. */ 148: 149: enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; 150: 151: /* Array containing all of the register names */ 152: 153: char *reg_names[] = REGISTER_NAMES; 154: 1.1.1.7 ! root 155: /* For each hard register, the widest mode object that it can contain. ! 156: This will be a MODE_INT mode if the register can hold integers. Otherwise ! 157: it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the ! 158: register. */ ! 159: ! 160: enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; ! 161: 1.1 root 162: /* Indexed by n, gives number of times (REG n) is set or clobbered. 163: This information remains valid for the rest of the compilation 164: of the current function; it is used to control register allocation. 165: 166: This information applies to both hard registers and pseudo registers, 167: unlike much of the information above. */ 168: 169: short *reg_n_sets; 170: 1.1.1.4 root 171: /* Maximum cost of moving from a register in one class to a register in 172: another class. Based on REGISTER_MOVE_COST. */ 173: 174: static int move_cost[N_REG_CLASSES][N_REG_CLASSES]; 175: 176: /* Similar, but here we don't have to move if the first index is a subset 177: of the second so in that case the cost is zero. */ 178: 179: static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES]; 180: 181: #ifdef FORBIDDEN_INC_DEC_CLASSES 182: 183: /* These are the classes that regs which are auto-incremented or decremented 184: cannot be put in. */ 185: 186: static int forbidden_inc_dec_class[N_REG_CLASSES]; 187: 188: /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec 189: context. */ 190: 191: static char *in_inc_dec; 192: 193: #endif /* FORBIDDEN_INC_DEC_CLASSES */ 194: 1.1 root 195: /* Function called only once to initialize the above data on reg usage. 196: Once this is done, various switches may override. */ 197: 198: void 199: init_reg_sets () 200: { 201: register int i, j; 202: 1.1.1.4 root 203: /* First copy the register information from the initial int form into 204: the regsets. */ 205: 206: for (i = 0; i < N_REG_CLASSES; i++) 207: { 208: CLEAR_HARD_REG_SET (reg_class_contents[i]); 209: 210: for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 211: if (int_reg_class_contents[i][j / HOST_BITS_PER_INT] 1.1.1.5 root 212: & ((unsigned) 1 << (j % HOST_BITS_PER_INT))) 1.1.1.4 root 213: SET_HARD_REG_BIT (reg_class_contents[i], j); 214: } 215: 1.1 root 216: bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); 217: bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); 218: bzero (global_regs, sizeof global_regs); 219: 220: /* Compute number of hard regs in each class. */ 221: 1.1.1.7 ! root 222: bzero ((char *) reg_class_size, sizeof reg_class_size); 1.1 root 223: for (i = 0; i < N_REG_CLASSES; i++) 224: for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 225: if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 226: reg_class_size[i]++; 227: 228: /* Initialize the table of subunions. 229: reg_class_subunion[I][J] gets the largest-numbered reg-class 230: that is contained in the union of classes I and J. */ 231: 232: for (i = 0; i < N_REG_CLASSES; i++) 233: { 234: for (j = 0; j < N_REG_CLASSES; j++) 235: { 236: #ifdef HARD_REG_SET 237: register /* Declare it register if it's a scalar. */ 238: #endif 239: HARD_REG_SET c; 240: register int k; 241: 242: COPY_HARD_REG_SET (c, reg_class_contents[i]); 243: IOR_HARD_REG_SET (c, reg_class_contents[j]); 244: for (k = 0; k < N_REG_CLASSES; k++) 245: { 246: GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, 247: subclass1); 248: continue; 249: 250: subclass1: 251: /* keep the largest subclass */ /* SPEE 900308 */ 252: GO_IF_HARD_REG_SUBSET (reg_class_contents[k], 253: reg_class_contents[(int) reg_class_subunion[i][j]], 254: subclass2); 255: reg_class_subunion[i][j] = (enum reg_class) k; 256: subclass2: 257: ; 258: } 259: } 260: } 261: 262: /* Initialize the table of superunions. 263: reg_class_superunion[I][J] gets the smallest-numbered reg-class 264: containing the union of classes I and J. */ 265: 266: for (i = 0; i < N_REG_CLASSES; i++) 267: { 268: for (j = 0; j < N_REG_CLASSES; j++) 269: { 270: #ifdef HARD_REG_SET 271: register /* Declare it register if it's a scalar. */ 272: #endif 273: HARD_REG_SET c; 274: register int k; 275: 276: COPY_HARD_REG_SET (c, reg_class_contents[i]); 277: IOR_HARD_REG_SET (c, reg_class_contents[j]); 278: for (k = 0; k < N_REG_CLASSES; k++) 279: GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); 280: 281: superclass: 282: reg_class_superunion[i][j] = (enum reg_class) k; 283: } 284: } 285: 286: /* Initialize the tables of subclasses and superclasses of each reg class. 287: First clear the whole table, then add the elements as they are found. */ 288: 289: for (i = 0; i < N_REG_CLASSES; i++) 290: { 291: for (j = 0; j < N_REG_CLASSES; j++) 292: { 293: reg_class_superclasses[i][j] = LIM_REG_CLASSES; 294: reg_class_subclasses[i][j] = LIM_REG_CLASSES; 295: } 296: } 297: 298: for (i = 0; i < N_REG_CLASSES; i++) 299: { 300: if (i == (int) NO_REGS) 301: continue; 302: 303: for (j = i + 1; j < N_REG_CLASSES; j++) 304: { 305: enum reg_class *p; 306: 307: GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], 308: subclass); 309: continue; 310: subclass: 311: /* Reg class I is a subclass of J. 312: Add J to the table of superclasses of I. */ 313: p = ®_class_superclasses[i][0]; 314: while (*p != LIM_REG_CLASSES) p++; 315: *p = (enum reg_class) j; 316: /* Add I to the table of superclasses of J. */ 317: p = ®_class_subclasses[j][0]; 318: while (*p != LIM_REG_CLASSES) p++; 319: *p = (enum reg_class) i; 320: } 321: } 1.1.1.4 root 322: 323: /* Initialize the move cost table. Find every subset of each class 324: and take the maximum cost of moving any subset to any other. */ 325: 326: for (i = 0; i < N_REG_CLASSES; i++) 327: for (j = 0; j < N_REG_CLASSES; j++) 328: { 329: int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j); 330: enum reg_class *p1, *p2; 331: 332: for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++) 333: if (*p2 != i) 334: cost = MAX (cost, REGISTER_MOVE_COST (i, *p2)); 335: 336: for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++) 337: { 338: if (*p1 != j) 339: cost = MAX (cost, REGISTER_MOVE_COST (*p1, j)); 340: 341: for (p2 = ®_class_subclasses[j][0]; 342: *p2 != LIM_REG_CLASSES; p2++) 343: if (*p1 != *p2) 344: cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2)); 345: } 346: 347: move_cost[i][j] = cost; 348: 349: if (reg_class_subset_p (i, j)) 350: cost = 0; 351: 352: may_move_cost[i][j] = cost; 353: } 1.1 root 354: } 355: 356: /* After switches have been processed, which perhaps alter 357: `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ 358: 1.1.1.7 ! root 359: static void 1.1 root 360: init_reg_sets_1 () 361: { 362: register int i; 363: 364: /* This macro allows the fixed or call-used registers 365: to depend on target flags. */ 366: 367: #ifdef CONDITIONAL_REGISTER_USAGE 368: CONDITIONAL_REGISTER_USAGE; 369: #endif 370: 371: /* Initialize "constant" tables. */ 372: 373: CLEAR_HARD_REG_SET (fixed_reg_set); 374: CLEAR_HARD_REG_SET (call_used_reg_set); 375: CLEAR_HARD_REG_SET (call_fixed_reg_set); 376: 377: bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); 378: 379: n_non_fixed_regs = 0; 380: 381: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 382: { 383: if (fixed_regs[i]) 384: SET_HARD_REG_BIT (fixed_reg_set, i); 385: else 386: n_non_fixed_regs++; 387: 388: if (call_used_regs[i]) 389: SET_HARD_REG_BIT (call_used_reg_set, i); 390: if (call_fixed_regs[i]) 391: SET_HARD_REG_BIT (call_fixed_reg_set, i); 392: } 393: } 394: 1.1.1.7 ! root 395: /* Compute the table of register modes. ! 396: These values are used to record death information for individual registers ! 397: (as opposed to a multi-register mode). */ ! 398: ! 399: static void ! 400: init_reg_modes () ! 401: { ! 402: register int i; ! 403: ! 404: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) ! 405: { ! 406: reg_raw_mode[i] = choose_hard_reg_mode (i, 1); ! 407: ! 408: /* If we couldn't find a valid mode, fall back to `word_mode'. ! 409: ??? We assume `word_mode' has already been initialized. ! 410: ??? One situation in which we need to do this is on the mips where ! 411: HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like ! 412: to use DF mode for the even registers and VOIDmode for the odd ! 413: (for the cpu models where the odd ones are inaccessable). */ ! 414: if (reg_raw_mode[i] == VOIDmode) ! 415: reg_raw_mode[i] = word_mode; ! 416: } ! 417: } ! 418: ! 419: /* Finish initializing the register sets and ! 420: initialize the register modes. */ ! 421: ! 422: void ! 423: init_regs () ! 424: { ! 425: /* This finishes what was started by init_reg_sets, but couldn't be done ! 426: until after register usage was specified. */ ! 427: if (!output_bytecode) ! 428: init_reg_sets_1 (); ! 429: ! 430: init_reg_modes (); ! 431: } ! 432: ! 433: /* Return a machine mode that is legitimate for hard reg REGNO and large ! 434: enough to save nregs. If we can't find one, return VOIDmode. */ ! 435: ! 436: enum machine_mode ! 437: choose_hard_reg_mode (regno, nregs) ! 438: int regno; ! 439: int nregs; ! 440: { ! 441: enum machine_mode found_mode = VOIDmode, mode; ! 442: ! 443: /* We first look for the largest integer mode that can be validly ! 444: held in REGNO. If none, we look for the largest floating-point mode. ! 445: If we still didn't find a valid mode, try CCmode. */ ! 446: ! 447: for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); ! 448: mode != VOIDmode; ! 449: mode = GET_MODE_WIDER_MODE (mode)) ! 450: if (HARD_REGNO_NREGS (regno, mode) == nregs ! 451: && HARD_REGNO_MODE_OK (regno, mode)) ! 452: found_mode = mode; ! 453: ! 454: if (found_mode != VOIDmode) ! 455: return found_mode; ! 456: ! 457: for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); ! 458: mode != VOIDmode; ! 459: mode = GET_MODE_WIDER_MODE (mode)) ! 460: if (HARD_REGNO_NREGS (regno, mode) == nregs ! 461: && HARD_REGNO_MODE_OK (regno, mode)) ! 462: found_mode = mode; ! 463: ! 464: if (found_mode != VOIDmode) ! 465: return found_mode; ! 466: ! 467: if (HARD_REGNO_NREGS (regno, CCmode) == nregs ! 468: && HARD_REGNO_MODE_OK (regno, CCmode)) ! 469: return CCmode; ! 470: ! 471: /* We can't find a mode valid for this register. */ ! 472: return VOIDmode; ! 473: } ! 474: 1.1 root 475: /* Specify the usage characteristics of the register named NAME. 476: It should be a fixed register if FIXED and a 477: call-used register if CALL_USED. */ 478: 479: void 480: fix_register (name, fixed, call_used) 481: char *name; 482: int fixed, call_used; 483: { 484: int i; 485: 1.1.1.6 root 486: if (output_bytecode) 487: { 488: warning ("request to mark `%s' as %s ignored by bytecode compiler", 489: name, call_used ? "call-used" : "fixed"); 490: return; 491: } 492: 1.1 root 493: /* Decode the name and update the primary form of 494: the register info. */ 495: 1.1.1.2 root 496: if ((i = decode_reg_name (name)) >= 0) 497: { 498: fixed_regs[i] = fixed; 499: call_used_regs[i] = call_used; 500: } 501: else 1.1 root 502: { 503: warning ("unknown register name: %s", name); 504: } 505: } 1.1.1.6 root 506: 507: /* Mark register number I as global. */ 508: 509: void 510: globalize_reg (i) 511: int i; 512: { 513: if (global_regs[i]) 514: { 515: warning ("register used for two global register variables"); 516: return; 517: } 518: 519: if (call_used_regs[i] && ! fixed_regs[i]) 520: warning ("call-clobbered register used for global register variable"); 521: 522: global_regs[i] = 1; 523: 524: /* If already fixed, nothing else to do. */ 525: if (fixed_regs[i]) 526: return; 527: 528: fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; 529: n_non_fixed_regs--; 530: 531: SET_HARD_REG_BIT (fixed_reg_set, i); 532: SET_HARD_REG_BIT (call_used_reg_set, i); 533: SET_HARD_REG_BIT (call_fixed_reg_set, i); 534: } 1.1 root 535: 536: /* Now the data and code for the `regclass' pass, which happens 537: just before local-alloc. */ 538: 1.1.1.4 root 539: /* The `costs' struct records the cost of using a hard register of each class 540: and of using memory for each pseudo. We use this data to set up 541: register class preferences. */ 1.1 root 542: 1.1.1.4 root 543: struct costs 1.1 root 544: { 1.1.1.4 root 545: int cost[N_REG_CLASSES]; 546: int mem_cost; 1.1 root 547: }; 548: 1.1.1.4 root 549: /* Record the cost of each class for each pseudo. */ 550: 551: static struct costs *costs; 552: 553: /* Record the same data by operand number, accumulated for each alternative 554: in an insn. The contribution to a pseudo is that of the minimum-cost 555: alternative. */ 556: 557: static struct costs op_costs[MAX_RECOG_OPERANDS]; 1.1 root 558: 559: /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. 560: This is available after `regclass' is run. */ 561: 562: static char *prefclass; 563: 1.1.1.4 root 564: /* altclass[R] is a register class that we should use for allocating 565: pseudo number R if no register in the preferred class is available. 566: If no register in this class is available, memory is preferred. 567: 568: It might appear to be more general to have a bitmask of classes here, 569: but since it is recommended that there be a class corresponding to the 570: union of most major pair of classes, that generality is not required. 571: 1.1 root 572: This is available after `regclass' is run. */ 573: 1.1.1.4 root 574: static char *altclass; 1.1 root 575: 1.1.1.4 root 576: /* Record the depth of loops that we are in. */ 1.1 root 577: 578: static int loop_depth; 579: 1.1.1.4 root 580: /* Account for the fact that insns within a loop are executed very commonly, 581: but don't keep doing this as loops go too deep. */ 582: 583: static int loop_cost; 584: 1.1.1.7 ! root 585: static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *, ! 586: char **, rtx)); ! 587: static int copy_cost PROTO((rtx, enum machine_mode, ! 588: enum reg_class, int)); ! 589: static void record_address_regs PROTO((rtx, enum reg_class, int)); ! 590: static auto_inc_dec_reg_p PROTO((rtx, enum machine_mode)); ! 591: static void reg_scan_mark_refs PROTO((rtx, rtx, int)); 1.1 root 592: 593: /* Return the reg_class in which pseudo reg number REGNO is best allocated. 594: This function is sometimes called before the info has been computed. 595: When that happens, just return GENERAL_REGS, which is innocuous. */ 596: 597: enum reg_class 598: reg_preferred_class (regno) 599: int regno; 600: { 601: if (prefclass == 0) 602: return GENERAL_REGS; 603: return (enum reg_class) prefclass[regno]; 604: } 605: 1.1.1.4 root 606: enum reg_class 607: reg_alternate_class (regno) 1.1 root 608: { 609: if (prefclass == 0) 1.1.1.4 root 610: return ALL_REGS; 611: 612: return (enum reg_class) altclass[regno]; 1.1 root 613: } 614: 615: /* This prevents dump_flow_info from losing if called 616: before regclass is run. */ 617: 618: void 619: regclass_init () 620: { 621: prefclass = 0; 622: } 623: 624: /* This is a pass of the compiler that scans all instructions 625: and calculates the preferred class for each pseudo-register. 626: This information can be accessed later by calling `reg_preferred_class'. 627: This pass comes just before local register allocation. */ 628: 629: void 630: regclass (f, nregs) 631: rtx f; 632: int nregs; 633: { 634: #ifdef REGISTER_CONSTRAINTS 635: register rtx insn; 1.1.1.4 root 636: register int i, j; 637: struct costs init_cost; 638: rtx set; 639: int pass; 1.1 root 640: 641: init_recog (); 642: 1.1.1.4 root 643: costs = (struct costs *) alloca (nregs * sizeof (struct costs)); 1.1 root 644: 1.1.1.4 root 645: #ifdef FORBIDDEN_INC_DEC_CLASSES 1.1 root 646: 1.1.1.4 root 647: in_inc_dec = (char *) alloca (nregs); 1.1 root 648: 1.1.1.4 root 649: /* Initialize information about which register classes can be used for 650: pseudos that are auto-incremented or auto-decremented. It would 651: seem better to put this in init_reg_sets, but we need to be able 652: to allocate rtx, which we can't do that early. */ 1.1 root 653: 1.1.1.4 root 654: for (i = 0; i < N_REG_CLASSES; i++) 1.1 root 655: { 1.1.1.4 root 656: rtx r = gen_rtx (REG, VOIDmode, 0); 657: enum machine_mode m; 1.1 root 658: 1.1.1.4 root 659: for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 660: if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 661: { 662: REGNO (r) = j; 1.1 root 663: 1.1.1.4 root 664: for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; 1.1.1.5 root 665: m = (enum machine_mode) ((int) m + 1)) 1.1.1.4 root 666: if (HARD_REGNO_MODE_OK (j, m)) 667: { 668: PUT_MODE (r, m); 1.1.1.7 ! root 669: ! 670: /* If a register is not directly suitable for an ! 671: auto-increment or decrement addressing mode and ! 672: requires secondary reloads, disallow its class from ! 673: being used in such addresses. */ ! 674: ! 675: if ((0 1.1.1.4 root 676: #ifdef SECONDARY_INPUT_RELOAD_CLASS 1.1.1.7 ! root 677: || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) ! 678: != NO_REGS) 1.1.1.4 root 679: #endif 680: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1.1.1.7 ! root 681: || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r) ! 682: != NO_REGS) 1.1.1.4 root 683: #endif 1.1.1.7 ! root 684: ) ! 685: && ! auto_inc_dec_reg_p (r, m)) 1.1.1.4 root 686: forbidden_inc_dec_class[i] = 1; 687: } 688: } 689: } 690: #endif /* FORBIDDEN_INC_DEC_CLASSES */ 1.1 root 691: 1.1.1.4 root 692: init_cost.mem_cost = 10000; 693: for (i = 0; i < N_REG_CLASSES; i++) 694: init_cost.cost[i] = 10000; 695: 696: /* Normally we scan the insns once and determine the best class to use for 697: each register. However, if -fexpensive_optimizations are on, we do so 698: twice, the second time using the tentative best classes to guide the 699: selection. */ 1.1 root 700: 1.1.1.4 root 701: for (pass = 0; pass <= flag_expensive_optimizations; pass++) 702: { 703: /* Zero out our accumulation of the cost of each class for each reg. */ 704: 1.1.1.7 ! root 705: bzero ((char *) costs, nregs * sizeof (struct costs)); 1.1.1.4 root 706: 707: #ifdef FORBIDDEN_INC_DEC_CLASSES 708: bzero (in_inc_dec, nregs); 709: #endif 1.1 root 710: 1.1.1.4 root 711: loop_depth = 0, loop_cost = 1; 712: 713: /* Scan the instructions and record each time it would 714: save code to put a certain register in a certain class. */ 715: 716: for (insn = f; insn; insn = NEXT_INSN (insn)) 717: { 718: char *constraints[MAX_RECOG_OPERANDS]; 719: enum machine_mode modes[MAX_RECOG_OPERANDS]; 720: int nalternatives; 721: int noperands; 722: 723: /* Show that an insn inside a loop is likely to be executed three 1.1.1.5 root 724: times more than insns outside a loop. This is much more aggressive 1.1.1.4 root 725: than the assumptions made elsewhere and is being tried as an 726: experiment. */ 727: 728: if (GET_CODE (insn) == NOTE 729: && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) 730: loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5)); 731: else if (GET_CODE (insn) == NOTE 732: && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) 733: loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5)); 734: 735: else if ((GET_CODE (insn) == INSN 736: && GET_CODE (PATTERN (insn)) != USE 737: && GET_CODE (PATTERN (insn)) != CLOBBER 738: && GET_CODE (PATTERN (insn)) != ASM_INPUT) 739: || (GET_CODE (insn) == JUMP_INSN 740: && GET_CODE (PATTERN (insn)) != ADDR_VEC 741: && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) 742: || GET_CODE (insn) == CALL_INSN) 743: { 744: if (GET_CODE (insn) == INSN 745: && (noperands = asm_noperands (PATTERN (insn))) >= 0) 1.1 root 746: { 1.1.1.4 root 747: decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR, 748: constraints, modes); 749: nalternatives = (noperands == 0 ? 0 750: : n_occurrences (',', constraints[0]) + 1); 1.1 root 751: } 1.1.1.4 root 752: else 1.1 root 753: { 1.1.1.4 root 754: int insn_code_number = recog_memoized (insn); 755: rtx note; 756: 757: set = single_set (insn); 758: insn_extract (insn); 1.1 root 759: 1.1.1.4 root 760: nalternatives = insn_n_alternatives[insn_code_number]; 761: noperands = insn_n_operands[insn_code_number]; 762: 763: /* If this insn loads a parameter from its stack slot, then 764: it represents a savings, rather than a cost, if the 765: parameter is stored in memory. Record this fact. */ 766: 767: if (set != 0 && GET_CODE (SET_DEST (set)) == REG 768: && GET_CODE (SET_SRC (set)) == MEM 769: && (note = find_reg_note (insn, REG_EQUIV, 770: NULL_RTX)) != 0 771: && GET_CODE (XEXP (note, 0)) == MEM) 772: { 773: costs[REGNO (SET_DEST (set))].mem_cost 774: -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set))) 775: * loop_cost); 776: record_address_regs (XEXP (SET_SRC (set), 0), 777: BASE_REG_CLASS, loop_cost * 2); 778: continue; 779: } 780: 781: /* Improve handling of two-address insns such as 782: (set X (ashift CONST Y)) where CONST must be made to 783: match X. Change it into two insns: (set X CONST) 784: (set X (ashift X Y)). If we left this for reloading, it 785: would probably get three insns because X and Y might go 786: in the same place. This prevents X and Y from receiving 787: the same hard reg. 788: 789: We can only do this if the modes of operands 0 and 1 790: (which might not be the same) are tieable and we only need 791: do this during our first pass. */ 792: 793: if (pass == 0 && optimize 794: && noperands >= 3 795: && insn_operand_constraint[insn_code_number][1][0] == '0' 796: && insn_operand_constraint[insn_code_number][1][1] == 0 797: && CONSTANT_P (recog_operand[1]) 798: && ! rtx_equal_p (recog_operand[0], recog_operand[1]) 799: && ! rtx_equal_p (recog_operand[0], recog_operand[2]) 800: && GET_CODE (recog_operand[0]) == REG 801: && MODES_TIEABLE_P (GET_MODE (recog_operand[0]), 802: insn_operand_mode[insn_code_number][1])) 1.1 root 803: { 1.1.1.4 root 804: rtx previnsn = prev_real_insn (insn); 805: rtx dest 806: = gen_lowpart (insn_operand_mode[insn_code_number][1], 807: recog_operand[0]); 808: rtx newinsn 809: = emit_insn_before (gen_move_insn (dest, 810: recog_operand[1]), 811: insn); 812: 813: /* If this insn was the start of a basic block, 814: include the new insn in that block. 815: We need not check for code_label here; 816: while a basic block can start with a code_label, 817: INSN could not be at the beginning of that block. */ 818: if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) 819: { 820: int b; 821: for (b = 0; b < n_basic_blocks; b++) 822: if (insn == basic_block_head[b]) 823: basic_block_head[b] = newinsn; 824: } 825: 826: /* This makes one more setting of new insns's dest. */ 827: reg_n_sets[REGNO (recog_operand[0])]++; 828: 829: *recog_operand_loc[1] = recog_operand[0]; 830: for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) 831: if (recog_dup_num[i] == 1) 832: *recog_dup_loc[i] = recog_operand[0]; 833: 834: insn = PREV_INSN (newinsn); 835: continue; 1.1 root 836: } 837: 1.1.1.4 root 838: for (i = 0; i < noperands; i++) 839: { 840: constraints[i] 841: = insn_operand_constraint[insn_code_number][i]; 842: modes[i] = insn_operand_mode[insn_code_number][i]; 843: } 1.1 root 844: } 1.1.1.4 root 845: 846: /* If we get here, we are set up to record the costs of all the 847: operands for this insn. Start by initializing the costs. 848: Then handle any address registers. Finally record the desired 849: classes for any pseudos, doing it twice if some pair of 850: operands are commutative. */ 851: 852: for (i = 0; i < noperands; i++) 853: { 854: op_costs[i] = init_cost; 855: 856: if (GET_CODE (recog_operand[i]) == SUBREG) 857: recog_operand[i] = SUBREG_REG (recog_operand[i]); 858: 859: if (GET_CODE (recog_operand[i]) == MEM) 860: record_address_regs (XEXP (recog_operand[i], 0), 861: BASE_REG_CLASS, loop_cost * 2); 862: else if (constraints[i][0] == 'p') 863: record_address_regs (recog_operand[i], 864: BASE_REG_CLASS, loop_cost * 2); 865: } 866: 867: /* Check for commutative in a separate loop so everything will 1.1.1.6 root 868: have been initialized. We must do this even if one operand 869: is a constant--see addsi3 in m68k.md. */ 1.1.1.4 root 870: 871: for (i = 0; i < noperands - 1; i++) 1.1.1.6 root 872: if (constraints[i][0] == '%') 1.1.1.4 root 873: { 874: char *xconstraints[MAX_RECOG_OPERANDS]; 875: int j; 876: 877: /* Handle commutative operands by swapping the constraints. 878: We assume the modes are the same. */ 879: 880: for (j = 0; j < noperands; j++) 881: xconstraints[j] = constraints[j]; 882: 883: xconstraints[i] = constraints[i+1]; 884: xconstraints[i+1] = constraints[i]; 885: record_reg_classes (nalternatives, noperands, 886: recog_operand, modes, xconstraints, 887: insn); 888: } 889: 890: record_reg_classes (nalternatives, noperands, recog_operand, 891: modes, constraints, insn); 892: 893: /* Now add the cost for each operand to the total costs for 894: its register. */ 895: 896: for (i = 0; i < noperands; i++) 897: if (GET_CODE (recog_operand[i]) == REG 898: && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) 899: { 900: int regno = REGNO (recog_operand[i]); 901: struct costs *p = &costs[regno], *q = &op_costs[i]; 902: 903: p->mem_cost += q->mem_cost * loop_cost; 904: for (j = 0; j < N_REG_CLASSES; j++) 905: p->cost[j] += q->cost[j] * loop_cost; 906: } 1.1 root 907: } 908: } 909: 1.1.1.4 root 910: /* Now for each register look at how desirable each class is 911: and find which class is preferred. Store that in 912: `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register 913: class any of whose registers is better than memory. */ 1.1 root 914: 1.1.1.4 root 915: if (pass == 0) 916: { 917: prefclass = (char *) oballoc (nregs); 918: altclass = (char *) oballoc (nregs); 919: } 1.1 root 920: 1.1.1.4 root 921: for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) 1.1 root 922: { 1.1.1.4 root 923: register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; 924: enum reg_class best = ALL_REGS, alt = NO_REGS; 925: /* This is an enum reg_class, but we call it an int 926: to save lots of casts. */ 927: register int class; 928: register struct costs *p = &costs[i]; 929: 930: for (class = (int) ALL_REGS - 1; class > 0; class--) 1.1 root 931: { 1.1.1.4 root 932: /* Ignore classes that are too small for this operand or 933: invalid for a operand that was auto-incremented. */ 934: if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i)) 935: > reg_class_size[class] 936: #ifdef FORBIDDEN_INC_DEC_CLASSES 937: || (in_inc_dec[i] && forbidden_inc_dec_class[class]) 938: #endif 939: ) 940: ; 941: else if (p->cost[class] < best_cost) 942: { 943: best_cost = p->cost[class]; 944: best = (enum reg_class) class; 945: } 946: else if (p->cost[class] == best_cost) 947: best = reg_class_subunion[(int)best][class]; 1.1 root 948: } 949: 1.1.1.4 root 950: /* Record the alternate register class; i.e., a class for which 951: every register in it is better than using memory. If adding a 952: class would make a smaller class (i.e., no union of just those 953: classes exists), skip that class. The major unions of classes 954: should be provided as a register class. Don't do this if we 955: will be doing it again later. */ 956: 957: if (pass == 1 || ! flag_expensive_optimizations) 958: for (class = 0; class < N_REG_CLASSES; class++) 959: if (p->cost[class] < p->mem_cost 960: && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] 961: > reg_class_size[(int) alt]) 962: #ifdef FORBIDDEN_INC_DEC_CLASSES 963: && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1.1 root 964: #endif 1.1.1.4 root 965: ) 966: alt = reg_class_subunion[(int) alt][class]; 967: 968: /* If we don't add any classes, nothing to try. */ 969: if (alt == best) 970: alt = (int) NO_REGS; 971: 972: /* We cast to (int) because (char) hits bugs in some compilers. */ 973: prefclass[i] = (int) best; 974: altclass[i] = (int) alt; 975: } 1.1 root 976: } 977: #endif /* REGISTER_CONSTRAINTS */ 978: } 979: 980: #ifdef REGISTER_CONSTRAINTS 981: 1.1.1.4 root 982: /* Record the cost of using memory or registers of various classes for 983: the operands in INSN. 1.1 root 984: 1.1.1.4 root 985: N_ALTS is the number of alternatives. 1.1 root 986: 1.1.1.4 root 987: N_OPS is the number of operands. 1.1 root 988: 1.1.1.4 root 989: OPS is an array of the operands. 1.1 root 990: 1.1.1.4 root 991: MODES are the modes of the operands, in case any are VOIDmode. 1.1 root 992: 1.1.1.4 root 993: CONSTRAINTS are the constraints to use for the operands. This array 994: is modified by this procedure. 1.1 root 995: 1.1.1.4 root 996: This procedure works alternative by alternative. For each alternative 997: we assume that we will be able to allocate all pseudos to their ideal 998: register class and calculate the cost of using that alternative. Then 999: we compute for each operand that is a pseudo-register, the cost of 1000: having the pseudo allocated to each register class and using it in that 1001: alternative. To this cost is added the cost of the alternative. 1.1 root 1002: 1.1.1.4 root 1003: The cost of each class for this insn is its lowest cost among all the 1004: alternatives. */ 1005: 1006: static void 1007: record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn) 1008: int n_alts; 1009: int n_ops; 1010: rtx *ops; 1011: enum machine_mode *modes; 1012: char **constraints; 1013: rtx insn; 1014: { 1015: int alt; 1016: enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS]; 1017: int i, j; 1018: 1019: /* By default, each operand is an input operand. */ 1020: 1021: for (i = 0; i < n_ops; i++) 1022: op_types[i] = OP_READ; 1.1 root 1023: 1.1.1.4 root 1024: /* Process each alternative, each time minimizing an operand's cost with 1025: the cost for each operand in that alternative. */ 1.1 root 1026: 1.1.1.4 root 1027: for (alt = 0; alt < n_alts; alt++) 1.1 root 1028: { 1.1.1.4 root 1029: struct costs this_op_costs[MAX_RECOG_OPERANDS]; 1030: int alt_fail = 0; 1031: int alt_cost = 0; 1032: enum reg_class classes[MAX_RECOG_OPERANDS]; 1033: int class; 1.1 root 1034: 1.1.1.4 root 1035: for (i = 0; i < n_ops; i++) 1.1 root 1036: { 1.1.1.4 root 1037: char *p = constraints[i]; 1038: rtx op = ops[i]; 1039: enum machine_mode mode = modes[i]; 1040: int allows_mem = 0; 1041: int win = 0; 1042: char c; 1043: 1044: /* If this operand has no constraints at all, we can conclude 1045: nothing about it since anything is valid. */ 1046: 1047: if (*p == 0) 1.1 root 1048: { 1.1.1.4 root 1049: if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1050: bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]); 1051: 1052: continue; 1.1 root 1053: } 1054: 1.1.1.4 root 1055: if (*p == '%') 1056: p++; 1.1 root 1057: 1.1.1.4 root 1058: /* If this alternative is only relevant when this operand 1059: matches a previous operand, we do different things depending 1060: on whether this operand is a pseudo-reg or not. */ 1061: 1062: if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) 1063: { 1064: j = p[0] - '0'; 1065: classes[i] = classes[j]; 1.1 root 1066: 1.1.1.4 root 1067: if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER) 1068: { 1069: /* If this matches the other operand, we have no added 1.1.1.7 ! root 1070: cost and we win. */ 1.1.1.4 root 1071: if (rtx_equal_p (ops[j], op)) 1.1.1.7 ! root 1072: win = 1; 1.1.1.4 root 1073: 1.1.1.5 root 1074: /* If we can put the other operand into a register, add to 1075: the cost of this alternative the cost to copy this 1076: operand to the register used for the other operand. */ 1.1.1.4 root 1077: 1.1.1.7 ! root 1078: else if (classes[j] != NO_REGS) 1.1.1.5 root 1079: alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; 1.1.1.4 root 1080: } 1081: else if (GET_CODE (ops[j]) != REG 1082: || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) 1083: { 1084: /* This op is a pseudo but the one it matches is not. */ 1085: 1086: /* If we can't put the other operand into a register, this 1087: alternative can't be used. */ 1088: 1089: if (classes[j] == NO_REGS) 1090: alt_fail = 1; 1091: 1092: /* Otherwise, add to the cost of this alternative the cost 1093: to copy the other operand to the register used for this 1094: operand. */ 1.1 root 1095: 1.1.1.4 root 1096: else 1097: alt_cost += copy_cost (ops[j], mode, classes[j], 1); 1098: } 1099: else 1100: { 1101: /* The costs of this operand are the same as that of the 1102: other operand. However, if we cannot tie them, this 1103: alternative needs to do a copy, which is one 1104: instruction. */ 1105: 1106: this_op_costs[i] = this_op_costs[j]; 1.1.1.6 root 1107: if (REGNO (ops[i]) != REGNO (ops[j]) 1108: && ! find_reg_note (insn, REG_DEAD, op)) 1.1.1.4 root 1109: alt_cost += 2; 1110: 1111: /* This is in place of ordinary cost computation 1.1.1.6 root 1112: for this operand, so skip to the end of the 1113: alternative (should be just one character). */ 1114: while (*p && *p++ != ',') 1115: ; 1116: 1117: constraints[i] = p; 1.1.1.4 root 1118: continue; 1119: } 1120: } 1.1 root 1121: 1.1.1.4 root 1122: /* Scan all the constraint letters. See if the operand matches 1123: any of the constraints. Collect the valid register classes 1124: and see if this operand accepts memory. */ 1125: 1126: classes[i] = NO_REGS; 1127: while (*p && (c = *p++) != ',') 1128: switch (c) 1.1 root 1129: { 1.1.1.4 root 1130: case '=': 1131: op_types[i] = OP_WRITE; 1132: break; 1133: 1134: case '+': 1135: op_types[i] = OP_READ_WRITE; 1136: break; 1137: 1138: case '*': 1139: /* Ignore the next letter for this pass. */ 1140: p++; 1141: break; 1142: 1143: case '%': 1144: case '?': case '!': case '#': 1145: case '&': 1146: case '0': case '1': case '2': case '3': case '4': 1147: case 'p': 1148: break; 1149: 1150: case 'm': case 'o': case 'V': 1.1.1.5 root 1151: /* It doesn't seem worth distinguishing between offsettable 1.1.1.4 root 1152: and non-offsettable addresses here. */ 1153: allows_mem = 1; 1154: if (GET_CODE (op) == MEM) 1155: win = 1; 1156: break; 1157: 1158: case '<': 1159: if (GET_CODE (op) == MEM 1160: && (GET_CODE (XEXP (op, 0)) == PRE_DEC 1161: || GET_CODE (XEXP (op, 0)) == POST_DEC)) 1162: win = 1; 1163: break; 1164: 1165: case '>': 1166: if (GET_CODE (op) == MEM 1167: && (GET_CODE (XEXP (op, 0)) == PRE_INC 1168: || GET_CODE (XEXP (op, 0)) == POST_INC)) 1169: win = 1; 1170: break; 1171: 1172: case 'E': 1173: /* Match any floating double constant, but only if 1174: we can examine the bits of it reliably. */ 1175: if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT 1176: || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) 1177: && GET_MODE (op) != VOIDmode && ! flag_pretend_float) 1178: break; 1179: if (GET_CODE (op) == CONST_DOUBLE) 1180: win = 1; 1181: break; 1182: 1183: case 'F': 1184: if (GET_CODE (op) == CONST_DOUBLE) 1185: win = 1; 1186: break; 1187: 1188: case 'G': 1189: case 'H': 1190: if (GET_CODE (op) == CONST_DOUBLE 1191: && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) 1192: win = 1; 1193: break; 1194: 1195: case 's': 1196: if (GET_CODE (op) == CONST_INT 1197: || (GET_CODE (op) == CONST_DOUBLE 1198: && GET_MODE (op) == VOIDmode)) 1.1 root 1199: break; 1.1.1.4 root 1200: case 'i': 1201: if (CONSTANT_P (op) 1202: #ifdef LEGITIMATE_PIC_OPERAND_P 1203: && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1204: #endif 1205: ) 1206: win = 1; 1207: break; 1208: 1209: case 'n': 1210: if (GET_CODE (op) == CONST_INT 1211: || (GET_CODE (op) == CONST_DOUBLE 1212: && GET_MODE (op) == VOIDmode)) 1213: win = 1; 1214: break; 1215: 1216: case 'I': 1217: case 'J': 1218: case 'K': 1219: case 'L': 1220: case 'M': 1221: case 'N': 1222: case 'O': 1223: case 'P': 1224: if (GET_CODE (op) == CONST_INT 1225: && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) 1226: win = 1; 1227: break; 1228: 1229: case 'X': 1230: win = 1; 1231: break; 1232: 1233: #ifdef EXTRA_CONSTRAINT 1234: case 'Q': 1235: case 'R': 1236: case 'S': 1237: case 'T': 1238: case 'U': 1239: if (EXTRA_CONSTRAINT (op, c)) 1240: win = 1; 1241: break; 1242: #endif 1243: 1244: case 'g': 1245: if (GET_CODE (op) == MEM 1246: || (CONSTANT_P (op) 1247: #ifdef LEGITIMATE_PIC_OPERAND_P 1248: && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1249: #endif 1250: )) 1251: win = 1; 1252: allows_mem = 1; 1253: case 'r': 1254: classes[i] 1255: = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; 1256: break; 1257: 1258: default: 1259: classes[i] 1260: = reg_class_subunion[(int) classes[i]] 1261: [(int) REG_CLASS_FROM_LETTER (c)]; 1.1 root 1262: } 1263: 1.1.1.4 root 1264: constraints[i] = p; 1265: 1266: /* How we account for this operand now depends on whether it is a 1267: pseudo register or not. If it is, we first check if any 1268: register classes are valid. If not, we ignore this alternative, 1269: since we want to assume that all pseudos get allocated for 1270: register preferencing. If some register class is valid, compute 1271: the costs of moving the pseudo into that class. */ 1272: 1273: if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1274: { 1275: if (classes[i] == NO_REGS) 1276: alt_fail = 1; 1277: else 1278: { 1279: struct costs *pp = &this_op_costs[i]; 1280: 1281: for (class = 0; class < N_REG_CLASSES; class++) 1282: pp->cost[class] = may_move_cost[class][(int) classes[i]]; 1283: 1284: /* If the alternative actually allows memory, make things 1285: a bit cheaper since we won't need an extra insn to 1286: load it. */ 1287: 1288: pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem; 1289: 1290: /* If we have assigned a class to this register in our 1291: first pass, add a cost to this alternative corresponding 1292: to what we would add if this register were not in the 1293: appropriate class. */ 1294: 1295: if (prefclass) 1296: alt_cost 1297: += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]]; 1298: } 1299: } 1300: 1301: /* Otherwise, if this alternative wins, either because we 1302: have already determined that or if we have a hard register of 1303: the proper class, there is no cost for this alternative. */ 1304: 1305: else if (win 1306: || (GET_CODE (op) == REG 1307: && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) 1308: ; 1309: 1310: /* If registers are valid, the cost of this alternative includes 1311: copying the object to and/or from a register. */ 1312: 1313: else if (classes[i] != NO_REGS) 1314: { 1315: if (op_types[i] != OP_WRITE) 1316: alt_cost += copy_cost (op, mode, classes[i], 1); 1317: 1318: if (op_types[i] != OP_READ) 1319: alt_cost += copy_cost (op, mode, classes[i], 0); 1320: } 1321: 1322: /* The only other way this alternative can be used is if this is a 1323: constant that could be placed into memory. */ 1.1 root 1324: 1.1.1.4 root 1325: else if (CONSTANT_P (op) && allows_mem) 1326: alt_cost += MEMORY_MOVE_COST (mode); 1327: else 1328: alt_fail = 1; 1329: } 1330: 1331: if (alt_fail) 1332: continue; 1333: 1334: /* Finally, update the costs with the information we've calculated 1335: about this alternative. */ 1336: 1337: for (i = 0; i < n_ops; i++) 1338: if (GET_CODE (ops[i]) == REG 1339: && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1340: { 1341: struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; 1342: int scale = 1 + (op_types[i] == OP_READ_WRITE); 1343: 1344: pp->mem_cost = MIN (pp->mem_cost, 1345: (qq->mem_cost + alt_cost) * scale); 1346: 1347: for (class = 0; class < N_REG_CLASSES; class++) 1348: pp->cost[class] = MIN (pp->cost[class], 1349: (qq->cost[class] + alt_cost) * scale); 1350: } 1351: } 1.1 root 1352: } 1.1.1.4 root 1353: 1354: /* Compute the cost of loading X into (if TO_P is non-zero) or from (if 1355: TO_P is zero) a register of class CLASS in mode MODE. 1356: 1357: X must not be a pseudo. */ 1358: 1359: static int 1360: copy_cost (x, mode, class, to_p) 1361: rtx x; 1362: enum machine_mode mode; 1363: enum reg_class class; 1364: int to_p; 1365: { 1366: enum reg_class secondary_class = NO_REGS; 1367: 1368: /* If X is a SCRATCH, there is actually nothing to move since we are 1369: assuming optimal allocation. */ 1370: 1371: if (GET_CODE (x) == SCRATCH) 1372: return 0; 1373: 1374: /* Get the class we will actually use for a reload. */ 1375: class = PREFERRED_RELOAD_CLASS (x, class); 1376: 1377: #ifdef HAVE_SECONDARY_RELOADS 1378: /* If we need a secondary reload (we assume here that we are using 1379: the secondary reload as an intermediate, not a scratch register), the 1380: cost is that to load the input into the intermediate register, then 1381: to copy them. We use a special value of TO_P to avoid recursion. */ 1382: 1383: #ifdef SECONDARY_INPUT_RELOAD_CLASS 1384: if (to_p == 1) 1385: secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); 1386: #endif 1.1 root 1387: 1.1.1.4 root 1388: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1389: if (! to_p) 1390: secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); 1391: #endif 1392: 1393: if (secondary_class != NO_REGS) 1394: return (move_cost[(int) secondary_class][(int) class] 1395: + copy_cost (x, mode, secondary_class, 2)); 1396: #endif /* HAVE_SECONDARY_RELOADS */ 1397: 1398: /* For memory, use the memory move cost, for (hard) registers, use the 1399: cost to move between the register classes, and use 2 for everything 1400: else (constants). */ 1401: 1402: if (GET_CODE (x) == MEM || class == NO_REGS) 1403: return MEMORY_MOVE_COST (mode); 1404: 1405: else if (GET_CODE (x) == REG) 1406: return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; 1407: 1408: else 1409: /* If this is a constant, we may eventually want to call rtx_cost here. */ 1410: return 2; 1411: } 1412: 1.1 root 1413: /* Record the pseudo registers we must reload into hard registers 1414: in a subexpression of a memory address, X. 1415: 1.1.1.4 root 1416: CLASS is the class that the register needs to be in and is either 1417: BASE_REG_CLASS or INDEX_REG_CLASS. 1418: 1419: SCALE is twice the amount to multiply the cost by (it is twice so we 1420: can represent half-cost adjustments). */ 1421: 1422: static void 1423: record_address_regs (x, class, scale) 1.1 root 1424: rtx x; 1.1.1.4 root 1425: enum reg_class class; 1426: int scale; 1.1 root 1427: { 1428: register enum rtx_code code = GET_CODE (x); 1429: 1430: switch (code) 1431: { 1432: case CONST_INT: 1433: case CONST: 1434: case CC0: 1435: case PC: 1436: case SYMBOL_REF: 1437: case LABEL_REF: 1438: return; 1439: 1440: case PLUS: 1441: /* When we have an address that is a sum, 1442: we must determine whether registers are "base" or "index" regs. 1443: If there is a sum of two registers, we must choose one to be 1444: the "base". Luckily, we can use the REGNO_POINTER_FLAG 1.1.1.4 root 1445: to make a good choice most of the time. We only need to do this 1446: on machines that can have two registers in an address and where 1447: the base and index register classes are different. 1448: 1449: ??? This code used to set REGNO_POINTER_FLAG in some cases, but 1450: that seems bogus since it should only be set when we are sure 1451: the register is being used as a pointer. */ 1452: 1.1 root 1453: { 1454: rtx arg0 = XEXP (x, 0); 1455: rtx arg1 = XEXP (x, 1); 1456: register enum rtx_code code0 = GET_CODE (arg0); 1457: register enum rtx_code code1 = GET_CODE (arg1); 1458: 1459: /* Look inside subregs. */ 1.1.1.4 root 1460: if (code0 == SUBREG) 1.1 root 1461: arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); 1.1.1.4 root 1462: if (code1 == SUBREG) 1.1 root 1463: arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); 1464: 1.1.1.4 root 1465: /* If this machine only allows one register per address, it must 1466: be in the first operand. */ 1467: 1468: if (MAX_REGS_PER_ADDRESS == 1) 1469: record_address_regs (arg0, class, scale); 1470: 1471: /* If index and base registers are the same on this machine, just 1472: record registers in any non-constant operands. We assume here, 1473: as well as in the tests below, that all addresses are in 1474: canonical form. */ 1475: 1476: else if (INDEX_REG_CLASS == BASE_REG_CLASS) 1.1 root 1477: { 1.1.1.4 root 1478: record_address_regs (arg0, class, scale); 1479: if (! CONSTANT_P (arg1)) 1480: record_address_regs (arg1, class, scale); 1.1 root 1481: } 1.1.1.4 root 1482: 1483: /* If the second operand is a constant integer, it doesn't change 1484: what class the first operand must be. */ 1485: 1486: else if (code1 == CONST_INT || code1 == CONST_DOUBLE) 1487: record_address_regs (arg0, class, scale); 1488: 1489: /* If the second operand is a symbolic constant, the first operand 1490: must be an index register. */ 1491: 1492: else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) 1493: record_address_regs (arg0, INDEX_REG_CLASS, scale); 1494: 1495: /* If this the sum of two registers where the first is known to be a 1496: pointer, it must be a base register with the second an index. */ 1497: 1498: else if (code0 == REG && code1 == REG 1499: && REGNO_POINTER_FLAG (REGNO (arg0))) 1.1 root 1500: { 1.1.1.4 root 1501: record_address_regs (arg0, BASE_REG_CLASS, scale); 1502: record_address_regs (arg1, INDEX_REG_CLASS, scale); 1.1 root 1503: } 1.1.1.4 root 1504: 1505: /* If this is the sum of two registers and neither is known to 1506: be a pointer, count equal chances that each might be a base 1507: or index register. This case should be rare. */ 1508: 1509: else if (code0 == REG && code1 == REG 1510: && ! REGNO_POINTER_FLAG (REGNO (arg0)) 1511: && ! REGNO_POINTER_FLAG (REGNO (arg1))) 1.1 root 1512: { 1.1.1.4 root 1513: record_address_regs (arg0, BASE_REG_CLASS, scale / 2); 1514: record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); 1515: record_address_regs (arg1, BASE_REG_CLASS, scale / 2); 1516: record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); 1.1 root 1517: } 1518: 1.1.1.4 root 1519: /* In all other cases, the first operand is an index and the 1520: second is the base. */ 1521: 1522: else 1523: { 1524: record_address_regs (arg0, INDEX_REG_CLASS, scale); 1525: record_address_regs (arg1, BASE_REG_CLASS, scale); 1526: } 1.1 root 1527: } 1528: break; 1529: 1530: case POST_INC: 1531: case PRE_INC: 1532: case POST_DEC: 1533: case PRE_DEC: 1534: /* Double the importance of a pseudo register that is incremented 1535: or decremented, since it would take two extra insns 1.1.1.4 root 1536: if it ends up in the wrong place. If the operand is a pseudo, 1537: show it is being used in an INC_DEC context. */ 1538: 1539: #ifdef FORBIDDEN_INC_DEC_CLASSES 1540: if (GET_CODE (XEXP (x, 0)) == REG 1541: && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) 1542: in_inc_dec[REGNO (XEXP (x, 0))] = 1; 1543: #endif 1544: 1545: record_address_regs (XEXP (x, 0), class, 2 * scale); 1.1 root 1546: break; 1547: 1548: case REG: 1549: { 1.1.1.4 root 1550: register struct costs *pp = &costs[REGNO (x)]; 1551: register int i; 1.1 root 1552: 1.1.1.4 root 1553: pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2; 1.1 root 1554: 1.1.1.4 root 1555: for (i = 0; i < N_REG_CLASSES; i++) 1556: pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2; 1.1 root 1557: } 1558: break; 1559: 1560: default: 1561: { 1562: register char *fmt = GET_RTX_FORMAT (code); 1563: register int i; 1564: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1565: if (fmt[i] == 'e') 1.1.1.4 root 1566: record_address_regs (XEXP (x, i), class, scale); 1.1 root 1567: } 1568: } 1569: } 1.1.1.7 ! root 1570: ! 1571: #ifdef FORBIDDEN_INC_DEC_CLASSES ! 1572: ! 1573: /* Return 1 if REG is valid as an auto-increment memory reference ! 1574: to an object of MODE. */ ! 1575: ! 1576: static ! 1577: auto_inc_dec_reg_p (reg, mode) ! 1578: rtx reg; ! 1579: enum machine_mode mode; ! 1580: { ! 1581: #ifdef HAVE_POST_INCREMENT ! 1582: if (memory_address_p (mode, gen_rtx (POST_INC, Pmode, reg))) ! 1583: return 1; ! 1584: #endif ! 1585: ! 1586: #ifdef HAVE_POST_DECREMENT ! 1587: if (memory_address_p (mode, gen_rtx (POST_DEC, Pmode, reg))) ! 1588: return 1; ! 1589: #endif ! 1590: ! 1591: #ifdef HAVE_PRE_INCREMENT ! 1592: if (memory_address_p (mode, gen_rtx (PRE_INC, Pmode, reg))) ! 1593: return 1; ! 1594: #endif ! 1595: ! 1596: #ifdef HAVE_PRE_DECREMENT ! 1597: if (memory_address_p (mode, gen_rtx (PRE_DEC, Pmode, reg))) ! 1598: return 1; ! 1599: #endif ! 1600: ! 1601: return 0; ! 1602: } ! 1603: #endif ! 1604: 1.1 root 1605: #endif /* REGISTER_CONSTRAINTS */ 1606: 1607: /* This is the `regscan' pass of the compiler, run just before cse 1608: and again just before loop. 1609: 1610: It finds the first and last use of each pseudo-register 1611: and records them in the vectors regno_first_uid, regno_last_uid 1612: and counts the number of sets in the vector reg_n_sets. 1613: 1614: REPEAT is nonzero the second time this is called. */ 1615: 1616: /* Indexed by pseudo register number, gives uid of first insn using the reg 1617: (as of the time reg_scan is called). */ 1618: 1.1.1.4 root 1619: int *regno_first_uid; 1.1 root 1620: 1621: /* Indexed by pseudo register number, gives uid of last insn using the reg 1622: (as of the time reg_scan is called). */ 1623: 1.1.1.4 root 1624: int *regno_last_uid; 1.1 root 1625: 1.1.1.6 root 1626: /* Indexed by pseudo register number, gives uid of last insn using the reg 1627: or mentioning it in a note (as of the time reg_scan is called). */ 1628: 1629: int *regno_last_note_uid; 1630: 1.1 root 1631: /* Record the number of registers we used when we allocated the above two 1632: tables. If we are called again with more than this, we must re-allocate 1633: the tables. */ 1634: 1635: static int highest_regno_in_uid_map; 1636: 1637: /* Maximum number of parallel sets and clobbers in any insn in this fn. 1638: Always at least 3, since the combiner could put that many togetherm 1639: and we want this to remain correct for all the remaining passes. */ 1640: 1641: int max_parallel; 1642: 1643: void 1644: reg_scan (f, nregs, repeat) 1645: rtx f; 1646: int nregs; 1647: int repeat; 1648: { 1649: register rtx insn; 1650: 1651: if (!repeat || nregs > highest_regno_in_uid_map) 1652: { 1653: /* Leave some spare space in case more regs are allocated. */ 1654: highest_regno_in_uid_map = nregs + nregs / 20; 1655: regno_first_uid 1.1.1.4 root 1656: = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); 1.1 root 1657: regno_last_uid 1.1.1.4 root 1658: = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); 1.1.1.6 root 1659: regno_last_note_uid 1660: = (int *) oballoc (highest_regno_in_uid_map * sizeof (int)); 1.1 root 1661: reg_n_sets 1662: = (short *) oballoc (highest_regno_in_uid_map * sizeof (short)); 1663: } 1664: 1.1.1.7 ! root 1665: bzero ((char *) regno_first_uid, highest_regno_in_uid_map * sizeof (int)); ! 1666: bzero ((char *) regno_last_uid, highest_regno_in_uid_map * sizeof (int)); ! 1667: bzero ((char *) regno_last_note_uid, ! 1668: highest_regno_in_uid_map * sizeof (int)); ! 1669: bzero ((char *) reg_n_sets, highest_regno_in_uid_map * sizeof (short)); 1.1 root 1670: 1671: max_parallel = 3; 1672: 1673: for (insn = f; insn; insn = NEXT_INSN (insn)) 1674: if (GET_CODE (insn) == INSN 1675: || GET_CODE (insn) == CALL_INSN 1676: || GET_CODE (insn) == JUMP_INSN) 1677: { 1678: if (GET_CODE (PATTERN (insn)) == PARALLEL 1679: && XVECLEN (PATTERN (insn), 0) > max_parallel) 1680: max_parallel = XVECLEN (PATTERN (insn), 0); 1.1.1.6 root 1681: reg_scan_mark_refs (PATTERN (insn), insn, 0); 1682: 1683: if (REG_NOTES (insn)) 1684: reg_scan_mark_refs (REG_NOTES (insn), insn, 1); 1.1 root 1685: } 1686: } 1687: 1.1.1.6 root 1688: /* X is the expression to scan. INSN is the insn it appears in. 1689: NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */ 1690: 1.1.1.7 ! root 1691: static void 1.1.1.6 root 1692: reg_scan_mark_refs (x, insn, note_flag) 1.1 root 1693: rtx x; 1.1.1.5 root 1694: rtx insn; 1.1.1.6 root 1695: int note_flag; 1.1 root 1696: { 1697: register enum rtx_code code = GET_CODE (x); 1698: register rtx dest; 1.1.1.5 root 1699: register rtx note; 1.1 root 1700: 1701: switch (code) 1702: { 1703: case CONST_INT: 1704: case CONST: 1705: case CONST_DOUBLE: 1706: case CC0: 1707: case PC: 1708: case SYMBOL_REF: 1709: case LABEL_REF: 1710: case ADDR_VEC: 1711: case ADDR_DIFF_VEC: 1712: return; 1713: 1714: case REG: 1715: { 1716: register int regno = REGNO (x); 1717: 1.1.1.6 root 1718: regno_last_note_uid[regno] = INSN_UID (insn); 1719: if (!note_flag) 1720: regno_last_uid[regno] = INSN_UID (insn); 1.1 root 1721: if (regno_first_uid[regno] == 0) 1.1.1.5 root 1722: regno_first_uid[regno] = INSN_UID (insn); 1.1 root 1723: } 1724: break; 1725: 1.1.1.6 root 1726: case EXPR_LIST: 1727: if (XEXP (x, 0)) 1728: reg_scan_mark_refs (XEXP (x, 0), insn, note_flag); 1729: if (XEXP (x, 1)) 1730: reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); 1731: break; 1732: 1733: case INSN_LIST: 1734: if (XEXP (x, 1)) 1735: reg_scan_mark_refs (XEXP (x, 1), insn, note_flag); 1736: break; 1737: 1.1 root 1738: case SET: 1739: /* Count a set of the destination if it is a register. */ 1740: for (dest = SET_DEST (x); 1741: GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART 1742: || GET_CODE (dest) == ZERO_EXTEND; 1743: dest = XEXP (dest, 0)) 1744: ; 1745: 1746: if (GET_CODE (dest) == REG) 1747: reg_n_sets[REGNO (dest)]++; 1748: 1.1.1.5 root 1749: /* If this is setting a pseudo from another pseudo or the sum of a 1750: pseudo and a constant integer and the other pseudo is known to be 1751: a pointer, set the destination to be a pointer as well. 1752: 1753: Likewise if it is setting the destination from an address or from a 1754: value equivalent to an address or to the sum of an address and 1755: something else. 1756: 1757: But don't do any of this if the pseudo corresponds to a user 1758: variable since it should have already been set as a pointer based 1759: on the type. */ 1760: 1761: if (GET_CODE (SET_DEST (x)) == REG 1762: && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER 1763: && ! REG_USERVAR_P (SET_DEST (x)) 1764: && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) 1765: && ((GET_CODE (SET_SRC (x)) == REG 1766: && REGNO_POINTER_FLAG (REGNO (SET_SRC (x)))) 1767: || ((GET_CODE (SET_SRC (x)) == PLUS 1768: || GET_CODE (SET_SRC (x)) == LO_SUM) 1769: && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 1770: && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 1771: && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0)))) 1772: || GET_CODE (SET_SRC (x)) == CONST 1773: || GET_CODE (SET_SRC (x)) == SYMBOL_REF 1774: || GET_CODE (SET_SRC (x)) == LABEL_REF 1775: || (GET_CODE (SET_SRC (x)) == HIGH 1776: && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST 1777: || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF 1778: || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) 1779: || ((GET_CODE (SET_SRC (x)) == PLUS 1780: || GET_CODE (SET_SRC (x)) == LO_SUM) 1781: && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST 1782: || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF 1783: || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) 1784: || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 1785: && (GET_CODE (XEXP (note, 0)) == CONST 1786: || GET_CODE (XEXP (note, 0)) == SYMBOL_REF 1787: || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) 1788: REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1; 1789: 1.1 root 1790: /* ... fall through ... */ 1791: 1792: default: 1793: { 1794: register char *fmt = GET_RTX_FORMAT (code); 1795: register int i; 1796: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1797: { 1798: if (fmt[i] == 'e') 1.1.1.6 root 1799: reg_scan_mark_refs (XEXP (x, i), insn, note_flag); 1.1 root 1800: else if (fmt[i] == 'E' && XVEC (x, i) != 0) 1801: { 1802: register int j; 1803: for (j = XVECLEN (x, i) - 1; j >= 0; j--) 1.1.1.6 root 1804: reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag); 1.1 root 1805: } 1806: } 1807: } 1808: } 1809: } 1810: 1811: /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 1812: is also in C2. */ 1813: 1814: int 1815: reg_class_subset_p (c1, c2) 1816: register enum reg_class c1; 1817: register enum reg_class c2; 1818: { 1819: if (c1 == c2) return 1; 1820: 1821: if (c2 == ALL_REGS) 1822: win: 1823: return 1; 1824: GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1], 1825: reg_class_contents[(int)c2], 1826: win); 1827: return 0; 1828: } 1829: 1830: /* Return nonzero if there is a register that is in both C1 and C2. */ 1831: 1832: int 1833: reg_classes_intersect_p (c1, c2) 1834: register enum reg_class c1; 1835: register enum reg_class c2; 1836: { 1837: #ifdef HARD_REG_SET 1838: register 1839: #endif 1840: HARD_REG_SET c; 1841: 1842: if (c1 == c2) return 1; 1843: 1844: if (c1 == ALL_REGS || c2 == ALL_REGS) 1845: return 1; 1846: 1847: COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); 1848: AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); 1849: 1850: GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); 1851: return 1; 1852: 1853: lose: 1854: return 0; 1855: } 1856:
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