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1.1 root 1: /* Search an insn for pseudo regs that must be in hard regs and are not.
2: Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: /* This file contains subroutines used only from the file reload1.c.
22: It knows how to scan one insn for operands and values
23: that need to be copied into registers to make valid code.
24: It also finds other operands and values which are valid
25: but for which equivalent values in registers exist and
26: ought to be used instead.
27:
28: Before processing the first insn of the function, call `init_reload'.
29:
30: To scan an insn, call `find_reloads'. This does two things:
31: 1. sets up tables describing which values must be reloaded
32: for this insn, and what kind of hard regs they must be reloaded into;
33: 2. optionally record the locations where those values appear in
34: the data, so they can be replaced properly later.
35: This is done only if the second arg to `find_reloads' is nonzero.
36:
37: The third arg to `find_reloads' specifies the number of levels
38: of indirect addressing supported by the machine. If it is zero,
39: indirect addressing is not valid. If it is one, (MEM (REG n))
40: is valid even if (REG n) did not get a hard register; if it is two,
41: (MEM (MEM (REG n))) is also valid even if (REG n) did not get a
42: hard register, and similarly for higher values.
43:
44: Then you must choose the hard regs to reload those pseudo regs into,
45: and generate appropriate load insns before this insn and perhaps
46: also store insns after this insn. Set up the array `reload_reg_rtx'
47: to contain the REG rtx's for the registers you used. In some
48: cases `find_reloads' will return a nonzero value in `reload_reg_rtx'
49: for certain reloads. Then that tells you which register to use,
50: so you do not need to allocate one. But you still do need to add extra
51: instructions to copy the value into and out of that register.
52:
53: Finally you must call `subst_reloads' to substitute the reload reg rtx's
54: into the locations already recorded.
55:
56: NOTE SIDE EFFECTS:
57:
58: find_reloads can alter the operands of the instruction it is called on.
59:
60: 1. Two operands of any sort may be interchanged, if they are in a
61: commutative instruction.
62: This happens only if find_reloads thinks the instruction will compile
63: better that way.
64:
65: 2. Pseudo-registers that are equivalent to constants are replaced
66: with those constants if they are not in hard registers.
67:
68: 1 happens every time find_reloads is called.
69: 2 happens only when REPLACE is 1, which is only when
70: actually doing the reloads, not when just counting them.
71:
72:
73: Using a reload register for several reloads in one insn:
74:
75: When an insn has reloads, it is considered as having three parts:
76: the input reloads, the insn itself after reloading, and the output reloads.
77: Reloads of values used in memory addresses are often needed for only one part.
78:
79: When this is so, reload_when_needed records which part needs the reload.
80: Two reloads for different parts of the insn can share the same reload
81: register.
82:
83: When a reload is used for addresses in multiple parts, or when it is
84: an ordinary operand, it is classified as RELOAD_OTHER, and cannot share
85: a register with any other reload. */
86:
87: #define REG_OK_STRICT
88:
89: #include "config.h"
90: #include "rtl.h"
91: #include "insn-config.h"
92: #include "insn-codes.h"
93: #include "recog.h"
94: #include "reload.h"
95: #include "regs.h"
96: #include "hard-reg-set.h"
97: #include "flags.h"
98: #include "real.h"
99:
100: #ifndef REGISTER_MOVE_COST
101: #define REGISTER_MOVE_COST(x, y) 2
102: #endif
103:
104: /* The variables set up by `find_reloads' are:
105:
106: n_reloads number of distinct reloads needed; max reload # + 1
107: tables indexed by reload number
108: reload_in rtx for value to reload from
109: reload_out rtx for where to store reload-reg afterward if nec
110: (often the same as reload_in)
111: reload_reg_class enum reg_class, saying what regs to reload into
112: reload_inmode enum machine_mode; mode this operand should have
113: when reloaded, on input.
114: reload_outmode enum machine_mode; mode this operand should have
115: when reloaded, on output.
116: reload_strict_low char; currently always zero; used to mean that this
117: reload is inside a STRICT_LOW_PART, but we don't
118: need to know this anymore.
119: reload_optional char, nonzero for an optional reload.
120: Optional reloads are ignored unless the
121: value is already sitting in a register.
122: reload_inc int, positive amount to increment or decrement by if
123: reload_in is a PRE_DEC, PRE_INC, POST_DEC, POST_INC.
124: Ignored otherwise (don't assume it is zero).
125: reload_in_reg rtx. A reg for which reload_in is the equivalent.
126: If reload_in is a symbol_ref which came from
127: reg_equiv_constant, then this is the pseudo
128: which has that symbol_ref as equivalent.
129: reload_reg_rtx rtx. This is the register to reload into.
130: If it is zero when `find_reloads' returns,
131: you must find a suitable register in the class
132: specified by reload_reg_class, and store here
133: an rtx for that register with mode from
134: reload_inmode or reload_outmode.
135: reload_nocombine char, nonzero if this reload shouldn't be
136: combined with another reload.
137: reload_needed_for rtx, operand this reload is needed for address of.
138: 0 means it isn't needed for addressing.
139: reload_needed_for_multiple
140: int, 1 if this reload needed for more than one thing.
141: reload_when_needed enum, classifies reload as needed either for
142: addressing an input reload, addressing an output,
143: for addressing a non-reloaded mem ref,
144: or for unspecified purposes (i.e., more than one
145: of the above).
146: reload_secondary_reload int, gives the reload number of a secondary
147: reload, when needed; otherwise -1
148: reload_secondary_p int, 1 if this is a secondary register for one
149: or more reloads.
150: reload_secondary_icode enum insn_code, if a secondary reload is required,
151: gives the INSN_CODE that uses the secondary
152: reload as a scratch register, or CODE_FOR_nothing
153: if the secondary reload register is to be an
154: intermediate register. */
155: int n_reloads;
156:
157: rtx reload_in[MAX_RELOADS];
158: rtx reload_out[MAX_RELOADS];
159: enum reg_class reload_reg_class[MAX_RELOADS];
160: enum machine_mode reload_inmode[MAX_RELOADS];
161: enum machine_mode reload_outmode[MAX_RELOADS];
162: char reload_strict_low[MAX_RELOADS];
163: rtx reload_reg_rtx[MAX_RELOADS];
164: char reload_optional[MAX_RELOADS];
165: int reload_inc[MAX_RELOADS];
166: rtx reload_in_reg[MAX_RELOADS];
167: char reload_nocombine[MAX_RELOADS];
168: int reload_needed_for_multiple[MAX_RELOADS];
169: rtx reload_needed_for[MAX_RELOADS];
170: enum reload_when_needed reload_when_needed[MAX_RELOADS];
171: int reload_secondary_reload[MAX_RELOADS];
172: int reload_secondary_p[MAX_RELOADS];
173: enum insn_code reload_secondary_icode[MAX_RELOADS];
174:
175: /* All the "earlyclobber" operands of the current insn
176: are recorded here. */
177: int n_earlyclobbers;
178: rtx reload_earlyclobbers[MAX_RECOG_OPERANDS];
179:
180: /* Replacing reloads.
181:
182: If `replace_reloads' is nonzero, then as each reload is recorded
183: an entry is made for it in the table `replacements'.
184: Then later `subst_reloads' can look through that table and
185: perform all the replacements needed. */
186:
187: /* Nonzero means record the places to replace. */
188: static int replace_reloads;
189:
190: /* Each replacement is recorded with a structure like this. */
191: struct replacement
192: {
193: rtx *where; /* Location to store in */
194: rtx *subreg_loc; /* Location of SUBREG if WHERE is inside
195: a SUBREG; 0 otherwise. */
196: int what; /* which reload this is for */
197: enum machine_mode mode; /* mode it must have */
198: };
199:
200: static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)];
201:
202: /* Number of replacements currently recorded. */
203: static int n_replacements;
204:
205: /* MEM-rtx's created for pseudo-regs in stack slots not directly addressable;
206: (see reg_equiv_address). */
207: static rtx memlocs[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)];
208: static int n_memlocs;
209:
210: /* The instruction we are doing reloads for;
211: so we can test whether a register dies in it. */
212: static rtx this_insn;
213:
214: /* Nonzero if this instruction is a user-specified asm with operands. */
215: static int this_insn_is_asm;
216:
217: /* If hard_regs_live_known is nonzero,
218: we can tell which hard regs are currently live,
219: at least enough to succeed in choosing dummy reloads. */
220: static int hard_regs_live_known;
221:
222: /* Indexed by hard reg number,
223: element is nonegative if hard reg has been spilled.
224: This vector is passed to `find_reloads' as an argument
225: and is not changed here. */
226: static short *static_reload_reg_p;
227:
228: /* Set to 1 in subst_reg_equivs if it changes anything. */
229: static int subst_reg_equivs_changed;
230:
231: /* On return from push_reload, holds the reload-number for the OUT
232: operand, which can be different for that from the input operand. */
233: static int output_reloadnum;
234:
235: static int alternative_allows_memconst ();
236: static rtx find_dummy_reload ();
237: static rtx find_reloads_toplev ();
238: static int find_reloads_address ();
239: static int find_reloads_address_1 ();
240: static void find_reloads_address_part ();
241: static int hard_reg_set_here_p ();
242: /* static rtx forget_volatility (); */
243: static rtx subst_reg_equivs ();
244: static rtx subst_indexed_address ();
245: rtx find_equiv_reg ();
246: static int find_inc_amount ();
247:
248: #ifdef HAVE_SECONDARY_RELOADS
249:
250: /* Determine if any secondary reloads are needed for loading (if IN_P is
251: non-zero) or storing (if IN_P is zero) X to or from a reload register of
252: register class RELOAD_CLASS in mode RELOAD_MODE.
253:
254: Return the register class of a secondary reload register, or NO_REGS if
255: none. *PMODE is set to the mode that the register is required in.
256: If the reload register is needed as a scratch register instead of an
257: intermediate register, *PICODE is set to the insn_code of the insn to be
258: used to load or store the primary reload register; otherwise *PICODE
259: is set to CODE_FOR_nothing.
260:
261: In some cases (such as storing MQ into an external memory location on
262: the RT), both an intermediate register and a scratch register. In that
263: case, *PICODE is set to CODE_FOR_nothing, the class for the intermediate
264: register is returned, and the *PTERTIARY_... variables are set to describe
265: the scratch register. */
266:
267: static enum reg_class
268: find_secondary_reload (x, reload_class, reload_mode, in_p, picode, pmode,
269: ptertiary_class, ptertiary_icode, ptertiary_mode)
270: rtx x;
271: enum reg_class reload_class;
272: enum machine_mode reload_mode;
273: int in_p;
274: enum insn_code *picode;
275: enum machine_mode *pmode;
276: enum reg_class *ptertiary_class;
277: enum insn_code *ptertiary_icode;
278: enum machine_mode *ptertiary_mode;
279: {
280: enum reg_class class = NO_REGS;
281: enum machine_mode mode = reload_mode;
282: enum insn_code icode = CODE_FOR_nothing;
283: enum reg_class t_class = NO_REGS;
284: enum machine_mode t_mode = VOIDmode;
285: enum insn_code t_icode = CODE_FOR_nothing;
286:
287: #ifdef SECONDARY_INPUT_RELOAD_CLASS
288: if (in_p)
289: class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x);
290: #endif
291:
292: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
293: if (! in_p)
294: class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x);
295: #endif
296:
297: /* If we don't need any secondary registers, go away; the rest of the
298: values won't be used. */
299: if (class == NO_REGS)
300: return NO_REGS;
301:
302: /* Get a possible insn to use. If the predicate doesn't accept X, don't
303: use the insn. */
304:
305: icode = (in_p ? reload_in_optab[(int) reload_mode]
306: : reload_out_optab[(int) reload_mode]);
307:
308: if (icode != CODE_FOR_nothing
309: && insn_operand_predicate[(int) icode][in_p]
310: && (! (insn_operand_predicate[(int) icode][in_p]) (x, reload_mode)))
311: icode = CODE_FOR_nothing;
312:
313: /* If we will be using an insn, see if it can directly handle the reload
314: register we will be using. If it can, the secondary reload is for a
315: scratch register. If it can't, we will use the secondary reload for
316: an intermediate register and require a tertiary reload for the scratch
317: register. */
318:
319: if (icode != CODE_FOR_nothing)
320: {
321: /* If IN_P is non-zero, the reload register will be the output in
322: operand 0. If IN_P is zero, the reload register will be the input
323: in operand 1. Outputs should have an initial "=", which we must
324: skip. */
325:
326: enum reg_class insn_class
327: = REG_CLASS_FROM_LETTER (insn_operand_constraint[(int) icode][!in_p][in_p]);
328:
329: if (insn_class == NO_REGS
330: || (in_p && insn_operand_constraint[(int) icode][!in_p][0] != '=')
331: /* The scratch register's constraint must start with "=&". */
332: || insn_operand_constraint[(int) icode][2][0] != '='
333: || insn_operand_constraint[(int) icode][2][1] != '&')
334: abort ();
335:
336: if (reg_class_subset_p (reload_class, insn_class))
337: mode = insn_operand_mode[(int) icode][2];
338: else
339: {
340: class = insn_class;
341: t_mode = insn_operand_mode[(int) icode][2];
342: t_class
343: = REG_CLASS_FROM_LETTER (insn_operand_constraint[(int) icode][2][2]);
344: t_icode = icode;
345: icode = CODE_FOR_nothing;
346: }
347: }
348:
349: *pmode = mode;
350: *picode = icode;
351: *ptertiary_class = t_class;
352: *ptertiary_mode = t_mode;
353: *ptertiary_icode = t_icode;
354:
355: return class;
356: }
357: #endif /* HAVE_SECONDARY_RELOADS */
358:
359: /* Record one (sometimes two) reload that needs to be performed.
360: IN is an rtx saying where the data are to be found before this instruction.
361: OUT says where they must be stored after the instruction.
362: (IN is zero for data not read, and OUT is zero for data not written.)
363: INLOC and OUTLOC point to the places in the instructions where
364: IN and OUT were found.
365: CLASS is a register class required for the reloaded data.
366: INMODE is the machine mode that the instruction requires
367: for the reg that replaces IN and OUTMODE is likewise for OUT.
368:
369: If IN is zero, then OUT's location and mode should be passed as
370: INLOC and INMODE.
371:
372: STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx.
373:
374: OPTIONAL nonzero means this reload does not need to be performed:
375: it can be discarded if that is more convenient.
376:
377: The return value is the reload-number for this reload.
378:
379: If both IN and OUT are nonzero, in some rare cases we might
380: want to make two separate reloads. (Actually we never do this now.)
381: Therefore, the reload-number for OUT is stored in
382: output_reloadnum when we return; the return value applies to IN.
383: Usually (presently always), when IN and OUT are nonzero,
384: the two reload-numbers are equal, but the caller should be careful to
385: distinguish them. */
386:
387: static int
388: push_reload (in, out, inloc, outloc, class,
389: inmode, outmode, strict_low, optional, needed_for)
390: register rtx in, out;
391: rtx *inloc, *outloc;
392: enum reg_class class;
393: enum machine_mode inmode, outmode;
394: int strict_low;
395: int optional;
396: rtx needed_for;
397: {
398: register int i;
399: int dont_share = 0;
400: rtx *in_subreg_loc = 0, *out_subreg_loc = 0;
401: int secondary_reload = -1;
402: enum insn_code secondary_icode = CODE_FOR_nothing;
403:
404: /* Compare two RTX's. */
405: #define MATCHES(x, y) \
406: (x == y || (x != 0 && (GET_CODE (x) == REG \
407: ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \
408: : rtx_equal_p (x, y) && ! side_effects_p (x))))
409:
410: /* INMODE and/or OUTMODE could be VOIDmode if no mode
411: has been specified for the operand. In that case,
412: use the operand's mode as the mode to reload. */
413: if (inmode == VOIDmode && in != 0)
414: inmode = GET_MODE (in);
415: if (outmode == VOIDmode && out != 0)
416: outmode = GET_MODE (out);
417:
418: /* If IN is a pseudo register everywhere-equivalent to a constant, and
419: it is not in a hard register, reload straight from the constant,
420: since we want to get rid of such pseudo registers.
421: Often this is done earlier, but not always in find_reloads_address. */
422: if (in != 0 && GET_CODE (in) == REG)
423: {
424: register int regno = REGNO (in);
425:
426: if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
427: && reg_equiv_constant[regno] != 0)
428: in = reg_equiv_constant[regno];
429: }
430:
431: /* Likewise for OUT. Of course, OUT will never be equivalent to
432: an actual constant, but it might be equivalent to a memory location
433: (in the case of a parameter). */
434: if (out != 0 && GET_CODE (out) == REG)
435: {
436: register int regno = REGNO (out);
437:
438: if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
439: && reg_equiv_constant[regno] != 0)
440: out = reg_equiv_constant[regno];
441: }
442:
443: /* If we have a read-write operand with an address side-effect,
444: change either IN or OUT so the side-effect happens only once. */
445: if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out))
446: {
447: if (GET_CODE (XEXP (in, 0)) == POST_INC
448: || GET_CODE (XEXP (in, 0)) == POST_DEC)
449: in = gen_rtx (MEM, GET_MODE (in), XEXP (XEXP (in, 0), 0));
450: if (GET_CODE (XEXP (in, 0)) == PRE_INC
451: || GET_CODE (XEXP (in, 0)) == PRE_DEC)
452: out = gen_rtx (MEM, GET_MODE (out), XEXP (XEXP (out, 0), 0));
453: }
454:
455: /* If we are reloading a (SUBREG (MEM ...) ...) or (SUBREG constant ...),
456: really reload just the inside expression in its own mode.
457: If we have (SUBREG:M1 (REG:M2 ...) ...) with M1 wider than M2 and the
458: register is a pseudo, this will become the same as the above case.
459: Do the same for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where
460: either M1 is not valid for R or M2 is wider than a word but we only
461: need one word to store an M2-sized quantity in R.
462: Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere;
463: we can't handle it here because CONST_INT does not indicate a mode.
464:
465: Similarly, we must reload the inside expression if we have a
466: STRICT_LOW_PART (presumably, in == out in the cas). */
467:
468: if (in != 0 && GET_CODE (in) == SUBREG
469: && (GET_CODE (SUBREG_REG (in)) != REG
470: || strict_low
471: || (GET_CODE (SUBREG_REG (in)) == REG
472: && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER
473: && (GET_MODE_SIZE (inmode)
474: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))))
475: || (GET_CODE (SUBREG_REG (in)) == REG
476: && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
477: && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (in)), inmode)
478: || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD
479: && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
480: > UNITS_PER_WORD)
481: && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
482: / UNITS_PER_WORD)
483: != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)),
484: GET_MODE (SUBREG_REG (in)))))))))
485: {
486: in_subreg_loc = inloc;
487: inloc = &SUBREG_REG (in);
488: in = *inloc;
489: if (GET_CODE (in) == MEM)
490: /* This is supposed to happen only for paradoxical subregs made by
491: combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */
492: if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode))
493: abort ();
494: inmode = GET_MODE (in);
495: }
496:
497: /* Similarly for paradoxical and problematical SUBREGs on the output.
498: Note that there is no reason we need worry about the previous value
499: of SUBREG_REG (out); even if wider than out,
500: storing in a subreg is entitled to clobber it all
501: (except in the case of STRICT_LOW_PART,
502: and in that case the constraint should label it input-output.) */
503: if (out != 0 && GET_CODE (out) == SUBREG
504: && (GET_CODE (SUBREG_REG (out)) != REG
505: || strict_low
506: || (GET_CODE (SUBREG_REG (out)) == REG
507: && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER
508: && (GET_MODE_SIZE (outmode)
509: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))))
510: || (GET_CODE (SUBREG_REG (out)) == REG
511: && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
512: && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (out)), outmode)
513: || (GET_MODE_SIZE (outmode) <= UNITS_PER_WORD
514: && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
515: > UNITS_PER_WORD)
516: && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
517: / UNITS_PER_WORD)
518: != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)),
519: GET_MODE (SUBREG_REG (out)))))))))
520: {
521: out_subreg_loc = outloc;
522: outloc = &SUBREG_REG (out);
523: out = *outloc;
524: if (GET_CODE (out) == MEM
525: && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode))
526: abort ();
527: outmode = GET_MODE (out);
528: }
529:
530: /* That's all we use STRICT_LOW for, so clear it. At some point,
531: we may want to get rid of reload_strict_low. */
532: strict_low = 0;
533:
534: /* If IN appears in OUT, we can't share any input-only reload for IN. */
535: if (in != 0 && out != 0 && GET_CODE (out) == MEM
536: && (GET_CODE (in) == REG || GET_CODE (in) == MEM)
537: && reg_overlap_mentioned_p (in, XEXP (out, 0)))
538: dont_share = 1;
539:
540: /* Narrow down the class of register wanted if that is
541: desirable on this machine for efficiency. */
542: if (in != 0)
543: class = PREFERRED_RELOAD_CLASS (in, class);
544:
545: /* Make sure we use a class that can handle the actual pseudo
546: inside any subreg. For example, on the 386, QImode regs
547: can appear within SImode subregs. Although GENERAL_REGS
548: can handle SImode, QImode needs a smaller class. */
549: #ifdef LIMIT_RELOAD_CLASS
550: if (in_subreg_loc)
551: class = LIMIT_RELOAD_CLASS (inmode, class);
552: else if (in != 0 && GET_CODE (in) == SUBREG)
553: class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), class);
554:
555: if (out_subreg_loc)
556: class = LIMIT_RELOAD_CLASS (outmode, class);
557: if (out != 0 && GET_CODE (out) == SUBREG)
558: class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), class);
559: #endif
560:
561: if (class == NO_REGS)
562: abort ();
563:
564: /* Verify that this class is at least possible for the mode that
565: is specified. */
566: if (this_insn_is_asm)
567: {
568: enum machine_mode mode;
569: if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode))
570: mode = inmode;
571: else
572: mode = outmode;
573: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
574: if (HARD_REGNO_MODE_OK (i, mode)
575: && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i))
576: {
577: int nregs = HARD_REGNO_NREGS (i, mode);
578:
579: int j;
580: for (j = 1; j < nregs; j++)
581: if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j))
582: break;
583: if (j == nregs)
584: break;
585: }
586: if (i == FIRST_PSEUDO_REGISTER)
587: {
588: error_for_asm (this_insn, "impossible register constraint in `asm'");
589: class = ALL_REGS;
590: }
591: }
592:
593: /* We can use an existing reload if the class is right
594: and at least one of IN and OUT is a match
595: and the other is at worst neutral.
596: (A zero compared against anything is neutral.) */
597: for (i = 0; i < n_reloads; i++)
598: if ((reg_class_subset_p (class, reload_reg_class[i])
599: || reg_class_subset_p (reload_reg_class[i], class))
600: && reload_strict_low[i] == strict_low
601: /* If the existing reload has a register, it must fit our class. */
602: && (reload_reg_rtx[i] == 0
603: || TEST_HARD_REG_BIT (reg_class_contents[(int) class],
604: true_regnum (reload_reg_rtx[i])))
605: && ((in != 0 && MATCHES (reload_in[i], in) && ! dont_share
606: && (out == 0 || reload_out[i] == 0 || MATCHES (reload_out[i], out)))
607: ||
608: (out != 0 && MATCHES (reload_out[i], out)
609: && (in == 0 || reload_in[i] == 0 || MATCHES (reload_in[i], in)))))
610: break;
611:
612: /* Reloading a plain reg for input can match a reload to postincrement
613: that reg, since the postincrement's value is the right value.
614: Likewise, it can match a preincrement reload, since we regard
615: the preincrementation as happening before any ref in this insn
616: to that register. */
617: if (i == n_reloads)
618: for (i = 0; i < n_reloads; i++)
619: if ((reg_class_subset_p (class, reload_reg_class[i])
620: || reg_class_subset_p (reload_reg_class[i], class))
621: /* If the existing reload has a register, it must fit our class. */
622: && (reload_reg_rtx[i] == 0
623: || TEST_HARD_REG_BIT (reg_class_contents[(int) class],
624: true_regnum (reload_reg_rtx[i])))
625: && reload_strict_low[i] == strict_low
626: && out == 0 && reload_out[i] == 0 && reload_in[i] != 0
627: && ((GET_CODE (in) == REG
628: && (GET_CODE (reload_in[i]) == POST_INC
629: || GET_CODE (reload_in[i]) == POST_DEC
630: || GET_CODE (reload_in[i]) == PRE_INC
631: || GET_CODE (reload_in[i]) == PRE_DEC)
632: && MATCHES (XEXP (reload_in[i], 0), in))
633: ||
634: (GET_CODE (reload_in[i]) == REG
635: && (GET_CODE (in) == POST_INC
636: || GET_CODE (in) == POST_DEC
637: || GET_CODE (in) == PRE_INC
638: || GET_CODE (in) == PRE_DEC)
639: && MATCHES (XEXP (in, 0), reload_in[i]))))
640: {
641: /* Make sure reload_in ultimately has the increment,
642: not the plain register. */
643: if (GET_CODE (in) == REG)
644: in = reload_in[i];
645: break;
646: }
647:
648: if (i == n_reloads)
649: {
650: #ifdef HAVE_SECONDARY_RELOADS
651: enum reg_class secondary_class = NO_REGS;
652: enum reg_class secondary_out_class = NO_REGS;
653: enum machine_mode secondary_mode = inmode;
654: enum machine_mode secondary_out_mode = outmode;
655: enum insn_code secondary_icode;
656: enum insn_code secondary_out_icode = CODE_FOR_nothing;
657: enum reg_class tertiary_class = NO_REGS;
658: enum reg_class tertiary_out_class = NO_REGS;
659: enum machine_mode tertiary_mode;
660: enum machine_mode tertiary_out_mode;
661: enum insn_code tertiary_icode;
662: enum insn_code tertiary_out_icode = CODE_FOR_nothing;
663: int tertiary_reload = -1;
664:
665: /* See if we need a secondary reload register to move between
666: CLASS and IN or CLASS and OUT. Get the modes and icodes to
667: use for each of them if so. */
668:
669: #ifdef SECONDARY_INPUT_RELOAD_CLASS
670: if (in != 0)
671: secondary_class
672: = find_secondary_reload (in, class, inmode, 1, &secondary_icode,
673: &secondary_mode, &tertiary_class,
674: &tertiary_icode, &tertiary_mode);
675: #endif
676:
677: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
678: if (out != 0 && GET_CODE (out) != SCRATCH)
679: secondary_out_class
680: = find_secondary_reload (out, class, outmode, 0,
681: &secondary_out_icode, &secondary_out_mode,
682: &tertiary_out_class, &tertiary_out_icode,
683: &tertiary_out_mode);
684: #endif
685:
686: /* We can only record one secondary and one tertiary reload. If both
687: IN and OUT need secondary reloads, we can only make an in-out
688: reload if neither need an insn and if the classes are compatible. */
689:
690: if (secondary_class != NO_REGS && secondary_out_class != NO_REGS
691: && reg_class_subset_p (secondary_out_class, secondary_class))
692: secondary_class = secondary_out_class;
693:
694: if (secondary_class != NO_REGS && secondary_out_class != NO_REGS
695: && (! reg_class_subset_p (secondary_class, secondary_out_class)
696: || secondary_icode != CODE_FOR_nothing
697: || secondary_out_icode != CODE_FOR_nothing))
698: {
699: push_reload (0, out, 0, outloc, class, VOIDmode, outmode,
700: strict_low, optional, needed_for);
701: out = 0;
702: outloc = 0;
703: outmode = VOIDmode;
704: }
705:
706: /* If we need a secondary reload for OUT but not IN, copy the
707: information. */
708: if (secondary_class == NO_REGS && secondary_out_class != NO_REGS)
709: {
710: secondary_class = secondary_out_class;
711: secondary_icode = secondary_out_icode;
712: tertiary_class = tertiary_out_class;
713: tertiary_icode = tertiary_out_icode;
714: tertiary_mode = tertiary_out_mode;
715: }
716:
717: if (secondary_class != NO_REGS)
718: {
719: /* If we need a tertiary reload, see if we have one we can reuse
720: or else make one. */
721:
722: if (tertiary_class != NO_REGS)
723: {
724: for (tertiary_reload = 0; tertiary_reload < n_reloads;
725: tertiary_reload++)
726: if (reload_secondary_p[tertiary_reload]
727: && (reg_class_subset_p (tertiary_class,
728: reload_reg_class[tertiary_reload])
729: || reg_class_subset_p (reload_reg_class[tertiary_reload],
730: tertiary_class))
731: && ((reload_inmode[tertiary_reload] == tertiary_mode)
732: || reload_inmode[tertiary_reload] == VOIDmode)
733: && ((reload_outmode[tertiary_reload] == tertiary_mode)
734: || reload_outmode[tertiary_reload] == VOIDmode)
735: && (reload_secondary_icode[tertiary_reload]
736: == CODE_FOR_nothing))
737:
738: {
739: if (tertiary_mode != VOIDmode)
740: reload_inmode[tertiary_reload] = tertiary_mode;
741: if (tertiary_out_mode != VOIDmode)
742: reload_outmode[tertiary_reload] = tertiary_mode;
743: if (reg_class_subset_p (tertiary_class,
744: reload_reg_class[tertiary_reload]))
745: reload_reg_class[tertiary_reload] = tertiary_class;
746: if (reload_needed_for[tertiary_reload] != needed_for)
747: reload_needed_for_multiple[tertiary_reload] = 1;
748: reload_optional[tertiary_reload] &= optional;
749: reload_secondary_p[tertiary_reload] = 1;
750: }
751:
752: if (tertiary_reload == n_reloads)
753: {
754: /* We need to make a new tertiary reload for this register
755: class. */
756: reload_in[tertiary_reload] = reload_out[tertiary_reload] = 0;
757: reload_reg_class[tertiary_reload] = tertiary_class;
758: reload_inmode[tertiary_reload] = tertiary_mode;
759: reload_outmode[tertiary_reload] = tertiary_mode;
760: reload_reg_rtx[tertiary_reload] = 0;
761: reload_optional[tertiary_reload] = optional;
762: reload_inc[tertiary_reload] = 0;
763: reload_strict_low[tertiary_reload] = 0;
764: /* Maybe we could combine these, but it seems too tricky. */
765: reload_nocombine[tertiary_reload] = 1;
766: reload_in_reg[tertiary_reload] = 0;
767: reload_needed_for[tertiary_reload] = needed_for;
768: reload_needed_for_multiple[tertiary_reload] = 0;
769: reload_secondary_reload[tertiary_reload] = -1;
770: reload_secondary_icode[tertiary_reload] = CODE_FOR_nothing;
771: reload_secondary_p[tertiary_reload] = 1;
772:
773: n_reloads++;
774: i = n_reloads;
775: }
776: }
777:
778: /* See if we can reuse an existing secondary reload. */
779: for (secondary_reload = 0; secondary_reload < n_reloads;
780: secondary_reload++)
781: if (reload_secondary_p[secondary_reload]
782: && (reg_class_subset_p (secondary_class,
783: reload_reg_class[secondary_reload])
784: || reg_class_subset_p (reload_reg_class[secondary_reload],
785: secondary_class))
786: && ((reload_inmode[secondary_reload] == secondary_mode)
787: || reload_inmode[secondary_reload] == VOIDmode)
788: && ((reload_outmode[secondary_reload] == secondary_out_mode)
789: || reload_outmode[secondary_reload] == VOIDmode)
790: && reload_secondary_reload[secondary_reload] == tertiary_reload
791: && reload_secondary_icode[secondary_reload] == tertiary_icode)
792: {
793: if (secondary_mode != VOIDmode)
794: reload_inmode[secondary_reload] = secondary_mode;
795: if (secondary_out_mode != VOIDmode)
796: reload_outmode[secondary_reload] = secondary_out_mode;
797: if (reg_class_subset_p (secondary_class,
798: reload_reg_class[secondary_reload]))
799: reload_reg_class[secondary_reload] = secondary_class;
800: if (reload_needed_for[secondary_reload] != needed_for)
801: reload_needed_for_multiple[secondary_reload] = 1;
802: reload_optional[secondary_reload] &= optional;
803: reload_secondary_p[secondary_reload] = 1;
804: }
805:
806: if (secondary_reload == n_reloads)
807: {
808: /* We need to make a new secondary reload for this register
809: class. */
810: reload_in[secondary_reload] = reload_out[secondary_reload] = 0;
811: reload_reg_class[secondary_reload] = secondary_class;
812: reload_inmode[secondary_reload] = secondary_mode;
813: reload_outmode[secondary_reload] = secondary_out_mode;
814: reload_reg_rtx[secondary_reload] = 0;
815: reload_optional[secondary_reload] = optional;
816: reload_inc[secondary_reload] = 0;
817: reload_strict_low[secondary_reload] = 0;
818: /* Maybe we could combine these, but it seems too tricky. */
819: reload_nocombine[secondary_reload] = 1;
820: reload_in_reg[secondary_reload] = 0;
821: reload_needed_for[secondary_reload] = needed_for;
822: reload_needed_for_multiple[secondary_reload] = 0;
823: reload_secondary_reload[secondary_reload] = tertiary_reload;
824: reload_secondary_icode[secondary_reload] = tertiary_icode;
825: reload_secondary_p[secondary_reload] = 1;
826:
827: n_reloads++;
828: i = n_reloads;
829: }
830: }
831: #endif
832:
833: /* We found no existing reload suitable for re-use.
834: So add an additional reload. */
835:
836: reload_in[i] = in;
837: reload_out[i] = out;
838: reload_reg_class[i] = class;
839: reload_inmode[i] = inmode;
840: reload_outmode[i] = outmode;
841: reload_reg_rtx[i] = 0;
842: reload_optional[i] = optional;
843: reload_inc[i] = 0;
844: reload_strict_low[i] = strict_low;
845: reload_nocombine[i] = 0;
846: reload_in_reg[i] = inloc ? *inloc : 0;
847: reload_needed_for[i] = needed_for;
848: reload_needed_for_multiple[i] = 0;
849: reload_secondary_reload[i] = secondary_reload;
850: reload_secondary_icode[i] = secondary_icode;
851: reload_secondary_p[i] = 0;
852:
853: n_reloads++;
854: }
855: else
856: {
857: /* We are reusing an existing reload,
858: but we may have additional information for it.
859: For example, we may now have both IN and OUT
860: while the old one may have just one of them. */
861:
862: if (inmode != VOIDmode)
863: reload_inmode[i] = inmode;
864: if (outmode != VOIDmode)
865: reload_outmode[i] = outmode;
866: if (in != 0)
867: reload_in[i] = in;
868: if (out != 0)
869: reload_out[i] = out;
870: if (reg_class_subset_p (class, reload_reg_class[i]))
871: reload_reg_class[i] = class;
872: reload_optional[i] &= optional;
873: if (reload_needed_for[i] != needed_for)
874: reload_needed_for_multiple[i] = 1;
875: }
876:
877: /* If the ostensible rtx being reload differs from the rtx found
878: in the location to substitute, this reload is not safe to combine
879: because we cannot reliably tell whether it appears in the insn. */
880:
881: if (in != 0 && in != *inloc)
882: reload_nocombine[i] = 1;
883:
884: #if 0
885: /* This was replaced by changes in find_reloads_address_1 and the new
886: function inc_for_reload, which go with a new meaning of reload_inc. */
887:
888: /* If this is an IN/OUT reload in an insn that sets the CC,
889: it must be for an autoincrement. It doesn't work to store
890: the incremented value after the insn because that would clobber the CC.
891: So we must do the increment of the value reloaded from,
892: increment it, store it back, then decrement again. */
893: if (out != 0 && sets_cc0_p (PATTERN (this_insn)))
894: {
895: out = 0;
896: reload_out[i] = 0;
897: reload_inc[i] = find_inc_amount (PATTERN (this_insn), in);
898: /* If we did not find a nonzero amount-to-increment-by,
899: that contradicts the belief that IN is being incremented
900: in an address in this insn. */
901: if (reload_inc[i] == 0)
902: abort ();
903: }
904: #endif
905:
906: /* If we will replace IN and OUT with the reload-reg,
907: record where they are located so that substitution need
908: not do a tree walk. */
909:
910: if (replace_reloads)
911: {
912: if (inloc != 0)
913: {
914: register struct replacement *r = &replacements[n_replacements++];
915: r->what = i;
916: r->subreg_loc = in_subreg_loc;
917: r->where = inloc;
918: r->mode = inmode;
919: }
920: if (outloc != 0 && outloc != inloc)
921: {
922: register struct replacement *r = &replacements[n_replacements++];
923: r->what = i;
924: r->where = outloc;
925: r->subreg_loc = out_subreg_loc;
926: r->mode = outmode;
927: }
928: }
929:
930: /* If this reload is just being introduced and it has both
931: an incoming quantity and an outgoing quantity that are
932: supposed to be made to match, see if either one of the two
933: can serve as the place to reload into.
934:
935: If one of them is acceptable, set reload_reg_rtx[i]
936: to that one. */
937:
938: if (in != 0 && out != 0 && in != out && reload_reg_rtx[i] == 0)
939: {
940: reload_reg_rtx[i] = find_dummy_reload (in, out, inloc, outloc,
941: reload_reg_class[i], i);
942:
943: /* If the outgoing register already contains the same value
944: as the incoming one, we can dispense with loading it.
945: The easiest way to tell the caller that is to give a phony
946: value for the incoming operand (same as outgoing one). */
947: if (reload_reg_rtx[i] == out
948: && (GET_CODE (in) == REG || CONSTANT_P (in))
949: && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out),
950: static_reload_reg_p, i, inmode))
951: reload_in[i] = out;
952: }
953:
954: /* If this is an input reload and the operand contains a register that
955: dies in this insn and is used nowhere else, see if it is the right class
956: to be used for this reload. Use it if so. (This occurs most commonly
957: in the case of paradoxical SUBREGs and in-out reloads). We cannot do
958: this if it is also an output reload that mentions the register unless
959: the output is a SUBREG that clobbers an entire register.
960:
961: Note that the operand might be one of the spill regs, if it is a
962: pseudo reg and we are in a block where spilling has not taken place.
963: But if there is no spilling in this block, that is OK.
964: An explicitly used hard reg cannot be a spill reg. */
965:
966: if (reload_reg_rtx[i] == 0 && in != 0)
967: {
968: rtx note;
969: int regno;
970:
971: for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
972: if (REG_NOTE_KIND (note) == REG_DEAD
973: && GET_CODE (XEXP (note, 0)) == REG
974: && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER
975: && reg_mentioned_p (XEXP (note, 0), in)
976: && ! refers_to_regno_for_reload_p (regno,
977: (regno
978: + HARD_REGNO_NREGS (regno,
979: inmode)),
980: PATTERN (this_insn), inloc)
981: && (in != out
982: || (GET_CODE (in) == SUBREG
983: && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1))
984: / UNITS_PER_WORD)
985: == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
986: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
987: /* Make sure the operand fits in the reg that dies. */
988: && GET_MODE_SIZE (inmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
989: && HARD_REGNO_MODE_OK (regno, inmode)
990: && GET_MODE_SIZE (outmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
991: && HARD_REGNO_MODE_OK (regno, outmode)
992: && TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
993: && !fixed_regs[regno])
994: {
995: reload_reg_rtx[i] = gen_rtx (REG, inmode, regno);
996: break;
997: }
998: }
999:
1000: if (out)
1001: output_reloadnum = i;
1002:
1003: return i;
1004: }
1005:
1006: /* Record an additional place we must replace a value
1007: for which we have already recorded a reload.
1008: RELOADNUM is the value returned by push_reload
1009: when the reload was recorded.
1010: This is used in insn patterns that use match_dup. */
1011:
1012: static void
1013: push_replacement (loc, reloadnum, mode)
1014: rtx *loc;
1015: int reloadnum;
1016: enum machine_mode mode;
1017: {
1018: if (replace_reloads)
1019: {
1020: register struct replacement *r = &replacements[n_replacements++];
1021: r->what = reloadnum;
1022: r->where = loc;
1023: r->subreg_loc = 0;
1024: r->mode = mode;
1025: }
1026: }
1027:
1028: /* If there is only one output reload, and it is not for an earlyclobber
1029: operand, try to combine it with a (logically unrelated) input reload
1030: to reduce the number of reload registers needed.
1031:
1032: This is safe if the input reload does not appear in
1033: the value being output-reloaded, because this implies
1034: it is not needed any more once the original insn completes.
1035:
1036: If that doesn't work, see we can use any of the registers that
1037: die in this insn as a reload register. We can if it is of the right
1038: class and does not appear in the value being output-reloaded. */
1039:
1040: static void
1041: combine_reloads ()
1042: {
1043: int i;
1044: int output_reload = -1;
1045: rtx note;
1046:
1047: /* Find the output reload; return unless there is exactly one
1048: and that one is mandatory. */
1049:
1050: for (i = 0; i < n_reloads; i++)
1051: if (reload_out[i] != 0)
1052: {
1053: if (output_reload >= 0)
1054: return;
1055: output_reload = i;
1056: }
1057:
1058: if (output_reload < 0 || reload_optional[output_reload])
1059: return;
1060:
1061: /* An input-output reload isn't combinable. */
1062:
1063: if (reload_in[output_reload] != 0)
1064: return;
1065:
1066: /* If this reload is for an earlyclobber operand, we can't do anyting. */
1067:
1068: for (i = 0; i < n_earlyclobbers; i++)
1069: if (reload_out[output_reload] == reload_earlyclobbers[i])
1070: return;
1071:
1072: /* Check each input reload; can we combine it? */
1073:
1074: for (i = 0; i < n_reloads; i++)
1075: if (reload_in[i] && ! reload_optional[i] && ! reload_nocombine[i]
1076: /* Life span of this reload must not extend past main insn. */
1077: && reload_when_needed[i] != RELOAD_FOR_OUTPUT_RELOAD_ADDRESS
1078: && reload_inmode[i] == reload_outmode[output_reload]
1079: && reload_inc[i] == 0
1080: && reload_reg_rtx[i] == 0
1081: && reload_strict_low[i] == 0
1082: /* Don't combine two reloads with different secondary reloads. */
1083: && (reload_secondary_reload[i] == reload_secondary_reload[output_reload]
1084: || reload_secondary_reload[i] == -1
1085: || reload_secondary_reload[output_reload] == -1)
1086: && (reg_class_subset_p (reload_reg_class[i],
1087: reload_reg_class[output_reload])
1088: || reg_class_subset_p (reload_reg_class[output_reload],
1089: reload_reg_class[i]))
1090: && (MATCHES (reload_in[i], reload_out[output_reload])
1091: /* Args reversed because the first arg seems to be
1092: the one that we imagine being modified
1093: while the second is the one that might be affected. */
1094: || (! reg_overlap_mentioned_p (reload_out[output_reload],
1095: reload_in[i])
1096: /* However, if the input is a register that appears inside
1097: the output, then we also can't share.
1098: Imagine (set (mem (reg 69)) (plus (reg 69) ...)).
1099: If the same reload reg is used for both reg 69 and the
1100: result to be stored in memory, then that result
1101: will clobber the address of the memory ref. */
1102: && ! (GET_CODE (reload_in[i]) == REG
1103: && reg_overlap_mentioned_p (reload_in[i],
1104: reload_out[output_reload])))))
1105: {
1106: int j;
1107:
1108: /* We have found a reload to combine with! */
1109: reload_out[i] = reload_out[output_reload];
1110: reload_outmode[i] = reload_outmode[output_reload];
1111: /* Mark the old output reload as inoperative. */
1112: reload_out[output_reload] = 0;
1113: /* The combined reload is needed for the entire insn. */
1114: reload_needed_for_multiple[i] = 1;
1115: reload_when_needed[i] = RELOAD_OTHER;
1116: /* If the output reload had a secondary reload, copy it. */
1117: if (reload_secondary_reload[output_reload] != -1)
1118: reload_secondary_reload[i] = reload_secondary_reload[output_reload];
1119: /* If required, minimize the register class. */
1120: if (reg_class_subset_p (reload_reg_class[output_reload],
1121: reload_reg_class[i]))
1122: reload_reg_class[i] = reload_reg_class[output_reload];
1123:
1124: /* Transfer all replacements from the old reload to the combined. */
1125: for (j = 0; j < n_replacements; j++)
1126: if (replacements[j].what == output_reload)
1127: replacements[j].what = i;
1128:
1129: return;
1130: }
1131:
1132: /* If this insn has only one operand that is modified or written (assumed
1133: to be the first), it must be the one corresponding to this reload. It
1134: is safe to use anything that dies in this insn for that output provided
1135: that it does not occur in the output (we already know it isn't an
1136: earlyclobber. If this is an asm insn, give up. */
1137:
1138: if (INSN_CODE (this_insn) == -1)
1139: return;
1140:
1141: for (i = 1; i < insn_n_operands[INSN_CODE (this_insn)]; i++)
1142: if (insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '='
1143: || insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '+')
1144: return;
1145:
1146: /* See if some hard register that dies in this insn and is not used in
1147: the output is the right class. Only works if the register we pick
1148: up can fully hold our output reload. */
1149: for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
1150: if (REG_NOTE_KIND (note) == REG_DEAD
1151: && GET_CODE (XEXP (note, 0)) == REG
1152: && ! reg_overlap_mentioned_p (XEXP (note, 0),
1153: reload_out[output_reload])
1154: && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
1155: && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), reload_outmode[output_reload])
1156: && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[output_reload]],
1157: REGNO (XEXP (note, 0)))
1158: && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), reload_outmode[output_reload])
1159: <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0))))
1160: && ! fixed_regs[REGNO (XEXP (note, 0))])
1161: {
1162: reload_reg_rtx[output_reload] = gen_rtx (REG,
1163: reload_outmode[output_reload],
1164: REGNO (XEXP (note, 0)));
1165: return;
1166: }
1167: }
1168:
1169: /* Try to find a reload register for an in-out reload (expressions IN and OUT).
1170: See if one of IN and OUT is a register that may be used;
1171: this is desirable since a spill-register won't be needed.
1172: If so, return the register rtx that proves acceptable.
1173:
1174: INLOC and OUTLOC are locations where IN and OUT appear in the insn.
1175: CLASS is the register class required for the reload.
1176:
1177: If FOR_REAL is >= 0, it is the number of the reload,
1178: and in some cases when it can be discovered that OUT doesn't need
1179: to be computed, clear out reload_out[FOR_REAL].
1180:
1181: If FOR_REAL is -1, this should not be done, because this call
1182: is just to see if a register can be found, not to find and install it. */
1183:
1184: static rtx
1185: find_dummy_reload (real_in, real_out, inloc, outloc, class, for_real)
1186: rtx real_in, real_out;
1187: rtx *inloc, *outloc;
1188: enum reg_class class;
1189: int for_real;
1190: {
1191: rtx in = real_in;
1192: rtx out = real_out;
1193: int in_offset = 0;
1194: int out_offset = 0;
1195: rtx value = 0;
1196:
1197: /* If operands exceed a word, we can't use either of them
1198: unless they have the same size. */
1199: if (GET_MODE_SIZE (GET_MODE (real_out)) != GET_MODE_SIZE (GET_MODE (real_in))
1200: && (GET_MODE_SIZE (GET_MODE (real_out)) > UNITS_PER_WORD
1201: || GET_MODE_SIZE (GET_MODE (real_in)) > UNITS_PER_WORD))
1202: return 0;
1203:
1204: /* Find the inside of any subregs. */
1205: while (GET_CODE (out) == SUBREG)
1206: {
1207: out_offset = SUBREG_WORD (out);
1208: out = SUBREG_REG (out);
1209: }
1210: while (GET_CODE (in) == SUBREG)
1211: {
1212: in_offset = SUBREG_WORD (in);
1213: in = SUBREG_REG (in);
1214: }
1215:
1216: /* Narrow down the reg class, the same way push_reload will;
1217: otherwise we might find a dummy now, but push_reload won't. */
1218: class = PREFERRED_RELOAD_CLASS (in, class);
1219:
1220: /* See if OUT will do. */
1221: if (GET_CODE (out) == REG
1222: && REGNO (out) < FIRST_PSEUDO_REGISTER)
1223: {
1224: register int regno = REGNO (out) + out_offset;
1225: int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_out));
1226:
1227: /* When we consider whether the insn uses OUT,
1228: ignore references within IN. They don't prevent us
1229: from copying IN into OUT, because those refs would
1230: move into the insn that reloads IN.
1231:
1232: However, we only ignore IN in its role as this reload.
1233: If the insn uses IN elsewhere and it contains OUT,
1234: that counts. We can't be sure it's the "same" operand
1235: so it might not go through this reload. */
1236: *inloc = const0_rtx;
1237:
1238: if (regno < FIRST_PSEUDO_REGISTER
1239: /* A fixed reg that can overlap other regs better not be used
1240: for reloading in any way. */
1241: #ifdef OVERLAPPING_REGNO_P
1242: && ! (fixed_regs[regno] && OVERLAPPING_REGNO_P (regno))
1243: #endif
1244: && ! refers_to_regno_for_reload_p (regno, regno + nwords,
1245: PATTERN (this_insn), outloc))
1246: {
1247: int i;
1248: for (i = 0; i < nwords; i++)
1249: if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1250: regno + i))
1251: break;
1252:
1253: if (i == nwords)
1254: {
1255: if (GET_CODE (real_out) == REG)
1256: value = real_out;
1257: else
1258: value = gen_rtx (REG, GET_MODE (real_out), regno);
1259: }
1260: }
1261:
1262: *inloc = real_in;
1263: }
1264:
1265: /* Consider using IN if OUT was not acceptable
1266: or if OUT dies in this insn (like the quotient in a divmod insn).
1267: We can't use IN unless it is dies in this insn,
1268: which means we must know accurately which hard regs are live.
1269: Also, the result can't go in IN if IN is used within OUT. */
1270: if (hard_regs_live_known
1271: && GET_CODE (in) == REG
1272: && REGNO (in) < FIRST_PSEUDO_REGISTER
1273: && (value == 0
1274: || find_reg_note (this_insn, REG_UNUSED, real_out))
1275: && find_reg_note (this_insn, REG_DEAD, real_in)
1276: && !fixed_regs[REGNO (in)]
1277: && HARD_REGNO_MODE_OK (REGNO (in), GET_MODE (out)))
1278: {
1279: register int regno = REGNO (in) + in_offset;
1280: int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_in));
1281:
1282: if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, 0)
1283: && ! hard_reg_set_here_p (regno, regno + nwords,
1284: PATTERN (this_insn)))
1285: {
1286: int i;
1287: for (i = 0; i < nwords; i++)
1288: if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1289: regno + i))
1290: break;
1291:
1292: if (i == nwords)
1293: {
1294: /* If we were going to use OUT as the reload reg
1295: and changed our mind, it means OUT is a dummy that
1296: dies here. So don't bother copying value to it. */
1297: if (for_real >= 0 && value == real_out)
1298: reload_out[for_real] = 0;
1299: if (GET_CODE (real_in) == REG)
1300: value = real_in;
1301: else
1302: value = gen_rtx (REG, GET_MODE (real_in), regno);
1303: }
1304: }
1305: }
1306:
1307: return value;
1308: }
1309:
1310: /* This page contains subroutines used mainly for determining
1311: whether the IN or an OUT of a reload can serve as the
1312: reload register. */
1313:
1314: /* Return 1 if expression X alters a hard reg in the range
1315: from BEG_REGNO (inclusive) to END_REGNO (exclusive),
1316: either explicitly or in the guise of a pseudo-reg allocated to REGNO.
1317: X should be the body of an instruction. */
1318:
1319: static int
1320: hard_reg_set_here_p (beg_regno, end_regno, x)
1321: register int beg_regno, end_regno;
1322: rtx x;
1323: {
1324: if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
1325: {
1326: register rtx op0 = SET_DEST (x);
1327: while (GET_CODE (op0) == SUBREG)
1328: op0 = SUBREG_REG (op0);
1329: if (GET_CODE (op0) == REG)
1330: {
1331: register int r = REGNO (op0);
1332: /* See if this reg overlaps range under consideration. */
1333: if (r < end_regno
1334: && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno)
1335: return 1;
1336: }
1337: }
1338: else if (GET_CODE (x) == PARALLEL)
1339: {
1340: register int i = XVECLEN (x, 0) - 1;
1341: for (; i >= 0; i--)
1342: if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i)))
1343: return 1;
1344: }
1345:
1346: return 0;
1347: }
1348:
1349: /* Return 1 if ADDR is a valid memory address for mode MODE,
1350: and check that each pseudo reg has the proper kind of
1351: hard reg. */
1352:
1353: int
1354: strict_memory_address_p (mode, addr)
1355: enum machine_mode mode;
1356: register rtx addr;
1357: {
1358: GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1359: return 0;
1360:
1361: win:
1362: return 1;
1363: }
1364:
1365:
1366: /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
1367: if they are the same hard reg, and has special hacks for
1368: autoincrement and autodecrement.
1369: This is specifically intended for find_reloads to use
1370: in determining whether two operands match.
1371: X is the operand whose number is the lower of the two.
1372:
1373: The value is 2 if Y contains a pre-increment that matches
1374: a non-incrementing address in X. */
1375:
1376: /* ??? To be completely correct, we should arrange to pass
1377: for X the output operand and for Y the input operand.
1378: For now, we assume that the output operand has the lower number
1379: because that is natural in (SET output (... input ...)). */
1380:
1381: int
1382: operands_match_p (x, y)
1383: register rtx x, y;
1384: {
1385: register int i;
1386: register RTX_CODE code = GET_CODE (x);
1387: register char *fmt;
1388: int success_2;
1389:
1390: if (x == y)
1391: return 1;
1392: if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG))
1393: && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG
1394: && GET_CODE (SUBREG_REG (y)) == REG)))
1395: {
1396: register int j;
1397:
1398: if (code == SUBREG)
1399: {
1400: i = REGNO (SUBREG_REG (x));
1401: if (i >= FIRST_PSEUDO_REGISTER)
1402: goto slow;
1403: i += SUBREG_WORD (x);
1404: }
1405: else
1406: i = REGNO (x);
1407:
1408: if (GET_CODE (y) == SUBREG)
1409: {
1410: j = REGNO (SUBREG_REG (y));
1411: if (j >= FIRST_PSEUDO_REGISTER)
1412: goto slow;
1413: j += SUBREG_WORD (y);
1414: }
1415: else
1416: j = REGNO (y);
1417:
1418: return i == j;
1419: }
1420: /* If two operands must match, because they are really a single
1421: operand of an assembler insn, then two postincrements are invalid
1422: because the assembler insn would increment only once.
1423: On the other hand, an postincrement matches ordinary indexing
1424: if the postincrement is the output operand. */
1425: if (code == POST_DEC || code == POST_INC)
1426: return operands_match_p (XEXP (x, 0), y);
1427: /* Two preincrements are invalid
1428: because the assembler insn would increment only once.
1429: On the other hand, an preincrement matches ordinary indexing
1430: if the preincrement is the input operand.
1431: In this case, return 2, since some callers need to do special
1432: things when this happens. */
1433: if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC)
1434: return operands_match_p (x, XEXP (y, 0)) ? 2 : 0;
1435:
1436: slow:
1437:
1438: /* Now we have disposed of all the cases
1439: in which different rtx codes can match. */
1440: if (code != GET_CODE (y))
1441: return 0;
1442: if (code == LABEL_REF)
1443: return XEXP (x, 0) == XEXP (y, 0);
1444: if (code == SYMBOL_REF)
1445: return XSTR (x, 0) == XSTR (y, 0);
1446:
1447: /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
1448:
1449: if (GET_MODE (x) != GET_MODE (y))
1450: return 0;
1451:
1452: /* Compare the elements. If any pair of corresponding elements
1453: fail to match, return 0 for the whole things. */
1454:
1455: success_2 = 0;
1456: fmt = GET_RTX_FORMAT (code);
1457: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1458: {
1459: int val;
1460: switch (fmt[i])
1461: {
1462: case 'i':
1463: if (XINT (x, i) != XINT (y, i))
1464: return 0;
1465: break;
1466:
1467: case 'e':
1468: val = operands_match_p (XEXP (x, i), XEXP (y, i));
1469: if (val == 0)
1470: return 0;
1471: /* If any subexpression returns 2,
1472: we should return 2 if we are successful. */
1473: if (val == 2)
1474: success_2 = 1;
1475: break;
1476:
1477: case '0':
1478: break;
1479:
1480: /* It is believed that rtx's at this level will never
1481: contain anything but integers and other rtx's,
1482: except for within LABEL_REFs and SYMBOL_REFs. */
1483: default:
1484: abort ();
1485: }
1486: }
1487: return 1 + success_2;
1488: }
1489:
1490: /* Return the number of times character C occurs in string S. */
1491:
1492: static int
1493: n_occurrences (c, s)
1494: char c;
1495: char *s;
1496: {
1497: int n = 0;
1498: while (*s)
1499: n += (*s++ == c);
1500: return n;
1501: }
1502:
1503: struct decomposition
1504: {
1505: int reg_flag;
1506: int safe;
1507: rtx base;
1508: int start;
1509: int end;
1510: };
1511:
1512: /* Describe the range of registers or memory referenced by X.
1513: If X is a register, set REG_FLAG and put the first register
1514: number into START and the last plus one into END.
1515: If X is a memory reference, put a base address into BASE
1516: and a range of integer offsets into START and END.
1517: If X is pushing on the stack, we can assume it causes no trouble,
1518: so we set the SAFE field. */
1519:
1520: static struct decomposition
1521: decompose (x)
1522: rtx x;
1523: {
1524: struct decomposition val;
1525: int all_const = 0;
1526:
1527: val.reg_flag = 0;
1528: val.safe = 0;
1529: if (GET_CODE (x) == MEM)
1530: {
1531: rtx base, offset = 0;
1532: rtx addr = XEXP (x, 0);
1533:
1534: if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC
1535: || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC)
1536: {
1537: val.base = XEXP (addr, 0);
1538: val.start = - GET_MODE_SIZE (GET_MODE (x));
1539: val.end = GET_MODE_SIZE (GET_MODE (x));
1540: val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
1541: return val;
1542: }
1543:
1544: if (GET_CODE (addr) == CONST)
1545: {
1546: addr = XEXP (addr, 0);
1547: all_const = 1;
1548: }
1549: if (GET_CODE (addr) == PLUS)
1550: {
1551: if (CONSTANT_P (XEXP (addr, 0)))
1552: {
1553: base = XEXP (addr, 1);
1554: offset = XEXP (addr, 0);
1555: }
1556: else if (CONSTANT_P (XEXP (addr, 1)))
1557: {
1558: base = XEXP (addr, 0);
1559: offset = XEXP (addr, 1);
1560: }
1561: }
1562:
1563: if (offset == 0)
1564: {
1565: base = addr;
1566: offset = const0_rtx;
1567: }
1568: if (GET_CODE (offset) == CONST)
1569: offset = XEXP (offset, 0);
1570: if (GET_CODE (offset) == PLUS)
1571: {
1572: if (GET_CODE (XEXP (offset, 0)) == CONST_INT)
1573: {
1574: base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 1));
1575: offset = XEXP (offset, 0);
1576: }
1577: else if (GET_CODE (XEXP (offset, 1)) == CONST_INT)
1578: {
1579: base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 0));
1580: offset = XEXP (offset, 1);
1581: }
1582: else
1583: {
1584: base = gen_rtx (PLUS, GET_MODE (base), base, offset);
1585: offset = const0_rtx;
1586: }
1587: }
1588: else if (GET_CODE (offset) != CONST_INT)
1589: {
1590: base = gen_rtx (PLUS, GET_MODE (base), base, offset);
1591: offset = const0_rtx;
1592: }
1593:
1594: if (all_const && GET_CODE (base) == PLUS)
1595: base = gen_rtx (CONST, GET_MODE (base), base);
1596:
1597: if (GET_CODE (offset) != CONST_INT)
1598: abort ();
1599:
1600: val.start = INTVAL (offset);
1601: val.end = val.start + GET_MODE_SIZE (GET_MODE (x));
1602: val.base = base;
1603: return val;
1604: }
1605: else if (GET_CODE (x) == REG)
1606: {
1607: val.reg_flag = 1;
1608: val.start = true_regnum (x);
1609: if (val.start < 0)
1610: {
1611: /* A pseudo with no hard reg. */
1612: val.start = REGNO (x);
1613: val.end = val.start + 1;
1614: }
1615: else
1616: /* A hard reg. */
1617: val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x));
1618: }
1619: else if (GET_CODE (x) == SUBREG)
1620: {
1621: if (GET_CODE (SUBREG_REG (x)) != REG)
1622: /* This could be more precise, but it's good enough. */
1623: return decompose (SUBREG_REG (x));
1624: val.reg_flag = 1;
1625: val.start = true_regnum (x);
1626: if (val.start < 0)
1627: return decompose (SUBREG_REG (x));
1628: else
1629: /* A hard reg. */
1630: val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x));
1631: }
1632: else if (CONSTANT_P (x)
1633: /* This hasn't been assigned yet, so it can't conflict yet. */
1634: || GET_CODE (x) == SCRATCH)
1635: val.safe = 1;
1636: else
1637: abort ();
1638: return val;
1639: }
1640:
1641: /* Return 1 if altering Y will not modify the value of X.
1642: Y is also described by YDATA, which should be decompose (Y). */
1643:
1644: static int
1645: immune_p (x, y, ydata)
1646: rtx x, y;
1647: struct decomposition ydata;
1648: {
1649: struct decomposition xdata;
1650:
1651: if (ydata.reg_flag)
1652: return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, 0);
1653: if (ydata.safe)
1654: return 1;
1655:
1656: if (GET_CODE (y) != MEM)
1657: abort ();
1658: /* If Y is memory and X is not, Y can't affect X. */
1659: if (GET_CODE (x) != MEM)
1660: return 1;
1661:
1662: xdata = decompose (x);
1663:
1664: if (! rtx_equal_p (xdata.base, ydata.base))
1665: {
1666: /* If bases are distinct symbolic constants, there is no overlap. */
1667: if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base))
1668: return 1;
1669: /* Constants and stack slots never overlap. */
1670: if (CONSTANT_P (xdata.base)
1671: && (ydata.base == frame_pointer_rtx
1672: || ydata.base == stack_pointer_rtx))
1673: return 1;
1674: if (CONSTANT_P (ydata.base)
1675: && (xdata.base == frame_pointer_rtx
1676: || xdata.base == stack_pointer_rtx))
1677: return 1;
1678: /* If either base is variable, we don't know anything. */
1679: return 0;
1680: }
1681:
1682:
1683: return (xdata.start >= ydata.end || ydata.start >= xdata.end);
1684: }
1685:
1686: /* Main entry point of this file: search the body of INSN
1687: for values that need reloading and record them with push_reload.
1688: REPLACE nonzero means record also where the values occur
1689: so that subst_reloads can be used.
1690:
1691: IND_LEVELS says how many levels of indirection are supported by this
1692: machine; a value of zero means that a memory reference is not a valid
1693: memory address.
1694:
1695: LIVE_KNOWN says we have valid information about which hard
1696: regs are live at each point in the program; this is true when
1697: we are called from global_alloc but false when stupid register
1698: allocation has been done.
1699:
1700: RELOAD_REG_P if nonzero is a vector indexed by hard reg number
1701: which is nonnegative if the reg has been commandeered for reloading into.
1702: It is copied into STATIC_RELOAD_REG_P and referenced from there
1703: by various subroutines. */
1704:
1705: void
1706: find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
1707: rtx insn;
1708: int replace, ind_levels;
1709: int live_known;
1710: short *reload_reg_p;
1711: {
1712: rtx non_reloaded_operands[MAX_RECOG_OPERANDS];
1713: int n_non_reloaded_operands = 0;
1714: #ifdef REGISTER_CONSTRAINTS
1715:
1716: enum reload_modified { RELOAD_NOTHING, RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE };
1717:
1718: register int insn_code_number;
1719: register int i;
1720: int noperands;
1721: /* These are the constraints for the insn. We don't change them. */
1722: char *constraints1[MAX_RECOG_OPERANDS];
1723: /* These start out as the constraints for the insn
1724: and they are chewed up as we consider alternatives. */
1725: char *constraints[MAX_RECOG_OPERANDS];
1726: /* These are the preferred classes for an operand, or NO_REGS if it isn't
1727: a register. */
1728: enum reg_class preferred_class[MAX_RECOG_OPERANDS];
1729: char pref_or_nothing[MAX_RECOG_OPERANDS];
1730: /* Nonzero for a MEM operand whose entire address needs a reload. */
1731: int address_reloaded[MAX_RECOG_OPERANDS];
1732: int no_input_reloads = 0, no_output_reloads = 0;
1733: int n_alternatives;
1734: int this_alternative[MAX_RECOG_OPERANDS];
1735: char this_alternative_win[MAX_RECOG_OPERANDS];
1736: char this_alternative_offmemok[MAX_RECOG_OPERANDS];
1737: char this_alternative_earlyclobber[MAX_RECOG_OPERANDS];
1738: int this_alternative_matches[MAX_RECOG_OPERANDS];
1739: int swapped;
1740: int goal_alternative[MAX_RECOG_OPERANDS];
1741: int this_alternative_number;
1742: int goal_alternative_number;
1743: int operand_reloadnum[MAX_RECOG_OPERANDS];
1744: int goal_alternative_matches[MAX_RECOG_OPERANDS];
1745: int goal_alternative_matched[MAX_RECOG_OPERANDS];
1746: char goal_alternative_win[MAX_RECOG_OPERANDS];
1747: char goal_alternative_offmemok[MAX_RECOG_OPERANDS];
1748: char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS];
1749: int goal_alternative_swapped;
1750: enum reload_modified modified[MAX_RECOG_OPERANDS];
1751: int best;
1752: int commutative;
1753: char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
1754: rtx substed_operand[MAX_RECOG_OPERANDS];
1755: rtx body = PATTERN (insn);
1756: rtx set = single_set (insn);
1757: int goal_earlyclobber, this_earlyclobber;
1758: enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1759:
1760: this_insn = insn;
1761: this_insn_is_asm = 0; /* Tentative. */
1762: n_reloads = 0;
1763: n_replacements = 0;
1764: n_memlocs = 0;
1765: n_earlyclobbers = 0;
1766: replace_reloads = replace;
1767: hard_regs_live_known = live_known;
1768: static_reload_reg_p = reload_reg_p;
1769:
1770: /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads;
1771: neither are insns that SET cc0. Insns that use CC0 are not allowed
1772: to have any input reloads. */
1773: if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN)
1774: no_output_reloads = 1;
1775:
1776: #ifdef HAVE_cc0
1777: if (reg_referenced_p (cc0_rtx, PATTERN (insn)))
1778: no_input_reloads = 1;
1779: if (reg_set_p (cc0_rtx, PATTERN (insn)))
1780: no_output_reloads = 1;
1781: #endif
1782:
1783: /* Find what kind of insn this is. NOPERANDS gets number of operands.
1784: Make OPERANDS point to a vector of operand values.
1785: Make OPERAND_LOCS point to a vector of pointers to
1786: where the operands were found.
1787: Fill CONSTRAINTS and CONSTRAINTS1 with pointers to the
1788: constraint-strings for this insn.
1789: Return if the insn needs no reload processing. */
1790:
1791: switch (GET_CODE (body))
1792: {
1793: case USE:
1794: case CLOBBER:
1795: case ASM_INPUT:
1796: case ADDR_VEC:
1797: case ADDR_DIFF_VEC:
1798: return;
1799:
1800: case SET:
1801: /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it
1802: is cheap to move between them. If it is not, there may not be an insn
1803: to do the copy, so we may need a reload. */
1804: if (GET_CODE (SET_DEST (body)) == REG
1805: && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER
1806: && GET_CODE (SET_SRC (body)) == REG
1807: && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER
1808: && REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (SET_SRC (body))),
1809: REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2)
1810: return;
1811: case PARALLEL:
1812: case ASM_OPERANDS:
1813: noperands = asm_noperands (body);
1814: if (noperands >= 0)
1815: {
1816: /* This insn is an `asm' with operands. */
1817:
1818: insn_code_number = -1;
1819: this_insn_is_asm = 1;
1820:
1821: /* expand_asm_operands makes sure there aren't too many operands. */
1822: if (noperands > MAX_RECOG_OPERANDS)
1823: abort ();
1824:
1825: /* Now get the operand values and constraints out of the insn. */
1826:
1827: decode_asm_operands (body, recog_operand, recog_operand_loc,
1828: constraints, operand_mode);
1829: if (noperands > 0)
1830: {
1831: bcopy (constraints, constraints1, noperands * sizeof (char *));
1832: n_alternatives = n_occurrences (',', constraints[0]) + 1;
1833: for (i = 1; i < noperands; i++)
1834: if (n_alternatives != n_occurrences (',', constraints[0]) + 1)
1835: {
1836: error_for_asm (insn, "operand constraints differ in number of alternatives");
1837: /* Avoid further trouble with this insn. */
1838: PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
1839: n_reloads = 0;
1840: return;
1841: }
1842: }
1843: break;
1844: }
1845:
1846: default:
1847: /* Ordinary insn: recognize it, get the operands via insn_extract
1848: and get the constraints. */
1849:
1850: insn_code_number = recog_memoized (insn);
1851: if (insn_code_number < 0)
1852: fatal_insn_not_found (insn);
1853:
1854: noperands = insn_n_operands[insn_code_number];
1855: n_alternatives = insn_n_alternatives[insn_code_number];
1856: /* Just return "no reloads" if insn has no operands with constraints. */
1857: if (n_alternatives == 0)
1858: return;
1859: insn_extract (insn);
1860: for (i = 0; i < noperands; i++)
1861: {
1862: constraints[i] = constraints1[i]
1863: = insn_operand_constraint[insn_code_number][i];
1864: operand_mode[i] = insn_operand_mode[insn_code_number][i];
1865: }
1866: }
1867:
1868: if (noperands == 0)
1869: return;
1870:
1871: commutative = -1;
1872:
1873: /* If we will need to know, later, whether some pair of operands
1874: are the same, we must compare them now and save the result.
1875: Reloading the base and index registers will clobber them
1876: and afterward they will fail to match. */
1877:
1878: for (i = 0; i < noperands; i++)
1879: {
1880: register char *p;
1881: register int c;
1882:
1883: substed_operand[i] = recog_operand[i];
1884: p = constraints[i];
1885:
1886: /* Scan this operand's constraint to see if it should match another. */
1887:
1888: while (c = *p++)
1889: if (c == '%')
1890: {
1891: /* The last operand should not be marked commutative. This
1892: problem is hard to detect, so make it obvious by calling
1893: abort here. */
1894: if (i == noperands - 1)
1895: abort ();
1896:
1897: commutative = i;
1898: }
1899: else if (c >= '0' && c <= '9')
1900: {
1901: c -= '0';
1902: operands_match[c][i]
1903: = operands_match_p (recog_operand[c], recog_operand[i]);
1904: /* If C can be commuted with C+1, and C might need to match I,
1905: then C+1 might also need to match I. */
1906: if (commutative >= 0)
1907: {
1908: if (c == commutative || c == commutative + 1)
1909: {
1910: int other = c + (c == commutative ? 1 : -1);
1911: operands_match[other][i]
1912: = operands_match_p (recog_operand[other], recog_operand[i]);
1913: }
1914: if (i == commutative || i == commutative + 1)
1915: {
1916: int other = i + (i == commutative ? 1 : -1);
1917: operands_match[c][other]
1918: = operands_match_p (recog_operand[c], recog_operand[other]);
1919: }
1920: /* Note that C is supposed to be less than I.
1921: No need to consider altering both C and I
1922: because in that case we would alter one into the other. */
1923: }
1924: }
1925: }
1926:
1927: /* Examine each operand that is a memory reference or memory address
1928: and reload parts of the addresses into index registers.
1929: While we are at it, initialize the array `modified'.
1930: Also here any references to pseudo regs that didn't get hard regs
1931: but are equivalent to constants get replaced in the insn itself
1932: with those constants. Nobody will ever see them again.
1933:
1934: Finally, set up the preferred classes of each operand. */
1935:
1936: for (i = 0; i < noperands; i++)
1937: {
1938: register RTX_CODE code = GET_CODE (recog_operand[i]);
1939: modified[i] = RELOAD_READ;
1940: address_reloaded[i] = 0;
1941: preferred_class[i]
1942: = ((code == REG && REGNO (recog_operand[i]) > FIRST_PSEUDO_REGISTER)
1943: ? reg_preferred_class (REGNO (recog_operand[i])) : NO_REGS);
1944: pref_or_nothing[i]
1945: = (code == REG && REGNO (recog_operand[i]) > FIRST_PSEUDO_REGISTER
1946: && reg_preferred_or_nothing (REGNO (recog_operand[i])));
1947:
1948: if (constraints[i][0] == 'p')
1949: {
1950: find_reloads_address (VOIDmode, 0,
1951: recog_operand[i], recog_operand_loc[i],
1952: recog_operand[i], ind_levels);
1953: substed_operand[i] = recog_operand[i] = *recog_operand_loc[i];
1954: }
1955: else if (code == MEM)
1956: {
1957: if (find_reloads_address (GET_MODE (recog_operand[i]),
1958: recog_operand_loc[i],
1959: XEXP (recog_operand[i], 0),
1960: &XEXP (recog_operand[i], 0),
1961: recog_operand[i], ind_levels))
1962: address_reloaded[i] = 1;
1963: substed_operand[i] = recog_operand[i] = *recog_operand_loc[i];
1964: }
1965: else if (code == SUBREG)
1966: substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]
1967: = find_reloads_toplev (recog_operand[i], ind_levels,
1968: set != 0
1969: && &SET_DEST (set) == recog_operand_loc[i]);
1970: else if (code == REG)
1971: {
1972: /* This is equivalent to calling find_reloads_toplev.
1973: The code is duplicated for speed.
1974: When we find a pseudo always equivalent to a constant,
1975: we replace it by the constant. We must be sure, however,
1976: that we don't try to replace it in the insn in which it
1977: is being set. */
1978: register int regno = REGNO (recog_operand[i]);
1979: if (reg_equiv_constant[regno] != 0
1980: && (set == 0 || &SET_DEST (set) != recog_operand_loc[i]))
1981: substed_operand[i] = recog_operand[i]
1982: = reg_equiv_constant[regno];
1983: #if 0 /* This might screw code in reload1.c to delete prior output-reload
1984: that feeds this insn. */
1985: if (reg_equiv_mem[regno] != 0)
1986: substed_operand[i] = recog_operand[i]
1987: = reg_equiv_mem[regno];
1988: #endif
1989: if (reg_equiv_address[regno] != 0)
1990: {
1991: /* If reg_equiv_address is not a constant address, copy it,
1992: since it may be shared. */
1993: rtx address = reg_equiv_address[regno];
1994:
1995: if (rtx_varies_p (address))
1996: address = copy_rtx (address);
1997:
1998: /* If this is an output operand, we must output a CLOBBER
1999: after INSN so find_equiv_reg knows REGNO is being written. */
2000: if (constraints[i][0] == '='
2001: || constraints[i][0] == '+')
2002: emit_insn_after (gen_rtx (CLOBBER, VOIDmode, recog_operand[i]),
2003: insn);
2004:
2005: *recog_operand_loc[i] = recog_operand[i]
2006: = gen_rtx (MEM, GET_MODE (recog_operand[i]), address);
2007: RTX_UNCHANGING_P (recog_operand[i])
2008: = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
2009: find_reloads_address (GET_MODE (recog_operand[i]),
2010: recog_operand_loc[i],
2011: XEXP (recog_operand[i], 0),
2012: &XEXP (recog_operand[i], 0),
2013: recog_operand[i], ind_levels);
2014: substed_operand[i] = recog_operand[i] = *recog_operand_loc[i];
2015: }
2016: }
2017: }
2018:
2019: /* If this is simply a copy from operand 1 to operand 0, merge the
2020: preferred classes for the operands. */
2021: if (set != 0 && noperands >= 2 && recog_operand[0] == SET_DEST (set)
2022: && recog_operand[1] == SET_SRC (set))
2023: {
2024: preferred_class[0] = preferred_class[1]
2025: = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]];
2026: pref_or_nothing[0] |= pref_or_nothing[1];
2027: pref_or_nothing[1] |= pref_or_nothing[0];
2028: }
2029:
2030: /* Now see what we need for pseudo-regs that didn't get hard regs
2031: or got the wrong kind of hard reg. For this, we must consider
2032: all the operands together against the register constraints. */
2033:
2034: best = MAX_RECOG_OPERANDS + 300;
2035:
2036: swapped = 0;
2037: goal_alternative_swapped = 0;
2038: try_swapped:
2039:
2040: /* The constraints are made of several alternatives.
2041: Each operand's constraint looks like foo,bar,... with commas
2042: separating the alternatives. The first alternatives for all
2043: operands go together, the second alternatives go together, etc.
2044:
2045: First loop over alternatives. */
2046:
2047: for (this_alternative_number = 0;
2048: this_alternative_number < n_alternatives;
2049: this_alternative_number++)
2050: {
2051: /* Loop over operands for one constraint alternative. */
2052: /* LOSERS counts those that don't fit this alternative
2053: and would require loading. */
2054: int losers = 0;
2055: /* BAD is set to 1 if it some operand can't fit this alternative
2056: even after reloading. */
2057: int bad = 0;
2058: /* REJECT is a count of how undesirable this alternative says it is
2059: if any reloading is required. If the alternative matches exactly
2060: then REJECT is ignored, but otherwise it gets this much
2061: counted against it in addition to the reloading needed. Each
2062: ? counts three times here since we want the disparaging caused by
2063: a bad register class to only count 1/3 as much. */
2064: int reject = 0;
2065:
2066: this_earlyclobber = 0;
2067:
2068: for (i = 0; i < noperands; i++)
2069: {
2070: register char *p = constraints[i];
2071: register int win = 0;
2072: /* 0 => this operand can be reloaded somehow for this alternative */
2073: int badop = 1;
2074: /* 0 => this operand can be reloaded if the alternative allows regs. */
2075: int winreg = 0;
2076: int c;
2077: register rtx operand = recog_operand[i];
2078: int offset = 0;
2079: /* Nonzero means this is a MEM that must be reloaded into a reg
2080: regardless of what the constraint says. */
2081: int force_reload = 0;
2082: int offmemok = 0;
2083: int earlyclobber = 0;
2084:
2085: /* If the operand is a SUBREG, extract
2086: the REG or MEM (or maybe even a constant) within.
2087: (Constants can occur as a result of reg_equiv_constant.) */
2088:
2089: while (GET_CODE (operand) == SUBREG)
2090: {
2091: offset += SUBREG_WORD (operand);
2092: operand = SUBREG_REG (operand);
2093: /* Force reload if this is not a register or if there may may
2094: be a problem accessing the register in the outer mode. */
2095: if (GET_CODE (operand) != REG
2096: #ifdef BYTE_LOADS_ZERO_EXTEND
2097: /* Nonparadoxical subreg of a pseudoreg.
2098: Don't to load the full width if on this machine
2099: we expected the fetch to zero-extend. */
2100: || ((GET_MODE_SIZE (operand_mode[i])
2101: > GET_MODE_SIZE (GET_MODE (operand)))
2102: && REGNO (operand) >= FIRST_PSEUDO_REGISTER)
2103: #endif /* BYTE_LOADS_ZERO_EXTEND */
2104: /* Subreg of a hard reg which can't handle the subreg's mode
2105: or which would handle that mode in the wrong number of
2106: registers for subregging to work. */
2107: || (REGNO (operand) < FIRST_PSEUDO_REGISTER
2108: && (! HARD_REGNO_MODE_OK (REGNO (operand),
2109: operand_mode[i])
2110: || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD
2111: && (GET_MODE_SIZE (GET_MODE (operand))
2112: > UNITS_PER_WORD)
2113: && ((GET_MODE_SIZE (GET_MODE (operand))
2114: / UNITS_PER_WORD)
2115: != HARD_REGNO_NREGS (REGNO (operand),
2116: GET_MODE (operand)))))))
2117: force_reload = 1;
2118: }
2119:
2120: this_alternative[i] = (int) NO_REGS;
2121: this_alternative_win[i] = 0;
2122: this_alternative_offmemok[i] = 0;
2123: this_alternative_earlyclobber[i] = 0;
2124: this_alternative_matches[i] = -1;
2125:
2126: /* An empty constraint or empty alternative
2127: allows anything which matched the pattern. */
2128: if (*p == 0 || *p == ',')
2129: win = 1, badop = 0;
2130:
2131: /* Scan this alternative's specs for this operand;
2132: set WIN if the operand fits any letter in this alternative.
2133: Otherwise, clear BADOP if this operand could
2134: fit some letter after reloads,
2135: or set WINREG if this operand could fit after reloads
2136: provided the constraint allows some registers. */
2137:
2138: while (*p && (c = *p++) != ',')
2139: switch (c)
2140: {
2141: case '=':
2142: modified[i] = RELOAD_WRITE;
2143: break;
2144:
2145: case '+':
2146: modified[i] = RELOAD_READ_WRITE;
2147: break;
2148:
2149: case '*':
2150: break;
2151:
2152: case '%':
2153: commutative = i;
2154: break;
2155:
2156: case '?':
2157: reject += 3;
2158: break;
2159:
2160: case '!':
2161: reject = 300;
2162: break;
2163:
2164: case '#':
2165: /* Ignore rest of this alternative as far as
2166: reloading is concerned. */
2167: while (*p && *p != ',') p++;
2168: break;
2169:
2170: case '0':
2171: case '1':
2172: case '2':
2173: case '3':
2174: case '4':
2175: c -= '0';
2176: this_alternative_matches[i] = c;
2177: /* We are supposed to match a previous operand.
2178: If we do, we win if that one did.
2179: If we do not, count both of the operands as losers.
2180: (This is too conservative, since most of the time
2181: only a single reload insn will be needed to make
2182: the two operands win. As a result, this alternative
2183: may be rejected when it is actually desirable.) */
2184: if ((swapped && (c != commutative || i != commutative + 1))
2185: /* If we are matching as if two operands were swapped,
2186: also pretend that operands_match had been computed
2187: with swapped.
2188: But if I is the second of those and C is the first,
2189: don't exchange them, because operands_match is valid
2190: only on one side of its diagonal. */
2191: ? (operands_match
2192: [(c == commutative || c == commutative + 1)
2193: ? 2*commutative + 1 - c : c]
2194: [(i == commutative || i == commutative + 1)
2195: ? 2*commutative + 1 - i : i])
2196: : operands_match[c][i])
2197: win = this_alternative_win[c];
2198: else
2199: {
2200: /* Operands don't match. */
2201: rtx value;
2202: /* Retroactively mark the operand we had to match
2203: as a loser, if it wasn't already. */
2204: if (this_alternative_win[c])
2205: losers++;
2206: this_alternative_win[c] = 0;
2207: if (this_alternative[c] == (int) NO_REGS)
2208: bad = 1;
2209: /* But count the pair only once in the total badness of
2210: this alternative, if the pair can be a dummy reload. */
2211: value
2212: = find_dummy_reload (recog_operand[i], recog_operand[c],
2213: recog_operand_loc[i], recog_operand_loc[c],
2214: this_alternative[c], -1);
2215:
2216: if (value != 0)
2217: losers--;
2218: }
2219: /* This can be fixed with reloads if the operand
2220: we are supposed to match can be fixed with reloads. */
2221: badop = 0;
2222: this_alternative[i] = this_alternative[c];
2223: break;
2224:
2225: case 'p':
2226: /* All necessary reloads for an address_operand
2227: were handled in find_reloads_address. */
2228: this_alternative[i] = (int) ALL_REGS;
2229: win = 1;
2230: break;
2231:
2232: case 'm':
2233: if (force_reload)
2234: break;
2235: if (GET_CODE (operand) == MEM
2236: || (GET_CODE (operand) == REG
2237: && REGNO (operand) >= FIRST_PSEUDO_REGISTER
2238: && reg_renumber[REGNO (operand)] < 0))
2239: win = 1;
2240: if (CONSTANT_P (operand))
2241: badop = 0;
2242: break;
2243:
2244: case '<':
2245: if (GET_CODE (operand) == MEM
2246: && ! address_reloaded[i]
2247: && (GET_CODE (XEXP (operand, 0)) == PRE_DEC
2248: || GET_CODE (XEXP (operand, 0)) == POST_DEC))
2249: win = 1;
2250: break;
2251:
2252: case '>':
2253: if (GET_CODE (operand) == MEM
2254: && ! address_reloaded[i]
2255: && (GET_CODE (XEXP (operand, 0)) == PRE_INC
2256: || GET_CODE (XEXP (operand, 0)) == POST_INC))
2257: win = 1;
2258: break;
2259:
2260: /* Memory operand whose address is not offsettable. */
2261: case 'V':
2262: if (force_reload)
2263: break;
2264: if (GET_CODE (operand) == MEM
2265: && ! (ind_levels ? offsettable_memref_p (operand)
2266: : offsettable_nonstrict_memref_p (operand))
2267: /* Certain mem addresses will become offsettable
2268: after they themselves are reloaded. This is important;
2269: we don't want our own handling of unoffsettables
2270: to override the handling of reg_equiv_address. */
2271: && !(GET_CODE (XEXP (operand, 0)) == REG
2272: && (ind_levels == 0
2273: || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)))
2274: win = 1;
2275: break;
2276:
2277: /* Memory operand whose address is offsettable. */
2278: case 'o':
2279: if (force_reload)
2280: break;
2281: if ((GET_CODE (operand) == MEM
2282: /* If IND_LEVELS, find_reloads_address won't reload a
2283: pseudo that didn't get a hard reg, so we have to
2284: reject that case. */
2285: && (ind_levels ? offsettable_memref_p (operand)
2286: : offsettable_nonstrict_memref_p (operand)))
2287: /* Certain mem addresses will become offsettable
2288: after they themselves are reloaded. This is important;
2289: we don't want our own handling of unoffsettables
2290: to override the handling of reg_equiv_address. */
2291: || (GET_CODE (operand) == MEM
2292: && GET_CODE (XEXP (operand, 0)) == REG
2293: && (ind_levels == 0
2294: || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))
2295: || (GET_CODE (operand) == REG
2296: && REGNO (operand) >= FIRST_PSEUDO_REGISTER
2297: && reg_renumber[REGNO (operand)] < 0))
2298: win = 1;
2299: if (CONSTANT_P (operand) || GET_CODE (operand) == MEM)
2300: badop = 0;
2301: offmemok = 1;
2302: break;
2303:
2304: case '&':
2305: /* Output operand that is stored before the need for the
2306: input operands (and their index registers) is over. */
2307: earlyclobber = 1, this_earlyclobber = 1;
2308: break;
2309:
2310: case 'E':
2311: /* Match any floating double constant, but only if
2312: we can examine the bits of it reliably. */
2313: if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2314: || HOST_BITS_PER_INT != BITS_PER_WORD)
2315: && GET_MODE (operand) != VOIDmode && ! flag_pretend_float)
2316: break;
2317: if (GET_CODE (operand) == CONST_DOUBLE)
2318: win = 1;
2319: break;
2320:
2321: case 'F':
2322: if (GET_CODE (operand) == CONST_DOUBLE)
2323: win = 1;
2324: break;
2325:
2326: case 'G':
2327: case 'H':
2328: if (GET_CODE (operand) == CONST_DOUBLE
2329: && CONST_DOUBLE_OK_FOR_LETTER_P (operand, c))
2330: win = 1;
2331: break;
2332:
2333: case 's':
2334: if (GET_CODE (operand) == CONST_INT
2335: || (GET_CODE (operand) == CONST_DOUBLE
2336: && GET_MODE (operand) == VOIDmode))
2337: break;
2338: case 'i':
2339: if (CONSTANT_P (operand)
2340: #ifdef LEGITIMATE_PIC_OPERAND_P
2341: && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand))
2342: #endif
2343: )
2344: win = 1;
2345: break;
2346:
2347: case 'n':
2348: if (GET_CODE (operand) == CONST_INT
2349: || (GET_CODE (operand) == CONST_DOUBLE
2350: && GET_MODE (operand) == VOIDmode))
2351: win = 1;
2352: break;
2353:
2354: case 'I':
2355: case 'J':
2356: case 'K':
2357: case 'L':
2358: case 'M':
2359: case 'N':
2360: case 'O':
2361: case 'P':
2362: if (GET_CODE (operand) == CONST_INT
2363: && CONST_OK_FOR_LETTER_P (INTVAL (operand), c))
2364: win = 1;
2365: break;
2366:
2367: case 'X':
2368: win = 1;
2369: break;
2370:
2371: case 'g':
2372: if (! force_reload
2373: /* A PLUS is never a valid operand, but reload can make
2374: it from a register when eliminating registers. */
2375: && GET_CODE (operand) != PLUS
2376: /* A SCRATCH is not a valid operand. */
2377: && GET_CODE (operand) != SCRATCH
2378: #ifdef LEGITIMATE_PIC_OPERAND_P
2379: && (! CONSTANT_P (operand)
2380: || ! flag_pic
2381: || LEGITIMATE_PIC_OPERAND_P (operand))
2382: #endif
2383: && (GENERAL_REGS == ALL_REGS
2384: || GET_CODE (operand) != REG
2385: || (REGNO (operand) >= FIRST_PSEUDO_REGISTER
2386: && reg_renumber[REGNO (operand)] < 0)))
2387: win = 1;
2388: /* Drop through into 'r' case */
2389:
2390: case 'r':
2391: this_alternative[i]
2392: = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS];
2393: goto reg;
2394:
2395: #ifdef EXTRA_CONSTRAINT
2396: case 'Q':
2397: case 'R':
2398: case 'S':
2399: case 'T':
2400: case 'U':
2401: if (EXTRA_CONSTRAINT (operand, c))
2402: win = 1;
2403: break;
2404: #endif
2405:
2406: default:
2407: this_alternative[i]
2408: = (int) reg_class_subunion[this_alternative[i]][(int) REG_CLASS_FROM_LETTER (c)];
2409:
2410: reg:
2411: if (GET_MODE (operand) == BLKmode)
2412: break;
2413: winreg = 1;
2414: if (GET_CODE (operand) == REG
2415: && reg_fits_class_p (operand, this_alternative[i],
2416: offset, GET_MODE (recog_operand[i])))
2417: win = 1;
2418: break;
2419: }
2420:
2421: constraints[i] = p;
2422:
2423: /* If this operand could be handled with a reg,
2424: and some reg is allowed, then this operand can be handled. */
2425: if (winreg && this_alternative[i] != (int) NO_REGS)
2426: badop = 0;
2427:
2428: /* Record which operands fit this alternative. */
2429: this_alternative_earlyclobber[i] = earlyclobber;
2430: if (win && ! force_reload)
2431: this_alternative_win[i] = 1;
2432: else
2433: {
2434: this_alternative_offmemok[i] = offmemok;
2435: losers++;
2436: if (badop)
2437: bad = 1;
2438: /* Alternative loses if it has no regs for a reg operand. */
2439: if (GET_CODE (operand) == REG
2440: && this_alternative[i] == (int) NO_REGS
2441: && this_alternative_matches[i] < 0)
2442: bad = 1;
2443:
2444: /* Alternative loses if it requires a type of reload not
2445: permitted for this insn. We can always reload SCRATCH
2446: and objects with a REG_UNUSED note. */
2447: if (GET_CODE (operand) != SCRATCH && modified[i] != RELOAD_READ
2448: && no_output_reloads
2449: && ! find_reg_note (insn, REG_UNUSED, operand))
2450: bad = 1;
2451: else if (modified[i] != RELOAD_WRITE && no_input_reloads)
2452: bad = 1;
2453:
2454: /* We prefer to reload pseudos over reloading other things,
2455: since such reloads may be able to be eliminated later.
2456: If we are reloading a SCRATCH, we won't be generating any
2457: insns, just using a register, so it is also preferred.
2458: So bump REJECT in other cases. */
2459: if (GET_CODE (operand) != REG && GET_CODE (operand) != SCRATCH)
2460: reject++;
2461: }
2462:
2463: /* If this operand is a pseudo register that didn't get a hard
2464: reg and this alternative accepts some register, see if the
2465: class that we want is a subset of the preferred class for this
2466: register. If not, but it intersects that class, use the
2467: preferred class instead. If it does not intersect the preferred
2468: class, show that usage of this alternative should be discouraged;
2469: it will be discouraged more still if the register is `preferred
2470: or nothing'. We do this because it increases the chance of
2471: reusing our spill register in a later insn and avoiding a pair
2472: of memory stores and loads.
2473:
2474: Don't bother with this if this alternative will accept this
2475: operand.
2476:
2477: Don't do this if the preferred class has only one register
2478: because we might otherwise exhaust the class. */
2479:
2480:
2481: if (! win && this_alternative[i] != (int) NO_REGS
2482: && reg_class_size[(int) preferred_class[i]] > 1)
2483: {
2484: if (! reg_class_subset_p (this_alternative[i],
2485: preferred_class[i]))
2486: {
2487: /* Since we don't have a way of forming the intersection,
2488: we just do something special if the preferred class
2489: is a subset of the class we have; that's the most
2490: common case anyway. */
2491: if (reg_class_subset_p (preferred_class[i],
2492: this_alternative[i]))
2493: this_alternative[i] = (int) preferred_class[i];
2494: else
2495: reject += (1 + pref_or_nothing[i]);
2496: }
2497: }
2498: }
2499:
2500: /* Now see if any output operands that are marked "earlyclobber"
2501: in this alternative conflict with any input operands
2502: or any memory addresses. */
2503:
2504: for (i = 0; i < noperands; i++)
2505: if (this_alternative_earlyclobber[i]
2506: && this_alternative_win[i])
2507: {
2508: struct decomposition early_data;
2509: int j;
2510:
2511: early_data = decompose (recog_operand[i]);
2512:
2513: if (modified[i] == RELOAD_READ)
2514: {
2515: if (this_insn_is_asm)
2516: warning_for_asm (this_insn,
2517: "`&' constraint used with input operand");
2518: else
2519: abort ();
2520: continue;
2521: }
2522:
2523: if (this_alternative[i] == NO_REGS)
2524: {
2525: this_alternative_earlyclobber[i] = 0;
2526: if (this_insn_is_asm)
2527: error_for_asm (this_insn,
2528: "`&' constraint used with no register class");
2529: else
2530: abort ();
2531: }
2532:
2533: for (j = 0; j < noperands; j++)
2534: /* Is this an input operand or a memory ref? */
2535: if ((GET_CODE (recog_operand[j]) == MEM
2536: || modified[j] != RELOAD_WRITE)
2537: && j != i
2538: /* Ignore things like match_operator operands. */
2539: && *constraints1[j] != 0
2540: /* Don't count an input operand that is constrained to match
2541: the early clobber operand. */
2542: && ! (this_alternative_matches[j] == i
2543: && rtx_equal_p (recog_operand[i], recog_operand[j]))
2544: /* Is it altered by storing the earlyclobber operand? */
2545: && !immune_p (recog_operand[j], recog_operand[i], early_data))
2546: {
2547: /* If the output is in a single-reg class,
2548: it's costly to reload it, so reload the input instead. */
2549: if (reg_class_size[this_alternative[i]] == 1
2550: && (GET_CODE (recog_operand[j]) == REG
2551: || GET_CODE (recog_operand[j]) == SUBREG))
2552: {
2553: losers++;
2554: this_alternative_win[j] = 0;
2555: }
2556: else
2557: break;
2558: }
2559: /* If an earlyclobber operand conflicts with something,
2560: it must be reloaded, so request this and count the cost. */
2561: if (j != noperands)
2562: {
2563: losers++;
2564: this_alternative_win[i] = 0;
2565: for (j = 0; j < noperands; j++)
2566: if (this_alternative_matches[j] == i
2567: && this_alternative_win[j])
2568: {
2569: this_alternative_win[j] = 0;
2570: losers++;
2571: }
2572: }
2573: }
2574:
2575: /* If one alternative accepts all the operands, no reload required,
2576: choose that alternative; don't consider the remaining ones. */
2577: if (losers == 0)
2578: {
2579: /* Unswap these so that they are never swapped at `finish'. */
2580: if (commutative >= 0)
2581: {
2582: recog_operand[commutative] = substed_operand[commutative];
2583: recog_operand[commutative + 1]
2584: = substed_operand[commutative + 1];
2585: }
2586: for (i = 0; i < noperands; i++)
2587: {
2588: goal_alternative_win[i] = 1;
2589: goal_alternative[i] = this_alternative[i];
2590: goal_alternative_offmemok[i] = this_alternative_offmemok[i];
2591: goal_alternative_matches[i] = this_alternative_matches[i];
2592: goal_alternative_earlyclobber[i]
2593: = this_alternative_earlyclobber[i];
2594: }
2595: goal_alternative_number = this_alternative_number;
2596: goal_alternative_swapped = swapped;
2597: goal_earlyclobber = this_earlyclobber;
2598: goto finish;
2599: }
2600:
2601: /* REJECT, set by the ! and ? constraint characters and when a register
2602: would be reloaded into a non-preferred class, discourages the use of
2603: this alternative for a reload goal. REJECT is incremented by three
2604: for each ? and one for each non-preferred class. */
2605: losers = losers * 3 + reject;
2606:
2607: /* If this alternative can be made to work by reloading,
2608: and it needs less reloading than the others checked so far,
2609: record it as the chosen goal for reloading. */
2610: if (! bad && best > losers)
2611: {
2612: for (i = 0; i < noperands; i++)
2613: {
2614: goal_alternative[i] = this_alternative[i];
2615: goal_alternative_win[i] = this_alternative_win[i];
2616: goal_alternative_offmemok[i] = this_alternative_offmemok[i];
2617: goal_alternative_matches[i] = this_alternative_matches[i];
2618: goal_alternative_earlyclobber[i]
2619: = this_alternative_earlyclobber[i];
2620: }
2621: goal_alternative_swapped = swapped;
2622: best = losers;
2623: goal_alternative_number = this_alternative_number;
2624: goal_earlyclobber = this_earlyclobber;
2625: }
2626: }
2627:
2628: /* If insn is commutative (it's safe to exchange a certain pair of operands)
2629: then we need to try each alternative twice,
2630: the second time matching those two operands
2631: as if we had exchanged them.
2632: To do this, really exchange them in operands.
2633:
2634: If we have just tried the alternatives the second time,
2635: return operands to normal and drop through. */
2636:
2637: if (commutative >= 0)
2638: {
2639: swapped = !swapped;
2640: if (swapped)
2641: {
2642: register enum reg_class tclass;
2643: register int t;
2644:
2645: recog_operand[commutative] = substed_operand[commutative + 1];
2646: recog_operand[commutative + 1] = substed_operand[commutative];
2647:
2648: tclass = preferred_class[commutative];
2649: preferred_class[commutative] = preferred_class[commutative + 1];
2650: preferred_class[commutative + 1] = tclass;
2651:
2652: t = pref_or_nothing[commutative];
2653: pref_or_nothing[commutative] = pref_or_nothing[commutative + 1];
2654: pref_or_nothing[commutative + 1] = t;
2655:
2656: bcopy (constraints1, constraints, noperands * sizeof (char *));
2657: goto try_swapped;
2658: }
2659: else
2660: {
2661: recog_operand[commutative] = substed_operand[commutative];
2662: recog_operand[commutative + 1] = substed_operand[commutative + 1];
2663: }
2664: }
2665:
2666: /* The operands don't meet the constraints.
2667: goal_alternative describes the alternative
2668: that we could reach by reloading the fewest operands.
2669: Reload so as to fit it. */
2670:
2671: if (best == MAX_RECOG_OPERANDS + 300)
2672: {
2673: /* No alternative works with reloads?? */
2674: if (insn_code_number >= 0)
2675: abort ();
2676: error_for_asm (insn, "inconsistent operand constraints in an `asm'");
2677: /* Avoid further trouble with this insn. */
2678: PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
2679: n_reloads = 0;
2680: return;
2681: }
2682:
2683: /* Jump to `finish' from above if all operands are valid already.
2684: In that case, goal_alternative_win is all 1. */
2685: finish:
2686:
2687: /* Right now, for any pair of operands I and J that are required to match,
2688: with I < J,
2689: goal_alternative_matches[J] is I.
2690: Set up goal_alternative_matched as the inverse function:
2691: goal_alternative_matched[I] = J. */
2692:
2693: for (i = 0; i < noperands; i++)
2694: goal_alternative_matched[i] = -1;
2695:
2696: for (i = 0; i < noperands; i++)
2697: if (! goal_alternative_win[i]
2698: && goal_alternative_matches[i] >= 0)
2699: goal_alternative_matched[goal_alternative_matches[i]] = i;
2700:
2701: /* If the best alternative is with operands 1 and 2 swapped,
2702: consider them swapped before reporting the reloads. */
2703:
2704: if (goal_alternative_swapped)
2705: {
2706: register rtx tem;
2707:
2708: tem = substed_operand[commutative];
2709: substed_operand[commutative] = substed_operand[commutative + 1];
2710: substed_operand[commutative + 1] = tem;
2711: tem = recog_operand[commutative];
2712: recog_operand[commutative] = recog_operand[commutative + 1];
2713: recog_operand[commutative + 1] = tem;
2714: }
2715:
2716: /* Perform whatever substitutions on the operands we are supposed
2717: to make due to commutativity or replacement of registers
2718: with equivalent constants or memory slots. */
2719:
2720: for (i = 0; i < noperands; i++)
2721: {
2722: *recog_operand_loc[i] = substed_operand[i];
2723: /* While we are looping on operands, initialize this. */
2724: operand_reloadnum[i] = -1;
2725: }
2726:
2727: /* Any constants that aren't allowed and can't be reloaded
2728: into registers are here changed into memory references. */
2729: for (i = 0; i < noperands; i++)
2730: if (! goal_alternative_win[i]
2731: && CONSTANT_P (recog_operand[i])
2732: && (PREFERRED_RELOAD_CLASS (recog_operand[i],
2733: (enum reg_class) goal_alternative[i])
2734: == NO_REGS)
2735: && operand_mode[i] != VOIDmode)
2736: {
2737: *recog_operand_loc[i] = recog_operand[i]
2738: = find_reloads_toplev (force_const_mem (operand_mode[i],
2739: recog_operand[i]),
2740: ind_levels, 0);
2741: if (alternative_allows_memconst (constraints1[i],
2742: goal_alternative_number))
2743: goal_alternative_win[i] = 1;
2744: }
2745:
2746: /* Now record reloads for all the operands that need them. */
2747: for (i = 0; i < noperands; i++)
2748: if (! goal_alternative_win[i])
2749: {
2750: /* Operands that match previous ones have already been handled. */
2751: if (goal_alternative_matches[i] >= 0)
2752: ;
2753: /* Handle an operand with a nonoffsettable address
2754: appearing where an offsettable address will do
2755: by reloading the address into a base register. */
2756: else if (goal_alternative_matched[i] == -1
2757: && goal_alternative_offmemok[i]
2758: && GET_CODE (recog_operand[i]) == MEM)
2759: {
2760: operand_reloadnum[i]
2761: = push_reload (XEXP (recog_operand[i], 0), 0,
2762: &XEXP (recog_operand[i], 0), 0,
2763: BASE_REG_CLASS, GET_MODE (XEXP (recog_operand[i], 0)),
2764: VOIDmode, 0, 0, 0);
2765: reload_inc[operand_reloadnum[i]]
2766: = GET_MODE_SIZE (GET_MODE (recog_operand[i]));
2767: }
2768: else if (goal_alternative_matched[i] == -1)
2769: operand_reloadnum[i] =
2770: push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0,
2771: modified[i] != RELOAD_READ ? recog_operand[i] : 0,
2772: modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0,
2773: modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0,
2774: (enum reg_class) goal_alternative[i],
2775: (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]),
2776: (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]),
2777: (insn_code_number < 0 ? 0
2778: : insn_operand_strict_low[insn_code_number][i]),
2779: 0, 0);
2780: /* In a matching pair of operands, one must be input only
2781: and the other must be output only.
2782: Pass the input operand as IN and the other as OUT. */
2783: else if (modified[i] == RELOAD_READ
2784: && modified[goal_alternative_matched[i]] == RELOAD_WRITE)
2785: {
2786: operand_reloadnum[i]
2787: = push_reload (recog_operand[i],
2788: recog_operand[goal_alternative_matched[i]],
2789: recog_operand_loc[i],
2790: recog_operand_loc[goal_alternative_matched[i]],
2791: (enum reg_class) goal_alternative[i],
2792: operand_mode[i],
2793: operand_mode[goal_alternative_matched[i]],
2794: 0, 0, 0);
2795: operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum;
2796: }
2797: else if (modified[i] == RELOAD_WRITE
2798: && modified[goal_alternative_matched[i]] == RELOAD_READ)
2799: {
2800: operand_reloadnum[goal_alternative_matched[i]]
2801: = push_reload (recog_operand[goal_alternative_matched[i]],
2802: recog_operand[i],
2803: recog_operand_loc[goal_alternative_matched[i]],
2804: recog_operand_loc[i],
2805: (enum reg_class) goal_alternative[i],
2806: operand_mode[goal_alternative_matched[i]],
2807: operand_mode[i],
2808: 0, 0, 0);
2809: operand_reloadnum[i] = output_reloadnum;
2810: }
2811: else if (insn_code_number >= 0)
2812: abort ();
2813: else
2814: {
2815: error_for_asm (insn, "inconsistent operand constraints in an `asm'");
2816: /* Avoid further trouble with this insn. */
2817: PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
2818: n_reloads = 0;
2819: return;
2820: }
2821: }
2822: else if (goal_alternative_matched[i] < 0
2823: && goal_alternative_matches[i] < 0
2824: && optimize)
2825: {
2826: rtx operand = recog_operand[i];
2827: /* For each non-matching operand that's a pseudo-register
2828: that didn't get a hard register, make an optional reload.
2829: This may get done even if the insn needs no reloads otherwise. */
2830: /* (It would be safe to make an optional reload for a matching pair
2831: of operands, but we don't bother yet.) */
2832: while (GET_CODE (operand) == SUBREG)
2833: operand = XEXP (operand, 0);
2834: if (GET_CODE (operand) == REG
2835: && REGNO (operand) >= FIRST_PSEUDO_REGISTER
2836: && reg_renumber[REGNO (operand)] < 0
2837: && (enum reg_class) goal_alternative[i] != NO_REGS
2838: /* Don't make optional output reloads for jump insns
2839: (such as aobjeq on the vax). */
2840: && (modified[i] == RELOAD_READ
2841: || GET_CODE (insn) != JUMP_INSN))
2842: operand_reloadnum[i]
2843: = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0,
2844: modified[i] != RELOAD_READ ? recog_operand[i] : 0,
2845: modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0,
2846: modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0,
2847: (enum reg_class) goal_alternative[i],
2848: (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]),
2849: (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]),
2850: (insn_code_number < 0 ? 0
2851: : insn_operand_strict_low[insn_code_number][i]),
2852: 1, 0);
2853: /* Make an optional reload for an explicit mem ref. */
2854: else if (GET_CODE (operand) == MEM
2855: && (enum reg_class) goal_alternative[i] != NO_REGS
2856: /* Don't make optional output reloads for jump insns
2857: (such as aobjeq on the vax). */
2858: && (modified[i] == RELOAD_READ
2859: || GET_CODE (insn) != JUMP_INSN))
2860: operand_reloadnum[i]
2861: = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0,
2862: modified[i] != RELOAD_READ ? recog_operand[i] : 0,
2863: modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0,
2864: modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0,
2865: (enum reg_class) goal_alternative[i],
2866: (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]),
2867: (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]),
2868: (insn_code_number < 0 ? 0
2869: : insn_operand_strict_low[insn_code_number][i]),
2870: 1, 0);
2871: else
2872: non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i];
2873: }
2874: else if (goal_alternative_matched[i] < 0
2875: && goal_alternative_matches[i] < 0)
2876: non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i];
2877:
2878: /* Record the values of the earlyclobber operands for the caller. */
2879: if (goal_earlyclobber)
2880: for (i = 0; i < noperands; i++)
2881: if (goal_alternative_earlyclobber[i])
2882: reload_earlyclobbers[n_earlyclobbers++] = recog_operand[i];
2883:
2884: /* If this insn pattern contains any MATCH_DUP's, make sure that
2885: they will be substituted if the operands they match are substituted.
2886: Also do now any substitutions we already did on the operands.
2887:
2888: Don't do this if we aren't making replacements because we might be
2889: propagating things allocated by frame pointer elimination into places
2890: it doesn't expect. */
2891:
2892: if (insn_code_number >= 0 && replace)
2893: for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
2894: {
2895: int opno = recog_dup_num[i];
2896: *recog_dup_loc[i] = *recog_operand_loc[opno];
2897: if (operand_reloadnum[opno] >= 0)
2898: push_replacement (recog_dup_loc[i], operand_reloadnum[opno],
2899: insn_operand_mode[insn_code_number][opno]);
2900: }
2901:
2902: #if 0
2903: /* This loses because reloading of prior insns can invalidate the equivalence
2904: (or at least find_equiv_reg isn't smart enough to find it any more),
2905: causing this insn to need more reload regs than it needed before.
2906: It may be too late to make the reload regs available.
2907: Now this optimization is done safely in choose_reload_regs. */
2908:
2909: /* For each reload of a reg into some other class of reg,
2910: search for an existing equivalent reg (same value now) in the right class.
2911: We can use it as long as we don't need to change its contents. */
2912: for (i = 0; i < n_reloads; i++)
2913: if (reload_reg_rtx[i] == 0
2914: && reload_in[i] != 0
2915: && GET_CODE (reload_in[i]) == REG
2916: && reload_out[i] == 0)
2917: {
2918: reload_reg_rtx[i]
2919: = find_equiv_reg (reload_in[i], insn, reload_reg_class[i], -1,
2920: static_reload_reg_p, 0, reload_inmode[i]);
2921: /* Prevent generation of insn to load the value
2922: because the one we found already has the value. */
2923: if (reload_reg_rtx[i])
2924: reload_in[i] = reload_reg_rtx[i];
2925: }
2926: #endif
2927:
2928: #else /* no REGISTER_CONSTRAINTS */
2929: int noperands;
2930: int insn_code_number;
2931: int goal_earlyclobber = 0; /* Always 0, to make combine_reloads happen. */
2932: register int i;
2933: rtx body = PATTERN (insn);
2934:
2935: n_reloads = 0;
2936: n_replacements = 0;
2937: n_earlyclobbers = 0;
2938: replace_reloads = replace;
2939: this_insn = insn;
2940:
2941: /* Find what kind of insn this is. NOPERANDS gets number of operands.
2942: Store the operand values in RECOG_OPERAND and the locations
2943: of the words in the insn that point to them in RECOG_OPERAND_LOC.
2944: Return if the insn needs no reload processing. */
2945:
2946: switch (GET_CODE (body))
2947: {
2948: case USE:
2949: case CLOBBER:
2950: case ASM_INPUT:
2951: case ADDR_VEC:
2952: case ADDR_DIFF_VEC:
2953: return;
2954:
2955: case PARALLEL:
2956: case SET:
2957: noperands = asm_noperands (body);
2958: if (noperands >= 0)
2959: {
2960: /* This insn is an `asm' with operands.
2961: First, find out how many operands, and allocate space. */
2962:
2963: insn_code_number = -1;
2964: /* ??? This is a bug! ???
2965: Give up and delete this insn if it has too many operands. */
2966: if (noperands > MAX_RECOG_OPERANDS)
2967: abort ();
2968:
2969: /* Now get the operand values out of the insn. */
2970:
2971: decode_asm_operands (body, recog_operand, recog_operand_loc, 0, 0);
2972: break;
2973: }
2974:
2975: default:
2976: /* Ordinary insn: recognize it, allocate space for operands and
2977: constraints, and get them out via insn_extract. */
2978:
2979: insn_code_number = recog_memoized (insn);
2980: noperands = insn_n_operands[insn_code_number];
2981: insn_extract (insn);
2982: }
2983:
2984: if (noperands == 0)
2985: return;
2986:
2987: for (i = 0; i < noperands; i++)
2988: {
2989: register RTX_CODE code = GET_CODE (recog_operand[i]);
2990: int is_set_dest = GET_CODE (body) == SET && (i == 0);
2991:
2992: if (insn_code_number >= 0)
2993: if (insn_operand_address_p[insn_code_number][i])
2994: find_reloads_address (VOIDmode, 0,
2995: recog_operand[i], recog_operand_loc[i],
2996: recog_operand[i], ind_levels);
2997: if (code == MEM)
2998: find_reloads_address (GET_MODE (recog_operand[i]),
2999: recog_operand_loc[i],
3000: XEXP (recog_operand[i], 0),
3001: &XEXP (recog_operand[i], 0),
3002: recog_operand[i], ind_levels);
3003: if (code == SUBREG)
3004: recog_operand[i] = *recog_operand_loc[i]
3005: = find_reloads_toplev (recog_operand[i], ind_levels, is_set_dest);
3006: if (code == REG)
3007: {
3008: register int regno = REGNO (recog_operand[i]);
3009: if (reg_equiv_constant[regno] != 0 && !is_set_dest)
3010: recog_operand[i] = *recog_operand_loc[i]
3011: = reg_equiv_constant[regno];
3012: #if 0 /* This might screw code in reload1.c to delete prior output-reload
3013: that feeds this insn. */
3014: if (reg_equiv_mem[regno] != 0)
3015: recog_operand[i] = *recog_operand_loc[i]
3016: = reg_equiv_mem[regno];
3017: #endif
3018: }
3019: /* All operands are non-reloaded. */
3020: non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i];
3021: }
3022: #endif /* no REGISTER_CONSTRAINTS */
3023:
3024: /* Determine which part of the insn each reload is needed for,
3025: based on which operand the reload is needed for.
3026: Reloads of entire operands are classified as RELOAD_OTHER.
3027: So are reloads for which a unique purpose is not known. */
3028:
3029: for (i = 0; i < n_reloads; i++)
3030: {
3031: reload_when_needed[i] = RELOAD_OTHER;
3032:
3033: if (reload_needed_for[i] != 0 && ! reload_needed_for_multiple[i])
3034: {
3035: int j;
3036: int output_address = 0;
3037: int input_address = 0;
3038: int operand_address = 0;
3039:
3040: /* This reload is needed only for the address of something.
3041: Determine whether it is needed for addressing an operand
3042: being reloaded for input, whether it is needed for an
3043: operand being reloaded for output, and whether it is needed
3044: for addressing an operand that won't really be reloaded.
3045:
3046: Note that we know that this reload is needed in only one address,
3047: but we have not yet checked for the case where that same address
3048: is used in both input and output reloads.
3049: The following code detects this case. */
3050:
3051: for (j = 0; j < n_reloads; j++)
3052: if (reload_needed_for[i] == reload_in[j]
3053: || reload_needed_for[i] == reload_out[j])
3054: {
3055: if (reload_optional[j])
3056: operand_address = 1;
3057: else
3058: {
3059: if (reload_needed_for[i] == reload_in[j])
3060: input_address = 1;
3061: if (reload_needed_for[i] == reload_out[j])
3062: output_address = 1;
3063: }
3064: }
3065: /* Don't ignore memrefs without optional reloads. */
3066: for (j = 0; j < n_non_reloaded_operands; j++)
3067: if (reload_needed_for[i] == non_reloaded_operands[j])
3068: operand_address = 1;
3069:
3070: /* If it is needed for only one of those, record which one. */
3071:
3072: if (input_address && ! output_address && ! operand_address)
3073: reload_when_needed[i] = RELOAD_FOR_INPUT_RELOAD_ADDRESS;
3074: if (output_address && ! input_address && ! operand_address)
3075: reload_when_needed[i] = RELOAD_FOR_OUTPUT_RELOAD_ADDRESS;
3076: if (operand_address && ! input_address && ! output_address)
3077: reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS;
3078:
3079: /* Indicate those RELOAD_OTHER reloads which, though they have
3080: 0 for reload_output, still cannot overlap an output reload. */
3081:
3082: if (output_address && reload_when_needed[i] == RELOAD_OTHER)
3083: reload_needed_for_multiple[i] = 1;
3084: }
3085: }
3086:
3087: /* Perhaps an output reload can be combined with another
3088: to reduce needs by one. */
3089: if (!goal_earlyclobber)
3090: combine_reloads ();
3091: }
3092:
3093: /* Return 1 if alternative number ALTNUM in constraint-string CONSTRAINT
3094: accepts a memory operand with constant address. */
3095:
3096: static int
3097: alternative_allows_memconst (constraint, altnum)
3098: char *constraint;
3099: int altnum;
3100: {
3101: register int c;
3102: /* Skip alternatives before the one requested. */
3103: while (altnum > 0)
3104: {
3105: while (*constraint++ != ',');
3106: altnum--;
3107: }
3108: /* Scan the requested alternative for 'm' or 'o'.
3109: If one of them is present, this alternative accepts memory constants. */
3110: while ((c = *constraint++) && c != ',' && c != '#')
3111: if (c == 'm' || c == 'o')
3112: return 1;
3113: return 0;
3114: }
3115:
3116: /* Scan X for memory references and scan the addresses for reloading.
3117: Also checks for references to "constant" regs that we want to eliminate
3118: and replaces them with the values they stand for.
3119: We may alter X descructively if it contains a reference to such.
3120: If X is just a constant reg, we return the equivalent value
3121: instead of X.
3122:
3123: IND_LEVELS says how many levels of indirect addressing this machine
3124: supports.
3125:
3126: IS_SET_DEST is true if X is the destination of a SET, which is not
3127: appropriate to be replaced by a constant. */
3128:
3129: static rtx
3130: find_reloads_toplev (x, ind_levels, is_set_dest)
3131: rtx x;
3132: int ind_levels;
3133: int is_set_dest;
3134: {
3135: register RTX_CODE code = GET_CODE (x);
3136:
3137: register char *fmt = GET_RTX_FORMAT (code);
3138: register int i;
3139:
3140: if (code == REG)
3141: {
3142: /* This code is duplicated for speed in find_reloads. */
3143: register int regno = REGNO (x);
3144: if (reg_equiv_constant[regno] != 0 && !is_set_dest)
3145: x = reg_equiv_constant[regno];
3146: #if 0
3147: /* This creates (subreg (mem...)) which would cause an unnecessary
3148: reload of the mem. */
3149: else if (reg_equiv_mem[regno] != 0)
3150: x = reg_equiv_mem[regno];
3151: #endif
3152: else if (reg_equiv_address[regno] != 0)
3153: {
3154: /* If reg_equiv_address varies, it may be shared, so copy it. */
3155: rtx addr = reg_equiv_address[regno];
3156:
3157: if (rtx_varies_p (addr))
3158: addr = copy_rtx (addr);
3159:
3160: x = gen_rtx (MEM, GET_MODE (x), addr);
3161: RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
3162: find_reloads_address (GET_MODE (x), 0,
3163: XEXP (x, 0),
3164: &XEXP (x, 0), x, ind_levels);
3165: }
3166: return x;
3167: }
3168: if (code == MEM)
3169: {
3170: rtx tem = x;
3171: find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0),
3172: x, ind_levels);
3173: return tem;
3174: }
3175:
3176: if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)
3177: {
3178: /* Check for SUBREG containing a REG that's equivalent to a constant.
3179: If the constant has a known value, truncate it right now.
3180: Similarly if we are extracting a single-word of a multi-word
3181: constant. If the constant is symbolic, allow it to be substituted
3182: normally. push_reload will strip the subreg later. If the
3183: constant is VOIDmode, abort because we will lose the mode of
3184: the register (this should never happen because one of the cases
3185: above should handle it). */
3186:
3187: register int regno = REGNO (SUBREG_REG (x));
3188: rtx tem;
3189:
3190: if (subreg_lowpart_p (x)
3191: && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
3192: && reg_equiv_constant[regno] != 0
3193: && (tem = gen_lowpart_common (GET_MODE (x),
3194: reg_equiv_constant[regno])) != 0)
3195: return tem;
3196:
3197: if (GET_MODE_BITSIZE (GET_MODE (x)) == BITS_PER_WORD
3198: && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
3199: && reg_equiv_constant[regno] != 0
3200: && (tem = operand_subword (reg_equiv_constant[regno],
3201: SUBREG_WORD (x), 0,
3202: GET_MODE (SUBREG_REG (x)))) != 0)
3203: return tem;
3204:
3205: if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
3206: && reg_equiv_constant[regno] != 0
3207: && GET_MODE (reg_equiv_constant[regno]) == VOIDmode)
3208: abort ();
3209:
3210: /* If the subreg contains a reg that will be converted to a mem,
3211: convert the subreg to a narrower memref now.
3212: Otherwise, we would get (subreg (mem ...) ...),
3213: which would force reload of the mem.
3214:
3215: We also need to do this if there is an equivalent MEM that is
3216: not offsettable. In that case, alter_subreg would produce an
3217: invalid address on big-endian machines. */
3218:
3219: else if (regno >= FIRST_PSEUDO_REGISTER
3220: && (reg_equiv_address[regno] != 0
3221: || (reg_equiv_mem[regno] != 0
3222: && ! offsettable_memref_p (reg_equiv_mem[regno]))))
3223: {
3224: int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3225: rtx addr = (reg_equiv_address[regno] ? reg_equiv_address[regno]
3226: : XEXP (reg_equiv_mem[regno], 0));
3227: #if BYTES_BIG_ENDIAN
3228: int size;
3229: size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
3230: offset += MIN (size, UNITS_PER_WORD);
3231: size = GET_MODE_SIZE (GET_MODE (x));
3232: offset -= MIN (size, UNITS_PER_WORD);
3233: #endif
3234: addr = plus_constant (addr, offset);
3235: x = gen_rtx (MEM, GET_MODE (x), addr);
3236: RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
3237: find_reloads_address (GET_MODE (x), 0,
3238: XEXP (x, 0),
3239: &XEXP (x, 0), x, ind_levels);
3240: }
3241:
3242: }
3243:
3244: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3245: {
3246: if (fmt[i] == 'e')
3247: XEXP (x, i) = find_reloads_toplev (XEXP (x, i),
3248: ind_levels, is_set_dest);
3249: }
3250: return x;
3251: }
3252:
3253: static rtx
3254: make_memloc (ad, regno)
3255: rtx ad;
3256: int regno;
3257: {
3258: register int i;
3259: rtx tem = reg_equiv_address[regno];
3260: for (i = 0; i < n_memlocs; i++)
3261: if (rtx_equal_p (tem, XEXP (memlocs[i], 0)))
3262: return memlocs[i];
3263:
3264: /* If TEM might contain a pseudo, we must copy it to avoid
3265: modifying it when we do the substitution for the reload. */
3266: if (rtx_varies_p (tem))
3267: tem = copy_rtx (tem);
3268:
3269: tem = gen_rtx (MEM, GET_MODE (ad), tem);
3270: RTX_UNCHANGING_P (tem) = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
3271: memlocs[n_memlocs++] = tem;
3272: return tem;
3273: }
3274:
3275: /* Record all reloads needed for handling memory address AD
3276: which appears in *LOC in a memory reference to mode MODE
3277: which itself is found in location *MEMREFLOC.
3278: Note that we take shortcuts assuming that no multi-reg machine mode
3279: occurs as part of an address.
3280:
3281: OPERAND is the operand of the insn within which this address appears.
3282:
3283: IND_LEVELS says how many levels of indirect addressing this machine
3284: supports.
3285:
3286: Value is nonzero if this address is reloaded or replaced as a whole.
3287: This is interesting to the caller if the address is an autoincrement.
3288:
3289: Note that there is no verification that the address will be valid after
3290: this routine does its work. Instead, we rely on the fact that the address
3291: was valid when reload started. So we need only undo things that reload
3292: could have broken. These are wrong register types, pseudos not allocated
3293: to a hard register, and frame pointer elimination. */
3294:
3295: static int
3296: find_reloads_address (mode, memrefloc, ad, loc, operand, ind_levels)
3297: enum machine_mode mode;
3298: rtx *memrefloc;
3299: rtx ad;
3300: rtx *loc;
3301: rtx operand;
3302: int ind_levels;
3303: {
3304: register int regno;
3305: rtx tem;
3306:
3307: /* If the address is a register, see if it is a legitimate address and
3308: reload if not. We first handle the cases where we need not reload
3309: or where we must reload in a non-standard way. */
3310:
3311: if (GET_CODE (ad) == REG)
3312: {
3313: regno = REGNO (ad);
3314:
3315: if (reg_equiv_constant[regno] != 0
3316: && strict_memory_address_p (mode, reg_equiv_constant[regno]))
3317: {
3318: *loc = ad = reg_equiv_constant[regno];
3319: return 1;
3320: }
3321:
3322: else if (reg_equiv_address[regno] != 0)
3323: {
3324: tem = make_memloc (ad, regno);
3325: find_reloads_address (GET_MODE (tem), 0, XEXP (tem, 0),
3326: &XEXP (tem, 0), operand, ind_levels);
3327: push_reload (tem, 0, loc, 0, BASE_REG_CLASS,
3328: GET_MODE (ad), VOIDmode, 0, 0,
3329: operand);
3330: return 1;
3331: }
3332:
3333: else if (reg_equiv_mem[regno] != 0)
3334: {
3335: tem = XEXP (reg_equiv_mem[regno], 0);
3336:
3337: /* If we can't indirect any more, a pseudo must be reloaded.
3338: If the pseudo's address in its MEM is a SYMBOL_REF, it
3339: must be reloaded unless indirect_symref_ok. Otherwise, it
3340: can be reloaded if the address is REG or REG + CONST_INT. */
3341:
3342: if (ind_levels > 0
3343: && ! (GET_CODE (tem) == SYMBOL_REF && ! indirect_symref_ok)
3344: && ((GET_CODE (tem) == REG
3345: && REGNO (tem) < FIRST_PSEUDO_REGISTER)
3346: || (GET_CODE (tem) == PLUS
3347: && GET_CODE (XEXP (tem, 0)) == REG
3348: && REGNO (XEXP (tem, 0)) < FIRST_PSEUDO_REGISTER
3349: && GET_CODE (XEXP (tem, 1)) == CONST_INT)))
3350: return 0;
3351: }
3352:
3353: /* The only remaining case where we can avoid a reload is if this is a
3354: hard register that is valid as a base register and which is not the
3355: subject of a CLOBBER in this insn. */
3356:
3357: else if (regno < FIRST_PSEUDO_REGISTER && REGNO_OK_FOR_BASE_P (regno)
3358: && ! regno_clobbered_p (regno, this_insn))
3359: return 0;
3360:
3361: /* If we do not have one of the cases above, we must do the reload. */
3362: push_reload (ad, 0, loc, 0, BASE_REG_CLASS,
3363: GET_MODE (ad), VOIDmode, 0, 0, operand);
3364: return 1;
3365: }
3366:
3367: if (strict_memory_address_p (mode, ad))
3368: {
3369: /* The address appears valid, so reloads are not needed.
3370: But the address may contain an eliminable register.
3371: This can happen because a machine with indirect addressing
3372: may consider a pseudo register by itself a valid address even when
3373: it has failed to get a hard reg.
3374: So do a tree-walk to find and eliminate all such regs. */
3375:
3376: /* But first quickly dispose of a common case. */
3377: if (GET_CODE (ad) == PLUS
3378: && GET_CODE (XEXP (ad, 1)) == CONST_INT
3379: && GET_CODE (XEXP (ad, 0)) == REG
3380: && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0)
3381: return 0;
3382:
3383: subst_reg_equivs_changed = 0;
3384: *loc = subst_reg_equivs (ad);
3385:
3386: if (! subst_reg_equivs_changed)
3387: return 0;
3388:
3389: /* Check result for validity after substitution. */
3390: if (strict_memory_address_p (mode, ad))
3391: return 0;
3392: }
3393:
3394: /* The address is not valid. We have to figure out why. One possibility
3395: is that it is itself a MEM. This can happen when the frame pointer is
3396: being eliminated, a pseudo is not allocated to a hard register, and the
3397: offset between the frame and stack pointers is not its initial value.
3398: In that case the psuedo will have been replaced by a MEM referring to
3399: the stack pointer. */
3400: if (GET_CODE (ad) == MEM)
3401: {
3402: /* First ensure that the address in this MEM is valid. Then, unless
3403: indirect addresses are valid, reload the MEM into a register. */
3404: tem = ad;
3405: find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0),
3406: operand, ind_levels == 0 ? 0 : ind_levels - 1);
3407: /* Check similar cases as for indirect addresses as above except
3408: that we can allow pseudos and a MEM since they should have been
3409: taken care of above. */
3410:
3411: if (ind_levels == 0
3412: || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok)
3413: || GET_CODE (XEXP (tem, 0)) == MEM
3414: || ! (GET_CODE (XEXP (tem, 0)) == REG
3415: || (GET_CODE (XEXP (tem, 0)) == PLUS
3416: && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG
3417: && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT)))
3418: {
3419: /* Must use TEM here, not AD, since it is the one that will
3420: have any subexpressions reloaded, if needed. */
3421: push_reload (tem, 0, loc, 0,
3422: BASE_REG_CLASS, GET_MODE (tem), VOIDmode, 0,
3423: 0, operand);
3424: return 1;
3425: }
3426: else
3427: return 0;
3428: }
3429:
3430: /* If we have address of a stack slot but it's not valid
3431: (displacement is too large), compute the sum in a register. */
3432: else if (GET_CODE (ad) == PLUS
3433: && (XEXP (ad, 0) == frame_pointer_rtx
3434: #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3435: || XEXP (ad, 0) == arg_pointer_rtx
3436: #endif
3437: || XEXP (ad, 0) == stack_pointer_rtx)
3438: && GET_CODE (XEXP (ad, 1)) == CONST_INT)
3439: {
3440: /* Unshare the MEM rtx so we can safely alter it. */
3441: if (memrefloc)
3442: {
3443: rtx oldref = *memrefloc;
3444: *memrefloc = copy_rtx (*memrefloc);
3445: loc = &XEXP (*memrefloc, 0);
3446: if (operand == oldref)
3447: operand = *memrefloc;
3448: }
3449: if (double_reg_address_ok)
3450: {
3451: /* Unshare the sum as well. */
3452: *loc = ad = copy_rtx (ad);
3453: /* Reload the displacement into an index reg.
3454: We assume the frame pointer or arg pointer is a base reg. */
3455: find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1),
3456: INDEX_REG_CLASS, GET_MODE (ad), operand,
3457: ind_levels);
3458: }
3459: else
3460: {
3461: /* If the sum of two regs is not necessarily valid,
3462: reload the sum into a base reg.
3463: That will at least work. */
3464: find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode,
3465: operand, ind_levels);
3466: }
3467: return 1;
3468: }
3469:
3470: /* If we have an indexed stack slot, there are three possible reasons why
3471: it might be invalid: The index might need to be reloaded, the address
3472: might have been made by frame pointer elimination and hence have a
3473: constant out of range, or both reasons might apply.
3474:
3475: We can easily check for an index needing reload, but even if that is the
3476: case, we might also have an invalid constant. To avoid making the
3477: conservative assumption and requiring two reloads, we see if this address
3478: is valid when not interpreted strictly. If it is, the only problem is
3479: that the index needs a reload and find_reloads_address_1 will take care
3480: of it.
3481:
3482: There is still a case when we might generate an extra reload,
3483: however. In certain cases eliminate_regs will return a MEM for a REG
3484: (see the code there for details). In those cases, memory_address_p
3485: applied to our address will return 0 so we will think that our offset
3486: must be too large. But it might indeed be valid and the only problem
3487: is that a MEM is present where a REG should be. This case should be
3488: very rare and there doesn't seem to be any way to avoid it.
3489:
3490: If we decide to do something here, it must be that
3491: `double_reg_address_ok' is true and that this address rtl was made by
3492: eliminate_regs. We generate a reload of the fp/sp/ap + constant and
3493: rework the sum so that the reload register will be added to the index.
3494: This is safe because we know the address isn't shared.
3495:
3496: We check for fp/ap/sp as both the first and second operand of the
3497: innermost PLUS. */
3498:
3499: else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
3500: && GET_CODE (XEXP (ad, 0)) == PLUS
3501: && (XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx
3502: #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3503: || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx
3504: #endif
3505: || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx)
3506: && ! memory_address_p (mode, ad))
3507: {
3508: *loc = ad = gen_rtx (PLUS, GET_MODE (ad),
3509: plus_constant (XEXP (XEXP (ad, 0), 0),
3510: INTVAL (XEXP (ad, 1))),
3511: XEXP (XEXP (ad, 0), 1));
3512: find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS,
3513: GET_MODE (ad), operand, ind_levels);
3514: find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), operand, 0);
3515:
3516: return 1;
3517: }
3518:
3519: else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
3520: && GET_CODE (XEXP (ad, 0)) == PLUS
3521: && (XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx
3522: #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3523: || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx
3524: #endif
3525: || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx)
3526: && ! memory_address_p (mode, ad))
3527: {
3528: *loc = ad = gen_rtx (PLUS, GET_MODE (ad),
3529: plus_constant (XEXP (XEXP (ad, 0), 1),
3530: INTVAL (XEXP (ad, 1))),
3531: XEXP (XEXP (ad, 0), 0));
3532: find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS,
3533: GET_MODE (ad), operand, ind_levels);
3534: find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), operand, 0);
3535:
3536: return 1;
3537: }
3538:
3539: /* See if address becomes valid when an eliminable register
3540: in a sum is replaced. */
3541:
3542: tem = ad;
3543: if (GET_CODE (ad) == PLUS)
3544: tem = subst_indexed_address (ad);
3545: if (tem != ad && strict_memory_address_p (mode, tem))
3546: {
3547: /* Ok, we win that way. Replace any additional eliminable
3548: registers. */
3549:
3550: subst_reg_equivs_changed = 0;
3551: tem = subst_reg_equivs (tem);
3552:
3553: /* Make sure that didn't make the address invalid again. */
3554:
3555: if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem))
3556: {
3557: *loc = tem;
3558: return 0;
3559: }
3560: }
3561:
3562: /* If constants aren't valid addresses, reload the constant address
3563: into a register. */
3564: if (CONSTANT_ADDRESS_P (ad) && ! strict_memory_address_p (mode, ad))
3565: {
3566: /* If AD is in address in the constant pool, the MEM rtx may be shared.
3567: Unshare it so we can safely alter it. */
3568: if (memrefloc && GET_CODE (ad) == SYMBOL_REF
3569: && CONSTANT_POOL_ADDRESS_P (ad))
3570: {
3571: rtx oldref = *memrefloc;
3572: *memrefloc = copy_rtx (*memrefloc);
3573: loc = &XEXP (*memrefloc, 0);
3574: if (operand == oldref)
3575: operand = *memrefloc;
3576: }
3577:
3578: find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, operand,
3579: ind_levels);
3580: return 1;
3581: }
3582:
3583: return find_reloads_address_1 (ad, 0, loc, operand, ind_levels);
3584: }
3585:
3586: /* Find all pseudo regs appearing in AD
3587: that are eliminable in favor of equivalent values
3588: and do not have hard regs; replace them by their equivalents. */
3589:
3590: static rtx
3591: subst_reg_equivs (ad)
3592: rtx ad;
3593: {
3594: register RTX_CODE code = GET_CODE (ad);
3595: register int i;
3596: register char *fmt;
3597:
3598: switch (code)
3599: {
3600: case HIGH:
3601: case CONST_INT:
3602: case CONST:
3603: case CONST_DOUBLE:
3604: case SYMBOL_REF:
3605: case LABEL_REF:
3606: case PC:
3607: case CC0:
3608: return ad;
3609:
3610: case REG:
3611: {
3612: register int regno = REGNO (ad);
3613:
3614: if (reg_equiv_constant[regno] != 0)
3615: {
3616: subst_reg_equivs_changed = 1;
3617: return reg_equiv_constant[regno];
3618: }
3619: }
3620: return ad;
3621:
3622: case PLUS:
3623: /* Quickly dispose of a common case. */
3624: if (XEXP (ad, 0) == frame_pointer_rtx
3625: && GET_CODE (XEXP (ad, 1)) == CONST_INT)
3626: return ad;
3627: }
3628:
3629: fmt = GET_RTX_FORMAT (code);
3630: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3631: if (fmt[i] == 'e')
3632: XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i));
3633: return ad;
3634: }
3635:
3636: /* Compute the sum of X and Y, making canonicalizations assumed in an
3637: address, namely: sum constant integers, surround the sum of two
3638: constants with a CONST, put the constant as the second operand, and
3639: group the constant on the outermost sum.
3640:
3641: This routine assumes both inputs are already in canonical form. */
3642:
3643: rtx
3644: form_sum (x, y)
3645: rtx x, y;
3646: {
3647: rtx tem;
3648:
3649: if (GET_CODE (x) == CONST_INT)
3650: return plus_constant (y, INTVAL (x));
3651: else if (GET_CODE (y) == CONST_INT)
3652: return plus_constant (x, INTVAL (y));
3653: else if (CONSTANT_P (x))
3654: tem = x, x = y, y = tem;
3655:
3656: if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1)))
3657: return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y));
3658:
3659: /* Note that if the operands of Y are specified in the opposite
3660: order in the recursive calls below, infinite recursion will occur. */
3661: if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1)))
3662: return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1));
3663:
3664: /* If both constant, encapsulate sum. Otherwise, just form sum. A
3665: constant will have been placed second. */
3666: if (CONSTANT_P (x) && CONSTANT_P (y))
3667: {
3668: if (GET_CODE (x) == CONST)
3669: x = XEXP (x, 0);
3670: if (GET_CODE (y) == CONST)
3671: y = XEXP (y, 0);
3672:
3673: return gen_rtx (CONST, VOIDmode, gen_rtx (PLUS, Pmode, x, y));
3674: }
3675:
3676: return gen_rtx (PLUS, Pmode, x, y);
3677: }
3678:
3679: /* If ADDR is a sum containing a pseudo register that should be
3680: replaced with a constant (from reg_equiv_constant),
3681: return the result of doing so, and also apply the associative
3682: law so that the result is more likely to be a valid address.
3683: (But it is not guaranteed to be one.)
3684:
3685: Note that at most one register is replaced, even if more are
3686: replaceable. Also, we try to put the result into a canonical form
3687: so it is more likely to be a valid address.
3688:
3689: In all other cases, return ADDR. */
3690:
3691: static rtx
3692: subst_indexed_address (addr)
3693: rtx addr;
3694: {
3695: rtx op0 = 0, op1 = 0, op2 = 0;
3696: rtx tem;
3697: int regno;
3698:
3699: if (GET_CODE (addr) == PLUS)
3700: {
3701: /* Try to find a register to replace. */
3702: op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0;
3703: if (GET_CODE (op0) == REG
3704: && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER
3705: && reg_renumber[regno] < 0
3706: && reg_equiv_constant[regno] != 0)
3707: op0 = reg_equiv_constant[regno];
3708: else if (GET_CODE (op1) == REG
3709: && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER
3710: && reg_renumber[regno] < 0
3711: && reg_equiv_constant[regno] != 0)
3712: op1 = reg_equiv_constant[regno];
3713: else if (GET_CODE (op0) == PLUS
3714: && (tem = subst_indexed_address (op0)) != op0)
3715: op0 = tem;
3716: else if (GET_CODE (op1) == PLUS
3717: && (tem = subst_indexed_address (op1)) != op1)
3718: op1 = tem;
3719: else
3720: return addr;
3721:
3722: /* Pick out up to three things to add. */
3723: if (GET_CODE (op1) == PLUS)
3724: op2 = XEXP (op1, 1), op1 = XEXP (op1, 0);
3725: else if (GET_CODE (op0) == PLUS)
3726: op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3727:
3728: /* Compute the sum. */
3729: if (op2 != 0)
3730: op1 = form_sum (op1, op2);
3731: if (op1 != 0)
3732: op0 = form_sum (op0, op1);
3733:
3734: return op0;
3735: }
3736: return addr;
3737: }
3738:
3739: /* Record the pseudo registers we must reload into hard registers
3740: in a subexpression of a would-be memory address, X.
3741: (This function is not called if the address we find is strictly valid.)
3742: CONTEXT = 1 means we are considering regs as index regs,
3743: = 0 means we are considering them as base regs.
3744:
3745: OPERAND is the operand of the insn within which this address appears.
3746:
3747: IND_LEVELS says how many levels of indirect addressing are
3748: supported at this point in the address.
3749:
3750: We return nonzero if X, as a whole, is reloaded or replaced. */
3751:
3752: /* Note that we take shortcuts assuming that no multi-reg machine mode
3753: occurs as part of an address.
3754: Also, this is not fully machine-customizable; it works for machines
3755: such as vaxes and 68000's and 32000's, but other possible machines
3756: could have addressing modes that this does not handle right. */
3757:
3758: static int
3759: find_reloads_address_1 (x, context, loc, operand, ind_levels)
3760: rtx x;
3761: int context;
3762: rtx *loc;
3763: rtx operand;
3764: int ind_levels;
3765: {
3766: register RTX_CODE code = GET_CODE (x);
3767:
3768: if (code == PLUS)
3769: {
3770: register rtx op0 = XEXP (x, 0);
3771: register rtx op1 = XEXP (x, 1);
3772: register RTX_CODE code0 = GET_CODE (op0);
3773: register RTX_CODE code1 = GET_CODE (op1);
3774: if (code0 == MULT || code0 == SIGN_EXTEND || code1 == MEM)
3775: {
3776: find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels);
3777: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
3778: }
3779: else if (code1 == MULT || code1 == SIGN_EXTEND || code0 == MEM)
3780: {
3781: find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
3782: find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels);
3783: }
3784: else if (code0 == CONST_INT || code0 == CONST
3785: || code0 == SYMBOL_REF || code0 == LABEL_REF)
3786: {
3787: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
3788: }
3789: else if (code1 == CONST_INT || code1 == CONST
3790: || code1 == SYMBOL_REF || code1 == LABEL_REF)
3791: {
3792: find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
3793: }
3794: else if (code0 == REG && code1 == REG)
3795: {
3796: if (REG_OK_FOR_INDEX_P (op0)
3797: && REG_OK_FOR_BASE_P (op1))
3798: return 0;
3799: else if (REG_OK_FOR_INDEX_P (op1)
3800: && REG_OK_FOR_BASE_P (op0))
3801: return 0;
3802: else if (REG_OK_FOR_BASE_P (op1))
3803: find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels);
3804: else if (REG_OK_FOR_BASE_P (op0))
3805: find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels);
3806: else if (REG_OK_FOR_INDEX_P (op1))
3807: find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
3808: else if (REG_OK_FOR_INDEX_P (op0))
3809: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
3810: else
3811: {
3812: find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand,
3813: ind_levels);
3814: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand,
3815: ind_levels);
3816: }
3817: }
3818: else if (code0 == REG)
3819: {
3820: find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels);
3821: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
3822: }
3823: else if (code1 == REG)
3824: {
3825: find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels);
3826: find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
3827: }
3828: }
3829: else if (code == POST_INC || code == POST_DEC
3830: || code == PRE_INC || code == PRE_DEC)
3831: {
3832: if (GET_CODE (XEXP (x, 0)) == REG)
3833: {
3834: register int regno = REGNO (XEXP (x, 0));
3835: int value = 0;
3836: rtx x_orig = x;
3837:
3838: /* A register that is incremented cannot be constant! */
3839: if (regno >= FIRST_PSEUDO_REGISTER
3840: && reg_equiv_constant[regno] != 0)
3841: abort ();
3842:
3843: /* Handle a register that is equivalent to a memory location
3844: which cannot be addressed directly. */
3845: if (reg_equiv_address[regno] != 0)
3846: {
3847: rtx tem = make_memloc (XEXP (x, 0), regno);
3848: /* First reload the memory location's address. */
3849: find_reloads_address (GET_MODE (tem), 0, XEXP (tem, 0),
3850: &XEXP (tem, 0), operand, ind_levels);
3851: /* Put this inside a new increment-expression. */
3852: x = gen_rtx (GET_CODE (x), GET_MODE (x), tem);
3853: /* Proceed to reload that, as if it contained a register. */
3854: }
3855:
3856: /* If we have a hard register that is ok as an index,
3857: don't make a reload. If an autoincrement of a nice register
3858: isn't "valid", it must be that no autoincrement is "valid".
3859: If that is true and something made an autoincrement anyway,
3860: this must be a special context where one is allowed.
3861: (For example, a "push" instruction.)
3862: We can't improve this address, so leave it alone. */
3863:
3864: /* Otherwise, reload the autoincrement into a suitable hard reg
3865: and record how much to increment by. */
3866:
3867: if (reg_renumber[regno] >= 0)
3868: regno = reg_renumber[regno];
3869: if ((regno >= FIRST_PSEUDO_REGISTER
3870: || !(context ? REGNO_OK_FOR_INDEX_P (regno)
3871: : REGNO_OK_FOR_BASE_P (regno))))
3872: {
3873: register rtx link;
3874:
3875: int reloadnum
3876: = push_reload (x, 0, loc, 0,
3877: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3878: GET_MODE (x), GET_MODE (x), VOIDmode, 0, operand);
3879: reload_inc[reloadnum]
3880: = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0));
3881:
3882: value = 1;
3883:
3884: #ifdef AUTO_INC_DEC
3885: /* Update the REG_INC notes. */
3886:
3887: for (link = REG_NOTES (this_insn);
3888: link; link = XEXP (link, 1))
3889: if (REG_NOTE_KIND (link) == REG_INC
3890: && REGNO (XEXP (link, 0)) == REGNO (XEXP (x_orig, 0)))
3891: push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
3892: #endif
3893: }
3894: return value;
3895: }
3896: else if (GET_CODE (XEXP (x, 0)) == MEM)
3897: {
3898: /* This is probably the result of a substitution, by eliminate_regs,
3899: of an equivalent address for a pseudo that was not allocated to a
3900: hard register. Verify that the specified address is valid and
3901: reload it into a register. */
3902: rtx tem = XEXP (x, 0);
3903: register rtx link;
3904: int reloadnum;
3905:
3906: /* Since we know we are going to reload this item, don't decrement
3907: for the indirection level.
3908:
3909: Note that this is actually conservative: it would be slightly
3910: more efficient to use the value of SPILL_INDIRECT_LEVELS from
3911: reload1.c here. */
3912: find_reloads_address (GET_MODE (x), &XEXP (x, 0),
3913: XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0),
3914: operand, ind_levels);
3915:
3916: reloadnum = push_reload (x, 0, loc, 0,
3917: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3918: GET_MODE (x), VOIDmode, 0, 0, operand);
3919: reload_inc[reloadnum]
3920: = find_inc_amount (PATTERN (this_insn), XEXP (x, 0));
3921:
3922: link = FIND_REG_INC_NOTE (this_insn, tem);
3923: if (link != 0)
3924: push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
3925:
3926: return 1;
3927: }
3928: }
3929: else if (code == MEM)
3930: {
3931: /* This is probably the result of a substitution, by eliminate_regs,
3932: of an equivalent address for a pseudo that was not allocated to a
3933: hard register. Verify that the specified address is valid and reload
3934: it into a register.
3935:
3936: Since we know we are going to reload this item, don't decrement
3937: for the indirection level.
3938:
3939: Note that this is actually conservative: it would be slightly more
3940: efficient to use the value of SPILL_INDIRECT_LEVELS from
3941: reload1.c here. */
3942:
3943: find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
3944: operand, ind_levels);
3945:
3946: push_reload (*loc, 0, loc, 0,
3947: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3948: GET_MODE (x), VOIDmode, 0, 0, operand);
3949: return 1;
3950: }
3951: else if (code == REG)
3952: {
3953: register int regno = REGNO (x);
3954:
3955: if (reg_equiv_constant[regno] != 0)
3956: {
3957: push_reload (reg_equiv_constant[regno], 0, loc, 0,
3958: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3959: GET_MODE (x), VOIDmode, 0, 0, operand);
3960: return 1;
3961: }
3962:
3963: #if 0 /* This might screw code in reload1.c to delete prior output-reload
3964: that feeds this insn. */
3965: if (reg_equiv_mem[regno] != 0)
3966: {
3967: push_reload (reg_equiv_mem[regno], 0, loc, 0,
3968: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3969: GET_MODE (x), VOIDmode, 0, 0, operand);
3970: return 1;
3971: }
3972: #endif
3973: if (reg_equiv_address[regno] != 0)
3974: {
3975: x = make_memloc (x, regno);
3976: find_reloads_address (GET_MODE (x), 0, XEXP (x, 0), &XEXP (x, 0),
3977: operand, ind_levels);
3978: }
3979:
3980: if (reg_renumber[regno] >= 0)
3981: regno = reg_renumber[regno];
3982: if ((regno >= FIRST_PSEUDO_REGISTER
3983: || !(context ? REGNO_OK_FOR_INDEX_P (regno)
3984: : REGNO_OK_FOR_BASE_P (regno))))
3985: {
3986: push_reload (x, 0, loc, 0,
3987: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3988: GET_MODE (x), VOIDmode, 0, 0, operand);
3989: return 1;
3990: }
3991:
3992: /* If a register appearing in an address is the subject of a CLOBBER
3993: in this insn, reload it into some other register to be safe.
3994: The CLOBBER is supposed to make the register unavailable
3995: from before this insn to after it. */
3996: if (regno_clobbered_p (regno, this_insn))
3997: {
3998: push_reload (x, 0, loc, 0,
3999: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4000: GET_MODE (x), VOIDmode, 0, 0, operand);
4001: return 1;
4002: }
4003: }
4004: else
4005: {
4006: register char *fmt = GET_RTX_FORMAT (code);
4007: register int i;
4008: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4009: {
4010: if (fmt[i] == 'e')
4011: find_reloads_address_1 (XEXP (x, i), context, &XEXP (x, i),
4012: operand, ind_levels);
4013: }
4014: }
4015:
4016: return 0;
4017: }
4018:
4019: /* X, which is found at *LOC, is a part of an address that needs to be
4020: reloaded into a register of class CLASS. If X is a constant, or if
4021: X is a PLUS that contains a constant, check that the constant is a
4022: legitimate operand and that we are supposed to be able to load
4023: it into the register.
4024:
4025: If not, force the constant into memory and reload the MEM instead.
4026:
4027: MODE is the mode to use, in case X is an integer constant.
4028:
4029: NEEDED_FOR says which operand this reload is needed for.
4030:
4031: IND_LEVELS says how many levels of indirect addressing this machine
4032: supports. */
4033:
4034: static void
4035: find_reloads_address_part (x, loc, class, mode, needed_for, ind_levels)
4036: rtx x;
4037: rtx *loc;
4038: enum reg_class class;
4039: enum machine_mode mode;
4040: rtx needed_for;
4041: int ind_levels;
4042: {
4043: if (CONSTANT_P (x)
4044: && (! LEGITIMATE_CONSTANT_P (x)
4045: || PREFERRED_RELOAD_CLASS (x, class) == NO_REGS))
4046: {
4047: rtx tem = x = force_const_mem (mode, x);
4048: find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0),
4049: needed_for, ind_levels);
4050: }
4051:
4052: else if (GET_CODE (x) == PLUS
4053: && CONSTANT_P (XEXP (x, 1))
4054: && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1))
4055: || PREFERRED_RELOAD_CLASS (XEXP (x, 1), class) == NO_REGS))
4056: {
4057: rtx tem = force_const_mem (GET_MODE (x), XEXP (x, 1));
4058:
4059: x = gen_rtx (PLUS, GET_MODE (x), XEXP (x, 0), tem);
4060: find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0),
4061: needed_for, ind_levels);
4062: }
4063:
4064: push_reload (x, 0, loc, 0, class, mode, VOIDmode, 0, 0, needed_for);
4065: }
4066:
4067: /* Substitute into X the registers into which we have reloaded
4068: the things that need reloading. The array `replacements'
4069: says contains the locations of all pointers that must be changed
4070: and says what to replace them with.
4071:
4072: Return the rtx that X translates into; usually X, but modified. */
4073:
4074: void
4075: subst_reloads ()
4076: {
4077: register int i;
4078:
4079: for (i = 0; i < n_replacements; i++)
4080: {
4081: register struct replacement *r = &replacements[i];
4082: register rtx reloadreg = reload_reg_rtx[r->what];
4083: if (reloadreg)
4084: {
4085: /* Encapsulate RELOADREG so its machine mode matches what
4086: used to be there. */
4087: if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode)
4088: reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg));
4089:
4090: /* If we are putting this into a SUBREG and RELOADREG is a
4091: SUBREG, we would be making nested SUBREGs, so we have to fix
4092: this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */
4093:
4094: if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG)
4095: {
4096: if (GET_MODE (*r->subreg_loc)
4097: == GET_MODE (SUBREG_REG (reloadreg)))
4098: *r->subreg_loc = SUBREG_REG (reloadreg);
4099: else
4100: {
4101: *r->where = SUBREG_REG (reloadreg);
4102: SUBREG_WORD (*r->subreg_loc) += SUBREG_WORD (reloadreg);
4103: }
4104: }
4105: else
4106: *r->where = reloadreg;
4107: }
4108: /* If reload got no reg and isn't optional, something's wrong. */
4109: else if (! reload_optional[r->what])
4110: abort ();
4111: }
4112: }
4113:
4114: /* Make a copy of any replacements being done into X and move those copies
4115: to locations in Y, a copy of X. We only look at the highest level of
4116: the RTL. */
4117:
4118: void
4119: copy_replacements (x, y)
4120: rtx x;
4121: rtx y;
4122: {
4123: int i, j;
4124: enum rtx_code code = GET_CODE (x);
4125: char *fmt = GET_RTX_FORMAT (code);
4126: struct replacement *r;
4127:
4128: /* We can't support X being a SUBREG because we might then need to know its
4129: location if something inside it was replaced. */
4130: if (code == SUBREG)
4131: abort ();
4132:
4133: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4134: if (fmt[i] == 'e')
4135: for (j = 0; j < n_replacements; j++)
4136: {
4137: if (replacements[j].subreg_loc == &XEXP (x, i))
4138: {
4139: r = &replacements[n_replacements++];
4140: r->where = replacements[j].where;
4141: r->subreg_loc = &XEXP (y, i);
4142: r->what = replacements[j].what;
4143: r->mode = replacements[j].mode;
4144: }
4145: else if (replacements[j].where == &XEXP (x, i))
4146: {
4147: r = &replacements[n_replacements++];
4148: r->where = &XEXP (y, i);
4149: r->subreg_loc = 0;
4150: r->what = replacements[j].what;
4151: r->mode = replacements[j].mode;
4152: }
4153: }
4154: }
4155:
4156: /* Return nonzero if register in range [REGNO, ENDREGNO)
4157: appears either explicitly or implicitly in X
4158: other than being stored into.
4159:
4160: References contained within the substructure at LOC do not count.
4161: LOC may be zero, meaning don't ignore anything.
4162:
4163: This is similar to refers_to_regno_p in rtlanal.c except that we
4164: look at equivalences for pseudos that didn't get hard registers. */
4165:
4166: int
4167: refers_to_regno_for_reload_p (regno, endregno, x, loc)
4168: int regno, endregno;
4169: rtx x;
4170: rtx *loc;
4171: {
4172: register int i;
4173: register RTX_CODE code;
4174: register char *fmt;
4175:
4176: if (x == 0)
4177: return 0;
4178:
4179: repeat:
4180: code = GET_CODE (x);
4181:
4182: switch (code)
4183: {
4184: case REG:
4185: i = REGNO (x);
4186:
4187: if (i >= FIRST_PSEUDO_REGISTER && reg_renumber[i] == -1
4188: && ((reg_equiv_address[i]
4189: && refers_to_regno_for_reload_p (regno, endregno,
4190: reg_equiv_address[i], 0))
4191: || (reg_equiv_mem[i]
4192: && refers_to_regno_for_reload_p (regno, endregno,
4193: XEXP (reg_equiv_mem[i], 0),
4194: 0))))
4195: return 1;
4196:
4197: return (endregno > i
4198: && regno < i + (i < FIRST_PSEUDO_REGISTER
4199: ? HARD_REGNO_NREGS (i, GET_MODE (x))
4200: : 1));
4201:
4202: case SUBREG:
4203: /* If this is a SUBREG of a hard reg, we can see exactly which
4204: registers are being modified. Otherwise, handle normally. */
4205: if (GET_CODE (SUBREG_REG (x)) == REG
4206: && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
4207: {
4208: int inner_regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x);
4209: int inner_endregno
4210: = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER
4211: ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
4212:
4213: return endregno > inner_regno && regno < inner_endregno;
4214: }
4215: break;
4216:
4217: case CLOBBER:
4218: case SET:
4219: if (&SET_DEST (x) != loc
4220: /* Note setting a SUBREG counts as referring to the REG it is in for
4221: a pseudo but not for hard registers since we can
4222: treat each word individually. */
4223: && ((GET_CODE (SET_DEST (x)) == SUBREG
4224: && loc != &SUBREG_REG (SET_DEST (x))
4225: && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
4226: && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
4227: && refers_to_regno_for_reload_p (regno, endregno,
4228: SUBREG_REG (SET_DEST (x)),
4229: loc))
4230: || (GET_CODE (SET_DEST (x)) != REG
4231: && refers_to_regno_for_reload_p (regno, endregno,
4232: SET_DEST (x), loc))))
4233: return 1;
4234:
4235: if (code == CLOBBER || loc == &SET_SRC (x))
4236: return 0;
4237: x = SET_SRC (x);
4238: goto repeat;
4239: }
4240:
4241: /* X does not match, so try its subexpressions. */
4242:
4243: fmt = GET_RTX_FORMAT (code);
4244: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4245: {
4246: if (fmt[i] == 'e' && loc != &XEXP (x, i))
4247: {
4248: if (i == 0)
4249: {
4250: x = XEXP (x, 0);
4251: goto repeat;
4252: }
4253: else
4254: if (refers_to_regno_for_reload_p (regno, endregno,
4255: XEXP (x, i), loc))
4256: return 1;
4257: }
4258: else if (fmt[i] == 'E')
4259: {
4260: register int j;
4261: for (j = XVECLEN (x, i) - 1; j >=0; j--)
4262: if (loc != &XVECEXP (x, i, j)
4263: && refers_to_regno_for_reload_p (regno, endregno,
4264: XVECEXP (x, i, j), loc))
4265: return 1;
4266: }
4267: }
4268: return 0;
4269: }
4270:
4271: #if 0
4272:
4273: /* [[This function is currently obsolete, now that volatility
4274: is represented by a special bit `volatil' so VOLATILE is never used;
4275: and UNCHANGING has never been brought into use.]]
4276:
4277: Alter X by eliminating all VOLATILE and UNCHANGING expressions.
4278: Each of them is replaced by its operand.
4279: Thus, (PLUS (VOLATILE (MEM (REG 5))) (CONST_INT 4))
4280: becomes (PLUS (MEM (REG 5)) (CONST_INT 4)).
4281:
4282: If X is itself a VOLATILE expression,
4283: we return the expression that should replace it
4284: but we do not modify X. */
4285:
4286: static rtx
4287: forget_volatility (x)
4288: register rtx x;
4289: {
4290: enum rtx_code code = GET_CODE (x);
4291: register char *fmt;
4292: register int i;
4293: register rtx value = 0;
4294:
4295: switch (code)
4296: {
4297: case LABEL_REF:
4298: case SYMBOL_REF:
4299: case CONST_INT:
4300: case CONST_DOUBLE:
4301: case CONST:
4302: case REG:
4303: case CC0:
4304: case PC:
4305: return x;
4306:
4307: case VOLATILE:
4308: case UNCHANGING:
4309: return XEXP (x, 0);
4310: }
4311:
4312: fmt = GET_RTX_FORMAT (code);
4313: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4314: {
4315: if (fmt[i] == 'e')
4316: XEXP (x, i) = forget_volatility (XEXP (x, i));
4317: if (fmt[i] == 'E')
4318: {
4319: register int j;
4320: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4321: XVECEXP (x, i, j) = forget_volatility (XVECEXP (x, i, j));
4322: }
4323: }
4324:
4325: return x;
4326: }
4327:
4328: #endif
4329:
4330: /* Check the insns before INSN to see if there is a suitable register
4331: containing the same value as GOAL.
4332: If OTHER is -1, look for a register in class CLASS.
4333: Otherwise, just see if register number OTHER shares GOAL's value.
4334:
4335: Return an rtx for the register found, or zero if none is found.
4336:
4337: If RELOAD_REG_P is (short *)1,
4338: we reject any hard reg that appears in reload_reg_rtx
4339: because such a hard reg is also needed coming into this insn.
4340:
4341: If RELOAD_REG_P is any other nonzero value,
4342: it is a vector indexed by hard reg number
4343: and we reject any hard reg whose element in the vector is nonnegative
4344: as well as any that appears in reload_reg_rtx.
4345:
4346: If GOAL is zero, then GOALREG is a register number; we look
4347: for an equivalent for that register.
4348:
4349: MODE is the machine mode of the value we want an equivalence for.
4350: If GOAL is nonzero and not VOIDmode, then it must have mode MODE.
4351:
4352: This function is used by jump.c as well as in the reload pass.
4353:
4354: If GOAL is the sum of the stack pointer and a constant, we treat it
4355: as if it were a constant except that sp is required to be unchanging. */
4356:
4357: rtx
4358: find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode)
4359: register rtx goal;
4360: rtx insn;
4361: enum reg_class class;
4362: register int other;
4363: short *reload_reg_p;
4364: int goalreg;
4365: enum machine_mode mode;
4366: {
4367: register rtx p = insn;
4368: rtx valtry, value, where;
4369: register rtx pat;
4370: register int regno = -1;
4371: int valueno;
4372: int goal_mem = 0;
4373: int goal_const = 0;
4374: int goal_mem_addr_varies = 0;
4375: int need_stable_sp = 0;
4376: int nregs;
4377: int valuenregs;
4378:
4379: if (goal == 0)
4380: regno = goalreg;
4381: else if (GET_CODE (goal) == REG)
4382: regno = REGNO (goal);
4383: else if (GET_CODE (goal) == MEM)
4384: {
4385: enum rtx_code code = GET_CODE (XEXP (goal, 0));
4386: if (MEM_VOLATILE_P (goal))
4387: return 0;
4388: if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT)
4389: return 0;
4390: /* An address with side effects must be reexecuted. */
4391: switch (code)
4392: {
4393: case POST_INC:
4394: case PRE_INC:
4395: case POST_DEC:
4396: case PRE_DEC:
4397: return 0;
4398: }
4399: goal_mem = 1;
4400: }
4401: else if (CONSTANT_P (goal))
4402: goal_const = 1;
4403: else if (GET_CODE (goal) == PLUS
4404: && XEXP (goal, 0) == stack_pointer_rtx
4405: && CONSTANT_P (XEXP (goal, 1)))
4406: goal_const = need_stable_sp = 1;
4407: else
4408: return 0;
4409:
4410: /* On some machines, certain regs must always be rejected
4411: because they don't behave the way ordinary registers do. */
4412:
4413: #ifdef OVERLAPPING_REGNO_P
4414: if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4415: && OVERLAPPING_REGNO_P (regno))
4416: return 0;
4417: #endif
4418:
4419: /* Scan insns back from INSN, looking for one that copies
4420: a value into or out of GOAL.
4421: Stop and give up if we reach a label. */
4422:
4423: while (1)
4424: {
4425: p = PREV_INSN (p);
4426: if (p == 0 || GET_CODE (p) == CODE_LABEL)
4427: return 0;
4428: if (GET_CODE (p) == INSN
4429: /* If we don't want spill regs ... */
4430: && (! (reload_reg_p != 0 && reload_reg_p != (short *)1)
4431: /* ... then ignore insns introduced by reload; they aren't useful
4432: and can cause results in reload_as_needed to be different
4433: from what they were when calculating the need for spills.
4434: If we notice an input-reload insn here, we will reject it below,
4435: but it might hide a usable equivalent. That makes bad code.
4436: It may even abort: perhaps no reg was spilled for this insn
4437: because it was assumed we would find that equivalent. */
4438: || INSN_UID (p) < reload_first_uid))
4439: {
4440: pat = single_set (p);
4441: /* First check for something that sets some reg equal to GOAL. */
4442: if (pat != 0
4443: && ((regno >= 0
4444: && true_regnum (SET_SRC (pat)) == regno
4445: && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
4446: ||
4447: (regno >= 0
4448: && true_regnum (SET_DEST (pat)) == regno
4449: && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0)
4450: ||
4451: (goal_const && rtx_equal_p (SET_SRC (pat), goal)
4452: && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
4453: || (goal_mem
4454: && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0
4455: && rtx_renumbered_equal_p (goal, SET_SRC (pat)))
4456: || (goal_mem
4457: && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0
4458: && rtx_renumbered_equal_p (goal, SET_DEST (pat)))))
4459: if (other >= 0
4460: ? valueno == other
4461: : ((unsigned) valueno < FIRST_PSEUDO_REGISTER
4462: && TEST_HARD_REG_BIT (reg_class_contents[(int) class],
4463: valueno)))
4464: {
4465: value = valtry;
4466: where = p;
4467: break;
4468: }
4469: }
4470: }
4471:
4472: /* We found a previous insn copying GOAL into a suitable other reg VALUE
4473: (or copying VALUE into GOAL, if GOAL is also a register).
4474: Now verify that VALUE is really valid. */
4475:
4476: /* VALUENO is the register number of VALUE; a hard register. */
4477:
4478: /* Don't try to re-use something that is killed in this insn. We want
4479: to be able to trust REG_UNUSED notes. */
4480: if (find_reg_note (where, REG_UNUSED, value))
4481: return 0;
4482:
4483: /* If we propose to get the value from the stack pointer or if GOAL is
4484: a MEM based on the stack pointer, we need a stable SP. */
4485: if (valueno == STACK_POINTER_REGNUM
4486: || (goal_mem && reg_overlap_mentioned_p (stack_pointer_rtx, goal)))
4487: need_stable_sp = 1;
4488:
4489: /* Reject VALUE if the copy-insn moved the wrong sort of datum. */
4490: if (GET_MODE (value) != mode)
4491: return 0;
4492:
4493: /* Reject VALUE if it was loaded from GOAL
4494: and is also a register that appears in the address of GOAL. */
4495:
4496: if (goal_mem && value == SET_DEST (PATTERN (where))
4497: && refers_to_regno_p (valueno,
4498: valueno + HARD_REGNO_NREGS (valueno, mode),
4499: goal, 0))
4500: return 0;
4501:
4502: /* Reject registers that overlap GOAL. */
4503:
4504: if (!goal_mem && !goal_const
4505: && regno + HARD_REGNO_NREGS (regno, mode) > valueno
4506: && regno < valueno + HARD_REGNO_NREGS (valueno, mode))
4507: return 0;
4508:
4509: /* Reject VALUE if it is one of the regs reserved for reloads.
4510: Reload1 knows how to reuse them anyway, and it would get
4511: confused if we allocated one without its knowledge.
4512: (Now that insns introduced by reload are ignored above,
4513: this case shouldn't happen, but I'm not positive.) */
4514:
4515: if (reload_reg_p != 0 && reload_reg_p != (short *)1
4516: && reload_reg_p[valueno] >= 0)
4517: return 0;
4518:
4519: /* On some machines, certain regs must always be rejected
4520: because they don't behave the way ordinary registers do. */
4521:
4522: #ifdef OVERLAPPING_REGNO_P
4523: if (OVERLAPPING_REGNO_P (valueno))
4524: return 0;
4525: #endif
4526:
4527: nregs = HARD_REGNO_NREGS (regno, mode);
4528: valuenregs = HARD_REGNO_NREGS (valueno, mode);
4529:
4530: /* Reject VALUE if it is a register being used for an input reload
4531: even if it is not one of those reserved. */
4532:
4533: if (reload_reg_p != 0)
4534: {
4535: int i;
4536: for (i = 0; i < n_reloads; i++)
4537: if (reload_reg_rtx[i] != 0 && reload_in[i])
4538: {
4539: int regno1 = REGNO (reload_reg_rtx[i]);
4540: int nregs1 = HARD_REGNO_NREGS (regno1,
4541: GET_MODE (reload_reg_rtx[i]));
4542: if (regno1 < valueno + valuenregs
4543: && regno1 + nregs1 > valueno)
4544: return 0;
4545: }
4546: }
4547:
4548: if (goal_mem)
4549: goal_mem_addr_varies = rtx_addr_varies_p (goal);
4550:
4551: /* Now verify that the values of GOAL and VALUE remain unaltered
4552: until INSN is reached. */
4553:
4554: p = insn;
4555: while (1)
4556: {
4557: p = PREV_INSN (p);
4558: if (p == where)
4559: return value;
4560:
4561: /* Don't trust the conversion past a function call
4562: if either of the two is in a call-clobbered register, or memory. */
4563: if (GET_CODE (p) == CALL_INSN
4564: && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4565: && call_used_regs[regno])
4566: ||
4567: (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER
4568: && call_used_regs[valueno])
4569: ||
4570: goal_mem
4571: || need_stable_sp))
4572: return 0;
4573:
4574: #ifdef INSN_CLOBBERS_REGNO_P
4575: if ((valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER
4576: && INSN_CLOBBERS_REGNO_P (p, valueno))
4577: || (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4578: && INSN_CLOBBERS_REGNO_P (p, regno)))
4579: return 0;
4580: #endif
4581:
4582: if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
4583: {
4584: /* If this insn P stores in either GOAL or VALUE, return 0.
4585: If GOAL is a memory ref and this insn writes memory, return 0.
4586: If GOAL is a memory ref and its address is not constant,
4587: and this insn P changes a register used in GOAL, return 0. */
4588:
4589: pat = PATTERN (p);
4590: if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
4591: {
4592: register rtx dest = SET_DEST (pat);
4593: while (GET_CODE (dest) == SUBREG
4594: || GET_CODE (dest) == ZERO_EXTRACT
4595: || GET_CODE (dest) == SIGN_EXTRACT
4596: || GET_CODE (dest) == STRICT_LOW_PART)
4597: dest = XEXP (dest, 0);
4598: if (GET_CODE (dest) == REG)
4599: {
4600: register int xregno = REGNO (dest);
4601: int xnregs;
4602: if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
4603: xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
4604: else
4605: xnregs = 1;
4606: if (xregno < regno + nregs && xregno + xnregs > regno)
4607: return 0;
4608: if (xregno < valueno + valuenregs
4609: && xregno + xnregs > valueno)
4610: return 0;
4611: if (goal_mem_addr_varies
4612: && reg_overlap_mentioned_p (dest, goal))
4613: return 0;
4614: }
4615: else if (goal_mem && GET_CODE (dest) == MEM
4616: && ! push_operand (dest, GET_MODE (dest)))
4617: return 0;
4618: else if (need_stable_sp && push_operand (dest, GET_MODE (dest)))
4619: return 0;
4620: }
4621: else if (GET_CODE (pat) == PARALLEL)
4622: {
4623: register int i;
4624: for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
4625: {
4626: register rtx v1 = XVECEXP (pat, 0, i);
4627: if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER)
4628: {
4629: register rtx dest = SET_DEST (v1);
4630: while (GET_CODE (dest) == SUBREG
4631: || GET_CODE (dest) == ZERO_EXTRACT
4632: || GET_CODE (dest) == SIGN_EXTRACT
4633: || GET_CODE (dest) == STRICT_LOW_PART)
4634: dest = XEXP (dest, 0);
4635: if (GET_CODE (dest) == REG)
4636: {
4637: register int xregno = REGNO (dest);
4638: int xnregs;
4639: if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
4640: xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
4641: else
4642: xnregs = 1;
4643: if (xregno < regno + nregs
4644: && xregno + xnregs > regno)
4645: return 0;
4646: if (xregno < valueno + valuenregs
4647: && xregno + xnregs > valueno)
4648: return 0;
4649: if (goal_mem_addr_varies
4650: && reg_overlap_mentioned_p (dest, goal))
4651: return 0;
4652: }
4653: else if (goal_mem && GET_CODE (dest) == MEM
4654: && ! push_operand (dest, GET_MODE (dest)))
4655: return 0;
4656: else if (need_stable_sp
4657: && push_operand (dest, GET_MODE (dest)))
4658: return 0;
4659: }
4660: }
4661: }
4662:
4663: #ifdef AUTO_INC_DEC
4664: /* If this insn auto-increments or auto-decrements
4665: either regno or valueno, return 0 now.
4666: If GOAL is a memory ref and its address is not constant,
4667: and this insn P increments a register used in GOAL, return 0. */
4668: {
4669: register rtx link;
4670:
4671: for (link = REG_NOTES (p); link; link = XEXP (link, 1))
4672: if (REG_NOTE_KIND (link) == REG_INC
4673: && GET_CODE (XEXP (link, 0)) == REG)
4674: {
4675: register int incno = REGNO (XEXP (link, 0));
4676: if (incno < regno + nregs && incno >= regno)
4677: return 0;
4678: if (incno < valueno + valuenregs && incno >= valueno)
4679: return 0;
4680: if (goal_mem_addr_varies
4681: && reg_overlap_mentioned_p (XEXP (link, 0), goal))
4682: return 0;
4683: }
4684: }
4685: #endif
4686: }
4687: }
4688: }
4689:
4690: /* Find a place where INCED appears in an increment or decrement operator
4691: within X, and return the amount INCED is incremented or decremented by.
4692: The value is always positive. */
4693:
4694: static int
4695: find_inc_amount (x, inced)
4696: rtx x, inced;
4697: {
4698: register enum rtx_code code = GET_CODE (x);
4699: register char *fmt;
4700: register int i;
4701:
4702: if (code == MEM)
4703: {
4704: register rtx addr = XEXP (x, 0);
4705: if ((GET_CODE (addr) == PRE_DEC
4706: || GET_CODE (addr) == POST_DEC
4707: || GET_CODE (addr) == PRE_INC
4708: || GET_CODE (addr) == POST_INC)
4709: && XEXP (addr, 0) == inced)
4710: return GET_MODE_SIZE (GET_MODE (x));
4711: }
4712:
4713: fmt = GET_RTX_FORMAT (code);
4714: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4715: {
4716: if (fmt[i] == 'e')
4717: {
4718: register int tem = find_inc_amount (XEXP (x, i), inced);
4719: if (tem != 0)
4720: return tem;
4721: }
4722: if (fmt[i] == 'E')
4723: {
4724: register int j;
4725: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4726: {
4727: register int tem = find_inc_amount (XVECEXP (x, i, j), inced);
4728: if (tem != 0)
4729: return tem;
4730: }
4731: }
4732: }
4733:
4734: return 0;
4735: }
4736:
4737: /* Return 1 if register REGNO is the subject of a clobber in insn INSN. */
4738:
4739: int
4740: regno_clobbered_p (regno, insn)
4741: int regno;
4742: rtx insn;
4743: {
4744: if (GET_CODE (PATTERN (insn)) == CLOBBER
4745: && GET_CODE (XEXP (PATTERN (insn), 0)) == REG)
4746: return REGNO (XEXP (PATTERN (insn), 0)) == regno;
4747:
4748: if (GET_CODE (PATTERN (insn)) == PARALLEL)
4749: {
4750: int i = XVECLEN (PATTERN (insn), 0) - 1;
4751:
4752: for (; i >= 0; i--)
4753: {
4754: rtx elt = XVECEXP (PATTERN (insn), 0, i);
4755: if (GET_CODE (elt) == CLOBBER && GET_CODE (XEXP (elt, 0)) == REG
4756: && REGNO (XEXP (elt, 0)) == regno)
4757: return 1;
4758: }
4759: }
4760:
4761: return 0;
4762: }
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