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1.1 root 1: /* Search an insn for pseudo regs that must be in hard regs and are not.
2: Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: /* This file contains subroutines used only from the file reload1.c.
22: It knows how to scan one insn for operands and values
23: that need to be copied into registers to make valid code.
24: It also finds other operands and values which are valid
25: but for which equivalent values in registers exist and
26: ought to be used instead.
27:
28: Before processing the first insn of the function, call `init_reload'.
29:
30: To scan an insn, call `find_reloads'. This does two things:
31: 1. sets up tables describing which values must be reloaded
32: for this insn, and what kind of hard regs they must be reloaded into;
33: 2. optionally record the locations where those values appear in
34: the data, so they can be replaced properly later.
35: This is done only if the second arg to `find_reloads' is nonzero.
36:
37: The third arg to `find_reloads' specifies the number of levels
38: of indirect addressing supported by the machine. If it is zero,
39: indirect addressing is not valid. If it is one, (MEM (REG n))
40: is valid even if (REG n) did not get a hard register; if it is two,
41: (MEM (MEM (REG n))) is also valid even if (REG n) did not get a
42: hard register, and similarly for higher values.
43:
44: Then you must choose the hard regs to reload those pseudo regs into,
45: and generate appropriate load insns before this insn and perhaps
46: also store insns after this insn. Set up the array `reload_reg_rtx'
47: to contain the REG rtx's for the registers you used. In some
48: cases `find_reloads' will return a nonzero value in `reload_reg_rtx'
49: for certain reloads. Then that tells you which register to use,
50: so you do not need to allocate one. But you still do need to add extra
51: instructions to copy the value into and out of that register.
52:
53: Finally you must call `subst_reloads' to substitute the reload reg rtx's
54: into the locations already recorded.
55:
56: NOTE SIDE EFFECTS:
57:
58: find_reloads can alter the operands of the instruction it is called on.
59:
60: 1. Two operands of any sort may be interchanged, if they are in a
61: commutative instruction.
62: This happens only if find_reloads thinks the instruction will compile
63: better that way.
64:
65: 2. Pseudo-registers that are equivalent to constants are replaced
66: with those constants if they are not in hard registers.
67:
68: 1 happens every time find_reloads is called.
69: 2 happens only when REPLACE is 1, which is only when
70: actually doing the reloads, not when just counting them.
71:
72:
73: Using a reload register for several reloads in one insn:
74:
75: When an insn has reloads, it is considered as having three parts:
76: the input reloads, the insn itself after reloading, and the output reloads.
77: Reloads of values used in memory addresses are often needed for only one part.
78:
79: When this is so, reload_when_needed records which part needs the reload.
80: Two reloads for different parts of the insn can share the same reload
81: register.
82:
83: When a reload is used for addresses in multiple parts, or when it is
84: an ordinary operand, it is classified as RELOAD_OTHER, and cannot share
85: a register with any other reload. */
86:
87: #define REG_OK_STRICT
88:
89: #include "config.h"
90: #include "rtl.h"
91: #include "insn-config.h"
92: #include "insn-codes.h"
93: #include "recog.h"
94: #include "reload.h"
95: #include "regs.h"
96: #include "hard-reg-set.h"
97: #include "flags.h"
98: #include "real.h"
99:
100: #ifndef REGISTER_MOVE_COST
101: #define REGISTER_MOVE_COST(x, y) 2
102: #endif
103:
104: /* The variables set up by `find_reloads' are:
105:
106: n_reloads number of distinct reloads needed; max reload # + 1
107: tables indexed by reload number
108: reload_in rtx for value to reload from
109: reload_out rtx for where to store reload-reg afterward if nec
110: (often the same as reload_in)
111: reload_reg_class enum reg_class, saying what regs to reload into
112: reload_inmode enum machine_mode; mode this operand should have
113: when reloaded, on input.
114: reload_outmode enum machine_mode; mode this operand should have
115: when reloaded, on output.
116: reload_strict_low char; currently always zero; used to mean that this
117: reload is inside a STRICT_LOW_PART, but we don't
118: need to know this anymore.
119: reload_optional char, nonzero for an optional reload.
120: Optional reloads are ignored unless the
121: value is already sitting in a register.
122: reload_inc int, positive amount to increment or decrement by if
123: reload_in is a PRE_DEC, PRE_INC, POST_DEC, POST_INC.
124: Ignored otherwise (don't assume it is zero).
125: reload_in_reg rtx. A reg for which reload_in is the equivalent.
126: If reload_in is a symbol_ref which came from
127: reg_equiv_constant, then this is the pseudo
128: which has that symbol_ref as equivalent.
129: reload_reg_rtx rtx. This is the register to reload into.
130: If it is zero when `find_reloads' returns,
131: you must find a suitable register in the class
132: specified by reload_reg_class, and store here
133: an rtx for that register with mode from
134: reload_inmode or reload_outmode.
135: reload_nocombine char, nonzero if this reload shouldn't be
136: combined with another reload.
137: reload_needed_for rtx, operand this reload is needed for address of.
138: 0 means it isn't needed for addressing.
139: reload_needed_for_multiple
140: int, 1 if this reload needed for more than one thing.
141: reload_when_needed enum, classifies reload as needed either for
142: addressing an input reload, addressing an output,
143: for addressing a non-reloaded mem ref,
144: or for unspecified purposes (i.e., more than one
145: of the above).
146: reload_secondary_reload int, gives the reload number of a secondary
147: reload, when needed; otherwise -1
148: reload_secondary_p int, 1 if this is a secondary register for one
149: or more reloads.
150: reload_secondary_icode enum insn_code, if a secondary reload is required,
151: gives the INSN_CODE that uses the secondary
152: reload as a scratch register, or CODE_FOR_nothing
153: if the secondary reload register is to be an
154: intermediate register. */
155: int n_reloads;
156:
157: rtx reload_in[MAX_RELOADS];
158: rtx reload_out[MAX_RELOADS];
159: enum reg_class reload_reg_class[MAX_RELOADS];
160: enum machine_mode reload_inmode[MAX_RELOADS];
161: enum machine_mode reload_outmode[MAX_RELOADS];
162: char reload_strict_low[MAX_RELOADS];
163: rtx reload_reg_rtx[MAX_RELOADS];
164: char reload_optional[MAX_RELOADS];
165: int reload_inc[MAX_RELOADS];
166: rtx reload_in_reg[MAX_RELOADS];
167: char reload_nocombine[MAX_RELOADS];
168: int reload_needed_for_multiple[MAX_RELOADS];
169: rtx reload_needed_for[MAX_RELOADS];
170: enum reload_when_needed reload_when_needed[MAX_RELOADS];
171: int reload_secondary_reload[MAX_RELOADS];
172: int reload_secondary_p[MAX_RELOADS];
173: enum insn_code reload_secondary_icode[MAX_RELOADS];
174:
175: /* All the "earlyclobber" operands of the current insn
176: are recorded here. */
177: int n_earlyclobbers;
178: rtx reload_earlyclobbers[MAX_RECOG_OPERANDS];
179:
180: /* Replacing reloads.
181:
182: If `replace_reloads' is nonzero, then as each reload is recorded
183: an entry is made for it in the table `replacements'.
184: Then later `subst_reloads' can look through that table and
185: perform all the replacements needed. */
186:
187: /* Nonzero means record the places to replace. */
188: static int replace_reloads;
189:
190: /* Each replacement is recorded with a structure like this. */
191: struct replacement
192: {
193: rtx *where; /* Location to store in */
194: rtx *subreg_loc; /* Location of SUBREG if WHERE is inside
195: a SUBREG; 0 otherwise. */
196: int what; /* which reload this is for */
197: enum machine_mode mode; /* mode it must have */
198: };
199:
200: static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)];
201:
202: /* Number of replacements currently recorded. */
203: static int n_replacements;
204:
205: /* MEM-rtx's created for pseudo-regs in stack slots not directly addressable;
206: (see reg_equiv_address). */
207: static rtx memlocs[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)];
208: static int n_memlocs;
209:
210: /* The instruction we are doing reloads for;
211: so we can test whether a register dies in it. */
212: static rtx this_insn;
213:
214: /* Nonzero if this instruction is a user-specified asm with operands. */
215: static int this_insn_is_asm;
216:
217: /* If hard_regs_live_known is nonzero,
218: we can tell which hard regs are currently live,
219: at least enough to succeed in choosing dummy reloads. */
220: static int hard_regs_live_known;
221:
222: /* Indexed by hard reg number,
223: element is nonegative if hard reg has been spilled.
224: This vector is passed to `find_reloads' as an argument
225: and is not changed here. */
226: static short *static_reload_reg_p;
227:
228: /* Set to 1 in subst_reg_equivs if it changes anything. */
229: static int subst_reg_equivs_changed;
230:
231: /* On return from push_reload, holds the reload-number for the OUT
232: operand, which can be different for that from the input operand. */
233: static int output_reloadnum;
234:
235: static int alternative_allows_memconst ();
236: static rtx find_dummy_reload ();
237: static rtx find_reloads_toplev ();
238: static int find_reloads_address ();
239: static int find_reloads_address_1 ();
240: static void find_reloads_address_part ();
241: static int hard_reg_set_here_p ();
242: /* static rtx forget_volatility (); */
243: static rtx subst_reg_equivs ();
244: static rtx subst_indexed_address ();
245: rtx find_equiv_reg ();
246: static int find_inc_amount ();
247:
248: #ifdef HAVE_SECONDARY_RELOADS
249:
250: /* Determine if any secondary reloads are needed for loading (if IN_P is
251: non-zero) or storing (if IN_P is zero) X to or from a reload register of
252: register class RELOAD_CLASS in mode RELOAD_MODE.
253:
254: Return the register class of a secondary reload register, or NO_REGS if
255: none. *PMODE is set to the mode that the register is required in.
256: If the reload register is needed as a scratch register instead of an
257: intermediate register, *PICODE is set to the insn_code of the insn to be
258: used to load or store the primary reload register; otherwise *PICODE
259: is set to CODE_FOR_nothing.
260:
261: In some cases (such as storing MQ into an external memory location on
262: the RT), both an intermediate register and a scratch register. In that
263: case, *PICODE is set to CODE_FOR_nothing, the class for the intermediate
264: register is returned, and the *PTERTIARY_... variables are set to describe
265: the scratch register. */
266:
267: static enum reg_class
268: find_secondary_reload (x, reload_class, reload_mode, in_p, picode, pmode,
269: ptertiary_class, ptertiary_icode, ptertiary_mode)
270: rtx x;
271: enum reg_class reload_class;
272: enum machine_mode reload_mode;
273: int in_p;
274: enum insn_code *picode;
275: enum machine_mode *pmode;
276: enum reg_class *ptertiary_class;
277: enum insn_code *ptertiary_icode;
278: enum machine_mode *ptertiary_mode;
279: {
280: enum reg_class class = NO_REGS;
281: enum machine_mode mode = reload_mode;
282: enum insn_code icode = CODE_FOR_nothing;
283: enum reg_class t_class = NO_REGS;
284: enum machine_mode t_mode = VOIDmode;
285: enum insn_code t_icode = CODE_FOR_nothing;
286:
1.1.1.2 ! root 287: /* If X is a pseudo-register that has an equivalent MEM (actually, if it
! 288: is still a pseudo-register by now, it *must* have an equivalent MEM
! 289: but we don't want to assume that), use that equivalent when seeing if
! 290: a secondary reload is needed since whether or not a reload is needed
! 291: might be sensitive to the form of the MEM. */
! 292:
! 293: if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER
! 294: && reg_equiv_mem[REGNO (x)] != 0)
! 295: x = reg_equiv_mem[REGNO (x)];
! 296:
1.1 root 297: #ifdef SECONDARY_INPUT_RELOAD_CLASS
298: if (in_p)
299: class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x);
300: #endif
301:
302: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
303: if (! in_p)
304: class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x);
305: #endif
306:
307: /* If we don't need any secondary registers, go away; the rest of the
308: values won't be used. */
309: if (class == NO_REGS)
310: return NO_REGS;
311:
312: /* Get a possible insn to use. If the predicate doesn't accept X, don't
313: use the insn. */
314:
315: icode = (in_p ? reload_in_optab[(int) reload_mode]
316: : reload_out_optab[(int) reload_mode]);
317:
318: if (icode != CODE_FOR_nothing
319: && insn_operand_predicate[(int) icode][in_p]
320: && (! (insn_operand_predicate[(int) icode][in_p]) (x, reload_mode)))
321: icode = CODE_FOR_nothing;
322:
323: /* If we will be using an insn, see if it can directly handle the reload
324: register we will be using. If it can, the secondary reload is for a
325: scratch register. If it can't, we will use the secondary reload for
326: an intermediate register and require a tertiary reload for the scratch
327: register. */
328:
329: if (icode != CODE_FOR_nothing)
330: {
331: /* If IN_P is non-zero, the reload register will be the output in
332: operand 0. If IN_P is zero, the reload register will be the input
333: in operand 1. Outputs should have an initial "=", which we must
334: skip. */
335:
1.1.1.2 ! root 336: char insn_letter = insn_operand_constraint[(int) icode][!in_p][in_p];
1.1 root 337: enum reg_class insn_class
1.1.1.2 ! root 338: = (insn_letter == 'r' ? GENERAL_REGS
! 339: : REG_CLASS_FROM_LETTER (insn_letter));
1.1 root 340:
341: if (insn_class == NO_REGS
342: || (in_p && insn_operand_constraint[(int) icode][!in_p][0] != '=')
343: /* The scratch register's constraint must start with "=&". */
344: || insn_operand_constraint[(int) icode][2][0] != '='
345: || insn_operand_constraint[(int) icode][2][1] != '&')
346: abort ();
347:
348: if (reg_class_subset_p (reload_class, insn_class))
349: mode = insn_operand_mode[(int) icode][2];
350: else
351: {
1.1.1.2 ! root 352: char t_letter = insn_operand_constraint[(int) icode][2][2];
1.1 root 353: class = insn_class;
354: t_mode = insn_operand_mode[(int) icode][2];
1.1.1.2 ! root 355: t_class = (t_letter == 'r' ? GENERAL_REGS
! 356: : REG_CLASS_FROM_LETTER (t_letter));
1.1 root 357: t_icode = icode;
358: icode = CODE_FOR_nothing;
359: }
360: }
361:
362: *pmode = mode;
363: *picode = icode;
364: *ptertiary_class = t_class;
365: *ptertiary_mode = t_mode;
366: *ptertiary_icode = t_icode;
367:
368: return class;
369: }
370: #endif /* HAVE_SECONDARY_RELOADS */
371:
372: /* Record one (sometimes two) reload that needs to be performed.
373: IN is an rtx saying where the data are to be found before this instruction.
374: OUT says where they must be stored after the instruction.
375: (IN is zero for data not read, and OUT is zero for data not written.)
376: INLOC and OUTLOC point to the places in the instructions where
377: IN and OUT were found.
378: CLASS is a register class required for the reloaded data.
379: INMODE is the machine mode that the instruction requires
380: for the reg that replaces IN and OUTMODE is likewise for OUT.
381:
382: If IN is zero, then OUT's location and mode should be passed as
383: INLOC and INMODE.
384:
385: STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx.
386:
387: OPTIONAL nonzero means this reload does not need to be performed:
388: it can be discarded if that is more convenient.
389:
390: The return value is the reload-number for this reload.
391:
392: If both IN and OUT are nonzero, in some rare cases we might
393: want to make two separate reloads. (Actually we never do this now.)
394: Therefore, the reload-number for OUT is stored in
395: output_reloadnum when we return; the return value applies to IN.
396: Usually (presently always), when IN and OUT are nonzero,
397: the two reload-numbers are equal, but the caller should be careful to
398: distinguish them. */
399:
400: static int
401: push_reload (in, out, inloc, outloc, class,
402: inmode, outmode, strict_low, optional, needed_for)
403: register rtx in, out;
404: rtx *inloc, *outloc;
405: enum reg_class class;
406: enum machine_mode inmode, outmode;
407: int strict_low;
408: int optional;
409: rtx needed_for;
410: {
411: register int i;
412: int dont_share = 0;
413: rtx *in_subreg_loc = 0, *out_subreg_loc = 0;
414: int secondary_reload = -1;
415: enum insn_code secondary_icode = CODE_FOR_nothing;
416:
417: /* Compare two RTX's. */
418: #define MATCHES(x, y) \
419: (x == y || (x != 0 && (GET_CODE (x) == REG \
420: ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \
421: : rtx_equal_p (x, y) && ! side_effects_p (x))))
422:
423: /* INMODE and/or OUTMODE could be VOIDmode if no mode
424: has been specified for the operand. In that case,
425: use the operand's mode as the mode to reload. */
426: if (inmode == VOIDmode && in != 0)
427: inmode = GET_MODE (in);
428: if (outmode == VOIDmode && out != 0)
429: outmode = GET_MODE (out);
430:
431: /* If IN is a pseudo register everywhere-equivalent to a constant, and
432: it is not in a hard register, reload straight from the constant,
433: since we want to get rid of such pseudo registers.
434: Often this is done earlier, but not always in find_reloads_address. */
435: if (in != 0 && GET_CODE (in) == REG)
436: {
437: register int regno = REGNO (in);
438:
439: if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
440: && reg_equiv_constant[regno] != 0)
441: in = reg_equiv_constant[regno];
442: }
443:
444: /* Likewise for OUT. Of course, OUT will never be equivalent to
445: an actual constant, but it might be equivalent to a memory location
446: (in the case of a parameter). */
447: if (out != 0 && GET_CODE (out) == REG)
448: {
449: register int regno = REGNO (out);
450:
451: if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
452: && reg_equiv_constant[regno] != 0)
453: out = reg_equiv_constant[regno];
454: }
455:
456: /* If we have a read-write operand with an address side-effect,
457: change either IN or OUT so the side-effect happens only once. */
458: if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out))
459: {
460: if (GET_CODE (XEXP (in, 0)) == POST_INC
461: || GET_CODE (XEXP (in, 0)) == POST_DEC)
462: in = gen_rtx (MEM, GET_MODE (in), XEXP (XEXP (in, 0), 0));
463: if (GET_CODE (XEXP (in, 0)) == PRE_INC
464: || GET_CODE (XEXP (in, 0)) == PRE_DEC)
465: out = gen_rtx (MEM, GET_MODE (out), XEXP (XEXP (out, 0), 0));
466: }
467:
468: /* If we are reloading a (SUBREG (MEM ...) ...) or (SUBREG constant ...),
469: really reload just the inside expression in its own mode.
470: If we have (SUBREG:M1 (REG:M2 ...) ...) with M1 wider than M2 and the
471: register is a pseudo, this will become the same as the above case.
472: Do the same for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where
473: either M1 is not valid for R or M2 is wider than a word but we only
474: need one word to store an M2-sized quantity in R.
475: Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere;
476: we can't handle it here because CONST_INT does not indicate a mode.
477:
478: Similarly, we must reload the inside expression if we have a
479: STRICT_LOW_PART (presumably, in == out in the cas). */
480:
481: if (in != 0 && GET_CODE (in) == SUBREG
482: && (GET_CODE (SUBREG_REG (in)) != REG
483: || strict_low
484: || (GET_CODE (SUBREG_REG (in)) == REG
485: && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER
486: && (GET_MODE_SIZE (inmode)
487: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))))
488: || (GET_CODE (SUBREG_REG (in)) == REG
489: && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
490: && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (in)), inmode)
491: || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD
492: && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
493: > UNITS_PER_WORD)
494: && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
495: / UNITS_PER_WORD)
496: != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)),
497: GET_MODE (SUBREG_REG (in)))))))))
498: {
499: in_subreg_loc = inloc;
500: inloc = &SUBREG_REG (in);
501: in = *inloc;
502: if (GET_CODE (in) == MEM)
503: /* This is supposed to happen only for paradoxical subregs made by
504: combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */
505: if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode))
506: abort ();
507: inmode = GET_MODE (in);
508: }
509:
510: /* Similarly for paradoxical and problematical SUBREGs on the output.
511: Note that there is no reason we need worry about the previous value
512: of SUBREG_REG (out); even if wider than out,
513: storing in a subreg is entitled to clobber it all
514: (except in the case of STRICT_LOW_PART,
515: and in that case the constraint should label it input-output.) */
516: if (out != 0 && GET_CODE (out) == SUBREG
517: && (GET_CODE (SUBREG_REG (out)) != REG
518: || strict_low
519: || (GET_CODE (SUBREG_REG (out)) == REG
520: && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER
521: && (GET_MODE_SIZE (outmode)
522: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))))
523: || (GET_CODE (SUBREG_REG (out)) == REG
524: && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
525: && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (out)), outmode)
526: || (GET_MODE_SIZE (outmode) <= UNITS_PER_WORD
527: && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
528: > UNITS_PER_WORD)
529: && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
530: / UNITS_PER_WORD)
531: != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)),
532: GET_MODE (SUBREG_REG (out)))))))))
533: {
534: out_subreg_loc = outloc;
535: outloc = &SUBREG_REG (out);
536: out = *outloc;
537: if (GET_CODE (out) == MEM
538: && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode))
539: abort ();
540: outmode = GET_MODE (out);
541: }
542:
543: /* That's all we use STRICT_LOW for, so clear it. At some point,
544: we may want to get rid of reload_strict_low. */
545: strict_low = 0;
546:
547: /* If IN appears in OUT, we can't share any input-only reload for IN. */
548: if (in != 0 && out != 0 && GET_CODE (out) == MEM
549: && (GET_CODE (in) == REG || GET_CODE (in) == MEM)
550: && reg_overlap_mentioned_p (in, XEXP (out, 0)))
551: dont_share = 1;
552:
553: /* Narrow down the class of register wanted if that is
554: desirable on this machine for efficiency. */
555: if (in != 0)
556: class = PREFERRED_RELOAD_CLASS (in, class);
557:
558: /* Make sure we use a class that can handle the actual pseudo
559: inside any subreg. For example, on the 386, QImode regs
560: can appear within SImode subregs. Although GENERAL_REGS
561: can handle SImode, QImode needs a smaller class. */
562: #ifdef LIMIT_RELOAD_CLASS
563: if (in_subreg_loc)
564: class = LIMIT_RELOAD_CLASS (inmode, class);
565: else if (in != 0 && GET_CODE (in) == SUBREG)
566: class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), class);
567:
568: if (out_subreg_loc)
569: class = LIMIT_RELOAD_CLASS (outmode, class);
570: if (out != 0 && GET_CODE (out) == SUBREG)
571: class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), class);
572: #endif
573:
574: if (class == NO_REGS)
575: abort ();
576:
577: /* Verify that this class is at least possible for the mode that
578: is specified. */
579: if (this_insn_is_asm)
580: {
581: enum machine_mode mode;
582: if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode))
583: mode = inmode;
584: else
585: mode = outmode;
586: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
587: if (HARD_REGNO_MODE_OK (i, mode)
588: && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i))
589: {
590: int nregs = HARD_REGNO_NREGS (i, mode);
591:
592: int j;
593: for (j = 1; j < nregs; j++)
594: if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j))
595: break;
596: if (j == nregs)
597: break;
598: }
599: if (i == FIRST_PSEUDO_REGISTER)
600: {
601: error_for_asm (this_insn, "impossible register constraint in `asm'");
602: class = ALL_REGS;
603: }
604: }
605:
606: /* We can use an existing reload if the class is right
607: and at least one of IN and OUT is a match
608: and the other is at worst neutral.
609: (A zero compared against anything is neutral.) */
610: for (i = 0; i < n_reloads; i++)
611: if ((reg_class_subset_p (class, reload_reg_class[i])
612: || reg_class_subset_p (reload_reg_class[i], class))
613: && reload_strict_low[i] == strict_low
614: /* If the existing reload has a register, it must fit our class. */
615: && (reload_reg_rtx[i] == 0
616: || TEST_HARD_REG_BIT (reg_class_contents[(int) class],
617: true_regnum (reload_reg_rtx[i])))
618: && ((in != 0 && MATCHES (reload_in[i], in) && ! dont_share
619: && (out == 0 || reload_out[i] == 0 || MATCHES (reload_out[i], out)))
620: ||
621: (out != 0 && MATCHES (reload_out[i], out)
622: && (in == 0 || reload_in[i] == 0 || MATCHES (reload_in[i], in)))))
623: break;
624:
625: /* Reloading a plain reg for input can match a reload to postincrement
626: that reg, since the postincrement's value is the right value.
627: Likewise, it can match a preincrement reload, since we regard
628: the preincrementation as happening before any ref in this insn
629: to that register. */
630: if (i == n_reloads)
631: for (i = 0; i < n_reloads; i++)
632: if ((reg_class_subset_p (class, reload_reg_class[i])
633: || reg_class_subset_p (reload_reg_class[i], class))
634: /* If the existing reload has a register, it must fit our class. */
635: && (reload_reg_rtx[i] == 0
636: || TEST_HARD_REG_BIT (reg_class_contents[(int) class],
637: true_regnum (reload_reg_rtx[i])))
638: && reload_strict_low[i] == strict_low
639: && out == 0 && reload_out[i] == 0 && reload_in[i] != 0
640: && ((GET_CODE (in) == REG
641: && (GET_CODE (reload_in[i]) == POST_INC
642: || GET_CODE (reload_in[i]) == POST_DEC
643: || GET_CODE (reload_in[i]) == PRE_INC
644: || GET_CODE (reload_in[i]) == PRE_DEC)
645: && MATCHES (XEXP (reload_in[i], 0), in))
646: ||
647: (GET_CODE (reload_in[i]) == REG
648: && (GET_CODE (in) == POST_INC
649: || GET_CODE (in) == POST_DEC
650: || GET_CODE (in) == PRE_INC
651: || GET_CODE (in) == PRE_DEC)
652: && MATCHES (XEXP (in, 0), reload_in[i]))))
653: {
654: /* Make sure reload_in ultimately has the increment,
655: not the plain register. */
656: if (GET_CODE (in) == REG)
657: in = reload_in[i];
658: break;
659: }
660:
661: if (i == n_reloads)
662: {
663: #ifdef HAVE_SECONDARY_RELOADS
664: enum reg_class secondary_class = NO_REGS;
665: enum reg_class secondary_out_class = NO_REGS;
666: enum machine_mode secondary_mode = inmode;
667: enum machine_mode secondary_out_mode = outmode;
668: enum insn_code secondary_icode;
669: enum insn_code secondary_out_icode = CODE_FOR_nothing;
670: enum reg_class tertiary_class = NO_REGS;
671: enum reg_class tertiary_out_class = NO_REGS;
672: enum machine_mode tertiary_mode;
673: enum machine_mode tertiary_out_mode;
674: enum insn_code tertiary_icode;
675: enum insn_code tertiary_out_icode = CODE_FOR_nothing;
676: int tertiary_reload = -1;
677:
678: /* See if we need a secondary reload register to move between
679: CLASS and IN or CLASS and OUT. Get the modes and icodes to
680: use for each of them if so. */
681:
682: #ifdef SECONDARY_INPUT_RELOAD_CLASS
683: if (in != 0)
684: secondary_class
685: = find_secondary_reload (in, class, inmode, 1, &secondary_icode,
686: &secondary_mode, &tertiary_class,
687: &tertiary_icode, &tertiary_mode);
688: #endif
689:
690: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
691: if (out != 0 && GET_CODE (out) != SCRATCH)
692: secondary_out_class
693: = find_secondary_reload (out, class, outmode, 0,
694: &secondary_out_icode, &secondary_out_mode,
695: &tertiary_out_class, &tertiary_out_icode,
696: &tertiary_out_mode);
697: #endif
698:
699: /* We can only record one secondary and one tertiary reload. If both
700: IN and OUT need secondary reloads, we can only make an in-out
701: reload if neither need an insn and if the classes are compatible. */
702:
703: if (secondary_class != NO_REGS && secondary_out_class != NO_REGS
704: && reg_class_subset_p (secondary_out_class, secondary_class))
705: secondary_class = secondary_out_class;
706:
707: if (secondary_class != NO_REGS && secondary_out_class != NO_REGS
708: && (! reg_class_subset_p (secondary_class, secondary_out_class)
709: || secondary_icode != CODE_FOR_nothing
710: || secondary_out_icode != CODE_FOR_nothing))
711: {
712: push_reload (0, out, 0, outloc, class, VOIDmode, outmode,
713: strict_low, optional, needed_for);
714: out = 0;
715: outloc = 0;
716: outmode = VOIDmode;
717: }
718:
719: /* If we need a secondary reload for OUT but not IN, copy the
720: information. */
721: if (secondary_class == NO_REGS && secondary_out_class != NO_REGS)
722: {
723: secondary_class = secondary_out_class;
724: secondary_icode = secondary_out_icode;
725: tertiary_class = tertiary_out_class;
726: tertiary_icode = tertiary_out_icode;
727: tertiary_mode = tertiary_out_mode;
728: }
729:
730: if (secondary_class != NO_REGS)
731: {
732: /* If we need a tertiary reload, see if we have one we can reuse
733: or else make one. */
734:
735: if (tertiary_class != NO_REGS)
736: {
737: for (tertiary_reload = 0; tertiary_reload < n_reloads;
738: tertiary_reload++)
739: if (reload_secondary_p[tertiary_reload]
740: && (reg_class_subset_p (tertiary_class,
741: reload_reg_class[tertiary_reload])
742: || reg_class_subset_p (reload_reg_class[tertiary_reload],
743: tertiary_class))
744: && ((reload_inmode[tertiary_reload] == tertiary_mode)
745: || reload_inmode[tertiary_reload] == VOIDmode)
746: && ((reload_outmode[tertiary_reload] == tertiary_mode)
747: || reload_outmode[tertiary_reload] == VOIDmode)
748: && (reload_secondary_icode[tertiary_reload]
749: == CODE_FOR_nothing))
750:
751: {
752: if (tertiary_mode != VOIDmode)
753: reload_inmode[tertiary_reload] = tertiary_mode;
754: if (tertiary_out_mode != VOIDmode)
755: reload_outmode[tertiary_reload] = tertiary_mode;
756: if (reg_class_subset_p (tertiary_class,
757: reload_reg_class[tertiary_reload]))
758: reload_reg_class[tertiary_reload] = tertiary_class;
759: if (reload_needed_for[tertiary_reload] != needed_for)
760: reload_needed_for_multiple[tertiary_reload] = 1;
761: reload_optional[tertiary_reload] &= optional;
762: reload_secondary_p[tertiary_reload] = 1;
763: }
764:
765: if (tertiary_reload == n_reloads)
766: {
767: /* We need to make a new tertiary reload for this register
768: class. */
769: reload_in[tertiary_reload] = reload_out[tertiary_reload] = 0;
770: reload_reg_class[tertiary_reload] = tertiary_class;
771: reload_inmode[tertiary_reload] = tertiary_mode;
772: reload_outmode[tertiary_reload] = tertiary_mode;
773: reload_reg_rtx[tertiary_reload] = 0;
774: reload_optional[tertiary_reload] = optional;
775: reload_inc[tertiary_reload] = 0;
776: reload_strict_low[tertiary_reload] = 0;
777: /* Maybe we could combine these, but it seems too tricky. */
778: reload_nocombine[tertiary_reload] = 1;
779: reload_in_reg[tertiary_reload] = 0;
780: reload_needed_for[tertiary_reload] = needed_for;
781: reload_needed_for_multiple[tertiary_reload] = 0;
782: reload_secondary_reload[tertiary_reload] = -1;
783: reload_secondary_icode[tertiary_reload] = CODE_FOR_nothing;
784: reload_secondary_p[tertiary_reload] = 1;
785:
786: n_reloads++;
787: i = n_reloads;
788: }
789: }
790:
791: /* See if we can reuse an existing secondary reload. */
792: for (secondary_reload = 0; secondary_reload < n_reloads;
793: secondary_reload++)
794: if (reload_secondary_p[secondary_reload]
795: && (reg_class_subset_p (secondary_class,
796: reload_reg_class[secondary_reload])
797: || reg_class_subset_p (reload_reg_class[secondary_reload],
798: secondary_class))
799: && ((reload_inmode[secondary_reload] == secondary_mode)
800: || reload_inmode[secondary_reload] == VOIDmode)
801: && ((reload_outmode[secondary_reload] == secondary_out_mode)
802: || reload_outmode[secondary_reload] == VOIDmode)
803: && reload_secondary_reload[secondary_reload] == tertiary_reload
804: && reload_secondary_icode[secondary_reload] == tertiary_icode)
805: {
806: if (secondary_mode != VOIDmode)
807: reload_inmode[secondary_reload] = secondary_mode;
808: if (secondary_out_mode != VOIDmode)
809: reload_outmode[secondary_reload] = secondary_out_mode;
810: if (reg_class_subset_p (secondary_class,
811: reload_reg_class[secondary_reload]))
812: reload_reg_class[secondary_reload] = secondary_class;
813: if (reload_needed_for[secondary_reload] != needed_for)
814: reload_needed_for_multiple[secondary_reload] = 1;
815: reload_optional[secondary_reload] &= optional;
816: reload_secondary_p[secondary_reload] = 1;
817: }
818:
819: if (secondary_reload == n_reloads)
820: {
821: /* We need to make a new secondary reload for this register
822: class. */
823: reload_in[secondary_reload] = reload_out[secondary_reload] = 0;
824: reload_reg_class[secondary_reload] = secondary_class;
825: reload_inmode[secondary_reload] = secondary_mode;
826: reload_outmode[secondary_reload] = secondary_out_mode;
827: reload_reg_rtx[secondary_reload] = 0;
828: reload_optional[secondary_reload] = optional;
829: reload_inc[secondary_reload] = 0;
830: reload_strict_low[secondary_reload] = 0;
831: /* Maybe we could combine these, but it seems too tricky. */
832: reload_nocombine[secondary_reload] = 1;
833: reload_in_reg[secondary_reload] = 0;
834: reload_needed_for[secondary_reload] = needed_for;
835: reload_needed_for_multiple[secondary_reload] = 0;
836: reload_secondary_reload[secondary_reload] = tertiary_reload;
837: reload_secondary_icode[secondary_reload] = tertiary_icode;
838: reload_secondary_p[secondary_reload] = 1;
839:
840: n_reloads++;
841: i = n_reloads;
842: }
843: }
844: #endif
845:
846: /* We found no existing reload suitable for re-use.
847: So add an additional reload. */
848:
849: reload_in[i] = in;
850: reload_out[i] = out;
851: reload_reg_class[i] = class;
852: reload_inmode[i] = inmode;
853: reload_outmode[i] = outmode;
854: reload_reg_rtx[i] = 0;
855: reload_optional[i] = optional;
856: reload_inc[i] = 0;
857: reload_strict_low[i] = strict_low;
858: reload_nocombine[i] = 0;
859: reload_in_reg[i] = inloc ? *inloc : 0;
860: reload_needed_for[i] = needed_for;
861: reload_needed_for_multiple[i] = 0;
862: reload_secondary_reload[i] = secondary_reload;
863: reload_secondary_icode[i] = secondary_icode;
864: reload_secondary_p[i] = 0;
865:
866: n_reloads++;
867: }
868: else
869: {
870: /* We are reusing an existing reload,
871: but we may have additional information for it.
872: For example, we may now have both IN and OUT
873: while the old one may have just one of them. */
874:
875: if (inmode != VOIDmode)
876: reload_inmode[i] = inmode;
877: if (outmode != VOIDmode)
878: reload_outmode[i] = outmode;
879: if (in != 0)
880: reload_in[i] = in;
881: if (out != 0)
882: reload_out[i] = out;
883: if (reg_class_subset_p (class, reload_reg_class[i]))
884: reload_reg_class[i] = class;
885: reload_optional[i] &= optional;
886: if (reload_needed_for[i] != needed_for)
887: reload_needed_for_multiple[i] = 1;
888: }
889:
890: /* If the ostensible rtx being reload differs from the rtx found
891: in the location to substitute, this reload is not safe to combine
892: because we cannot reliably tell whether it appears in the insn. */
893:
894: if (in != 0 && in != *inloc)
895: reload_nocombine[i] = 1;
896:
897: #if 0
898: /* This was replaced by changes in find_reloads_address_1 and the new
899: function inc_for_reload, which go with a new meaning of reload_inc. */
900:
901: /* If this is an IN/OUT reload in an insn that sets the CC,
902: it must be for an autoincrement. It doesn't work to store
903: the incremented value after the insn because that would clobber the CC.
904: So we must do the increment of the value reloaded from,
905: increment it, store it back, then decrement again. */
906: if (out != 0 && sets_cc0_p (PATTERN (this_insn)))
907: {
908: out = 0;
909: reload_out[i] = 0;
910: reload_inc[i] = find_inc_amount (PATTERN (this_insn), in);
911: /* If we did not find a nonzero amount-to-increment-by,
912: that contradicts the belief that IN is being incremented
913: in an address in this insn. */
914: if (reload_inc[i] == 0)
915: abort ();
916: }
917: #endif
918:
919: /* If we will replace IN and OUT with the reload-reg,
920: record where they are located so that substitution need
921: not do a tree walk. */
922:
923: if (replace_reloads)
924: {
925: if (inloc != 0)
926: {
927: register struct replacement *r = &replacements[n_replacements++];
928: r->what = i;
929: r->subreg_loc = in_subreg_loc;
930: r->where = inloc;
931: r->mode = inmode;
932: }
933: if (outloc != 0 && outloc != inloc)
934: {
935: register struct replacement *r = &replacements[n_replacements++];
936: r->what = i;
937: r->where = outloc;
938: r->subreg_loc = out_subreg_loc;
939: r->mode = outmode;
940: }
941: }
942:
943: /* If this reload is just being introduced and it has both
944: an incoming quantity and an outgoing quantity that are
945: supposed to be made to match, see if either one of the two
946: can serve as the place to reload into.
947:
948: If one of them is acceptable, set reload_reg_rtx[i]
949: to that one. */
950:
951: if (in != 0 && out != 0 && in != out && reload_reg_rtx[i] == 0)
952: {
953: reload_reg_rtx[i] = find_dummy_reload (in, out, inloc, outloc,
954: reload_reg_class[i], i);
955:
956: /* If the outgoing register already contains the same value
957: as the incoming one, we can dispense with loading it.
958: The easiest way to tell the caller that is to give a phony
959: value for the incoming operand (same as outgoing one). */
960: if (reload_reg_rtx[i] == out
961: && (GET_CODE (in) == REG || CONSTANT_P (in))
962: && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out),
963: static_reload_reg_p, i, inmode))
964: reload_in[i] = out;
965: }
966:
967: /* If this is an input reload and the operand contains a register that
968: dies in this insn and is used nowhere else, see if it is the right class
969: to be used for this reload. Use it if so. (This occurs most commonly
970: in the case of paradoxical SUBREGs and in-out reloads). We cannot do
971: this if it is also an output reload that mentions the register unless
972: the output is a SUBREG that clobbers an entire register.
973:
974: Note that the operand might be one of the spill regs, if it is a
975: pseudo reg and we are in a block where spilling has not taken place.
976: But if there is no spilling in this block, that is OK.
977: An explicitly used hard reg cannot be a spill reg. */
978:
979: if (reload_reg_rtx[i] == 0 && in != 0)
980: {
981: rtx note;
982: int regno;
983:
984: for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
985: if (REG_NOTE_KIND (note) == REG_DEAD
986: && GET_CODE (XEXP (note, 0)) == REG
987: && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER
988: && reg_mentioned_p (XEXP (note, 0), in)
989: && ! refers_to_regno_for_reload_p (regno,
990: (regno
991: + HARD_REGNO_NREGS (regno,
992: inmode)),
993: PATTERN (this_insn), inloc)
994: && (in != out
995: || (GET_CODE (in) == SUBREG
996: && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1))
997: / UNITS_PER_WORD)
998: == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
999: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
1000: /* Make sure the operand fits in the reg that dies. */
1001: && GET_MODE_SIZE (inmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
1002: && HARD_REGNO_MODE_OK (regno, inmode)
1003: && GET_MODE_SIZE (outmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
1004: && HARD_REGNO_MODE_OK (regno, outmode)
1005: && TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
1006: && !fixed_regs[regno])
1007: {
1008: reload_reg_rtx[i] = gen_rtx (REG, inmode, regno);
1009: break;
1010: }
1011: }
1012:
1013: if (out)
1014: output_reloadnum = i;
1015:
1016: return i;
1017: }
1018:
1019: /* Record an additional place we must replace a value
1020: for which we have already recorded a reload.
1021: RELOADNUM is the value returned by push_reload
1022: when the reload was recorded.
1023: This is used in insn patterns that use match_dup. */
1024:
1025: static void
1026: push_replacement (loc, reloadnum, mode)
1027: rtx *loc;
1028: int reloadnum;
1029: enum machine_mode mode;
1030: {
1031: if (replace_reloads)
1032: {
1033: register struct replacement *r = &replacements[n_replacements++];
1034: r->what = reloadnum;
1035: r->where = loc;
1036: r->subreg_loc = 0;
1037: r->mode = mode;
1038: }
1039: }
1040:
1041: /* If there is only one output reload, and it is not for an earlyclobber
1042: operand, try to combine it with a (logically unrelated) input reload
1043: to reduce the number of reload registers needed.
1044:
1045: This is safe if the input reload does not appear in
1046: the value being output-reloaded, because this implies
1047: it is not needed any more once the original insn completes.
1048:
1049: If that doesn't work, see we can use any of the registers that
1050: die in this insn as a reload register. We can if it is of the right
1051: class and does not appear in the value being output-reloaded. */
1052:
1053: static void
1054: combine_reloads ()
1055: {
1056: int i;
1057: int output_reload = -1;
1058: rtx note;
1059:
1060: /* Find the output reload; return unless there is exactly one
1061: and that one is mandatory. */
1062:
1063: for (i = 0; i < n_reloads; i++)
1064: if (reload_out[i] != 0)
1065: {
1066: if (output_reload >= 0)
1067: return;
1068: output_reload = i;
1069: }
1070:
1071: if (output_reload < 0 || reload_optional[output_reload])
1072: return;
1073:
1074: /* An input-output reload isn't combinable. */
1075:
1076: if (reload_in[output_reload] != 0)
1077: return;
1078:
1079: /* If this reload is for an earlyclobber operand, we can't do anyting. */
1080:
1081: for (i = 0; i < n_earlyclobbers; i++)
1082: if (reload_out[output_reload] == reload_earlyclobbers[i])
1083: return;
1084:
1085: /* Check each input reload; can we combine it? */
1086:
1087: for (i = 0; i < n_reloads; i++)
1088: if (reload_in[i] && ! reload_optional[i] && ! reload_nocombine[i]
1089: /* Life span of this reload must not extend past main insn. */
1090: && reload_when_needed[i] != RELOAD_FOR_OUTPUT_RELOAD_ADDRESS
1091: && reload_inmode[i] == reload_outmode[output_reload]
1092: && reload_inc[i] == 0
1093: && reload_reg_rtx[i] == 0
1094: && reload_strict_low[i] == 0
1095: /* Don't combine two reloads with different secondary reloads. */
1096: && (reload_secondary_reload[i] == reload_secondary_reload[output_reload]
1097: || reload_secondary_reload[i] == -1
1098: || reload_secondary_reload[output_reload] == -1)
1099: && (reg_class_subset_p (reload_reg_class[i],
1100: reload_reg_class[output_reload])
1101: || reg_class_subset_p (reload_reg_class[output_reload],
1102: reload_reg_class[i]))
1103: && (MATCHES (reload_in[i], reload_out[output_reload])
1104: /* Args reversed because the first arg seems to be
1105: the one that we imagine being modified
1106: while the second is the one that might be affected. */
1107: || (! reg_overlap_mentioned_p (reload_out[output_reload],
1108: reload_in[i])
1109: /* However, if the input is a register that appears inside
1110: the output, then we also can't share.
1111: Imagine (set (mem (reg 69)) (plus (reg 69) ...)).
1112: If the same reload reg is used for both reg 69 and the
1113: result to be stored in memory, then that result
1114: will clobber the address of the memory ref. */
1115: && ! (GET_CODE (reload_in[i]) == REG
1116: && reg_overlap_mentioned_p (reload_in[i],
1117: reload_out[output_reload])))))
1118: {
1119: int j;
1120:
1121: /* We have found a reload to combine with! */
1122: reload_out[i] = reload_out[output_reload];
1123: reload_outmode[i] = reload_outmode[output_reload];
1124: /* Mark the old output reload as inoperative. */
1125: reload_out[output_reload] = 0;
1126: /* The combined reload is needed for the entire insn. */
1127: reload_needed_for_multiple[i] = 1;
1128: reload_when_needed[i] = RELOAD_OTHER;
1129: /* If the output reload had a secondary reload, copy it. */
1130: if (reload_secondary_reload[output_reload] != -1)
1131: reload_secondary_reload[i] = reload_secondary_reload[output_reload];
1132: /* If required, minimize the register class. */
1133: if (reg_class_subset_p (reload_reg_class[output_reload],
1134: reload_reg_class[i]))
1135: reload_reg_class[i] = reload_reg_class[output_reload];
1136:
1137: /* Transfer all replacements from the old reload to the combined. */
1138: for (j = 0; j < n_replacements; j++)
1139: if (replacements[j].what == output_reload)
1140: replacements[j].what = i;
1141:
1142: return;
1143: }
1144:
1145: /* If this insn has only one operand that is modified or written (assumed
1146: to be the first), it must be the one corresponding to this reload. It
1147: is safe to use anything that dies in this insn for that output provided
1148: that it does not occur in the output (we already know it isn't an
1149: earlyclobber. If this is an asm insn, give up. */
1150:
1151: if (INSN_CODE (this_insn) == -1)
1152: return;
1153:
1154: for (i = 1; i < insn_n_operands[INSN_CODE (this_insn)]; i++)
1155: if (insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '='
1156: || insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '+')
1157: return;
1158:
1159: /* See if some hard register that dies in this insn and is not used in
1160: the output is the right class. Only works if the register we pick
1161: up can fully hold our output reload. */
1162: for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
1163: if (REG_NOTE_KIND (note) == REG_DEAD
1164: && GET_CODE (XEXP (note, 0)) == REG
1165: && ! reg_overlap_mentioned_p (XEXP (note, 0),
1166: reload_out[output_reload])
1167: && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
1168: && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), reload_outmode[output_reload])
1169: && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[output_reload]],
1170: REGNO (XEXP (note, 0)))
1171: && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), reload_outmode[output_reload])
1172: <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0))))
1173: && ! fixed_regs[REGNO (XEXP (note, 0))])
1174: {
1175: reload_reg_rtx[output_reload] = gen_rtx (REG,
1176: reload_outmode[output_reload],
1177: REGNO (XEXP (note, 0)));
1178: return;
1179: }
1180: }
1181:
1182: /* Try to find a reload register for an in-out reload (expressions IN and OUT).
1183: See if one of IN and OUT is a register that may be used;
1184: this is desirable since a spill-register won't be needed.
1185: If so, return the register rtx that proves acceptable.
1186:
1187: INLOC and OUTLOC are locations where IN and OUT appear in the insn.
1188: CLASS is the register class required for the reload.
1189:
1190: If FOR_REAL is >= 0, it is the number of the reload,
1191: and in some cases when it can be discovered that OUT doesn't need
1192: to be computed, clear out reload_out[FOR_REAL].
1193:
1194: If FOR_REAL is -1, this should not be done, because this call
1195: is just to see if a register can be found, not to find and install it. */
1196:
1197: static rtx
1198: find_dummy_reload (real_in, real_out, inloc, outloc, class, for_real)
1199: rtx real_in, real_out;
1200: rtx *inloc, *outloc;
1201: enum reg_class class;
1202: int for_real;
1203: {
1204: rtx in = real_in;
1205: rtx out = real_out;
1206: int in_offset = 0;
1207: int out_offset = 0;
1208: rtx value = 0;
1209:
1210: /* If operands exceed a word, we can't use either of them
1211: unless they have the same size. */
1212: if (GET_MODE_SIZE (GET_MODE (real_out)) != GET_MODE_SIZE (GET_MODE (real_in))
1213: && (GET_MODE_SIZE (GET_MODE (real_out)) > UNITS_PER_WORD
1214: || GET_MODE_SIZE (GET_MODE (real_in)) > UNITS_PER_WORD))
1215: return 0;
1216:
1217: /* Find the inside of any subregs. */
1218: while (GET_CODE (out) == SUBREG)
1219: {
1220: out_offset = SUBREG_WORD (out);
1221: out = SUBREG_REG (out);
1222: }
1223: while (GET_CODE (in) == SUBREG)
1224: {
1225: in_offset = SUBREG_WORD (in);
1226: in = SUBREG_REG (in);
1227: }
1228:
1229: /* Narrow down the reg class, the same way push_reload will;
1230: otherwise we might find a dummy now, but push_reload won't. */
1231: class = PREFERRED_RELOAD_CLASS (in, class);
1232:
1233: /* See if OUT will do. */
1234: if (GET_CODE (out) == REG
1235: && REGNO (out) < FIRST_PSEUDO_REGISTER)
1236: {
1237: register int regno = REGNO (out) + out_offset;
1238: int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_out));
1239:
1240: /* When we consider whether the insn uses OUT,
1241: ignore references within IN. They don't prevent us
1242: from copying IN into OUT, because those refs would
1243: move into the insn that reloads IN.
1244:
1245: However, we only ignore IN in its role as this reload.
1246: If the insn uses IN elsewhere and it contains OUT,
1247: that counts. We can't be sure it's the "same" operand
1248: so it might not go through this reload. */
1249: *inloc = const0_rtx;
1250:
1251: if (regno < FIRST_PSEUDO_REGISTER
1252: /* A fixed reg that can overlap other regs better not be used
1253: for reloading in any way. */
1254: #ifdef OVERLAPPING_REGNO_P
1255: && ! (fixed_regs[regno] && OVERLAPPING_REGNO_P (regno))
1256: #endif
1257: && ! refers_to_regno_for_reload_p (regno, regno + nwords,
1258: PATTERN (this_insn), outloc))
1259: {
1260: int i;
1261: for (i = 0; i < nwords; i++)
1262: if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1263: regno + i))
1264: break;
1265:
1266: if (i == nwords)
1267: {
1268: if (GET_CODE (real_out) == REG)
1269: value = real_out;
1270: else
1271: value = gen_rtx (REG, GET_MODE (real_out), regno);
1272: }
1273: }
1274:
1275: *inloc = real_in;
1276: }
1277:
1278: /* Consider using IN if OUT was not acceptable
1279: or if OUT dies in this insn (like the quotient in a divmod insn).
1280: We can't use IN unless it is dies in this insn,
1281: which means we must know accurately which hard regs are live.
1282: Also, the result can't go in IN if IN is used within OUT. */
1283: if (hard_regs_live_known
1284: && GET_CODE (in) == REG
1285: && REGNO (in) < FIRST_PSEUDO_REGISTER
1286: && (value == 0
1287: || find_reg_note (this_insn, REG_UNUSED, real_out))
1288: && find_reg_note (this_insn, REG_DEAD, real_in)
1289: && !fixed_regs[REGNO (in)]
1290: && HARD_REGNO_MODE_OK (REGNO (in), GET_MODE (out)))
1291: {
1292: register int regno = REGNO (in) + in_offset;
1293: int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_in));
1294:
1295: if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, 0)
1296: && ! hard_reg_set_here_p (regno, regno + nwords,
1297: PATTERN (this_insn)))
1298: {
1299: int i;
1300: for (i = 0; i < nwords; i++)
1301: if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1302: regno + i))
1303: break;
1304:
1305: if (i == nwords)
1306: {
1307: /* If we were going to use OUT as the reload reg
1308: and changed our mind, it means OUT is a dummy that
1309: dies here. So don't bother copying value to it. */
1310: if (for_real >= 0 && value == real_out)
1311: reload_out[for_real] = 0;
1312: if (GET_CODE (real_in) == REG)
1313: value = real_in;
1314: else
1315: value = gen_rtx (REG, GET_MODE (real_in), regno);
1316: }
1317: }
1318: }
1319:
1320: return value;
1321: }
1322:
1323: /* This page contains subroutines used mainly for determining
1324: whether the IN or an OUT of a reload can serve as the
1325: reload register. */
1326:
1327: /* Return 1 if expression X alters a hard reg in the range
1328: from BEG_REGNO (inclusive) to END_REGNO (exclusive),
1329: either explicitly or in the guise of a pseudo-reg allocated to REGNO.
1330: X should be the body of an instruction. */
1331:
1332: static int
1333: hard_reg_set_here_p (beg_regno, end_regno, x)
1334: register int beg_regno, end_regno;
1335: rtx x;
1336: {
1337: if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
1338: {
1339: register rtx op0 = SET_DEST (x);
1340: while (GET_CODE (op0) == SUBREG)
1341: op0 = SUBREG_REG (op0);
1342: if (GET_CODE (op0) == REG)
1343: {
1344: register int r = REGNO (op0);
1345: /* See if this reg overlaps range under consideration. */
1346: if (r < end_regno
1347: && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno)
1348: return 1;
1349: }
1350: }
1351: else if (GET_CODE (x) == PARALLEL)
1352: {
1353: register int i = XVECLEN (x, 0) - 1;
1354: for (; i >= 0; i--)
1355: if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i)))
1356: return 1;
1357: }
1358:
1359: return 0;
1360: }
1361:
1362: /* Return 1 if ADDR is a valid memory address for mode MODE,
1363: and check that each pseudo reg has the proper kind of
1364: hard reg. */
1365:
1366: int
1367: strict_memory_address_p (mode, addr)
1368: enum machine_mode mode;
1369: register rtx addr;
1370: {
1371: GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1372: return 0;
1373:
1374: win:
1375: return 1;
1376: }
1377:
1378:
1379: /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
1380: if they are the same hard reg, and has special hacks for
1381: autoincrement and autodecrement.
1382: This is specifically intended for find_reloads to use
1383: in determining whether two operands match.
1384: X is the operand whose number is the lower of the two.
1385:
1386: The value is 2 if Y contains a pre-increment that matches
1387: a non-incrementing address in X. */
1388:
1389: /* ??? To be completely correct, we should arrange to pass
1390: for X the output operand and for Y the input operand.
1391: For now, we assume that the output operand has the lower number
1392: because that is natural in (SET output (... input ...)). */
1393:
1394: int
1395: operands_match_p (x, y)
1396: register rtx x, y;
1397: {
1398: register int i;
1399: register RTX_CODE code = GET_CODE (x);
1400: register char *fmt;
1401: int success_2;
1402:
1403: if (x == y)
1404: return 1;
1405: if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG))
1406: && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG
1407: && GET_CODE (SUBREG_REG (y)) == REG)))
1408: {
1409: register int j;
1410:
1411: if (code == SUBREG)
1412: {
1413: i = REGNO (SUBREG_REG (x));
1414: if (i >= FIRST_PSEUDO_REGISTER)
1415: goto slow;
1416: i += SUBREG_WORD (x);
1417: }
1418: else
1419: i = REGNO (x);
1420:
1421: if (GET_CODE (y) == SUBREG)
1422: {
1423: j = REGNO (SUBREG_REG (y));
1424: if (j >= FIRST_PSEUDO_REGISTER)
1425: goto slow;
1426: j += SUBREG_WORD (y);
1427: }
1428: else
1429: j = REGNO (y);
1430:
1431: return i == j;
1432: }
1433: /* If two operands must match, because they are really a single
1434: operand of an assembler insn, then two postincrements are invalid
1435: because the assembler insn would increment only once.
1436: On the other hand, an postincrement matches ordinary indexing
1437: if the postincrement is the output operand. */
1438: if (code == POST_DEC || code == POST_INC)
1439: return operands_match_p (XEXP (x, 0), y);
1440: /* Two preincrements are invalid
1441: because the assembler insn would increment only once.
1442: On the other hand, an preincrement matches ordinary indexing
1443: if the preincrement is the input operand.
1444: In this case, return 2, since some callers need to do special
1445: things when this happens. */
1446: if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC)
1447: return operands_match_p (x, XEXP (y, 0)) ? 2 : 0;
1448:
1449: slow:
1450:
1451: /* Now we have disposed of all the cases
1452: in which different rtx codes can match. */
1453: if (code != GET_CODE (y))
1454: return 0;
1455: if (code == LABEL_REF)
1456: return XEXP (x, 0) == XEXP (y, 0);
1457: if (code == SYMBOL_REF)
1458: return XSTR (x, 0) == XSTR (y, 0);
1459:
1460: /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
1461:
1462: if (GET_MODE (x) != GET_MODE (y))
1463: return 0;
1464:
1465: /* Compare the elements. If any pair of corresponding elements
1466: fail to match, return 0 for the whole things. */
1467:
1468: success_2 = 0;
1469: fmt = GET_RTX_FORMAT (code);
1470: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1471: {
1472: int val;
1473: switch (fmt[i])
1474: {
1475: case 'i':
1476: if (XINT (x, i) != XINT (y, i))
1477: return 0;
1478: break;
1479:
1480: case 'e':
1481: val = operands_match_p (XEXP (x, i), XEXP (y, i));
1482: if (val == 0)
1483: return 0;
1484: /* If any subexpression returns 2,
1485: we should return 2 if we are successful. */
1486: if (val == 2)
1487: success_2 = 1;
1488: break;
1489:
1490: case '0':
1491: break;
1492:
1493: /* It is believed that rtx's at this level will never
1494: contain anything but integers and other rtx's,
1495: except for within LABEL_REFs and SYMBOL_REFs. */
1496: default:
1497: abort ();
1498: }
1499: }
1500: return 1 + success_2;
1501: }
1502:
1503: /* Return the number of times character C occurs in string S. */
1504:
1505: static int
1506: n_occurrences (c, s)
1507: char c;
1508: char *s;
1509: {
1510: int n = 0;
1511: while (*s)
1512: n += (*s++ == c);
1513: return n;
1514: }
1515:
1516: struct decomposition
1517: {
1518: int reg_flag;
1519: int safe;
1520: rtx base;
1521: int start;
1522: int end;
1523: };
1524:
1525: /* Describe the range of registers or memory referenced by X.
1526: If X is a register, set REG_FLAG and put the first register
1527: number into START and the last plus one into END.
1528: If X is a memory reference, put a base address into BASE
1529: and a range of integer offsets into START and END.
1530: If X is pushing on the stack, we can assume it causes no trouble,
1531: so we set the SAFE field. */
1532:
1533: static struct decomposition
1534: decompose (x)
1535: rtx x;
1536: {
1537: struct decomposition val;
1538: int all_const = 0;
1539:
1540: val.reg_flag = 0;
1541: val.safe = 0;
1542: if (GET_CODE (x) == MEM)
1543: {
1544: rtx base, offset = 0;
1545: rtx addr = XEXP (x, 0);
1546:
1547: if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC
1548: || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC)
1549: {
1550: val.base = XEXP (addr, 0);
1551: val.start = - GET_MODE_SIZE (GET_MODE (x));
1552: val.end = GET_MODE_SIZE (GET_MODE (x));
1553: val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
1554: return val;
1555: }
1556:
1557: if (GET_CODE (addr) == CONST)
1558: {
1559: addr = XEXP (addr, 0);
1560: all_const = 1;
1561: }
1562: if (GET_CODE (addr) == PLUS)
1563: {
1564: if (CONSTANT_P (XEXP (addr, 0)))
1565: {
1566: base = XEXP (addr, 1);
1567: offset = XEXP (addr, 0);
1568: }
1569: else if (CONSTANT_P (XEXP (addr, 1)))
1570: {
1571: base = XEXP (addr, 0);
1572: offset = XEXP (addr, 1);
1573: }
1574: }
1575:
1576: if (offset == 0)
1577: {
1578: base = addr;
1579: offset = const0_rtx;
1580: }
1581: if (GET_CODE (offset) == CONST)
1582: offset = XEXP (offset, 0);
1583: if (GET_CODE (offset) == PLUS)
1584: {
1585: if (GET_CODE (XEXP (offset, 0)) == CONST_INT)
1586: {
1587: base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 1));
1588: offset = XEXP (offset, 0);
1589: }
1590: else if (GET_CODE (XEXP (offset, 1)) == CONST_INT)
1591: {
1592: base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 0));
1593: offset = XEXP (offset, 1);
1594: }
1595: else
1596: {
1597: base = gen_rtx (PLUS, GET_MODE (base), base, offset);
1598: offset = const0_rtx;
1599: }
1600: }
1601: else if (GET_CODE (offset) != CONST_INT)
1602: {
1603: base = gen_rtx (PLUS, GET_MODE (base), base, offset);
1604: offset = const0_rtx;
1605: }
1606:
1607: if (all_const && GET_CODE (base) == PLUS)
1608: base = gen_rtx (CONST, GET_MODE (base), base);
1609:
1610: if (GET_CODE (offset) != CONST_INT)
1611: abort ();
1612:
1613: val.start = INTVAL (offset);
1614: val.end = val.start + GET_MODE_SIZE (GET_MODE (x));
1615: val.base = base;
1616: return val;
1617: }
1618: else if (GET_CODE (x) == REG)
1619: {
1620: val.reg_flag = 1;
1621: val.start = true_regnum (x);
1622: if (val.start < 0)
1623: {
1624: /* A pseudo with no hard reg. */
1625: val.start = REGNO (x);
1626: val.end = val.start + 1;
1627: }
1628: else
1629: /* A hard reg. */
1630: val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x));
1631: }
1632: else if (GET_CODE (x) == SUBREG)
1633: {
1634: if (GET_CODE (SUBREG_REG (x)) != REG)
1635: /* This could be more precise, but it's good enough. */
1636: return decompose (SUBREG_REG (x));
1637: val.reg_flag = 1;
1638: val.start = true_regnum (x);
1639: if (val.start < 0)
1640: return decompose (SUBREG_REG (x));
1641: else
1642: /* A hard reg. */
1643: val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x));
1644: }
1645: else if (CONSTANT_P (x)
1646: /* This hasn't been assigned yet, so it can't conflict yet. */
1647: || GET_CODE (x) == SCRATCH)
1648: val.safe = 1;
1649: else
1650: abort ();
1651: return val;
1652: }
1653:
1654: /* Return 1 if altering Y will not modify the value of X.
1655: Y is also described by YDATA, which should be decompose (Y). */
1656:
1657: static int
1658: immune_p (x, y, ydata)
1659: rtx x, y;
1660: struct decomposition ydata;
1661: {
1662: struct decomposition xdata;
1663:
1664: if (ydata.reg_flag)
1665: return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, 0);
1666: if (ydata.safe)
1667: return 1;
1668:
1669: if (GET_CODE (y) != MEM)
1670: abort ();
1671: /* If Y is memory and X is not, Y can't affect X. */
1672: if (GET_CODE (x) != MEM)
1673: return 1;
1674:
1675: xdata = decompose (x);
1676:
1677: if (! rtx_equal_p (xdata.base, ydata.base))
1678: {
1679: /* If bases are distinct symbolic constants, there is no overlap. */
1680: if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base))
1681: return 1;
1682: /* Constants and stack slots never overlap. */
1683: if (CONSTANT_P (xdata.base)
1684: && (ydata.base == frame_pointer_rtx
1685: || ydata.base == stack_pointer_rtx))
1686: return 1;
1687: if (CONSTANT_P (ydata.base)
1688: && (xdata.base == frame_pointer_rtx
1689: || xdata.base == stack_pointer_rtx))
1690: return 1;
1691: /* If either base is variable, we don't know anything. */
1692: return 0;
1693: }
1694:
1695:
1696: return (xdata.start >= ydata.end || ydata.start >= xdata.end);
1697: }
1698:
1699: /* Main entry point of this file: search the body of INSN
1700: for values that need reloading and record them with push_reload.
1701: REPLACE nonzero means record also where the values occur
1702: so that subst_reloads can be used.
1703:
1704: IND_LEVELS says how many levels of indirection are supported by this
1705: machine; a value of zero means that a memory reference is not a valid
1706: memory address.
1707:
1708: LIVE_KNOWN says we have valid information about which hard
1709: regs are live at each point in the program; this is true when
1710: we are called from global_alloc but false when stupid register
1711: allocation has been done.
1712:
1713: RELOAD_REG_P if nonzero is a vector indexed by hard reg number
1714: which is nonnegative if the reg has been commandeered for reloading into.
1715: It is copied into STATIC_RELOAD_REG_P and referenced from there
1716: by various subroutines. */
1717:
1718: void
1719: find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
1720: rtx insn;
1721: int replace, ind_levels;
1722: int live_known;
1723: short *reload_reg_p;
1724: {
1725: rtx non_reloaded_operands[MAX_RECOG_OPERANDS];
1726: int n_non_reloaded_operands = 0;
1727: #ifdef REGISTER_CONSTRAINTS
1728:
1729: enum reload_modified { RELOAD_NOTHING, RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE };
1730:
1731: register int insn_code_number;
1732: register int i;
1733: int noperands;
1734: /* These are the constraints for the insn. We don't change them. */
1735: char *constraints1[MAX_RECOG_OPERANDS];
1736: /* These start out as the constraints for the insn
1737: and they are chewed up as we consider alternatives. */
1738: char *constraints[MAX_RECOG_OPERANDS];
1739: /* These are the preferred classes for an operand, or NO_REGS if it isn't
1740: a register. */
1741: enum reg_class preferred_class[MAX_RECOG_OPERANDS];
1742: char pref_or_nothing[MAX_RECOG_OPERANDS];
1743: /* Nonzero for a MEM operand whose entire address needs a reload. */
1744: int address_reloaded[MAX_RECOG_OPERANDS];
1745: int no_input_reloads = 0, no_output_reloads = 0;
1746: int n_alternatives;
1747: int this_alternative[MAX_RECOG_OPERANDS];
1748: char this_alternative_win[MAX_RECOG_OPERANDS];
1749: char this_alternative_offmemok[MAX_RECOG_OPERANDS];
1750: char this_alternative_earlyclobber[MAX_RECOG_OPERANDS];
1751: int this_alternative_matches[MAX_RECOG_OPERANDS];
1752: int swapped;
1753: int goal_alternative[MAX_RECOG_OPERANDS];
1754: int this_alternative_number;
1755: int goal_alternative_number;
1756: int operand_reloadnum[MAX_RECOG_OPERANDS];
1757: int goal_alternative_matches[MAX_RECOG_OPERANDS];
1758: int goal_alternative_matched[MAX_RECOG_OPERANDS];
1759: char goal_alternative_win[MAX_RECOG_OPERANDS];
1760: char goal_alternative_offmemok[MAX_RECOG_OPERANDS];
1761: char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS];
1762: int goal_alternative_swapped;
1763: enum reload_modified modified[MAX_RECOG_OPERANDS];
1764: int best;
1765: int commutative;
1766: char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
1767: rtx substed_operand[MAX_RECOG_OPERANDS];
1768: rtx body = PATTERN (insn);
1769: rtx set = single_set (insn);
1770: int goal_earlyclobber, this_earlyclobber;
1771: enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1772:
1773: this_insn = insn;
1774: this_insn_is_asm = 0; /* Tentative. */
1775: n_reloads = 0;
1776: n_replacements = 0;
1777: n_memlocs = 0;
1778: n_earlyclobbers = 0;
1779: replace_reloads = replace;
1780: hard_regs_live_known = live_known;
1781: static_reload_reg_p = reload_reg_p;
1782:
1783: /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads;
1784: neither are insns that SET cc0. Insns that use CC0 are not allowed
1785: to have any input reloads. */
1786: if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN)
1787: no_output_reloads = 1;
1788:
1789: #ifdef HAVE_cc0
1790: if (reg_referenced_p (cc0_rtx, PATTERN (insn)))
1791: no_input_reloads = 1;
1792: if (reg_set_p (cc0_rtx, PATTERN (insn)))
1793: no_output_reloads = 1;
1794: #endif
1795:
1796: /* Find what kind of insn this is. NOPERANDS gets number of operands.
1797: Make OPERANDS point to a vector of operand values.
1798: Make OPERAND_LOCS point to a vector of pointers to
1799: where the operands were found.
1800: Fill CONSTRAINTS and CONSTRAINTS1 with pointers to the
1801: constraint-strings for this insn.
1802: Return if the insn needs no reload processing. */
1803:
1804: switch (GET_CODE (body))
1805: {
1806: case USE:
1807: case CLOBBER:
1808: case ASM_INPUT:
1809: case ADDR_VEC:
1810: case ADDR_DIFF_VEC:
1811: return;
1812:
1813: case SET:
1814: /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it
1815: is cheap to move between them. If it is not, there may not be an insn
1816: to do the copy, so we may need a reload. */
1817: if (GET_CODE (SET_DEST (body)) == REG
1818: && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER
1819: && GET_CODE (SET_SRC (body)) == REG
1820: && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER
1821: && REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (SET_SRC (body))),
1822: REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2)
1823: return;
1824: case PARALLEL:
1825: case ASM_OPERANDS:
1826: noperands = asm_noperands (body);
1827: if (noperands >= 0)
1828: {
1829: /* This insn is an `asm' with operands. */
1830:
1831: insn_code_number = -1;
1832: this_insn_is_asm = 1;
1833:
1834: /* expand_asm_operands makes sure there aren't too many operands. */
1835: if (noperands > MAX_RECOG_OPERANDS)
1836: abort ();
1837:
1838: /* Now get the operand values and constraints out of the insn. */
1839:
1840: decode_asm_operands (body, recog_operand, recog_operand_loc,
1841: constraints, operand_mode);
1842: if (noperands > 0)
1843: {
1844: bcopy (constraints, constraints1, noperands * sizeof (char *));
1845: n_alternatives = n_occurrences (',', constraints[0]) + 1;
1846: for (i = 1; i < noperands; i++)
1.1.1.2 ! root 1847: if (n_alternatives != n_occurrences (',', constraints[i]) + 1)
1.1 root 1848: {
1849: error_for_asm (insn, "operand constraints differ in number of alternatives");
1850: /* Avoid further trouble with this insn. */
1851: PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
1852: n_reloads = 0;
1853: return;
1854: }
1855: }
1856: break;
1857: }
1858:
1859: default:
1860: /* Ordinary insn: recognize it, get the operands via insn_extract
1861: and get the constraints. */
1862:
1863: insn_code_number = recog_memoized (insn);
1864: if (insn_code_number < 0)
1865: fatal_insn_not_found (insn);
1866:
1867: noperands = insn_n_operands[insn_code_number];
1868: n_alternatives = insn_n_alternatives[insn_code_number];
1869: /* Just return "no reloads" if insn has no operands with constraints. */
1870: if (n_alternatives == 0)
1871: return;
1872: insn_extract (insn);
1873: for (i = 0; i < noperands; i++)
1874: {
1875: constraints[i] = constraints1[i]
1876: = insn_operand_constraint[insn_code_number][i];
1877: operand_mode[i] = insn_operand_mode[insn_code_number][i];
1878: }
1879: }
1880:
1881: if (noperands == 0)
1882: return;
1883:
1884: commutative = -1;
1885:
1886: /* If we will need to know, later, whether some pair of operands
1887: are the same, we must compare them now and save the result.
1888: Reloading the base and index registers will clobber them
1889: and afterward they will fail to match. */
1890:
1891: for (i = 0; i < noperands; i++)
1892: {
1893: register char *p;
1894: register int c;
1895:
1896: substed_operand[i] = recog_operand[i];
1897: p = constraints[i];
1898:
1899: /* Scan this operand's constraint to see if it should match another. */
1900:
1901: while (c = *p++)
1902: if (c == '%')
1903: {
1904: /* The last operand should not be marked commutative. This
1905: problem is hard to detect, so make it obvious by calling
1906: abort here. */
1907: if (i == noperands - 1)
1908: abort ();
1909:
1910: commutative = i;
1911: }
1912: else if (c >= '0' && c <= '9')
1913: {
1914: c -= '0';
1915: operands_match[c][i]
1916: = operands_match_p (recog_operand[c], recog_operand[i]);
1917: /* If C can be commuted with C+1, and C might need to match I,
1918: then C+1 might also need to match I. */
1919: if (commutative >= 0)
1920: {
1921: if (c == commutative || c == commutative + 1)
1922: {
1923: int other = c + (c == commutative ? 1 : -1);
1924: operands_match[other][i]
1925: = operands_match_p (recog_operand[other], recog_operand[i]);
1926: }
1927: if (i == commutative || i == commutative + 1)
1928: {
1929: int other = i + (i == commutative ? 1 : -1);
1930: operands_match[c][other]
1931: = operands_match_p (recog_operand[c], recog_operand[other]);
1932: }
1933: /* Note that C is supposed to be less than I.
1934: No need to consider altering both C and I
1935: because in that case we would alter one into the other. */
1936: }
1937: }
1938: }
1939:
1940: /* Examine each operand that is a memory reference or memory address
1941: and reload parts of the addresses into index registers.
1942: While we are at it, initialize the array `modified'.
1943: Also here any references to pseudo regs that didn't get hard regs
1944: but are equivalent to constants get replaced in the insn itself
1945: with those constants. Nobody will ever see them again.
1946:
1947: Finally, set up the preferred classes of each operand. */
1948:
1949: for (i = 0; i < noperands; i++)
1950: {
1951: register RTX_CODE code = GET_CODE (recog_operand[i]);
1952: modified[i] = RELOAD_READ;
1953: address_reloaded[i] = 0;
1954: preferred_class[i]
1955: = ((code == REG && REGNO (recog_operand[i]) > FIRST_PSEUDO_REGISTER)
1956: ? reg_preferred_class (REGNO (recog_operand[i])) : NO_REGS);
1957: pref_or_nothing[i]
1958: = (code == REG && REGNO (recog_operand[i]) > FIRST_PSEUDO_REGISTER
1959: && reg_preferred_or_nothing (REGNO (recog_operand[i])));
1960:
1961: if (constraints[i][0] == 'p')
1962: {
1963: find_reloads_address (VOIDmode, 0,
1964: recog_operand[i], recog_operand_loc[i],
1965: recog_operand[i], ind_levels);
1966: substed_operand[i] = recog_operand[i] = *recog_operand_loc[i];
1967: }
1968: else if (code == MEM)
1969: {
1970: if (find_reloads_address (GET_MODE (recog_operand[i]),
1971: recog_operand_loc[i],
1972: XEXP (recog_operand[i], 0),
1973: &XEXP (recog_operand[i], 0),
1974: recog_operand[i], ind_levels))
1975: address_reloaded[i] = 1;
1976: substed_operand[i] = recog_operand[i] = *recog_operand_loc[i];
1977: }
1978: else if (code == SUBREG)
1979: substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]
1980: = find_reloads_toplev (recog_operand[i], ind_levels,
1981: set != 0
1982: && &SET_DEST (set) == recog_operand_loc[i]);
1983: else if (code == REG)
1984: {
1985: /* This is equivalent to calling find_reloads_toplev.
1986: The code is duplicated for speed.
1987: When we find a pseudo always equivalent to a constant,
1988: we replace it by the constant. We must be sure, however,
1989: that we don't try to replace it in the insn in which it
1990: is being set. */
1991: register int regno = REGNO (recog_operand[i]);
1992: if (reg_equiv_constant[regno] != 0
1993: && (set == 0 || &SET_DEST (set) != recog_operand_loc[i]))
1994: substed_operand[i] = recog_operand[i]
1995: = reg_equiv_constant[regno];
1996: #if 0 /* This might screw code in reload1.c to delete prior output-reload
1997: that feeds this insn. */
1998: if (reg_equiv_mem[regno] != 0)
1999: substed_operand[i] = recog_operand[i]
2000: = reg_equiv_mem[regno];
2001: #endif
2002: if (reg_equiv_address[regno] != 0)
2003: {
2004: /* If reg_equiv_address is not a constant address, copy it,
2005: since it may be shared. */
2006: rtx address = reg_equiv_address[regno];
2007:
2008: if (rtx_varies_p (address))
2009: address = copy_rtx (address);
2010:
2011: /* If this is an output operand, we must output a CLOBBER
2012: after INSN so find_equiv_reg knows REGNO is being written. */
2013: if (constraints[i][0] == '='
2014: || constraints[i][0] == '+')
2015: emit_insn_after (gen_rtx (CLOBBER, VOIDmode, recog_operand[i]),
2016: insn);
2017:
2018: *recog_operand_loc[i] = recog_operand[i]
2019: = gen_rtx (MEM, GET_MODE (recog_operand[i]), address);
2020: RTX_UNCHANGING_P (recog_operand[i])
2021: = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
2022: find_reloads_address (GET_MODE (recog_operand[i]),
2023: recog_operand_loc[i],
2024: XEXP (recog_operand[i], 0),
2025: &XEXP (recog_operand[i], 0),
2026: recog_operand[i], ind_levels);
2027: substed_operand[i] = recog_operand[i] = *recog_operand_loc[i];
1.1.1.2 ! root 2028:
! 2029: /* This is no longer a psuedo register. To prevent later code
! 2030: from thinking it still is, we must reset the preferred_class
! 2031: to NO_REGS. */
! 2032: preferred_class[i] = NO_REGS;
1.1 root 2033: }
2034: }
2035: }
2036:
2037: /* If this is simply a copy from operand 1 to operand 0, merge the
2038: preferred classes for the operands. */
2039: if (set != 0 && noperands >= 2 && recog_operand[0] == SET_DEST (set)
2040: && recog_operand[1] == SET_SRC (set))
2041: {
2042: preferred_class[0] = preferred_class[1]
2043: = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]];
2044: pref_or_nothing[0] |= pref_or_nothing[1];
2045: pref_or_nothing[1] |= pref_or_nothing[0];
2046: }
2047:
2048: /* Now see what we need for pseudo-regs that didn't get hard regs
2049: or got the wrong kind of hard reg. For this, we must consider
2050: all the operands together against the register constraints. */
2051:
2052: best = MAX_RECOG_OPERANDS + 300;
2053:
2054: swapped = 0;
2055: goal_alternative_swapped = 0;
2056: try_swapped:
2057:
2058: /* The constraints are made of several alternatives.
2059: Each operand's constraint looks like foo,bar,... with commas
2060: separating the alternatives. The first alternatives for all
2061: operands go together, the second alternatives go together, etc.
2062:
2063: First loop over alternatives. */
2064:
2065: for (this_alternative_number = 0;
2066: this_alternative_number < n_alternatives;
2067: this_alternative_number++)
2068: {
2069: /* Loop over operands for one constraint alternative. */
2070: /* LOSERS counts those that don't fit this alternative
2071: and would require loading. */
2072: int losers = 0;
2073: /* BAD is set to 1 if it some operand can't fit this alternative
2074: even after reloading. */
2075: int bad = 0;
2076: /* REJECT is a count of how undesirable this alternative says it is
2077: if any reloading is required. If the alternative matches exactly
2078: then REJECT is ignored, but otherwise it gets this much
2079: counted against it in addition to the reloading needed. Each
2080: ? counts three times here since we want the disparaging caused by
2081: a bad register class to only count 1/3 as much. */
2082: int reject = 0;
2083:
2084: this_earlyclobber = 0;
2085:
2086: for (i = 0; i < noperands; i++)
2087: {
2088: register char *p = constraints[i];
2089: register int win = 0;
2090: /* 0 => this operand can be reloaded somehow for this alternative */
2091: int badop = 1;
2092: /* 0 => this operand can be reloaded if the alternative allows regs. */
2093: int winreg = 0;
2094: int c;
2095: register rtx operand = recog_operand[i];
2096: int offset = 0;
2097: /* Nonzero means this is a MEM that must be reloaded into a reg
2098: regardless of what the constraint says. */
2099: int force_reload = 0;
2100: int offmemok = 0;
2101: int earlyclobber = 0;
2102:
2103: /* If the operand is a SUBREG, extract
2104: the REG or MEM (or maybe even a constant) within.
2105: (Constants can occur as a result of reg_equiv_constant.) */
2106:
2107: while (GET_CODE (operand) == SUBREG)
2108: {
2109: offset += SUBREG_WORD (operand);
2110: operand = SUBREG_REG (operand);
2111: /* Force reload if this is not a register or if there may may
2112: be a problem accessing the register in the outer mode. */
2113: if (GET_CODE (operand) != REG
2114: #ifdef BYTE_LOADS_ZERO_EXTEND
2115: /* Nonparadoxical subreg of a pseudoreg.
2116: Don't to load the full width if on this machine
2117: we expected the fetch to zero-extend. */
2118: || ((GET_MODE_SIZE (operand_mode[i])
2119: > GET_MODE_SIZE (GET_MODE (operand)))
2120: && REGNO (operand) >= FIRST_PSEUDO_REGISTER)
2121: #endif /* BYTE_LOADS_ZERO_EXTEND */
2122: /* Subreg of a hard reg which can't handle the subreg's mode
2123: or which would handle that mode in the wrong number of
2124: registers for subregging to work. */
2125: || (REGNO (operand) < FIRST_PSEUDO_REGISTER
2126: && (! HARD_REGNO_MODE_OK (REGNO (operand),
2127: operand_mode[i])
2128: || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD
2129: && (GET_MODE_SIZE (GET_MODE (operand))
2130: > UNITS_PER_WORD)
2131: && ((GET_MODE_SIZE (GET_MODE (operand))
2132: / UNITS_PER_WORD)
2133: != HARD_REGNO_NREGS (REGNO (operand),
2134: GET_MODE (operand)))))))
2135: force_reload = 1;
2136: }
2137:
2138: this_alternative[i] = (int) NO_REGS;
2139: this_alternative_win[i] = 0;
2140: this_alternative_offmemok[i] = 0;
2141: this_alternative_earlyclobber[i] = 0;
2142: this_alternative_matches[i] = -1;
2143:
2144: /* An empty constraint or empty alternative
2145: allows anything which matched the pattern. */
2146: if (*p == 0 || *p == ',')
2147: win = 1, badop = 0;
2148:
2149: /* Scan this alternative's specs for this operand;
2150: set WIN if the operand fits any letter in this alternative.
2151: Otherwise, clear BADOP if this operand could
2152: fit some letter after reloads,
2153: or set WINREG if this operand could fit after reloads
2154: provided the constraint allows some registers. */
2155:
2156: while (*p && (c = *p++) != ',')
2157: switch (c)
2158: {
2159: case '=':
2160: modified[i] = RELOAD_WRITE;
2161: break;
2162:
2163: case '+':
2164: modified[i] = RELOAD_READ_WRITE;
2165: break;
2166:
2167: case '*':
2168: break;
2169:
2170: case '%':
2171: commutative = i;
2172: break;
2173:
2174: case '?':
2175: reject += 3;
2176: break;
2177:
2178: case '!':
2179: reject = 300;
2180: break;
2181:
2182: case '#':
2183: /* Ignore rest of this alternative as far as
2184: reloading is concerned. */
2185: while (*p && *p != ',') p++;
2186: break;
2187:
2188: case '0':
2189: case '1':
2190: case '2':
2191: case '3':
2192: case '4':
2193: c -= '0';
2194: this_alternative_matches[i] = c;
2195: /* We are supposed to match a previous operand.
2196: If we do, we win if that one did.
2197: If we do not, count both of the operands as losers.
2198: (This is too conservative, since most of the time
2199: only a single reload insn will be needed to make
2200: the two operands win. As a result, this alternative
2201: may be rejected when it is actually desirable.) */
2202: if ((swapped && (c != commutative || i != commutative + 1))
2203: /* If we are matching as if two operands were swapped,
2204: also pretend that operands_match had been computed
2205: with swapped.
2206: But if I is the second of those and C is the first,
2207: don't exchange them, because operands_match is valid
2208: only on one side of its diagonal. */
2209: ? (operands_match
2210: [(c == commutative || c == commutative + 1)
2211: ? 2*commutative + 1 - c : c]
2212: [(i == commutative || i == commutative + 1)
2213: ? 2*commutative + 1 - i : i])
2214: : operands_match[c][i])
2215: win = this_alternative_win[c];
2216: else
2217: {
2218: /* Operands don't match. */
2219: rtx value;
2220: /* Retroactively mark the operand we had to match
2221: as a loser, if it wasn't already. */
2222: if (this_alternative_win[c])
2223: losers++;
2224: this_alternative_win[c] = 0;
2225: if (this_alternative[c] == (int) NO_REGS)
2226: bad = 1;
2227: /* But count the pair only once in the total badness of
2228: this alternative, if the pair can be a dummy reload. */
2229: value
2230: = find_dummy_reload (recog_operand[i], recog_operand[c],
2231: recog_operand_loc[i], recog_operand_loc[c],
2232: this_alternative[c], -1);
2233:
2234: if (value != 0)
2235: losers--;
2236: }
2237: /* This can be fixed with reloads if the operand
2238: we are supposed to match can be fixed with reloads. */
2239: badop = 0;
2240: this_alternative[i] = this_alternative[c];
2241: break;
2242:
2243: case 'p':
2244: /* All necessary reloads for an address_operand
2245: were handled in find_reloads_address. */
2246: this_alternative[i] = (int) ALL_REGS;
2247: win = 1;
2248: break;
2249:
2250: case 'm':
2251: if (force_reload)
2252: break;
2253: if (GET_CODE (operand) == MEM
2254: || (GET_CODE (operand) == REG
2255: && REGNO (operand) >= FIRST_PSEUDO_REGISTER
2256: && reg_renumber[REGNO (operand)] < 0))
2257: win = 1;
2258: if (CONSTANT_P (operand))
2259: badop = 0;
2260: break;
2261:
2262: case '<':
2263: if (GET_CODE (operand) == MEM
2264: && ! address_reloaded[i]
2265: && (GET_CODE (XEXP (operand, 0)) == PRE_DEC
2266: || GET_CODE (XEXP (operand, 0)) == POST_DEC))
2267: win = 1;
2268: break;
2269:
2270: case '>':
2271: if (GET_CODE (operand) == MEM
2272: && ! address_reloaded[i]
2273: && (GET_CODE (XEXP (operand, 0)) == PRE_INC
2274: || GET_CODE (XEXP (operand, 0)) == POST_INC))
2275: win = 1;
2276: break;
2277:
2278: /* Memory operand whose address is not offsettable. */
2279: case 'V':
2280: if (force_reload)
2281: break;
2282: if (GET_CODE (operand) == MEM
2283: && ! (ind_levels ? offsettable_memref_p (operand)
2284: : offsettable_nonstrict_memref_p (operand))
2285: /* Certain mem addresses will become offsettable
2286: after they themselves are reloaded. This is important;
2287: we don't want our own handling of unoffsettables
2288: to override the handling of reg_equiv_address. */
2289: && !(GET_CODE (XEXP (operand, 0)) == REG
2290: && (ind_levels == 0
2291: || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)))
2292: win = 1;
2293: break;
2294:
2295: /* Memory operand whose address is offsettable. */
2296: case 'o':
2297: if (force_reload)
2298: break;
2299: if ((GET_CODE (operand) == MEM
2300: /* If IND_LEVELS, find_reloads_address won't reload a
2301: pseudo that didn't get a hard reg, so we have to
2302: reject that case. */
2303: && (ind_levels ? offsettable_memref_p (operand)
2304: : offsettable_nonstrict_memref_p (operand)))
2305: /* Certain mem addresses will become offsettable
2306: after they themselves are reloaded. This is important;
2307: we don't want our own handling of unoffsettables
2308: to override the handling of reg_equiv_address. */
2309: || (GET_CODE (operand) == MEM
2310: && GET_CODE (XEXP (operand, 0)) == REG
2311: && (ind_levels == 0
2312: || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))
2313: || (GET_CODE (operand) == REG
2314: && REGNO (operand) >= FIRST_PSEUDO_REGISTER
2315: && reg_renumber[REGNO (operand)] < 0))
2316: win = 1;
2317: if (CONSTANT_P (operand) || GET_CODE (operand) == MEM)
2318: badop = 0;
2319: offmemok = 1;
2320: break;
2321:
2322: case '&':
2323: /* Output operand that is stored before the need for the
2324: input operands (and their index registers) is over. */
2325: earlyclobber = 1, this_earlyclobber = 1;
2326: break;
2327:
2328: case 'E':
2329: /* Match any floating double constant, but only if
2330: we can examine the bits of it reliably. */
2331: if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2332: || HOST_BITS_PER_INT != BITS_PER_WORD)
2333: && GET_MODE (operand) != VOIDmode && ! flag_pretend_float)
2334: break;
2335: if (GET_CODE (operand) == CONST_DOUBLE)
2336: win = 1;
2337: break;
2338:
2339: case 'F':
2340: if (GET_CODE (operand) == CONST_DOUBLE)
2341: win = 1;
2342: break;
2343:
2344: case 'G':
2345: case 'H':
2346: if (GET_CODE (operand) == CONST_DOUBLE
2347: && CONST_DOUBLE_OK_FOR_LETTER_P (operand, c))
2348: win = 1;
2349: break;
2350:
2351: case 's':
2352: if (GET_CODE (operand) == CONST_INT
2353: || (GET_CODE (operand) == CONST_DOUBLE
2354: && GET_MODE (operand) == VOIDmode))
2355: break;
2356: case 'i':
2357: if (CONSTANT_P (operand)
2358: #ifdef LEGITIMATE_PIC_OPERAND_P
2359: && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand))
2360: #endif
2361: )
2362: win = 1;
2363: break;
2364:
2365: case 'n':
2366: if (GET_CODE (operand) == CONST_INT
2367: || (GET_CODE (operand) == CONST_DOUBLE
2368: && GET_MODE (operand) == VOIDmode))
2369: win = 1;
2370: break;
2371:
2372: case 'I':
2373: case 'J':
2374: case 'K':
2375: case 'L':
2376: case 'M':
2377: case 'N':
2378: case 'O':
2379: case 'P':
2380: if (GET_CODE (operand) == CONST_INT
2381: && CONST_OK_FOR_LETTER_P (INTVAL (operand), c))
2382: win = 1;
2383: break;
2384:
2385: case 'X':
2386: win = 1;
2387: break;
2388:
2389: case 'g':
2390: if (! force_reload
2391: /* A PLUS is never a valid operand, but reload can make
2392: it from a register when eliminating registers. */
2393: && GET_CODE (operand) != PLUS
2394: /* A SCRATCH is not a valid operand. */
2395: && GET_CODE (operand) != SCRATCH
2396: #ifdef LEGITIMATE_PIC_OPERAND_P
2397: && (! CONSTANT_P (operand)
2398: || ! flag_pic
2399: || LEGITIMATE_PIC_OPERAND_P (operand))
2400: #endif
2401: && (GENERAL_REGS == ALL_REGS
2402: || GET_CODE (operand) != REG
2403: || (REGNO (operand) >= FIRST_PSEUDO_REGISTER
2404: && reg_renumber[REGNO (operand)] < 0)))
2405: win = 1;
2406: /* Drop through into 'r' case */
2407:
2408: case 'r':
2409: this_alternative[i]
2410: = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS];
2411: goto reg;
2412:
2413: #ifdef EXTRA_CONSTRAINT
2414: case 'Q':
2415: case 'R':
2416: case 'S':
2417: case 'T':
2418: case 'U':
2419: if (EXTRA_CONSTRAINT (operand, c))
2420: win = 1;
2421: break;
2422: #endif
2423:
2424: default:
2425: this_alternative[i]
2426: = (int) reg_class_subunion[this_alternative[i]][(int) REG_CLASS_FROM_LETTER (c)];
2427:
2428: reg:
2429: if (GET_MODE (operand) == BLKmode)
2430: break;
2431: winreg = 1;
2432: if (GET_CODE (operand) == REG
2433: && reg_fits_class_p (operand, this_alternative[i],
2434: offset, GET_MODE (recog_operand[i])))
2435: win = 1;
2436: break;
2437: }
2438:
2439: constraints[i] = p;
2440:
2441: /* If this operand could be handled with a reg,
2442: and some reg is allowed, then this operand can be handled. */
2443: if (winreg && this_alternative[i] != (int) NO_REGS)
2444: badop = 0;
2445:
2446: /* Record which operands fit this alternative. */
2447: this_alternative_earlyclobber[i] = earlyclobber;
2448: if (win && ! force_reload)
2449: this_alternative_win[i] = 1;
2450: else
2451: {
2452: this_alternative_offmemok[i] = offmemok;
2453: losers++;
2454: if (badop)
2455: bad = 1;
2456: /* Alternative loses if it has no regs for a reg operand. */
2457: if (GET_CODE (operand) == REG
2458: && this_alternative[i] == (int) NO_REGS
2459: && this_alternative_matches[i] < 0)
2460: bad = 1;
2461:
2462: /* Alternative loses if it requires a type of reload not
2463: permitted for this insn. We can always reload SCRATCH
2464: and objects with a REG_UNUSED note. */
2465: if (GET_CODE (operand) != SCRATCH && modified[i] != RELOAD_READ
2466: && no_output_reloads
2467: && ! find_reg_note (insn, REG_UNUSED, operand))
2468: bad = 1;
2469: else if (modified[i] != RELOAD_WRITE && no_input_reloads)
2470: bad = 1;
2471:
2472: /* We prefer to reload pseudos over reloading other things,
2473: since such reloads may be able to be eliminated later.
2474: If we are reloading a SCRATCH, we won't be generating any
2475: insns, just using a register, so it is also preferred.
2476: So bump REJECT in other cases. */
2477: if (GET_CODE (operand) != REG && GET_CODE (operand) != SCRATCH)
2478: reject++;
2479: }
2480:
2481: /* If this operand is a pseudo register that didn't get a hard
2482: reg and this alternative accepts some register, see if the
2483: class that we want is a subset of the preferred class for this
2484: register. If not, but it intersects that class, use the
2485: preferred class instead. If it does not intersect the preferred
2486: class, show that usage of this alternative should be discouraged;
2487: it will be discouraged more still if the register is `preferred
2488: or nothing'. We do this because it increases the chance of
2489: reusing our spill register in a later insn and avoiding a pair
2490: of memory stores and loads.
2491:
2492: Don't bother with this if this alternative will accept this
2493: operand.
2494:
2495: Don't do this if the preferred class has only one register
2496: because we might otherwise exhaust the class. */
2497:
2498:
2499: if (! win && this_alternative[i] != (int) NO_REGS
2500: && reg_class_size[(int) preferred_class[i]] > 1)
2501: {
2502: if (! reg_class_subset_p (this_alternative[i],
2503: preferred_class[i]))
2504: {
2505: /* Since we don't have a way of forming the intersection,
2506: we just do something special if the preferred class
2507: is a subset of the class we have; that's the most
2508: common case anyway. */
2509: if (reg_class_subset_p (preferred_class[i],
2510: this_alternative[i]))
2511: this_alternative[i] = (int) preferred_class[i];
2512: else
2513: reject += (1 + pref_or_nothing[i]);
2514: }
2515: }
2516: }
2517:
2518: /* Now see if any output operands that are marked "earlyclobber"
2519: in this alternative conflict with any input operands
2520: or any memory addresses. */
2521:
2522: for (i = 0; i < noperands; i++)
2523: if (this_alternative_earlyclobber[i]
2524: && this_alternative_win[i])
2525: {
2526: struct decomposition early_data;
2527: int j;
2528:
2529: early_data = decompose (recog_operand[i]);
2530:
2531: if (modified[i] == RELOAD_READ)
2532: {
2533: if (this_insn_is_asm)
2534: warning_for_asm (this_insn,
2535: "`&' constraint used with input operand");
2536: else
2537: abort ();
2538: continue;
2539: }
2540:
2541: if (this_alternative[i] == NO_REGS)
2542: {
2543: this_alternative_earlyclobber[i] = 0;
2544: if (this_insn_is_asm)
2545: error_for_asm (this_insn,
2546: "`&' constraint used with no register class");
2547: else
2548: abort ();
2549: }
2550:
2551: for (j = 0; j < noperands; j++)
2552: /* Is this an input operand or a memory ref? */
2553: if ((GET_CODE (recog_operand[j]) == MEM
2554: || modified[j] != RELOAD_WRITE)
2555: && j != i
2556: /* Ignore things like match_operator operands. */
2557: && *constraints1[j] != 0
2558: /* Don't count an input operand that is constrained to match
2559: the early clobber operand. */
2560: && ! (this_alternative_matches[j] == i
2561: && rtx_equal_p (recog_operand[i], recog_operand[j]))
2562: /* Is it altered by storing the earlyclobber operand? */
2563: && !immune_p (recog_operand[j], recog_operand[i], early_data))
2564: {
2565: /* If the output is in a single-reg class,
2566: it's costly to reload it, so reload the input instead. */
2567: if (reg_class_size[this_alternative[i]] == 1
2568: && (GET_CODE (recog_operand[j]) == REG
2569: || GET_CODE (recog_operand[j]) == SUBREG))
2570: {
2571: losers++;
2572: this_alternative_win[j] = 0;
2573: }
2574: else
2575: break;
2576: }
2577: /* If an earlyclobber operand conflicts with something,
2578: it must be reloaded, so request this and count the cost. */
2579: if (j != noperands)
2580: {
2581: losers++;
2582: this_alternative_win[i] = 0;
2583: for (j = 0; j < noperands; j++)
2584: if (this_alternative_matches[j] == i
2585: && this_alternative_win[j])
2586: {
2587: this_alternative_win[j] = 0;
2588: losers++;
2589: }
2590: }
2591: }
2592:
2593: /* If one alternative accepts all the operands, no reload required,
2594: choose that alternative; don't consider the remaining ones. */
2595: if (losers == 0)
2596: {
2597: /* Unswap these so that they are never swapped at `finish'. */
2598: if (commutative >= 0)
2599: {
2600: recog_operand[commutative] = substed_operand[commutative];
2601: recog_operand[commutative + 1]
2602: = substed_operand[commutative + 1];
2603: }
2604: for (i = 0; i < noperands; i++)
2605: {
2606: goal_alternative_win[i] = 1;
2607: goal_alternative[i] = this_alternative[i];
2608: goal_alternative_offmemok[i] = this_alternative_offmemok[i];
2609: goal_alternative_matches[i] = this_alternative_matches[i];
2610: goal_alternative_earlyclobber[i]
2611: = this_alternative_earlyclobber[i];
2612: }
2613: goal_alternative_number = this_alternative_number;
2614: goal_alternative_swapped = swapped;
2615: goal_earlyclobber = this_earlyclobber;
2616: goto finish;
2617: }
2618:
2619: /* REJECT, set by the ! and ? constraint characters and when a register
2620: would be reloaded into a non-preferred class, discourages the use of
2621: this alternative for a reload goal. REJECT is incremented by three
2622: for each ? and one for each non-preferred class. */
2623: losers = losers * 3 + reject;
2624:
2625: /* If this alternative can be made to work by reloading,
2626: and it needs less reloading than the others checked so far,
2627: record it as the chosen goal for reloading. */
2628: if (! bad && best > losers)
2629: {
2630: for (i = 0; i < noperands; i++)
2631: {
2632: goal_alternative[i] = this_alternative[i];
2633: goal_alternative_win[i] = this_alternative_win[i];
2634: goal_alternative_offmemok[i] = this_alternative_offmemok[i];
2635: goal_alternative_matches[i] = this_alternative_matches[i];
2636: goal_alternative_earlyclobber[i]
2637: = this_alternative_earlyclobber[i];
2638: }
2639: goal_alternative_swapped = swapped;
2640: best = losers;
2641: goal_alternative_number = this_alternative_number;
2642: goal_earlyclobber = this_earlyclobber;
2643: }
2644: }
2645:
2646: /* If insn is commutative (it's safe to exchange a certain pair of operands)
2647: then we need to try each alternative twice,
2648: the second time matching those two operands
2649: as if we had exchanged them.
2650: To do this, really exchange them in operands.
2651:
2652: If we have just tried the alternatives the second time,
2653: return operands to normal and drop through. */
2654:
2655: if (commutative >= 0)
2656: {
2657: swapped = !swapped;
2658: if (swapped)
2659: {
2660: register enum reg_class tclass;
2661: register int t;
2662:
2663: recog_operand[commutative] = substed_operand[commutative + 1];
2664: recog_operand[commutative + 1] = substed_operand[commutative];
2665:
2666: tclass = preferred_class[commutative];
2667: preferred_class[commutative] = preferred_class[commutative + 1];
2668: preferred_class[commutative + 1] = tclass;
2669:
2670: t = pref_or_nothing[commutative];
2671: pref_or_nothing[commutative] = pref_or_nothing[commutative + 1];
2672: pref_or_nothing[commutative + 1] = t;
2673:
2674: bcopy (constraints1, constraints, noperands * sizeof (char *));
2675: goto try_swapped;
2676: }
2677: else
2678: {
2679: recog_operand[commutative] = substed_operand[commutative];
2680: recog_operand[commutative + 1] = substed_operand[commutative + 1];
2681: }
2682: }
2683:
2684: /* The operands don't meet the constraints.
2685: goal_alternative describes the alternative
2686: that we could reach by reloading the fewest operands.
2687: Reload so as to fit it. */
2688:
2689: if (best == MAX_RECOG_OPERANDS + 300)
2690: {
2691: /* No alternative works with reloads?? */
2692: if (insn_code_number >= 0)
2693: abort ();
2694: error_for_asm (insn, "inconsistent operand constraints in an `asm'");
2695: /* Avoid further trouble with this insn. */
2696: PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
2697: n_reloads = 0;
2698: return;
2699: }
2700:
2701: /* Jump to `finish' from above if all operands are valid already.
2702: In that case, goal_alternative_win is all 1. */
2703: finish:
2704:
2705: /* Right now, for any pair of operands I and J that are required to match,
2706: with I < J,
2707: goal_alternative_matches[J] is I.
2708: Set up goal_alternative_matched as the inverse function:
2709: goal_alternative_matched[I] = J. */
2710:
2711: for (i = 0; i < noperands; i++)
2712: goal_alternative_matched[i] = -1;
2713:
2714: for (i = 0; i < noperands; i++)
2715: if (! goal_alternative_win[i]
2716: && goal_alternative_matches[i] >= 0)
2717: goal_alternative_matched[goal_alternative_matches[i]] = i;
2718:
2719: /* If the best alternative is with operands 1 and 2 swapped,
2720: consider them swapped before reporting the reloads. */
2721:
2722: if (goal_alternative_swapped)
2723: {
2724: register rtx tem;
2725:
2726: tem = substed_operand[commutative];
2727: substed_operand[commutative] = substed_operand[commutative + 1];
2728: substed_operand[commutative + 1] = tem;
2729: tem = recog_operand[commutative];
2730: recog_operand[commutative] = recog_operand[commutative + 1];
2731: recog_operand[commutative + 1] = tem;
2732: }
2733:
2734: /* Perform whatever substitutions on the operands we are supposed
2735: to make due to commutativity or replacement of registers
2736: with equivalent constants or memory slots. */
2737:
2738: for (i = 0; i < noperands; i++)
2739: {
2740: *recog_operand_loc[i] = substed_operand[i];
2741: /* While we are looping on operands, initialize this. */
2742: operand_reloadnum[i] = -1;
2743: }
2744:
2745: /* Any constants that aren't allowed and can't be reloaded
2746: into registers are here changed into memory references. */
2747: for (i = 0; i < noperands; i++)
2748: if (! goal_alternative_win[i]
2749: && CONSTANT_P (recog_operand[i])
2750: && (PREFERRED_RELOAD_CLASS (recog_operand[i],
2751: (enum reg_class) goal_alternative[i])
2752: == NO_REGS)
2753: && operand_mode[i] != VOIDmode)
2754: {
2755: *recog_operand_loc[i] = recog_operand[i]
2756: = find_reloads_toplev (force_const_mem (operand_mode[i],
2757: recog_operand[i]),
2758: ind_levels, 0);
2759: if (alternative_allows_memconst (constraints1[i],
2760: goal_alternative_number))
2761: goal_alternative_win[i] = 1;
2762: }
2763:
2764: /* Now record reloads for all the operands that need them. */
2765: for (i = 0; i < noperands; i++)
2766: if (! goal_alternative_win[i])
2767: {
2768: /* Operands that match previous ones have already been handled. */
2769: if (goal_alternative_matches[i] >= 0)
2770: ;
2771: /* Handle an operand with a nonoffsettable address
2772: appearing where an offsettable address will do
2773: by reloading the address into a base register. */
2774: else if (goal_alternative_matched[i] == -1
2775: && goal_alternative_offmemok[i]
2776: && GET_CODE (recog_operand[i]) == MEM)
2777: {
2778: operand_reloadnum[i]
2779: = push_reload (XEXP (recog_operand[i], 0), 0,
2780: &XEXP (recog_operand[i], 0), 0,
2781: BASE_REG_CLASS, GET_MODE (XEXP (recog_operand[i], 0)),
2782: VOIDmode, 0, 0, 0);
2783: reload_inc[operand_reloadnum[i]]
2784: = GET_MODE_SIZE (GET_MODE (recog_operand[i]));
2785: }
2786: else if (goal_alternative_matched[i] == -1)
2787: operand_reloadnum[i] =
2788: push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0,
2789: modified[i] != RELOAD_READ ? recog_operand[i] : 0,
2790: modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0,
2791: modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0,
2792: (enum reg_class) goal_alternative[i],
2793: (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]),
2794: (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]),
2795: (insn_code_number < 0 ? 0
2796: : insn_operand_strict_low[insn_code_number][i]),
2797: 0, 0);
2798: /* In a matching pair of operands, one must be input only
2799: and the other must be output only.
2800: Pass the input operand as IN and the other as OUT. */
2801: else if (modified[i] == RELOAD_READ
2802: && modified[goal_alternative_matched[i]] == RELOAD_WRITE)
2803: {
2804: operand_reloadnum[i]
2805: = push_reload (recog_operand[i],
2806: recog_operand[goal_alternative_matched[i]],
2807: recog_operand_loc[i],
2808: recog_operand_loc[goal_alternative_matched[i]],
2809: (enum reg_class) goal_alternative[i],
2810: operand_mode[i],
2811: operand_mode[goal_alternative_matched[i]],
2812: 0, 0, 0);
2813: operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum;
2814: }
2815: else if (modified[i] == RELOAD_WRITE
2816: && modified[goal_alternative_matched[i]] == RELOAD_READ)
2817: {
2818: operand_reloadnum[goal_alternative_matched[i]]
2819: = push_reload (recog_operand[goal_alternative_matched[i]],
2820: recog_operand[i],
2821: recog_operand_loc[goal_alternative_matched[i]],
2822: recog_operand_loc[i],
2823: (enum reg_class) goal_alternative[i],
2824: operand_mode[goal_alternative_matched[i]],
2825: operand_mode[i],
2826: 0, 0, 0);
2827: operand_reloadnum[i] = output_reloadnum;
2828: }
2829: else if (insn_code_number >= 0)
2830: abort ();
2831: else
2832: {
2833: error_for_asm (insn, "inconsistent operand constraints in an `asm'");
2834: /* Avoid further trouble with this insn. */
2835: PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
2836: n_reloads = 0;
2837: return;
2838: }
2839: }
2840: else if (goal_alternative_matched[i] < 0
2841: && goal_alternative_matches[i] < 0
2842: && optimize)
2843: {
2844: rtx operand = recog_operand[i];
2845: /* For each non-matching operand that's a pseudo-register
2846: that didn't get a hard register, make an optional reload.
2847: This may get done even if the insn needs no reloads otherwise. */
2848: /* (It would be safe to make an optional reload for a matching pair
2849: of operands, but we don't bother yet.) */
2850: while (GET_CODE (operand) == SUBREG)
2851: operand = XEXP (operand, 0);
2852: if (GET_CODE (operand) == REG
2853: && REGNO (operand) >= FIRST_PSEUDO_REGISTER
2854: && reg_renumber[REGNO (operand)] < 0
2855: && (enum reg_class) goal_alternative[i] != NO_REGS
2856: /* Don't make optional output reloads for jump insns
2857: (such as aobjeq on the vax). */
2858: && (modified[i] == RELOAD_READ
2859: || GET_CODE (insn) != JUMP_INSN))
2860: operand_reloadnum[i]
2861: = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0,
2862: modified[i] != RELOAD_READ ? recog_operand[i] : 0,
2863: modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0,
2864: modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0,
2865: (enum reg_class) goal_alternative[i],
2866: (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]),
2867: (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]),
2868: (insn_code_number < 0 ? 0
2869: : insn_operand_strict_low[insn_code_number][i]),
2870: 1, 0);
2871: /* Make an optional reload for an explicit mem ref. */
2872: else if (GET_CODE (operand) == MEM
2873: && (enum reg_class) goal_alternative[i] != NO_REGS
2874: /* Don't make optional output reloads for jump insns
2875: (such as aobjeq on the vax). */
2876: && (modified[i] == RELOAD_READ
2877: || GET_CODE (insn) != JUMP_INSN))
2878: operand_reloadnum[i]
2879: = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0,
2880: modified[i] != RELOAD_READ ? recog_operand[i] : 0,
2881: modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0,
2882: modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0,
2883: (enum reg_class) goal_alternative[i],
2884: (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]),
2885: (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]),
2886: (insn_code_number < 0 ? 0
2887: : insn_operand_strict_low[insn_code_number][i]),
2888: 1, 0);
2889: else
2890: non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i];
2891: }
2892: else if (goal_alternative_matched[i] < 0
2893: && goal_alternative_matches[i] < 0)
2894: non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i];
2895:
2896: /* Record the values of the earlyclobber operands for the caller. */
2897: if (goal_earlyclobber)
2898: for (i = 0; i < noperands; i++)
2899: if (goal_alternative_earlyclobber[i])
2900: reload_earlyclobbers[n_earlyclobbers++] = recog_operand[i];
2901:
2902: /* If this insn pattern contains any MATCH_DUP's, make sure that
2903: they will be substituted if the operands they match are substituted.
2904: Also do now any substitutions we already did on the operands.
2905:
2906: Don't do this if we aren't making replacements because we might be
2907: propagating things allocated by frame pointer elimination into places
2908: it doesn't expect. */
2909:
2910: if (insn_code_number >= 0 && replace)
2911: for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
2912: {
2913: int opno = recog_dup_num[i];
2914: *recog_dup_loc[i] = *recog_operand_loc[opno];
2915: if (operand_reloadnum[opno] >= 0)
2916: push_replacement (recog_dup_loc[i], operand_reloadnum[opno],
2917: insn_operand_mode[insn_code_number][opno]);
2918: }
2919:
2920: #if 0
2921: /* This loses because reloading of prior insns can invalidate the equivalence
2922: (or at least find_equiv_reg isn't smart enough to find it any more),
2923: causing this insn to need more reload regs than it needed before.
2924: It may be too late to make the reload regs available.
2925: Now this optimization is done safely in choose_reload_regs. */
2926:
2927: /* For each reload of a reg into some other class of reg,
2928: search for an existing equivalent reg (same value now) in the right class.
2929: We can use it as long as we don't need to change its contents. */
2930: for (i = 0; i < n_reloads; i++)
2931: if (reload_reg_rtx[i] == 0
2932: && reload_in[i] != 0
2933: && GET_CODE (reload_in[i]) == REG
2934: && reload_out[i] == 0)
2935: {
2936: reload_reg_rtx[i]
2937: = find_equiv_reg (reload_in[i], insn, reload_reg_class[i], -1,
2938: static_reload_reg_p, 0, reload_inmode[i]);
2939: /* Prevent generation of insn to load the value
2940: because the one we found already has the value. */
2941: if (reload_reg_rtx[i])
2942: reload_in[i] = reload_reg_rtx[i];
2943: }
2944: #endif
2945:
2946: #else /* no REGISTER_CONSTRAINTS */
2947: int noperands;
2948: int insn_code_number;
2949: int goal_earlyclobber = 0; /* Always 0, to make combine_reloads happen. */
2950: register int i;
2951: rtx body = PATTERN (insn);
2952:
2953: n_reloads = 0;
2954: n_replacements = 0;
2955: n_earlyclobbers = 0;
2956: replace_reloads = replace;
2957: this_insn = insn;
2958:
2959: /* Find what kind of insn this is. NOPERANDS gets number of operands.
2960: Store the operand values in RECOG_OPERAND and the locations
2961: of the words in the insn that point to them in RECOG_OPERAND_LOC.
2962: Return if the insn needs no reload processing. */
2963:
2964: switch (GET_CODE (body))
2965: {
2966: case USE:
2967: case CLOBBER:
2968: case ASM_INPUT:
2969: case ADDR_VEC:
2970: case ADDR_DIFF_VEC:
2971: return;
2972:
2973: case PARALLEL:
2974: case SET:
2975: noperands = asm_noperands (body);
2976: if (noperands >= 0)
2977: {
2978: /* This insn is an `asm' with operands.
2979: First, find out how many operands, and allocate space. */
2980:
2981: insn_code_number = -1;
2982: /* ??? This is a bug! ???
2983: Give up and delete this insn if it has too many operands. */
2984: if (noperands > MAX_RECOG_OPERANDS)
2985: abort ();
2986:
2987: /* Now get the operand values out of the insn. */
2988:
2989: decode_asm_operands (body, recog_operand, recog_operand_loc, 0, 0);
2990: break;
2991: }
2992:
2993: default:
2994: /* Ordinary insn: recognize it, allocate space for operands and
2995: constraints, and get them out via insn_extract. */
2996:
2997: insn_code_number = recog_memoized (insn);
2998: noperands = insn_n_operands[insn_code_number];
2999: insn_extract (insn);
3000: }
3001:
3002: if (noperands == 0)
3003: return;
3004:
3005: for (i = 0; i < noperands; i++)
3006: {
3007: register RTX_CODE code = GET_CODE (recog_operand[i]);
3008: int is_set_dest = GET_CODE (body) == SET && (i == 0);
3009:
3010: if (insn_code_number >= 0)
3011: if (insn_operand_address_p[insn_code_number][i])
3012: find_reloads_address (VOIDmode, 0,
3013: recog_operand[i], recog_operand_loc[i],
3014: recog_operand[i], ind_levels);
3015: if (code == MEM)
3016: find_reloads_address (GET_MODE (recog_operand[i]),
3017: recog_operand_loc[i],
3018: XEXP (recog_operand[i], 0),
3019: &XEXP (recog_operand[i], 0),
3020: recog_operand[i], ind_levels);
3021: if (code == SUBREG)
3022: recog_operand[i] = *recog_operand_loc[i]
3023: = find_reloads_toplev (recog_operand[i], ind_levels, is_set_dest);
3024: if (code == REG)
3025: {
3026: register int regno = REGNO (recog_operand[i]);
3027: if (reg_equiv_constant[regno] != 0 && !is_set_dest)
3028: recog_operand[i] = *recog_operand_loc[i]
3029: = reg_equiv_constant[regno];
3030: #if 0 /* This might screw code in reload1.c to delete prior output-reload
3031: that feeds this insn. */
3032: if (reg_equiv_mem[regno] != 0)
3033: recog_operand[i] = *recog_operand_loc[i]
3034: = reg_equiv_mem[regno];
3035: #endif
3036: }
3037: /* All operands are non-reloaded. */
3038: non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i];
3039: }
3040: #endif /* no REGISTER_CONSTRAINTS */
3041:
3042: /* Determine which part of the insn each reload is needed for,
3043: based on which operand the reload is needed for.
3044: Reloads of entire operands are classified as RELOAD_OTHER.
3045: So are reloads for which a unique purpose is not known. */
3046:
3047: for (i = 0; i < n_reloads; i++)
3048: {
3049: reload_when_needed[i] = RELOAD_OTHER;
3050:
3051: if (reload_needed_for[i] != 0 && ! reload_needed_for_multiple[i])
3052: {
3053: int j;
3054: int output_address = 0;
3055: int input_address = 0;
3056: int operand_address = 0;
3057:
3058: /* This reload is needed only for the address of something.
3059: Determine whether it is needed for addressing an operand
3060: being reloaded for input, whether it is needed for an
3061: operand being reloaded for output, and whether it is needed
3062: for addressing an operand that won't really be reloaded.
3063:
3064: Note that we know that this reload is needed in only one address,
3065: but we have not yet checked for the case where that same address
3066: is used in both input and output reloads.
3067: The following code detects this case. */
3068:
3069: for (j = 0; j < n_reloads; j++)
3070: if (reload_needed_for[i] == reload_in[j]
3071: || reload_needed_for[i] == reload_out[j])
3072: {
3073: if (reload_optional[j])
3074: operand_address = 1;
3075: else
3076: {
3077: if (reload_needed_for[i] == reload_in[j])
3078: input_address = 1;
3079: if (reload_needed_for[i] == reload_out[j])
3080: output_address = 1;
3081: }
3082: }
3083: /* Don't ignore memrefs without optional reloads. */
3084: for (j = 0; j < n_non_reloaded_operands; j++)
3085: if (reload_needed_for[i] == non_reloaded_operands[j])
3086: operand_address = 1;
3087:
3088: /* If it is needed for only one of those, record which one. */
3089:
3090: if (input_address && ! output_address && ! operand_address)
3091: reload_when_needed[i] = RELOAD_FOR_INPUT_RELOAD_ADDRESS;
3092: if (output_address && ! input_address && ! operand_address)
3093: reload_when_needed[i] = RELOAD_FOR_OUTPUT_RELOAD_ADDRESS;
3094: if (operand_address && ! input_address && ! output_address)
3095: reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS;
3096:
3097: /* Indicate those RELOAD_OTHER reloads which, though they have
3098: 0 for reload_output, still cannot overlap an output reload. */
3099:
3100: if (output_address && reload_when_needed[i] == RELOAD_OTHER)
3101: reload_needed_for_multiple[i] = 1;
3102: }
3103: }
3104:
3105: /* Perhaps an output reload can be combined with another
3106: to reduce needs by one. */
3107: if (!goal_earlyclobber)
3108: combine_reloads ();
3109: }
3110:
3111: /* Return 1 if alternative number ALTNUM in constraint-string CONSTRAINT
3112: accepts a memory operand with constant address. */
3113:
3114: static int
3115: alternative_allows_memconst (constraint, altnum)
3116: char *constraint;
3117: int altnum;
3118: {
3119: register int c;
3120: /* Skip alternatives before the one requested. */
3121: while (altnum > 0)
3122: {
3123: while (*constraint++ != ',');
3124: altnum--;
3125: }
3126: /* Scan the requested alternative for 'm' or 'o'.
3127: If one of them is present, this alternative accepts memory constants. */
3128: while ((c = *constraint++) && c != ',' && c != '#')
3129: if (c == 'm' || c == 'o')
3130: return 1;
3131: return 0;
3132: }
3133:
3134: /* Scan X for memory references and scan the addresses for reloading.
3135: Also checks for references to "constant" regs that we want to eliminate
3136: and replaces them with the values they stand for.
3137: We may alter X descructively if it contains a reference to such.
3138: If X is just a constant reg, we return the equivalent value
3139: instead of X.
3140:
3141: IND_LEVELS says how many levels of indirect addressing this machine
3142: supports.
3143:
3144: IS_SET_DEST is true if X is the destination of a SET, which is not
3145: appropriate to be replaced by a constant. */
3146:
3147: static rtx
3148: find_reloads_toplev (x, ind_levels, is_set_dest)
3149: rtx x;
3150: int ind_levels;
3151: int is_set_dest;
3152: {
3153: register RTX_CODE code = GET_CODE (x);
3154:
3155: register char *fmt = GET_RTX_FORMAT (code);
3156: register int i;
3157:
3158: if (code == REG)
3159: {
3160: /* This code is duplicated for speed in find_reloads. */
3161: register int regno = REGNO (x);
3162: if (reg_equiv_constant[regno] != 0 && !is_set_dest)
3163: x = reg_equiv_constant[regno];
3164: #if 0
3165: /* This creates (subreg (mem...)) which would cause an unnecessary
3166: reload of the mem. */
3167: else if (reg_equiv_mem[regno] != 0)
3168: x = reg_equiv_mem[regno];
3169: #endif
3170: else if (reg_equiv_address[regno] != 0)
3171: {
3172: /* If reg_equiv_address varies, it may be shared, so copy it. */
3173: rtx addr = reg_equiv_address[regno];
3174:
3175: if (rtx_varies_p (addr))
3176: addr = copy_rtx (addr);
3177:
3178: x = gen_rtx (MEM, GET_MODE (x), addr);
3179: RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
3180: find_reloads_address (GET_MODE (x), 0,
3181: XEXP (x, 0),
3182: &XEXP (x, 0), x, ind_levels);
3183: }
3184: return x;
3185: }
3186: if (code == MEM)
3187: {
3188: rtx tem = x;
3189: find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0),
3190: x, ind_levels);
3191: return tem;
3192: }
3193:
3194: if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)
3195: {
3196: /* Check for SUBREG containing a REG that's equivalent to a constant.
3197: If the constant has a known value, truncate it right now.
3198: Similarly if we are extracting a single-word of a multi-word
3199: constant. If the constant is symbolic, allow it to be substituted
3200: normally. push_reload will strip the subreg later. If the
3201: constant is VOIDmode, abort because we will lose the mode of
3202: the register (this should never happen because one of the cases
3203: above should handle it). */
3204:
3205: register int regno = REGNO (SUBREG_REG (x));
3206: rtx tem;
3207:
3208: if (subreg_lowpart_p (x)
3209: && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
3210: && reg_equiv_constant[regno] != 0
3211: && (tem = gen_lowpart_common (GET_MODE (x),
3212: reg_equiv_constant[regno])) != 0)
3213: return tem;
3214:
3215: if (GET_MODE_BITSIZE (GET_MODE (x)) == BITS_PER_WORD
3216: && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
3217: && reg_equiv_constant[regno] != 0
3218: && (tem = operand_subword (reg_equiv_constant[regno],
3219: SUBREG_WORD (x), 0,
3220: GET_MODE (SUBREG_REG (x)))) != 0)
3221: return tem;
3222:
3223: if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
3224: && reg_equiv_constant[regno] != 0
3225: && GET_MODE (reg_equiv_constant[regno]) == VOIDmode)
3226: abort ();
3227:
3228: /* If the subreg contains a reg that will be converted to a mem,
3229: convert the subreg to a narrower memref now.
3230: Otherwise, we would get (subreg (mem ...) ...),
3231: which would force reload of the mem.
3232:
3233: We also need to do this if there is an equivalent MEM that is
3234: not offsettable. In that case, alter_subreg would produce an
1.1.1.2 ! root 3235: invalid address on big-endian machines.
! 3236:
! 3237: For machines that zero-extend byte loads, we must not reload using
! 3238: a wider mode if we have a paradoxical SUBREG. find_reloads will
! 3239: force a reload in that case. So we should not do anything here. */
1.1 root 3240:
3241: else if (regno >= FIRST_PSEUDO_REGISTER
1.1.1.2 ! root 3242: #ifdef BYTE_LOADS_ZERO_EXTEND
! 3243: && (GET_MODE_SIZE (GET_MODE (x))
! 3244: <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
! 3245: #endif
1.1 root 3246: && (reg_equiv_address[regno] != 0
3247: || (reg_equiv_mem[regno] != 0
3248: && ! offsettable_memref_p (reg_equiv_mem[regno]))))
3249: {
3250: int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3251: rtx addr = (reg_equiv_address[regno] ? reg_equiv_address[regno]
3252: : XEXP (reg_equiv_mem[regno], 0));
3253: #if BYTES_BIG_ENDIAN
3254: int size;
3255: size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
3256: offset += MIN (size, UNITS_PER_WORD);
3257: size = GET_MODE_SIZE (GET_MODE (x));
3258: offset -= MIN (size, UNITS_PER_WORD);
3259: #endif
3260: addr = plus_constant (addr, offset);
3261: x = gen_rtx (MEM, GET_MODE (x), addr);
3262: RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
3263: find_reloads_address (GET_MODE (x), 0,
3264: XEXP (x, 0),
3265: &XEXP (x, 0), x, ind_levels);
3266: }
3267:
3268: }
3269:
3270: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3271: {
3272: if (fmt[i] == 'e')
3273: XEXP (x, i) = find_reloads_toplev (XEXP (x, i),
3274: ind_levels, is_set_dest);
3275: }
3276: return x;
3277: }
3278:
3279: static rtx
3280: make_memloc (ad, regno)
3281: rtx ad;
3282: int regno;
3283: {
3284: register int i;
3285: rtx tem = reg_equiv_address[regno];
3286: for (i = 0; i < n_memlocs; i++)
3287: if (rtx_equal_p (tem, XEXP (memlocs[i], 0)))
3288: return memlocs[i];
3289:
3290: /* If TEM might contain a pseudo, we must copy it to avoid
3291: modifying it when we do the substitution for the reload. */
3292: if (rtx_varies_p (tem))
3293: tem = copy_rtx (tem);
3294:
3295: tem = gen_rtx (MEM, GET_MODE (ad), tem);
3296: RTX_UNCHANGING_P (tem) = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
3297: memlocs[n_memlocs++] = tem;
3298: return tem;
3299: }
3300:
3301: /* Record all reloads needed for handling memory address AD
3302: which appears in *LOC in a memory reference to mode MODE
3303: which itself is found in location *MEMREFLOC.
3304: Note that we take shortcuts assuming that no multi-reg machine mode
3305: occurs as part of an address.
3306:
3307: OPERAND is the operand of the insn within which this address appears.
3308:
3309: IND_LEVELS says how many levels of indirect addressing this machine
3310: supports.
3311:
3312: Value is nonzero if this address is reloaded or replaced as a whole.
3313: This is interesting to the caller if the address is an autoincrement.
3314:
3315: Note that there is no verification that the address will be valid after
3316: this routine does its work. Instead, we rely on the fact that the address
3317: was valid when reload started. So we need only undo things that reload
3318: could have broken. These are wrong register types, pseudos not allocated
3319: to a hard register, and frame pointer elimination. */
3320:
3321: static int
3322: find_reloads_address (mode, memrefloc, ad, loc, operand, ind_levels)
3323: enum machine_mode mode;
3324: rtx *memrefloc;
3325: rtx ad;
3326: rtx *loc;
3327: rtx operand;
3328: int ind_levels;
3329: {
3330: register int regno;
3331: rtx tem;
3332:
3333: /* If the address is a register, see if it is a legitimate address and
3334: reload if not. We first handle the cases where we need not reload
3335: or where we must reload in a non-standard way. */
3336:
3337: if (GET_CODE (ad) == REG)
3338: {
3339: regno = REGNO (ad);
3340:
3341: if (reg_equiv_constant[regno] != 0
3342: && strict_memory_address_p (mode, reg_equiv_constant[regno]))
3343: {
3344: *loc = ad = reg_equiv_constant[regno];
3345: return 1;
3346: }
3347:
3348: else if (reg_equiv_address[regno] != 0)
3349: {
3350: tem = make_memloc (ad, regno);
3351: find_reloads_address (GET_MODE (tem), 0, XEXP (tem, 0),
3352: &XEXP (tem, 0), operand, ind_levels);
3353: push_reload (tem, 0, loc, 0, BASE_REG_CLASS,
3354: GET_MODE (ad), VOIDmode, 0, 0,
3355: operand);
3356: return 1;
3357: }
3358:
3359: else if (reg_equiv_mem[regno] != 0)
3360: {
3361: tem = XEXP (reg_equiv_mem[regno], 0);
3362:
3363: /* If we can't indirect any more, a pseudo must be reloaded.
3364: If the pseudo's address in its MEM is a SYMBOL_REF, it
3365: must be reloaded unless indirect_symref_ok. Otherwise, it
3366: can be reloaded if the address is REG or REG + CONST_INT. */
3367:
3368: if (ind_levels > 0
3369: && ! (GET_CODE (tem) == SYMBOL_REF && ! indirect_symref_ok)
3370: && ((GET_CODE (tem) == REG
3371: && REGNO (tem) < FIRST_PSEUDO_REGISTER)
3372: || (GET_CODE (tem) == PLUS
3373: && GET_CODE (XEXP (tem, 0)) == REG
3374: && REGNO (XEXP (tem, 0)) < FIRST_PSEUDO_REGISTER
3375: && GET_CODE (XEXP (tem, 1)) == CONST_INT)))
3376: return 0;
3377: }
3378:
3379: /* The only remaining case where we can avoid a reload is if this is a
3380: hard register that is valid as a base register and which is not the
3381: subject of a CLOBBER in this insn. */
3382:
3383: else if (regno < FIRST_PSEUDO_REGISTER && REGNO_OK_FOR_BASE_P (regno)
3384: && ! regno_clobbered_p (regno, this_insn))
3385: return 0;
3386:
3387: /* If we do not have one of the cases above, we must do the reload. */
3388: push_reload (ad, 0, loc, 0, BASE_REG_CLASS,
3389: GET_MODE (ad), VOIDmode, 0, 0, operand);
3390: return 1;
3391: }
3392:
3393: if (strict_memory_address_p (mode, ad))
3394: {
3395: /* The address appears valid, so reloads are not needed.
3396: But the address may contain an eliminable register.
3397: This can happen because a machine with indirect addressing
3398: may consider a pseudo register by itself a valid address even when
3399: it has failed to get a hard reg.
3400: So do a tree-walk to find and eliminate all such regs. */
3401:
3402: /* But first quickly dispose of a common case. */
3403: if (GET_CODE (ad) == PLUS
3404: && GET_CODE (XEXP (ad, 1)) == CONST_INT
3405: && GET_CODE (XEXP (ad, 0)) == REG
3406: && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0)
3407: return 0;
3408:
3409: subst_reg_equivs_changed = 0;
3410: *loc = subst_reg_equivs (ad);
3411:
3412: if (! subst_reg_equivs_changed)
3413: return 0;
3414:
3415: /* Check result for validity after substitution. */
3416: if (strict_memory_address_p (mode, ad))
3417: return 0;
3418: }
3419:
3420: /* The address is not valid. We have to figure out why. One possibility
3421: is that it is itself a MEM. This can happen when the frame pointer is
3422: being eliminated, a pseudo is not allocated to a hard register, and the
3423: offset between the frame and stack pointers is not its initial value.
1.1.1.2 ! root 3424: In that case the pseudo will have been replaced by a MEM referring to
1.1 root 3425: the stack pointer. */
3426: if (GET_CODE (ad) == MEM)
3427: {
3428: /* First ensure that the address in this MEM is valid. Then, unless
3429: indirect addresses are valid, reload the MEM into a register. */
3430: tem = ad;
3431: find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0),
3432: operand, ind_levels == 0 ? 0 : ind_levels - 1);
3433: /* Check similar cases as for indirect addresses as above except
3434: that we can allow pseudos and a MEM since they should have been
3435: taken care of above. */
3436:
3437: if (ind_levels == 0
3438: || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok)
3439: || GET_CODE (XEXP (tem, 0)) == MEM
3440: || ! (GET_CODE (XEXP (tem, 0)) == REG
3441: || (GET_CODE (XEXP (tem, 0)) == PLUS
3442: && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG
3443: && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT)))
3444: {
3445: /* Must use TEM here, not AD, since it is the one that will
3446: have any subexpressions reloaded, if needed. */
3447: push_reload (tem, 0, loc, 0,
3448: BASE_REG_CLASS, GET_MODE (tem), VOIDmode, 0,
3449: 0, operand);
3450: return 1;
3451: }
3452: else
3453: return 0;
3454: }
3455:
3456: /* If we have address of a stack slot but it's not valid
3457: (displacement is too large), compute the sum in a register. */
3458: else if (GET_CODE (ad) == PLUS
3459: && (XEXP (ad, 0) == frame_pointer_rtx
3460: #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3461: || XEXP (ad, 0) == arg_pointer_rtx
3462: #endif
3463: || XEXP (ad, 0) == stack_pointer_rtx)
3464: && GET_CODE (XEXP (ad, 1)) == CONST_INT)
3465: {
3466: /* Unshare the MEM rtx so we can safely alter it. */
3467: if (memrefloc)
3468: {
3469: rtx oldref = *memrefloc;
3470: *memrefloc = copy_rtx (*memrefloc);
3471: loc = &XEXP (*memrefloc, 0);
3472: if (operand == oldref)
3473: operand = *memrefloc;
3474: }
3475: if (double_reg_address_ok)
3476: {
3477: /* Unshare the sum as well. */
3478: *loc = ad = copy_rtx (ad);
3479: /* Reload the displacement into an index reg.
3480: We assume the frame pointer or arg pointer is a base reg. */
3481: find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1),
3482: INDEX_REG_CLASS, GET_MODE (ad), operand,
3483: ind_levels);
3484: }
3485: else
3486: {
3487: /* If the sum of two regs is not necessarily valid,
3488: reload the sum into a base reg.
3489: That will at least work. */
3490: find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode,
3491: operand, ind_levels);
3492: }
3493: return 1;
3494: }
3495:
3496: /* If we have an indexed stack slot, there are three possible reasons why
3497: it might be invalid: The index might need to be reloaded, the address
3498: might have been made by frame pointer elimination and hence have a
3499: constant out of range, or both reasons might apply.
3500:
3501: We can easily check for an index needing reload, but even if that is the
3502: case, we might also have an invalid constant. To avoid making the
3503: conservative assumption and requiring two reloads, we see if this address
3504: is valid when not interpreted strictly. If it is, the only problem is
3505: that the index needs a reload and find_reloads_address_1 will take care
3506: of it.
3507:
3508: There is still a case when we might generate an extra reload,
3509: however. In certain cases eliminate_regs will return a MEM for a REG
3510: (see the code there for details). In those cases, memory_address_p
3511: applied to our address will return 0 so we will think that our offset
3512: must be too large. But it might indeed be valid and the only problem
3513: is that a MEM is present where a REG should be. This case should be
3514: very rare and there doesn't seem to be any way to avoid it.
3515:
3516: If we decide to do something here, it must be that
3517: `double_reg_address_ok' is true and that this address rtl was made by
3518: eliminate_regs. We generate a reload of the fp/sp/ap + constant and
3519: rework the sum so that the reload register will be added to the index.
3520: This is safe because we know the address isn't shared.
3521:
3522: We check for fp/ap/sp as both the first and second operand of the
3523: innermost PLUS. */
3524:
3525: else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
3526: && GET_CODE (XEXP (ad, 0)) == PLUS
3527: && (XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx
3528: #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3529: || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx
3530: #endif
3531: || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx)
3532: && ! memory_address_p (mode, ad))
3533: {
3534: *loc = ad = gen_rtx (PLUS, GET_MODE (ad),
3535: plus_constant (XEXP (XEXP (ad, 0), 0),
3536: INTVAL (XEXP (ad, 1))),
3537: XEXP (XEXP (ad, 0), 1));
3538: find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS,
3539: GET_MODE (ad), operand, ind_levels);
3540: find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), operand, 0);
3541:
3542: return 1;
3543: }
3544:
3545: else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
3546: && GET_CODE (XEXP (ad, 0)) == PLUS
3547: && (XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx
3548: #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3549: || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx
3550: #endif
3551: || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx)
3552: && ! memory_address_p (mode, ad))
3553: {
3554: *loc = ad = gen_rtx (PLUS, GET_MODE (ad),
3555: plus_constant (XEXP (XEXP (ad, 0), 1),
3556: INTVAL (XEXP (ad, 1))),
3557: XEXP (XEXP (ad, 0), 0));
3558: find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS,
3559: GET_MODE (ad), operand, ind_levels);
3560: find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), operand, 0);
3561:
3562: return 1;
3563: }
3564:
3565: /* See if address becomes valid when an eliminable register
3566: in a sum is replaced. */
3567:
3568: tem = ad;
3569: if (GET_CODE (ad) == PLUS)
3570: tem = subst_indexed_address (ad);
3571: if (tem != ad && strict_memory_address_p (mode, tem))
3572: {
3573: /* Ok, we win that way. Replace any additional eliminable
3574: registers. */
3575:
3576: subst_reg_equivs_changed = 0;
3577: tem = subst_reg_equivs (tem);
3578:
3579: /* Make sure that didn't make the address invalid again. */
3580:
3581: if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem))
3582: {
3583: *loc = tem;
3584: return 0;
3585: }
3586: }
3587:
3588: /* If constants aren't valid addresses, reload the constant address
3589: into a register. */
3590: if (CONSTANT_ADDRESS_P (ad) && ! strict_memory_address_p (mode, ad))
3591: {
3592: /* If AD is in address in the constant pool, the MEM rtx may be shared.
3593: Unshare it so we can safely alter it. */
3594: if (memrefloc && GET_CODE (ad) == SYMBOL_REF
3595: && CONSTANT_POOL_ADDRESS_P (ad))
3596: {
3597: rtx oldref = *memrefloc;
3598: *memrefloc = copy_rtx (*memrefloc);
3599: loc = &XEXP (*memrefloc, 0);
3600: if (operand == oldref)
3601: operand = *memrefloc;
3602: }
3603:
3604: find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, operand,
3605: ind_levels);
3606: return 1;
3607: }
3608:
3609: return find_reloads_address_1 (ad, 0, loc, operand, ind_levels);
3610: }
3611:
3612: /* Find all pseudo regs appearing in AD
3613: that are eliminable in favor of equivalent values
3614: and do not have hard regs; replace them by their equivalents. */
3615:
3616: static rtx
3617: subst_reg_equivs (ad)
3618: rtx ad;
3619: {
3620: register RTX_CODE code = GET_CODE (ad);
3621: register int i;
3622: register char *fmt;
3623:
3624: switch (code)
3625: {
3626: case HIGH:
3627: case CONST_INT:
3628: case CONST:
3629: case CONST_DOUBLE:
3630: case SYMBOL_REF:
3631: case LABEL_REF:
3632: case PC:
3633: case CC0:
3634: return ad;
3635:
3636: case REG:
3637: {
3638: register int regno = REGNO (ad);
3639:
3640: if (reg_equiv_constant[regno] != 0)
3641: {
3642: subst_reg_equivs_changed = 1;
3643: return reg_equiv_constant[regno];
3644: }
3645: }
3646: return ad;
3647:
3648: case PLUS:
3649: /* Quickly dispose of a common case. */
3650: if (XEXP (ad, 0) == frame_pointer_rtx
3651: && GET_CODE (XEXP (ad, 1)) == CONST_INT)
3652: return ad;
3653: }
3654:
3655: fmt = GET_RTX_FORMAT (code);
3656: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3657: if (fmt[i] == 'e')
3658: XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i));
3659: return ad;
3660: }
3661:
3662: /* Compute the sum of X and Y, making canonicalizations assumed in an
3663: address, namely: sum constant integers, surround the sum of two
3664: constants with a CONST, put the constant as the second operand, and
3665: group the constant on the outermost sum.
3666:
3667: This routine assumes both inputs are already in canonical form. */
3668:
3669: rtx
3670: form_sum (x, y)
3671: rtx x, y;
3672: {
3673: rtx tem;
3674:
3675: if (GET_CODE (x) == CONST_INT)
3676: return plus_constant (y, INTVAL (x));
3677: else if (GET_CODE (y) == CONST_INT)
3678: return plus_constant (x, INTVAL (y));
3679: else if (CONSTANT_P (x))
3680: tem = x, x = y, y = tem;
3681:
3682: if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1)))
3683: return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y));
3684:
3685: /* Note that if the operands of Y are specified in the opposite
3686: order in the recursive calls below, infinite recursion will occur. */
3687: if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1)))
3688: return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1));
3689:
3690: /* If both constant, encapsulate sum. Otherwise, just form sum. A
3691: constant will have been placed second. */
3692: if (CONSTANT_P (x) && CONSTANT_P (y))
3693: {
3694: if (GET_CODE (x) == CONST)
3695: x = XEXP (x, 0);
3696: if (GET_CODE (y) == CONST)
3697: y = XEXP (y, 0);
3698:
3699: return gen_rtx (CONST, VOIDmode, gen_rtx (PLUS, Pmode, x, y));
3700: }
3701:
3702: return gen_rtx (PLUS, Pmode, x, y);
3703: }
3704:
3705: /* If ADDR is a sum containing a pseudo register that should be
3706: replaced with a constant (from reg_equiv_constant),
3707: return the result of doing so, and also apply the associative
3708: law so that the result is more likely to be a valid address.
3709: (But it is not guaranteed to be one.)
3710:
3711: Note that at most one register is replaced, even if more are
3712: replaceable. Also, we try to put the result into a canonical form
3713: so it is more likely to be a valid address.
3714:
3715: In all other cases, return ADDR. */
3716:
3717: static rtx
3718: subst_indexed_address (addr)
3719: rtx addr;
3720: {
3721: rtx op0 = 0, op1 = 0, op2 = 0;
3722: rtx tem;
3723: int regno;
3724:
3725: if (GET_CODE (addr) == PLUS)
3726: {
3727: /* Try to find a register to replace. */
3728: op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0;
3729: if (GET_CODE (op0) == REG
3730: && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER
3731: && reg_renumber[regno] < 0
3732: && reg_equiv_constant[regno] != 0)
3733: op0 = reg_equiv_constant[regno];
3734: else if (GET_CODE (op1) == REG
3735: && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER
3736: && reg_renumber[regno] < 0
3737: && reg_equiv_constant[regno] != 0)
3738: op1 = reg_equiv_constant[regno];
3739: else if (GET_CODE (op0) == PLUS
3740: && (tem = subst_indexed_address (op0)) != op0)
3741: op0 = tem;
3742: else if (GET_CODE (op1) == PLUS
3743: && (tem = subst_indexed_address (op1)) != op1)
3744: op1 = tem;
3745: else
3746: return addr;
3747:
3748: /* Pick out up to three things to add. */
3749: if (GET_CODE (op1) == PLUS)
3750: op2 = XEXP (op1, 1), op1 = XEXP (op1, 0);
3751: else if (GET_CODE (op0) == PLUS)
3752: op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3753:
3754: /* Compute the sum. */
3755: if (op2 != 0)
3756: op1 = form_sum (op1, op2);
3757: if (op1 != 0)
3758: op0 = form_sum (op0, op1);
3759:
3760: return op0;
3761: }
3762: return addr;
3763: }
3764:
3765: /* Record the pseudo registers we must reload into hard registers
3766: in a subexpression of a would-be memory address, X.
3767: (This function is not called if the address we find is strictly valid.)
3768: CONTEXT = 1 means we are considering regs as index regs,
3769: = 0 means we are considering them as base regs.
3770:
3771: OPERAND is the operand of the insn within which this address appears.
3772:
3773: IND_LEVELS says how many levels of indirect addressing are
3774: supported at this point in the address.
3775:
3776: We return nonzero if X, as a whole, is reloaded or replaced. */
3777:
3778: /* Note that we take shortcuts assuming that no multi-reg machine mode
3779: occurs as part of an address.
3780: Also, this is not fully machine-customizable; it works for machines
3781: such as vaxes and 68000's and 32000's, but other possible machines
3782: could have addressing modes that this does not handle right. */
3783:
3784: static int
3785: find_reloads_address_1 (x, context, loc, operand, ind_levels)
3786: rtx x;
3787: int context;
3788: rtx *loc;
3789: rtx operand;
3790: int ind_levels;
3791: {
3792: register RTX_CODE code = GET_CODE (x);
3793:
3794: if (code == PLUS)
3795: {
3796: register rtx op0 = XEXP (x, 0);
3797: register rtx op1 = XEXP (x, 1);
3798: register RTX_CODE code0 = GET_CODE (op0);
3799: register RTX_CODE code1 = GET_CODE (op1);
3800: if (code0 == MULT || code0 == SIGN_EXTEND || code1 == MEM)
3801: {
3802: find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels);
3803: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
3804: }
3805: else if (code1 == MULT || code1 == SIGN_EXTEND || code0 == MEM)
3806: {
3807: find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
3808: find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels);
3809: }
3810: else if (code0 == CONST_INT || code0 == CONST
3811: || code0 == SYMBOL_REF || code0 == LABEL_REF)
3812: {
3813: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
3814: }
3815: else if (code1 == CONST_INT || code1 == CONST
3816: || code1 == SYMBOL_REF || code1 == LABEL_REF)
3817: {
3818: find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
3819: }
3820: else if (code0 == REG && code1 == REG)
3821: {
3822: if (REG_OK_FOR_INDEX_P (op0)
3823: && REG_OK_FOR_BASE_P (op1))
3824: return 0;
3825: else if (REG_OK_FOR_INDEX_P (op1)
3826: && REG_OK_FOR_BASE_P (op0))
3827: return 0;
3828: else if (REG_OK_FOR_BASE_P (op1))
3829: find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels);
3830: else if (REG_OK_FOR_BASE_P (op0))
3831: find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels);
3832: else if (REG_OK_FOR_INDEX_P (op1))
3833: find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
3834: else if (REG_OK_FOR_INDEX_P (op0))
3835: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
3836: else
3837: {
3838: find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand,
3839: ind_levels);
3840: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand,
3841: ind_levels);
3842: }
3843: }
3844: else if (code0 == REG)
3845: {
3846: find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels);
3847: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
3848: }
3849: else if (code1 == REG)
3850: {
3851: find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels);
3852: find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
3853: }
3854: }
3855: else if (code == POST_INC || code == POST_DEC
3856: || code == PRE_INC || code == PRE_DEC)
3857: {
3858: if (GET_CODE (XEXP (x, 0)) == REG)
3859: {
3860: register int regno = REGNO (XEXP (x, 0));
3861: int value = 0;
3862: rtx x_orig = x;
3863:
3864: /* A register that is incremented cannot be constant! */
3865: if (regno >= FIRST_PSEUDO_REGISTER
3866: && reg_equiv_constant[regno] != 0)
3867: abort ();
3868:
3869: /* Handle a register that is equivalent to a memory location
3870: which cannot be addressed directly. */
3871: if (reg_equiv_address[regno] != 0)
3872: {
3873: rtx tem = make_memloc (XEXP (x, 0), regno);
3874: /* First reload the memory location's address. */
3875: find_reloads_address (GET_MODE (tem), 0, XEXP (tem, 0),
3876: &XEXP (tem, 0), operand, ind_levels);
3877: /* Put this inside a new increment-expression. */
3878: x = gen_rtx (GET_CODE (x), GET_MODE (x), tem);
3879: /* Proceed to reload that, as if it contained a register. */
3880: }
3881:
3882: /* If we have a hard register that is ok as an index,
3883: don't make a reload. If an autoincrement of a nice register
3884: isn't "valid", it must be that no autoincrement is "valid".
3885: If that is true and something made an autoincrement anyway,
3886: this must be a special context where one is allowed.
3887: (For example, a "push" instruction.)
3888: We can't improve this address, so leave it alone. */
3889:
3890: /* Otherwise, reload the autoincrement into a suitable hard reg
3891: and record how much to increment by. */
3892:
3893: if (reg_renumber[regno] >= 0)
3894: regno = reg_renumber[regno];
3895: if ((regno >= FIRST_PSEUDO_REGISTER
3896: || !(context ? REGNO_OK_FOR_INDEX_P (regno)
3897: : REGNO_OK_FOR_BASE_P (regno))))
3898: {
3899: register rtx link;
3900:
3901: int reloadnum
3902: = push_reload (x, 0, loc, 0,
3903: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3904: GET_MODE (x), GET_MODE (x), VOIDmode, 0, operand);
3905: reload_inc[reloadnum]
3906: = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0));
3907:
3908: value = 1;
3909:
3910: #ifdef AUTO_INC_DEC
3911: /* Update the REG_INC notes. */
3912:
3913: for (link = REG_NOTES (this_insn);
3914: link; link = XEXP (link, 1))
3915: if (REG_NOTE_KIND (link) == REG_INC
3916: && REGNO (XEXP (link, 0)) == REGNO (XEXP (x_orig, 0)))
3917: push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
3918: #endif
3919: }
3920: return value;
3921: }
3922: else if (GET_CODE (XEXP (x, 0)) == MEM)
3923: {
3924: /* This is probably the result of a substitution, by eliminate_regs,
3925: of an equivalent address for a pseudo that was not allocated to a
3926: hard register. Verify that the specified address is valid and
3927: reload it into a register. */
3928: rtx tem = XEXP (x, 0);
3929: register rtx link;
3930: int reloadnum;
3931:
3932: /* Since we know we are going to reload this item, don't decrement
3933: for the indirection level.
3934:
3935: Note that this is actually conservative: it would be slightly
3936: more efficient to use the value of SPILL_INDIRECT_LEVELS from
3937: reload1.c here. */
3938: find_reloads_address (GET_MODE (x), &XEXP (x, 0),
3939: XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0),
3940: operand, ind_levels);
3941:
3942: reloadnum = push_reload (x, 0, loc, 0,
3943: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3944: GET_MODE (x), VOIDmode, 0, 0, operand);
3945: reload_inc[reloadnum]
3946: = find_inc_amount (PATTERN (this_insn), XEXP (x, 0));
3947:
3948: link = FIND_REG_INC_NOTE (this_insn, tem);
3949: if (link != 0)
3950: push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
3951:
3952: return 1;
3953: }
3954: }
3955: else if (code == MEM)
3956: {
3957: /* This is probably the result of a substitution, by eliminate_regs,
3958: of an equivalent address for a pseudo that was not allocated to a
3959: hard register. Verify that the specified address is valid and reload
3960: it into a register.
3961:
3962: Since we know we are going to reload this item, don't decrement
3963: for the indirection level.
3964:
3965: Note that this is actually conservative: it would be slightly more
3966: efficient to use the value of SPILL_INDIRECT_LEVELS from
3967: reload1.c here. */
3968:
3969: find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
3970: operand, ind_levels);
3971:
3972: push_reload (*loc, 0, loc, 0,
3973: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3974: GET_MODE (x), VOIDmode, 0, 0, operand);
3975: return 1;
3976: }
3977: else if (code == REG)
3978: {
3979: register int regno = REGNO (x);
3980:
3981: if (reg_equiv_constant[regno] != 0)
3982: {
3983: push_reload (reg_equiv_constant[regno], 0, loc, 0,
3984: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3985: GET_MODE (x), VOIDmode, 0, 0, operand);
3986: return 1;
3987: }
3988:
3989: #if 0 /* This might screw code in reload1.c to delete prior output-reload
3990: that feeds this insn. */
3991: if (reg_equiv_mem[regno] != 0)
3992: {
3993: push_reload (reg_equiv_mem[regno], 0, loc, 0,
3994: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
3995: GET_MODE (x), VOIDmode, 0, 0, operand);
3996: return 1;
3997: }
3998: #endif
3999: if (reg_equiv_address[regno] != 0)
4000: {
4001: x = make_memloc (x, regno);
4002: find_reloads_address (GET_MODE (x), 0, XEXP (x, 0), &XEXP (x, 0),
4003: operand, ind_levels);
4004: }
4005:
4006: if (reg_renumber[regno] >= 0)
4007: regno = reg_renumber[regno];
4008: if ((regno >= FIRST_PSEUDO_REGISTER
4009: || !(context ? REGNO_OK_FOR_INDEX_P (regno)
4010: : REGNO_OK_FOR_BASE_P (regno))))
4011: {
4012: push_reload (x, 0, loc, 0,
4013: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4014: GET_MODE (x), VOIDmode, 0, 0, operand);
4015: return 1;
4016: }
4017:
4018: /* If a register appearing in an address is the subject of a CLOBBER
4019: in this insn, reload it into some other register to be safe.
4020: The CLOBBER is supposed to make the register unavailable
4021: from before this insn to after it. */
4022: if (regno_clobbered_p (regno, this_insn))
4023: {
4024: push_reload (x, 0, loc, 0,
4025: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4026: GET_MODE (x), VOIDmode, 0, 0, operand);
4027: return 1;
4028: }
4029: }
4030: else
4031: {
4032: register char *fmt = GET_RTX_FORMAT (code);
4033: register int i;
4034: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4035: {
4036: if (fmt[i] == 'e')
4037: find_reloads_address_1 (XEXP (x, i), context, &XEXP (x, i),
4038: operand, ind_levels);
4039: }
4040: }
4041:
4042: return 0;
4043: }
4044:
4045: /* X, which is found at *LOC, is a part of an address that needs to be
4046: reloaded into a register of class CLASS. If X is a constant, or if
4047: X is a PLUS that contains a constant, check that the constant is a
4048: legitimate operand and that we are supposed to be able to load
4049: it into the register.
4050:
4051: If not, force the constant into memory and reload the MEM instead.
4052:
4053: MODE is the mode to use, in case X is an integer constant.
4054:
4055: NEEDED_FOR says which operand this reload is needed for.
4056:
4057: IND_LEVELS says how many levels of indirect addressing this machine
4058: supports. */
4059:
4060: static void
4061: find_reloads_address_part (x, loc, class, mode, needed_for, ind_levels)
4062: rtx x;
4063: rtx *loc;
4064: enum reg_class class;
4065: enum machine_mode mode;
4066: rtx needed_for;
4067: int ind_levels;
4068: {
4069: if (CONSTANT_P (x)
4070: && (! LEGITIMATE_CONSTANT_P (x)
4071: || PREFERRED_RELOAD_CLASS (x, class) == NO_REGS))
4072: {
4073: rtx tem = x = force_const_mem (mode, x);
4074: find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0),
4075: needed_for, ind_levels);
4076: }
4077:
4078: else if (GET_CODE (x) == PLUS
4079: && CONSTANT_P (XEXP (x, 1))
4080: && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1))
4081: || PREFERRED_RELOAD_CLASS (XEXP (x, 1), class) == NO_REGS))
4082: {
4083: rtx tem = force_const_mem (GET_MODE (x), XEXP (x, 1));
4084:
4085: x = gen_rtx (PLUS, GET_MODE (x), XEXP (x, 0), tem);
4086: find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0),
4087: needed_for, ind_levels);
4088: }
4089:
4090: push_reload (x, 0, loc, 0, class, mode, VOIDmode, 0, 0, needed_for);
4091: }
4092:
4093: /* Substitute into X the registers into which we have reloaded
4094: the things that need reloading. The array `replacements'
4095: says contains the locations of all pointers that must be changed
4096: and says what to replace them with.
4097:
4098: Return the rtx that X translates into; usually X, but modified. */
4099:
4100: void
4101: subst_reloads ()
4102: {
4103: register int i;
4104:
4105: for (i = 0; i < n_replacements; i++)
4106: {
4107: register struct replacement *r = &replacements[i];
4108: register rtx reloadreg = reload_reg_rtx[r->what];
4109: if (reloadreg)
4110: {
4111: /* Encapsulate RELOADREG so its machine mode matches what
4112: used to be there. */
4113: if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode)
4114: reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg));
4115:
4116: /* If we are putting this into a SUBREG and RELOADREG is a
4117: SUBREG, we would be making nested SUBREGs, so we have to fix
4118: this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */
4119:
4120: if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG)
4121: {
4122: if (GET_MODE (*r->subreg_loc)
4123: == GET_MODE (SUBREG_REG (reloadreg)))
4124: *r->subreg_loc = SUBREG_REG (reloadreg);
4125: else
4126: {
4127: *r->where = SUBREG_REG (reloadreg);
4128: SUBREG_WORD (*r->subreg_loc) += SUBREG_WORD (reloadreg);
4129: }
4130: }
4131: else
4132: *r->where = reloadreg;
4133: }
4134: /* If reload got no reg and isn't optional, something's wrong. */
4135: else if (! reload_optional[r->what])
4136: abort ();
4137: }
4138: }
4139:
4140: /* Make a copy of any replacements being done into X and move those copies
4141: to locations in Y, a copy of X. We only look at the highest level of
4142: the RTL. */
4143:
4144: void
4145: copy_replacements (x, y)
4146: rtx x;
4147: rtx y;
4148: {
4149: int i, j;
4150: enum rtx_code code = GET_CODE (x);
4151: char *fmt = GET_RTX_FORMAT (code);
4152: struct replacement *r;
4153:
4154: /* We can't support X being a SUBREG because we might then need to know its
4155: location if something inside it was replaced. */
4156: if (code == SUBREG)
4157: abort ();
4158:
4159: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4160: if (fmt[i] == 'e')
4161: for (j = 0; j < n_replacements; j++)
4162: {
4163: if (replacements[j].subreg_loc == &XEXP (x, i))
4164: {
4165: r = &replacements[n_replacements++];
4166: r->where = replacements[j].where;
4167: r->subreg_loc = &XEXP (y, i);
4168: r->what = replacements[j].what;
4169: r->mode = replacements[j].mode;
4170: }
4171: else if (replacements[j].where == &XEXP (x, i))
4172: {
4173: r = &replacements[n_replacements++];
4174: r->where = &XEXP (y, i);
4175: r->subreg_loc = 0;
4176: r->what = replacements[j].what;
4177: r->mode = replacements[j].mode;
4178: }
4179: }
4180: }
4181:
4182: /* Return nonzero if register in range [REGNO, ENDREGNO)
4183: appears either explicitly or implicitly in X
4184: other than being stored into.
4185:
4186: References contained within the substructure at LOC do not count.
4187: LOC may be zero, meaning don't ignore anything.
4188:
4189: This is similar to refers_to_regno_p in rtlanal.c except that we
4190: look at equivalences for pseudos that didn't get hard registers. */
4191:
4192: int
4193: refers_to_regno_for_reload_p (regno, endregno, x, loc)
4194: int regno, endregno;
4195: rtx x;
4196: rtx *loc;
4197: {
4198: register int i;
4199: register RTX_CODE code;
4200: register char *fmt;
4201:
4202: if (x == 0)
4203: return 0;
4204:
4205: repeat:
4206: code = GET_CODE (x);
4207:
4208: switch (code)
4209: {
4210: case REG:
4211: i = REGNO (x);
4212:
4213: if (i >= FIRST_PSEUDO_REGISTER && reg_renumber[i] == -1
4214: && ((reg_equiv_address[i]
4215: && refers_to_regno_for_reload_p (regno, endregno,
4216: reg_equiv_address[i], 0))
4217: || (reg_equiv_mem[i]
4218: && refers_to_regno_for_reload_p (regno, endregno,
4219: XEXP (reg_equiv_mem[i], 0),
4220: 0))))
4221: return 1;
4222:
4223: return (endregno > i
4224: && regno < i + (i < FIRST_PSEUDO_REGISTER
4225: ? HARD_REGNO_NREGS (i, GET_MODE (x))
4226: : 1));
4227:
4228: case SUBREG:
4229: /* If this is a SUBREG of a hard reg, we can see exactly which
4230: registers are being modified. Otherwise, handle normally. */
4231: if (GET_CODE (SUBREG_REG (x)) == REG
4232: && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
4233: {
4234: int inner_regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x);
4235: int inner_endregno
4236: = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER
4237: ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
4238:
4239: return endregno > inner_regno && regno < inner_endregno;
4240: }
4241: break;
4242:
4243: case CLOBBER:
4244: case SET:
4245: if (&SET_DEST (x) != loc
4246: /* Note setting a SUBREG counts as referring to the REG it is in for
4247: a pseudo but not for hard registers since we can
4248: treat each word individually. */
4249: && ((GET_CODE (SET_DEST (x)) == SUBREG
4250: && loc != &SUBREG_REG (SET_DEST (x))
4251: && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
4252: && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
4253: && refers_to_regno_for_reload_p (regno, endregno,
4254: SUBREG_REG (SET_DEST (x)),
4255: loc))
4256: || (GET_CODE (SET_DEST (x)) != REG
4257: && refers_to_regno_for_reload_p (regno, endregno,
4258: SET_DEST (x), loc))))
4259: return 1;
4260:
4261: if (code == CLOBBER || loc == &SET_SRC (x))
4262: return 0;
4263: x = SET_SRC (x);
4264: goto repeat;
4265: }
4266:
4267: /* X does not match, so try its subexpressions. */
4268:
4269: fmt = GET_RTX_FORMAT (code);
4270: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4271: {
4272: if (fmt[i] == 'e' && loc != &XEXP (x, i))
4273: {
4274: if (i == 0)
4275: {
4276: x = XEXP (x, 0);
4277: goto repeat;
4278: }
4279: else
4280: if (refers_to_regno_for_reload_p (regno, endregno,
4281: XEXP (x, i), loc))
4282: return 1;
4283: }
4284: else if (fmt[i] == 'E')
4285: {
4286: register int j;
4287: for (j = XVECLEN (x, i) - 1; j >=0; j--)
4288: if (loc != &XVECEXP (x, i, j)
4289: && refers_to_regno_for_reload_p (regno, endregno,
4290: XVECEXP (x, i, j), loc))
4291: return 1;
4292: }
4293: }
4294: return 0;
4295: }
4296:
4297: #if 0
4298:
4299: /* [[This function is currently obsolete, now that volatility
4300: is represented by a special bit `volatil' so VOLATILE is never used;
4301: and UNCHANGING has never been brought into use.]]
4302:
4303: Alter X by eliminating all VOLATILE and UNCHANGING expressions.
4304: Each of them is replaced by its operand.
4305: Thus, (PLUS (VOLATILE (MEM (REG 5))) (CONST_INT 4))
4306: becomes (PLUS (MEM (REG 5)) (CONST_INT 4)).
4307:
4308: If X is itself a VOLATILE expression,
4309: we return the expression that should replace it
4310: but we do not modify X. */
4311:
4312: static rtx
4313: forget_volatility (x)
4314: register rtx x;
4315: {
4316: enum rtx_code code = GET_CODE (x);
4317: register char *fmt;
4318: register int i;
4319: register rtx value = 0;
4320:
4321: switch (code)
4322: {
4323: case LABEL_REF:
4324: case SYMBOL_REF:
4325: case CONST_INT:
4326: case CONST_DOUBLE:
4327: case CONST:
4328: case REG:
4329: case CC0:
4330: case PC:
4331: return x;
4332:
4333: case VOLATILE:
4334: case UNCHANGING:
4335: return XEXP (x, 0);
4336: }
4337:
4338: fmt = GET_RTX_FORMAT (code);
4339: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4340: {
4341: if (fmt[i] == 'e')
4342: XEXP (x, i) = forget_volatility (XEXP (x, i));
4343: if (fmt[i] == 'E')
4344: {
4345: register int j;
4346: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4347: XVECEXP (x, i, j) = forget_volatility (XVECEXP (x, i, j));
4348: }
4349: }
4350:
4351: return x;
4352: }
4353:
4354: #endif
4355:
4356: /* Check the insns before INSN to see if there is a suitable register
4357: containing the same value as GOAL.
4358: If OTHER is -1, look for a register in class CLASS.
4359: Otherwise, just see if register number OTHER shares GOAL's value.
4360:
4361: Return an rtx for the register found, or zero if none is found.
4362:
4363: If RELOAD_REG_P is (short *)1,
4364: we reject any hard reg that appears in reload_reg_rtx
4365: because such a hard reg is also needed coming into this insn.
4366:
4367: If RELOAD_REG_P is any other nonzero value,
4368: it is a vector indexed by hard reg number
4369: and we reject any hard reg whose element in the vector is nonnegative
4370: as well as any that appears in reload_reg_rtx.
4371:
4372: If GOAL is zero, then GOALREG is a register number; we look
4373: for an equivalent for that register.
4374:
4375: MODE is the machine mode of the value we want an equivalence for.
4376: If GOAL is nonzero and not VOIDmode, then it must have mode MODE.
4377:
4378: This function is used by jump.c as well as in the reload pass.
4379:
4380: If GOAL is the sum of the stack pointer and a constant, we treat it
4381: as if it were a constant except that sp is required to be unchanging. */
4382:
4383: rtx
4384: find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode)
4385: register rtx goal;
4386: rtx insn;
4387: enum reg_class class;
4388: register int other;
4389: short *reload_reg_p;
4390: int goalreg;
4391: enum machine_mode mode;
4392: {
4393: register rtx p = insn;
4394: rtx valtry, value, where;
4395: register rtx pat;
4396: register int regno = -1;
4397: int valueno;
4398: int goal_mem = 0;
4399: int goal_const = 0;
4400: int goal_mem_addr_varies = 0;
4401: int need_stable_sp = 0;
4402: int nregs;
4403: int valuenregs;
4404:
4405: if (goal == 0)
4406: regno = goalreg;
4407: else if (GET_CODE (goal) == REG)
4408: regno = REGNO (goal);
4409: else if (GET_CODE (goal) == MEM)
4410: {
4411: enum rtx_code code = GET_CODE (XEXP (goal, 0));
4412: if (MEM_VOLATILE_P (goal))
4413: return 0;
4414: if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT)
4415: return 0;
4416: /* An address with side effects must be reexecuted. */
4417: switch (code)
4418: {
4419: case POST_INC:
4420: case PRE_INC:
4421: case POST_DEC:
4422: case PRE_DEC:
4423: return 0;
4424: }
4425: goal_mem = 1;
4426: }
4427: else if (CONSTANT_P (goal))
4428: goal_const = 1;
4429: else if (GET_CODE (goal) == PLUS
4430: && XEXP (goal, 0) == stack_pointer_rtx
4431: && CONSTANT_P (XEXP (goal, 1)))
4432: goal_const = need_stable_sp = 1;
4433: else
4434: return 0;
4435:
4436: /* On some machines, certain regs must always be rejected
4437: because they don't behave the way ordinary registers do. */
4438:
4439: #ifdef OVERLAPPING_REGNO_P
4440: if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4441: && OVERLAPPING_REGNO_P (regno))
4442: return 0;
4443: #endif
4444:
4445: /* Scan insns back from INSN, looking for one that copies
4446: a value into or out of GOAL.
4447: Stop and give up if we reach a label. */
4448:
4449: while (1)
4450: {
4451: p = PREV_INSN (p);
4452: if (p == 0 || GET_CODE (p) == CODE_LABEL)
4453: return 0;
4454: if (GET_CODE (p) == INSN
4455: /* If we don't want spill regs ... */
4456: && (! (reload_reg_p != 0 && reload_reg_p != (short *)1)
4457: /* ... then ignore insns introduced by reload; they aren't useful
4458: and can cause results in reload_as_needed to be different
4459: from what they were when calculating the need for spills.
4460: If we notice an input-reload insn here, we will reject it below,
4461: but it might hide a usable equivalent. That makes bad code.
4462: It may even abort: perhaps no reg was spilled for this insn
4463: because it was assumed we would find that equivalent. */
4464: || INSN_UID (p) < reload_first_uid))
4465: {
4466: pat = single_set (p);
4467: /* First check for something that sets some reg equal to GOAL. */
4468: if (pat != 0
4469: && ((regno >= 0
4470: && true_regnum (SET_SRC (pat)) == regno
4471: && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
4472: ||
4473: (regno >= 0
4474: && true_regnum (SET_DEST (pat)) == regno
4475: && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0)
4476: ||
4477: (goal_const && rtx_equal_p (SET_SRC (pat), goal)
4478: && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
4479: || (goal_mem
4480: && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0
4481: && rtx_renumbered_equal_p (goal, SET_SRC (pat)))
4482: || (goal_mem
4483: && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0
4484: && rtx_renumbered_equal_p (goal, SET_DEST (pat)))))
4485: if (other >= 0
4486: ? valueno == other
4487: : ((unsigned) valueno < FIRST_PSEUDO_REGISTER
4488: && TEST_HARD_REG_BIT (reg_class_contents[(int) class],
4489: valueno)))
4490: {
4491: value = valtry;
4492: where = p;
4493: break;
4494: }
4495: }
4496: }
4497:
4498: /* We found a previous insn copying GOAL into a suitable other reg VALUE
4499: (or copying VALUE into GOAL, if GOAL is also a register).
4500: Now verify that VALUE is really valid. */
4501:
4502: /* VALUENO is the register number of VALUE; a hard register. */
4503:
4504: /* Don't try to re-use something that is killed in this insn. We want
4505: to be able to trust REG_UNUSED notes. */
4506: if (find_reg_note (where, REG_UNUSED, value))
4507: return 0;
4508:
4509: /* If we propose to get the value from the stack pointer or if GOAL is
4510: a MEM based on the stack pointer, we need a stable SP. */
4511: if (valueno == STACK_POINTER_REGNUM
4512: || (goal_mem && reg_overlap_mentioned_p (stack_pointer_rtx, goal)))
4513: need_stable_sp = 1;
4514:
4515: /* Reject VALUE if the copy-insn moved the wrong sort of datum. */
4516: if (GET_MODE (value) != mode)
4517: return 0;
4518:
4519: /* Reject VALUE if it was loaded from GOAL
4520: and is also a register that appears in the address of GOAL. */
4521:
4522: if (goal_mem && value == SET_DEST (PATTERN (where))
4523: && refers_to_regno_p (valueno,
4524: valueno + HARD_REGNO_NREGS (valueno, mode),
4525: goal, 0))
4526: return 0;
4527:
4528: /* Reject registers that overlap GOAL. */
4529:
4530: if (!goal_mem && !goal_const
4531: && regno + HARD_REGNO_NREGS (regno, mode) > valueno
4532: && regno < valueno + HARD_REGNO_NREGS (valueno, mode))
4533: return 0;
4534:
4535: /* Reject VALUE if it is one of the regs reserved for reloads.
4536: Reload1 knows how to reuse them anyway, and it would get
4537: confused if we allocated one without its knowledge.
4538: (Now that insns introduced by reload are ignored above,
4539: this case shouldn't happen, but I'm not positive.) */
4540:
4541: if (reload_reg_p != 0 && reload_reg_p != (short *)1
4542: && reload_reg_p[valueno] >= 0)
4543: return 0;
4544:
4545: /* On some machines, certain regs must always be rejected
4546: because they don't behave the way ordinary registers do. */
4547:
4548: #ifdef OVERLAPPING_REGNO_P
4549: if (OVERLAPPING_REGNO_P (valueno))
4550: return 0;
4551: #endif
4552:
4553: nregs = HARD_REGNO_NREGS (regno, mode);
4554: valuenregs = HARD_REGNO_NREGS (valueno, mode);
4555:
4556: /* Reject VALUE if it is a register being used for an input reload
4557: even if it is not one of those reserved. */
4558:
4559: if (reload_reg_p != 0)
4560: {
4561: int i;
4562: for (i = 0; i < n_reloads; i++)
4563: if (reload_reg_rtx[i] != 0 && reload_in[i])
4564: {
4565: int regno1 = REGNO (reload_reg_rtx[i]);
4566: int nregs1 = HARD_REGNO_NREGS (regno1,
4567: GET_MODE (reload_reg_rtx[i]));
4568: if (regno1 < valueno + valuenregs
4569: && regno1 + nregs1 > valueno)
4570: return 0;
4571: }
4572: }
4573:
4574: if (goal_mem)
4575: goal_mem_addr_varies = rtx_addr_varies_p (goal);
4576:
4577: /* Now verify that the values of GOAL and VALUE remain unaltered
4578: until INSN is reached. */
4579:
4580: p = insn;
4581: while (1)
4582: {
4583: p = PREV_INSN (p);
4584: if (p == where)
4585: return value;
4586:
4587: /* Don't trust the conversion past a function call
4588: if either of the two is in a call-clobbered register, or memory. */
4589: if (GET_CODE (p) == CALL_INSN
4590: && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4591: && call_used_regs[regno])
4592: ||
4593: (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER
4594: && call_used_regs[valueno])
4595: ||
4596: goal_mem
4597: || need_stable_sp))
4598: return 0;
4599:
4600: #ifdef INSN_CLOBBERS_REGNO_P
4601: if ((valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER
4602: && INSN_CLOBBERS_REGNO_P (p, valueno))
4603: || (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4604: && INSN_CLOBBERS_REGNO_P (p, regno)))
4605: return 0;
4606: #endif
4607:
4608: if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
4609: {
4610: /* If this insn P stores in either GOAL or VALUE, return 0.
4611: If GOAL is a memory ref and this insn writes memory, return 0.
4612: If GOAL is a memory ref and its address is not constant,
4613: and this insn P changes a register used in GOAL, return 0. */
4614:
4615: pat = PATTERN (p);
4616: if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
4617: {
4618: register rtx dest = SET_DEST (pat);
4619: while (GET_CODE (dest) == SUBREG
4620: || GET_CODE (dest) == ZERO_EXTRACT
4621: || GET_CODE (dest) == SIGN_EXTRACT
4622: || GET_CODE (dest) == STRICT_LOW_PART)
4623: dest = XEXP (dest, 0);
4624: if (GET_CODE (dest) == REG)
4625: {
4626: register int xregno = REGNO (dest);
4627: int xnregs;
4628: if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
4629: xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
4630: else
4631: xnregs = 1;
4632: if (xregno < regno + nregs && xregno + xnregs > regno)
4633: return 0;
4634: if (xregno < valueno + valuenregs
4635: && xregno + xnregs > valueno)
4636: return 0;
4637: if (goal_mem_addr_varies
4638: && reg_overlap_mentioned_p (dest, goal))
4639: return 0;
4640: }
4641: else if (goal_mem && GET_CODE (dest) == MEM
4642: && ! push_operand (dest, GET_MODE (dest)))
4643: return 0;
4644: else if (need_stable_sp && push_operand (dest, GET_MODE (dest)))
4645: return 0;
4646: }
4647: else if (GET_CODE (pat) == PARALLEL)
4648: {
4649: register int i;
4650: for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
4651: {
4652: register rtx v1 = XVECEXP (pat, 0, i);
4653: if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER)
4654: {
4655: register rtx dest = SET_DEST (v1);
4656: while (GET_CODE (dest) == SUBREG
4657: || GET_CODE (dest) == ZERO_EXTRACT
4658: || GET_CODE (dest) == SIGN_EXTRACT
4659: || GET_CODE (dest) == STRICT_LOW_PART)
4660: dest = XEXP (dest, 0);
4661: if (GET_CODE (dest) == REG)
4662: {
4663: register int xregno = REGNO (dest);
4664: int xnregs;
4665: if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
4666: xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
4667: else
4668: xnregs = 1;
4669: if (xregno < regno + nregs
4670: && xregno + xnregs > regno)
4671: return 0;
4672: if (xregno < valueno + valuenregs
4673: && xregno + xnregs > valueno)
4674: return 0;
4675: if (goal_mem_addr_varies
4676: && reg_overlap_mentioned_p (dest, goal))
4677: return 0;
4678: }
4679: else if (goal_mem && GET_CODE (dest) == MEM
4680: && ! push_operand (dest, GET_MODE (dest)))
4681: return 0;
4682: else if (need_stable_sp
4683: && push_operand (dest, GET_MODE (dest)))
4684: return 0;
4685: }
4686: }
4687: }
4688:
4689: #ifdef AUTO_INC_DEC
4690: /* If this insn auto-increments or auto-decrements
4691: either regno or valueno, return 0 now.
4692: If GOAL is a memory ref and its address is not constant,
4693: and this insn P increments a register used in GOAL, return 0. */
4694: {
4695: register rtx link;
4696:
4697: for (link = REG_NOTES (p); link; link = XEXP (link, 1))
4698: if (REG_NOTE_KIND (link) == REG_INC
4699: && GET_CODE (XEXP (link, 0)) == REG)
4700: {
4701: register int incno = REGNO (XEXP (link, 0));
4702: if (incno < regno + nregs && incno >= regno)
4703: return 0;
4704: if (incno < valueno + valuenregs && incno >= valueno)
4705: return 0;
4706: if (goal_mem_addr_varies
4707: && reg_overlap_mentioned_p (XEXP (link, 0), goal))
4708: return 0;
4709: }
4710: }
4711: #endif
4712: }
4713: }
4714: }
4715:
4716: /* Find a place where INCED appears in an increment or decrement operator
4717: within X, and return the amount INCED is incremented or decremented by.
4718: The value is always positive. */
4719:
4720: static int
4721: find_inc_amount (x, inced)
4722: rtx x, inced;
4723: {
4724: register enum rtx_code code = GET_CODE (x);
4725: register char *fmt;
4726: register int i;
4727:
4728: if (code == MEM)
4729: {
4730: register rtx addr = XEXP (x, 0);
4731: if ((GET_CODE (addr) == PRE_DEC
4732: || GET_CODE (addr) == POST_DEC
4733: || GET_CODE (addr) == PRE_INC
4734: || GET_CODE (addr) == POST_INC)
4735: && XEXP (addr, 0) == inced)
4736: return GET_MODE_SIZE (GET_MODE (x));
4737: }
4738:
4739: fmt = GET_RTX_FORMAT (code);
4740: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4741: {
4742: if (fmt[i] == 'e')
4743: {
4744: register int tem = find_inc_amount (XEXP (x, i), inced);
4745: if (tem != 0)
4746: return tem;
4747: }
4748: if (fmt[i] == 'E')
4749: {
4750: register int j;
4751: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4752: {
4753: register int tem = find_inc_amount (XVECEXP (x, i, j), inced);
4754: if (tem != 0)
4755: return tem;
4756: }
4757: }
4758: }
4759:
4760: return 0;
4761: }
4762:
4763: /* Return 1 if register REGNO is the subject of a clobber in insn INSN. */
4764:
4765: int
4766: regno_clobbered_p (regno, insn)
4767: int regno;
4768: rtx insn;
4769: {
4770: if (GET_CODE (PATTERN (insn)) == CLOBBER
4771: && GET_CODE (XEXP (PATTERN (insn), 0)) == REG)
4772: return REGNO (XEXP (PATTERN (insn), 0)) == regno;
4773:
4774: if (GET_CODE (PATTERN (insn)) == PARALLEL)
4775: {
4776: int i = XVECLEN (PATTERN (insn), 0) - 1;
4777:
4778: for (; i >= 0; i--)
4779: {
4780: rtx elt = XVECEXP (PATTERN (insn), 0, i);
4781: if (GET_CODE (elt) == CLOBBER && GET_CODE (XEXP (elt, 0)) == REG
4782: && REGNO (XEXP (elt, 0)) == regno)
4783: return 1;
4784: }
4785: }
4786:
4787: return 0;
4788: }
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