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1.1 root 1: /* Search an insn for pseudo regs that must be in hard regs and are not.
2: Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: /* This file contains subroutines used only from the file reload1.c.
22: It knows how to scan one insn for operands and values
23: that need to be copied into registers to make valid code.
24: It also finds other operands and values which are valid
25: but for which equivalent values in registers exist and
26: ought to be used instead.
27:
28: Before processing the first insn of the function, call `init_reload'.
29:
30: To scan an insn, call `find_reloads'. This does two things:
31: 1. sets up tables describing which values must be reloaded
32: for this insn, and what kind of hard regs they must be reloaded into;
33: 2. optionally record the locations where those values appear in
34: the data, so they can be replaced properly later.
35: This is done only if the second arg to `find_reloads' is nonzero.
36:
37: The third arg to `find_reloads' specifies the number of levels
38: of indirect addressing supported by the machine. If it is zero,
39: indirect addressing is not valid. If it is one, (MEM (REG n))
40: is valid even if (REG n) did not get a hard register; if it is two,
41: (MEM (MEM (REG n))) is also valid even if (REG n) did not get a
42: hard register, and similarly for higher values.
43:
44: Then you must choose the hard regs to reload those pseudo regs into,
45: and generate appropriate load insns before this insn and perhaps
46: also store insns after this insn. Set up the array `reload_reg_rtx'
47: to contain the REG rtx's for the registers you used. In some
48: cases `find_reloads' will return a nonzero value in `reload_reg_rtx'
49: for certain reloads. Then that tells you which register to use,
50: so you do not need to allocate one. But you still do need to add extra
51: instructions to copy the value into and out of that register.
52:
53: Finally you must call `subst_reloads' to substitute the reload reg rtx's
54: into the locations already recorded.
55:
56: NOTE SIDE EFFECTS:
57:
58: find_reloads can alter the operands of the instruction it is called on.
59:
60: 1. Two operands of any sort may be interchanged, if they are in a
61: commutative instruction.
62: This happens only if find_reloads thinks the instruction will compile
63: better that way.
64:
65: 2. Pseudo-registers that are equivalent to constants are replaced
66: with those constants if they are not in hard registers.
67:
68: 1 happens every time find_reloads is called.
69: 2 happens only when REPLACE is 1, which is only when
70: actually doing the reloads, not when just counting them.
71:
72:
73: Using a reload register for several reloads in one insn:
74:
75: When an insn has reloads, it is considered as having three parts:
76: the input reloads, the insn itself after reloading, and the output reloads.
77: Reloads of values used in memory addresses are often needed for only one part.
78:
79: When this is so, reload_when_needed records which part needs the reload.
80: Two reloads for different parts of the insn can share the same reload
81: register.
82:
83: When a reload is used for addresses in multiple parts, or when it is
84: an ordinary operand, it is classified as RELOAD_OTHER, and cannot share
85: a register with any other reload. */
86:
87: #define REG_OK_STRICT
88:
89: #include "config.h"
90: #include "rtl.h"
91: #include "insn-config.h"
92: #include "insn-codes.h"
93: #include "recog.h"
94: #include "reload.h"
95: #include "regs.h"
96: #include "hard-reg-set.h"
97: #include "flags.h"
98: #include "real.h"
99:
100: #ifndef REGISTER_MOVE_COST
101: #define REGISTER_MOVE_COST(x, y) 2
102: #endif
103:
104: /* The variables set up by `find_reloads' are:
105:
106: n_reloads number of distinct reloads needed; max reload # + 1
107: tables indexed by reload number
108: reload_in rtx for value to reload from
109: reload_out rtx for where to store reload-reg afterward if nec
110: (often the same as reload_in)
111: reload_reg_class enum reg_class, saying what regs to reload into
112: reload_inmode enum machine_mode; mode this operand should have
113: when reloaded, on input.
114: reload_outmode enum machine_mode; mode this operand should have
115: when reloaded, on output.
116: reload_strict_low char; currently always zero; used to mean that this
117: reload is inside a STRICT_LOW_PART, but we don't
118: need to know this anymore.
119: reload_optional char, nonzero for an optional reload.
120: Optional reloads are ignored unless the
121: value is already sitting in a register.
122: reload_inc int, positive amount to increment or decrement by if
123: reload_in is a PRE_DEC, PRE_INC, POST_DEC, POST_INC.
124: Ignored otherwise (don't assume it is zero).
125: reload_in_reg rtx. A reg for which reload_in is the equivalent.
126: If reload_in is a symbol_ref which came from
127: reg_equiv_constant, then this is the pseudo
128: which has that symbol_ref as equivalent.
129: reload_reg_rtx rtx. This is the register to reload into.
130: If it is zero when `find_reloads' returns,
131: you must find a suitable register in the class
132: specified by reload_reg_class, and store here
133: an rtx for that register with mode from
134: reload_inmode or reload_outmode.
135: reload_nocombine char, nonzero if this reload shouldn't be
136: combined with another reload.
137: reload_needed_for rtx, operand this reload is needed for address of.
138: 0 means it isn't needed for addressing.
139: reload_needed_for_multiple
140: int, 1 if this reload needed for more than one thing.
141: reload_when_needed enum, classifies reload as needed either for
142: addressing an input reload, addressing an output,
143: for addressing a non-reloaded mem ref,
144: or for unspecified purposes (i.e., more than one
145: of the above).
146: reload_secondary_reload int, gives the reload number of a secondary
147: reload, when needed; otherwise -1
148: reload_secondary_p int, 1 if this is a secondary register for one
149: or more reloads.
150: reload_secondary_icode enum insn_code, if a secondary reload is required,
151: gives the INSN_CODE that uses the secondary
152: reload as a scratch register, or CODE_FOR_nothing
153: if the secondary reload register is to be an
154: intermediate register. */
155: int n_reloads;
156:
157: rtx reload_in[MAX_RELOADS];
158: rtx reload_out[MAX_RELOADS];
159: enum reg_class reload_reg_class[MAX_RELOADS];
160: enum machine_mode reload_inmode[MAX_RELOADS];
161: enum machine_mode reload_outmode[MAX_RELOADS];
162: char reload_strict_low[MAX_RELOADS];
163: rtx reload_reg_rtx[MAX_RELOADS];
164: char reload_optional[MAX_RELOADS];
165: int reload_inc[MAX_RELOADS];
166: rtx reload_in_reg[MAX_RELOADS];
167: char reload_nocombine[MAX_RELOADS];
168: int reload_needed_for_multiple[MAX_RELOADS];
169: rtx reload_needed_for[MAX_RELOADS];
170: enum reload_when_needed reload_when_needed[MAX_RELOADS];
171: int reload_secondary_reload[MAX_RELOADS];
172: int reload_secondary_p[MAX_RELOADS];
173: enum insn_code reload_secondary_icode[MAX_RELOADS];
174:
175: /* All the "earlyclobber" operands of the current insn
176: are recorded here. */
177: int n_earlyclobbers;
178: rtx reload_earlyclobbers[MAX_RECOG_OPERANDS];
179:
180: /* Replacing reloads.
181:
182: If `replace_reloads' is nonzero, then as each reload is recorded
183: an entry is made for it in the table `replacements'.
184: Then later `subst_reloads' can look through that table and
185: perform all the replacements needed. */
186:
187: /* Nonzero means record the places to replace. */
188: static int replace_reloads;
189:
190: /* Each replacement is recorded with a structure like this. */
191: struct replacement
192: {
193: rtx *where; /* Location to store in */
194: rtx *subreg_loc; /* Location of SUBREG if WHERE is inside
195: a SUBREG; 0 otherwise. */
196: int what; /* which reload this is for */
197: enum machine_mode mode; /* mode it must have */
198: };
199:
200: static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)];
201:
202: /* Number of replacements currently recorded. */
203: static int n_replacements;
204:
205: /* MEM-rtx's created for pseudo-regs in stack slots not directly addressable;
206: (see reg_equiv_address). */
207: static rtx memlocs[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)];
208: static int n_memlocs;
209:
1.1.1.4 ! root 210: #ifdef SECONDARY_MEMORY_NEEDED
! 211:
! 212: /* Save MEMs needed to copy from one class of registers to another. One MEM
! 213: is used per mode, but normally only one or two modes are ever used.
! 214:
! 215: We keep two versions, before and after register elimination. */
! 216:
! 217: static rtx secondary_memlocs[NUM_MACHINE_MODES];
! 218: static rtx secondary_memlocs_elim[NUM_MACHINE_MODES];
! 219: #endif
! 220:
1.1 root 221: /* The instruction we are doing reloads for;
222: so we can test whether a register dies in it. */
223: static rtx this_insn;
224:
225: /* Nonzero if this instruction is a user-specified asm with operands. */
226: static int this_insn_is_asm;
227:
228: /* If hard_regs_live_known is nonzero,
229: we can tell which hard regs are currently live,
230: at least enough to succeed in choosing dummy reloads. */
231: static int hard_regs_live_known;
232:
233: /* Indexed by hard reg number,
234: element is nonegative if hard reg has been spilled.
235: This vector is passed to `find_reloads' as an argument
236: and is not changed here. */
237: static short *static_reload_reg_p;
238:
239: /* Set to 1 in subst_reg_equivs if it changes anything. */
240: static int subst_reg_equivs_changed;
241:
242: /* On return from push_reload, holds the reload-number for the OUT
243: operand, which can be different for that from the input operand. */
244: static int output_reloadnum;
245:
246: static int alternative_allows_memconst ();
247: static rtx find_dummy_reload ();
248: static rtx find_reloads_toplev ();
249: static int find_reloads_address ();
250: static int find_reloads_address_1 ();
251: static void find_reloads_address_part ();
252: static int hard_reg_set_here_p ();
253: /* static rtx forget_volatility (); */
254: static rtx subst_reg_equivs ();
255: static rtx subst_indexed_address ();
1.1.1.4 ! root 256: void copy_replacements ();
1.1 root 257: rtx find_equiv_reg ();
258: static int find_inc_amount ();
259:
260: #ifdef HAVE_SECONDARY_RELOADS
261:
262: /* Determine if any secondary reloads are needed for loading (if IN_P is
263: non-zero) or storing (if IN_P is zero) X to or from a reload register of
264: register class RELOAD_CLASS in mode RELOAD_MODE.
265:
266: Return the register class of a secondary reload register, or NO_REGS if
267: none. *PMODE is set to the mode that the register is required in.
268: If the reload register is needed as a scratch register instead of an
269: intermediate register, *PICODE is set to the insn_code of the insn to be
270: used to load or store the primary reload register; otherwise *PICODE
271: is set to CODE_FOR_nothing.
272:
273: In some cases (such as storing MQ into an external memory location on
274: the RT), both an intermediate register and a scratch register. In that
275: case, *PICODE is set to CODE_FOR_nothing, the class for the intermediate
276: register is returned, and the *PTERTIARY_... variables are set to describe
277: the scratch register. */
278:
279: static enum reg_class
280: find_secondary_reload (x, reload_class, reload_mode, in_p, picode, pmode,
281: ptertiary_class, ptertiary_icode, ptertiary_mode)
282: rtx x;
283: enum reg_class reload_class;
284: enum machine_mode reload_mode;
285: int in_p;
286: enum insn_code *picode;
287: enum machine_mode *pmode;
288: enum reg_class *ptertiary_class;
289: enum insn_code *ptertiary_icode;
290: enum machine_mode *ptertiary_mode;
291: {
292: enum reg_class class = NO_REGS;
293: enum machine_mode mode = reload_mode;
294: enum insn_code icode = CODE_FOR_nothing;
295: enum reg_class t_class = NO_REGS;
296: enum machine_mode t_mode = VOIDmode;
297: enum insn_code t_icode = CODE_FOR_nothing;
298:
1.1.1.2 root 299: /* If X is a pseudo-register that has an equivalent MEM (actually, if it
300: is still a pseudo-register by now, it *must* have an equivalent MEM
301: but we don't want to assume that), use that equivalent when seeing if
302: a secondary reload is needed since whether or not a reload is needed
303: might be sensitive to the form of the MEM. */
304:
305: if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER
306: && reg_equiv_mem[REGNO (x)] != 0)
307: x = reg_equiv_mem[REGNO (x)];
308:
1.1 root 309: #ifdef SECONDARY_INPUT_RELOAD_CLASS
310: if (in_p)
311: class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x);
312: #endif
313:
314: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
315: if (! in_p)
316: class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x);
317: #endif
318:
319: /* If we don't need any secondary registers, go away; the rest of the
320: values won't be used. */
321: if (class == NO_REGS)
322: return NO_REGS;
323:
324: /* Get a possible insn to use. If the predicate doesn't accept X, don't
325: use the insn. */
326:
327: icode = (in_p ? reload_in_optab[(int) reload_mode]
328: : reload_out_optab[(int) reload_mode]);
329:
330: if (icode != CODE_FOR_nothing
331: && insn_operand_predicate[(int) icode][in_p]
332: && (! (insn_operand_predicate[(int) icode][in_p]) (x, reload_mode)))
333: icode = CODE_FOR_nothing;
334:
335: /* If we will be using an insn, see if it can directly handle the reload
336: register we will be using. If it can, the secondary reload is for a
337: scratch register. If it can't, we will use the secondary reload for
338: an intermediate register and require a tertiary reload for the scratch
339: register. */
340:
341: if (icode != CODE_FOR_nothing)
342: {
343: /* If IN_P is non-zero, the reload register will be the output in
344: operand 0. If IN_P is zero, the reload register will be the input
345: in operand 1. Outputs should have an initial "=", which we must
346: skip. */
347:
1.1.1.2 root 348: char insn_letter = insn_operand_constraint[(int) icode][!in_p][in_p];
1.1 root 349: enum reg_class insn_class
1.1.1.2 root 350: = (insn_letter == 'r' ? GENERAL_REGS
351: : REG_CLASS_FROM_LETTER (insn_letter));
1.1 root 352:
353: if (insn_class == NO_REGS
354: || (in_p && insn_operand_constraint[(int) icode][!in_p][0] != '=')
355: /* The scratch register's constraint must start with "=&". */
356: || insn_operand_constraint[(int) icode][2][0] != '='
357: || insn_operand_constraint[(int) icode][2][1] != '&')
358: abort ();
359:
360: if (reg_class_subset_p (reload_class, insn_class))
361: mode = insn_operand_mode[(int) icode][2];
362: else
363: {
1.1.1.2 root 364: char t_letter = insn_operand_constraint[(int) icode][2][2];
1.1 root 365: class = insn_class;
366: t_mode = insn_operand_mode[(int) icode][2];
1.1.1.2 root 367: t_class = (t_letter == 'r' ? GENERAL_REGS
368: : REG_CLASS_FROM_LETTER (t_letter));
1.1 root 369: t_icode = icode;
370: icode = CODE_FOR_nothing;
371: }
372: }
373:
374: *pmode = mode;
375: *picode = icode;
376: *ptertiary_class = t_class;
377: *ptertiary_mode = t_mode;
378: *ptertiary_icode = t_icode;
379:
380: return class;
381: }
382: #endif /* HAVE_SECONDARY_RELOADS */
383:
1.1.1.4 ! root 384: #ifdef SECONDARY_MEMORY_NEEDED
! 385:
! 386: /* Return a memory location that will be used to copy X in mode MODE.
! 387: If we haven't already made a location for this mode in this insn,
! 388: call find_reloads_address on the location being returned. */
! 389:
! 390: rtx
! 391: get_secondary_mem (x, mode)
! 392: rtx x;
! 393: enum machine_mode mode;
! 394: {
! 395: rtx loc;
! 396: int mem_valid;
! 397:
! 398: /* If MODE is narrower than a word, widen it. This is required because
! 399: most machines that require these memory locations do not support
! 400: short load and stores from all registers (e.g., FP registers). We could
! 401: possibly conditionalize this, but we lose nothing by doing the wider
! 402: mode. */
! 403:
! 404: if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
! 405: mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0);
! 406:
! 407: /* If we already have made a MEM for this insn, return it. */
! 408: if (secondary_memlocs_elim[(int) mode] != 0)
! 409: return secondary_memlocs_elim[(int) mode];
! 410:
! 411: /* If this is the first time we've tried to get a MEM for this mode,
! 412: allocate a new one. `something_changed' in reload will get set
! 413: by noticing that the frame size has changed. */
! 414:
! 415: if (secondary_memlocs[(int) mode] == 0)
! 416: secondary_memlocs[(int) mode]
! 417: = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
! 418:
! 419: /* Get a version of the address doing any eliminations needed. If that
! 420: didn't give us a new MEM, make a new one if it isn't valid. */
! 421:
! 422: loc = eliminate_regs (secondary_memlocs[(int) mode], 0, NULL_RTX);
! 423: mem_valid = strict_memory_address_p (mode, XEXP (loc, 0));
! 424:
! 425: if (! mem_valid && loc == secondary_memlocs[(int) mode])
! 426: loc = copy_rtx (loc);
! 427:
! 428: /* The only time the call below will do anything is if the stack
! 429: offset is too large. In that case IND_LEVELS doesn't matter, so we
! 430: can just pass a zero. */
! 431: if (! mem_valid)
! 432: find_reloads_address (mode, NULL_PTR, XEXP (loc, 0), &XEXP (loc, 0), x, 0);
! 433:
! 434: /* If the address was not valid to begin with, we can not save it, because
! 435: there is no guarantee that the reloads needed to make it valid will
! 436: occur before every use of this address. */
! 437:
! 438: else
! 439: secondary_memlocs_elim[(int) mode] = loc;
! 440:
! 441: return loc;
! 442: }
! 443:
! 444: /* Clear any secondary memory locations we've made. */
! 445:
! 446: void
! 447: clear_secondary_mem ()
! 448: {
! 449: int i;
! 450:
! 451: for (i = 0; i < NUM_MACHINE_MODES; i++)
! 452: secondary_memlocs[i] = 0;
! 453: }
! 454: #endif /* SECONDARY_MEMORY_NEEDED */
! 455:
1.1 root 456: /* Record one (sometimes two) reload that needs to be performed.
457: IN is an rtx saying where the data are to be found before this instruction.
458: OUT says where they must be stored after the instruction.
459: (IN is zero for data not read, and OUT is zero for data not written.)
460: INLOC and OUTLOC point to the places in the instructions where
461: IN and OUT were found.
462: CLASS is a register class required for the reloaded data.
463: INMODE is the machine mode that the instruction requires
464: for the reg that replaces IN and OUTMODE is likewise for OUT.
465:
466: If IN is zero, then OUT's location and mode should be passed as
467: INLOC and INMODE.
468:
469: STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx.
470:
471: OPTIONAL nonzero means this reload does not need to be performed:
472: it can be discarded if that is more convenient.
473:
474: The return value is the reload-number for this reload.
475:
476: If both IN and OUT are nonzero, in some rare cases we might
477: want to make two separate reloads. (Actually we never do this now.)
478: Therefore, the reload-number for OUT is stored in
479: output_reloadnum when we return; the return value applies to IN.
480: Usually (presently always), when IN and OUT are nonzero,
481: the two reload-numbers are equal, but the caller should be careful to
482: distinguish them. */
483:
484: static int
485: push_reload (in, out, inloc, outloc, class,
486: inmode, outmode, strict_low, optional, needed_for)
487: register rtx in, out;
488: rtx *inloc, *outloc;
489: enum reg_class class;
490: enum machine_mode inmode, outmode;
491: int strict_low;
492: int optional;
493: rtx needed_for;
494: {
495: register int i;
496: int dont_share = 0;
497: rtx *in_subreg_loc = 0, *out_subreg_loc = 0;
498: int secondary_reload = -1;
499: enum insn_code secondary_icode = CODE_FOR_nothing;
500:
501: /* Compare two RTX's. */
502: #define MATCHES(x, y) \
503: (x == y || (x != 0 && (GET_CODE (x) == REG \
504: ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \
505: : rtx_equal_p (x, y) && ! side_effects_p (x))))
506:
507: /* INMODE and/or OUTMODE could be VOIDmode if no mode
508: has been specified for the operand. In that case,
509: use the operand's mode as the mode to reload. */
510: if (inmode == VOIDmode && in != 0)
511: inmode = GET_MODE (in);
512: if (outmode == VOIDmode && out != 0)
513: outmode = GET_MODE (out);
514:
515: /* If IN is a pseudo register everywhere-equivalent to a constant, and
516: it is not in a hard register, reload straight from the constant,
517: since we want to get rid of such pseudo registers.
518: Often this is done earlier, but not always in find_reloads_address. */
519: if (in != 0 && GET_CODE (in) == REG)
520: {
521: register int regno = REGNO (in);
522:
523: if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
524: && reg_equiv_constant[regno] != 0)
525: in = reg_equiv_constant[regno];
526: }
527:
528: /* Likewise for OUT. Of course, OUT will never be equivalent to
529: an actual constant, but it might be equivalent to a memory location
530: (in the case of a parameter). */
531: if (out != 0 && GET_CODE (out) == REG)
532: {
533: register int regno = REGNO (out);
534:
535: if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
536: && reg_equiv_constant[regno] != 0)
537: out = reg_equiv_constant[regno];
538: }
539:
540: /* If we have a read-write operand with an address side-effect,
541: change either IN or OUT so the side-effect happens only once. */
542: if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out))
543: {
544: if (GET_CODE (XEXP (in, 0)) == POST_INC
545: || GET_CODE (XEXP (in, 0)) == POST_DEC)
546: in = gen_rtx (MEM, GET_MODE (in), XEXP (XEXP (in, 0), 0));
547: if (GET_CODE (XEXP (in, 0)) == PRE_INC
548: || GET_CODE (XEXP (in, 0)) == PRE_DEC)
549: out = gen_rtx (MEM, GET_MODE (out), XEXP (XEXP (out, 0), 0));
550: }
551:
552: /* If we are reloading a (SUBREG (MEM ...) ...) or (SUBREG constant ...),
553: really reload just the inside expression in its own mode.
554: If we have (SUBREG:M1 (REG:M2 ...) ...) with M1 wider than M2 and the
555: register is a pseudo, this will become the same as the above case.
556: Do the same for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where
557: either M1 is not valid for R or M2 is wider than a word but we only
558: need one word to store an M2-sized quantity in R.
559: Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere;
560: we can't handle it here because CONST_INT does not indicate a mode.
561:
562: Similarly, we must reload the inside expression if we have a
1.1.1.4 ! root 563: STRICT_LOW_PART (presumably, in == out in the cas).
! 564:
! 565: Also reload the inner expression if it does not require a secondary
! 566: reload but the SUBREG does. */
1.1 root 567:
568: if (in != 0 && GET_CODE (in) == SUBREG
569: && (GET_CODE (SUBREG_REG (in)) != REG
570: || strict_low
571: || (GET_CODE (SUBREG_REG (in)) == REG
572: && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER
573: && (GET_MODE_SIZE (inmode)
574: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))))
575: || (GET_CODE (SUBREG_REG (in)) == REG
576: && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
577: && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (in)), inmode)
578: || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD
579: && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
580: > UNITS_PER_WORD)
581: && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
582: / UNITS_PER_WORD)
583: != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)),
1.1.1.4 ! root 584: GET_MODE (SUBREG_REG (in)))))))
! 585: #ifdef SECONDARY_INPUT_RELOAD_CLASS
! 586: || (SECONDARY_INPUT_RELOAD_CLASS (class, inmode, in) != NO_REGS
! 587: && (SECONDARY_INPUT_RELOAD_CLASS (class,
! 588: GET_MODE (SUBREG_REG (in)),
! 589: SUBREG_REG (in))
! 590: == NO_REGS))
! 591: #endif
! 592: ))
1.1 root 593: {
594: in_subreg_loc = inloc;
595: inloc = &SUBREG_REG (in);
596: in = *inloc;
597: if (GET_CODE (in) == MEM)
598: /* This is supposed to happen only for paradoxical subregs made by
599: combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */
600: if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode))
601: abort ();
602: inmode = GET_MODE (in);
603: }
604:
605: /* Similarly for paradoxical and problematical SUBREGs on the output.
606: Note that there is no reason we need worry about the previous value
607: of SUBREG_REG (out); even if wider than out,
608: storing in a subreg is entitled to clobber it all
609: (except in the case of STRICT_LOW_PART,
610: and in that case the constraint should label it input-output.) */
611: if (out != 0 && GET_CODE (out) == SUBREG
612: && (GET_CODE (SUBREG_REG (out)) != REG
613: || strict_low
614: || (GET_CODE (SUBREG_REG (out)) == REG
615: && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER
616: && (GET_MODE_SIZE (outmode)
617: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))))
618: || (GET_CODE (SUBREG_REG (out)) == REG
619: && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
620: && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (out)), outmode)
621: || (GET_MODE_SIZE (outmode) <= UNITS_PER_WORD
622: && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
623: > UNITS_PER_WORD)
624: && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
625: / UNITS_PER_WORD)
626: != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)),
1.1.1.4 ! root 627: GET_MODE (SUBREG_REG (out)))))))
! 628: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
! 629: || (SECONDARY_OUTPUT_RELOAD_CLASS (class, outmode, out) != NO_REGS
! 630: && (SECONDARY_OUTPUT_RELOAD_CLASS (class,
! 631: GET_MODE (SUBREG_REG (out)),
! 632: SUBREG_REG (out))
! 633: == NO_REGS))
! 634: #endif
! 635: ))
1.1 root 636: {
637: out_subreg_loc = outloc;
638: outloc = &SUBREG_REG (out);
639: out = *outloc;
640: if (GET_CODE (out) == MEM
641: && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode))
642: abort ();
643: outmode = GET_MODE (out);
644: }
645:
646: /* That's all we use STRICT_LOW for, so clear it. At some point,
647: we may want to get rid of reload_strict_low. */
648: strict_low = 0;
649:
650: /* If IN appears in OUT, we can't share any input-only reload for IN. */
651: if (in != 0 && out != 0 && GET_CODE (out) == MEM
652: && (GET_CODE (in) == REG || GET_CODE (in) == MEM)
1.1.1.3 root 653: && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0)))
1.1 root 654: dont_share = 1;
655:
1.1.1.4 ! root 656: /* If IN is a SUBREG of a hard register, make a new REG. This
! 657: simplifies some of the cases below. */
! 658:
! 659: if (in != 0 && GET_CODE (in) == SUBREG && GET_CODE (SUBREG_REG (in)) == REG
! 660: && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER)
! 661: in = gen_rtx (REG, GET_MODE (in),
! 662: REGNO (SUBREG_REG (in)) + SUBREG_WORD (in));
! 663:
! 664: /* Similarly for OUT. */
! 665: if (out != 0 && GET_CODE (out) == SUBREG
! 666: && GET_CODE (SUBREG_REG (out)) == REG
! 667: && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER)
! 668: out = gen_rtx (REG, GET_MODE (out),
! 669: REGNO (SUBREG_REG (out)) + SUBREG_WORD (out));
! 670:
1.1 root 671: /* Narrow down the class of register wanted if that is
672: desirable on this machine for efficiency. */
673: if (in != 0)
674: class = PREFERRED_RELOAD_CLASS (in, class);
675:
1.1.1.4 ! root 676: /* Output reloads may need analagous treatment, different in detail. */
! 677: #ifdef PREFERRED_OUTPUT_RELOAD_CLASS
! 678: if (out != 0)
! 679: class = PREFERRED_OUTPUT_RELOAD_CLASS (out, class);
! 680: #endif
! 681:
1.1 root 682: /* Make sure we use a class that can handle the actual pseudo
683: inside any subreg. For example, on the 386, QImode regs
684: can appear within SImode subregs. Although GENERAL_REGS
685: can handle SImode, QImode needs a smaller class. */
686: #ifdef LIMIT_RELOAD_CLASS
687: if (in_subreg_loc)
688: class = LIMIT_RELOAD_CLASS (inmode, class);
689: else if (in != 0 && GET_CODE (in) == SUBREG)
690: class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), class);
691:
692: if (out_subreg_loc)
693: class = LIMIT_RELOAD_CLASS (outmode, class);
694: if (out != 0 && GET_CODE (out) == SUBREG)
695: class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), class);
696: #endif
697:
698: if (class == NO_REGS)
699: abort ();
700:
701: /* Verify that this class is at least possible for the mode that
702: is specified. */
703: if (this_insn_is_asm)
704: {
705: enum machine_mode mode;
706: if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode))
707: mode = inmode;
708: else
709: mode = outmode;
710: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
711: if (HARD_REGNO_MODE_OK (i, mode)
712: && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i))
713: {
714: int nregs = HARD_REGNO_NREGS (i, mode);
715:
716: int j;
717: for (j = 1; j < nregs; j++)
718: if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j))
719: break;
720: if (j == nregs)
721: break;
722: }
723: if (i == FIRST_PSEUDO_REGISTER)
724: {
725: error_for_asm (this_insn, "impossible register constraint in `asm'");
726: class = ALL_REGS;
727: }
728: }
729:
730: /* We can use an existing reload if the class is right
731: and at least one of IN and OUT is a match
732: and the other is at worst neutral.
733: (A zero compared against anything is neutral.) */
734: for (i = 0; i < n_reloads; i++)
735: if ((reg_class_subset_p (class, reload_reg_class[i])
736: || reg_class_subset_p (reload_reg_class[i], class))
737: && reload_strict_low[i] == strict_low
738: /* If the existing reload has a register, it must fit our class. */
739: && (reload_reg_rtx[i] == 0
740: || TEST_HARD_REG_BIT (reg_class_contents[(int) class],
741: true_regnum (reload_reg_rtx[i])))
742: && ((in != 0 && MATCHES (reload_in[i], in) && ! dont_share
743: && (out == 0 || reload_out[i] == 0 || MATCHES (reload_out[i], out)))
744: ||
745: (out != 0 && MATCHES (reload_out[i], out)
746: && (in == 0 || reload_in[i] == 0 || MATCHES (reload_in[i], in)))))
747: break;
748:
749: /* Reloading a plain reg for input can match a reload to postincrement
750: that reg, since the postincrement's value is the right value.
751: Likewise, it can match a preincrement reload, since we regard
752: the preincrementation as happening before any ref in this insn
753: to that register. */
754: if (i == n_reloads)
755: for (i = 0; i < n_reloads; i++)
756: if ((reg_class_subset_p (class, reload_reg_class[i])
757: || reg_class_subset_p (reload_reg_class[i], class))
758: /* If the existing reload has a register, it must fit our class. */
759: && (reload_reg_rtx[i] == 0
760: || TEST_HARD_REG_BIT (reg_class_contents[(int) class],
761: true_regnum (reload_reg_rtx[i])))
762: && reload_strict_low[i] == strict_low
763: && out == 0 && reload_out[i] == 0 && reload_in[i] != 0
764: && ((GET_CODE (in) == REG
765: && (GET_CODE (reload_in[i]) == POST_INC
766: || GET_CODE (reload_in[i]) == POST_DEC
767: || GET_CODE (reload_in[i]) == PRE_INC
768: || GET_CODE (reload_in[i]) == PRE_DEC)
769: && MATCHES (XEXP (reload_in[i], 0), in))
770: ||
771: (GET_CODE (reload_in[i]) == REG
772: && (GET_CODE (in) == POST_INC
773: || GET_CODE (in) == POST_DEC
774: || GET_CODE (in) == PRE_INC
775: || GET_CODE (in) == PRE_DEC)
776: && MATCHES (XEXP (in, 0), reload_in[i]))))
777: {
778: /* Make sure reload_in ultimately has the increment,
779: not the plain register. */
780: if (GET_CODE (in) == REG)
781: in = reload_in[i];
782: break;
783: }
784:
785: if (i == n_reloads)
786: {
787: #ifdef HAVE_SECONDARY_RELOADS
788: enum reg_class secondary_class = NO_REGS;
789: enum reg_class secondary_out_class = NO_REGS;
790: enum machine_mode secondary_mode = inmode;
791: enum machine_mode secondary_out_mode = outmode;
792: enum insn_code secondary_icode;
793: enum insn_code secondary_out_icode = CODE_FOR_nothing;
794: enum reg_class tertiary_class = NO_REGS;
795: enum reg_class tertiary_out_class = NO_REGS;
796: enum machine_mode tertiary_mode;
797: enum machine_mode tertiary_out_mode;
798: enum insn_code tertiary_icode;
799: enum insn_code tertiary_out_icode = CODE_FOR_nothing;
800: int tertiary_reload = -1;
801:
802: /* See if we need a secondary reload register to move between
803: CLASS and IN or CLASS and OUT. Get the modes and icodes to
804: use for each of them if so. */
805:
806: #ifdef SECONDARY_INPUT_RELOAD_CLASS
807: if (in != 0)
808: secondary_class
809: = find_secondary_reload (in, class, inmode, 1, &secondary_icode,
810: &secondary_mode, &tertiary_class,
811: &tertiary_icode, &tertiary_mode);
812: #endif
813:
814: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
815: if (out != 0 && GET_CODE (out) != SCRATCH)
816: secondary_out_class
817: = find_secondary_reload (out, class, outmode, 0,
818: &secondary_out_icode, &secondary_out_mode,
819: &tertiary_out_class, &tertiary_out_icode,
820: &tertiary_out_mode);
821: #endif
822:
823: /* We can only record one secondary and one tertiary reload. If both
824: IN and OUT need secondary reloads, we can only make an in-out
825: reload if neither need an insn and if the classes are compatible. */
826:
827: if (secondary_class != NO_REGS && secondary_out_class != NO_REGS
828: && reg_class_subset_p (secondary_out_class, secondary_class))
829: secondary_class = secondary_out_class;
830:
831: if (secondary_class != NO_REGS && secondary_out_class != NO_REGS
832: && (! reg_class_subset_p (secondary_class, secondary_out_class)
833: || secondary_icode != CODE_FOR_nothing
834: || secondary_out_icode != CODE_FOR_nothing))
835: {
1.1.1.4 ! root 836: push_reload (NULL_RTX, out, NULL_PTR, outloc, class,
! 837: VOIDmode, outmode, strict_low, optional, needed_for);
1.1 root 838: out = 0;
839: outloc = 0;
840: outmode = VOIDmode;
841: }
842:
843: /* If we need a secondary reload for OUT but not IN, copy the
844: information. */
845: if (secondary_class == NO_REGS && secondary_out_class != NO_REGS)
846: {
847: secondary_class = secondary_out_class;
848: secondary_icode = secondary_out_icode;
849: tertiary_class = tertiary_out_class;
850: tertiary_icode = tertiary_out_icode;
851: tertiary_mode = tertiary_out_mode;
852: }
853:
854: if (secondary_class != NO_REGS)
855: {
856: /* If we need a tertiary reload, see if we have one we can reuse
857: or else make one. */
858:
859: if (tertiary_class != NO_REGS)
860: {
861: for (tertiary_reload = 0; tertiary_reload < n_reloads;
862: tertiary_reload++)
863: if (reload_secondary_p[tertiary_reload]
864: && (reg_class_subset_p (tertiary_class,
865: reload_reg_class[tertiary_reload])
866: || reg_class_subset_p (reload_reg_class[tertiary_reload],
867: tertiary_class))
868: && ((reload_inmode[tertiary_reload] == tertiary_mode)
869: || reload_inmode[tertiary_reload] == VOIDmode)
870: && ((reload_outmode[tertiary_reload] == tertiary_mode)
871: || reload_outmode[tertiary_reload] == VOIDmode)
872: && (reload_secondary_icode[tertiary_reload]
873: == CODE_FOR_nothing))
874:
875: {
876: if (tertiary_mode != VOIDmode)
877: reload_inmode[tertiary_reload] = tertiary_mode;
878: if (tertiary_out_mode != VOIDmode)
879: reload_outmode[tertiary_reload] = tertiary_mode;
880: if (reg_class_subset_p (tertiary_class,
881: reload_reg_class[tertiary_reload]))
882: reload_reg_class[tertiary_reload] = tertiary_class;
883: if (reload_needed_for[tertiary_reload] != needed_for)
884: reload_needed_for_multiple[tertiary_reload] = 1;
885: reload_optional[tertiary_reload] &= optional;
886: reload_secondary_p[tertiary_reload] = 1;
887: }
888:
889: if (tertiary_reload == n_reloads)
890: {
891: /* We need to make a new tertiary reload for this register
892: class. */
893: reload_in[tertiary_reload] = reload_out[tertiary_reload] = 0;
894: reload_reg_class[tertiary_reload] = tertiary_class;
895: reload_inmode[tertiary_reload] = tertiary_mode;
896: reload_outmode[tertiary_reload] = tertiary_mode;
897: reload_reg_rtx[tertiary_reload] = 0;
898: reload_optional[tertiary_reload] = optional;
899: reload_inc[tertiary_reload] = 0;
900: reload_strict_low[tertiary_reload] = 0;
901: /* Maybe we could combine these, but it seems too tricky. */
902: reload_nocombine[tertiary_reload] = 1;
903: reload_in_reg[tertiary_reload] = 0;
904: reload_needed_for[tertiary_reload] = needed_for;
905: reload_needed_for_multiple[tertiary_reload] = 0;
906: reload_secondary_reload[tertiary_reload] = -1;
907: reload_secondary_icode[tertiary_reload] = CODE_FOR_nothing;
908: reload_secondary_p[tertiary_reload] = 1;
909:
910: n_reloads++;
911: i = n_reloads;
912: }
913: }
914:
915: /* See if we can reuse an existing secondary reload. */
916: for (secondary_reload = 0; secondary_reload < n_reloads;
917: secondary_reload++)
918: if (reload_secondary_p[secondary_reload]
919: && (reg_class_subset_p (secondary_class,
920: reload_reg_class[secondary_reload])
921: || reg_class_subset_p (reload_reg_class[secondary_reload],
922: secondary_class))
923: && ((reload_inmode[secondary_reload] == secondary_mode)
924: || reload_inmode[secondary_reload] == VOIDmode)
925: && ((reload_outmode[secondary_reload] == secondary_out_mode)
926: || reload_outmode[secondary_reload] == VOIDmode)
927: && reload_secondary_reload[secondary_reload] == tertiary_reload
928: && reload_secondary_icode[secondary_reload] == tertiary_icode)
929: {
930: if (secondary_mode != VOIDmode)
931: reload_inmode[secondary_reload] = secondary_mode;
932: if (secondary_out_mode != VOIDmode)
933: reload_outmode[secondary_reload] = secondary_out_mode;
934: if (reg_class_subset_p (secondary_class,
935: reload_reg_class[secondary_reload]))
936: reload_reg_class[secondary_reload] = secondary_class;
937: if (reload_needed_for[secondary_reload] != needed_for)
938: reload_needed_for_multiple[secondary_reload] = 1;
939: reload_optional[secondary_reload] &= optional;
940: reload_secondary_p[secondary_reload] = 1;
941: }
942:
943: if (secondary_reload == n_reloads)
944: {
945: /* We need to make a new secondary reload for this register
946: class. */
947: reload_in[secondary_reload] = reload_out[secondary_reload] = 0;
948: reload_reg_class[secondary_reload] = secondary_class;
949: reload_inmode[secondary_reload] = secondary_mode;
950: reload_outmode[secondary_reload] = secondary_out_mode;
951: reload_reg_rtx[secondary_reload] = 0;
952: reload_optional[secondary_reload] = optional;
953: reload_inc[secondary_reload] = 0;
954: reload_strict_low[secondary_reload] = 0;
955: /* Maybe we could combine these, but it seems too tricky. */
956: reload_nocombine[secondary_reload] = 1;
957: reload_in_reg[secondary_reload] = 0;
958: reload_needed_for[secondary_reload] = needed_for;
959: reload_needed_for_multiple[secondary_reload] = 0;
960: reload_secondary_reload[secondary_reload] = tertiary_reload;
961: reload_secondary_icode[secondary_reload] = tertiary_icode;
962: reload_secondary_p[secondary_reload] = 1;
963:
964: n_reloads++;
965: i = n_reloads;
1.1.1.4 ! root 966:
! 967: #ifdef SECONDARY_MEMORY_NEEDED
! 968: /* If we need a memory location to copy between the two
! 969: reload regs, set it up now. */
! 970:
! 971: if (in != 0 && secondary_icode == CODE_FOR_nothing
! 972: && SECONDARY_MEMORY_NEEDED (secondary_class, class, inmode))
! 973: get_secondary_mem (in, inmode);
! 974:
! 975: if (out != 0 && secondary_icode == CODE_FOR_nothing
! 976: && SECONDARY_MEMORY_NEEDED (class, secondary_class, outmode))
! 977: get_secondary_mem (out, outmode);
! 978: #endif
1.1 root 979: }
980: }
981: #endif
982:
983: /* We found no existing reload suitable for re-use.
984: So add an additional reload. */
985:
986: reload_in[i] = in;
987: reload_out[i] = out;
988: reload_reg_class[i] = class;
989: reload_inmode[i] = inmode;
990: reload_outmode[i] = outmode;
991: reload_reg_rtx[i] = 0;
992: reload_optional[i] = optional;
993: reload_inc[i] = 0;
994: reload_strict_low[i] = strict_low;
995: reload_nocombine[i] = 0;
996: reload_in_reg[i] = inloc ? *inloc : 0;
997: reload_needed_for[i] = needed_for;
998: reload_needed_for_multiple[i] = 0;
999: reload_secondary_reload[i] = secondary_reload;
1000: reload_secondary_icode[i] = secondary_icode;
1001: reload_secondary_p[i] = 0;
1002:
1003: n_reloads++;
1.1.1.4 ! root 1004:
! 1005: #ifdef SECONDARY_MEMORY_NEEDED
! 1006: /* If a memory location is needed for the copy, make one. */
! 1007: if (in != 0 && GET_CODE (in) == REG
! 1008: && REGNO (in) < FIRST_PSEUDO_REGISTER
! 1009: && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
! 1010: class, inmode))
! 1011: get_secondary_mem (in, inmode);
! 1012:
! 1013: if (out != 0 && GET_CODE (out) == REG
! 1014: && REGNO (out) < FIRST_PSEUDO_REGISTER
! 1015: && SECONDARY_MEMORY_NEEDED (class, REGNO_REG_CLASS (REGNO (out)),
! 1016: outmode))
! 1017: get_secondary_mem (out, outmode);
! 1018: #endif
1.1 root 1019: }
1020: else
1021: {
1022: /* We are reusing an existing reload,
1023: but we may have additional information for it.
1024: For example, we may now have both IN and OUT
1025: while the old one may have just one of them. */
1026:
1027: if (inmode != VOIDmode)
1028: reload_inmode[i] = inmode;
1029: if (outmode != VOIDmode)
1030: reload_outmode[i] = outmode;
1031: if (in != 0)
1032: reload_in[i] = in;
1033: if (out != 0)
1034: reload_out[i] = out;
1035: if (reg_class_subset_p (class, reload_reg_class[i]))
1036: reload_reg_class[i] = class;
1037: reload_optional[i] &= optional;
1038: if (reload_needed_for[i] != needed_for)
1039: reload_needed_for_multiple[i] = 1;
1040: }
1041:
1042: /* If the ostensible rtx being reload differs from the rtx found
1043: in the location to substitute, this reload is not safe to combine
1044: because we cannot reliably tell whether it appears in the insn. */
1045:
1046: if (in != 0 && in != *inloc)
1047: reload_nocombine[i] = 1;
1048:
1049: #if 0
1050: /* This was replaced by changes in find_reloads_address_1 and the new
1051: function inc_for_reload, which go with a new meaning of reload_inc. */
1052:
1053: /* If this is an IN/OUT reload in an insn that sets the CC,
1054: it must be for an autoincrement. It doesn't work to store
1055: the incremented value after the insn because that would clobber the CC.
1056: So we must do the increment of the value reloaded from,
1057: increment it, store it back, then decrement again. */
1058: if (out != 0 && sets_cc0_p (PATTERN (this_insn)))
1059: {
1060: out = 0;
1061: reload_out[i] = 0;
1062: reload_inc[i] = find_inc_amount (PATTERN (this_insn), in);
1063: /* If we did not find a nonzero amount-to-increment-by,
1064: that contradicts the belief that IN is being incremented
1065: in an address in this insn. */
1066: if (reload_inc[i] == 0)
1067: abort ();
1068: }
1069: #endif
1070:
1071: /* If we will replace IN and OUT with the reload-reg,
1072: record where they are located so that substitution need
1073: not do a tree walk. */
1074:
1075: if (replace_reloads)
1076: {
1077: if (inloc != 0)
1078: {
1079: register struct replacement *r = &replacements[n_replacements++];
1080: r->what = i;
1081: r->subreg_loc = in_subreg_loc;
1082: r->where = inloc;
1083: r->mode = inmode;
1084: }
1085: if (outloc != 0 && outloc != inloc)
1086: {
1087: register struct replacement *r = &replacements[n_replacements++];
1088: r->what = i;
1089: r->where = outloc;
1090: r->subreg_loc = out_subreg_loc;
1091: r->mode = outmode;
1092: }
1093: }
1094:
1095: /* If this reload is just being introduced and it has both
1096: an incoming quantity and an outgoing quantity that are
1097: supposed to be made to match, see if either one of the two
1098: can serve as the place to reload into.
1099:
1100: If one of them is acceptable, set reload_reg_rtx[i]
1101: to that one. */
1102:
1103: if (in != 0 && out != 0 && in != out && reload_reg_rtx[i] == 0)
1104: {
1105: reload_reg_rtx[i] = find_dummy_reload (in, out, inloc, outloc,
1106: reload_reg_class[i], i);
1107:
1108: /* If the outgoing register already contains the same value
1109: as the incoming one, we can dispense with loading it.
1110: The easiest way to tell the caller that is to give a phony
1111: value for the incoming operand (same as outgoing one). */
1112: if (reload_reg_rtx[i] == out
1113: && (GET_CODE (in) == REG || CONSTANT_P (in))
1114: && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out),
1115: static_reload_reg_p, i, inmode))
1116: reload_in[i] = out;
1117: }
1118:
1119: /* If this is an input reload and the operand contains a register that
1120: dies in this insn and is used nowhere else, see if it is the right class
1121: to be used for this reload. Use it if so. (This occurs most commonly
1122: in the case of paradoxical SUBREGs and in-out reloads). We cannot do
1123: this if it is also an output reload that mentions the register unless
1124: the output is a SUBREG that clobbers an entire register.
1125:
1126: Note that the operand might be one of the spill regs, if it is a
1127: pseudo reg and we are in a block where spilling has not taken place.
1128: But if there is no spilling in this block, that is OK.
1129: An explicitly used hard reg cannot be a spill reg. */
1130:
1131: if (reload_reg_rtx[i] == 0 && in != 0)
1132: {
1133: rtx note;
1134: int regno;
1135:
1136: for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
1137: if (REG_NOTE_KIND (note) == REG_DEAD
1138: && GET_CODE (XEXP (note, 0)) == REG
1139: && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER
1140: && reg_mentioned_p (XEXP (note, 0), in)
1141: && ! refers_to_regno_for_reload_p (regno,
1142: (regno
1143: + HARD_REGNO_NREGS (regno,
1144: inmode)),
1145: PATTERN (this_insn), inloc)
1146: && (in != out
1147: || (GET_CODE (in) == SUBREG
1148: && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1))
1149: / UNITS_PER_WORD)
1150: == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
1151: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
1152: /* Make sure the operand fits in the reg that dies. */
1153: && GET_MODE_SIZE (inmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
1154: && HARD_REGNO_MODE_OK (regno, inmode)
1155: && GET_MODE_SIZE (outmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
1156: && HARD_REGNO_MODE_OK (regno, outmode)
1157: && TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
1158: && !fixed_regs[regno])
1159: {
1160: reload_reg_rtx[i] = gen_rtx (REG, inmode, regno);
1161: break;
1162: }
1163: }
1164:
1165: if (out)
1166: output_reloadnum = i;
1167:
1168: return i;
1169: }
1170:
1171: /* Record an additional place we must replace a value
1172: for which we have already recorded a reload.
1173: RELOADNUM is the value returned by push_reload
1174: when the reload was recorded.
1175: This is used in insn patterns that use match_dup. */
1176:
1177: static void
1178: push_replacement (loc, reloadnum, mode)
1179: rtx *loc;
1180: int reloadnum;
1181: enum machine_mode mode;
1182: {
1183: if (replace_reloads)
1184: {
1185: register struct replacement *r = &replacements[n_replacements++];
1186: r->what = reloadnum;
1187: r->where = loc;
1188: r->subreg_loc = 0;
1189: r->mode = mode;
1190: }
1191: }
1192:
1193: /* If there is only one output reload, and it is not for an earlyclobber
1194: operand, try to combine it with a (logically unrelated) input reload
1195: to reduce the number of reload registers needed.
1196:
1197: This is safe if the input reload does not appear in
1198: the value being output-reloaded, because this implies
1199: it is not needed any more once the original insn completes.
1200:
1201: If that doesn't work, see we can use any of the registers that
1202: die in this insn as a reload register. We can if it is of the right
1203: class and does not appear in the value being output-reloaded. */
1204:
1205: static void
1206: combine_reloads ()
1207: {
1208: int i;
1209: int output_reload = -1;
1210: rtx note;
1211:
1212: /* Find the output reload; return unless there is exactly one
1213: and that one is mandatory. */
1214:
1215: for (i = 0; i < n_reloads; i++)
1216: if (reload_out[i] != 0)
1217: {
1218: if (output_reload >= 0)
1219: return;
1220: output_reload = i;
1221: }
1222:
1223: if (output_reload < 0 || reload_optional[output_reload])
1224: return;
1225:
1226: /* An input-output reload isn't combinable. */
1227:
1228: if (reload_in[output_reload] != 0)
1229: return;
1230:
1.1.1.3 root 1231: /* If this reload is for an earlyclobber operand, we can't do anything. */
1.1 root 1232:
1233: for (i = 0; i < n_earlyclobbers; i++)
1234: if (reload_out[output_reload] == reload_earlyclobbers[i])
1235: return;
1236:
1237: /* Check each input reload; can we combine it? */
1238:
1239: for (i = 0; i < n_reloads; i++)
1240: if (reload_in[i] && ! reload_optional[i] && ! reload_nocombine[i]
1241: /* Life span of this reload must not extend past main insn. */
1242: && reload_when_needed[i] != RELOAD_FOR_OUTPUT_RELOAD_ADDRESS
1.1.1.4 ! root 1243: && ! reload_needed_for_multiple[i]
1.1 root 1244: && reload_inmode[i] == reload_outmode[output_reload]
1245: && reload_inc[i] == 0
1246: && reload_reg_rtx[i] == 0
1247: && reload_strict_low[i] == 0
1248: /* Don't combine two reloads with different secondary reloads. */
1249: && (reload_secondary_reload[i] == reload_secondary_reload[output_reload]
1250: || reload_secondary_reload[i] == -1
1251: || reload_secondary_reload[output_reload] == -1)
1252: && (reg_class_subset_p (reload_reg_class[i],
1253: reload_reg_class[output_reload])
1254: || reg_class_subset_p (reload_reg_class[output_reload],
1255: reload_reg_class[i]))
1256: && (MATCHES (reload_in[i], reload_out[output_reload])
1257: /* Args reversed because the first arg seems to be
1258: the one that we imagine being modified
1259: while the second is the one that might be affected. */
1.1.1.3 root 1260: || (! reg_overlap_mentioned_for_reload_p (reload_out[output_reload],
1261: reload_in[i])
1.1 root 1262: /* However, if the input is a register that appears inside
1263: the output, then we also can't share.
1264: Imagine (set (mem (reg 69)) (plus (reg 69) ...)).
1265: If the same reload reg is used for both reg 69 and the
1266: result to be stored in memory, then that result
1267: will clobber the address of the memory ref. */
1268: && ! (GET_CODE (reload_in[i]) == REG
1.1.1.3 root 1269: && reg_overlap_mentioned_for_reload_p (reload_in[i],
1270: reload_out[output_reload])))))
1.1 root 1271: {
1272: int j;
1273:
1274: /* We have found a reload to combine with! */
1275: reload_out[i] = reload_out[output_reload];
1276: reload_outmode[i] = reload_outmode[output_reload];
1277: /* Mark the old output reload as inoperative. */
1278: reload_out[output_reload] = 0;
1279: /* The combined reload is needed for the entire insn. */
1280: reload_needed_for_multiple[i] = 1;
1281: reload_when_needed[i] = RELOAD_OTHER;
1282: /* If the output reload had a secondary reload, copy it. */
1283: if (reload_secondary_reload[output_reload] != -1)
1284: reload_secondary_reload[i] = reload_secondary_reload[output_reload];
1285: /* If required, minimize the register class. */
1286: if (reg_class_subset_p (reload_reg_class[output_reload],
1287: reload_reg_class[i]))
1288: reload_reg_class[i] = reload_reg_class[output_reload];
1289:
1290: /* Transfer all replacements from the old reload to the combined. */
1291: for (j = 0; j < n_replacements; j++)
1292: if (replacements[j].what == output_reload)
1293: replacements[j].what = i;
1294:
1295: return;
1296: }
1297:
1298: /* If this insn has only one operand that is modified or written (assumed
1299: to be the first), it must be the one corresponding to this reload. It
1300: is safe to use anything that dies in this insn for that output provided
1301: that it does not occur in the output (we already know it isn't an
1302: earlyclobber. If this is an asm insn, give up. */
1303:
1304: if (INSN_CODE (this_insn) == -1)
1305: return;
1306:
1307: for (i = 1; i < insn_n_operands[INSN_CODE (this_insn)]; i++)
1308: if (insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '='
1309: || insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '+')
1310: return;
1311:
1312: /* See if some hard register that dies in this insn and is not used in
1313: the output is the right class. Only works if the register we pick
1314: up can fully hold our output reload. */
1315: for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
1316: if (REG_NOTE_KIND (note) == REG_DEAD
1317: && GET_CODE (XEXP (note, 0)) == REG
1.1.1.3 root 1318: && ! reg_overlap_mentioned_for_reload_p (XEXP (note, 0),
1319: reload_out[output_reload])
1.1 root 1320: && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
1321: && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), reload_outmode[output_reload])
1322: && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[output_reload]],
1323: REGNO (XEXP (note, 0)))
1324: && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), reload_outmode[output_reload])
1325: <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0))))
1326: && ! fixed_regs[REGNO (XEXP (note, 0))])
1327: {
1328: reload_reg_rtx[output_reload] = gen_rtx (REG,
1329: reload_outmode[output_reload],
1330: REGNO (XEXP (note, 0)));
1331: return;
1332: }
1333: }
1334:
1335: /* Try to find a reload register for an in-out reload (expressions IN and OUT).
1336: See if one of IN and OUT is a register that may be used;
1337: this is desirable since a spill-register won't be needed.
1338: If so, return the register rtx that proves acceptable.
1339:
1340: INLOC and OUTLOC are locations where IN and OUT appear in the insn.
1341: CLASS is the register class required for the reload.
1342:
1343: If FOR_REAL is >= 0, it is the number of the reload,
1344: and in some cases when it can be discovered that OUT doesn't need
1345: to be computed, clear out reload_out[FOR_REAL].
1346:
1347: If FOR_REAL is -1, this should not be done, because this call
1348: is just to see if a register can be found, not to find and install it. */
1349:
1350: static rtx
1351: find_dummy_reload (real_in, real_out, inloc, outloc, class, for_real)
1352: rtx real_in, real_out;
1353: rtx *inloc, *outloc;
1354: enum reg_class class;
1355: int for_real;
1356: {
1357: rtx in = real_in;
1358: rtx out = real_out;
1359: int in_offset = 0;
1360: int out_offset = 0;
1361: rtx value = 0;
1362:
1363: /* If operands exceed a word, we can't use either of them
1364: unless they have the same size. */
1365: if (GET_MODE_SIZE (GET_MODE (real_out)) != GET_MODE_SIZE (GET_MODE (real_in))
1366: && (GET_MODE_SIZE (GET_MODE (real_out)) > UNITS_PER_WORD
1367: || GET_MODE_SIZE (GET_MODE (real_in)) > UNITS_PER_WORD))
1368: return 0;
1369:
1370: /* Find the inside of any subregs. */
1371: while (GET_CODE (out) == SUBREG)
1372: {
1373: out_offset = SUBREG_WORD (out);
1374: out = SUBREG_REG (out);
1375: }
1376: while (GET_CODE (in) == SUBREG)
1377: {
1378: in_offset = SUBREG_WORD (in);
1379: in = SUBREG_REG (in);
1380: }
1381:
1382: /* Narrow down the reg class, the same way push_reload will;
1383: otherwise we might find a dummy now, but push_reload won't. */
1384: class = PREFERRED_RELOAD_CLASS (in, class);
1385:
1386: /* See if OUT will do. */
1387: if (GET_CODE (out) == REG
1388: && REGNO (out) < FIRST_PSEUDO_REGISTER)
1389: {
1390: register int regno = REGNO (out) + out_offset;
1391: int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_out));
1.1.1.4 ! root 1392: rtx saved_rtx;
1.1 root 1393:
1394: /* When we consider whether the insn uses OUT,
1395: ignore references within IN. They don't prevent us
1396: from copying IN into OUT, because those refs would
1397: move into the insn that reloads IN.
1398:
1399: However, we only ignore IN in its role as this reload.
1400: If the insn uses IN elsewhere and it contains OUT,
1401: that counts. We can't be sure it's the "same" operand
1402: so it might not go through this reload. */
1.1.1.4 ! root 1403: saved_rtx = *inloc;
1.1 root 1404: *inloc = const0_rtx;
1405:
1406: if (regno < FIRST_PSEUDO_REGISTER
1407: /* A fixed reg that can overlap other regs better not be used
1408: for reloading in any way. */
1409: #ifdef OVERLAPPING_REGNO_P
1410: && ! (fixed_regs[regno] && OVERLAPPING_REGNO_P (regno))
1411: #endif
1412: && ! refers_to_regno_for_reload_p (regno, regno + nwords,
1413: PATTERN (this_insn), outloc))
1414: {
1415: int i;
1416: for (i = 0; i < nwords; i++)
1417: if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1418: regno + i))
1419: break;
1420:
1421: if (i == nwords)
1422: {
1423: if (GET_CODE (real_out) == REG)
1424: value = real_out;
1425: else
1426: value = gen_rtx (REG, GET_MODE (real_out), regno);
1427: }
1428: }
1429:
1.1.1.4 ! root 1430: *inloc = saved_rtx;
1.1 root 1431: }
1432:
1433: /* Consider using IN if OUT was not acceptable
1434: or if OUT dies in this insn (like the quotient in a divmod insn).
1435: We can't use IN unless it is dies in this insn,
1436: which means we must know accurately which hard regs are live.
1437: Also, the result can't go in IN if IN is used within OUT. */
1438: if (hard_regs_live_known
1439: && GET_CODE (in) == REG
1440: && REGNO (in) < FIRST_PSEUDO_REGISTER
1441: && (value == 0
1442: || find_reg_note (this_insn, REG_UNUSED, real_out))
1443: && find_reg_note (this_insn, REG_DEAD, real_in)
1444: && !fixed_regs[REGNO (in)]
1445: && HARD_REGNO_MODE_OK (REGNO (in), GET_MODE (out)))
1446: {
1447: register int regno = REGNO (in) + in_offset;
1448: int nwords = HARD_REGNO_NREGS (regno, GET_MODE (real_in));
1449:
1.1.1.4 ! root 1450: if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, NULL_PTR)
1.1 root 1451: && ! hard_reg_set_here_p (regno, regno + nwords,
1452: PATTERN (this_insn)))
1453: {
1454: int i;
1455: for (i = 0; i < nwords; i++)
1456: if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1457: regno + i))
1458: break;
1459:
1460: if (i == nwords)
1461: {
1462: /* If we were going to use OUT as the reload reg
1463: and changed our mind, it means OUT is a dummy that
1464: dies here. So don't bother copying value to it. */
1465: if (for_real >= 0 && value == real_out)
1466: reload_out[for_real] = 0;
1467: if (GET_CODE (real_in) == REG)
1468: value = real_in;
1469: else
1470: value = gen_rtx (REG, GET_MODE (real_in), regno);
1471: }
1472: }
1473: }
1474:
1475: return value;
1476: }
1477:
1478: /* This page contains subroutines used mainly for determining
1479: whether the IN or an OUT of a reload can serve as the
1480: reload register. */
1481:
1482: /* Return 1 if expression X alters a hard reg in the range
1483: from BEG_REGNO (inclusive) to END_REGNO (exclusive),
1484: either explicitly or in the guise of a pseudo-reg allocated to REGNO.
1485: X should be the body of an instruction. */
1486:
1487: static int
1488: hard_reg_set_here_p (beg_regno, end_regno, x)
1489: register int beg_regno, end_regno;
1490: rtx x;
1491: {
1492: if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
1493: {
1494: register rtx op0 = SET_DEST (x);
1495: while (GET_CODE (op0) == SUBREG)
1496: op0 = SUBREG_REG (op0);
1497: if (GET_CODE (op0) == REG)
1498: {
1499: register int r = REGNO (op0);
1500: /* See if this reg overlaps range under consideration. */
1501: if (r < end_regno
1502: && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno)
1503: return 1;
1504: }
1505: }
1506: else if (GET_CODE (x) == PARALLEL)
1507: {
1508: register int i = XVECLEN (x, 0) - 1;
1509: for (; i >= 0; i--)
1510: if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i)))
1511: return 1;
1512: }
1513:
1514: return 0;
1515: }
1516:
1517: /* Return 1 if ADDR is a valid memory address for mode MODE,
1518: and check that each pseudo reg has the proper kind of
1519: hard reg. */
1520:
1521: int
1522: strict_memory_address_p (mode, addr)
1523: enum machine_mode mode;
1524: register rtx addr;
1525: {
1526: GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1527: return 0;
1528:
1529: win:
1530: return 1;
1531: }
1532:
1533:
1534: /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
1535: if they are the same hard reg, and has special hacks for
1536: autoincrement and autodecrement.
1537: This is specifically intended for find_reloads to use
1538: in determining whether two operands match.
1539: X is the operand whose number is the lower of the two.
1540:
1541: The value is 2 if Y contains a pre-increment that matches
1542: a non-incrementing address in X. */
1543:
1544: /* ??? To be completely correct, we should arrange to pass
1545: for X the output operand and for Y the input operand.
1546: For now, we assume that the output operand has the lower number
1547: because that is natural in (SET output (... input ...)). */
1548:
1549: int
1550: operands_match_p (x, y)
1551: register rtx x, y;
1552: {
1553: register int i;
1554: register RTX_CODE code = GET_CODE (x);
1555: register char *fmt;
1556: int success_2;
1557:
1558: if (x == y)
1559: return 1;
1560: if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG))
1561: && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG
1562: && GET_CODE (SUBREG_REG (y)) == REG)))
1563: {
1564: register int j;
1565:
1566: if (code == SUBREG)
1567: {
1568: i = REGNO (SUBREG_REG (x));
1569: if (i >= FIRST_PSEUDO_REGISTER)
1570: goto slow;
1571: i += SUBREG_WORD (x);
1572: }
1573: else
1574: i = REGNO (x);
1575:
1576: if (GET_CODE (y) == SUBREG)
1577: {
1578: j = REGNO (SUBREG_REG (y));
1579: if (j >= FIRST_PSEUDO_REGISTER)
1580: goto slow;
1581: j += SUBREG_WORD (y);
1582: }
1583: else
1584: j = REGNO (y);
1585:
1586: return i == j;
1587: }
1588: /* If two operands must match, because they are really a single
1589: operand of an assembler insn, then two postincrements are invalid
1590: because the assembler insn would increment only once.
1591: On the other hand, an postincrement matches ordinary indexing
1592: if the postincrement is the output operand. */
1593: if (code == POST_DEC || code == POST_INC)
1594: return operands_match_p (XEXP (x, 0), y);
1595: /* Two preincrements are invalid
1596: because the assembler insn would increment only once.
1597: On the other hand, an preincrement matches ordinary indexing
1598: if the preincrement is the input operand.
1599: In this case, return 2, since some callers need to do special
1600: things when this happens. */
1601: if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC)
1602: return operands_match_p (x, XEXP (y, 0)) ? 2 : 0;
1603:
1604: slow:
1605:
1606: /* Now we have disposed of all the cases
1607: in which different rtx codes can match. */
1608: if (code != GET_CODE (y))
1609: return 0;
1610: if (code == LABEL_REF)
1611: return XEXP (x, 0) == XEXP (y, 0);
1612: if (code == SYMBOL_REF)
1613: return XSTR (x, 0) == XSTR (y, 0);
1614:
1615: /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
1616:
1617: if (GET_MODE (x) != GET_MODE (y))
1618: return 0;
1619:
1620: /* Compare the elements. If any pair of corresponding elements
1621: fail to match, return 0 for the whole things. */
1622:
1623: success_2 = 0;
1624: fmt = GET_RTX_FORMAT (code);
1625: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1626: {
1627: int val;
1628: switch (fmt[i])
1629: {
1.1.1.4 ! root 1630: case 'w':
! 1631: if (XWINT (x, i) != XWINT (y, i))
! 1632: return 0;
! 1633: break;
! 1634:
1.1 root 1635: case 'i':
1636: if (XINT (x, i) != XINT (y, i))
1637: return 0;
1638: break;
1639:
1640: case 'e':
1641: val = operands_match_p (XEXP (x, i), XEXP (y, i));
1642: if (val == 0)
1643: return 0;
1644: /* If any subexpression returns 2,
1645: we should return 2 if we are successful. */
1646: if (val == 2)
1647: success_2 = 1;
1648: break;
1649:
1650: case '0':
1651: break;
1652:
1653: /* It is believed that rtx's at this level will never
1654: contain anything but integers and other rtx's,
1655: except for within LABEL_REFs and SYMBOL_REFs. */
1656: default:
1657: abort ();
1658: }
1659: }
1660: return 1 + success_2;
1661: }
1662:
1663: /* Return the number of times character C occurs in string S. */
1664:
1.1.1.4 ! root 1665: int
1.1 root 1666: n_occurrences (c, s)
1667: char c;
1668: char *s;
1669: {
1670: int n = 0;
1671: while (*s)
1672: n += (*s++ == c);
1673: return n;
1674: }
1675:
1676: struct decomposition
1677: {
1678: int reg_flag;
1679: int safe;
1680: rtx base;
1.1.1.4 ! root 1681: HOST_WIDE_INT start;
! 1682: HOST_WIDE_INT end;
1.1 root 1683: };
1684:
1685: /* Describe the range of registers or memory referenced by X.
1686: If X is a register, set REG_FLAG and put the first register
1687: number into START and the last plus one into END.
1688: If X is a memory reference, put a base address into BASE
1689: and a range of integer offsets into START and END.
1690: If X is pushing on the stack, we can assume it causes no trouble,
1691: so we set the SAFE field. */
1692:
1693: static struct decomposition
1694: decompose (x)
1695: rtx x;
1696: {
1697: struct decomposition val;
1698: int all_const = 0;
1699:
1700: val.reg_flag = 0;
1701: val.safe = 0;
1702: if (GET_CODE (x) == MEM)
1703: {
1704: rtx base, offset = 0;
1705: rtx addr = XEXP (x, 0);
1706:
1707: if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC
1708: || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC)
1709: {
1710: val.base = XEXP (addr, 0);
1711: val.start = - GET_MODE_SIZE (GET_MODE (x));
1712: val.end = GET_MODE_SIZE (GET_MODE (x));
1713: val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
1714: return val;
1715: }
1716:
1717: if (GET_CODE (addr) == CONST)
1718: {
1719: addr = XEXP (addr, 0);
1720: all_const = 1;
1721: }
1722: if (GET_CODE (addr) == PLUS)
1723: {
1724: if (CONSTANT_P (XEXP (addr, 0)))
1725: {
1726: base = XEXP (addr, 1);
1727: offset = XEXP (addr, 0);
1728: }
1729: else if (CONSTANT_P (XEXP (addr, 1)))
1730: {
1731: base = XEXP (addr, 0);
1732: offset = XEXP (addr, 1);
1733: }
1734: }
1735:
1736: if (offset == 0)
1737: {
1738: base = addr;
1739: offset = const0_rtx;
1740: }
1741: if (GET_CODE (offset) == CONST)
1742: offset = XEXP (offset, 0);
1743: if (GET_CODE (offset) == PLUS)
1744: {
1745: if (GET_CODE (XEXP (offset, 0)) == CONST_INT)
1746: {
1747: base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 1));
1748: offset = XEXP (offset, 0);
1749: }
1750: else if (GET_CODE (XEXP (offset, 1)) == CONST_INT)
1751: {
1752: base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 0));
1753: offset = XEXP (offset, 1);
1754: }
1755: else
1756: {
1757: base = gen_rtx (PLUS, GET_MODE (base), base, offset);
1758: offset = const0_rtx;
1759: }
1760: }
1761: else if (GET_CODE (offset) != CONST_INT)
1762: {
1763: base = gen_rtx (PLUS, GET_MODE (base), base, offset);
1764: offset = const0_rtx;
1765: }
1766:
1767: if (all_const && GET_CODE (base) == PLUS)
1768: base = gen_rtx (CONST, GET_MODE (base), base);
1769:
1770: if (GET_CODE (offset) != CONST_INT)
1771: abort ();
1772:
1773: val.start = INTVAL (offset);
1774: val.end = val.start + GET_MODE_SIZE (GET_MODE (x));
1775: val.base = base;
1776: return val;
1777: }
1778: else if (GET_CODE (x) == REG)
1779: {
1780: val.reg_flag = 1;
1781: val.start = true_regnum (x);
1782: if (val.start < 0)
1783: {
1784: /* A pseudo with no hard reg. */
1785: val.start = REGNO (x);
1786: val.end = val.start + 1;
1787: }
1788: else
1789: /* A hard reg. */
1790: val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x));
1791: }
1792: else if (GET_CODE (x) == SUBREG)
1793: {
1794: if (GET_CODE (SUBREG_REG (x)) != REG)
1795: /* This could be more precise, but it's good enough. */
1796: return decompose (SUBREG_REG (x));
1797: val.reg_flag = 1;
1798: val.start = true_regnum (x);
1799: if (val.start < 0)
1800: return decompose (SUBREG_REG (x));
1801: else
1802: /* A hard reg. */
1803: val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x));
1804: }
1805: else if (CONSTANT_P (x)
1806: /* This hasn't been assigned yet, so it can't conflict yet. */
1807: || GET_CODE (x) == SCRATCH)
1808: val.safe = 1;
1809: else
1810: abort ();
1811: return val;
1812: }
1813:
1814: /* Return 1 if altering Y will not modify the value of X.
1815: Y is also described by YDATA, which should be decompose (Y). */
1816:
1817: static int
1818: immune_p (x, y, ydata)
1819: rtx x, y;
1820: struct decomposition ydata;
1821: {
1822: struct decomposition xdata;
1823:
1824: if (ydata.reg_flag)
1.1.1.4 ! root 1825: return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, NULL_PTR);
1.1 root 1826: if (ydata.safe)
1827: return 1;
1828:
1829: if (GET_CODE (y) != MEM)
1830: abort ();
1831: /* If Y is memory and X is not, Y can't affect X. */
1832: if (GET_CODE (x) != MEM)
1833: return 1;
1834:
1835: xdata = decompose (x);
1836:
1837: if (! rtx_equal_p (xdata.base, ydata.base))
1838: {
1839: /* If bases are distinct symbolic constants, there is no overlap. */
1840: if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base))
1841: return 1;
1842: /* Constants and stack slots never overlap. */
1843: if (CONSTANT_P (xdata.base)
1844: && (ydata.base == frame_pointer_rtx
1845: || ydata.base == stack_pointer_rtx))
1846: return 1;
1847: if (CONSTANT_P (ydata.base)
1848: && (xdata.base == frame_pointer_rtx
1849: || xdata.base == stack_pointer_rtx))
1850: return 1;
1851: /* If either base is variable, we don't know anything. */
1852: return 0;
1853: }
1854:
1855:
1856: return (xdata.start >= ydata.end || ydata.start >= xdata.end);
1857: }
1.1.1.3 root 1858:
1.1.1.4 ! root 1859: /* Similar, but calls decompose. */
1.1.1.3 root 1860:
1861: int
1862: safe_from_earlyclobber (op, clobber)
1863: rtx op, clobber;
1864: {
1865: struct decomposition early_data;
1866:
1867: early_data = decompose (clobber);
1868: return immune_p (op, clobber, early_data);
1869: }
1.1 root 1870:
1871: /* Main entry point of this file: search the body of INSN
1872: for values that need reloading and record them with push_reload.
1873: REPLACE nonzero means record also where the values occur
1874: so that subst_reloads can be used.
1875:
1876: IND_LEVELS says how many levels of indirection are supported by this
1877: machine; a value of zero means that a memory reference is not a valid
1878: memory address.
1879:
1880: LIVE_KNOWN says we have valid information about which hard
1881: regs are live at each point in the program; this is true when
1882: we are called from global_alloc but false when stupid register
1883: allocation has been done.
1884:
1885: RELOAD_REG_P if nonzero is a vector indexed by hard reg number
1886: which is nonnegative if the reg has been commandeered for reloading into.
1887: It is copied into STATIC_RELOAD_REG_P and referenced from there
1888: by various subroutines. */
1889:
1890: void
1891: find_reloads (insn, replace, ind_levels, live_known, reload_reg_p)
1892: rtx insn;
1893: int replace, ind_levels;
1894: int live_known;
1895: short *reload_reg_p;
1896: {
1897: rtx non_reloaded_operands[MAX_RECOG_OPERANDS];
1898: int n_non_reloaded_operands = 0;
1899: #ifdef REGISTER_CONSTRAINTS
1900:
1901: enum reload_modified { RELOAD_NOTHING, RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE };
1902:
1903: register int insn_code_number;
1904: register int i;
1905: int noperands;
1906: /* These are the constraints for the insn. We don't change them. */
1907: char *constraints1[MAX_RECOG_OPERANDS];
1908: /* These start out as the constraints for the insn
1909: and they are chewed up as we consider alternatives. */
1910: char *constraints[MAX_RECOG_OPERANDS];
1911: /* These are the preferred classes for an operand, or NO_REGS if it isn't
1912: a register. */
1913: enum reg_class preferred_class[MAX_RECOG_OPERANDS];
1914: char pref_or_nothing[MAX_RECOG_OPERANDS];
1915: /* Nonzero for a MEM operand whose entire address needs a reload. */
1916: int address_reloaded[MAX_RECOG_OPERANDS];
1917: int no_input_reloads = 0, no_output_reloads = 0;
1918: int n_alternatives;
1919: int this_alternative[MAX_RECOG_OPERANDS];
1920: char this_alternative_win[MAX_RECOG_OPERANDS];
1921: char this_alternative_offmemok[MAX_RECOG_OPERANDS];
1922: char this_alternative_earlyclobber[MAX_RECOG_OPERANDS];
1923: int this_alternative_matches[MAX_RECOG_OPERANDS];
1924: int swapped;
1925: int goal_alternative[MAX_RECOG_OPERANDS];
1926: int this_alternative_number;
1927: int goal_alternative_number;
1928: int operand_reloadnum[MAX_RECOG_OPERANDS];
1929: int goal_alternative_matches[MAX_RECOG_OPERANDS];
1930: int goal_alternative_matched[MAX_RECOG_OPERANDS];
1931: char goal_alternative_win[MAX_RECOG_OPERANDS];
1932: char goal_alternative_offmemok[MAX_RECOG_OPERANDS];
1933: char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS];
1934: int goal_alternative_swapped;
1935: enum reload_modified modified[MAX_RECOG_OPERANDS];
1936: int best;
1937: int commutative;
1938: char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
1939: rtx substed_operand[MAX_RECOG_OPERANDS];
1940: rtx body = PATTERN (insn);
1941: rtx set = single_set (insn);
1942: int goal_earlyclobber, this_earlyclobber;
1943: enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1944:
1945: this_insn = insn;
1946: this_insn_is_asm = 0; /* Tentative. */
1947: n_reloads = 0;
1948: n_replacements = 0;
1949: n_memlocs = 0;
1950: n_earlyclobbers = 0;
1951: replace_reloads = replace;
1952: hard_regs_live_known = live_known;
1953: static_reload_reg_p = reload_reg_p;
1954:
1955: /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads;
1956: neither are insns that SET cc0. Insns that use CC0 are not allowed
1957: to have any input reloads. */
1958: if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN)
1959: no_output_reloads = 1;
1960:
1961: #ifdef HAVE_cc0
1962: if (reg_referenced_p (cc0_rtx, PATTERN (insn)))
1963: no_input_reloads = 1;
1964: if (reg_set_p (cc0_rtx, PATTERN (insn)))
1965: no_output_reloads = 1;
1966: #endif
1967:
1.1.1.4 ! root 1968: #ifdef SECONDARY_MEMORY_NEEDED
! 1969: /* The eliminated forms of any secondary memory locations are per-insn, so
! 1970: clear them out here. */
! 1971:
! 1972: bzero (secondary_memlocs_elim, sizeof secondary_memlocs_elim);
! 1973: #endif
! 1974:
1.1 root 1975: /* Find what kind of insn this is. NOPERANDS gets number of operands.
1976: Make OPERANDS point to a vector of operand values.
1977: Make OPERAND_LOCS point to a vector of pointers to
1978: where the operands were found.
1979: Fill CONSTRAINTS and CONSTRAINTS1 with pointers to the
1980: constraint-strings for this insn.
1981: Return if the insn needs no reload processing. */
1982:
1983: switch (GET_CODE (body))
1984: {
1985: case USE:
1986: case CLOBBER:
1987: case ASM_INPUT:
1988: case ADDR_VEC:
1989: case ADDR_DIFF_VEC:
1990: return;
1991:
1992: case SET:
1993: /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it
1994: is cheap to move between them. If it is not, there may not be an insn
1995: to do the copy, so we may need a reload. */
1996: if (GET_CODE (SET_DEST (body)) == REG
1997: && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER
1998: && GET_CODE (SET_SRC (body)) == REG
1999: && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER
2000: && REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (SET_SRC (body))),
2001: REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2)
2002: return;
2003: case PARALLEL:
2004: case ASM_OPERANDS:
2005: noperands = asm_noperands (body);
2006: if (noperands >= 0)
2007: {
2008: /* This insn is an `asm' with operands. */
2009:
2010: insn_code_number = -1;
2011: this_insn_is_asm = 1;
2012:
2013: /* expand_asm_operands makes sure there aren't too many operands. */
2014: if (noperands > MAX_RECOG_OPERANDS)
2015: abort ();
2016:
2017: /* Now get the operand values and constraints out of the insn. */
2018:
2019: decode_asm_operands (body, recog_operand, recog_operand_loc,
2020: constraints, operand_mode);
2021: if (noperands > 0)
2022: {
2023: bcopy (constraints, constraints1, noperands * sizeof (char *));
2024: n_alternatives = n_occurrences (',', constraints[0]) + 1;
2025: for (i = 1; i < noperands; i++)
1.1.1.2 root 2026: if (n_alternatives != n_occurrences (',', constraints[i]) + 1)
1.1 root 2027: {
2028: error_for_asm (insn, "operand constraints differ in number of alternatives");
2029: /* Avoid further trouble with this insn. */
2030: PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
2031: n_reloads = 0;
2032: return;
2033: }
2034: }
2035: break;
2036: }
2037:
2038: default:
2039: /* Ordinary insn: recognize it, get the operands via insn_extract
2040: and get the constraints. */
2041:
2042: insn_code_number = recog_memoized (insn);
2043: if (insn_code_number < 0)
2044: fatal_insn_not_found (insn);
2045:
2046: noperands = insn_n_operands[insn_code_number];
2047: n_alternatives = insn_n_alternatives[insn_code_number];
2048: /* Just return "no reloads" if insn has no operands with constraints. */
2049: if (n_alternatives == 0)
2050: return;
2051: insn_extract (insn);
2052: for (i = 0; i < noperands; i++)
2053: {
2054: constraints[i] = constraints1[i]
2055: = insn_operand_constraint[insn_code_number][i];
2056: operand_mode[i] = insn_operand_mode[insn_code_number][i];
2057: }
2058: }
2059:
2060: if (noperands == 0)
2061: return;
2062:
2063: commutative = -1;
2064:
2065: /* If we will need to know, later, whether some pair of operands
2066: are the same, we must compare them now and save the result.
2067: Reloading the base and index registers will clobber them
2068: and afterward they will fail to match. */
2069:
2070: for (i = 0; i < noperands; i++)
2071: {
2072: register char *p;
2073: register int c;
2074:
2075: substed_operand[i] = recog_operand[i];
2076: p = constraints[i];
2077:
2078: /* Scan this operand's constraint to see if it should match another. */
2079:
2080: while (c = *p++)
2081: if (c == '%')
2082: {
1.1.1.3 root 2083: /* The last operand should not be marked commutative. */
1.1 root 2084: if (i == noperands - 1)
1.1.1.3 root 2085: {
2086: if (this_insn_is_asm)
2087: warning_for_asm (this_insn,
2088: "`%%' constraint used with last operand");
2089: else
2090: abort ();
2091: }
2092: else
2093: commutative = i;
1.1 root 2094: }
2095: else if (c >= '0' && c <= '9')
2096: {
2097: c -= '0';
2098: operands_match[c][i]
2099: = operands_match_p (recog_operand[c], recog_operand[i]);
1.1.1.4 ! root 2100:
! 2101: /* An operand may not match itself. */
! 2102: if (c == i)
! 2103: {
! 2104: if (this_insn_is_asm)
! 2105: warning_for_asm (this_insn,
! 2106: "operand %d has constraint %d", i, c);
! 2107: else
! 2108: abort ();
! 2109: }
! 2110:
1.1 root 2111: /* If C can be commuted with C+1, and C might need to match I,
2112: then C+1 might also need to match I. */
2113: if (commutative >= 0)
2114: {
2115: if (c == commutative || c == commutative + 1)
2116: {
2117: int other = c + (c == commutative ? 1 : -1);
2118: operands_match[other][i]
2119: = operands_match_p (recog_operand[other], recog_operand[i]);
2120: }
2121: if (i == commutative || i == commutative + 1)
2122: {
2123: int other = i + (i == commutative ? 1 : -1);
2124: operands_match[c][other]
2125: = operands_match_p (recog_operand[c], recog_operand[other]);
2126: }
2127: /* Note that C is supposed to be less than I.
2128: No need to consider altering both C and I
2129: because in that case we would alter one into the other. */
2130: }
2131: }
2132: }
2133:
2134: /* Examine each operand that is a memory reference or memory address
2135: and reload parts of the addresses into index registers.
2136: While we are at it, initialize the array `modified'.
2137: Also here any references to pseudo regs that didn't get hard regs
2138: but are equivalent to constants get replaced in the insn itself
2139: with those constants. Nobody will ever see them again.
2140:
2141: Finally, set up the preferred classes of each operand. */
2142:
2143: for (i = 0; i < noperands; i++)
2144: {
2145: register RTX_CODE code = GET_CODE (recog_operand[i]);
2146: modified[i] = RELOAD_READ;
2147: address_reloaded[i] = 0;
2148:
2149: if (constraints[i][0] == 'p')
2150: {
1.1.1.4 ! root 2151: find_reloads_address (VOIDmode, NULL_PTR,
1.1 root 2152: recog_operand[i], recog_operand_loc[i],
2153: recog_operand[i], ind_levels);
2154: substed_operand[i] = recog_operand[i] = *recog_operand_loc[i];
2155: }
2156: else if (code == MEM)
2157: {
2158: if (find_reloads_address (GET_MODE (recog_operand[i]),
2159: recog_operand_loc[i],
2160: XEXP (recog_operand[i], 0),
2161: &XEXP (recog_operand[i], 0),
2162: recog_operand[i], ind_levels))
2163: address_reloaded[i] = 1;
2164: substed_operand[i] = recog_operand[i] = *recog_operand_loc[i];
2165: }
2166: else if (code == SUBREG)
2167: substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]
2168: = find_reloads_toplev (recog_operand[i], ind_levels,
2169: set != 0
2170: && &SET_DEST (set) == recog_operand_loc[i]);
2171: else if (code == REG)
2172: {
2173: /* This is equivalent to calling find_reloads_toplev.
2174: The code is duplicated for speed.
2175: When we find a pseudo always equivalent to a constant,
2176: we replace it by the constant. We must be sure, however,
2177: that we don't try to replace it in the insn in which it
2178: is being set. */
2179: register int regno = REGNO (recog_operand[i]);
2180: if (reg_equiv_constant[regno] != 0
2181: && (set == 0 || &SET_DEST (set) != recog_operand_loc[i]))
2182: substed_operand[i] = recog_operand[i]
2183: = reg_equiv_constant[regno];
2184: #if 0 /* This might screw code in reload1.c to delete prior output-reload
2185: that feeds this insn. */
2186: if (reg_equiv_mem[regno] != 0)
2187: substed_operand[i] = recog_operand[i]
2188: = reg_equiv_mem[regno];
2189: #endif
2190: if (reg_equiv_address[regno] != 0)
2191: {
2192: /* If reg_equiv_address is not a constant address, copy it,
2193: since it may be shared. */
2194: rtx address = reg_equiv_address[regno];
2195:
2196: if (rtx_varies_p (address))
2197: address = copy_rtx (address);
2198:
2199: /* If this is an output operand, we must output a CLOBBER
2200: after INSN so find_equiv_reg knows REGNO is being written. */
2201: if (constraints[i][0] == '='
2202: || constraints[i][0] == '+')
2203: emit_insn_after (gen_rtx (CLOBBER, VOIDmode, recog_operand[i]),
2204: insn);
2205:
2206: *recog_operand_loc[i] = recog_operand[i]
2207: = gen_rtx (MEM, GET_MODE (recog_operand[i]), address);
2208: RTX_UNCHANGING_P (recog_operand[i])
2209: = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
2210: find_reloads_address (GET_MODE (recog_operand[i]),
2211: recog_operand_loc[i],
2212: XEXP (recog_operand[i], 0),
2213: &XEXP (recog_operand[i], 0),
2214: recog_operand[i], ind_levels);
2215: substed_operand[i] = recog_operand[i] = *recog_operand_loc[i];
2216: }
2217: }
1.1.1.3 root 2218: /* If the operand is still a register (we didn't replace it with an
2219: equivalent), get the preferred class to reload it into. */
2220: code = GET_CODE (recog_operand[i]);
2221: preferred_class[i]
1.1.1.4 ! root 2222: = ((code == REG && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
1.1.1.3 root 2223: ? reg_preferred_class (REGNO (recog_operand[i])) : NO_REGS);
2224: pref_or_nothing[i]
1.1.1.4 ! root 2225: = (code == REG && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER
! 2226: && reg_alternate_class (REGNO (recog_operand[i])) == NO_REGS);
1.1 root 2227: }
2228:
2229: /* If this is simply a copy from operand 1 to operand 0, merge the
2230: preferred classes for the operands. */
2231: if (set != 0 && noperands >= 2 && recog_operand[0] == SET_DEST (set)
2232: && recog_operand[1] == SET_SRC (set))
2233: {
2234: preferred_class[0] = preferred_class[1]
2235: = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]];
2236: pref_or_nothing[0] |= pref_or_nothing[1];
2237: pref_or_nothing[1] |= pref_or_nothing[0];
2238: }
2239:
2240: /* Now see what we need for pseudo-regs that didn't get hard regs
2241: or got the wrong kind of hard reg. For this, we must consider
2242: all the operands together against the register constraints. */
2243:
2244: best = MAX_RECOG_OPERANDS + 300;
2245:
2246: swapped = 0;
2247: goal_alternative_swapped = 0;
2248: try_swapped:
2249:
2250: /* The constraints are made of several alternatives.
2251: Each operand's constraint looks like foo,bar,... with commas
2252: separating the alternatives. The first alternatives for all
2253: operands go together, the second alternatives go together, etc.
2254:
2255: First loop over alternatives. */
2256:
2257: for (this_alternative_number = 0;
2258: this_alternative_number < n_alternatives;
2259: this_alternative_number++)
2260: {
2261: /* Loop over operands for one constraint alternative. */
2262: /* LOSERS counts those that don't fit this alternative
2263: and would require loading. */
2264: int losers = 0;
2265: /* BAD is set to 1 if it some operand can't fit this alternative
2266: even after reloading. */
2267: int bad = 0;
2268: /* REJECT is a count of how undesirable this alternative says it is
2269: if any reloading is required. If the alternative matches exactly
2270: then REJECT is ignored, but otherwise it gets this much
2271: counted against it in addition to the reloading needed. Each
2272: ? counts three times here since we want the disparaging caused by
2273: a bad register class to only count 1/3 as much. */
2274: int reject = 0;
2275:
2276: this_earlyclobber = 0;
2277:
2278: for (i = 0; i < noperands; i++)
2279: {
2280: register char *p = constraints[i];
2281: register int win = 0;
2282: /* 0 => this operand can be reloaded somehow for this alternative */
2283: int badop = 1;
2284: /* 0 => this operand can be reloaded if the alternative allows regs. */
2285: int winreg = 0;
2286: int c;
2287: register rtx operand = recog_operand[i];
2288: int offset = 0;
2289: /* Nonzero means this is a MEM that must be reloaded into a reg
2290: regardless of what the constraint says. */
2291: int force_reload = 0;
2292: int offmemok = 0;
2293: int earlyclobber = 0;
2294:
2295: /* If the operand is a SUBREG, extract
2296: the REG or MEM (or maybe even a constant) within.
2297: (Constants can occur as a result of reg_equiv_constant.) */
2298:
2299: while (GET_CODE (operand) == SUBREG)
2300: {
2301: offset += SUBREG_WORD (operand);
2302: operand = SUBREG_REG (operand);
2303: /* Force reload if this is not a register or if there may may
2304: be a problem accessing the register in the outer mode. */
2305: if (GET_CODE (operand) != REG
1.1.1.4 ! root 2306: #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
! 2307: /* ??? The comment below clearly does not match the code.
! 2308: What the code below actually does is set force_reload
! 2309: for a paradoxical subreg of a pseudo. rms and kenner
! 2310: can't see the point of doing this. */
1.1 root 2311: /* Nonparadoxical subreg of a pseudoreg.
2312: Don't to load the full width if on this machine
1.1.1.4 ! root 2313: we expected the fetch to extend. */
1.1 root 2314: || ((GET_MODE_SIZE (operand_mode[i])
2315: > GET_MODE_SIZE (GET_MODE (operand)))
2316: && REGNO (operand) >= FIRST_PSEUDO_REGISTER)
1.1.1.4 ! root 2317: #endif
1.1 root 2318: /* Subreg of a hard reg which can't handle the subreg's mode
2319: or which would handle that mode in the wrong number of
2320: registers for subregging to work. */
2321: || (REGNO (operand) < FIRST_PSEUDO_REGISTER
2322: && (! HARD_REGNO_MODE_OK (REGNO (operand),
2323: operand_mode[i])
2324: || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD
2325: && (GET_MODE_SIZE (GET_MODE (operand))
2326: > UNITS_PER_WORD)
2327: && ((GET_MODE_SIZE (GET_MODE (operand))
2328: / UNITS_PER_WORD)
2329: != HARD_REGNO_NREGS (REGNO (operand),
2330: GET_MODE (operand)))))))
2331: force_reload = 1;
2332: }
2333:
2334: this_alternative[i] = (int) NO_REGS;
2335: this_alternative_win[i] = 0;
2336: this_alternative_offmemok[i] = 0;
2337: this_alternative_earlyclobber[i] = 0;
2338: this_alternative_matches[i] = -1;
2339:
2340: /* An empty constraint or empty alternative
2341: allows anything which matched the pattern. */
2342: if (*p == 0 || *p == ',')
2343: win = 1, badop = 0;
2344:
2345: /* Scan this alternative's specs for this operand;
2346: set WIN if the operand fits any letter in this alternative.
2347: Otherwise, clear BADOP if this operand could
2348: fit some letter after reloads,
2349: or set WINREG if this operand could fit after reloads
2350: provided the constraint allows some registers. */
2351:
2352: while (*p && (c = *p++) != ',')
2353: switch (c)
2354: {
2355: case '=':
2356: modified[i] = RELOAD_WRITE;
2357: break;
2358:
2359: case '+':
2360: modified[i] = RELOAD_READ_WRITE;
2361: break;
2362:
2363: case '*':
2364: break;
2365:
2366: case '%':
1.1.1.4 ! root 2367: /* The last operand should not be marked commutative. */
! 2368: if (i != noperands - 1)
! 2369: commutative = i;
1.1 root 2370: break;
2371:
2372: case '?':
2373: reject += 3;
2374: break;
2375:
2376: case '!':
2377: reject = 300;
2378: break;
2379:
2380: case '#':
2381: /* Ignore rest of this alternative as far as
2382: reloading is concerned. */
2383: while (*p && *p != ',') p++;
2384: break;
2385:
2386: case '0':
2387: case '1':
2388: case '2':
2389: case '3':
2390: case '4':
2391: c -= '0';
2392: this_alternative_matches[i] = c;
2393: /* We are supposed to match a previous operand.
2394: If we do, we win if that one did.
2395: If we do not, count both of the operands as losers.
2396: (This is too conservative, since most of the time
2397: only a single reload insn will be needed to make
2398: the two operands win. As a result, this alternative
2399: may be rejected when it is actually desirable.) */
2400: if ((swapped && (c != commutative || i != commutative + 1))
2401: /* If we are matching as if two operands were swapped,
2402: also pretend that operands_match had been computed
2403: with swapped.
2404: But if I is the second of those and C is the first,
2405: don't exchange them, because operands_match is valid
2406: only on one side of its diagonal. */
2407: ? (operands_match
2408: [(c == commutative || c == commutative + 1)
2409: ? 2*commutative + 1 - c : c]
2410: [(i == commutative || i == commutative + 1)
2411: ? 2*commutative + 1 - i : i])
2412: : operands_match[c][i])
2413: win = this_alternative_win[c];
2414: else
2415: {
2416: /* Operands don't match. */
2417: rtx value;
2418: /* Retroactively mark the operand we had to match
2419: as a loser, if it wasn't already. */
2420: if (this_alternative_win[c])
2421: losers++;
2422: this_alternative_win[c] = 0;
2423: if (this_alternative[c] == (int) NO_REGS)
2424: bad = 1;
2425: /* But count the pair only once in the total badness of
2426: this alternative, if the pair can be a dummy reload. */
2427: value
2428: = find_dummy_reload (recog_operand[i], recog_operand[c],
2429: recog_operand_loc[i], recog_operand_loc[c],
2430: this_alternative[c], -1);
2431:
2432: if (value != 0)
2433: losers--;
2434: }
2435: /* This can be fixed with reloads if the operand
2436: we are supposed to match can be fixed with reloads. */
2437: badop = 0;
2438: this_alternative[i] = this_alternative[c];
2439: break;
2440:
2441: case 'p':
2442: /* All necessary reloads for an address_operand
2443: were handled in find_reloads_address. */
2444: this_alternative[i] = (int) ALL_REGS;
2445: win = 1;
2446: break;
2447:
2448: case 'm':
2449: if (force_reload)
2450: break;
2451: if (GET_CODE (operand) == MEM
2452: || (GET_CODE (operand) == REG
2453: && REGNO (operand) >= FIRST_PSEUDO_REGISTER
2454: && reg_renumber[REGNO (operand)] < 0))
2455: win = 1;
2456: if (CONSTANT_P (operand))
2457: badop = 0;
2458: break;
2459:
2460: case '<':
2461: if (GET_CODE (operand) == MEM
2462: && ! address_reloaded[i]
2463: && (GET_CODE (XEXP (operand, 0)) == PRE_DEC
2464: || GET_CODE (XEXP (operand, 0)) == POST_DEC))
2465: win = 1;
2466: break;
2467:
2468: case '>':
2469: if (GET_CODE (operand) == MEM
2470: && ! address_reloaded[i]
2471: && (GET_CODE (XEXP (operand, 0)) == PRE_INC
2472: || GET_CODE (XEXP (operand, 0)) == POST_INC))
2473: win = 1;
2474: break;
2475:
2476: /* Memory operand whose address is not offsettable. */
2477: case 'V':
2478: if (force_reload)
2479: break;
2480: if (GET_CODE (operand) == MEM
2481: && ! (ind_levels ? offsettable_memref_p (operand)
2482: : offsettable_nonstrict_memref_p (operand))
2483: /* Certain mem addresses will become offsettable
2484: after they themselves are reloaded. This is important;
2485: we don't want our own handling of unoffsettables
2486: to override the handling of reg_equiv_address. */
2487: && !(GET_CODE (XEXP (operand, 0)) == REG
2488: && (ind_levels == 0
2489: || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)))
2490: win = 1;
2491: break;
2492:
2493: /* Memory operand whose address is offsettable. */
2494: case 'o':
2495: if (force_reload)
2496: break;
2497: if ((GET_CODE (operand) == MEM
2498: /* If IND_LEVELS, find_reloads_address won't reload a
2499: pseudo that didn't get a hard reg, so we have to
2500: reject that case. */
2501: && (ind_levels ? offsettable_memref_p (operand)
2502: : offsettable_nonstrict_memref_p (operand)))
2503: /* Certain mem addresses will become offsettable
2504: after they themselves are reloaded. This is important;
2505: we don't want our own handling of unoffsettables
2506: to override the handling of reg_equiv_address. */
2507: || (GET_CODE (operand) == MEM
2508: && GET_CODE (XEXP (operand, 0)) == REG
2509: && (ind_levels == 0
2510: || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))
2511: || (GET_CODE (operand) == REG
2512: && REGNO (operand) >= FIRST_PSEUDO_REGISTER
2513: && reg_renumber[REGNO (operand)] < 0))
2514: win = 1;
2515: if (CONSTANT_P (operand) || GET_CODE (operand) == MEM)
2516: badop = 0;
2517: offmemok = 1;
2518: break;
2519:
2520: case '&':
2521: /* Output operand that is stored before the need for the
2522: input operands (and their index registers) is over. */
2523: earlyclobber = 1, this_earlyclobber = 1;
2524: break;
2525:
2526: case 'E':
2527: /* Match any floating double constant, but only if
2528: we can examine the bits of it reliably. */
2529: if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1.1.1.4 ! root 2530: || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1.1 root 2531: && GET_MODE (operand) != VOIDmode && ! flag_pretend_float)
2532: break;
2533: if (GET_CODE (operand) == CONST_DOUBLE)
2534: win = 1;
2535: break;
2536:
2537: case 'F':
2538: if (GET_CODE (operand) == CONST_DOUBLE)
2539: win = 1;
2540: break;
2541:
2542: case 'G':
2543: case 'H':
2544: if (GET_CODE (operand) == CONST_DOUBLE
2545: && CONST_DOUBLE_OK_FOR_LETTER_P (operand, c))
2546: win = 1;
2547: break;
2548:
2549: case 's':
2550: if (GET_CODE (operand) == CONST_INT
2551: || (GET_CODE (operand) == CONST_DOUBLE
2552: && GET_MODE (operand) == VOIDmode))
2553: break;
2554: case 'i':
2555: if (CONSTANT_P (operand)
2556: #ifdef LEGITIMATE_PIC_OPERAND_P
2557: && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand))
2558: #endif
2559: )
2560: win = 1;
2561: break;
2562:
2563: case 'n':
2564: if (GET_CODE (operand) == CONST_INT
2565: || (GET_CODE (operand) == CONST_DOUBLE
2566: && GET_MODE (operand) == VOIDmode))
2567: win = 1;
2568: break;
2569:
2570: case 'I':
2571: case 'J':
2572: case 'K':
2573: case 'L':
2574: case 'M':
2575: case 'N':
2576: case 'O':
2577: case 'P':
2578: if (GET_CODE (operand) == CONST_INT
2579: && CONST_OK_FOR_LETTER_P (INTVAL (operand), c))
2580: win = 1;
2581: break;
2582:
2583: case 'X':
2584: win = 1;
2585: break;
2586:
2587: case 'g':
2588: if (! force_reload
2589: /* A PLUS is never a valid operand, but reload can make
2590: it from a register when eliminating registers. */
2591: && GET_CODE (operand) != PLUS
2592: /* A SCRATCH is not a valid operand. */
2593: && GET_CODE (operand) != SCRATCH
2594: #ifdef LEGITIMATE_PIC_OPERAND_P
2595: && (! CONSTANT_P (operand)
2596: || ! flag_pic
2597: || LEGITIMATE_PIC_OPERAND_P (operand))
2598: #endif
2599: && (GENERAL_REGS == ALL_REGS
2600: || GET_CODE (operand) != REG
2601: || (REGNO (operand) >= FIRST_PSEUDO_REGISTER
2602: && reg_renumber[REGNO (operand)] < 0)))
2603: win = 1;
2604: /* Drop through into 'r' case */
2605:
2606: case 'r':
2607: this_alternative[i]
2608: = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS];
2609: goto reg;
2610:
2611: #ifdef EXTRA_CONSTRAINT
2612: case 'Q':
2613: case 'R':
2614: case 'S':
2615: case 'T':
2616: case 'U':
2617: if (EXTRA_CONSTRAINT (operand, c))
2618: win = 1;
2619: break;
2620: #endif
2621:
2622: default:
2623: this_alternative[i]
2624: = (int) reg_class_subunion[this_alternative[i]][(int) REG_CLASS_FROM_LETTER (c)];
2625:
2626: reg:
2627: if (GET_MODE (operand) == BLKmode)
2628: break;
2629: winreg = 1;
2630: if (GET_CODE (operand) == REG
2631: && reg_fits_class_p (operand, this_alternative[i],
2632: offset, GET_MODE (recog_operand[i])))
2633: win = 1;
2634: break;
2635: }
2636:
2637: constraints[i] = p;
2638:
2639: /* If this operand could be handled with a reg,
2640: and some reg is allowed, then this operand can be handled. */
2641: if (winreg && this_alternative[i] != (int) NO_REGS)
2642: badop = 0;
2643:
2644: /* Record which operands fit this alternative. */
2645: this_alternative_earlyclobber[i] = earlyclobber;
2646: if (win && ! force_reload)
2647: this_alternative_win[i] = 1;
2648: else
2649: {
2650: this_alternative_offmemok[i] = offmemok;
2651: losers++;
2652: if (badop)
2653: bad = 1;
2654: /* Alternative loses if it has no regs for a reg operand. */
2655: if (GET_CODE (operand) == REG
2656: && this_alternative[i] == (int) NO_REGS
2657: && this_alternative_matches[i] < 0)
2658: bad = 1;
2659:
2660: /* Alternative loses if it requires a type of reload not
2661: permitted for this insn. We can always reload SCRATCH
2662: and objects with a REG_UNUSED note. */
2663: if (GET_CODE (operand) != SCRATCH && modified[i] != RELOAD_READ
2664: && no_output_reloads
2665: && ! find_reg_note (insn, REG_UNUSED, operand))
2666: bad = 1;
2667: else if (modified[i] != RELOAD_WRITE && no_input_reloads)
2668: bad = 1;
2669:
2670: /* We prefer to reload pseudos over reloading other things,
2671: since such reloads may be able to be eliminated later.
2672: If we are reloading a SCRATCH, we won't be generating any
2673: insns, just using a register, so it is also preferred.
2674: So bump REJECT in other cases. */
2675: if (GET_CODE (operand) != REG && GET_CODE (operand) != SCRATCH)
2676: reject++;
2677: }
2678:
2679: /* If this operand is a pseudo register that didn't get a hard
2680: reg and this alternative accepts some register, see if the
2681: class that we want is a subset of the preferred class for this
2682: register. If not, but it intersects that class, use the
2683: preferred class instead. If it does not intersect the preferred
2684: class, show that usage of this alternative should be discouraged;
2685: it will be discouraged more still if the register is `preferred
2686: or nothing'. We do this because it increases the chance of
2687: reusing our spill register in a later insn and avoiding a pair
2688: of memory stores and loads.
2689:
2690: Don't bother with this if this alternative will accept this
2691: operand.
2692:
1.1.1.4 ! root 2693: Don't do this for a multiword operand, if
! 2694: we have to worry about small classes, because making reg groups
! 2695: harder to allocate is asking for trouble.
! 2696:
1.1 root 2697: Don't do this if the preferred class has only one register
2698: because we might otherwise exhaust the class. */
2699:
2700:
2701: if (! win && this_alternative[i] != (int) NO_REGS
1.1.1.4 ! root 2702: #ifdef SMALL_REGISTER_CLASSES
! 2703: && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD
! 2704: #endif
1.1 root 2705: && reg_class_size[(int) preferred_class[i]] > 1)
2706: {
2707: if (! reg_class_subset_p (this_alternative[i],
2708: preferred_class[i]))
2709: {
2710: /* Since we don't have a way of forming the intersection,
2711: we just do something special if the preferred class
2712: is a subset of the class we have; that's the most
2713: common case anyway. */
2714: if (reg_class_subset_p (preferred_class[i],
2715: this_alternative[i]))
2716: this_alternative[i] = (int) preferred_class[i];
2717: else
2718: reject += (1 + pref_or_nothing[i]);
2719: }
2720: }
2721: }
2722:
2723: /* Now see if any output operands that are marked "earlyclobber"
2724: in this alternative conflict with any input operands
2725: or any memory addresses. */
2726:
2727: for (i = 0; i < noperands; i++)
2728: if (this_alternative_earlyclobber[i]
2729: && this_alternative_win[i])
2730: {
2731: struct decomposition early_data;
2732: int j;
2733:
2734: early_data = decompose (recog_operand[i]);
2735:
2736: if (modified[i] == RELOAD_READ)
2737: {
2738: if (this_insn_is_asm)
2739: warning_for_asm (this_insn,
2740: "`&' constraint used with input operand");
2741: else
2742: abort ();
2743: continue;
2744: }
2745:
2746: if (this_alternative[i] == NO_REGS)
2747: {
2748: this_alternative_earlyclobber[i] = 0;
2749: if (this_insn_is_asm)
2750: error_for_asm (this_insn,
2751: "`&' constraint used with no register class");
2752: else
2753: abort ();
2754: }
2755:
2756: for (j = 0; j < noperands; j++)
2757: /* Is this an input operand or a memory ref? */
2758: if ((GET_CODE (recog_operand[j]) == MEM
2759: || modified[j] != RELOAD_WRITE)
2760: && j != i
2761: /* Ignore things like match_operator operands. */
2762: && *constraints1[j] != 0
2763: /* Don't count an input operand that is constrained to match
2764: the early clobber operand. */
2765: && ! (this_alternative_matches[j] == i
2766: && rtx_equal_p (recog_operand[i], recog_operand[j]))
2767: /* Is it altered by storing the earlyclobber operand? */
2768: && !immune_p (recog_operand[j], recog_operand[i], early_data))
2769: {
2770: /* If the output is in a single-reg class,
2771: it's costly to reload it, so reload the input instead. */
2772: if (reg_class_size[this_alternative[i]] == 1
2773: && (GET_CODE (recog_operand[j]) == REG
2774: || GET_CODE (recog_operand[j]) == SUBREG))
2775: {
2776: losers++;
2777: this_alternative_win[j] = 0;
2778: }
2779: else
2780: break;
2781: }
2782: /* If an earlyclobber operand conflicts with something,
2783: it must be reloaded, so request this and count the cost. */
2784: if (j != noperands)
2785: {
2786: losers++;
2787: this_alternative_win[i] = 0;
2788: for (j = 0; j < noperands; j++)
2789: if (this_alternative_matches[j] == i
2790: && this_alternative_win[j])
2791: {
2792: this_alternative_win[j] = 0;
2793: losers++;
2794: }
2795: }
2796: }
2797:
2798: /* If one alternative accepts all the operands, no reload required,
2799: choose that alternative; don't consider the remaining ones. */
2800: if (losers == 0)
2801: {
2802: /* Unswap these so that they are never swapped at `finish'. */
2803: if (commutative >= 0)
2804: {
2805: recog_operand[commutative] = substed_operand[commutative];
2806: recog_operand[commutative + 1]
2807: = substed_operand[commutative + 1];
2808: }
2809: for (i = 0; i < noperands; i++)
2810: {
2811: goal_alternative_win[i] = 1;
2812: goal_alternative[i] = this_alternative[i];
2813: goal_alternative_offmemok[i] = this_alternative_offmemok[i];
2814: goal_alternative_matches[i] = this_alternative_matches[i];
2815: goal_alternative_earlyclobber[i]
2816: = this_alternative_earlyclobber[i];
2817: }
2818: goal_alternative_number = this_alternative_number;
2819: goal_alternative_swapped = swapped;
2820: goal_earlyclobber = this_earlyclobber;
2821: goto finish;
2822: }
2823:
2824: /* REJECT, set by the ! and ? constraint characters and when a register
2825: would be reloaded into a non-preferred class, discourages the use of
2826: this alternative for a reload goal. REJECT is incremented by three
2827: for each ? and one for each non-preferred class. */
2828: losers = losers * 3 + reject;
2829:
2830: /* If this alternative can be made to work by reloading,
2831: and it needs less reloading than the others checked so far,
2832: record it as the chosen goal for reloading. */
2833: if (! bad && best > losers)
2834: {
2835: for (i = 0; i < noperands; i++)
2836: {
2837: goal_alternative[i] = this_alternative[i];
2838: goal_alternative_win[i] = this_alternative_win[i];
2839: goal_alternative_offmemok[i] = this_alternative_offmemok[i];
2840: goal_alternative_matches[i] = this_alternative_matches[i];
2841: goal_alternative_earlyclobber[i]
2842: = this_alternative_earlyclobber[i];
2843: }
2844: goal_alternative_swapped = swapped;
2845: best = losers;
2846: goal_alternative_number = this_alternative_number;
2847: goal_earlyclobber = this_earlyclobber;
2848: }
2849: }
2850:
2851: /* If insn is commutative (it's safe to exchange a certain pair of operands)
2852: then we need to try each alternative twice,
2853: the second time matching those two operands
2854: as if we had exchanged them.
2855: To do this, really exchange them in operands.
2856:
2857: If we have just tried the alternatives the second time,
2858: return operands to normal and drop through. */
2859:
2860: if (commutative >= 0)
2861: {
2862: swapped = !swapped;
2863: if (swapped)
2864: {
2865: register enum reg_class tclass;
2866: register int t;
2867:
2868: recog_operand[commutative] = substed_operand[commutative + 1];
2869: recog_operand[commutative + 1] = substed_operand[commutative];
2870:
2871: tclass = preferred_class[commutative];
2872: preferred_class[commutative] = preferred_class[commutative + 1];
2873: preferred_class[commutative + 1] = tclass;
2874:
2875: t = pref_or_nothing[commutative];
2876: pref_or_nothing[commutative] = pref_or_nothing[commutative + 1];
2877: pref_or_nothing[commutative + 1] = t;
2878:
2879: bcopy (constraints1, constraints, noperands * sizeof (char *));
2880: goto try_swapped;
2881: }
2882: else
2883: {
2884: recog_operand[commutative] = substed_operand[commutative];
2885: recog_operand[commutative + 1] = substed_operand[commutative + 1];
2886: }
2887: }
2888:
2889: /* The operands don't meet the constraints.
2890: goal_alternative describes the alternative
2891: that we could reach by reloading the fewest operands.
2892: Reload so as to fit it. */
2893:
2894: if (best == MAX_RECOG_OPERANDS + 300)
2895: {
2896: /* No alternative works with reloads?? */
2897: if (insn_code_number >= 0)
2898: abort ();
2899: error_for_asm (insn, "inconsistent operand constraints in an `asm'");
2900: /* Avoid further trouble with this insn. */
2901: PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
2902: n_reloads = 0;
2903: return;
2904: }
2905:
2906: /* Jump to `finish' from above if all operands are valid already.
2907: In that case, goal_alternative_win is all 1. */
2908: finish:
2909:
2910: /* Right now, for any pair of operands I and J that are required to match,
2911: with I < J,
2912: goal_alternative_matches[J] is I.
2913: Set up goal_alternative_matched as the inverse function:
2914: goal_alternative_matched[I] = J. */
2915:
2916: for (i = 0; i < noperands; i++)
2917: goal_alternative_matched[i] = -1;
2918:
2919: for (i = 0; i < noperands; i++)
2920: if (! goal_alternative_win[i]
2921: && goal_alternative_matches[i] >= 0)
2922: goal_alternative_matched[goal_alternative_matches[i]] = i;
2923:
2924: /* If the best alternative is with operands 1 and 2 swapped,
2925: consider them swapped before reporting the reloads. */
2926:
2927: if (goal_alternative_swapped)
2928: {
2929: register rtx tem;
2930:
2931: tem = substed_operand[commutative];
2932: substed_operand[commutative] = substed_operand[commutative + 1];
2933: substed_operand[commutative + 1] = tem;
2934: tem = recog_operand[commutative];
2935: recog_operand[commutative] = recog_operand[commutative + 1];
2936: recog_operand[commutative + 1] = tem;
2937: }
2938:
2939: /* Perform whatever substitutions on the operands we are supposed
2940: to make due to commutativity or replacement of registers
2941: with equivalent constants or memory slots. */
2942:
2943: for (i = 0; i < noperands; i++)
2944: {
2945: *recog_operand_loc[i] = substed_operand[i];
2946: /* While we are looping on operands, initialize this. */
2947: operand_reloadnum[i] = -1;
2948: }
2949:
2950: /* Any constants that aren't allowed and can't be reloaded
2951: into registers are here changed into memory references. */
2952: for (i = 0; i < noperands; i++)
2953: if (! goal_alternative_win[i]
2954: && CONSTANT_P (recog_operand[i])
2955: && (PREFERRED_RELOAD_CLASS (recog_operand[i],
2956: (enum reg_class) goal_alternative[i])
2957: == NO_REGS)
2958: && operand_mode[i] != VOIDmode)
2959: {
2960: *recog_operand_loc[i] = recog_operand[i]
2961: = find_reloads_toplev (force_const_mem (operand_mode[i],
2962: recog_operand[i]),
2963: ind_levels, 0);
2964: if (alternative_allows_memconst (constraints1[i],
2965: goal_alternative_number))
2966: goal_alternative_win[i] = 1;
2967: }
2968:
2969: /* Now record reloads for all the operands that need them. */
2970: for (i = 0; i < noperands; i++)
2971: if (! goal_alternative_win[i])
2972: {
2973: /* Operands that match previous ones have already been handled. */
2974: if (goal_alternative_matches[i] >= 0)
2975: ;
2976: /* Handle an operand with a nonoffsettable address
2977: appearing where an offsettable address will do
2978: by reloading the address into a base register. */
2979: else if (goal_alternative_matched[i] == -1
2980: && goal_alternative_offmemok[i]
2981: && GET_CODE (recog_operand[i]) == MEM)
2982: {
2983: operand_reloadnum[i]
1.1.1.4 ! root 2984: = push_reload (XEXP (recog_operand[i], 0), NULL_RTX,
! 2985: &XEXP (recog_operand[i], 0), NULL_PTR,
1.1 root 2986: BASE_REG_CLASS, GET_MODE (XEXP (recog_operand[i], 0)),
1.1.1.4 ! root 2987: VOIDmode, 0, 0, NULL_RTX);
1.1 root 2988: reload_inc[operand_reloadnum[i]]
2989: = GET_MODE_SIZE (GET_MODE (recog_operand[i]));
2990: }
2991: else if (goal_alternative_matched[i] == -1)
2992: operand_reloadnum[i] =
2993: push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0,
2994: modified[i] != RELOAD_READ ? recog_operand[i] : 0,
2995: modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0,
2996: modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0,
2997: (enum reg_class) goal_alternative[i],
2998: (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]),
2999: (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]),
3000: (insn_code_number < 0 ? 0
3001: : insn_operand_strict_low[insn_code_number][i]),
1.1.1.4 ! root 3002: 0, NULL_RTX);
1.1 root 3003: /* In a matching pair of operands, one must be input only
3004: and the other must be output only.
3005: Pass the input operand as IN and the other as OUT. */
3006: else if (modified[i] == RELOAD_READ
3007: && modified[goal_alternative_matched[i]] == RELOAD_WRITE)
3008: {
3009: operand_reloadnum[i]
3010: = push_reload (recog_operand[i],
3011: recog_operand[goal_alternative_matched[i]],
3012: recog_operand_loc[i],
3013: recog_operand_loc[goal_alternative_matched[i]],
3014: (enum reg_class) goal_alternative[i],
3015: operand_mode[i],
3016: operand_mode[goal_alternative_matched[i]],
1.1.1.4 ! root 3017: 0, 0, NULL_RTX);
1.1 root 3018: operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum;
3019: }
3020: else if (modified[i] == RELOAD_WRITE
3021: && modified[goal_alternative_matched[i]] == RELOAD_READ)
3022: {
3023: operand_reloadnum[goal_alternative_matched[i]]
3024: = push_reload (recog_operand[goal_alternative_matched[i]],
3025: recog_operand[i],
3026: recog_operand_loc[goal_alternative_matched[i]],
3027: recog_operand_loc[i],
3028: (enum reg_class) goal_alternative[i],
3029: operand_mode[goal_alternative_matched[i]],
3030: operand_mode[i],
1.1.1.4 ! root 3031: 0, 0, NULL_RTX);
1.1 root 3032: operand_reloadnum[i] = output_reloadnum;
3033: }
3034: else if (insn_code_number >= 0)
3035: abort ();
3036: else
3037: {
3038: error_for_asm (insn, "inconsistent operand constraints in an `asm'");
3039: /* Avoid further trouble with this insn. */
3040: PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx);
3041: n_reloads = 0;
3042: return;
3043: }
3044: }
3045: else if (goal_alternative_matched[i] < 0
3046: && goal_alternative_matches[i] < 0
3047: && optimize)
3048: {
3049: rtx operand = recog_operand[i];
3050: /* For each non-matching operand that's a pseudo-register
3051: that didn't get a hard register, make an optional reload.
3052: This may get done even if the insn needs no reloads otherwise. */
3053: /* (It would be safe to make an optional reload for a matching pair
3054: of operands, but we don't bother yet.) */
3055: while (GET_CODE (operand) == SUBREG)
3056: operand = XEXP (operand, 0);
3057: if (GET_CODE (operand) == REG
3058: && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3059: && reg_renumber[REGNO (operand)] < 0
3060: && (enum reg_class) goal_alternative[i] != NO_REGS
3061: /* Don't make optional output reloads for jump insns
3062: (such as aobjeq on the vax). */
3063: && (modified[i] == RELOAD_READ
3064: || GET_CODE (insn) != JUMP_INSN))
3065: operand_reloadnum[i]
3066: = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0,
3067: modified[i] != RELOAD_READ ? recog_operand[i] : 0,
3068: modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0,
3069: modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0,
3070: (enum reg_class) goal_alternative[i],
3071: (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]),
3072: (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]),
3073: (insn_code_number < 0 ? 0
3074: : insn_operand_strict_low[insn_code_number][i]),
1.1.1.4 ! root 3075: 1, NULL_RTX);
1.1 root 3076: /* Make an optional reload for an explicit mem ref. */
3077: else if (GET_CODE (operand) == MEM
3078: && (enum reg_class) goal_alternative[i] != NO_REGS
3079: /* Don't make optional output reloads for jump insns
3080: (such as aobjeq on the vax). */
3081: && (modified[i] == RELOAD_READ
3082: || GET_CODE (insn) != JUMP_INSN))
3083: operand_reloadnum[i]
3084: = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0,
3085: modified[i] != RELOAD_READ ? recog_operand[i] : 0,
3086: modified[i] != RELOAD_WRITE ? recog_operand_loc[i] : 0,
3087: modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0,
3088: (enum reg_class) goal_alternative[i],
3089: (modified[i] == RELOAD_WRITE ? VOIDmode : operand_mode[i]),
3090: (modified[i] == RELOAD_READ ? VOIDmode : operand_mode[i]),
3091: (insn_code_number < 0 ? 0
3092: : insn_operand_strict_low[insn_code_number][i]),
1.1.1.4 ! root 3093: 1, NULL_RTX);
1.1 root 3094: else
3095: non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i];
3096: }
3097: else if (goal_alternative_matched[i] < 0
3098: && goal_alternative_matches[i] < 0)
3099: non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i];
3100:
3101: /* Record the values of the earlyclobber operands for the caller. */
3102: if (goal_earlyclobber)
3103: for (i = 0; i < noperands; i++)
3104: if (goal_alternative_earlyclobber[i])
3105: reload_earlyclobbers[n_earlyclobbers++] = recog_operand[i];
3106:
3107: /* If this insn pattern contains any MATCH_DUP's, make sure that
3108: they will be substituted if the operands they match are substituted.
3109: Also do now any substitutions we already did on the operands.
3110:
3111: Don't do this if we aren't making replacements because we might be
3112: propagating things allocated by frame pointer elimination into places
3113: it doesn't expect. */
3114:
3115: if (insn_code_number >= 0 && replace)
3116: for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
3117: {
3118: int opno = recog_dup_num[i];
3119: *recog_dup_loc[i] = *recog_operand_loc[opno];
3120: if (operand_reloadnum[opno] >= 0)
3121: push_replacement (recog_dup_loc[i], operand_reloadnum[opno],
3122: insn_operand_mode[insn_code_number][opno]);
3123: }
3124:
3125: #if 0
3126: /* This loses because reloading of prior insns can invalidate the equivalence
3127: (or at least find_equiv_reg isn't smart enough to find it any more),
3128: causing this insn to need more reload regs than it needed before.
3129: It may be too late to make the reload regs available.
3130: Now this optimization is done safely in choose_reload_regs. */
3131:
3132: /* For each reload of a reg into some other class of reg,
3133: search for an existing equivalent reg (same value now) in the right class.
3134: We can use it as long as we don't need to change its contents. */
3135: for (i = 0; i < n_reloads; i++)
3136: if (reload_reg_rtx[i] == 0
3137: && reload_in[i] != 0
3138: && GET_CODE (reload_in[i]) == REG
3139: && reload_out[i] == 0)
3140: {
3141: reload_reg_rtx[i]
3142: = find_equiv_reg (reload_in[i], insn, reload_reg_class[i], -1,
3143: static_reload_reg_p, 0, reload_inmode[i]);
3144: /* Prevent generation of insn to load the value
3145: because the one we found already has the value. */
3146: if (reload_reg_rtx[i])
3147: reload_in[i] = reload_reg_rtx[i];
3148: }
3149: #endif
3150:
3151: #else /* no REGISTER_CONSTRAINTS */
3152: int noperands;
3153: int insn_code_number;
3154: int goal_earlyclobber = 0; /* Always 0, to make combine_reloads happen. */
3155: register int i;
3156: rtx body = PATTERN (insn);
3157:
3158: n_reloads = 0;
3159: n_replacements = 0;
3160: n_earlyclobbers = 0;
3161: replace_reloads = replace;
3162: this_insn = insn;
3163:
3164: /* Find what kind of insn this is. NOPERANDS gets number of operands.
3165: Store the operand values in RECOG_OPERAND and the locations
3166: of the words in the insn that point to them in RECOG_OPERAND_LOC.
3167: Return if the insn needs no reload processing. */
3168:
3169: switch (GET_CODE (body))
3170: {
3171: case USE:
3172: case CLOBBER:
3173: case ASM_INPUT:
3174: case ADDR_VEC:
3175: case ADDR_DIFF_VEC:
3176: return;
3177:
3178: case PARALLEL:
3179: case SET:
3180: noperands = asm_noperands (body);
3181: if (noperands >= 0)
3182: {
3183: /* This insn is an `asm' with operands.
3184: First, find out how many operands, and allocate space. */
3185:
3186: insn_code_number = -1;
3187: /* ??? This is a bug! ???
3188: Give up and delete this insn if it has too many operands. */
3189: if (noperands > MAX_RECOG_OPERANDS)
3190: abort ();
3191:
3192: /* Now get the operand values out of the insn. */
3193:
1.1.1.4 ! root 3194: decode_asm_operands (body, recog_operand, recog_operand_loc,
! 3195: NULL_PTR, NULL_PTR);
1.1 root 3196: break;
3197: }
3198:
3199: default:
3200: /* Ordinary insn: recognize it, allocate space for operands and
3201: constraints, and get them out via insn_extract. */
3202:
3203: insn_code_number = recog_memoized (insn);
3204: noperands = insn_n_operands[insn_code_number];
3205: insn_extract (insn);
3206: }
3207:
3208: if (noperands == 0)
3209: return;
3210:
3211: for (i = 0; i < noperands; i++)
3212: {
3213: register RTX_CODE code = GET_CODE (recog_operand[i]);
3214: int is_set_dest = GET_CODE (body) == SET && (i == 0);
3215:
3216: if (insn_code_number >= 0)
3217: if (insn_operand_address_p[insn_code_number][i])
1.1.1.4 ! root 3218: find_reloads_address (VOIDmode, NULL_PTR,
1.1 root 3219: recog_operand[i], recog_operand_loc[i],
3220: recog_operand[i], ind_levels);
3221: if (code == MEM)
3222: find_reloads_address (GET_MODE (recog_operand[i]),
3223: recog_operand_loc[i],
3224: XEXP (recog_operand[i], 0),
3225: &XEXP (recog_operand[i], 0),
3226: recog_operand[i], ind_levels);
3227: if (code == SUBREG)
3228: recog_operand[i] = *recog_operand_loc[i]
3229: = find_reloads_toplev (recog_operand[i], ind_levels, is_set_dest);
3230: if (code == REG)
3231: {
3232: register int regno = REGNO (recog_operand[i]);
3233: if (reg_equiv_constant[regno] != 0 && !is_set_dest)
3234: recog_operand[i] = *recog_operand_loc[i]
3235: = reg_equiv_constant[regno];
3236: #if 0 /* This might screw code in reload1.c to delete prior output-reload
3237: that feeds this insn. */
3238: if (reg_equiv_mem[regno] != 0)
3239: recog_operand[i] = *recog_operand_loc[i]
3240: = reg_equiv_mem[regno];
3241: #endif
3242: }
3243: /* All operands are non-reloaded. */
3244: non_reloaded_operands[n_non_reloaded_operands++] = recog_operand[i];
3245: }
3246: #endif /* no REGISTER_CONSTRAINTS */
3247:
3248: /* Determine which part of the insn each reload is needed for,
3249: based on which operand the reload is needed for.
3250: Reloads of entire operands are classified as RELOAD_OTHER.
3251: So are reloads for which a unique purpose is not known. */
3252:
3253: for (i = 0; i < n_reloads; i++)
3254: {
3255: reload_when_needed[i] = RELOAD_OTHER;
3256:
3257: if (reload_needed_for[i] != 0 && ! reload_needed_for_multiple[i])
3258: {
3259: int j;
3260: int output_address = 0;
3261: int input_address = 0;
3262: int operand_address = 0;
3263:
3264: /* This reload is needed only for the address of something.
3265: Determine whether it is needed for addressing an operand
3266: being reloaded for input, whether it is needed for an
3267: operand being reloaded for output, and whether it is needed
3268: for addressing an operand that won't really be reloaded.
3269:
3270: Note that we know that this reload is needed in only one address,
3271: but we have not yet checked for the case where that same address
3272: is used in both input and output reloads.
3273: The following code detects this case. */
3274:
3275: for (j = 0; j < n_reloads; j++)
3276: if (reload_needed_for[i] == reload_in[j]
3277: || reload_needed_for[i] == reload_out[j])
3278: {
3279: if (reload_optional[j])
3280: operand_address = 1;
3281: else
3282: {
3283: if (reload_needed_for[i] == reload_in[j])
3284: input_address = 1;
3285: if (reload_needed_for[i] == reload_out[j])
3286: output_address = 1;
3287: }
3288: }
3289: /* Don't ignore memrefs without optional reloads. */
3290: for (j = 0; j < n_non_reloaded_operands; j++)
3291: if (reload_needed_for[i] == non_reloaded_operands[j])
3292: operand_address = 1;
3293:
3294: /* If it is needed for only one of those, record which one. */
3295:
3296: if (input_address && ! output_address && ! operand_address)
3297: reload_when_needed[i] = RELOAD_FOR_INPUT_RELOAD_ADDRESS;
3298: if (output_address && ! input_address && ! operand_address)
3299: reload_when_needed[i] = RELOAD_FOR_OUTPUT_RELOAD_ADDRESS;
3300: if (operand_address && ! input_address && ! output_address)
3301: reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS;
3302:
3303: /* Indicate those RELOAD_OTHER reloads which, though they have
3304: 0 for reload_output, still cannot overlap an output reload. */
3305:
3306: if (output_address && reload_when_needed[i] == RELOAD_OTHER)
3307: reload_needed_for_multiple[i] = 1;
1.1.1.4 ! root 3308:
! 3309: /* If we have earlyclobbers, make sure nothing overlaps them. */
! 3310: if (n_earlyclobbers > 0)
! 3311: {
! 3312: reload_when_needed[i] = RELOAD_OTHER;
! 3313: reload_needed_for_multiple[i] = 1;
! 3314: }
1.1 root 3315: }
3316: }
3317:
3318: /* Perhaps an output reload can be combined with another
3319: to reduce needs by one. */
3320: if (!goal_earlyclobber)
3321: combine_reloads ();
3322: }
3323:
3324: /* Return 1 if alternative number ALTNUM in constraint-string CONSTRAINT
3325: accepts a memory operand with constant address. */
3326:
3327: static int
3328: alternative_allows_memconst (constraint, altnum)
3329: char *constraint;
3330: int altnum;
3331: {
3332: register int c;
3333: /* Skip alternatives before the one requested. */
3334: while (altnum > 0)
3335: {
3336: while (*constraint++ != ',');
3337: altnum--;
3338: }
3339: /* Scan the requested alternative for 'm' or 'o'.
3340: If one of them is present, this alternative accepts memory constants. */
3341: while ((c = *constraint++) && c != ',' && c != '#')
3342: if (c == 'm' || c == 'o')
3343: return 1;
3344: return 0;
3345: }
3346:
3347: /* Scan X for memory references and scan the addresses for reloading.
3348: Also checks for references to "constant" regs that we want to eliminate
3349: and replaces them with the values they stand for.
1.1.1.3 root 3350: We may alter X destructively if it contains a reference to such.
1.1 root 3351: If X is just a constant reg, we return the equivalent value
3352: instead of X.
3353:
3354: IND_LEVELS says how many levels of indirect addressing this machine
3355: supports.
3356:
3357: IS_SET_DEST is true if X is the destination of a SET, which is not
3358: appropriate to be replaced by a constant. */
3359:
3360: static rtx
3361: find_reloads_toplev (x, ind_levels, is_set_dest)
3362: rtx x;
3363: int ind_levels;
3364: int is_set_dest;
3365: {
3366: register RTX_CODE code = GET_CODE (x);
3367:
3368: register char *fmt = GET_RTX_FORMAT (code);
3369: register int i;
3370:
3371: if (code == REG)
3372: {
3373: /* This code is duplicated for speed in find_reloads. */
3374: register int regno = REGNO (x);
3375: if (reg_equiv_constant[regno] != 0 && !is_set_dest)
3376: x = reg_equiv_constant[regno];
3377: #if 0
3378: /* This creates (subreg (mem...)) which would cause an unnecessary
3379: reload of the mem. */
3380: else if (reg_equiv_mem[regno] != 0)
3381: x = reg_equiv_mem[regno];
3382: #endif
3383: else if (reg_equiv_address[regno] != 0)
3384: {
3385: /* If reg_equiv_address varies, it may be shared, so copy it. */
3386: rtx addr = reg_equiv_address[regno];
3387:
3388: if (rtx_varies_p (addr))
3389: addr = copy_rtx (addr);
3390:
3391: x = gen_rtx (MEM, GET_MODE (x), addr);
3392: RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
1.1.1.4 ! root 3393: find_reloads_address (GET_MODE (x), NULL_PTR,
1.1 root 3394: XEXP (x, 0),
3395: &XEXP (x, 0), x, ind_levels);
3396: }
3397: return x;
3398: }
3399: if (code == MEM)
3400: {
3401: rtx tem = x;
3402: find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0),
3403: x, ind_levels);
3404: return tem;
3405: }
3406:
3407: if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)
3408: {
3409: /* Check for SUBREG containing a REG that's equivalent to a constant.
3410: If the constant has a known value, truncate it right now.
3411: Similarly if we are extracting a single-word of a multi-word
3412: constant. If the constant is symbolic, allow it to be substituted
3413: normally. push_reload will strip the subreg later. If the
3414: constant is VOIDmode, abort because we will lose the mode of
3415: the register (this should never happen because one of the cases
3416: above should handle it). */
3417:
3418: register int regno = REGNO (SUBREG_REG (x));
3419: rtx tem;
3420:
3421: if (subreg_lowpart_p (x)
3422: && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
3423: && reg_equiv_constant[regno] != 0
3424: && (tem = gen_lowpart_common (GET_MODE (x),
3425: reg_equiv_constant[regno])) != 0)
3426: return tem;
3427:
3428: if (GET_MODE_BITSIZE (GET_MODE (x)) == BITS_PER_WORD
3429: && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
3430: && reg_equiv_constant[regno] != 0
3431: && (tem = operand_subword (reg_equiv_constant[regno],
3432: SUBREG_WORD (x), 0,
3433: GET_MODE (SUBREG_REG (x)))) != 0)
3434: return tem;
3435:
3436: if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
3437: && reg_equiv_constant[regno] != 0
3438: && GET_MODE (reg_equiv_constant[regno]) == VOIDmode)
3439: abort ();
3440:
3441: /* If the subreg contains a reg that will be converted to a mem,
3442: convert the subreg to a narrower memref now.
3443: Otherwise, we would get (subreg (mem ...) ...),
3444: which would force reload of the mem.
3445:
3446: We also need to do this if there is an equivalent MEM that is
3447: not offsettable. In that case, alter_subreg would produce an
1.1.1.2 root 3448: invalid address on big-endian machines.
3449:
1.1.1.4 ! root 3450: For machines that extend byte loads, we must not reload using
1.1.1.2 root 3451: a wider mode if we have a paradoxical SUBREG. find_reloads will
3452: force a reload in that case. So we should not do anything here. */
1.1 root 3453:
3454: else if (regno >= FIRST_PSEUDO_REGISTER
1.1.1.4 ! root 3455: #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
1.1.1.2 root 3456: && (GET_MODE_SIZE (GET_MODE (x))
3457: <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3458: #endif
1.1 root 3459: && (reg_equiv_address[regno] != 0
3460: || (reg_equiv_mem[regno] != 0
3461: && ! offsettable_memref_p (reg_equiv_mem[regno]))))
3462: {
3463: int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3464: rtx addr = (reg_equiv_address[regno] ? reg_equiv_address[regno]
3465: : XEXP (reg_equiv_mem[regno], 0));
3466: #if BYTES_BIG_ENDIAN
3467: int size;
3468: size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
3469: offset += MIN (size, UNITS_PER_WORD);
3470: size = GET_MODE_SIZE (GET_MODE (x));
3471: offset -= MIN (size, UNITS_PER_WORD);
3472: #endif
3473: addr = plus_constant (addr, offset);
3474: x = gen_rtx (MEM, GET_MODE (x), addr);
3475: RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
1.1.1.4 ! root 3476: find_reloads_address (GET_MODE (x), NULL_PTR,
1.1 root 3477: XEXP (x, 0),
3478: &XEXP (x, 0), x, ind_levels);
3479: }
3480:
3481: }
3482:
3483: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3484: {
3485: if (fmt[i] == 'e')
3486: XEXP (x, i) = find_reloads_toplev (XEXP (x, i),
3487: ind_levels, is_set_dest);
3488: }
3489: return x;
3490: }
3491:
3492: static rtx
3493: make_memloc (ad, regno)
3494: rtx ad;
3495: int regno;
3496: {
3497: register int i;
3498: rtx tem = reg_equiv_address[regno];
3499: for (i = 0; i < n_memlocs; i++)
3500: if (rtx_equal_p (tem, XEXP (memlocs[i], 0)))
3501: return memlocs[i];
3502:
3503: /* If TEM might contain a pseudo, we must copy it to avoid
3504: modifying it when we do the substitution for the reload. */
3505: if (rtx_varies_p (tem))
3506: tem = copy_rtx (tem);
3507:
3508: tem = gen_rtx (MEM, GET_MODE (ad), tem);
3509: RTX_UNCHANGING_P (tem) = RTX_UNCHANGING_P (regno_reg_rtx[regno]);
3510: memlocs[n_memlocs++] = tem;
3511: return tem;
3512: }
3513:
3514: /* Record all reloads needed for handling memory address AD
3515: which appears in *LOC in a memory reference to mode MODE
3516: which itself is found in location *MEMREFLOC.
3517: Note that we take shortcuts assuming that no multi-reg machine mode
3518: occurs as part of an address.
3519:
3520: OPERAND is the operand of the insn within which this address appears.
3521:
3522: IND_LEVELS says how many levels of indirect addressing this machine
3523: supports.
3524:
3525: Value is nonzero if this address is reloaded or replaced as a whole.
3526: This is interesting to the caller if the address is an autoincrement.
3527:
3528: Note that there is no verification that the address will be valid after
3529: this routine does its work. Instead, we rely on the fact that the address
3530: was valid when reload started. So we need only undo things that reload
3531: could have broken. These are wrong register types, pseudos not allocated
3532: to a hard register, and frame pointer elimination. */
3533:
3534: static int
3535: find_reloads_address (mode, memrefloc, ad, loc, operand, ind_levels)
3536: enum machine_mode mode;
3537: rtx *memrefloc;
3538: rtx ad;
3539: rtx *loc;
3540: rtx operand;
3541: int ind_levels;
3542: {
3543: register int regno;
3544: rtx tem;
3545:
3546: /* If the address is a register, see if it is a legitimate address and
3547: reload if not. We first handle the cases where we need not reload
3548: or where we must reload in a non-standard way. */
3549:
3550: if (GET_CODE (ad) == REG)
3551: {
3552: regno = REGNO (ad);
3553:
3554: if (reg_equiv_constant[regno] != 0
3555: && strict_memory_address_p (mode, reg_equiv_constant[regno]))
3556: {
3557: *loc = ad = reg_equiv_constant[regno];
3558: return 1;
3559: }
3560:
3561: else if (reg_equiv_address[regno] != 0)
3562: {
3563: tem = make_memloc (ad, regno);
1.1.1.4 ! root 3564: find_reloads_address (GET_MODE (tem), NULL_PTR, XEXP (tem, 0),
1.1 root 3565: &XEXP (tem, 0), operand, ind_levels);
1.1.1.4 ! root 3566: push_reload (tem, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS,
1.1 root 3567: GET_MODE (ad), VOIDmode, 0, 0,
3568: operand);
3569: return 1;
3570: }
3571:
3572: else if (reg_equiv_mem[regno] != 0)
3573: {
3574: tem = XEXP (reg_equiv_mem[regno], 0);
3575:
3576: /* If we can't indirect any more, a pseudo must be reloaded.
3577: If the pseudo's address in its MEM is a SYMBOL_REF, it
3578: must be reloaded unless indirect_symref_ok. Otherwise, it
3579: can be reloaded if the address is REG or REG + CONST_INT. */
3580:
3581: if (ind_levels > 0
3582: && ! (GET_CODE (tem) == SYMBOL_REF && ! indirect_symref_ok)
3583: && ((GET_CODE (tem) == REG
3584: && REGNO (tem) < FIRST_PSEUDO_REGISTER)
3585: || (GET_CODE (tem) == PLUS
3586: && GET_CODE (XEXP (tem, 0)) == REG
3587: && REGNO (XEXP (tem, 0)) < FIRST_PSEUDO_REGISTER
3588: && GET_CODE (XEXP (tem, 1)) == CONST_INT)))
3589: return 0;
3590: }
3591:
3592: /* The only remaining case where we can avoid a reload is if this is a
3593: hard register that is valid as a base register and which is not the
3594: subject of a CLOBBER in this insn. */
3595:
3596: else if (regno < FIRST_PSEUDO_REGISTER && REGNO_OK_FOR_BASE_P (regno)
3597: && ! regno_clobbered_p (regno, this_insn))
3598: return 0;
3599:
3600: /* If we do not have one of the cases above, we must do the reload. */
1.1.1.4 ! root 3601: push_reload (ad, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS,
1.1 root 3602: GET_MODE (ad), VOIDmode, 0, 0, operand);
3603: return 1;
3604: }
3605:
3606: if (strict_memory_address_p (mode, ad))
3607: {
3608: /* The address appears valid, so reloads are not needed.
3609: But the address may contain an eliminable register.
3610: This can happen because a machine with indirect addressing
3611: may consider a pseudo register by itself a valid address even when
3612: it has failed to get a hard reg.
3613: So do a tree-walk to find and eliminate all such regs. */
3614:
3615: /* But first quickly dispose of a common case. */
3616: if (GET_CODE (ad) == PLUS
3617: && GET_CODE (XEXP (ad, 1)) == CONST_INT
3618: && GET_CODE (XEXP (ad, 0)) == REG
3619: && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0)
3620: return 0;
3621:
3622: subst_reg_equivs_changed = 0;
3623: *loc = subst_reg_equivs (ad);
3624:
3625: if (! subst_reg_equivs_changed)
3626: return 0;
3627:
3628: /* Check result for validity after substitution. */
3629: if (strict_memory_address_p (mode, ad))
3630: return 0;
3631: }
3632:
3633: /* The address is not valid. We have to figure out why. One possibility
3634: is that it is itself a MEM. This can happen when the frame pointer is
3635: being eliminated, a pseudo is not allocated to a hard register, and the
3636: offset between the frame and stack pointers is not its initial value.
1.1.1.2 root 3637: In that case the pseudo will have been replaced by a MEM referring to
1.1 root 3638: the stack pointer. */
3639: if (GET_CODE (ad) == MEM)
3640: {
3641: /* First ensure that the address in this MEM is valid. Then, unless
3642: indirect addresses are valid, reload the MEM into a register. */
3643: tem = ad;
3644: find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0),
3645: operand, ind_levels == 0 ? 0 : ind_levels - 1);
1.1.1.4 ! root 3646:
! 3647: /* If tem was changed, then we must create a new memory reference to
! 3648: hold it and store it back into memrefloc. */
! 3649: if (tem != ad && memrefloc)
! 3650: {
! 3651: rtx oldref = *memrefloc;
! 3652: *memrefloc = copy_rtx (*memrefloc);
! 3653: copy_replacements (tem, XEXP (*memrefloc, 0));
! 3654: loc = &XEXP (*memrefloc, 0);
! 3655: if (operand == oldref)
! 3656: operand = *memrefloc;
! 3657: }
! 3658:
1.1 root 3659: /* Check similar cases as for indirect addresses as above except
3660: that we can allow pseudos and a MEM since they should have been
3661: taken care of above. */
3662:
3663: if (ind_levels == 0
3664: || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok)
3665: || GET_CODE (XEXP (tem, 0)) == MEM
3666: || ! (GET_CODE (XEXP (tem, 0)) == REG
3667: || (GET_CODE (XEXP (tem, 0)) == PLUS
3668: && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG
3669: && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT)))
3670: {
3671: /* Must use TEM here, not AD, since it is the one that will
3672: have any subexpressions reloaded, if needed. */
1.1.1.4 ! root 3673: push_reload (tem, NULL_RTX, loc, NULL_PTR,
1.1 root 3674: BASE_REG_CLASS, GET_MODE (tem), VOIDmode, 0,
3675: 0, operand);
3676: return 1;
3677: }
3678: else
3679: return 0;
3680: }
3681:
3682: /* If we have address of a stack slot but it's not valid
3683: (displacement is too large), compute the sum in a register. */
3684: else if (GET_CODE (ad) == PLUS
3685: && (XEXP (ad, 0) == frame_pointer_rtx
3686: #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3687: || XEXP (ad, 0) == arg_pointer_rtx
3688: #endif
3689: || XEXP (ad, 0) == stack_pointer_rtx)
3690: && GET_CODE (XEXP (ad, 1)) == CONST_INT)
3691: {
3692: /* Unshare the MEM rtx so we can safely alter it. */
3693: if (memrefloc)
3694: {
3695: rtx oldref = *memrefloc;
3696: *memrefloc = copy_rtx (*memrefloc);
3697: loc = &XEXP (*memrefloc, 0);
3698: if (operand == oldref)
3699: operand = *memrefloc;
3700: }
3701: if (double_reg_address_ok)
3702: {
3703: /* Unshare the sum as well. */
3704: *loc = ad = copy_rtx (ad);
3705: /* Reload the displacement into an index reg.
3706: We assume the frame pointer or arg pointer is a base reg. */
3707: find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1),
3708: INDEX_REG_CLASS, GET_MODE (ad), operand,
3709: ind_levels);
3710: }
3711: else
3712: {
3713: /* If the sum of two regs is not necessarily valid,
3714: reload the sum into a base reg.
3715: That will at least work. */
3716: find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode,
3717: operand, ind_levels);
3718: }
3719: return 1;
3720: }
3721:
3722: /* If we have an indexed stack slot, there are three possible reasons why
3723: it might be invalid: The index might need to be reloaded, the address
3724: might have been made by frame pointer elimination and hence have a
3725: constant out of range, or both reasons might apply.
3726:
3727: We can easily check for an index needing reload, but even if that is the
3728: case, we might also have an invalid constant. To avoid making the
3729: conservative assumption and requiring two reloads, we see if this address
3730: is valid when not interpreted strictly. If it is, the only problem is
3731: that the index needs a reload and find_reloads_address_1 will take care
3732: of it.
3733:
3734: There is still a case when we might generate an extra reload,
3735: however. In certain cases eliminate_regs will return a MEM for a REG
3736: (see the code there for details). In those cases, memory_address_p
3737: applied to our address will return 0 so we will think that our offset
3738: must be too large. But it might indeed be valid and the only problem
3739: is that a MEM is present where a REG should be. This case should be
3740: very rare and there doesn't seem to be any way to avoid it.
3741:
3742: If we decide to do something here, it must be that
3743: `double_reg_address_ok' is true and that this address rtl was made by
3744: eliminate_regs. We generate a reload of the fp/sp/ap + constant and
3745: rework the sum so that the reload register will be added to the index.
3746: This is safe because we know the address isn't shared.
3747:
3748: We check for fp/ap/sp as both the first and second operand of the
3749: innermost PLUS. */
3750:
3751: else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
3752: && GET_CODE (XEXP (ad, 0)) == PLUS
3753: && (XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx
3754: #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3755: || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx
3756: #endif
3757: || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx)
3758: && ! memory_address_p (mode, ad))
3759: {
3760: *loc = ad = gen_rtx (PLUS, GET_MODE (ad),
3761: plus_constant (XEXP (XEXP (ad, 0), 0),
3762: INTVAL (XEXP (ad, 1))),
3763: XEXP (XEXP (ad, 0), 1));
3764: find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS,
3765: GET_MODE (ad), operand, ind_levels);
3766: find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), operand, 0);
3767:
3768: return 1;
3769: }
3770:
3771: else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
3772: && GET_CODE (XEXP (ad, 0)) == PLUS
3773: && (XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx
3774: #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3775: || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx
3776: #endif
3777: || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx)
3778: && ! memory_address_p (mode, ad))
3779: {
3780: *loc = ad = gen_rtx (PLUS, GET_MODE (ad),
3781: plus_constant (XEXP (XEXP (ad, 0), 1),
3782: INTVAL (XEXP (ad, 1))),
3783: XEXP (XEXP (ad, 0), 0));
3784: find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS,
3785: GET_MODE (ad), operand, ind_levels);
3786: find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), operand, 0);
3787:
3788: return 1;
3789: }
3790:
3791: /* See if address becomes valid when an eliminable register
3792: in a sum is replaced. */
3793:
3794: tem = ad;
3795: if (GET_CODE (ad) == PLUS)
3796: tem = subst_indexed_address (ad);
3797: if (tem != ad && strict_memory_address_p (mode, tem))
3798: {
3799: /* Ok, we win that way. Replace any additional eliminable
3800: registers. */
3801:
3802: subst_reg_equivs_changed = 0;
3803: tem = subst_reg_equivs (tem);
3804:
3805: /* Make sure that didn't make the address invalid again. */
3806:
3807: if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem))
3808: {
3809: *loc = tem;
3810: return 0;
3811: }
3812: }
3813:
3814: /* If constants aren't valid addresses, reload the constant address
3815: into a register. */
1.1.1.4 ! root 3816: if (CONSTANT_P (ad) && ! strict_memory_address_p (mode, ad))
1.1 root 3817: {
3818: /* If AD is in address in the constant pool, the MEM rtx may be shared.
3819: Unshare it so we can safely alter it. */
3820: if (memrefloc && GET_CODE (ad) == SYMBOL_REF
3821: && CONSTANT_POOL_ADDRESS_P (ad))
3822: {
3823: rtx oldref = *memrefloc;
3824: *memrefloc = copy_rtx (*memrefloc);
3825: loc = &XEXP (*memrefloc, 0);
3826: if (operand == oldref)
3827: operand = *memrefloc;
3828: }
3829:
3830: find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, operand,
3831: ind_levels);
3832: return 1;
3833: }
3834:
3835: return find_reloads_address_1 (ad, 0, loc, operand, ind_levels);
3836: }
3837:
3838: /* Find all pseudo regs appearing in AD
3839: that are eliminable in favor of equivalent values
3840: and do not have hard regs; replace them by their equivalents. */
3841:
3842: static rtx
3843: subst_reg_equivs (ad)
3844: rtx ad;
3845: {
3846: register RTX_CODE code = GET_CODE (ad);
3847: register int i;
3848: register char *fmt;
3849:
3850: switch (code)
3851: {
3852: case HIGH:
3853: case CONST_INT:
3854: case CONST:
3855: case CONST_DOUBLE:
3856: case SYMBOL_REF:
3857: case LABEL_REF:
3858: case PC:
3859: case CC0:
3860: return ad;
3861:
3862: case REG:
3863: {
3864: register int regno = REGNO (ad);
3865:
3866: if (reg_equiv_constant[regno] != 0)
3867: {
3868: subst_reg_equivs_changed = 1;
3869: return reg_equiv_constant[regno];
3870: }
3871: }
3872: return ad;
3873:
3874: case PLUS:
3875: /* Quickly dispose of a common case. */
3876: if (XEXP (ad, 0) == frame_pointer_rtx
3877: && GET_CODE (XEXP (ad, 1)) == CONST_INT)
3878: return ad;
3879: }
3880:
3881: fmt = GET_RTX_FORMAT (code);
3882: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3883: if (fmt[i] == 'e')
3884: XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i));
3885: return ad;
3886: }
3887:
3888: /* Compute the sum of X and Y, making canonicalizations assumed in an
3889: address, namely: sum constant integers, surround the sum of two
3890: constants with a CONST, put the constant as the second operand, and
3891: group the constant on the outermost sum.
3892:
3893: This routine assumes both inputs are already in canonical form. */
3894:
3895: rtx
3896: form_sum (x, y)
3897: rtx x, y;
3898: {
3899: rtx tem;
3900:
3901: if (GET_CODE (x) == CONST_INT)
3902: return plus_constant (y, INTVAL (x));
3903: else if (GET_CODE (y) == CONST_INT)
3904: return plus_constant (x, INTVAL (y));
3905: else if (CONSTANT_P (x))
3906: tem = x, x = y, y = tem;
3907:
3908: if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1)))
3909: return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y));
3910:
3911: /* Note that if the operands of Y are specified in the opposite
3912: order in the recursive calls below, infinite recursion will occur. */
3913: if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1)))
3914: return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1));
3915:
3916: /* If both constant, encapsulate sum. Otherwise, just form sum. A
3917: constant will have been placed second. */
3918: if (CONSTANT_P (x) && CONSTANT_P (y))
3919: {
3920: if (GET_CODE (x) == CONST)
3921: x = XEXP (x, 0);
3922: if (GET_CODE (y) == CONST)
3923: y = XEXP (y, 0);
3924:
3925: return gen_rtx (CONST, VOIDmode, gen_rtx (PLUS, Pmode, x, y));
3926: }
3927:
3928: return gen_rtx (PLUS, Pmode, x, y);
3929: }
3930:
3931: /* If ADDR is a sum containing a pseudo register that should be
3932: replaced with a constant (from reg_equiv_constant),
3933: return the result of doing so, and also apply the associative
3934: law so that the result is more likely to be a valid address.
3935: (But it is not guaranteed to be one.)
3936:
3937: Note that at most one register is replaced, even if more are
3938: replaceable. Also, we try to put the result into a canonical form
3939: so it is more likely to be a valid address.
3940:
3941: In all other cases, return ADDR. */
3942:
3943: static rtx
3944: subst_indexed_address (addr)
3945: rtx addr;
3946: {
3947: rtx op0 = 0, op1 = 0, op2 = 0;
3948: rtx tem;
3949: int regno;
3950:
3951: if (GET_CODE (addr) == PLUS)
3952: {
3953: /* Try to find a register to replace. */
3954: op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0;
3955: if (GET_CODE (op0) == REG
3956: && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER
3957: && reg_renumber[regno] < 0
3958: && reg_equiv_constant[regno] != 0)
3959: op0 = reg_equiv_constant[regno];
3960: else if (GET_CODE (op1) == REG
3961: && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER
3962: && reg_renumber[regno] < 0
3963: && reg_equiv_constant[regno] != 0)
3964: op1 = reg_equiv_constant[regno];
3965: else if (GET_CODE (op0) == PLUS
3966: && (tem = subst_indexed_address (op0)) != op0)
3967: op0 = tem;
3968: else if (GET_CODE (op1) == PLUS
3969: && (tem = subst_indexed_address (op1)) != op1)
3970: op1 = tem;
3971: else
3972: return addr;
3973:
3974: /* Pick out up to three things to add. */
3975: if (GET_CODE (op1) == PLUS)
3976: op2 = XEXP (op1, 1), op1 = XEXP (op1, 0);
3977: else if (GET_CODE (op0) == PLUS)
3978: op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3979:
3980: /* Compute the sum. */
3981: if (op2 != 0)
3982: op1 = form_sum (op1, op2);
3983: if (op1 != 0)
3984: op0 = form_sum (op0, op1);
3985:
3986: return op0;
3987: }
3988: return addr;
3989: }
3990:
3991: /* Record the pseudo registers we must reload into hard registers
3992: in a subexpression of a would-be memory address, X.
3993: (This function is not called if the address we find is strictly valid.)
3994: CONTEXT = 1 means we are considering regs as index regs,
3995: = 0 means we are considering them as base regs.
3996:
3997: OPERAND is the operand of the insn within which this address appears.
3998:
3999: IND_LEVELS says how many levels of indirect addressing are
4000: supported at this point in the address.
4001:
4002: We return nonzero if X, as a whole, is reloaded or replaced. */
4003:
4004: /* Note that we take shortcuts assuming that no multi-reg machine mode
4005: occurs as part of an address.
4006: Also, this is not fully machine-customizable; it works for machines
4007: such as vaxes and 68000's and 32000's, but other possible machines
4008: could have addressing modes that this does not handle right. */
4009:
4010: static int
4011: find_reloads_address_1 (x, context, loc, operand, ind_levels)
4012: rtx x;
4013: int context;
4014: rtx *loc;
4015: rtx operand;
4016: int ind_levels;
4017: {
4018: register RTX_CODE code = GET_CODE (x);
4019:
4020: if (code == PLUS)
4021: {
4022: register rtx op0 = XEXP (x, 0);
4023: register rtx op1 = XEXP (x, 1);
4024: register RTX_CODE code0 = GET_CODE (op0);
4025: register RTX_CODE code1 = GET_CODE (op1);
4026: if (code0 == MULT || code0 == SIGN_EXTEND || code1 == MEM)
4027: {
4028: find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels);
4029: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
4030: }
4031: else if (code1 == MULT || code1 == SIGN_EXTEND || code0 == MEM)
4032: {
4033: find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
4034: find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels);
4035: }
4036: else if (code0 == CONST_INT || code0 == CONST
4037: || code0 == SYMBOL_REF || code0 == LABEL_REF)
4038: {
4039: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
4040: }
4041: else if (code1 == CONST_INT || code1 == CONST
4042: || code1 == SYMBOL_REF || code1 == LABEL_REF)
4043: {
4044: find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
4045: }
4046: else if (code0 == REG && code1 == REG)
4047: {
4048: if (REG_OK_FOR_INDEX_P (op0)
4049: && REG_OK_FOR_BASE_P (op1))
4050: return 0;
4051: else if (REG_OK_FOR_INDEX_P (op1)
4052: && REG_OK_FOR_BASE_P (op0))
4053: return 0;
4054: else if (REG_OK_FOR_BASE_P (op1))
4055: find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels);
4056: else if (REG_OK_FOR_BASE_P (op0))
4057: find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels);
4058: else if (REG_OK_FOR_INDEX_P (op1))
4059: find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
4060: else if (REG_OK_FOR_INDEX_P (op0))
4061: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
4062: else
4063: {
4064: find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand,
4065: ind_levels);
4066: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand,
4067: ind_levels);
4068: }
4069: }
4070: else if (code0 == REG)
4071: {
4072: find_reloads_address_1 (op0, 1, &XEXP (x, 0), operand, ind_levels);
4073: find_reloads_address_1 (op1, 0, &XEXP (x, 1), operand, ind_levels);
4074: }
4075: else if (code1 == REG)
4076: {
4077: find_reloads_address_1 (op1, 1, &XEXP (x, 1), operand, ind_levels);
4078: find_reloads_address_1 (op0, 0, &XEXP (x, 0), operand, ind_levels);
4079: }
4080: }
4081: else if (code == POST_INC || code == POST_DEC
4082: || code == PRE_INC || code == PRE_DEC)
4083: {
4084: if (GET_CODE (XEXP (x, 0)) == REG)
4085: {
4086: register int regno = REGNO (XEXP (x, 0));
4087: int value = 0;
4088: rtx x_orig = x;
4089:
4090: /* A register that is incremented cannot be constant! */
4091: if (regno >= FIRST_PSEUDO_REGISTER
4092: && reg_equiv_constant[regno] != 0)
4093: abort ();
4094:
4095: /* Handle a register that is equivalent to a memory location
4096: which cannot be addressed directly. */
4097: if (reg_equiv_address[regno] != 0)
4098: {
4099: rtx tem = make_memloc (XEXP (x, 0), regno);
4100: /* First reload the memory location's address. */
4101: find_reloads_address (GET_MODE (tem), 0, XEXP (tem, 0),
4102: &XEXP (tem, 0), operand, ind_levels);
4103: /* Put this inside a new increment-expression. */
4104: x = gen_rtx (GET_CODE (x), GET_MODE (x), tem);
4105: /* Proceed to reload that, as if it contained a register. */
4106: }
4107:
4108: /* If we have a hard register that is ok as an index,
4109: don't make a reload. If an autoincrement of a nice register
4110: isn't "valid", it must be that no autoincrement is "valid".
4111: If that is true and something made an autoincrement anyway,
4112: this must be a special context where one is allowed.
4113: (For example, a "push" instruction.)
4114: We can't improve this address, so leave it alone. */
4115:
4116: /* Otherwise, reload the autoincrement into a suitable hard reg
4117: and record how much to increment by. */
4118:
4119: if (reg_renumber[regno] >= 0)
4120: regno = reg_renumber[regno];
4121: if ((regno >= FIRST_PSEUDO_REGISTER
4122: || !(context ? REGNO_OK_FOR_INDEX_P (regno)
4123: : REGNO_OK_FOR_BASE_P (regno))))
4124: {
4125: register rtx link;
4126:
4127: int reloadnum
1.1.1.4 ! root 4128: = push_reload (x, NULL_RTX, loc, NULL_PTR,
1.1 root 4129: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4130: GET_MODE (x), GET_MODE (x), VOIDmode, 0, operand);
4131: reload_inc[reloadnum]
4132: = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0));
4133:
4134: value = 1;
4135:
4136: #ifdef AUTO_INC_DEC
4137: /* Update the REG_INC notes. */
4138:
4139: for (link = REG_NOTES (this_insn);
4140: link; link = XEXP (link, 1))
4141: if (REG_NOTE_KIND (link) == REG_INC
4142: && REGNO (XEXP (link, 0)) == REGNO (XEXP (x_orig, 0)))
4143: push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
4144: #endif
4145: }
4146: return value;
4147: }
4148: else if (GET_CODE (XEXP (x, 0)) == MEM)
4149: {
4150: /* This is probably the result of a substitution, by eliminate_regs,
4151: of an equivalent address for a pseudo that was not allocated to a
4152: hard register. Verify that the specified address is valid and
4153: reload it into a register. */
4154: rtx tem = XEXP (x, 0);
4155: register rtx link;
4156: int reloadnum;
4157:
4158: /* Since we know we are going to reload this item, don't decrement
4159: for the indirection level.
4160:
4161: Note that this is actually conservative: it would be slightly
4162: more efficient to use the value of SPILL_INDIRECT_LEVELS from
4163: reload1.c here. */
4164: find_reloads_address (GET_MODE (x), &XEXP (x, 0),
4165: XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0),
4166: operand, ind_levels);
4167:
1.1.1.4 ! root 4168: reloadnum = push_reload (x, NULL_RTX, loc, NULL_PTR,
1.1 root 4169: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4170: GET_MODE (x), VOIDmode, 0, 0, operand);
4171: reload_inc[reloadnum]
4172: = find_inc_amount (PATTERN (this_insn), XEXP (x, 0));
4173:
4174: link = FIND_REG_INC_NOTE (this_insn, tem);
4175: if (link != 0)
4176: push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
4177:
4178: return 1;
4179: }
4180: }
4181: else if (code == MEM)
4182: {
4183: /* This is probably the result of a substitution, by eliminate_regs,
4184: of an equivalent address for a pseudo that was not allocated to a
4185: hard register. Verify that the specified address is valid and reload
4186: it into a register.
4187:
4188: Since we know we are going to reload this item, don't decrement
4189: for the indirection level.
4190:
4191: Note that this is actually conservative: it would be slightly more
4192: efficient to use the value of SPILL_INDIRECT_LEVELS from
4193: reload1.c here. */
4194:
4195: find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
4196: operand, ind_levels);
4197:
1.1.1.4 ! root 4198: push_reload (*loc, NULL_RTX, loc, NULL_PTR,
1.1 root 4199: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4200: GET_MODE (x), VOIDmode, 0, 0, operand);
4201: return 1;
4202: }
4203: else if (code == REG)
4204: {
4205: register int regno = REGNO (x);
4206:
4207: if (reg_equiv_constant[regno] != 0)
4208: {
1.1.1.4 ! root 4209: find_reloads_address_part (reg_equiv_constant[regno], loc,
! 4210: (context ? INDEX_REG_CLASS
! 4211: : BASE_REG_CLASS),
! 4212: GET_MODE (x), operand, ind_levels);
1.1 root 4213: return 1;
4214: }
4215:
4216: #if 0 /* This might screw code in reload1.c to delete prior output-reload
4217: that feeds this insn. */
4218: if (reg_equiv_mem[regno] != 0)
4219: {
1.1.1.4 ! root 4220: push_reload (reg_equiv_mem[regno], NULL_RTX, loc, NULL_PTR,
1.1 root 4221: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4222: GET_MODE (x), VOIDmode, 0, 0, operand);
4223: return 1;
4224: }
4225: #endif
4226: if (reg_equiv_address[regno] != 0)
4227: {
4228: x = make_memloc (x, regno);
4229: find_reloads_address (GET_MODE (x), 0, XEXP (x, 0), &XEXP (x, 0),
4230: operand, ind_levels);
4231: }
4232:
4233: if (reg_renumber[regno] >= 0)
4234: regno = reg_renumber[regno];
4235: if ((regno >= FIRST_PSEUDO_REGISTER
4236: || !(context ? REGNO_OK_FOR_INDEX_P (regno)
4237: : REGNO_OK_FOR_BASE_P (regno))))
4238: {
1.1.1.4 ! root 4239: push_reload (x, NULL_RTX, loc, NULL_PTR,
1.1 root 4240: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4241: GET_MODE (x), VOIDmode, 0, 0, operand);
4242: return 1;
4243: }
4244:
4245: /* If a register appearing in an address is the subject of a CLOBBER
4246: in this insn, reload it into some other register to be safe.
4247: The CLOBBER is supposed to make the register unavailable
4248: from before this insn to after it. */
4249: if (regno_clobbered_p (regno, this_insn))
4250: {
1.1.1.4 ! root 4251: push_reload (x, NULL_RTX, loc, NULL_PTR,
1.1 root 4252: context ? INDEX_REG_CLASS : BASE_REG_CLASS,
4253: GET_MODE (x), VOIDmode, 0, 0, operand);
4254: return 1;
4255: }
4256: }
4257: else
4258: {
4259: register char *fmt = GET_RTX_FORMAT (code);
4260: register int i;
4261: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4262: {
4263: if (fmt[i] == 'e')
4264: find_reloads_address_1 (XEXP (x, i), context, &XEXP (x, i),
4265: operand, ind_levels);
4266: }
4267: }
4268:
4269: return 0;
4270: }
4271:
4272: /* X, which is found at *LOC, is a part of an address that needs to be
4273: reloaded into a register of class CLASS. If X is a constant, or if
4274: X is a PLUS that contains a constant, check that the constant is a
4275: legitimate operand and that we are supposed to be able to load
4276: it into the register.
4277:
4278: If not, force the constant into memory and reload the MEM instead.
4279:
4280: MODE is the mode to use, in case X is an integer constant.
4281:
4282: NEEDED_FOR says which operand this reload is needed for.
4283:
4284: IND_LEVELS says how many levels of indirect addressing this machine
4285: supports. */
4286:
4287: static void
4288: find_reloads_address_part (x, loc, class, mode, needed_for, ind_levels)
4289: rtx x;
4290: rtx *loc;
4291: enum reg_class class;
4292: enum machine_mode mode;
4293: rtx needed_for;
4294: int ind_levels;
4295: {
4296: if (CONSTANT_P (x)
4297: && (! LEGITIMATE_CONSTANT_P (x)
4298: || PREFERRED_RELOAD_CLASS (x, class) == NO_REGS))
4299: {
4300: rtx tem = x = force_const_mem (mode, x);
4301: find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0),
4302: needed_for, ind_levels);
4303: }
4304:
4305: else if (GET_CODE (x) == PLUS
4306: && CONSTANT_P (XEXP (x, 1))
4307: && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1))
4308: || PREFERRED_RELOAD_CLASS (XEXP (x, 1), class) == NO_REGS))
4309: {
4310: rtx tem = force_const_mem (GET_MODE (x), XEXP (x, 1));
4311:
4312: x = gen_rtx (PLUS, GET_MODE (x), XEXP (x, 0), tem);
4313: find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0),
4314: needed_for, ind_levels);
4315: }
4316:
1.1.1.4 ! root 4317: push_reload (x, NULL_RTX, loc, NULL_PTR, class,
! 4318: mode, VOIDmode, 0, 0, needed_for);
1.1 root 4319: }
4320:
4321: /* Substitute into X the registers into which we have reloaded
4322: the things that need reloading. The array `replacements'
4323: says contains the locations of all pointers that must be changed
4324: and says what to replace them with.
4325:
4326: Return the rtx that X translates into; usually X, but modified. */
4327:
4328: void
4329: subst_reloads ()
4330: {
4331: register int i;
4332:
4333: for (i = 0; i < n_replacements; i++)
4334: {
4335: register struct replacement *r = &replacements[i];
4336: register rtx reloadreg = reload_reg_rtx[r->what];
4337: if (reloadreg)
4338: {
4339: /* Encapsulate RELOADREG so its machine mode matches what
4340: used to be there. */
4341: if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode)
4342: reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg));
4343:
4344: /* If we are putting this into a SUBREG and RELOADREG is a
4345: SUBREG, we would be making nested SUBREGs, so we have to fix
4346: this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */
4347:
4348: if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG)
4349: {
4350: if (GET_MODE (*r->subreg_loc)
4351: == GET_MODE (SUBREG_REG (reloadreg)))
4352: *r->subreg_loc = SUBREG_REG (reloadreg);
4353: else
4354: {
4355: *r->where = SUBREG_REG (reloadreg);
4356: SUBREG_WORD (*r->subreg_loc) += SUBREG_WORD (reloadreg);
4357: }
4358: }
4359: else
4360: *r->where = reloadreg;
4361: }
4362: /* If reload got no reg and isn't optional, something's wrong. */
4363: else if (! reload_optional[r->what])
4364: abort ();
4365: }
4366: }
4367:
4368: /* Make a copy of any replacements being done into X and move those copies
4369: to locations in Y, a copy of X. We only look at the highest level of
4370: the RTL. */
4371:
4372: void
4373: copy_replacements (x, y)
4374: rtx x;
4375: rtx y;
4376: {
4377: int i, j;
4378: enum rtx_code code = GET_CODE (x);
4379: char *fmt = GET_RTX_FORMAT (code);
4380: struct replacement *r;
4381:
4382: /* We can't support X being a SUBREG because we might then need to know its
4383: location if something inside it was replaced. */
4384: if (code == SUBREG)
4385: abort ();
4386:
4387: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4388: if (fmt[i] == 'e')
4389: for (j = 0; j < n_replacements; j++)
4390: {
4391: if (replacements[j].subreg_loc == &XEXP (x, i))
4392: {
4393: r = &replacements[n_replacements++];
4394: r->where = replacements[j].where;
4395: r->subreg_loc = &XEXP (y, i);
4396: r->what = replacements[j].what;
4397: r->mode = replacements[j].mode;
4398: }
4399: else if (replacements[j].where == &XEXP (x, i))
4400: {
4401: r = &replacements[n_replacements++];
4402: r->where = &XEXP (y, i);
4403: r->subreg_loc = 0;
4404: r->what = replacements[j].what;
4405: r->mode = replacements[j].mode;
4406: }
4407: }
4408: }
4409:
1.1.1.3 root 4410: /* If LOC was scheduled to be replaced by something, return the replacement.
4411: Otherwise, return *LOC. */
4412:
4413: rtx
4414: find_replacement (loc)
4415: rtx *loc;
4416: {
4417: struct replacement *r;
4418:
4419: for (r = &replacements[0]; r < &replacements[n_replacements]; r++)
4420: {
4421: rtx reloadreg = reload_reg_rtx[r->what];
4422:
4423: if (reloadreg && r->where == loc)
4424: {
4425: if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode)
4426: reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg));
4427:
4428: return reloadreg;
4429: }
4430: else if (reloadreg && r->subreg_loc == loc)
4431: {
4432: /* RELOADREG must be either a REG or a SUBREG.
4433:
4434: ??? Is it actually still ever a SUBREG? If so, why? */
4435:
4436: if (GET_CODE (reloadreg) == REG)
4437: return gen_rtx (REG, GET_MODE (*loc),
4438: REGNO (reloadreg) + SUBREG_WORD (*loc));
4439: else if (GET_MODE (reloadreg) == GET_MODE (*loc))
4440: return reloadreg;
4441: else
4442: return gen_rtx (SUBREG, GET_MODE (*loc), SUBREG_REG (reloadreg),
4443: SUBREG_WORD (reloadreg) + SUBREG_WORD (*loc));
4444: }
4445: }
4446:
4447: return *loc;
4448: }
4449:
1.1 root 4450: /* Return nonzero if register in range [REGNO, ENDREGNO)
4451: appears either explicitly or implicitly in X
4452: other than being stored into.
4453:
4454: References contained within the substructure at LOC do not count.
4455: LOC may be zero, meaning don't ignore anything.
4456:
4457: This is similar to refers_to_regno_p in rtlanal.c except that we
4458: look at equivalences for pseudos that didn't get hard registers. */
4459:
4460: int
4461: refers_to_regno_for_reload_p (regno, endregno, x, loc)
4462: int regno, endregno;
4463: rtx x;
4464: rtx *loc;
4465: {
4466: register int i;
4467: register RTX_CODE code;
4468: register char *fmt;
4469:
4470: if (x == 0)
4471: return 0;
4472:
4473: repeat:
4474: code = GET_CODE (x);
4475:
4476: switch (code)
4477: {
4478: case REG:
4479: i = REGNO (x);
4480:
1.1.1.3 root 4481: /* If this is a pseudo, a hard register must not have been allocated.
4482: X must therefore either be a constant or be in memory. */
4483: if (i >= FIRST_PSEUDO_REGISTER)
4484: {
4485: if (reg_equiv_memory_loc[i])
4486: return refers_to_regno_for_reload_p (regno, endregno,
1.1.1.4 ! root 4487: reg_equiv_memory_loc[i],
! 4488: NULL_PTR);
1.1.1.3 root 4489:
4490: if (reg_equiv_constant[i])
4491: return 0;
4492:
4493: abort ();
4494: }
1.1 root 4495:
4496: return (endregno > i
4497: && regno < i + (i < FIRST_PSEUDO_REGISTER
4498: ? HARD_REGNO_NREGS (i, GET_MODE (x))
4499: : 1));
4500:
4501: case SUBREG:
4502: /* If this is a SUBREG of a hard reg, we can see exactly which
4503: registers are being modified. Otherwise, handle normally. */
4504: if (GET_CODE (SUBREG_REG (x)) == REG
4505: && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
4506: {
4507: int inner_regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x);
4508: int inner_endregno
4509: = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER
4510: ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
4511:
4512: return endregno > inner_regno && regno < inner_endregno;
4513: }
4514: break;
4515:
4516: case CLOBBER:
4517: case SET:
4518: if (&SET_DEST (x) != loc
4519: /* Note setting a SUBREG counts as referring to the REG it is in for
4520: a pseudo but not for hard registers since we can
4521: treat each word individually. */
4522: && ((GET_CODE (SET_DEST (x)) == SUBREG
4523: && loc != &SUBREG_REG (SET_DEST (x))
4524: && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
4525: && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
4526: && refers_to_regno_for_reload_p (regno, endregno,
4527: SUBREG_REG (SET_DEST (x)),
4528: loc))
4529: || (GET_CODE (SET_DEST (x)) != REG
4530: && refers_to_regno_for_reload_p (regno, endregno,
4531: SET_DEST (x), loc))))
4532: return 1;
4533:
4534: if (code == CLOBBER || loc == &SET_SRC (x))
4535: return 0;
4536: x = SET_SRC (x);
4537: goto repeat;
4538: }
4539:
4540: /* X does not match, so try its subexpressions. */
4541:
4542: fmt = GET_RTX_FORMAT (code);
4543: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4544: {
4545: if (fmt[i] == 'e' && loc != &XEXP (x, i))
4546: {
4547: if (i == 0)
4548: {
4549: x = XEXP (x, 0);
4550: goto repeat;
4551: }
4552: else
4553: if (refers_to_regno_for_reload_p (regno, endregno,
4554: XEXP (x, i), loc))
4555: return 1;
4556: }
4557: else if (fmt[i] == 'E')
4558: {
4559: register int j;
4560: for (j = XVECLEN (x, i) - 1; j >=0; j--)
4561: if (loc != &XVECEXP (x, i, j)
4562: && refers_to_regno_for_reload_p (regno, endregno,
4563: XVECEXP (x, i, j), loc))
4564: return 1;
4565: }
4566: }
4567: return 0;
4568: }
1.1.1.3 root 4569:
4570: /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
4571: we check if any register number in X conflicts with the relevant register
4572: numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
4573: contains a MEM (we don't bother checking for memory addresses that can't
4574: conflict because we expect this to be a rare case.
4575:
4576: This function is similar to reg_overlap_mention_p in rtlanal.c except
4577: that we look at equivalences for pseudos that didn't get hard registers. */
4578:
4579: int
4580: reg_overlap_mentioned_for_reload_p (x, in)
4581: rtx x, in;
4582: {
4583: int regno, endregno;
4584:
4585: if (GET_CODE (x) == SUBREG)
4586: {
4587: regno = REGNO (SUBREG_REG (x));
4588: if (regno < FIRST_PSEUDO_REGISTER)
4589: regno += SUBREG_WORD (x);
4590: }
4591: else if (GET_CODE (x) == REG)
4592: {
4593: regno = REGNO (x);
4594:
4595: /* If this is a pseudo, it must not have been assigned a hard register.
4596: Therefore, it must either be in memory or be a constant. */
4597:
4598: if (regno >= FIRST_PSEUDO_REGISTER)
4599: {
4600: if (reg_equiv_memory_loc[regno])
4601: return refers_to_mem_for_reload_p (in);
4602: else if (reg_equiv_constant[regno])
4603: return 0;
4604: abort ();
4605: }
4606: }
4607: else if (CONSTANT_P (x))
4608: return 0;
4609: else if (GET_CODE (x) == MEM)
4610: return refers_to_mem_for_reload_p (in);
4611: else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC
4612: || GET_CODE (x) == CC0)
4613: return reg_mentioned_p (x, in);
4614: else
4615: abort ();
4616:
4617: endregno = regno + (regno < FIRST_PSEUDO_REGISTER
4618: ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
4619:
1.1.1.4 ! root 4620: return refers_to_regno_for_reload_p (regno, endregno, in, NULL_PTR);
1.1.1.3 root 4621: }
4622:
4623: /* Return nonzero if anything in X contains a MEM. Look also for pseudo
4624: registers. */
4625:
4626: int
4627: refers_to_mem_for_reload_p (x)
4628: rtx x;
4629: {
4630: char *fmt;
4631: int i;
4632:
4633: if (GET_CODE (x) == MEM)
4634: return 1;
4635:
4636: if (GET_CODE (x) == REG)
4637: return (REGNO (x) >= FIRST_PSEUDO_REGISTER
4638: && reg_equiv_memory_loc[REGNO (x)]);
4639:
4640: fmt = GET_RTX_FORMAT (GET_CODE (x));
4641: for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4642: if (fmt[i] == 'e'
4643: && (GET_CODE (XEXP (x, i)) == MEM
4644: || refers_to_mem_for_reload_p (XEXP (x, i))))
4645: return 1;
4646:
4647: return 0;
4648: }
1.1 root 4649:
4650: #if 0
4651:
4652: /* [[This function is currently obsolete, now that volatility
4653: is represented by a special bit `volatil' so VOLATILE is never used;
4654: and UNCHANGING has never been brought into use.]]
4655:
4656: Alter X by eliminating all VOLATILE and UNCHANGING expressions.
4657: Each of them is replaced by its operand.
4658: Thus, (PLUS (VOLATILE (MEM (REG 5))) (CONST_INT 4))
4659: becomes (PLUS (MEM (REG 5)) (CONST_INT 4)).
4660:
4661: If X is itself a VOLATILE expression,
4662: we return the expression that should replace it
4663: but we do not modify X. */
4664:
4665: static rtx
4666: forget_volatility (x)
4667: register rtx x;
4668: {
4669: enum rtx_code code = GET_CODE (x);
4670: register char *fmt;
4671: register int i;
4672: register rtx value = 0;
4673:
4674: switch (code)
4675: {
4676: case LABEL_REF:
4677: case SYMBOL_REF:
4678: case CONST_INT:
4679: case CONST_DOUBLE:
4680: case CONST:
4681: case REG:
4682: case CC0:
4683: case PC:
4684: return x;
4685:
4686: case VOLATILE:
4687: case UNCHANGING:
4688: return XEXP (x, 0);
4689: }
4690:
4691: fmt = GET_RTX_FORMAT (code);
4692: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4693: {
4694: if (fmt[i] == 'e')
4695: XEXP (x, i) = forget_volatility (XEXP (x, i));
4696: if (fmt[i] == 'E')
4697: {
4698: register int j;
4699: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4700: XVECEXP (x, i, j) = forget_volatility (XVECEXP (x, i, j));
4701: }
4702: }
4703:
4704: return x;
4705: }
4706:
4707: #endif
4708:
4709: /* Check the insns before INSN to see if there is a suitable register
4710: containing the same value as GOAL.
4711: If OTHER is -1, look for a register in class CLASS.
4712: Otherwise, just see if register number OTHER shares GOAL's value.
4713:
4714: Return an rtx for the register found, or zero if none is found.
4715:
4716: If RELOAD_REG_P is (short *)1,
4717: we reject any hard reg that appears in reload_reg_rtx
4718: because such a hard reg is also needed coming into this insn.
4719:
4720: If RELOAD_REG_P is any other nonzero value,
4721: it is a vector indexed by hard reg number
4722: and we reject any hard reg whose element in the vector is nonnegative
4723: as well as any that appears in reload_reg_rtx.
4724:
4725: If GOAL is zero, then GOALREG is a register number; we look
4726: for an equivalent for that register.
4727:
4728: MODE is the machine mode of the value we want an equivalence for.
4729: If GOAL is nonzero and not VOIDmode, then it must have mode MODE.
4730:
4731: This function is used by jump.c as well as in the reload pass.
4732:
4733: If GOAL is the sum of the stack pointer and a constant, we treat it
4734: as if it were a constant except that sp is required to be unchanging. */
4735:
4736: rtx
4737: find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode)
4738: register rtx goal;
4739: rtx insn;
4740: enum reg_class class;
4741: register int other;
4742: short *reload_reg_p;
4743: int goalreg;
4744: enum machine_mode mode;
4745: {
4746: register rtx p = insn;
4747: rtx valtry, value, where;
4748: register rtx pat;
4749: register int regno = -1;
4750: int valueno;
4751: int goal_mem = 0;
4752: int goal_const = 0;
4753: int goal_mem_addr_varies = 0;
4754: int need_stable_sp = 0;
4755: int nregs;
4756: int valuenregs;
4757:
4758: if (goal == 0)
4759: regno = goalreg;
4760: else if (GET_CODE (goal) == REG)
4761: regno = REGNO (goal);
4762: else if (GET_CODE (goal) == MEM)
4763: {
4764: enum rtx_code code = GET_CODE (XEXP (goal, 0));
4765: if (MEM_VOLATILE_P (goal))
4766: return 0;
4767: if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT)
4768: return 0;
4769: /* An address with side effects must be reexecuted. */
4770: switch (code)
4771: {
4772: case POST_INC:
4773: case PRE_INC:
4774: case POST_DEC:
4775: case PRE_DEC:
4776: return 0;
4777: }
4778: goal_mem = 1;
4779: }
4780: else if (CONSTANT_P (goal))
4781: goal_const = 1;
4782: else if (GET_CODE (goal) == PLUS
4783: && XEXP (goal, 0) == stack_pointer_rtx
4784: && CONSTANT_P (XEXP (goal, 1)))
4785: goal_const = need_stable_sp = 1;
4786: else
4787: return 0;
4788:
4789: /* On some machines, certain regs must always be rejected
4790: because they don't behave the way ordinary registers do. */
4791:
4792: #ifdef OVERLAPPING_REGNO_P
4793: if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4794: && OVERLAPPING_REGNO_P (regno))
4795: return 0;
4796: #endif
4797:
4798: /* Scan insns back from INSN, looking for one that copies
4799: a value into or out of GOAL.
4800: Stop and give up if we reach a label. */
4801:
4802: while (1)
4803: {
4804: p = PREV_INSN (p);
4805: if (p == 0 || GET_CODE (p) == CODE_LABEL)
4806: return 0;
4807: if (GET_CODE (p) == INSN
4808: /* If we don't want spill regs ... */
4809: && (! (reload_reg_p != 0 && reload_reg_p != (short *)1)
4810: /* ... then ignore insns introduced by reload; they aren't useful
4811: and can cause results in reload_as_needed to be different
4812: from what they were when calculating the need for spills.
4813: If we notice an input-reload insn here, we will reject it below,
4814: but it might hide a usable equivalent. That makes bad code.
4815: It may even abort: perhaps no reg was spilled for this insn
4816: because it was assumed we would find that equivalent. */
4817: || INSN_UID (p) < reload_first_uid))
4818: {
1.1.1.3 root 4819: rtx tem;
1.1 root 4820: pat = single_set (p);
4821: /* First check for something that sets some reg equal to GOAL. */
4822: if (pat != 0
4823: && ((regno >= 0
4824: && true_regnum (SET_SRC (pat)) == regno
4825: && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
4826: ||
4827: (regno >= 0
4828: && true_regnum (SET_DEST (pat)) == regno
4829: && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0)
4830: ||
4831: (goal_const && rtx_equal_p (SET_SRC (pat), goal)
4832: && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
4833: || (goal_mem
4834: && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0
4835: && rtx_renumbered_equal_p (goal, SET_SRC (pat)))
4836: || (goal_mem
4837: && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0
1.1.1.3 root 4838: && rtx_renumbered_equal_p (goal, SET_DEST (pat)))
4839: /* If we are looking for a constant,
4840: and something equivalent to that constant was copied
4841: into a reg, we can use that reg. */
1.1.1.4 ! root 4842: || (goal_const && (tem = find_reg_note (p, REG_EQUIV,
! 4843: NULL_RTX))
1.1.1.3 root 4844: && rtx_equal_p (XEXP (tem, 0), goal)
4845: && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0)
1.1.1.4 ! root 4846: || (goal_const && (tem = find_reg_note (p, REG_EQUIV,
! 4847: NULL_RTX))
1.1.1.3 root 4848: && GET_CODE (SET_DEST (pat)) == REG
4849: && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE
4850: && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT
4851: && GET_CODE (goal) == CONST_INT
4852: && INTVAL (goal) == CONST_DOUBLE_LOW (XEXP (tem, 0))
4853: && (valtry = operand_subword (SET_DEST (pat), 0, 0,
4854: VOIDmode))
4855: && (valueno = true_regnum (valtry)) >= 0)
1.1.1.4 ! root 4856: || (goal_const && (tem = find_reg_note (p, REG_EQUIV,
! 4857: NULL_RTX))
1.1.1.3 root 4858: && GET_CODE (SET_DEST (pat)) == REG
4859: && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE
4860: && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT
4861: && GET_CODE (goal) == CONST_INT
4862: && INTVAL (goal) == CONST_DOUBLE_HIGH (XEXP (tem, 0))
4863: && (valtry
4864: = operand_subword (SET_DEST (pat), 1, 0, VOIDmode))
4865: && (valueno = true_regnum (valtry)) >= 0)))
1.1 root 4866: if (other >= 0
4867: ? valueno == other
4868: : ((unsigned) valueno < FIRST_PSEUDO_REGISTER
4869: && TEST_HARD_REG_BIT (reg_class_contents[(int) class],
4870: valueno)))
4871: {
4872: value = valtry;
4873: where = p;
4874: break;
4875: }
4876: }
4877: }
4878:
4879: /* We found a previous insn copying GOAL into a suitable other reg VALUE
4880: (or copying VALUE into GOAL, if GOAL is also a register).
4881: Now verify that VALUE is really valid. */
4882:
4883: /* VALUENO is the register number of VALUE; a hard register. */
4884:
4885: /* Don't try to re-use something that is killed in this insn. We want
4886: to be able to trust REG_UNUSED notes. */
4887: if (find_reg_note (where, REG_UNUSED, value))
4888: return 0;
4889:
4890: /* If we propose to get the value from the stack pointer or if GOAL is
4891: a MEM based on the stack pointer, we need a stable SP. */
4892: if (valueno == STACK_POINTER_REGNUM
1.1.1.3 root 4893: || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx,
4894: goal)))
1.1 root 4895: need_stable_sp = 1;
4896:
4897: /* Reject VALUE if the copy-insn moved the wrong sort of datum. */
4898: if (GET_MODE (value) != mode)
4899: return 0;
4900:
4901: /* Reject VALUE if it was loaded from GOAL
4902: and is also a register that appears in the address of GOAL. */
4903:
4904: if (goal_mem && value == SET_DEST (PATTERN (where))
1.1.1.3 root 4905: && refers_to_regno_for_reload_p (valueno,
4906: (valueno
4907: + HARD_REGNO_NREGS (valueno, mode)),
1.1.1.4 ! root 4908: goal, NULL_PTR))
1.1 root 4909: return 0;
4910:
4911: /* Reject registers that overlap GOAL. */
4912:
4913: if (!goal_mem && !goal_const
4914: && regno + HARD_REGNO_NREGS (regno, mode) > valueno
4915: && regno < valueno + HARD_REGNO_NREGS (valueno, mode))
4916: return 0;
4917:
4918: /* Reject VALUE if it is one of the regs reserved for reloads.
4919: Reload1 knows how to reuse them anyway, and it would get
4920: confused if we allocated one without its knowledge.
4921: (Now that insns introduced by reload are ignored above,
4922: this case shouldn't happen, but I'm not positive.) */
4923:
4924: if (reload_reg_p != 0 && reload_reg_p != (short *)1
4925: && reload_reg_p[valueno] >= 0)
4926: return 0;
4927:
4928: /* On some machines, certain regs must always be rejected
4929: because they don't behave the way ordinary registers do. */
4930:
4931: #ifdef OVERLAPPING_REGNO_P
4932: if (OVERLAPPING_REGNO_P (valueno))
4933: return 0;
4934: #endif
4935:
4936: nregs = HARD_REGNO_NREGS (regno, mode);
4937: valuenregs = HARD_REGNO_NREGS (valueno, mode);
4938:
4939: /* Reject VALUE if it is a register being used for an input reload
4940: even if it is not one of those reserved. */
4941:
4942: if (reload_reg_p != 0)
4943: {
4944: int i;
4945: for (i = 0; i < n_reloads; i++)
4946: if (reload_reg_rtx[i] != 0 && reload_in[i])
4947: {
4948: int regno1 = REGNO (reload_reg_rtx[i]);
4949: int nregs1 = HARD_REGNO_NREGS (regno1,
4950: GET_MODE (reload_reg_rtx[i]));
4951: if (regno1 < valueno + valuenregs
4952: && regno1 + nregs1 > valueno)
4953: return 0;
4954: }
4955: }
4956:
4957: if (goal_mem)
4958: goal_mem_addr_varies = rtx_addr_varies_p (goal);
4959:
4960: /* Now verify that the values of GOAL and VALUE remain unaltered
4961: until INSN is reached. */
4962:
4963: p = insn;
4964: while (1)
4965: {
4966: p = PREV_INSN (p);
4967: if (p == where)
4968: return value;
4969:
4970: /* Don't trust the conversion past a function call
4971: if either of the two is in a call-clobbered register, or memory. */
4972: if (GET_CODE (p) == CALL_INSN
4973: && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4974: && call_used_regs[regno])
4975: ||
4976: (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER
4977: && call_used_regs[valueno])
4978: ||
4979: goal_mem
4980: || need_stable_sp))
4981: return 0;
4982:
4983: #ifdef INSN_CLOBBERS_REGNO_P
4984: if ((valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER
4985: && INSN_CLOBBERS_REGNO_P (p, valueno))
4986: || (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
4987: && INSN_CLOBBERS_REGNO_P (p, regno)))
4988: return 0;
4989: #endif
4990:
4991: if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
4992: {
4993: /* If this insn P stores in either GOAL or VALUE, return 0.
4994: If GOAL is a memory ref and this insn writes memory, return 0.
4995: If GOAL is a memory ref and its address is not constant,
4996: and this insn P changes a register used in GOAL, return 0. */
4997:
4998: pat = PATTERN (p);
4999: if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
5000: {
5001: register rtx dest = SET_DEST (pat);
5002: while (GET_CODE (dest) == SUBREG
5003: || GET_CODE (dest) == ZERO_EXTRACT
5004: || GET_CODE (dest) == SIGN_EXTRACT
5005: || GET_CODE (dest) == STRICT_LOW_PART)
5006: dest = XEXP (dest, 0);
5007: if (GET_CODE (dest) == REG)
5008: {
5009: register int xregno = REGNO (dest);
5010: int xnregs;
5011: if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
5012: xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
5013: else
5014: xnregs = 1;
5015: if (xregno < regno + nregs && xregno + xnregs > regno)
5016: return 0;
5017: if (xregno < valueno + valuenregs
5018: && xregno + xnregs > valueno)
5019: return 0;
5020: if (goal_mem_addr_varies
1.1.1.3 root 5021: && reg_overlap_mentioned_for_reload_p (dest, goal))
1.1 root 5022: return 0;
5023: }
5024: else if (goal_mem && GET_CODE (dest) == MEM
5025: && ! push_operand (dest, GET_MODE (dest)))
5026: return 0;
5027: else if (need_stable_sp && push_operand (dest, GET_MODE (dest)))
5028: return 0;
5029: }
5030: else if (GET_CODE (pat) == PARALLEL)
5031: {
5032: register int i;
5033: for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
5034: {
5035: register rtx v1 = XVECEXP (pat, 0, i);
5036: if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER)
5037: {
5038: register rtx dest = SET_DEST (v1);
5039: while (GET_CODE (dest) == SUBREG
5040: || GET_CODE (dest) == ZERO_EXTRACT
5041: || GET_CODE (dest) == SIGN_EXTRACT
5042: || GET_CODE (dest) == STRICT_LOW_PART)
5043: dest = XEXP (dest, 0);
5044: if (GET_CODE (dest) == REG)
5045: {
5046: register int xregno = REGNO (dest);
5047: int xnregs;
5048: if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
5049: xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
5050: else
5051: xnregs = 1;
5052: if (xregno < regno + nregs
5053: && xregno + xnregs > regno)
5054: return 0;
5055: if (xregno < valueno + valuenregs
5056: && xregno + xnregs > valueno)
5057: return 0;
5058: if (goal_mem_addr_varies
1.1.1.3 root 5059: && reg_overlap_mentioned_for_reload_p (dest,
5060: goal))
1.1 root 5061: return 0;
5062: }
5063: else if (goal_mem && GET_CODE (dest) == MEM
5064: && ! push_operand (dest, GET_MODE (dest)))
5065: return 0;
5066: else if (need_stable_sp
5067: && push_operand (dest, GET_MODE (dest)))
5068: return 0;
5069: }
5070: }
5071: }
5072:
5073: #ifdef AUTO_INC_DEC
5074: /* If this insn auto-increments or auto-decrements
5075: either regno or valueno, return 0 now.
5076: If GOAL is a memory ref and its address is not constant,
5077: and this insn P increments a register used in GOAL, return 0. */
5078: {
5079: register rtx link;
5080:
5081: for (link = REG_NOTES (p); link; link = XEXP (link, 1))
5082: if (REG_NOTE_KIND (link) == REG_INC
5083: && GET_CODE (XEXP (link, 0)) == REG)
5084: {
5085: register int incno = REGNO (XEXP (link, 0));
5086: if (incno < regno + nregs && incno >= regno)
5087: return 0;
5088: if (incno < valueno + valuenregs && incno >= valueno)
5089: return 0;
5090: if (goal_mem_addr_varies
1.1.1.3 root 5091: && reg_overlap_mentioned_for_reload_p (XEXP (link, 0),
5092: goal))
1.1 root 5093: return 0;
5094: }
5095: }
5096: #endif
5097: }
5098: }
5099: }
5100:
5101: /* Find a place where INCED appears in an increment or decrement operator
5102: within X, and return the amount INCED is incremented or decremented by.
5103: The value is always positive. */
5104:
5105: static int
5106: find_inc_amount (x, inced)
5107: rtx x, inced;
5108: {
5109: register enum rtx_code code = GET_CODE (x);
5110: register char *fmt;
5111: register int i;
5112:
5113: if (code == MEM)
5114: {
5115: register rtx addr = XEXP (x, 0);
5116: if ((GET_CODE (addr) == PRE_DEC
5117: || GET_CODE (addr) == POST_DEC
5118: || GET_CODE (addr) == PRE_INC
5119: || GET_CODE (addr) == POST_INC)
5120: && XEXP (addr, 0) == inced)
5121: return GET_MODE_SIZE (GET_MODE (x));
5122: }
5123:
5124: fmt = GET_RTX_FORMAT (code);
5125: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5126: {
5127: if (fmt[i] == 'e')
5128: {
5129: register int tem = find_inc_amount (XEXP (x, i), inced);
5130: if (tem != 0)
5131: return tem;
5132: }
5133: if (fmt[i] == 'E')
5134: {
5135: register int j;
5136: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5137: {
5138: register int tem = find_inc_amount (XVECEXP (x, i, j), inced);
5139: if (tem != 0)
5140: return tem;
5141: }
5142: }
5143: }
5144:
5145: return 0;
5146: }
5147:
5148: /* Return 1 if register REGNO is the subject of a clobber in insn INSN. */
5149:
5150: int
5151: regno_clobbered_p (regno, insn)
5152: int regno;
5153: rtx insn;
5154: {
5155: if (GET_CODE (PATTERN (insn)) == CLOBBER
5156: && GET_CODE (XEXP (PATTERN (insn), 0)) == REG)
5157: return REGNO (XEXP (PATTERN (insn), 0)) == regno;
5158:
5159: if (GET_CODE (PATTERN (insn)) == PARALLEL)
5160: {
5161: int i = XVECLEN (PATTERN (insn), 0) - 1;
5162:
5163: for (; i >= 0; i--)
5164: {
5165: rtx elt = XVECEXP (PATTERN (insn), 0, i);
5166: if (GET_CODE (elt) == CLOBBER && GET_CODE (XEXP (elt, 0)) == REG
5167: && REGNO (XEXP (elt, 0)) == regno)
5168: return 1;
5169: }
5170: }
5171:
5172: return 0;
5173: }
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