![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to reload1.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GCC 2.x] / gcc|
Return to reload1.c CVS log | Up to [GCC 2.x] / gcc |
1.1 root 1: /* Reload pseudo regs into hard regs for insns that require hard regs.
2: Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: #include "config.h"
22: #include "rtl.h"
23: #include "obstack.h"
24: #include "insn-config.h"
25: #include "insn-flags.h"
26: #include "insn-codes.h"
27: #include "flags.h"
28: #include "expr.h"
29: #include "regs.h"
30: #include "hard-reg-set.h"
31: #include "reload.h"
32: #include "recog.h"
33: #include "basic-block.h"
34: #include "output.h"
35: #include <stdio.h>
36:
37: /* This file contains the reload pass of the compiler, which is
38: run after register allocation has been done. It checks that
39: each insn is valid (operands required to be in registers really
40: are in registers of the proper class) and fixes up invalid ones
41: by copying values temporarily into registers for the insns
42: that need them.
43:
44: The results of register allocation are described by the vector
45: reg_renumber; the insns still contain pseudo regs, but reg_renumber
46: can be used to find which hard reg, if any, a pseudo reg is in.
47:
48: The technique we always use is to free up a few hard regs that are
49: called ``reload regs'', and for each place where a pseudo reg
50: must be in a hard reg, copy it temporarily into one of the reload regs.
51:
52: All the pseudos that were formerly allocated to the hard regs that
53: are now in use as reload regs must be ``spilled''. This means
54: that they go to other hard regs, or to stack slots if no other
55: available hard regs can be found. Spilling can invalidate more
56: insns, requiring additional need for reloads, so we must keep checking
57: until the process stabilizes.
58:
59: For machines with different classes of registers, we must keep track
60: of the register class needed for each reload, and make sure that
61: we allocate enough reload registers of each class.
62:
63: The file reload.c contains the code that checks one insn for
64: validity and reports the reloads that it needs. This file
65: is in charge of scanning the entire rtl code, accumulating the
66: reload needs, spilling, assigning reload registers to use for
67: fixing up each insn, and generating the new insns to copy values
68: into the reload registers. */
69:
70: /* During reload_as_needed, element N contains a REG rtx for the hard reg
71: into which pseudo reg N has been reloaded (perhaps for a previous insn). */
72: static rtx *reg_last_reload_reg;
73:
74: /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
75: for an output reload that stores into reg N. */
76: static char *reg_has_output_reload;
77:
78: /* Indicates which hard regs are reload-registers for an output reload
79: in the current insn. */
80: static HARD_REG_SET reg_is_output_reload;
81:
82: /* Element N is the constant value to which pseudo reg N is equivalent,
83: or zero if pseudo reg N is not equivalent to a constant.
84: find_reloads looks at this in order to replace pseudo reg N
85: with the constant it stands for. */
86: rtx *reg_equiv_constant;
87:
88: /* Element N is a memory location to which pseudo reg N is equivalent,
89: prior to any register elimination (such as frame pointer to stack
90: pointer). Depending on whether or not it is a valid address, this value
91: is transferred to either reg_equiv_address or reg_equiv_mem. */
92: static rtx *reg_equiv_memory_loc;
93:
94: /* Element N is the address of stack slot to which pseudo reg N is equivalent.
95: This is used when the address is not valid as a memory address
96: (because its displacement is too big for the machine.) */
97: rtx *reg_equiv_address;
98:
99: /* Element N is the memory slot to which pseudo reg N is equivalent,
100: or zero if pseudo reg N is not equivalent to a memory slot. */
101: rtx *reg_equiv_mem;
102:
103: /* Widest width in which each pseudo reg is referred to (via subreg). */
104: static int *reg_max_ref_width;
105:
106: /* Element N is the insn that initialized reg N from its equivalent
107: constant or memory slot. */
108: static rtx *reg_equiv_init;
109:
110: /* During reload_as_needed, element N contains the last pseudo regno
111: reloaded into the Nth reload register. This vector is in parallel
112: with spill_regs. If that pseudo reg occupied more than one register,
113: reg_reloaded_contents points to that pseudo for each spill register in
114: use; all of these must remain set for an inheritance to occur. */
115: static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
116:
117: /* During reload_as_needed, element N contains the insn for which
118: the Nth reload register was last used. This vector is in parallel
119: with spill_regs, and its contents are significant only when
120: reg_reloaded_contents is significant. */
121: static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
122:
123: /* Number of spill-regs so far; number of valid elements of spill_regs. */
124: static int n_spills;
125:
126: /* In parallel with spill_regs, contains REG rtx's for those regs.
127: Holds the last rtx used for any given reg, or 0 if it has never
128: been used for spilling yet. This rtx is reused, provided it has
129: the proper mode. */
130: static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
131:
132: /* In parallel with spill_regs, contains nonzero for a spill reg
133: that was stored after the last time it was used.
134: The precise value is the insn generated to do the store. */
135: static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
136:
137: /* This table is the inverse mapping of spill_regs:
138: indexed by hard reg number,
139: it contains the position of that reg in spill_regs,
140: or -1 for something that is not in spill_regs. */
141: static short spill_reg_order[FIRST_PSEUDO_REGISTER];
142:
143: /* This reg set indicates registers that may not be used for retrying global
144: allocation. The registers that may not be used include all spill registers
145: and the frame pointer (if we are using one). */
146: HARD_REG_SET forbidden_regs;
147:
148: /* This reg set indicates registers that are not good for spill registers.
149: They will not be used to complete groups of spill registers. This includes
150: all fixed registers, registers that may be eliminated, and registers
151: explicitly used in the rtl.
152:
153: (spill_reg_order prevents these registers from being used to start a
154: group.) */
155: static HARD_REG_SET bad_spill_regs;
156:
157: /* Describes order of use of registers for reloading
158: of spilled pseudo-registers. `spills' is the number of
159: elements that are actually valid; new ones are added at the end. */
160: static short spill_regs[FIRST_PSEUDO_REGISTER];
161:
162: /* Describes order of preference for putting regs into spill_regs.
163: Contains the numbers of all the hard regs, in order most preferred first.
164: This order is different for each function.
165: It is set up by order_regs_for_reload.
166: Empty elements at the end contain -1. */
167: static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
168:
169: /* 1 for a hard register that appears explicitly in the rtl
170: (for example, function value registers, special registers
171: used by insns, structure value pointer registers). */
172: static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
173:
174: /* Indicates if a register was counted against the need for
175: groups. 0 means it can count against max_nongroup instead. */
176: static HARD_REG_SET counted_for_groups;
177:
178: /* Indicates if a register was counted against the need for
179: non-groups. 0 means it can become part of a new group.
180: During choose_reload_regs, 1 here means don't use this reg
181: as part of a group, even if it seems to be otherwise ok. */
182: static HARD_REG_SET counted_for_nongroups;
183:
184: /* Nonzero if indirect addressing is supported on the machine; this means
185: that spilling (REG n) does not require reloading it into a register in
186: order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
187: value indicates the level of indirect addressing supported, e.g., two
188: means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
189: a hard register. */
190:
191: static char spill_indirect_levels;
192:
193: /* Nonzero if indirect addressing is supported when the innermost MEM is
194: of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
195: which these are valid is the same as spill_indirect_levels, above. */
196:
197: char indirect_symref_ok;
198:
199: /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
200:
201: char double_reg_address_ok;
202:
203: /* Record the stack slot for each spilled hard register. */
204:
205: static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
206:
207: /* Width allocated so far for that stack slot. */
208:
209: static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
210:
211: /* Indexed by register class and basic block number, nonzero if there is
212: any need for a spill register of that class in that basic block.
213: The pointer is 0 if we did stupid allocation and don't know
214: the structure of basic blocks. */
215:
216: char *basic_block_needs[N_REG_CLASSES];
217:
218: /* First uid used by insns created by reload in this function.
219: Used in find_equiv_reg. */
220: int reload_first_uid;
221:
222: /* Flag set by local-alloc or global-alloc if anything is live in
223: a call-clobbered reg across calls. */
224:
225: int caller_save_needed;
226:
227: /* Set to 1 while reload_as_needed is operating.
228: Required by some machines to handle any generated moves differently. */
229:
230: int reload_in_progress = 0;
231:
232: /* These arrays record the insn_code of insns that may be needed to
233: perform input and output reloads of special objects. They provide a
234: place to pass a scratch register. */
235:
236: enum insn_code reload_in_optab[NUM_MACHINE_MODES];
237: enum insn_code reload_out_optab[NUM_MACHINE_MODES];
238:
1.1.1.2 ! root 239: /* This obstack is used for allocation of rtl during register elimination.
1.1 root 240: The allocated storage can be freed once find_reloads has processed the
241: insn. */
242:
243: struct obstack reload_obstack;
244: char *reload_firstobj;
245:
246: #define obstack_chunk_alloc xmalloc
247: #define obstack_chunk_free free
248:
249: extern int xmalloc ();
250: extern void free ();
251:
252: /* List of labels that must never be deleted. */
253: extern rtx forced_labels;
254:
255: /* This structure is used to record information about register eliminations.
256: Each array entry describes one possible way of eliminating a register
257: in favor of another. If there is more than one way of eliminating a
258: particular register, the most preferred should be specified first. */
259:
260: static struct elim_table
261: {
262: int from; /* Register number to be eliminated. */
263: int to; /* Register number used as replacement. */
264: int initial_offset; /* Initial difference between values. */
265: int can_eliminate; /* Non-zero if this elimination can be done. */
266: int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
267: insns made by reload. */
268: int offset; /* Current offset between the two regs. */
269: int max_offset; /* Maximum offset between the two regs. */
270: int previous_offset; /* Offset at end of previous insn. */
271: int ref_outside_mem; /* "to" has been referenced outside a MEM. */
272: rtx from_rtx; /* REG rtx for the register to be eliminated.
273: We cannot simply compare the number since
274: we might then spuriously replace a hard
275: register corresponding to a pseudo
276: assigned to the reg to be eliminated. */
277: rtx to_rtx; /* REG rtx for the replacement. */
278: } reg_eliminate[] =
279:
280: /* If a set of eliminable registers was specified, define the table from it.
281: Otherwise, default to the normal case of the frame pointer being
282: replaced by the stack pointer. */
283:
284: #ifdef ELIMINABLE_REGS
285: ELIMINABLE_REGS;
286: #else
287: {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
288: #endif
289:
290: #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
291:
292: /* Record the number of pending eliminations that have an offset not equal
293: to their initial offset. If non-zero, we use a new copy of each
294: replacement result in any insns encountered. */
295: static int num_not_at_initial_offset;
296:
297: /* Count the number of registers that we may be able to eliminate. */
298: static int num_eliminable;
299:
300: /* For each label, we record the offset of each elimination. If we reach
301: a label by more than one path and an offset differs, we cannot do the
302: elimination. This information is indexed by the number of the label.
303: The first table is an array of flags that records whether we have yet
304: encountered a label and the second table is an array of arrays, one
305: entry in the latter array for each elimination. */
306:
307: static char *offsets_known_at;
308: static int (*offsets_at)[NUM_ELIMINABLE_REGS];
309:
310: /* Number of labels in the current function. */
311:
312: static int num_labels;
313:
314: void mark_home_live ();
315: static void count_possible_groups ();
316: static int possible_group_p ();
317: static void scan_paradoxical_subregs ();
318: static void reload_as_needed ();
319: static int modes_equiv_for_class_p ();
320: static void alter_reg ();
321: static void delete_dead_insn ();
322: static int new_spill_reg();
323: static void set_label_offsets ();
324: static int eliminate_regs_in_insn ();
325: static void mark_not_eliminable ();
326: static int spill_hard_reg ();
327: static void choose_reload_regs ();
328: static void emit_reload_insns ();
329: static void delete_output_reload ();
330: static void forget_old_reloads_1 ();
331: static void order_regs_for_reload ();
332: static rtx inc_for_reload ();
333: static int constraint_accepts_reg_p ();
334: static int count_occurrences ();
335:
336: extern void remove_death ();
337: extern rtx adj_offsettable_operand ();
338: extern rtx form_sum ();
339:
340: void
341: init_reload ()
342: {
343: register int i;
344:
345: /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
346: Set spill_indirect_levels to the number of levels such addressing is
347: permitted, zero if it is not permitted at all. */
348:
349: register rtx tem
350: = gen_rtx (MEM, Pmode,
351: gen_rtx (PLUS, Pmode,
352: gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
353: gen_rtx (CONST_INT, VOIDmode, 4)));
354: spill_indirect_levels = 0;
355:
356: while (memory_address_p (QImode, tem))
357: {
358: spill_indirect_levels++;
359: tem = gen_rtx (MEM, Pmode, tem);
360: }
361:
362: /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
363:
364: tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
365: indirect_symref_ok = memory_address_p (QImode, tem);
366:
367: /* See if reg+reg is a valid (and offsettable) address. */
368:
369: tem = gen_rtx (PLUS, Pmode,
370: gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM),
371: gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM));
372: /* This way, we make sure that reg+reg is an offsettable address. */
373: tem = plus_constant (tem, 4);
374:
375: double_reg_address_ok = memory_address_p (QImode, tem);
376:
377: /* Initialize obstack for our rtl allocation. */
378: gcc_obstack_init (&reload_obstack);
379: reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
380:
381: #ifdef HAVE_SECONDARY_RELOADS
382:
383: /* Initialize the optabs for doing special input and output reloads. */
384:
385: for (i = 0; i < NUM_MACHINE_MODES; i++)
386: reload_in_optab[i] = reload_out_optab[i] = CODE_FOR_nothing;
387:
388: #ifdef HAVE_reload_inqi
389: if (HAVE_reload_inqi)
390: reload_in_optab[(int) QImode] = CODE_FOR_reload_inqi;
391: #endif
392: #ifdef HAVE_reload_inhi
393: if (HAVE_reload_inhi)
394: reload_in_optab[(int) HImode] = CODE_FOR_reload_inhi;
395: #endif
396: #ifdef HAVE_reload_insi
397: if (HAVE_reload_insi)
398: reload_in_optab[(int) SImode] = CODE_FOR_reload_insi;
399: #endif
400: #ifdef HAVE_reload_indi
401: if (HAVE_reload_indi)
402: reload_in_optab[(int) DImode] = CODE_FOR_reload_indi;
403: #endif
404: #ifdef HAVE_reload_inti
405: if (HAVE_reload_inti)
406: reload_in_optab[(int) TImode] = CODE_FOR_reload_inti;
407: #endif
408: #ifdef HAVE_reload_insf
409: if (HAVE_reload_insf)
410: reload_in_optab[(int) SFmode] = CODE_FOR_reload_insf;
411: #endif
412: #ifdef HAVE_reload_indf
413: if (HAVE_reload_indf)
414: reload_in_optab[(int) DFmode] = CODE_FOR_reload_indf;
415: #endif
416: #ifdef HAVE_reload_inxf
417: if (HAVE_reload_inxf)
418: reload_in_optab[(int) XFmode] = CODE_FOR_reload_inxf;
419: #endif
420: #ifdef HAVE_reload_intf
421: if (HAVE_reload_intf)
422: reload_in_optab[(int) TFmode] = CODE_FOR_reload_intf;
423: #endif
424:
425: #ifdef HAVE_reload_outqi
426: if (HAVE_reload_outqi)
427: reload_out_optab[(int) QImode] = CODE_FOR_reload_outqi;
428: #endif
429: #ifdef HAVE_reload_outhi
430: if (HAVE_reload_outhi)
431: reload_out_optab[(int) HImode] = CODE_FOR_reload_outhi;
432: #endif
433: #ifdef HAVE_reload_outsi
434: if (HAVE_reload_outsi)
435: reload_out_optab[(int) SImode] = CODE_FOR_reload_outsi;
436: #endif
437: #ifdef HAVE_reload_outdi
438: if (HAVE_reload_outdi)
439: reload_out_optab[(int) DImode] = CODE_FOR_reload_outdi;
440: #endif
441: #ifdef HAVE_reload_outti
442: if (HAVE_reload_outti)
443: reload_out_optab[(int) TImode] = CODE_FOR_reload_outti;
444: #endif
445: #ifdef HAVE_reload_outsf
446: if (HAVE_reload_outsf)
447: reload_out_optab[(int) SFmode] = CODE_FOR_reload_outsf;
448: #endif
449: #ifdef HAVE_reload_outdf
450: if (HAVE_reload_outdf)
451: reload_out_optab[(int) DFmode] = CODE_FOR_reload_outdf;
452: #endif
453: #ifdef HAVE_reload_outxf
454: if (HAVE_reload_outxf)
455: reload_out_optab[(int) XFmode] = CODE_FOR_reload_outxf;
456: #endif
457: #ifdef HAVE_reload_outtf
458: if (HAVE_reload_outtf)
459: reload_out_optab[(int) TFmode] = CODE_FOR_reload_outtf;
460: #endif
461:
462: #endif /* HAVE_SECONDARY_RELOADS */
463:
464: }
465:
466: /* Main entry point for the reload pass, and only entry point
467: in this file.
468:
469: FIRST is the first insn of the function being compiled.
470:
471: GLOBAL nonzero means we were called from global_alloc
472: and should attempt to reallocate any pseudoregs that we
473: displace from hard regs we will use for reloads.
474: If GLOBAL is zero, we do not have enough information to do that,
475: so any pseudo reg that is spilled must go to the stack.
476:
477: DUMPFILE is the global-reg debugging dump file stream, or 0.
478: If it is nonzero, messages are written to it to describe
479: which registers are seized as reload regs, which pseudo regs
480: are spilled from them, and where the pseudo regs are reallocated to. */
481:
482: void
483: reload (first, global, dumpfile)
484: rtx first;
485: int global;
486: FILE *dumpfile;
487: {
488: register int class;
489: register int i;
490: register rtx insn;
491: register struct elim_table *ep;
492:
493: int something_changed;
494: int something_needs_reloads;
495: int something_needs_elimination;
496: int new_basic_block_needs;
497: enum reg_class caller_save_spill_class = NO_REGS;
498: int caller_save_group_size = 1;
499:
500: /* The basic block number currently being processed for INSN. */
501: int this_block;
502:
503: /* Make sure even insns with volatile mem refs are recognizable. */
504: init_recog ();
505:
506: /* Enable find_equiv_reg to distinguish insns made by reload. */
507: reload_first_uid = get_max_uid ();
508:
509: for (i = 0; i < N_REG_CLASSES; i++)
510: basic_block_needs[i] = 0;
511:
512: /* Remember which hard regs appear explicitly
513: before we merge into `regs_ever_live' the ones in which
514: pseudo regs have been allocated. */
515: bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
516:
517: /* We don't have a stack slot for any spill reg yet. */
518: bzero (spill_stack_slot, sizeof spill_stack_slot);
519: bzero (spill_stack_slot_width, sizeof spill_stack_slot_width);
520:
521: /* Initialize the save area information for caller-save, in case some
522: are needed. */
523: init_save_areas ();
524:
525: /* Compute which hard registers are now in use
526: as homes for pseudo registers.
527: This is done here rather than (eg) in global_alloc
528: because this point is reached even if not optimizing. */
529:
530: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
531: mark_home_live (i);
532:
533: /* Make sure that the last insn in the chain
534: is not something that needs reloading. */
535: emit_note (0, NOTE_INSN_DELETED);
536:
537: /* Find all the pseudo registers that didn't get hard regs
538: but do have known equivalent constants or memory slots.
539: These include parameters (known equivalent to parameter slots)
540: and cse'd or loop-moved constant memory addresses.
541:
542: Record constant equivalents in reg_equiv_constant
543: so they will be substituted by find_reloads.
544: Record memory equivalents in reg_mem_equiv so they can
545: be substituted eventually by altering the REG-rtx's. */
546:
547: reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
548: bzero (reg_equiv_constant, max_regno * sizeof (rtx));
549: reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
550: bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx));
551: reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
552: bzero (reg_equiv_mem, max_regno * sizeof (rtx));
553: reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
554: bzero (reg_equiv_init, max_regno * sizeof (rtx));
555: reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
556: bzero (reg_equiv_address, max_regno * sizeof (rtx));
557: reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
558: bzero (reg_max_ref_width, max_regno * sizeof (int));
559:
560: /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
561: Also find all paradoxical subregs
562: and find largest such for each pseudo. */
563:
564: for (insn = first; insn; insn = NEXT_INSN (insn))
565: {
566: rtx set = single_set (insn);
567:
568: if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
569: {
570: rtx note = find_reg_note (insn, REG_EQUIV, 0);
571: if (note
572: #ifdef LEGITIMATE_PIC_OPERAND_P
573: && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
574: || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
575: #endif
576: )
577: {
578: rtx x = XEXP (note, 0);
579: i = REGNO (SET_DEST (set));
580: if (i > LAST_VIRTUAL_REGISTER)
581: {
582: if (GET_CODE (x) == MEM)
583: reg_equiv_memory_loc[i] = x;
584: else if (CONSTANT_P (x))
585: {
586: if (LEGITIMATE_CONSTANT_P (x))
587: reg_equiv_constant[i] = x;
588: else
589: reg_equiv_memory_loc[i]
590: = force_const_mem (GET_MODE (SET_DEST (set)), x);
591: }
592: else
593: continue;
594:
595: /* If this register is being made equivalent to a MEM
596: and the MEM is not SET_SRC, the equivalencing insn
597: is one with the MEM as a SET_DEST and it occurs later.
598: So don't mark this insn now. */
599: if (GET_CODE (x) != MEM
600: || rtx_equal_p (SET_SRC (set), x))
601: reg_equiv_init[i] = insn;
602: }
603: }
604: }
605:
606: /* If this insn is setting a MEM from a register equivalent to it,
607: this is the equivalencing insn. */
608: else if (set && GET_CODE (SET_DEST (set)) == MEM
609: && GET_CODE (SET_SRC (set)) == REG
610: && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
611: && rtx_equal_p (SET_DEST (set),
612: reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
613: reg_equiv_init[REGNO (SET_SRC (set))] = insn;
614:
615: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
616: scan_paradoxical_subregs (PATTERN (insn));
617: }
618:
619: /* Does this function require a frame pointer? */
620:
621: frame_pointer_needed = (! flag_omit_frame_pointer
622: #ifdef EXIT_IGNORE_STACK
623: /* ?? If EXIT_IGNORE_STACK is set, we will not save
624: and restore sp for alloca. So we can't eliminate
625: the frame pointer in that case. At some point,
626: we should improve this by emitting the
627: sp-adjusting insns for this case. */
628: || (current_function_calls_alloca
629: && EXIT_IGNORE_STACK)
630: #endif
631: || FRAME_POINTER_REQUIRED);
632:
633: num_eliminable = 0;
634:
635: /* Initialize the table of registers to eliminate. The way we do this
636: depends on how the eliminable registers were defined. */
637: #ifdef ELIMINABLE_REGS
638: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
639: {
640: ep->can_eliminate = ep->can_eliminate_previous
641: = (CAN_ELIMINATE (ep->from, ep->to)
642: && (ep->from != FRAME_POINTER_REGNUM || ! frame_pointer_needed));
643: }
644: #else
645: reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
646: = ! frame_pointer_needed;
647: #endif
648:
649: /* Count the number of eliminable registers and build the FROM and TO
650: REG rtx's. Note that code in gen_rtx will cause, e.g.,
651: gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
652: We depend on this. */
653: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
654: {
655: num_eliminable += ep->can_eliminate;
656: ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
657: ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
658: }
659:
660: num_labels = max_label_num () - get_first_label_num ();
661:
662: /* Allocate the tables used to store offset information at labels. */
663: offsets_known_at = (char *) alloca (num_labels);
664: offsets_at
665: = (int (*)[NUM_ELIMINABLE_REGS])
666: alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
667:
668: offsets_known_at -= get_first_label_num ();
669: offsets_at -= get_first_label_num ();
670:
671: /* Alter each pseudo-reg rtx to contain its hard reg number.
672: Assign stack slots to the pseudos that lack hard regs or equivalents.
673: Do not touch virtual registers. */
674:
675: for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
676: alter_reg (i, -1);
677:
678: /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
679: because the stack size may be a part of the offset computation for
680: register elimination. */
681: assign_stack_local (BLKmode, 0, 0);
682:
683: /* If we have some registers we think can be eliminated, scan all insns to
684: see if there is an insn that sets one of these registers to something
685: other than itself plus a constant. If so, the register cannot be
686: eliminated. Doing this scan here eliminates an extra pass through the
687: main reload loop in the most common case where register elimination
688: cannot be done. */
689: for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
690: if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
691: || GET_CODE (insn) == CALL_INSN)
692: note_stores (PATTERN (insn), mark_not_eliminable);
693:
694: #ifndef REGISTER_CONSTRAINTS
695: /* If all the pseudo regs have hard regs,
696: except for those that are never referenced,
697: we know that no reloads are needed. */
698: /* But that is not true if there are register constraints, since
699: in that case some pseudos might be in the wrong kind of hard reg. */
700:
701: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
702: if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
703: break;
704:
1.1.1.2 ! root 705: if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
1.1 root 706: return;
707: #endif
708:
709: /* Compute the order of preference for hard registers to spill.
710: Store them by decreasing preference in potential_reload_regs. */
711:
712: order_regs_for_reload ();
713:
714: /* So far, no hard regs have been spilled. */
715: n_spills = 0;
716: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
717: spill_reg_order[i] = -1;
718:
719: /* On most machines, we can't use any register explicitly used in the
720: rtl as a spill register. But on some, we have to. Those will have
721: taken care to keep the life of hard regs as short as possible. */
722:
723: #ifdef SMALL_REGISTER_CLASSES
724: CLEAR_HARD_REG_SET (forbidden_regs);
725: #else
726: COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
727: #endif
728:
729: /* Spill any hard regs that we know we can't eliminate. */
730: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
731: if (! ep->can_eliminate)
732: {
733: spill_hard_reg (ep->from, global, dumpfile, 1);
734: regs_ever_live[ep->from] = 1;
735: }
736:
737: if (global)
738: for (i = 0; i < N_REG_CLASSES; i++)
739: {
740: basic_block_needs[i] = (char *)alloca (n_basic_blocks);
741: bzero (basic_block_needs[i], n_basic_blocks);
742: }
743:
744: /* This loop scans the entire function each go-round
745: and repeats until one repetition spills no additional hard regs. */
746:
1.1.1.2 ! root 747: /* This flag is set when a pseudo reg is spilled,
1.1 root 748: to require another pass. Note that getting an additional reload
749: reg does not necessarily imply any pseudo reg was spilled;
750: sometimes we find a reload reg that no pseudo reg was allocated in. */
751: something_changed = 1;
752: /* This flag is set if there are any insns that require reloading. */
753: something_needs_reloads = 0;
754: /* This flag is set if there are any insns that require register
755: eliminations. */
756: something_needs_elimination = 0;
757: while (something_changed)
758: {
759: rtx after_call = 0;
760:
761: /* For each class, number of reload regs needed in that class.
762: This is the maximum over all insns of the needs in that class
763: of the individual insn. */
764: int max_needs[N_REG_CLASSES];
765: /* For each class, size of group of consecutive regs
766: that is needed for the reloads of this class. */
767: int group_size[N_REG_CLASSES];
768: /* For each class, max number of consecutive groups needed.
769: (Each group contains group_size[CLASS] consecutive registers.) */
770: int max_groups[N_REG_CLASSES];
771: /* For each class, max number needed of regs that don't belong
772: to any of the groups. */
773: int max_nongroups[N_REG_CLASSES];
774: /* For each class, the machine mode which requires consecutive
775: groups of regs of that class.
776: If two different modes ever require groups of one class,
777: they must be the same size and equally restrictive for that class,
778: otherwise we can't handle the complexity. */
779: enum machine_mode group_mode[N_REG_CLASSES];
780: rtx x;
781:
782: something_changed = 0;
783: bzero (max_needs, sizeof max_needs);
784: bzero (max_groups, sizeof max_groups);
785: bzero (max_nongroups, sizeof max_nongroups);
786: bzero (group_size, sizeof group_size);
787: for (i = 0; i < N_REG_CLASSES; i++)
788: group_mode[i] = VOIDmode;
789:
790: /* Keep track of which basic blocks are needing the reloads. */
791: this_block = 0;
792:
793: /* Remember whether any element of basic_block_needs
794: changes from 0 to 1 in this pass. */
795: new_basic_block_needs = 0;
796:
797: /* Reset all offsets on eliminable registers to their initial values. */
798: #ifdef ELIMINABLE_REGS
799: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
800: {
801: INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
802: ep->previous_offset = ep->offset
803: = ep->max_offset = ep->initial_offset;
804: }
805: #else
806: #ifdef INITIAL_FRAME_POINTER_OFFSET
807: INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
808: #else
809: if (!FRAME_POINTER_REQUIRED)
810: abort ();
811: reg_eliminate[0].initial_offset = 0;
812: #endif
813: reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
814: = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
815: #endif
816:
817: num_not_at_initial_offset = 0;
818:
819: bzero (&offsets_known_at[get_first_label_num ()], num_labels);
820:
821: /* Set a known offset for each forced label to be at the initial offset
822: of each elimination. We do this because we assume that all
823: computed jumps occur from a location where each elimination is
824: at its initial offset. */
825:
826: for (x = forced_labels; x; x = XEXP (x, 1))
827: if (XEXP (x, 0))
828: set_label_offsets (XEXP (x, 0), 0, 1);
829:
830: /* For each pseudo register that has an equivalent location defined,
831: try to eliminate any eliminable registers (such as the frame pointer)
832: assuming initial offsets for the replacement register, which
833: is the normal case.
834:
835: If the resulting location is directly addressable, substitute
836: the MEM we just got directly for the old REG.
837:
838: If it is not addressable but is a constant or the sum of a hard reg
839: and constant, it is probably not addressable because the constant is
840: out of range, in that case record the address; we will generate
841: hairy code to compute the address in a register each time it is
842: needed.
843:
844: If the location is not addressable, but does not have one of the
845: above forms, assign a stack slot. We have to do this to avoid the
846: potential of producing lots of reloads if, e.g., a location involves
847: a pseudo that didn't get a hard register and has an equivalent memory
848: location that also involves a pseudo that didn't get a hard register.
849:
850: Perhaps at some point we will improve reload_when_needed handling
851: so this problem goes away. But that's very hairy. */
852:
853: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
854: if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
855: {
856: rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, 0);
857:
858: if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
859: XEXP (x, 0)))
860: reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
861: else if (CONSTANT_P (XEXP (x, 0))
862: || (GET_CODE (XEXP (x, 0)) == PLUS
863: && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
864: && (REGNO (XEXP (XEXP (x, 0), 0))
865: < FIRST_PSEUDO_REGISTER)
866: && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
867: reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
868: else
869: {
870: /* Make a new stack slot. Then indicate that something
871: changed so we go back and recompute offsets for
872: eliminable registers because the allocation of memory
873: below might change some offset. reg_equiv_{mem,address}
874: will be set up for this pseudo on the next pass around
875: the loop. */
876: reg_equiv_memory_loc[i] = 0;
877: reg_equiv_init[i] = 0;
878: alter_reg (i, -1);
879: something_changed = 1;
880: }
881: }
882:
1.1.1.2 ! root 883: /* If we allocated another pseudo to the stack, redo elimination
1.1 root 884: bookkeeping. */
885: if (something_changed)
886: continue;
887:
888: /* If caller-saves needs a group, initialize the group to include
889: the size and mode required for caller-saves. */
890:
891: if (caller_save_group_size > 1)
892: {
893: group_mode[(int) caller_save_spill_class] = Pmode;
894: group_size[(int) caller_save_spill_class] = caller_save_group_size;
895: }
896:
897: /* Compute the most additional registers needed by any instruction.
898: Collect information separately for each class of regs. */
899:
900: for (insn = first; insn; insn = NEXT_INSN (insn))
901: {
902: if (global && this_block + 1 < n_basic_blocks
903: && insn == basic_block_head[this_block+1])
904: ++this_block;
905:
906: /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
907: might include REG_LABEL), we need to see what effects this
908: has on the known offsets at labels. */
909:
910: if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
911: || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
912: && REG_NOTES (insn) != 0))
913: set_label_offsets (insn, insn, 0);
914:
915: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
916: {
917: /* Nonzero means don't use a reload reg that overlaps
918: the place where a function value can be returned. */
919: rtx avoid_return_reg = 0;
920:
921: rtx old_body = PATTERN (insn);
922: int old_code = INSN_CODE (insn);
923: rtx old_notes = REG_NOTES (insn);
924: int did_elimination = 0;
925:
926: /* Initially, count RELOAD_OTHER reloads.
927: Later, merge in the other kinds. */
928: int insn_needs[N_REG_CLASSES];
929: int insn_groups[N_REG_CLASSES];
930: int insn_total_groups = 0;
931:
932: /* Count RELOAD_FOR_INPUT_RELOAD_ADDRESS reloads. */
933: int insn_needs_for_inputs[N_REG_CLASSES];
934: int insn_groups_for_inputs[N_REG_CLASSES];
935: int insn_total_groups_for_inputs = 0;
936:
937: /* Count RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reloads. */
938: int insn_needs_for_outputs[N_REG_CLASSES];
939: int insn_groups_for_outputs[N_REG_CLASSES];
940: int insn_total_groups_for_outputs = 0;
941:
942: /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */
943: int insn_needs_for_operands[N_REG_CLASSES];
944: int insn_groups_for_operands[N_REG_CLASSES];
945: int insn_total_groups_for_operands = 0;
946:
947: #if 0 /* This wouldn't work nowadays, since optimize_bit_field
948: looks for non-strict memory addresses. */
949: /* Optimization: a bit-field instruction whose field
950: happens to be a byte or halfword in memory
951: can be changed to a move instruction. */
952:
953: if (GET_CODE (PATTERN (insn)) == SET)
954: {
955: rtx dest = SET_DEST (PATTERN (insn));
956: rtx src = SET_SRC (PATTERN (insn));
957:
958: if (GET_CODE (dest) == ZERO_EXTRACT
959: || GET_CODE (dest) == SIGN_EXTRACT)
960: optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
961: if (GET_CODE (src) == ZERO_EXTRACT
962: || GET_CODE (src) == SIGN_EXTRACT)
963: optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
964: }
965: #endif
966:
967: /* If needed, eliminate any eliminable registers. */
968: if (num_eliminable)
969: did_elimination = eliminate_regs_in_insn (insn, 0);
970:
971: #ifdef SMALL_REGISTER_CLASSES
972: /* Set avoid_return_reg if this is an insn
973: that might use the value of a function call. */
974: if (GET_CODE (insn) == CALL_INSN)
975: {
976: if (GET_CODE (PATTERN (insn)) == SET)
977: after_call = SET_DEST (PATTERN (insn));
978: else if (GET_CODE (PATTERN (insn)) == PARALLEL
979: && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
980: after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
981: else
982: after_call = 0;
983: }
984: else if (after_call != 0
985: && !(GET_CODE (PATTERN (insn)) == SET
986: && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
987: {
988: if (reg_mentioned_p (after_call, PATTERN (insn)))
989: avoid_return_reg = after_call;
990: after_call = 0;
991: }
992: #endif /* SMALL_REGISTER_CLASSES */
993:
994: /* Analyze the instruction. */
995: find_reloads (insn, 0, spill_indirect_levels, global,
996: spill_reg_order);
997:
998: /* Remember for later shortcuts which insns had any reloads or
999: register eliminations.
1000:
1001: One might think that it would be worthwhile to mark insns
1002: that need register replacements but not reloads, but this is
1003: not safe because find_reloads may do some manipulation of
1004: the insn (such as swapping commutative operands), which would
1005: be lost when we restore the old pattern after register
1006: replacement. So the actions of find_reloads must be redone in
1007: subsequent passes or in reload_as_needed.
1008:
1009: However, it is safe to mark insns that need reloads
1010: but not register replacement. */
1011:
1012: PUT_MODE (insn, (did_elimination ? QImode
1013: : n_reloads ? HImode
1014: : VOIDmode));
1015:
1016: /* Discard any register replacements done. */
1017: if (did_elimination)
1018: {
1019: obstack_free (&reload_obstack, reload_firstobj);
1020: PATTERN (insn) = old_body;
1021: INSN_CODE (insn) = old_code;
1022: REG_NOTES (insn) = old_notes;
1023: something_needs_elimination = 1;
1024: }
1025:
1026: /* If this insn has no reloads, we need not do anything except
1027: in the case of a CALL_INSN when we have caller-saves and
1028: caller-save needs reloads. */
1029:
1030: if (n_reloads == 0
1031: && ! (GET_CODE (insn) == CALL_INSN
1032: && caller_save_spill_class != NO_REGS))
1033: continue;
1034:
1035: something_needs_reloads = 1;
1036:
1037: for (i = 0; i < N_REG_CLASSES; i++)
1038: {
1039: insn_needs[i] = 0, insn_groups[i] = 0;
1040: insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0;
1041: insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0;
1042: insn_needs_for_operands[i] = 0, insn_groups_for_operands[i] = 0;
1043: }
1044:
1045: /* Count each reload once in every class
1046: containing the reload's own class. */
1047:
1048: for (i = 0; i < n_reloads; i++)
1049: {
1050: register enum reg_class *p;
1051: int size;
1052: enum machine_mode mode;
1053: int *this_groups;
1054: int *this_needs;
1055: int *this_total_groups;
1056:
1057: /* Don't count the dummy reloads, for which one of the
1058: regs mentioned in the insn can be used for reloading.
1059: Don't count optional reloads.
1060: Don't count reloads that got combined with others. */
1061: if (reload_reg_rtx[i] != 0
1062: || reload_optional[i] != 0
1063: || (reload_out[i] == 0 && reload_in[i] == 0
1064: && ! reload_secondary_p[i]))
1065: continue;
1066:
1067: /* Decide which time-of-use to count this reload for. */
1068: switch (reload_when_needed[i])
1069: {
1070: case RELOAD_OTHER:
1071: case RELOAD_FOR_OUTPUT:
1072: case RELOAD_FOR_INPUT:
1073: this_needs = insn_needs;
1074: this_groups = insn_groups;
1075: this_total_groups = &insn_total_groups;
1076: break;
1077:
1078: case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
1079: this_needs = insn_needs_for_inputs;
1080: this_groups = insn_groups_for_inputs;
1081: this_total_groups = &insn_total_groups_for_inputs;
1082: break;
1083:
1084: case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
1085: this_needs = insn_needs_for_outputs;
1086: this_groups = insn_groups_for_outputs;
1087: this_total_groups = &insn_total_groups_for_outputs;
1088: break;
1089:
1090: case RELOAD_FOR_OPERAND_ADDRESS:
1091: this_needs = insn_needs_for_operands;
1092: this_groups = insn_groups_for_operands;
1093: this_total_groups = &insn_total_groups_for_operands;
1094: break;
1095: }
1096:
1097: mode = reload_inmode[i];
1098: if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1099: mode = reload_outmode[i];
1100: size = CLASS_MAX_NREGS (reload_reg_class[i], mode);
1101: if (size > 1)
1102: {
1103: enum machine_mode other_mode, allocate_mode;
1104:
1105: /* Count number of groups needed separately from
1106: number of individual regs needed. */
1107: this_groups[(int) reload_reg_class[i]]++;
1108: p = reg_class_superclasses[(int) reload_reg_class[i]];
1109: while (*p != LIM_REG_CLASSES)
1110: this_groups[(int) *p++]++;
1111: (*this_total_groups)++;
1112:
1113: /* Record size and mode of a group of this class. */
1114: /* If more than one size group is needed,
1115: make all groups the largest needed size. */
1116: if (group_size[(int) reload_reg_class[i]] < size)
1117: {
1118: other_mode = group_mode[(int) reload_reg_class[i]];
1119: allocate_mode = mode;
1120:
1121: group_size[(int) reload_reg_class[i]] = size;
1122: group_mode[(int) reload_reg_class[i]] = mode;
1123: }
1124: else
1125: {
1126: other_mode = mode;
1127: allocate_mode = group_mode[(int) reload_reg_class[i]];
1128: }
1129:
1130: /* Crash if two dissimilar machine modes both need
1131: groups of consecutive regs of the same class. */
1132:
1133: if (other_mode != VOIDmode
1134: && other_mode != allocate_mode
1135: && ! modes_equiv_for_class_p (allocate_mode,
1136: other_mode,
1137: reload_reg_class[i]))
1138: abort ();
1139: }
1140: else if (size == 1)
1141: {
1142: this_needs[(int) reload_reg_class[i]] += 1;
1143: p = reg_class_superclasses[(int) reload_reg_class[i]];
1144: while (*p != LIM_REG_CLASSES)
1145: this_needs[(int) *p++] += 1;
1146: }
1147: else
1148: abort ();
1149: }
1150:
1151: /* All reloads have been counted for this insn;
1152: now merge the various times of use.
1153: This sets insn_needs, etc., to the maximum total number
1154: of registers needed at any point in this insn. */
1155:
1156: for (i = 0; i < N_REG_CLASSES; i++)
1157: {
1158: int this_max;
1159: this_max = insn_needs_for_inputs[i];
1160: if (insn_needs_for_outputs[i] > this_max)
1161: this_max = insn_needs_for_outputs[i];
1162: if (insn_needs_for_operands[i] > this_max)
1163: this_max = insn_needs_for_operands[i];
1164: insn_needs[i] += this_max;
1165: this_max = insn_groups_for_inputs[i];
1166: if (insn_groups_for_outputs[i] > this_max)
1167: this_max = insn_groups_for_outputs[i];
1168: if (insn_groups_for_operands[i] > this_max)
1169: this_max = insn_groups_for_operands[i];
1170: insn_groups[i] += this_max;
1171: }
1172:
1173: insn_total_groups += MAX (insn_total_groups_for_inputs,
1174: MAX (insn_total_groups_for_outputs,
1175: insn_total_groups_for_operands));
1176:
1177: /* If this is a CALL_INSN and caller-saves will need
1178: a spill register, act as if the spill register is
1179: needed for this insn. However, the spill register
1180: can be used by any reload of this insn, so we only
1181: need do something if no need for that class has
1182: been recorded.
1183:
1184: The assumption that every CALL_INSN will trigger a
1185: caller-save is highly conservative, however, the number
1186: of cases where caller-saves will need a spill register but
1187: a block containing a CALL_INSN won't need a spill register
1188: of that class should be quite rare.
1189:
1190: If a group is needed, the size and mode of the group will
1.1.1.2 ! root 1191: have been set up at the beginning of this loop. */
1.1 root 1192:
1193: if (GET_CODE (insn) == CALL_INSN
1194: && caller_save_spill_class != NO_REGS)
1195: {
1196: int *caller_save_needs
1197: = (caller_save_group_size > 1 ? insn_groups : insn_needs);
1198:
1199: if (caller_save_needs[(int) caller_save_spill_class] == 0)
1200: {
1201: register enum reg_class *p
1202: = reg_class_superclasses[(int) caller_save_spill_class];
1203:
1204: caller_save_needs[(int) caller_save_spill_class]++;
1205:
1206: while (*p != LIM_REG_CLASSES)
1207: caller_save_needs[(int) *p++] += 1;
1208: }
1209:
1210: if (caller_save_group_size > 1)
1211: insn_total_groups = MAX (insn_total_groups, 1);
1212: }
1213:
1214: /* Update the basic block needs. */
1215:
1216: for (i = 0; i < N_REG_CLASSES; i++)
1217: if (global && (insn_needs[i] || insn_groups[i])
1218: && ! basic_block_needs[i][this_block])
1219: {
1220: new_basic_block_needs = 1;
1221: basic_block_needs[i][this_block] = 1;
1222: }
1223:
1224: #ifdef SMALL_REGISTER_CLASSES
1225: /* If this insn stores the value of a function call,
1226: and that value is in a register that has been spilled,
1227: and if the insn needs a reload in a class
1228: that might use that register as the reload register,
1229: then add add an extra need in that class.
1230: This makes sure we have a register available that does
1231: not overlap the return value. */
1232: if (avoid_return_reg)
1233: {
1234: int regno = REGNO (avoid_return_reg);
1235: int nregs
1236: = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1237: int r;
1238: int inc_groups = 0;
1239: for (r = regno; r < regno + nregs; r++)
1240: if (spill_reg_order[r] >= 0)
1241: for (i = 0; i < N_REG_CLASSES; i++)
1242: if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1243: {
1244: if (insn_needs[i] > 0)
1245: insn_needs[i]++;
1246: if (insn_groups[i] > 0
1247: && nregs > 1)
1248: inc_groups = 1;
1249: }
1250: if (inc_groups)
1251: insn_groups[i]++;
1252: }
1253: #endif /* SMALL_REGISTER_CLASSES */
1254:
1255: /* For each class, collect maximum need of any insn. */
1256:
1257: for (i = 0; i < N_REG_CLASSES; i++)
1258: {
1259: if (max_needs[i] < insn_needs[i])
1260: max_needs[i] = insn_needs[i];
1261: if (max_groups[i] < insn_groups[i])
1262: max_groups[i] = insn_groups[i];
1263: if (insn_total_groups > 0)
1264: if (max_nongroups[i] < insn_needs[i])
1265: max_nongroups[i] = insn_needs[i];
1266: }
1267: }
1268: /* Note that there is a continue statement above. */
1269: }
1270:
1271: /* If we have caller-saves, set up the save areas and see if caller-save
1272: will need a spill register. */
1273:
1274: if (caller_save_needed
1275: && ! setup_save_areas (&something_changed)
1276: && caller_save_spill_class == NO_REGS)
1277: {
1278: /* The class we will need depends on whether the machine
1279: supports the sum of two registers for an address; see
1280: find_address_reloads for details. */
1281:
1282: caller_save_spill_class
1283: = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1284: caller_save_group_size
1285: = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1286: something_changed = 1;
1287: }
1288:
1289: /* Now deduct from the needs for the registers already
1290: available (already spilled). */
1291:
1292: CLEAR_HARD_REG_SET (counted_for_groups);
1293: CLEAR_HARD_REG_SET (counted_for_nongroups);
1294:
1295: /* First find all regs alone in their class
1296: and count them (if desired) for non-groups.
1297: We would be screwed if a group took the only reg in a class
1298: for which a non-group reload is needed.
1299: (Note there is still a bug; if a class has 2 regs,
1300: both could be stolen by groups and we would lose the same way.
1301: With luck, no machine will need a nongroup in a 2-reg class.) */
1302:
1303: for (i = 0; i < n_spills; i++)
1304: {
1305: register enum reg_class *p;
1306: class = (int) REGNO_REG_CLASS (spill_regs[i]);
1307:
1308: if (reg_class_size[class] == 1 && max_nongroups[class] > 0)
1309: {
1310: max_needs[class]--;
1311: p = reg_class_superclasses[class];
1312: while (*p != LIM_REG_CLASSES)
1313: max_needs[(int) *p++]--;
1314:
1315: SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1316: max_nongroups[class]--;
1317: p = reg_class_superclasses[class];
1318: while (*p != LIM_REG_CLASSES)
1319: {
1320: if (max_nongroups[(int) *p] > 0)
1321: SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1322: max_nongroups[(int) *p++]--;
1323: }
1324: }
1325: }
1326:
1327: /* Now find all consecutive groups of spilled registers
1328: and mark each group off against the need for such groups.
1329: But don't count them against ordinary need, yet. */
1330:
1331: count_possible_groups (group_size, group_mode, max_groups);
1332:
1333: /* Now count all spill regs against the individual need,
1334: This includes those counted above for groups,
1335: but not those previously counted for nongroups.
1336:
1337: Those that weren't counted_for_groups can also count against
1338: the not-in-group need. */
1339:
1340: for (i = 0; i < n_spills; i++)
1341: {
1342: register enum reg_class *p;
1343: class = (int) REGNO_REG_CLASS (spill_regs[i]);
1344:
1345: /* Those counted at the beginning shouldn't be counted twice. */
1346: if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
1347: {
1348: max_needs[class]--;
1349: p = reg_class_superclasses[class];
1350: while (*p != LIM_REG_CLASSES)
1351: max_needs[(int) *p++]--;
1352:
1353: if (! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i]))
1354: {
1355: if (max_nongroups[class] > 0)
1356: SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1357: max_nongroups[class]--;
1358: p = reg_class_superclasses[class];
1359: while (*p != LIM_REG_CLASSES)
1360: {
1361: if (max_nongroups[(int) *p] > 0)
1362: SET_HARD_REG_BIT (counted_for_nongroups,
1363: spill_regs[i]);
1364: max_nongroups[(int) *p++]--;
1365: }
1366: }
1367: }
1368: }
1369:
1.1.1.2 ! root 1370: /* See if anything that happened changes which eliminations are valid.
! 1371: For example, on the Sparc, whether or not the frame pointer can
! 1372: be eliminated can depend on what registers have been used. We need
! 1373: not check some conditions again (such as flag_omit_frame_pointer)
! 1374: since they can't have changed. */
! 1375:
! 1376: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
! 1377: if ((ep->from == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
! 1378: #ifdef ELIMINABLE_REGS
! 1379: || ! CAN_ELIMINATE (ep->from, ep->to)
! 1380: #endif
! 1381: )
! 1382: ep->can_eliminate = 0;
! 1383:
1.1 root 1384: /* Look for the case where we have discovered that we can't replace
1385: register A with register B and that means that we will now be
1386: trying to replace register A with register C. This means we can
1387: no longer replace register C with register B and we need to disable
1388: such an elimination, if it exists. This occurs often with A == ap,
1389: B == sp, and C == fp. */
1390:
1391: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1392: {
1393: struct elim_table *op;
1394: register int new_to = -1;
1395:
1396: if (! ep->can_eliminate && ep->can_eliminate_previous)
1397: {
1398: /* Find the current elimination for ep->from, if there is a
1399: new one. */
1400: for (op = reg_eliminate;
1401: op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1402: if (op->from == ep->from && op->can_eliminate)
1403: {
1404: new_to = op->to;
1405: break;
1406: }
1407:
1408: /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1409: disable it. */
1410: for (op = reg_eliminate;
1411: op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1412: if (op->from == new_to && op->to == ep->to)
1413: op->can_eliminate = 0;
1414: }
1415: }
1416:
1417: /* See if any registers that we thought we could eliminate the previous
1418: time are no longer eliminable. If so, something has changed and we
1419: must spill the register. Also, recompute the number of eliminable
1420: registers and see if the frame pointer is needed; it is if there is
1421: no elimination of the frame pointer that we can perform. */
1422:
1423: frame_pointer_needed = 1;
1424: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1425: {
1426: if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM)
1427: frame_pointer_needed = 0;
1428:
1429: if (! ep->can_eliminate && ep->can_eliminate_previous)
1430: {
1431: ep->can_eliminate_previous = 0;
1432: spill_hard_reg (ep->from, global, dumpfile, 1);
1433: regs_ever_live[ep->from] = 1;
1434: something_changed = 1;
1435: num_eliminable--;
1436: }
1437: }
1438:
1439: /* If all needs are met, we win. */
1440:
1441: for (i = 0; i < N_REG_CLASSES; i++)
1442: if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1443: break;
1444: if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1445: break;
1446:
1447: /* Not all needs are met; must spill more hard regs. */
1448:
1449: /* If any element of basic_block_needs changed from 0 to 1,
1450: re-spill all the regs already spilled. This may spill
1451: additional pseudos that didn't spill before. */
1452:
1453: if (new_basic_block_needs)
1454: for (i = 0; i < n_spills; i++)
1455: something_changed
1456: |= spill_hard_reg (spill_regs[i], global, dumpfile, 0);
1457:
1458: /* Now find more reload regs to satisfy the remaining need
1459: Do it by ascending class number, since otherwise a reg
1460: might be spilled for a big class and might fail to count
1461: for a smaller class even though it belongs to that class.
1462:
1463: Count spilled regs in `spills', and add entries to
1464: `spill_regs' and `spill_reg_order'.
1465:
1466: ??? Note there is a problem here.
1467: When there is a need for a group in a high-numbered class,
1468: and also need for non-group regs that come from a lower class,
1469: the non-group regs are chosen first. If there aren't many regs,
1470: they might leave no room for a group.
1471:
1472: This was happening on the 386. To fix it, we added the code
1473: that calls possible_group_p, so that the lower class won't
1474: break up the last possible group.
1475:
1476: Really fixing the problem would require changes above
1477: in counting the regs already spilled, and in choose_reload_regs.
1478: It might be hard to avoid introducing bugs there. */
1479:
1480: for (class = 0; class < N_REG_CLASSES; class++)
1481: {
1482: /* First get the groups of registers.
1483: If we got single registers first, we might fragment
1484: possible groups. */
1485: while (max_groups[class] > 0)
1486: {
1487: /* If any single spilled regs happen to form groups,
1488: count them now. Maybe we don't really need
1489: to spill another group. */
1490: count_possible_groups (group_size, group_mode, max_groups);
1491:
1492: /* Groups of size 2 (the only groups used on most machines)
1493: are treated specially. */
1494: if (group_size[class] == 2)
1495: {
1496: /* First, look for a register that will complete a group. */
1497: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1498: {
1499: int j = potential_reload_regs[i];
1500: int other;
1501: if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1502: &&
1503: ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1504: && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1505: && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1506: && HARD_REGNO_MODE_OK (other, group_mode[class])
1507: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1508: other)
1509: /* We don't want one part of another group.
1510: We could get "two groups" that overlap! */
1511: && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1512: ||
1513: (j < FIRST_PSEUDO_REGISTER - 1
1514: && (other = j + 1, spill_reg_order[other] >= 0)
1515: && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1516: && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1517: && HARD_REGNO_MODE_OK (j, group_mode[class])
1518: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1519: other)
1520: && ! TEST_HARD_REG_BIT (counted_for_groups,
1521: other))))
1522: {
1523: register enum reg_class *p;
1524:
1525: /* We have found one that will complete a group,
1526: so count off one group as provided. */
1527: max_groups[class]--;
1528: p = reg_class_superclasses[class];
1529: while (*p != LIM_REG_CLASSES)
1530: max_groups[(int) *p++]--;
1531:
1532: /* Indicate both these regs are part of a group. */
1533: SET_HARD_REG_BIT (counted_for_groups, j);
1534: SET_HARD_REG_BIT (counted_for_groups, other);
1535: break;
1536: }
1537: }
1538: /* We can't complete a group, so start one. */
1539: if (i == FIRST_PSEUDO_REGISTER)
1540: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1541: {
1542: int j = potential_reload_regs[i];
1543: if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1544: && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1545: && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1546: && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1547: && HARD_REGNO_MODE_OK (j, group_mode[class])
1548: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1549: j + 1))
1550: break;
1551: }
1552:
1553: /* I should be the index in potential_reload_regs
1554: of the new reload reg we have found. */
1555:
1556: something_changed
1557: |= new_spill_reg (i, class, max_needs, 0,
1558: global, dumpfile);
1559: }
1560: else
1561: {
1562: /* For groups of more than 2 registers,
1563: look for a sufficient sequence of unspilled registers,
1564: and spill them all at once. */
1565: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1566: {
1567: int j = potential_reload_regs[i];
1568: int k;
1569: if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1570: && HARD_REGNO_MODE_OK (j, group_mode[class]))
1571: {
1572: /* Check each reg in the sequence. */
1573: for (k = 0; k < group_size[class]; k++)
1574: if (! (spill_reg_order[j + k] < 0
1575: && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1576: && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1577: break;
1578: /* We got a full sequence, so spill them all. */
1579: if (k == group_size[class])
1580: {
1581: register enum reg_class *p;
1582: for (k = 0; k < group_size[class]; k++)
1583: {
1584: int idx;
1585: SET_HARD_REG_BIT (counted_for_groups, j + k);
1586: for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1587: if (potential_reload_regs[idx] == j + k)
1588: break;
1589: something_changed
1590: |= new_spill_reg (idx, class, max_needs, 0,
1591: global, dumpfile);
1592: }
1593:
1594: /* We have found one that will complete a group,
1595: so count off one group as provided. */
1596: max_groups[class]--;
1597: p = reg_class_superclasses[class];
1598: while (*p != LIM_REG_CLASSES)
1599: max_groups[(int) *p++]--;
1600:
1601: break;
1602: }
1603: }
1604: }
1605: }
1606: }
1607:
1608: /* Now similarly satisfy all need for single registers. */
1609:
1610: while (max_needs[class] > 0 || max_nongroups[class] > 0)
1611: {
1612: /* Consider the potential reload regs that aren't
1613: yet in use as reload regs, in order of preference.
1614: Find the most preferred one that's in this class. */
1615:
1616: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1617: if (potential_reload_regs[i] >= 0
1618: && TEST_HARD_REG_BIT (reg_class_contents[class],
1619: potential_reload_regs[i])
1620: /* If this reg will not be available for groups,
1621: pick one that does not foreclose possible groups.
1622: This is a kludge, and not very general,
1623: but it should be sufficient to make the 386 work,
1624: and the problem should not occur on machines with
1625: more registers. */
1626: && (max_nongroups[class] == 0
1627: || possible_group_p (potential_reload_regs[i], max_groups)))
1628: break;
1629:
1630: /* I should be the index in potential_reload_regs
1631: of the new reload reg we have found. */
1632:
1633: something_changed
1634: |= new_spill_reg (i, class, max_needs, max_nongroups,
1635: global, dumpfile);
1636: }
1637: }
1638: }
1639:
1640: /* If global-alloc was run, notify it of any register eliminations we have
1641: done. */
1642: if (global)
1643: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1644: if (ep->can_eliminate)
1645: mark_elimination (ep->from, ep->to);
1646:
1647: /* From now on, we need to emit any moves without making new pseudos. */
1648: reload_in_progress = 1;
1649:
1650: /* Insert code to save and restore call-clobbered hard regs
1651: around calls. Tell if what mode to use so that we will process
1652: those insns in reload_as_needed if we have to. */
1653:
1654: if (caller_save_needed)
1655: save_call_clobbered_regs (num_eliminable ? QImode
1656: : caller_save_spill_class != NO_REGS ? HImode
1657: : VOIDmode);
1658:
1659: /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1660: If that insn didn't set the register (i.e., it copied the register to
1661: memory), just delete that insn instead of the equivalencing insn plus
1662: anything now dead. If we call delete_dead_insn on that insn, we may
1663: delete the insn that actually sets the register if the register die
1664: there and that is incorrect. */
1665:
1666: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1667: if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1668: && GET_CODE (reg_equiv_init[i]) != NOTE)
1669: {
1670: if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1671: delete_dead_insn (reg_equiv_init[i]);
1672: else
1673: {
1674: PUT_CODE (reg_equiv_init[i], NOTE);
1675: NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1676: NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1677: }
1678: }
1679:
1680: /* Use the reload registers where necessary
1681: by generating move instructions to move the must-be-register
1682: values into or out of the reload registers. */
1683:
1684: if (something_needs_reloads || something_needs_elimination
1685: || (caller_save_needed && num_eliminable)
1686: || caller_save_spill_class != NO_REGS)
1687: reload_as_needed (first, global);
1688:
1689: reload_in_progress = 0;
1690:
1691: /* Now eliminate all pseudo regs by modifying them into
1692: their equivalent memory references.
1693: The REG-rtx's for the pseudos are modified in place,
1694: so all insns that used to refer to them now refer to memory.
1695:
1696: For a reg that has a reg_equiv_address, all those insns
1697: were changed by reloading so that no insns refer to it any longer;
1698: but the DECL_RTL of a variable decl may refer to it,
1699: and if so this causes the debugging info to mention the variable. */
1700:
1701: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1702: {
1703: rtx addr = 0;
1704: if (reg_equiv_mem[i])
1705: addr = XEXP (reg_equiv_mem[i], 0);
1706: if (reg_equiv_address[i])
1707: addr = reg_equiv_address[i];
1708: if (addr)
1709: {
1710: if (reg_renumber[i] < 0)
1711: {
1712: rtx reg = regno_reg_rtx[i];
1713: XEXP (reg, 0) = addr;
1714: REG_USERVAR_P (reg) = 0;
1715: PUT_CODE (reg, MEM);
1716: }
1717: else if (reg_equiv_mem[i])
1718: XEXP (reg_equiv_mem[i], 0) = addr;
1719: }
1720: }
1721:
1722: #ifdef PRESERVE_DEATH_INFO_REGNO_P
1723: /* Make a pass over all the insns and remove death notes for things that
1724: are no longer registers or no longer die in the insn (e.g., an input
1725: and output pseudo being tied). */
1726:
1727: for (insn = first; insn; insn = NEXT_INSN (insn))
1728: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1729: {
1730: rtx note, next;
1731:
1732: for (note = REG_NOTES (insn); note; note = next)
1733: {
1734: next = XEXP (note, 1);
1735: if (REG_NOTE_KIND (note) == REG_DEAD
1736: && (GET_CODE (XEXP (note, 0)) != REG
1737: || reg_set_p (XEXP (note, 0), PATTERN (insn))))
1738: remove_note (insn, note);
1739: }
1740: }
1741: #endif
1742:
1743: /* Indicate that we no longer have known memory locations or constants. */
1744: reg_equiv_constant = 0;
1745: reg_equiv_memory_loc = 0;
1746: }
1747:
1748: /* Nonzero if, after spilling reg REGNO for non-groups,
1749: it will still be possible to find a group if we still need one. */
1750:
1751: static int
1752: possible_group_p (regno, max_groups)
1753: int regno;
1754: int *max_groups;
1755: {
1756: int i;
1757: int class = (int) NO_REGS;
1758:
1759: for (i = 0; i < (int) N_REG_CLASSES; i++)
1760: if (max_groups[i] > 0)
1761: {
1762: class = i;
1763: break;
1764: }
1765:
1766: if (class == (int) NO_REGS)
1767: return 1;
1768:
1769: /* Consider each pair of consecutive registers. */
1770: for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
1771: {
1772: /* Ignore pairs that include reg REGNO. */
1773: if (i == regno || i + 1 == regno)
1774: continue;
1775:
1776: /* Ignore pairs that are outside the class that needs the group.
1777: ??? Here we fail to handle the case where two different classes
1778: independently need groups. But this never happens with our
1779: current machine descriptions. */
1780: if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
1781: && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
1782: continue;
1783:
1784: /* A pair of consecutive regs we can still spill does the trick. */
1785: if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
1786: && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1787: && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
1788: return 1;
1789:
1790: /* A pair of one already spilled and one we can spill does it
1791: provided the one already spilled is not otherwise reserved. */
1792: if (spill_reg_order[i] < 0
1793: && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1794: && spill_reg_order[i + 1] >= 0
1795: && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
1796: && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
1797: return 1;
1798: if (spill_reg_order[i + 1] < 0
1799: && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
1800: && spill_reg_order[i] >= 0
1801: && ! TEST_HARD_REG_BIT (counted_for_groups, i)
1802: && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
1803: return 1;
1804: }
1805:
1806: return 0;
1807: }
1808:
1809: /* Count any groups that can be formed from the registers recently spilled.
1810: This is done class by class, in order of ascending class number. */
1811:
1812: static void
1813: count_possible_groups (group_size, group_mode, max_groups)
1814: int *group_size, *max_groups;
1815: enum machine_mode *group_mode;
1816: {
1817: int i;
1818: /* Now find all consecutive groups of spilled registers
1819: and mark each group off against the need for such groups.
1820: But don't count them against ordinary need, yet. */
1821:
1822: for (i = 0; i < N_REG_CLASSES; i++)
1823: if (group_size[i] > 1)
1824: {
1825: char regmask[FIRST_PSEUDO_REGISTER];
1826: int j;
1827:
1828: bzero (regmask, sizeof regmask);
1829: /* Make a mask of all the regs that are spill regs in class I. */
1830: for (j = 0; j < n_spills; j++)
1831: if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j])
1832: && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j])
1833: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1834: spill_regs[j]))
1835: regmask[spill_regs[j]] = 1;
1836: /* Find each consecutive group of them. */
1837: for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++)
1838: if (regmask[j] && j + group_size[i] <= FIRST_PSEUDO_REGISTER
1839: /* Next line in case group-mode for this class
1840: demands an even-odd pair. */
1841: && HARD_REGNO_MODE_OK (j, group_mode[i]))
1842: {
1843: int k;
1844: for (k = 1; k < group_size[i]; k++)
1845: if (! regmask[j + k])
1846: break;
1847: if (k == group_size[i])
1848: {
1849: /* We found a group. Mark it off against this class's
1850: need for groups, and against each superclass too. */
1851: register enum reg_class *p;
1852: max_groups[i]--;
1853: p = reg_class_superclasses[i];
1854: while (*p != LIM_REG_CLASSES)
1855: max_groups[(int) *p++]--;
1856: /* Don't count these registers again. */
1857: for (k = 0; k < group_size[i]; k++)
1858: SET_HARD_REG_BIT (counted_for_groups, j + k);
1859: }
1860: j += k;
1861: }
1862: }
1863:
1864: }
1865:
1866: /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
1867: another mode that needs to be reloaded for the same register class CLASS.
1868: If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
1869: ALLOCATE_MODE will never be smaller than OTHER_MODE.
1870:
1871: This code used to also fail if any reg in CLASS allows OTHER_MODE but not
1872: ALLOCATE_MODE. This test is unnecessary, because we will never try to put
1873: something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
1874: causes unnecessary failures on machines requiring alignment of register
1875: groups when the two modes are different sizes, because the larger mode has
1876: more strict alignment rules than the smaller mode. */
1877:
1878: static int
1879: modes_equiv_for_class_p (allocate_mode, other_mode, class)
1880: enum machine_mode allocate_mode, other_mode;
1881: enum reg_class class;
1882: {
1883: register int regno;
1884: for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1885: {
1886: if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
1887: && HARD_REGNO_MODE_OK (regno, allocate_mode)
1888: && ! HARD_REGNO_MODE_OK (regno, other_mode))
1889: return 0;
1890: }
1891: return 1;
1892: }
1893:
1894: /* Add a new register to the tables of available spill-registers
1895: (as well as spilling all pseudos allocated to the register).
1896: I is the index of this register in potential_reload_regs.
1897: CLASS is the regclass whose need is being satisfied.
1898: MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
1899: so that this register can count off against them.
1900: MAX_NONGROUPS is 0 if this register is part of a group.
1901: GLOBAL and DUMPFILE are the same as the args that `reload' got. */
1902:
1903: static int
1904: new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
1905: int i;
1906: int class;
1907: int *max_needs;
1908: int *max_nongroups;
1909: int global;
1910: FILE *dumpfile;
1911: {
1912: register enum reg_class *p;
1913: int val;
1914: int regno = potential_reload_regs[i];
1915:
1916: if (i >= FIRST_PSEUDO_REGISTER)
1917: abort (); /* Caller failed to find any register. */
1918:
1919: if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
1920: fatal ("fixed or forbidden register was spilled.\n\
1921: This may be due to a compiler bug or to impossible asm statements.");
1922:
1923: /* Make reg REGNO an additional reload reg. */
1924:
1925: potential_reload_regs[i] = -1;
1926: spill_regs[n_spills] = regno;
1927: spill_reg_order[regno] = n_spills;
1928: if (dumpfile)
1929: fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
1930:
1931: /* Clear off the needs we just satisfied. */
1932:
1933: max_needs[class]--;
1934: p = reg_class_superclasses[class];
1935: while (*p != LIM_REG_CLASSES)
1936: max_needs[(int) *p++]--;
1937:
1938: if (max_nongroups && max_nongroups[class] > 0)
1939: {
1940: SET_HARD_REG_BIT (counted_for_nongroups, regno);
1941: max_nongroups[class]--;
1942: p = reg_class_superclasses[class];
1943: while (*p != LIM_REG_CLASSES)
1944: max_nongroups[(int) *p++]--;
1945: }
1946:
1947: /* Spill every pseudo reg that was allocated to this reg
1948: or to something that overlaps this reg. */
1949:
1950: val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
1951:
1952: /* If there are some registers still to eliminate and this register
1953: wasn't ever used before, additional stack space may have to be
1954: allocated to store this register. Thus, we may have changed the offset
1955: between the stack and frame pointers, so mark that something has changed.
1956: (If new pseudos were spilled, thus requiring more space, VAL would have
1957: been set non-zero by the call to spill_hard_reg above since additional
1958: reloads may be needed in that case.
1959:
1960: One might think that we need only set VAL to 1 if this is a call-used
1961: register. However, the set of registers that must be saved by the
1962: prologue is not identical to the call-used set. For example, the
1963: register used by the call insn for the return PC is a call-used register,
1964: but must be saved by the prologue. */
1965: if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
1966: val = 1;
1967:
1968: regs_ever_live[spill_regs[n_spills]] = 1;
1969: n_spills++;
1970:
1971: return val;
1972: }
1973:
1974: /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1975: data that is dead in INSN. */
1976:
1977: static void
1978: delete_dead_insn (insn)
1979: rtx insn;
1980: {
1981: rtx prev = prev_real_insn (insn);
1982: rtx prev_dest;
1983:
1984: /* If the previous insn sets a register that dies in our insn, delete it
1985: too. */
1986: if (prev && GET_CODE (PATTERN (prev)) == SET
1987: && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1988: && reg_mentioned_p (prev_dest, PATTERN (insn))
1989: && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
1990: delete_dead_insn (prev);
1991:
1992: PUT_CODE (insn, NOTE);
1993: NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1994: NOTE_SOURCE_FILE (insn) = 0;
1995: }
1996:
1997: /* Modify the home of pseudo-reg I.
1998: The new home is present in reg_renumber[I].
1999:
2000: FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2001: or it may be -1, meaning there is none or it is not relevant.
2002: This is used so that all pseudos spilled from a given hard reg
2003: can share one stack slot. */
2004:
2005: static void
2006: alter_reg (i, from_reg)
2007: register int i;
2008: int from_reg;
2009: {
2010: /* When outputting an inline function, this can happen
2011: for a reg that isn't actually used. */
2012: if (regno_reg_rtx[i] == 0)
2013: return;
2014:
2015: /* If the reg got changed to a MEM at rtl-generation time,
2016: ignore it. */
2017: if (GET_CODE (regno_reg_rtx[i]) != REG)
2018: return;
2019:
2020: /* Modify the reg-rtx to contain the new hard reg
2021: number or else to contain its pseudo reg number. */
2022: REGNO (regno_reg_rtx[i])
2023: = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2024:
2025: /* If we have a pseudo that is needed but has no hard reg or equivalent,
2026: allocate a stack slot for it. */
2027:
2028: if (reg_renumber[i] < 0
2029: && reg_n_refs[i] > 0
2030: && reg_equiv_constant[i] == 0
2031: && reg_equiv_memory_loc[i] == 0)
2032: {
2033: register rtx x;
2034: int inherent_size = PSEUDO_REGNO_BYTES (i);
2035: int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2036: int adjust = 0;
2037:
2038: /* Each pseudo reg has an inherent size which comes from its own mode,
2039: and a total size which provides room for paradoxical subregs
2040: which refer to the pseudo reg in wider modes.
2041:
2042: We can use a slot already allocated if it provides both
2043: enough inherent space and enough total space.
2044: Otherwise, we allocate a new slot, making sure that it has no less
2045: inherent space, and no less total space, then the previous slot. */
2046: if (from_reg == -1)
2047: {
2048: /* No known place to spill from => no slot to reuse. */
2049: x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2050: #if BYTES_BIG_ENDIAN
2051: /* Cancel the big-endian correction done in assign_stack_local.
2052: Get the address of the beginning of the slot.
2053: This is so we can do a big-endian correction unconditionally
2054: below. */
2055: adjust = inherent_size - total_size;
2056: #endif
2057: }
2058: /* Reuse a stack slot if possible. */
2059: else if (spill_stack_slot[from_reg] != 0
2060: && spill_stack_slot_width[from_reg] >= total_size
2061: && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2062: >= inherent_size))
2063: x = spill_stack_slot[from_reg];
2064: /* Allocate a bigger slot. */
2065: else
2066: {
2067: /* Compute maximum size needed, both for inherent size
2068: and for total size. */
2069: enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2070: if (spill_stack_slot[from_reg])
2071: {
2072: if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2073: > inherent_size)
2074: mode = GET_MODE (spill_stack_slot[from_reg]);
2075: if (spill_stack_slot_width[from_reg] > total_size)
2076: total_size = spill_stack_slot_width[from_reg];
2077: }
2078: /* Make a slot with that size. */
2079: x = assign_stack_local (mode, total_size, -1);
2080: #if BYTES_BIG_ENDIAN
2081: /* Cancel the big-endian correction done in assign_stack_local.
2082: Get the address of the beginning of the slot.
2083: This is so we can do a big-endian correction unconditionally
2084: below. */
2085: adjust = GET_MODE_SIZE (mode) - total_size;
2086: #endif
2087: spill_stack_slot[from_reg] = x;
2088: spill_stack_slot_width[from_reg] = total_size;
2089: }
2090:
2091: #if BYTES_BIG_ENDIAN
2092: /* On a big endian machine, the "address" of the slot
2093: is the address of the low part that fits its inherent mode. */
2094: if (inherent_size < total_size)
2095: adjust += (total_size - inherent_size);
2096: #endif /* BYTES_BIG_ENDIAN */
2097:
2098: /* If we have any adjustment to make, or if the stack slot is the
2099: wrong mode, make a new stack slot. */
2100: if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2101: {
2102: x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2103: plus_constant (XEXP (x, 0), adjust));
2104: RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2105: }
2106:
2107: /* Save the stack slot for later. */
2108: reg_equiv_memory_loc[i] = x;
2109: }
2110: }
2111:
2112: /* Mark the slots in regs_ever_live for the hard regs
2113: used by pseudo-reg number REGNO. */
2114:
2115: void
2116: mark_home_live (regno)
2117: int regno;
2118: {
2119: register int i, lim;
2120: i = reg_renumber[regno];
2121: if (i < 0)
2122: return;
2123: lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2124: while (i < lim)
2125: regs_ever_live[i++] = 1;
2126: }
2127:
2128: /* This function handles the tracking of elimination offsets around branches.
2129:
2130: X is a piece of RTL being scanned.
2131:
2132: INSN is the insn that it came from, if any.
2133:
2134: INITIAL_P is non-zero if we are to set the offset to be the initial
2135: offset and zero if we are setting the offset of the label to be the
2136: current offset. */
2137:
2138: static void
2139: set_label_offsets (x, insn, initial_p)
2140: rtx x;
2141: rtx insn;
2142: int initial_p;
2143: {
2144: enum rtx_code code = GET_CODE (x);
2145: rtx tem;
2146: int i;
2147: struct elim_table *p;
2148:
2149: switch (code)
2150: {
2151: case LABEL_REF:
2152: x = XEXP (x, 0);
2153:
2154: /* ... fall through ... */
2155:
2156: case CODE_LABEL:
2157: /* If we know nothing about this label, set the desired offsets. Note
2158: that this sets the offset at a label to be the offset before a label
2159: if we don't know anything about the label. This is not correct for
2160: the label after a BARRIER, but is the best guess we can make. If
2161: we guessed wrong, we will suppress an elimination that might have
2162: been possible had we been able to guess correctly. */
2163:
2164: if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2165: {
2166: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2167: offsets_at[CODE_LABEL_NUMBER (x)][i]
2168: = (initial_p ? reg_eliminate[i].initial_offset
2169: : reg_eliminate[i].offset);
2170: offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2171: }
2172:
2173: /* Otherwise, if this is the definition of a label and it is
1.1.1.2 ! root 2174: preceded by a BARRIER, set our offsets to the known offset of
1.1 root 2175: that label. */
2176:
2177: else if (x == insn
2178: && (tem = prev_nonnote_insn (insn)) != 0
2179: && GET_CODE (tem) == BARRIER)
2180: {
2181: num_not_at_initial_offset = 0;
2182: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2183: {
2184: reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2185: = offsets_at[CODE_LABEL_NUMBER (x)][i];
1.1.1.2 ! root 2186: if (reg_eliminate[i].can_eliminate
! 2187: && (reg_eliminate[i].offset
! 2188: != reg_eliminate[i].initial_offset))
1.1 root 2189: num_not_at_initial_offset++;
2190: }
2191: }
2192:
2193: else
2194: /* If neither of the above cases is true, compare each offset
2195: with those previously recorded and suppress any eliminations
2196: where the offsets disagree. */
2197:
2198: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2199: if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2200: != (initial_p ? reg_eliminate[i].initial_offset
2201: : reg_eliminate[i].offset))
2202: reg_eliminate[i].can_eliminate = 0;
2203:
2204: return;
2205:
2206: case JUMP_INSN:
2207: set_label_offsets (PATTERN (insn), insn, initial_p);
2208:
2209: /* ... fall through ... */
2210:
2211: case INSN:
2212: case CALL_INSN:
2213: /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2214: and hence must have all eliminations at their initial offsets. */
2215: for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2216: if (REG_NOTE_KIND (tem) == REG_LABEL)
2217: set_label_offsets (XEXP (tem, 0), insn, 1);
2218: return;
2219:
2220: case ADDR_VEC:
2221: case ADDR_DIFF_VEC:
2222: /* Each of the labels in the address vector must be at their initial
2223: offsets. We want the first first for ADDR_VEC and the second
2224: field for ADDR_DIFF_VEC. */
2225:
2226: for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2227: set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2228: insn, initial_p);
2229: return;
2230:
2231: case SET:
2232: /* We only care about setting PC. If the source is not RETURN,
2233: IF_THEN_ELSE, or a label, disable any eliminations not at
2234: their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2235: isn't one of those possibilities. For branches to a label,
2236: call ourselves recursively.
2237:
2238: Note that this can disable elimination unnecessarily when we have
2239: a non-local goto since it will look like a non-constant jump to
2240: someplace in the current function. This isn't a significant
2241: problem since such jumps will normally be when all elimination
2242: pairs are back to their initial offsets. */
2243:
2244: if (SET_DEST (x) != pc_rtx)
2245: return;
2246:
2247: switch (GET_CODE (SET_SRC (x)))
2248: {
2249: case PC:
2250: case RETURN:
2251: return;
2252:
2253: case LABEL_REF:
2254: set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2255: return;
2256:
2257: case IF_THEN_ELSE:
2258: tem = XEXP (SET_SRC (x), 1);
2259: if (GET_CODE (tem) == LABEL_REF)
2260: set_label_offsets (XEXP (tem, 0), insn, initial_p);
2261: else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2262: break;
2263:
2264: tem = XEXP (SET_SRC (x), 2);
2265: if (GET_CODE (tem) == LABEL_REF)
2266: set_label_offsets (XEXP (tem, 0), insn, initial_p);
2267: else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2268: break;
2269: return;
2270: }
2271:
2272: /* If we reach here, all eliminations must be at their initial
2273: offset because we are doing a jump to a variable address. */
2274: for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2275: if (p->offset != p->initial_offset)
2276: p->can_eliminate = 0;
2277: }
2278: }
2279:
2280: /* Used for communication between the next two function to properly share
2281: the vector for an ASM_OPERANDS. */
2282:
2283: static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2284:
2285: /* Scan X and replace any eliminable registers (such as fp) with a
2286: replacement (such as sp), plus an offset.
2287:
2288: MEM_MODE is the mode of an enclosing MEM. We need this to know how
2289: much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2290: MEM, we are allowed to replace a sum of a register and the constant zero
2291: with the register, which we cannot do outside a MEM. In addition, we need
2292: to record the fact that a register is referenced outside a MEM.
2293:
2294: If INSN is nonzero, it is the insn containing X. If we replace a REG
2295: in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2296: CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2297: that the REG is being modified.
2298:
2299: If we see a modification to a register we know about, take the
2300: appropriate action (see case SET, below).
2301:
2302: REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2303: replacements done assuming all offsets are at their initial values. If
2304: they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2305: encounter, return the actual location so that find_reloads will do
2306: the proper thing. */
2307:
2308: rtx
2309: eliminate_regs (x, mem_mode, insn)
2310: rtx x;
2311: enum machine_mode mem_mode;
2312: rtx insn;
2313: {
2314: enum rtx_code code = GET_CODE (x);
2315: struct elim_table *ep;
2316: int regno;
2317: rtx new;
2318: int i, j;
2319: char *fmt;
2320: int copied = 0;
2321:
2322: switch (code)
2323: {
2324: case CONST_INT:
2325: case CONST_DOUBLE:
2326: case CONST:
2327: case SYMBOL_REF:
2328: case CODE_LABEL:
2329: case PC:
2330: case CC0:
2331: case ASM_INPUT:
2332: case ADDR_VEC:
2333: case ADDR_DIFF_VEC:
2334: case RETURN:
2335: return x;
2336:
2337: case REG:
2338: regno = REGNO (x);
2339:
2340: /* First handle the case where we encounter a bare register that
2341: is eliminable. Replace it with a PLUS. */
2342: if (regno < FIRST_PSEUDO_REGISTER)
2343: {
2344: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2345: ep++)
2346: if (ep->from_rtx == x && ep->can_eliminate)
2347: {
2348: if (! mem_mode)
2349: ep->ref_outside_mem = 1;
2350: return plus_constant (ep->to_rtx, ep->previous_offset);
2351: }
2352:
2353: }
2354: else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2355: && (reg_equiv_address[regno] || num_not_at_initial_offset))
2356: {
2357: /* In this case, find_reloads would attempt to either use an
2358: incorrect address (if something is not at its initial offset)
2359: or substitute an replaced address into an insn (which loses
2360: if the offset is changed by some later action). So we simply
2361: return the replaced stack slot (assuming it is changed by
2362: elimination) and ignore the fact that this is actually a
2363: reference to the pseudo. Ensure we make a copy of the
2364: address in case it is shared. */
2365: new = eliminate_regs (reg_equiv_memory_loc[regno], mem_mode, 0);
2366: if (new != reg_equiv_memory_loc[regno])
2367: return copy_rtx (new);
2368: }
2369: return x;
2370:
2371: case PLUS:
2372: /* If this is the sum of an eliminable register and a constant, rework
2373: the sum. */
2374: if (GET_CODE (XEXP (x, 0)) == REG
2375: && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2376: && CONSTANT_P (XEXP (x, 1)))
2377: {
2378: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2379: ep++)
2380: if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2381: {
2382: if (! mem_mode)
2383: ep->ref_outside_mem = 1;
2384:
2385: /* The only time we want to replace a PLUS with a REG (this
2386: occurs when the constant operand of the PLUS is the negative
2387: of the offset) is when we are inside a MEM. We won't want
2388: to do so at other times because that would change the
2389: structure of the insn in a way that reload can't handle.
2390: We special-case the commonest situation in
2391: eliminate_regs_in_insn, so just replace a PLUS with a
2392: PLUS here, unless inside a MEM. */
2393: if (mem_mode && GET_CODE (XEXP (x, 1)) == CONST_INT
2394: && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2395: return ep->to_rtx;
2396: else
2397: return gen_rtx (PLUS, Pmode, ep->to_rtx,
2398: plus_constant (XEXP (x, 1),
2399: ep->previous_offset));
2400: }
2401:
2402: /* If the register is not eliminable, we are done since the other
2403: operand is a constant. */
2404: return x;
2405: }
2406:
2407: /* If this is part of an address, we want to bring any constant to the
2408: outermost PLUS. We will do this by doing register replacement in
2409: our operands and seeing if a constant shows up in one of them.
2410:
2411: We assume here this is part of an address (or a "load address" insn)
2412: since an eliminable register is not likely to appear in any other
2413: context.
2414:
2415: If we have (plus (eliminable) (reg)), we want to produce
2416: (plus (plus (replacement) (reg) (const))). If this was part of a
2417: normal add insn, (plus (replacement) (reg)) will be pushed as a
2418: reload. This is the desired action. */
2419:
2420: {
2421: rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, 0);
2422: rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, 0);
2423:
2424: if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2425: {
2426: /* If one side is a PLUS and the other side is a pseudo that
2427: didn't get a hard register but has a reg_equiv_constant,
2428: we must replace the constant here since it may no longer
2429: be in the position of any operand. */
2430: if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2431: && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2432: && reg_renumber[REGNO (new1)] < 0
2433: && reg_equiv_constant != 0
2434: && reg_equiv_constant[REGNO (new1)] != 0)
2435: new1 = reg_equiv_constant[REGNO (new1)];
2436: else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2437: && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2438: && reg_renumber[REGNO (new0)] < 0
2439: && reg_equiv_constant[REGNO (new0)] != 0)
2440: new0 = reg_equiv_constant[REGNO (new0)];
2441:
2442: new = form_sum (new0, new1);
2443:
2444: /* As above, if we are not inside a MEM we do not want to
2445: turn a PLUS into something else. We might try to do so here
2446: for an addition of 0 if we aren't optimizing. */
2447: if (! mem_mode && GET_CODE (new) != PLUS)
2448: return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2449: else
2450: return new;
2451: }
2452: }
2453: return x;
2454:
2455: case EXPR_LIST:
2456: /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2457: if (XEXP (x, 0))
2458: {
2459: new = eliminate_regs (XEXP (x, 0), mem_mode, 0);
2460: if (new != XEXP (x, 0))
2461: x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2462: }
2463:
2464: /* ... fall through ... */
2465:
2466: case INSN_LIST:
2467: /* Now do eliminations in the rest of the chain. If this was
2468: an EXPR_LIST, this might result in allocating more memory than is
2469: strictly needed, but it simplifies the code. */
2470: if (XEXP (x, 1))
2471: {
2472: new = eliminate_regs (XEXP (x, 1), mem_mode, 0);
2473: if (new != XEXP (x, 1))
2474: return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new);
2475: }
2476: return x;
2477:
2478: case CALL:
2479: case COMPARE:
2480: case MINUS:
2481: case MULT:
2482: case DIV: case UDIV:
2483: case MOD: case UMOD:
2484: case AND: case IOR: case XOR:
2485: case LSHIFT: case ASHIFT: case ROTATE:
2486: case ASHIFTRT: case LSHIFTRT: case ROTATERT:
2487: case NE: case EQ:
2488: case GE: case GT: case GEU: case GTU:
2489: case LE: case LT: case LEU: case LTU:
2490: {
2491: rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, 0);
2492: rtx new1 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, 0) : 0;
2493:
2494: if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2495: return gen_rtx (code, GET_MODE (x), new0, new1);
2496: }
2497: return x;
2498:
2499: case PRE_INC:
2500: case POST_INC:
2501: case PRE_DEC:
2502: case POST_DEC:
2503: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2504: if (ep->to_rtx == XEXP (x, 0))
2505: {
2506: if (code == PRE_DEC || code == POST_DEC)
2507: ep->offset += GET_MODE_SIZE (mem_mode);
2508: else
2509: ep->offset -= GET_MODE_SIZE (mem_mode);
2510: }
2511:
2512: /* Fall through to generic unary operation case. */
2513: case USE:
2514: case STRICT_LOW_PART:
2515: case NEG: case NOT:
2516: case SIGN_EXTEND: case ZERO_EXTEND:
2517: case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2518: case FLOAT: case FIX:
2519: case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2520: case ABS:
2521: case SQRT:
2522: case FFS:
2523: new = eliminate_regs (XEXP (x, 0), mem_mode, 0);
2524: if (new != XEXP (x, 0))
2525: return gen_rtx (code, GET_MODE (x), new);
2526: return x;
2527:
2528: case SUBREG:
2529: /* Similar to above processing, but preserve SUBREG_WORD.
2530: Convert (subreg (mem)) to (mem) if not paradoxical.
2531: Also, if we have a non-paradoxical (subreg (pseudo)) and the
2532: pseudo didn't get a hard reg, we must replace this with the
2533: eliminated version of the memory location because push_reloads
2534: may do the replacement in certain circumstances. */
2535: if (GET_CODE (SUBREG_REG (x)) == REG
2536: && (GET_MODE_SIZE (GET_MODE (x))
2537: <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2538: && reg_equiv_memory_loc != 0
2539: && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2540: {
2541: new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2542: mem_mode, 0);
2543:
2544: /* If we didn't change anything, we must retain the pseudo. */
2545: if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2546: new = XEXP (x, 0);
2547: else
2548: /* Otherwise, ensure NEW isn't shared in case we have to reload
2549: it. */
2550: new = copy_rtx (new);
2551: }
2552: else
2553: new = eliminate_regs (SUBREG_REG (x), mem_mode, 0);
2554:
2555: if (new != XEXP (x, 0))
2556: {
2557: if (GET_CODE (new) == MEM
2558: && (GET_MODE_SIZE (GET_MODE (x))
2559: <= GET_MODE_SIZE (GET_MODE (new))))
2560: {
2561: int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2562: enum machine_mode mode = GET_MODE (x);
2563:
2564: #if BYTES_BIG_ENDIAN
2565: offset += (MIN (UNITS_PER_WORD,
2566: GET_MODE_SIZE (GET_MODE (new)))
2567: - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2568: #endif
2569:
2570: PUT_MODE (new, mode);
2571: XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2572: return new;
2573: }
2574: else
2575: return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
2576: }
2577:
2578: return x;
2579:
2580: case CLOBBER:
2581: /* If clobbering a register that is the replacement register for an
1.1.1.2 ! root 2582: elimination we still think can be performed, note that it cannot
1.1 root 2583: be performed. Otherwise, we need not be concerned about it. */
2584: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2585: if (ep->to_rtx == XEXP (x, 0))
2586: ep->can_eliminate = 0;
2587:
2588: return x;
2589:
2590: case ASM_OPERANDS:
2591: {
2592: rtx *temp_vec;
2593: /* Properly handle sharing input and constraint vectors. */
2594: if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2595: {
2596: /* When we come to a new vector not seen before,
2597: scan all its elements; keep the old vector if none
2598: of them changes; otherwise, make a copy. */
2599: old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
2600: temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
2601: for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2602: temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
2603: mem_mode, 0);
2604:
2605: for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2606: if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
2607: break;
2608:
2609: if (i == ASM_OPERANDS_INPUT_LENGTH (x))
2610: new_asm_operands_vec = old_asm_operands_vec;
2611: else
2612: new_asm_operands_vec
2613: = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
2614: }
2615:
2616: /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2617: if (new_asm_operands_vec == old_asm_operands_vec)
2618: return x;
2619:
2620: new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
2621: ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
2622: ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
2623: ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
2624: ASM_OPERANDS_SOURCE_FILE (x),
2625: ASM_OPERANDS_SOURCE_LINE (x));
2626: new->volatil = x->volatil;
2627: return new;
2628: }
2629:
2630: case SET:
2631: /* Check for setting a register that we know about. */
2632: if (GET_CODE (SET_DEST (x)) == REG)
2633: {
2634: /* See if this is setting the replacement register for an
2635: elimination.
2636:
2637: If DEST is the frame pointer, we do nothing because we assume that
2638: all assignments to the frame pointer are for non-local gotos and
2639: are being done at a time when they are valid and do not disturb
2640: anything else. Some machines want to eliminate a fake argument
2641: pointer with either the frame or stack pointer. Assignments to
2642: the frame pointer must not prevent this elimination. */
2643:
2644: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2645: ep++)
2646: if (ep->to_rtx == SET_DEST (x)
2647: && SET_DEST (x) != frame_pointer_rtx)
2648: {
2649: /* If it is being incrememented, adjust the offset. Otherwise,
2650: this elimination can't be done. */
2651: rtx src = SET_SRC (x);
2652:
2653: if (GET_CODE (src) == PLUS
2654: && XEXP (src, 0) == SET_DEST (x)
2655: && GET_CODE (XEXP (src, 1)) == CONST_INT)
2656: ep->offset -= INTVAL (XEXP (src, 1));
2657: else
2658: ep->can_eliminate = 0;
2659: }
2660:
2661: /* Now check to see we are assigning to a register that can be
2662: eliminated. If so, it must be as part of a PARALLEL, since we
2663: will not have been called if this is a single SET. So indicate
2664: that we can no longer eliminate this reg. */
2665: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2666: ep++)
2667: if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
2668: ep->can_eliminate = 0;
2669: }
2670:
2671: /* Now avoid the loop below in this common case. */
2672: {
2673: rtx new0 = eliminate_regs (SET_DEST (x), 0, 0);
2674: rtx new1 = eliminate_regs (SET_SRC (x), 0, 0);
2675:
2676: /* If SET_DEST changed from a REG to a MEM and INSN is non-zero,
2677: write a CLOBBER insn. */
2678: if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
2679: && insn != 0)
2680: emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
2681:
2682: if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
2683: return gen_rtx (SET, VOIDmode, new0, new1);
2684: }
2685:
2686: return x;
2687:
2688: case MEM:
2689: /* Our only special processing is to pass the mode of the MEM to our
2690: recursive call and copy the flags. While we are here, handle this
2691: case more efficiently. */
2692: new = eliminate_regs (XEXP (x, 0), GET_MODE (x), 0);
2693: if (new != XEXP (x, 0))
2694: {
2695: new = gen_rtx (MEM, GET_MODE (x), new);
2696: new->volatil = x->volatil;
2697: new->unchanging = x->unchanging;
2698: new->in_struct = x->in_struct;
2699: return new;
2700: }
2701: else
2702: return x;
2703: }
2704:
2705: /* Process each of our operands recursively. If any have changed, make a
2706: copy of the rtx. */
2707: fmt = GET_RTX_FORMAT (code);
2708: for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2709: {
2710: if (*fmt == 'e')
2711: {
2712: new = eliminate_regs (XEXP (x, i), mem_mode, 0);
2713: if (new != XEXP (x, i) && ! copied)
2714: {
2715: rtx new_x = rtx_alloc (code);
2716: bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2717: + (sizeof (new_x->fld[0])
2718: * GET_RTX_LENGTH (code))));
2719: x = new_x;
2720: copied = 1;
2721: }
2722: XEXP (x, i) = new;
2723: }
2724: else if (*fmt == 'E')
2725: {
2726: int copied_vec = 0;
2727: for (j = 0; j < XVECLEN (x, i); j++)
2728: {
2729: new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2730: if (new != XVECEXP (x, i, j) && ! copied_vec)
2731: {
2732: rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2733: &XVECEXP (x, i, 0));
2734: if (! copied)
2735: {
2736: rtx new_x = rtx_alloc (code);
2737: bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2738: + (sizeof (new_x->fld[0])
2739: * GET_RTX_LENGTH (code))));
2740: x = new_x;
2741: copied = 1;
2742: }
2743: XVEC (x, i) = new_v;
2744: copied_vec = 1;
2745: }
2746: XVECEXP (x, i, j) = new;
2747: }
2748: }
2749: }
2750:
2751: return x;
2752: }
2753:
2754: /* Scan INSN and eliminate all eliminable registers in it.
2755:
2756: If REPLACE is nonzero, do the replacement destructively. Also
2757: delete the insn as dead it if it is setting an eliminable register.
2758:
2759: If REPLACE is zero, do all our allocations in reload_obstack.
2760:
2761: If no eliminations were done and this insn doesn't require any elimination
2762: processing (these are not identical conditions: it might be updating sp,
2763: but not referencing fp; this needs to be seen during reload_as_needed so
2764: that the offset between fp and sp can be taken into consideration), zero
2765: is returned. Otherwise, 1 is returned. */
2766:
2767: static int
2768: eliminate_regs_in_insn (insn, replace)
2769: rtx insn;
2770: int replace;
2771: {
2772: rtx old_body = PATTERN (insn);
2773: rtx new_body;
2774: int val = 0;
2775: struct elim_table *ep;
2776:
2777: if (! replace)
2778: push_obstacks (&reload_obstack, &reload_obstack);
2779:
2780: if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG
2781: && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER)
2782: {
2783: /* Check for setting an eliminable register. */
2784: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2785: if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate)
2786: {
2787: /* In this case this insn isn't serving a useful purpose. We
2788: will delete it in reload_as_needed once we know that this
2789: elimination is, in fact, being done.
2790:
2791: If REPLACE isn't set, we can't delete this insn, but neededn't
2792: process it since it won't be used unless something changes. */
2793: if (replace)
2794: delete_dead_insn (insn);
2795: val = 1;
2796: goto done;
2797: }
2798:
2799: /* Check for (set (reg) (plus (reg from) (offset))) where the offset
2800: in the insn is the negative of the offset in FROM. Substitute
2801: (set (reg) (reg to)) for the insn and change its code.
2802:
2803: We have to do this here, rather than in eliminate_regs, do that we can
2804: change the insn code. */
2805:
2806: if (GET_CODE (SET_SRC (old_body)) == PLUS
2807: && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG
2808: && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT)
2809: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2810: ep++)
2811: if (ep->from_rtx == XEXP (SET_SRC (old_body), 0)
2812: && ep->can_eliminate
2813: && ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1)))
2814: {
2815: PATTERN (insn) = gen_rtx (SET, VOIDmode,
2816: SET_DEST (old_body), ep->to_rtx);
2817: INSN_CODE (insn) = -1;
2818: val = 1;
2819: goto done;
2820: }
2821: }
2822:
2823: old_asm_operands_vec = 0;
2824:
2825: /* Replace the body of this insn with a substituted form. If we changed
2826: something, return non-zero. If this is the final call for this
2827: insn (REPLACE is non-zero), do the elimination in REG_NOTES as well.
2828:
2829: If we are replacing a body that was a (set X (plus Y Z)), try to
2830: re-recognize the insn. We do this in case we had a simple addition
2831: but now can do this as a load-address. This saves an insn in this
2832: common case. */
2833:
2834: new_body = eliminate_regs (old_body, 0, replace ? insn : 0);
2835: if (new_body != old_body)
2836: {
2837: if (GET_CODE (old_body) != SET || GET_CODE (SET_SRC (old_body)) != PLUS
2838: || ! validate_change (insn, &PATTERN (insn), new_body, 0))
2839: PATTERN (insn) = new_body;
2840:
2841: if (replace && REG_NOTES (insn))
2842: REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, 0);
2843: val = 1;
2844: }
2845:
2846: /* Loop through all elimination pairs. See if any have changed and
2847: recalculate the number not at initial offset.
2848:
2849: Compute the maximum offset (minimum offset if the stack does not
2850: grow downward) for each elimination pair.
2851:
2852: We also detect a cases where register elimination cannot be done,
2853: namely, if a register would be both changed and referenced outside a MEM
2854: in the resulting insn since such an insn is often undefined and, even if
2855: not, we cannot know what meaning will be given to it. Note that it is
2856: valid to have a register used in an address in an insn that changes it
2857: (presumably with a pre- or post-increment or decrement).
2858:
2859: If anything changes, return nonzero. */
2860:
2861: num_not_at_initial_offset = 0;
2862: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2863: {
2864: if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
2865: ep->can_eliminate = 0;
2866:
2867: ep->ref_outside_mem = 0;
2868:
2869: if (ep->previous_offset != ep->offset)
2870: val = 1;
2871:
2872: ep->previous_offset = ep->offset;
2873: if (ep->can_eliminate && ep->offset != ep->initial_offset)
2874: num_not_at_initial_offset++;
2875:
2876: #ifdef STACK_GROWS_DOWNWARD
2877: ep->max_offset = MAX (ep->max_offset, ep->offset);
2878: #else
2879: ep->max_offset = MIN (ep->max_offset, ep->offset);
2880: #endif
2881: }
2882:
2883: done:
2884: if (! replace)
2885: pop_obstacks ();
2886:
2887: return val;
2888: }
2889:
2890: /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
2891: replacement we currently believe is valid, mark it as not eliminable if X
2892: modifies DEST in any way other than by adding a constant integer to it.
2893:
2894: If DEST is the frame pointer, we do nothing because we assume that
2895: all assignments to the frame pointer are nonlocal gotos and are being done
2896: at a time when they are valid and do not disturb anything else.
2897: Some machines want to eliminate a fake argument pointer with either the
2898: frame or stack pointer. Assignments to the frame pointer must not prevent
2899: this elimination.
2900:
2901: Called via note_stores from reload before starting its passes to scan
2902: the insns of the function. */
2903:
2904: static void
2905: mark_not_eliminable (dest, x)
2906: rtx dest;
2907: rtx x;
2908: {
2909: register int i;
2910:
2911: /* A SUBREG of a hard register here is just changing its mode. We should
2912: not see a SUBREG of an eliminable hard register, but check just in
2913: case. */
2914: if (GET_CODE (dest) == SUBREG)
2915: dest = SUBREG_REG (dest);
2916:
2917: if (dest == frame_pointer_rtx)
2918: return;
2919:
2920: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2921: if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
2922: && (GET_CODE (x) != SET
2923: || GET_CODE (SET_SRC (x)) != PLUS
2924: || XEXP (SET_SRC (x), 0) != dest
2925: || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
2926: {
2927: reg_eliminate[i].can_eliminate_previous
2928: = reg_eliminate[i].can_eliminate = 0;
2929: num_eliminable--;
2930: }
2931: }
2932:
2933: /* Kick all pseudos out of hard register REGNO.
2934: If GLOBAL is nonzero, try to find someplace else to put them.
2935: If DUMPFILE is nonzero, log actions taken on that file.
2936:
2937: If CANT_ELIMINATE is nonzero, it means that we are doing this spill
2938: because we found we can't eliminate some register. In the case, no pseudos
2939: are allowed to be in the register, even if they are only in a block that
2940: doesn't require spill registers, unlike the case when we are spilling this
2941: hard reg to produce another spill register.
2942:
2943: Return nonzero if any pseudos needed to be kicked out. */
2944:
2945: static int
2946: spill_hard_reg (regno, global, dumpfile, cant_eliminate)
2947: register int regno;
2948: int global;
2949: FILE *dumpfile;
2950: int cant_eliminate;
2951: {
2952: int something_changed = 0;
2953: register int i;
2954:
2955: SET_HARD_REG_BIT (forbidden_regs, regno);
2956:
2957: /* Spill every pseudo reg that was allocated to this reg
2958: or to something that overlaps this reg. */
2959:
2960: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2961: if (reg_renumber[i] >= 0
2962: && reg_renumber[i] <= regno
2963: && (reg_renumber[i]
2964: + HARD_REGNO_NREGS (reg_renumber[i],
2965: PSEUDO_REGNO_MODE (i))
2966: > regno))
2967: {
2968: enum reg_class class = REGNO_REG_CLASS (regno);
2969:
2970: /* If this register belongs solely to a basic block which needed no
2971: spilling of any class that this register is contained in,
2972: leave it be, unless we are spilling this register because
2973: it was a hard register that can't be eliminated. */
2974:
2975: if (! cant_eliminate
2976: && basic_block_needs[0]
2977: && reg_basic_block[i] >= 0
2978: && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
2979: {
2980: enum reg_class *p;
2981:
2982: for (p = reg_class_superclasses[(int) class];
2983: *p != LIM_REG_CLASSES; p++)
2984: if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
2985: break;
2986:
2987: if (*p == LIM_REG_CLASSES)
2988: continue;
2989: }
2990:
2991: /* Mark it as no longer having a hard register home. */
2992: reg_renumber[i] = -1;
2993: /* We will need to scan everything again. */
2994: something_changed = 1;
2995: if (global)
2996: retry_global_alloc (i, forbidden_regs);
2997:
2998: alter_reg (i, regno);
2999: if (dumpfile)
3000: {
3001: if (reg_renumber[i] == -1)
3002: fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3003: else
3004: fprintf (dumpfile, " Register %d now in %d.\n\n",
3005: i, reg_renumber[i]);
3006: }
3007: }
3008:
3009: return something_changed;
3010: }
3011:
3012: /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3013:
3014: static void
3015: scan_paradoxical_subregs (x)
3016: register rtx x;
3017: {
3018: register int i;
3019: register char *fmt;
3020: register enum rtx_code code = GET_CODE (x);
3021:
3022: switch (code)
3023: {
3024: case CONST_INT:
3025: case CONST:
3026: case SYMBOL_REF:
3027: case LABEL_REF:
3028: case CONST_DOUBLE:
3029: case CC0:
3030: case PC:
3031: case REG:
3032: case USE:
3033: case CLOBBER:
3034: return;
3035:
3036: case SUBREG:
3037: if (GET_CODE (SUBREG_REG (x)) == REG
3038: && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3039: reg_max_ref_width[REGNO (SUBREG_REG (x))]
3040: = GET_MODE_SIZE (GET_MODE (x));
3041: return;
3042: }
3043:
3044: fmt = GET_RTX_FORMAT (code);
3045: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3046: {
3047: if (fmt[i] == 'e')
3048: scan_paradoxical_subregs (XEXP (x, i));
3049: else if (fmt[i] == 'E')
3050: {
3051: register int j;
3052: for (j = XVECLEN (x, i) - 1; j >=0; j--)
3053: scan_paradoxical_subregs (XVECEXP (x, i, j));
3054: }
3055: }
3056: }
3057:
3058: struct hard_reg_n_uses { int regno; int uses; };
3059:
3060: static int
3061: hard_reg_use_compare (p1, p2)
3062: struct hard_reg_n_uses *p1, *p2;
3063: {
3064: int tem = p1->uses - p2->uses;
3065: if (tem != 0) return tem;
3066: /* If regs are equally good, sort by regno,
3067: so that the results of qsort leave nothing to chance. */
3068: return p1->regno - p2->regno;
3069: }
3070:
3071: /* Choose the order to consider regs for use as reload registers
3072: based on how much trouble would be caused by spilling one.
3073: Store them in order of decreasing preference in potential_reload_regs. */
3074:
3075: static void
3076: order_regs_for_reload ()
3077: {
3078: register int i;
3079: register int o = 0;
3080: int large = 0;
3081:
3082: struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3083:
3084: CLEAR_HARD_REG_SET (bad_spill_regs);
3085:
3086: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3087: potential_reload_regs[i] = -1;
3088:
3089: /* Count number of uses of each hard reg by pseudo regs allocated to it
3090: and then order them by decreasing use. */
3091:
3092: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3093: {
3094: hard_reg_n_uses[i].uses = 0;
3095: hard_reg_n_uses[i].regno = i;
3096: }
3097:
3098: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3099: {
3100: int regno = reg_renumber[i];
3101: if (regno >= 0)
3102: {
3103: int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3104: while (regno < lim)
3105: hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3106: }
3107: large += reg_n_refs[i];
3108: }
3109:
3110: /* Now fixed registers (which cannot safely be used for reloading)
3111: get a very high use count so they will be considered least desirable.
3112: Registers used explicitly in the rtl code are almost as bad. */
3113:
3114: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3115: {
3116: if (fixed_regs[i])
3117: {
3118: hard_reg_n_uses[i].uses += 2 * large + 2;
3119: SET_HARD_REG_BIT (bad_spill_regs, i);
3120: }
3121: else if (regs_explicitly_used[i])
3122: {
3123: hard_reg_n_uses[i].uses += large + 1;
3124: /* ??? We are doing this here because of the potential that
3125: bad code may be generated if a register explicitly used in
3126: an insn was used as a spill register for that insn. But
3127: not using these are spill registers may lose on some machine.
3128: We'll have to see how this works out. */
3129: SET_HARD_REG_BIT (bad_spill_regs, i);
3130: }
3131: }
3132: hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3133: SET_HARD_REG_BIT (bad_spill_regs, FRAME_POINTER_REGNUM);
3134:
3135: #ifdef ELIMINABLE_REGS
3136: /* If registers other than the frame pointer are eliminable, mark them as
3137: poor choices. */
3138: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3139: {
3140: hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3141: SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3142: }
3143: #endif
3144:
3145: /* Prefer registers not so far used, for use in temporary loading.
3146: Among them, if REG_ALLOC_ORDER is defined, use that order.
3147: Otherwise, prefer registers not preserved by calls. */
3148:
3149: #ifdef REG_ALLOC_ORDER
3150: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3151: {
3152: int regno = reg_alloc_order[i];
3153:
3154: if (hard_reg_n_uses[regno].uses == 0)
3155: potential_reload_regs[o++] = regno;
3156: }
3157: #else
3158: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3159: {
3160: if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3161: potential_reload_regs[o++] = i;
3162: }
3163: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3164: {
3165: if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3166: potential_reload_regs[o++] = i;
3167: }
3168: #endif
3169:
3170: qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3171: sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3172:
3173: /* Now add the regs that are already used,
3174: preferring those used less often. The fixed and otherwise forbidden
3175: registers will be at the end of this list. */
3176:
3177: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3178: if (hard_reg_n_uses[i].uses != 0)
3179: potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3180: }
3181:
3182: /* Reload pseudo-registers into hard regs around each insn as needed.
3183: Additional register load insns are output before the insn that needs it
3184: and perhaps store insns after insns that modify the reloaded pseudo reg.
3185:
3186: reg_last_reload_reg and reg_reloaded_contents keep track of
3187: which pseudo-registers are already available in reload registers.
3188: We update these for the reloads that we perform,
3189: as the insns are scanned. */
3190:
3191: static void
3192: reload_as_needed (first, live_known)
3193: rtx first;
3194: int live_known;
3195: {
3196: register rtx insn;
3197: register int i;
3198: int this_block = 0;
3199: rtx x;
3200: rtx after_call = 0;
3201:
3202: bzero (spill_reg_rtx, sizeof spill_reg_rtx);
3203: reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3204: bzero (reg_last_reload_reg, max_regno * sizeof (rtx));
3205: reg_has_output_reload = (char *) alloca (max_regno);
3206: for (i = 0; i < n_spills; i++)
3207: {
3208: reg_reloaded_contents[i] = -1;
3209: reg_reloaded_insn[i] = 0;
3210: }
3211:
3212: /* Reset all offsets on eliminable registers to their initial values. */
3213: #ifdef ELIMINABLE_REGS
3214: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3215: {
3216: INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3217: reg_eliminate[i].initial_offset)
3218: reg_eliminate[i].previous_offset
3219: = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3220: }
3221: #else
3222: INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3223: reg_eliminate[0].previous_offset
3224: = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3225: #endif
3226:
3227: num_not_at_initial_offset = 0;
3228:
3229: for (insn = first; insn;)
3230: {
3231: register rtx next = NEXT_INSN (insn);
3232:
3233: /* Notice when we move to a new basic block. */
1.1.1.2 ! root 3234: if (live_known && this_block + 1 < n_basic_blocks
1.1 root 3235: && insn == basic_block_head[this_block+1])
3236: ++this_block;
3237:
3238: /* If we pass a label, copy the offsets from the label information
3239: into the current offsets of each elimination. */
3240: if (GET_CODE (insn) == CODE_LABEL)
3241: {
3242: num_not_at_initial_offset = 0;
3243: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3244: {
3245: reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3246: = offsets_at[CODE_LABEL_NUMBER (insn)][i];
1.1.1.2 ! root 3247: if (reg_eliminate[i].can_eliminate
! 3248: && (reg_eliminate[i].offset
! 3249: != reg_eliminate[i].initial_offset))
1.1 root 3250: num_not_at_initial_offset++;
3251: }
3252: }
3253:
3254: else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3255: {
3256: rtx avoid_return_reg = 0;
3257:
3258: #ifdef SMALL_REGISTER_CLASSES
3259: /* Set avoid_return_reg if this is an insn
3260: that might use the value of a function call. */
3261: if (GET_CODE (insn) == CALL_INSN)
3262: {
3263: if (GET_CODE (PATTERN (insn)) == SET)
3264: after_call = SET_DEST (PATTERN (insn));
3265: else if (GET_CODE (PATTERN (insn)) == PARALLEL
3266: && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3267: after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3268: else
3269: after_call = 0;
3270: }
3271: else if (after_call != 0
3272: && !(GET_CODE (PATTERN (insn)) == SET
3273: && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3274: {
3275: if (reg_mentioned_p (after_call, PATTERN (insn)))
3276: avoid_return_reg = after_call;
3277: after_call = 0;
3278: }
3279: #endif /* SMALL_REGISTER_CLASSES */
3280:
1.1.1.2 ! root 3281: /* If this is a USE and CLOBBER of a MEM, ensure that any
! 3282: references to eliminable registers have been removed. */
! 3283:
! 3284: if ((GET_CODE (PATTERN (insn)) == USE
! 3285: || GET_CODE (PATTERN (insn)) == CLOBBER)
! 3286: && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
! 3287: XEXP (XEXP (PATTERN (insn), 0), 0)
! 3288: = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
! 3289: GET_MODE (XEXP (PATTERN (insn), 0)), 0);
! 3290:
1.1 root 3291: /* If we need to do register elimination processing, do so.
3292: This might delete the insn, in which case we are done. */
3293: if (num_eliminable && GET_MODE (insn) == QImode)
3294: {
3295: eliminate_regs_in_insn (insn, 1);
3296: if (GET_CODE (insn) == NOTE)
3297: {
3298: insn = next;
3299: continue;
3300: }
3301: }
3302:
3303: if (GET_MODE (insn) == VOIDmode)
3304: n_reloads = 0;
3305: /* First find the pseudo regs that must be reloaded for this insn.
3306: This info is returned in the tables reload_... (see reload.h).
3307: Also modify the body of INSN by substituting RELOAD
3308: rtx's for those pseudo regs. */
3309: else
3310: {
3311: bzero (reg_has_output_reload, max_regno);
3312: CLEAR_HARD_REG_SET (reg_is_output_reload);
3313:
3314: find_reloads (insn, 1, spill_indirect_levels, live_known,
3315: spill_reg_order);
3316: }
3317:
3318: if (n_reloads > 0)
3319: {
3320: int class;
3321:
3322: /* If this block has not had spilling done for a
3323: particular class, deactivate any optional reloads
3324: of that class lest they try to use a spill-reg which isn't
3325: available here. If we have any non-optionals that need a
3326: spill reg, abort. */
3327:
3328: for (class = 0; class < N_REG_CLASSES; class++)
3329: if (basic_block_needs[class] != 0
3330: && basic_block_needs[class][this_block] == 0)
3331: for (i = 0; i < n_reloads; i++)
3332: if (class == (int) reload_reg_class[i])
3333: {
3334: if (reload_optional[i])
3335: reload_in[i] = reload_out[i] = reload_reg_rtx[i] = 0;
3336: else if (reload_reg_rtx[i] == 0)
3337: abort ();
3338: }
3339:
3340: /* Now compute which reload regs to reload them into. Perhaps
3341: reusing reload regs from previous insns, or else output
3342: load insns to reload them. Maybe output store insns too.
3343: Record the choices of reload reg in reload_reg_rtx. */
3344: choose_reload_regs (insn, avoid_return_reg);
3345:
3346: /* Generate the insns to reload operands into or out of
3347: their reload regs. */
3348: emit_reload_insns (insn);
3349:
3350: /* Substitute the chosen reload regs from reload_reg_rtx
3351: into the insn's body (or perhaps into the bodies of other
3352: load and store insn that we just made for reloading
3353: and that we moved the structure into). */
3354: subst_reloads ();
3355: }
3356: /* Any previously reloaded spilled pseudo reg, stored in this insn,
3357: is no longer validly lying around to save a future reload.
3358: Note that this does not detect pseudos that were reloaded
3359: for this insn in order to be stored in
3360: (obeying register constraints). That is correct; such reload
3361: registers ARE still valid. */
3362: note_stores (PATTERN (insn), forget_old_reloads_1);
3363:
3364: /* There may have been CLOBBER insns placed after INSN. So scan
3365: between INSN and NEXT and use them to forget old reloads. */
3366: for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3367: if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3368: note_stores (PATTERN (x), forget_old_reloads_1);
3369:
3370: #ifdef AUTO_INC_DEC
3371: /* Likewise for regs altered by auto-increment in this insn.
3372: But note that the reg-notes are not changed by reloading:
3373: they still contain the pseudo-regs, not the spill regs. */
3374: for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3375: if (REG_NOTE_KIND (x) == REG_INC)
3376: {
3377: /* See if this pseudo reg was reloaded in this insn.
3378: If so, its last-reload info is still valid
3379: because it is based on this insn's reload. */
3380: for (i = 0; i < n_reloads; i++)
3381: if (reload_out[i] == XEXP (x, 0))
3382: break;
3383:
3384: if (i != n_reloads)
3385: forget_old_reloads_1 (XEXP (x, 0));
3386: }
3387: #endif
3388: }
3389: /* A reload reg's contents are unknown after a label. */
3390: if (GET_CODE (insn) == CODE_LABEL)
3391: for (i = 0; i < n_spills; i++)
3392: {
3393: reg_reloaded_contents[i] = -1;
3394: reg_reloaded_insn[i] = 0;
3395: }
3396:
3397: /* Don't assume a reload reg is still good after a call insn
3398: if it is a call-used reg. */
3399: if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == CALL_INSN)
3400: for (i = 0; i < n_spills; i++)
3401: if (call_used_regs[spill_regs[i]])
3402: {
3403: reg_reloaded_contents[i] = -1;
3404: reg_reloaded_insn[i] = 0;
3405: }
3406:
3407: /* In case registers overlap, allow certain insns to invalidate
3408: particular hard registers. */
3409:
3410: #ifdef INSN_CLOBBERS_REGNO_P
3411: for (i = 0 ; i < n_spills ; i++)
3412: if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
3413: {
3414: reg_reloaded_contents[i] = -1;
3415: reg_reloaded_insn[i] = 0;
3416: }
3417: #endif
3418:
3419: insn = next;
3420:
3421: #ifdef USE_C_ALLOCA
3422: alloca (0);
3423: #endif
3424: }
3425: }
3426:
3427: /* Discard all record of any value reloaded from X,
3428: or reloaded in X from someplace else;
3429: unless X is an output reload reg of the current insn.
3430:
3431: X may be a hard reg (the reload reg)
3432: or it may be a pseudo reg that was reloaded from. */
3433:
3434: static void
3435: forget_old_reloads_1 (x)
3436: rtx x;
3437: {
3438: register int regno;
3439: int nr;
3440:
3441: if (GET_CODE (x) != REG)
3442: return;
3443:
3444: regno = REGNO (x);
3445:
3446: if (regno >= FIRST_PSEUDO_REGISTER)
3447: nr = 1;
3448: else
3449: {
3450: int i;
3451: nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3452: /* Storing into a spilled-reg invalidates its contents.
3453: This can happen if a block-local pseudo is allocated to that reg
3454: and it wasn't spilled because this block's total need is 0.
3455: Then some insn might have an optional reload and use this reg. */
3456: for (i = 0; i < nr; i++)
3457: if (spill_reg_order[regno + i] >= 0
3458: /* But don't do this if the reg actually serves as an output
3459: reload reg in the current instruction. */
3460: && (n_reloads == 0
3461: || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
3462: {
3463: reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
3464: reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
3465: }
3466: }
3467:
3468: /* Since value of X has changed,
3469: forget any value previously copied from it. */
3470:
3471: while (nr-- > 0)
3472: /* But don't forget a copy if this is the output reload
3473: that establishes the copy's validity. */
3474: if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3475: reg_last_reload_reg[regno + nr] = 0;
3476: }
3477:
3478: /* For each reload, the mode of the reload register. */
3479: static enum machine_mode reload_mode[MAX_RELOADS];
3480:
3481: /* For each reload, the largest number of registers it will require. */
3482: static int reload_nregs[MAX_RELOADS];
3483:
3484: /* Comparison function for qsort to decide which of two reloads
3485: should be handled first. *P1 and *P2 are the reload numbers. */
3486:
3487: static int
3488: reload_reg_class_lower (p1, p2)
3489: short *p1, *p2;
3490: {
3491: register int r1 = *p1, r2 = *p2;
3492: register int t;
3493:
3494: /* Consider required reloads before optional ones. */
3495: t = reload_optional[r1] - reload_optional[r2];
3496: if (t != 0)
3497: return t;
3498:
3499: /* Count all solitary classes before non-solitary ones. */
3500: t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
3501: - (reg_class_size[(int) reload_reg_class[r1]] == 1));
3502: if (t != 0)
3503: return t;
3504:
3505: /* Aside from solitaires, consider all multi-reg groups first. */
3506: t = reload_nregs[r2] - reload_nregs[r1];
3507: if (t != 0)
3508: return t;
3509:
3510: /* Consider reloads in order of increasing reg-class number. */
3511: t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
3512: if (t != 0)
3513: return t;
3514:
3515: /* If reloads are equally urgent, sort by reload number,
3516: so that the results of qsort leave nothing to chance. */
3517: return r1 - r2;
3518: }
3519:
3520: /* The following HARD_REG_SETs indicate when each hard register is
3521: used for a reload of various parts of the current insn. */
3522:
3523: /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3524: static HARD_REG_SET reload_reg_used;
3525: /* If reg is in use for a RELOAD_FOR_INPUT_RELOAD_ADDRESS reload. */
3526: static HARD_REG_SET reload_reg_used_in_input_addr;
3527: /* If reg is in use for a RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reload. */
3528: static HARD_REG_SET reload_reg_used_in_output_addr;
3529: /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
3530: static HARD_REG_SET reload_reg_used_in_op_addr;
3531: /* If reg is in use for a RELOAD_FOR_INPUT reload. */
3532: static HARD_REG_SET reload_reg_used_in_input;
3533: /* If reg is in use for a RELOAD_FOR_OUTPUT reload. */
3534: static HARD_REG_SET reload_reg_used_in_output;
3535:
3536: /* If reg is in use as a reload reg for any sort of reload. */
3537: static HARD_REG_SET reload_reg_used_at_all;
3538:
3539: /* Mark reg REGNO as in use for a reload of the sort spec'd by WHEN_NEEDED.
3540: MODE is used to indicate how many consecutive regs are actually used. */
3541:
3542: static void
3543: mark_reload_reg_in_use (regno, when_needed, mode)
3544: int regno;
3545: enum reload_when_needed when_needed;
3546: enum machine_mode mode;
3547: {
3548: int nregs = HARD_REGNO_NREGS (regno, mode);
3549: int i;
3550:
3551: for (i = regno; i < nregs + regno; i++)
3552: {
3553: switch (when_needed)
3554: {
3555: case RELOAD_OTHER:
3556: SET_HARD_REG_BIT (reload_reg_used, i);
3557: break;
3558:
3559: case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3560: SET_HARD_REG_BIT (reload_reg_used_in_input_addr, i);
3561: break;
3562:
3563: case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3564: SET_HARD_REG_BIT (reload_reg_used_in_output_addr, i);
3565: break;
3566:
3567: case RELOAD_FOR_OPERAND_ADDRESS:
3568: SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
3569: break;
3570:
3571: case RELOAD_FOR_INPUT:
3572: SET_HARD_REG_BIT (reload_reg_used_in_input, i);
3573: break;
3574:
3575: case RELOAD_FOR_OUTPUT:
3576: SET_HARD_REG_BIT (reload_reg_used_in_output, i);
3577: break;
3578: }
3579:
3580: SET_HARD_REG_BIT (reload_reg_used_at_all, i);
3581: }
3582: }
3583:
3584: /* 1 if reg REGNO is free as a reload reg for a reload of the sort
3585: specified by WHEN_NEEDED. */
3586:
3587: static int
3588: reload_reg_free_p (regno, when_needed)
3589: int regno;
3590: enum reload_when_needed when_needed;
3591: {
3592: /* In use for a RELOAD_OTHER means it's not available for anything. */
3593: if (TEST_HARD_REG_BIT (reload_reg_used, regno))
3594: return 0;
3595: switch (when_needed)
3596: {
3597: case RELOAD_OTHER:
3598: /* In use for anything means not available for a RELOAD_OTHER. */
3599: return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno);
3600:
3601: /* The other kinds of use can sometimes share a register. */
3602: case RELOAD_FOR_INPUT:
3603: return (! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno)
3604: && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3605: && ! TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno));
3606: case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3607: return (! TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno)
3608: && ! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno));
3609: case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3610: return (! TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno)
3611: && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3612: case RELOAD_FOR_OPERAND_ADDRESS:
3613: return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3614: && ! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno)
3615: && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3616: case RELOAD_FOR_OUTPUT:
3617: return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3618: && ! TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno)
3619: && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3620: }
3621: abort ();
3622: }
3623:
3624: /* Return 1 if the value in reload reg REGNO, as used by a reload
3625: needed for the part of the insn specified by WHEN_NEEDED,
3626: is not in use for a reload in any prior part of the insn.
3627:
3628: We can assume that the reload reg was already tested for availability
3629: at the time it is needed, and we should not check this again,
3630: in case the reg has already been marked in use. */
3631:
3632: static int
3633: reload_reg_free_before_p (regno, when_needed)
3634: int regno;
3635: enum reload_when_needed when_needed;
3636: {
3637: switch (when_needed)
3638: {
3639: case RELOAD_OTHER:
3640: /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
3641: its use starts from the beginning, so nothing can use it earlier. */
3642: return 1;
3643:
3644: /* If this use is for part of the insn,
3645: check the reg is not in use for any prior part. */
3646: case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3647: if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
3648: return 0;
3649: case RELOAD_FOR_OUTPUT:
3650: if (TEST_HARD_REG_BIT (reload_reg_used_in_input, regno))
3651: return 0;
3652: case RELOAD_FOR_OPERAND_ADDRESS:
3653: if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno))
3654: return 0;
3655: case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3656: case RELOAD_FOR_INPUT:
3657: return 1;
3658: }
3659: abort ();
3660: }
3661:
3662: /* Return 1 if the value in reload reg REGNO, as used by a reload
3663: needed for the part of the insn specified by WHEN_NEEDED,
3664: is still available in REGNO at the end of the insn.
3665:
3666: We can assume that the reload reg was already tested for availability
3667: at the time it is needed, and we should not check this again,
3668: in case the reg has already been marked in use. */
3669:
3670: static int
3671: reload_reg_reaches_end_p (regno, when_needed)
3672: int regno;
3673: enum reload_when_needed when_needed;
3674: {
3675: switch (when_needed)
3676: {
3677: case RELOAD_OTHER:
3678: /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
3679: its value must reach the end. */
3680: return 1;
3681:
3682: /* If this use is for part of the insn,
3683: its value reaches if no subsequent part uses the same register. */
3684: case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3685: case RELOAD_FOR_INPUT:
3686: if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3687: || TEST_HARD_REG_BIT (reload_reg_used_in_output, regno))
3688: return 0;
3689: case RELOAD_FOR_OPERAND_ADDRESS:
3690: if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno))
3691: return 0;
3692: case RELOAD_FOR_OUTPUT:
3693: case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3694: return 1;
3695: }
3696: abort ();
3697: }
3698:
3699: /* Vector of reload-numbers showing the order in which the reloads should
3700: be processed. */
3701: short reload_order[MAX_RELOADS];
3702:
3703: /* Indexed by reload number, 1 if incoming value
3704: inherited from previous insns. */
3705: char reload_inherited[MAX_RELOADS];
3706:
3707: /* For an inherited reload, this is the insn the reload was inherited from,
3708: if we know it. Otherwise, this is 0. */
3709: rtx reload_inheritance_insn[MAX_RELOADS];
3710:
3711: /* If non-zero, this is a place to get the value of the reload,
3712: rather than using reload_in. */
3713: rtx reload_override_in[MAX_RELOADS];
3714:
3715: /* For each reload, the index in spill_regs of the spill register used,
3716: or -1 if we did not need one of the spill registers for this reload. */
3717: int reload_spill_index[MAX_RELOADS];
3718:
3719: /* Index of last register assigned as a spill register. We allocate in
3720: a round-robin fashio. */
3721:
3722: static last_spill_reg = 0;
3723:
3724: /* Find a spill register to use as a reload register for reload R.
3725: LAST_RELOAD is non-zero if this is the last reload for the insn being
3726: processed.
3727:
3728: Set reload_reg_rtx[R] to the register allocated.
3729:
3730: If NOERROR is nonzero, we return 1 if successful,
3731: or 0 if we couldn't find a spill reg and we didn't change anything. */
3732:
3733: static int
3734: allocate_reload_reg (r, insn, last_reload, noerror)
3735: int r;
3736: rtx insn;
3737: int last_reload;
3738: int noerror;
3739: {
3740: int i;
3741: int pass;
3742: int count;
3743: rtx new;
3744: int regno;
3745:
3746: /* If we put this reload ahead, thinking it is a group,
3747: then insist on finding a group. Otherwise we can grab a
3748: reg that some other reload needs.
3749: (That can happen when we have a 68000 DATA_OR_FP_REG
3750: which is a group of data regs or one fp reg.)
3751: We need not be so restrictive if there are no more reloads
3752: for this insn.
3753:
3754: ??? Really it would be nicer to have smarter handling
3755: for that kind of reg class, where a problem like this is normal.
3756: Perhaps those classes should be avoided for reloading
3757: by use of more alternatives. */
3758:
3759: int force_group = reload_nregs[r] > 1 && ! last_reload;
3760:
3761: /* If we want a single register and haven't yet found one,
3762: take any reg in the right class and not in use.
3763: If we want a consecutive group, here is where we look for it.
3764:
3765: We use two passes so we can first look for reload regs to
3766: reuse, which are already in use for other reloads in this insn,
3767: and only then use additional registers.
3768: I think that maximizing reuse is needed to make sure we don't
3769: run out of reload regs. Suppose we have three reloads, and
3770: reloads A and B can share regs. These need two regs.
3771: Suppose A and B are given different regs.
3772: That leaves none for C. */
3773: for (pass = 0; pass < 2; pass++)
3774: {
3775: /* I is the index in spill_regs.
3776: We advance it round-robin between insns to use all spill regs
3777: equally, so that inherited reloads have a chance
3778: of leapfrogging each other. */
3779:
3780: for (count = 0, i = last_spill_reg; count < n_spills; count++)
3781: {
3782: int class = (int) reload_reg_class[r];
3783:
3784: i = (i + 1) % n_spills;
3785:
3786: if (reload_reg_free_p (spill_regs[i], reload_when_needed[r])
3787: && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
3788: && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
3789: /* Look first for regs to share, then for unshared. */
3790: && (pass || TEST_HARD_REG_BIT (reload_reg_used_at_all,
3791: spill_regs[i])))
3792: {
3793: int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
3794: /* Avoid the problem where spilling a GENERAL_OR_FP_REG
3795: (on 68000) got us two FP regs. If NR is 1,
3796: we would reject both of them. */
3797: if (force_group)
3798: nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
3799: /* If we need only one reg, we have already won. */
3800: if (nr == 1)
3801: {
3802: /* But reject a single reg if we demand a group. */
3803: if (force_group)
3804: continue;
3805: break;
3806: }
3807: /* Otherwise check that as many consecutive regs as we need
3808: are available here.
3809: Also, don't use for a group registers that are
3810: needed for nongroups. */
3811: if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
3812: while (nr > 1)
3813: {
3814: regno = spill_regs[i] + nr - 1;
3815: if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
3816: && spill_reg_order[regno] >= 0
3817: && reload_reg_free_p (regno, reload_when_needed[r])
3818: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
3819: regno)))
3820: break;
3821: nr--;
3822: }
3823: if (nr == 1)
3824: break;
3825: }
3826: }
3827:
3828: /* If we found something on pass 1, omit pass 2. */
3829: if (count < n_spills)
3830: break;
3831: }
3832:
3833: /* We should have found a spill register by now. */
3834: if (count == n_spills)
3835: {
3836: if (noerror)
3837: return 0;
3838: abort ();
3839: }
3840:
3841: last_spill_reg = i;
3842:
3843: /* Mark as in use for this insn the reload regs we use for this. */
3844: mark_reload_reg_in_use (spill_regs[i], reload_when_needed[r],
3845: reload_mode[r]);
3846:
3847: new = spill_reg_rtx[i];
3848:
3849: if (new == 0 || GET_MODE (new) != reload_mode[r])
3850: spill_reg_rtx[i] = new = gen_rtx (REG, reload_mode[r], spill_regs[i]);
3851:
3852: reload_reg_rtx[r] = new;
3853: reload_spill_index[r] = i;
3854: regno = true_regnum (new);
3855:
3856: /* Detect when the reload reg can't hold the reload mode.
3857: This used to be one `if', but Sequent compiler can't handle that. */
3858: if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
3859: {
3860: enum machine_mode test_mode = VOIDmode;
3861: if (reload_in[r])
3862: test_mode = GET_MODE (reload_in[r]);
3863: /* If reload_in[r] has VOIDmode, it means we will load it
3864: in whatever mode the reload reg has: to wit, reload_mode[r].
3865: We have already tested that for validity. */
3866: /* Aside from that, we need to test that the expressions
3867: to reload from or into have modes which are valid for this
3868: reload register. Otherwise the reload insns would be invalid. */
3869: if (! (reload_in[r] != 0 && test_mode != VOIDmode
3870: && ! HARD_REGNO_MODE_OK (regno, test_mode)))
3871: if (! (reload_out[r] != 0
3872: && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
3873: /* The reg is OK. */
3874: return 1;
3875: }
3876:
3877: /* The reg is not OK. */
3878: if (noerror)
3879: return 0;
3880:
3881: if (asm_noperands (PATTERN (insn)) < 0)
3882: /* It's the compiler's fault. */
3883: abort ();
3884:
3885: /* It's the user's fault; the operand's mode and constraint
3886: don't match. Disable this reload so we don't crash in final. */
3887: error_for_asm (insn,
3888: "`asm' operand constraint incompatible with operand size");
3889: reload_in[r] = 0;
3890: reload_out[r] = 0;
3891: reload_reg_rtx[r] = 0;
3892: reload_optional[r] = 1;
3893: reload_secondary_p[r] = 1;
3894:
3895: return 1;
3896: }
3897:
3898: /* Assign hard reg targets for the pseudo-registers we must reload
3899: into hard regs for this insn.
3900: Also output the instructions to copy them in and out of the hard regs.
3901:
3902: For machines with register classes, we are responsible for
3903: finding a reload reg in the proper class. */
3904:
3905: static void
3906: choose_reload_regs (insn, avoid_return_reg)
3907: rtx insn;
3908: /* This argument is currently ignored. */
3909: rtx avoid_return_reg;
3910: {
3911: register int i, j;
3912: int max_group_size = 1;
3913: enum reg_class group_class = NO_REGS;
3914: int inheritance;
3915:
3916: rtx save_reload_reg_rtx[MAX_RELOADS];
3917: char save_reload_inherited[MAX_RELOADS];
3918: rtx save_reload_inheritance_insn[MAX_RELOADS];
3919: rtx save_reload_override_in[MAX_RELOADS];
3920: int save_reload_spill_index[MAX_RELOADS];
3921: HARD_REG_SET save_reload_reg_used;
3922: HARD_REG_SET save_reload_reg_used_in_input_addr;
3923: HARD_REG_SET save_reload_reg_used_in_output_addr;
3924: HARD_REG_SET save_reload_reg_used_in_op_addr;
3925: HARD_REG_SET save_reload_reg_used_in_input;
3926: HARD_REG_SET save_reload_reg_used_in_output;
3927: HARD_REG_SET save_reload_reg_used_at_all;
3928:
3929: bzero (reload_inherited, MAX_RELOADS);
3930: bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
3931: bzero (reload_override_in, MAX_RELOADS * sizeof (rtx));
3932:
3933: CLEAR_HARD_REG_SET (reload_reg_used);
3934: CLEAR_HARD_REG_SET (reload_reg_used_at_all);
3935: CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr);
3936: CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr);
3937: CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
3938: CLEAR_HARD_REG_SET (reload_reg_used_in_output);
3939: CLEAR_HARD_REG_SET (reload_reg_used_in_input);
3940:
3941: /* Distinguish output-only and input-only reloads
3942: because they can overlap with other things. */
3943: for (j = 0; j < n_reloads; j++)
3944: if (reload_when_needed[j] == RELOAD_OTHER
3945: && ! reload_needed_for_multiple[j])
3946: {
3947: if (reload_in[j] == 0)
3948: {
3949: /* But earlyclobber operands must stay as RELOAD_OTHER. */
3950: for (i = 0; i < n_earlyclobbers; i++)
3951: if (rtx_equal_p (reload_out[j], reload_earlyclobbers[i]))
3952: break;
3953: if (i == n_earlyclobbers)
3954: reload_when_needed[j] = RELOAD_FOR_OUTPUT;
3955: }
3956: if (reload_out[j] == 0)
3957: reload_when_needed[j] = RELOAD_FOR_INPUT;
3958:
3959: if (reload_secondary_reload[j] >= 0
3960: && ! reload_needed_for_multiple[reload_secondary_reload[j]])
3961: reload_when_needed[reload_secondary_reload[j]]
3962: = reload_when_needed[j];
3963: }
3964:
3965: #ifdef SMALL_REGISTER_CLASSES
3966: /* Don't bother with avoiding the return reg
3967: if we have no mandatory reload that could use it. */
3968: if (avoid_return_reg)
3969: {
3970: int do_avoid = 0;
3971: int regno = REGNO (avoid_return_reg);
3972: int nregs
3973: = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
3974: int r;
3975:
3976: for (r = regno; r < regno + nregs; r++)
3977: if (spill_reg_order[r] >= 0)
3978: for (j = 0; j < n_reloads; j++)
3979: if (!reload_optional[j] && reload_reg_rtx[j] == 0
3980: && (reload_in[j] != 0 || reload_out[j] != 0
3981: || reload_secondary_p[j])
3982: &&
3983: TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
3984: do_avoid = 1;
3985: if (!do_avoid)
3986: avoid_return_reg = 0;
3987: }
3988: #endif /* SMALL_REGISTER_CLASSES */
3989:
3990: #if 0 /* Not needed, now that we can always retry without inheritance. */
3991: /* See if we have more mandatory reloads than spill regs.
3992: If so, then we cannot risk optimizations that could prevent
3993: reloads from sharing one spill register.
3994:
3995: Since we will try finding a better register than reload_reg_rtx
3996: unless it is equal to reload_in or reload_out, count such reloads. */
3997:
3998: {
3999: int tem = 0;
4000: #ifdef SMALL_REGISTER_CLASSES
4001: int tem = (avoid_return_reg != 0);
4002: #endif
4003: for (j = 0; j < n_reloads; j++)
4004: if (! reload_optional[j]
4005: && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
4006: && (reload_reg_rtx[j] == 0
4007: || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
4008: && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
4009: tem++;
4010: if (tem > n_spills)
4011: must_reuse = 1;
4012: }
4013: #endif
4014:
4015: #ifdef SMALL_REGISTER_CLASSES
4016: /* Don't use the subroutine call return reg for a reload
4017: if we are supposed to avoid it. */
4018: if (avoid_return_reg)
4019: {
4020: int regno = REGNO (avoid_return_reg);
4021: int nregs
4022: = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4023: int r;
4024:
4025: for (r = regno; r < regno + nregs; r++)
4026: if (spill_reg_order[r] >= 0)
4027: SET_HARD_REG_BIT (reload_reg_used, r);
4028: }
4029: #endif /* SMALL_REGISTER_CLASSES */
4030:
4031: /* In order to be certain of getting the registers we need,
4032: we must sort the reloads into order of increasing register class.
4033: Then our grabbing of reload registers will parallel the process
4034: that provided the reload registers.
4035:
4036: Also note whether any of the reloads wants a consecutive group of regs.
4037: If so, record the maximum size of the group desired and what
4038: register class contains all the groups needed by this insn. */
4039:
4040: for (j = 0; j < n_reloads; j++)
4041: {
4042: reload_order[j] = j;
4043: reload_spill_index[j] = -1;
4044:
4045: reload_mode[j]
4046: = (reload_strict_low[j] && reload_out[j]
4047: ? GET_MODE (SUBREG_REG (reload_out[j]))
4048: : (reload_inmode[j] == VOIDmode
4049: || (GET_MODE_SIZE (reload_outmode[j])
4050: > GET_MODE_SIZE (reload_inmode[j])))
4051: ? reload_outmode[j] : reload_inmode[j]);
4052:
4053: reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
4054:
4055: if (reload_nregs[j] > 1)
4056: {
4057: max_group_size = MAX (reload_nregs[j], max_group_size);
4058: group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
4059: }
4060:
4061: /* If we have already decided to use a certain register,
4062: don't use it in another way. */
4063: if (reload_reg_rtx[j])
4064: mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]),
4065: reload_when_needed[j], reload_mode[j]);
4066: }
4067:
4068: if (n_reloads > 1)
4069: qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
4070:
4071: bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx);
4072: bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
4073: bcopy (reload_inheritance_insn, save_reload_inheritance_insn,
4074: sizeof reload_inheritance_insn);
4075: bcopy (reload_override_in, save_reload_override_in,
4076: sizeof reload_override_in);
4077: bcopy (reload_spill_index, save_reload_spill_index,
4078: sizeof reload_spill_index);
4079: COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
4080: COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
4081: COPY_HARD_REG_SET (save_reload_reg_used_in_output,
4082: reload_reg_used_in_output);
4083: COPY_HARD_REG_SET (save_reload_reg_used_in_input,
4084: reload_reg_used_in_input);
4085: COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr,
4086: reload_reg_used_in_input_addr);
4087: COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr,
4088: reload_reg_used_in_output_addr);
4089: COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
4090: reload_reg_used_in_op_addr);
4091:
4092: /* Try first with inheritance, then turning it off. */
4093:
4094: for (inheritance = 1; inheritance >= 0; inheritance--)
4095: {
4096: /* Process the reloads in order of preference just found.
4097: Beyond this point, subregs can be found in reload_reg_rtx.
4098:
4099: This used to look for an existing reloaded home for all
4100: of the reloads, and only then perform any new reloads.
4101: But that could lose if the reloads were done out of reg-class order
4102: because a later reload with a looser constraint might have an old
4103: home in a register needed by an earlier reload with a tighter constraint.
4104:
4105: To solve this, we make two passes over the reloads, in the order
4106: described above. In the first pass we try to inherit a reload
4107: from a previous insn. If there is a later reload that needs a
4108: class that is a proper subset of the class being processed, we must
4109: also allocate a spill register during the first pass.
4110:
4111: Then make a second pass over the reloads to allocate any reloads
4112: that haven't been given registers yet. */
4113:
4114: for (j = 0; j < n_reloads; j++)
4115: {
4116: register int r = reload_order[j];
4117:
4118: /* Ignore reloads that got marked inoperative. */
4119: if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4120: continue;
4121:
4122: /* If find_reloads chose a to use reload_in or reload_out as a reload
4123: register, we don't need to chose one. Otherwise, try even if it found
4124: one since we might save an insn if we find the value lying around. */
4125: if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
4126: && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
4127: || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
4128: continue;
4129:
4130: #if 0 /* No longer needed for correct operation.
4131: It might give better code, or might not; worth an experiment? */
4132: /* If this is an optional reload, we can't inherit from earlier insns
4133: until we are sure that any non-optional reloads have been allocated.
4134: The following code takes advantage of the fact that optional reloads
4135: are at the end of reload_order. */
4136: if (reload_optional[r] != 0)
4137: for (i = 0; i < j; i++)
4138: if ((reload_out[reload_order[i]] != 0
4139: || reload_in[reload_order[i]] != 0
4140: || reload_secondary_p[reload_order[i]])
4141: && ! reload_optional[reload_order[i]]
4142: && reload_reg_rtx[reload_order[i]] == 0)
4143: allocate_reload_reg (reload_order[i], insn, 0, inheritance);
4144: #endif
4145:
4146: /* First see if this pseudo is already available as reloaded
4147: for a previous insn. We cannot try to inherit for reloads
4148: that are smaller than the maximum number of registers needed
4149: for groups unless the register we would allocate cannot be used
4150: for the groups.
4151:
4152: We could check here to see if this is a secondary reload for
4153: an object that is already in a register of the desired class.
4154: This would avoid the need for the secondary reload register.
4155: But this is complex because we can't easily determine what
4156: objects might want to be loaded via this reload. So let a register
4157: be allocated here. In `emit_reload_insns' we suppress one of the
4158: loads in the case described above. */
4159:
4160: if (inheritance)
4161: {
4162: register int regno = -1;
4163:
4164: if (reload_in[r] == 0)
4165: ;
4166: else if (GET_CODE (reload_in[r]) == REG)
4167: regno = REGNO (reload_in[r]);
4168: else if (GET_CODE (reload_in_reg[r]) == REG)
4169: regno = REGNO (reload_in_reg[r]);
4170: #if 0
4171: /* This won't work, since REGNO can be a pseudo reg number.
4172: Also, it takes much more hair to keep track of all the things
4173: that can invalidate an inherited reload of part of a pseudoreg. */
4174: else if (GET_CODE (reload_in[r]) == SUBREG
4175: && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
4176: regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
4177: #endif
4178:
4179: if (regno >= 0 && reg_last_reload_reg[regno] != 0)
4180: {
4181: i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
4182:
4183: if (reg_reloaded_contents[i] == regno
4184: && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4185: && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4186: spill_regs[i])
4187: && (reload_nregs[r] == max_group_size
4188: || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
4189: spill_regs[i]))
4190: && reload_reg_free_p (spill_regs[i], reload_when_needed[r])
4191: && reload_reg_free_before_p (spill_regs[i],
4192: reload_when_needed[r]))
4193: {
4194: /* If a group is needed, verify that all the subsequent
4195: registers still have their values intact. */
4196: int nr
4197: = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4198: int k;
4199:
4200: for (k = 1; k < nr; k++)
4201: if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
4202: != regno)
4203: break;
4204:
4205: if (k == nr)
4206: {
4207: /* Mark the register as in use for this part of
4208: the insn. */
4209: mark_reload_reg_in_use (spill_regs[i],
4210: reload_when_needed[r],
4211: reload_mode[r]);
4212: reload_reg_rtx[r] = reg_last_reload_reg[regno];
4213: reload_inherited[r] = 1;
4214: reload_inheritance_insn[r] = reg_reloaded_insn[i];
4215: reload_spill_index[r] = i;
4216: }
4217: }
4218: }
4219: }
4220:
4221: /* Here's another way to see if the value is already lying around. */
4222: if (inheritance
4223: && reload_in[r] != 0
4224: && ! reload_inherited[r]
4225: && reload_out[r] == 0
4226: && (CONSTANT_P (reload_in[r])
4227: || GET_CODE (reload_in[r]) == PLUS
4228: || GET_CODE (reload_in[r]) == REG
4229: || GET_CODE (reload_in[r]) == MEM)
4230: && (reload_nregs[r] == max_group_size
4231: || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
4232: {
4233: register rtx equiv
4234: = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
4235: -1, 0, 0, reload_mode[r]);
4236: int regno;
4237:
4238: if (equiv != 0)
4239: {
4240: if (GET_CODE (equiv) == REG)
4241: regno = REGNO (equiv);
4242: else if (GET_CODE (equiv) == SUBREG)
4243: {
4244: regno = REGNO (SUBREG_REG (equiv));
4245: if (regno < FIRST_PSEUDO_REGISTER)
4246: regno += SUBREG_WORD (equiv);
4247: }
4248: else
4249: abort ();
4250: }
4251:
4252: /* If we found a spill reg, reject it unless it is free
4253: and of the desired class. */
4254: if (equiv != 0
4255: && ((spill_reg_order[regno] >= 0
4256: && ! reload_reg_free_before_p (regno,
4257: reload_when_needed[r]))
4258: || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4259: regno)))
4260: equiv = 0;
4261:
4262: if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
4263: equiv = 0;
4264:
4265: if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4266: equiv = 0;
4267:
4268: /* We found a register that contains the value we need.
4269: If this register is the same as an `earlyclobber' operand
4270: of the current insn, just mark it as a place to reload from
4271: since we can't use it as the reload register itself. */
4272:
4273: if (equiv != 0)
4274: for (i = 0; i < n_earlyclobbers; i++)
4275: if (reg_overlap_mentioned_p (equiv, reload_earlyclobbers[i]))
4276: {
4277: reload_override_in[r] = equiv;
4278: equiv = 0;
4279: break;
4280: }
4281:
4282: /* JRV: If the equiv register we have found is explicitly
4283: clobbered in the current insn, mark but don't use, as above. */
4284:
4285: if (equiv != 0 && regno_clobbered_p (regno, insn))
4286: {
4287: reload_override_in[r] = equiv;
4288: equiv = 0;
4289: }
4290:
4291: /* If we found an equivalent reg, say no code need be generated
4292: to load it, and use it as our reload reg. */
4293: if (equiv != 0 && regno != FRAME_POINTER_REGNUM)
4294: {
4295: reload_reg_rtx[r] = equiv;
4296: reload_inherited[r] = 1;
4297: /* If it is a spill reg,
4298: mark the spill reg as in use for this insn. */
4299: i = spill_reg_order[regno];
4300: if (i >= 0)
4301: mark_reload_reg_in_use (regno, reload_when_needed[r],
4302: reload_mode[r]);
4303: }
4304: }
4305:
4306: /* If we found a register to use already, or if this is an optional
4307: reload, we are done. */
4308: if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
4309: continue;
4310:
4311: #if 0 /* No longer needed for correct operation. Might or might not
4312: give better code on the average. Want to experiment? */
4313:
4314: /* See if there is a later reload that has a class different from our
4315: class that intersects our class or that requires less register
4316: than our reload. If so, we must allocate a register to this
4317: reload now, since that reload might inherit a previous reload
4318: and take the only available register in our class. Don't do this
4319: for optional reloads since they will force all previous reloads
4320: to be allocated. Also don't do this for reloads that have been
4321: turned off. */
4322:
4323: for (i = j + 1; i < n_reloads; i++)
4324: {
4325: int s = reload_order[i];
4326:
1.1.1.2 ! root 4327: if ((reload_in[s] == 0 && reload_out[s] == 0
! 4328: && ! reload_secondary_p[s])
1.1 root 4329: || reload_optional[s])
4330: continue;
4331:
4332: if ((reload_reg_class[s] != reload_reg_class[r]
4333: && reg_classes_intersect_p (reload_reg_class[r],
4334: reload_reg_class[s]))
4335: || reload_nregs[s] < reload_nregs[r])
4336: break;
4337: }
4338:
4339: if (i == n_reloads)
4340: continue;
4341:
4342: allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
4343: #endif
4344: }
4345:
4346: /* Now allocate reload registers for anything non-optional that
4347: didn't get one yet. */
4348: for (j = 0; j < n_reloads; j++)
4349: {
4350: register int r = reload_order[j];
4351:
4352: /* Ignore reloads that got marked inoperative. */
4353: if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4354: continue;
4355:
4356: /* Skip reloads that already have a register allocated or are
4357: optional. */
4358: if (reload_reg_rtx[r] != 0 || reload_optional[r])
4359: continue;
4360:
4361: if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
4362: break;
4363: }
4364:
4365: /* If that loop got all the way, we have won. */
4366: if (j == n_reloads)
4367: break;
4368:
4369: fail:
4370: /* Loop around and try without any inheritance. */
4371: /* First undo everything done by the failed attempt
4372: to allocate with inheritance. */
4373: bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx);
4374: bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited);
4375: bcopy (save_reload_inheritance_insn, reload_inheritance_insn,
4376: sizeof reload_inheritance_insn);
4377: bcopy (save_reload_override_in, reload_override_in,
4378: sizeof reload_override_in);
4379: bcopy (save_reload_spill_index, reload_spill_index,
4380: sizeof reload_spill_index);
4381: COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
4382: COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
4383: COPY_HARD_REG_SET (reload_reg_used_in_input,
4384: save_reload_reg_used_in_input);
4385: COPY_HARD_REG_SET (reload_reg_used_in_output,
4386: save_reload_reg_used_in_output);
4387: COPY_HARD_REG_SET (reload_reg_used_in_input_addr,
4388: save_reload_reg_used_in_input_addr);
4389: COPY_HARD_REG_SET (reload_reg_used_in_output_addr,
4390: save_reload_reg_used_in_output_addr);
4391: COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
4392: save_reload_reg_used_in_op_addr);
4393: }
4394:
4395: /* If we thought we could inherit a reload, because it seemed that
4396: nothing else wanted the same reload register earlier in the insn,
4397: verify that assumption, now that all reloads have been assigned. */
4398:
4399: for (j = 0; j < n_reloads; j++)
4400: {
4401: register int r = reload_order[j];
4402:
4403: if (reload_inherited[r] && reload_reg_rtx[r] != 0
4404: && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
4405: reload_when_needed[r]))
4406: reload_inherited[r] = 0;
4407:
4408: /* If we found a better place to reload from,
4409: validate it in the same fashion, if it is a reload reg. */
4410: if (reload_override_in[r]
4411: && (GET_CODE (reload_override_in[r]) == REG
4412: || GET_CODE (reload_override_in[r]) == SUBREG))
4413: {
4414: int regno = true_regnum (reload_override_in[r]);
4415: if (spill_reg_order[regno] >= 0
4416: && ! reload_reg_free_before_p (regno, reload_when_needed[r]))
4417: reload_override_in[r] = 0;
4418: }
4419: }
4420:
4421: /* Now that reload_override_in is known valid,
4422: actually override reload_in. */
4423: for (j = 0; j < n_reloads; j++)
4424: if (reload_override_in[j])
4425: reload_in[j] = reload_override_in[j];
4426:
4427: /* If this reload won't be done because it has been cancelled or is
4428: optional and not inherited, clear reload_reg_rtx so other
4429: routines (such as subst_reloads) don't get confused. */
4430: for (j = 0; j < n_reloads; j++)
4431: if ((reload_optional[j] && ! reload_inherited[j])
4432: || (reload_in[j] == 0 && reload_out[j] == 0
4433: && ! reload_secondary_p[j]))
4434: reload_reg_rtx[j] = 0;
4435:
4436: /* Record which pseudos and which spill regs have output reloads. */
4437: for (j = 0; j < n_reloads; j++)
4438: {
4439: register int r = reload_order[j];
4440:
4441: i = reload_spill_index[r];
4442:
4443: /* I is nonneg if this reload used one of the spill regs.
4444: If reload_reg_rtx[r] is 0, this is an optional reload
4445: that we opted to ignore. */
4446: if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
4447: && reload_reg_rtx[r] != 0)
4448: {
4449: register int nregno = REGNO (reload_out[r]);
4450: int nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
4451:
4452: while (--nr >= 0)
4453: {
4454: reg_has_output_reload[nregno + nr] = 1;
4455: if (i >= 0)
4456: SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
4457: }
4458:
4459: if (reload_when_needed[r] != RELOAD_OTHER
4460: && reload_when_needed[r] != RELOAD_FOR_OUTPUT)
4461: abort ();
4462: }
4463: }
4464: }
4465:
4466: /* Output insns to reload values in and out of the chosen reload regs. */
4467:
4468: static void
4469: emit_reload_insns (insn)
4470: rtx insn;
4471: {
4472: register int j;
4473: rtx following_insn = NEXT_INSN (insn);
4474: rtx before_insn = insn;
4475: rtx first_output_reload_insn = NEXT_INSN (insn);
4476: rtx first_other_reload_insn = insn;
4477: rtx first_operand_address_reload_insn = insn;
4478: int special;
4479: /* Values to be put in spill_reg_store are put here first. */
4480: rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
4481:
1.1.1.2 ! root 4482: /* If this is a CALL_INSN preceded by USE insns, any reload insns
1.1 root 4483: must go in front of the first USE insn, not in front of INSN. */
4484:
4485: if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN
4486: && GET_CODE (PATTERN (PREV_INSN (insn))) == USE)
4487: while (GET_CODE (PREV_INSN (before_insn)) == INSN
4488: && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE)
4489: first_other_reload_insn = first_operand_address_reload_insn
4490: = before_insn = PREV_INSN (before_insn);
4491:
4492: /* Now output the instructions to copy the data into and out of the
4493: reload registers. Do these in the order that the reloads were reported,
4494: since reloads of base and index registers precede reloads of operands
4495: and the operands may need the base and index registers reloaded. */
4496:
4497: for (j = 0; j < n_reloads; j++)
4498: {
4499: register rtx old;
4500: rtx oldequiv_reg = 0;
4501: rtx this_reload_insn = 0;
4502: rtx store_insn = 0;
4503:
4504: old = reload_in[j];
4505: if (old != 0 && ! reload_inherited[j]
4506: && ! rtx_equal_p (reload_reg_rtx[j], old)
4507: && reload_reg_rtx[j] != 0)
4508: {
4509: register rtx reloadreg = reload_reg_rtx[j];
4510: rtx oldequiv = 0;
4511: enum machine_mode mode;
4512: rtx where;
4513: rtx reload_insn;
4514:
4515: /* Determine the mode to reload in.
4516: This is very tricky because we have three to choose from.
4517: There is the mode the insn operand wants (reload_inmode[J]).
4518: There is the mode of the reload register RELOADREG.
4519: There is the intrinsic mode of the operand, which we could find
4520: by stripping some SUBREGs.
4521: It turns out that RELOADREG's mode is irrelevant:
4522: we can change that arbitrarily.
4523:
4524: Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
4525: then the reload reg may not support QImode moves, so use SImode.
4526: If foo is in memory due to spilling a pseudo reg, this is safe,
4527: because the QImode value is in the least significant part of a
4528: slot big enough for a SImode. If foo is some other sort of
4529: memory reference, then it is impossible to reload this case,
4530: so previous passes had better make sure this never happens.
4531:
4532: Then consider a one-word union which has SImode and one of its
4533: members is a float, being fetched as (SUBREG:SF union:SI).
4534: We must fetch that as SFmode because we could be loading into
4535: a float-only register. In this case OLD's mode is correct.
4536:
4537: Consider an immediate integer: it has VOIDmode. Here we need
4538: to get a mode from something else.
4539:
4540: In some cases, there is a fourth mode, the operand's
4541: containing mode. If the insn specifies a containing mode for
4542: this operand, it overrides all others.
4543:
4544: I am not sure whether the algorithm here is always right,
4545: but it does the right things in those cases. */
4546:
4547: mode = GET_MODE (old);
4548: if (mode == VOIDmode)
4549: mode = reload_inmode[j];
4550: if (reload_strict_low[j])
4551: mode = GET_MODE (SUBREG_REG (reload_in[j]));
4552:
4553: #ifdef SECONDARY_INPUT_RELOAD_CLASS
4554: /* If we need a secondary register for this operation, see if
4555: the value is already in a register in that class. Don't
4556: do this if the secondary register will be used as a scratch
4557: register. */
4558:
4559: if (reload_secondary_reload[j] >= 0
4560: && reload_secondary_icode[j] == CODE_FOR_nothing)
4561: oldequiv
4562: = find_equiv_reg (old, insn,
4563: reload_reg_class[reload_secondary_reload[j]],
4564: -1, 0, 0, mode);
4565: #endif
4566:
4567: /* If reloading from memory, see if there is a register
4568: that already holds the same value. If so, reload from there.
4569: We can pass 0 as the reload_reg_p argument because
4570: any other reload has either already been emitted,
4571: in which case find_equiv_reg will see the reload-insn,
4572: or has yet to be emitted, in which case it doesn't matter
4573: because we will use this equiv reg right away. */
4574:
4575: if (oldequiv == 0
4576: && (GET_CODE (old) == MEM
4577: || (GET_CODE (old) == REG
4578: && REGNO (old) >= FIRST_PSEUDO_REGISTER
4579: && reg_renumber[REGNO (old)] < 0)))
4580: oldequiv = find_equiv_reg (old, insn, GENERAL_REGS,
4581: -1, 0, 0, mode);
4582:
4583: if (oldequiv)
4584: {
4585: int regno = true_regnum (oldequiv);
4586:
4587: /* If OLDEQUIV is a spill register, don't use it for this
4588: if any other reload needs it at an earlier stage of this insn
4589: or at this stage. */
4590: if (spill_reg_order[regno] >= 0
4591: && (! reload_reg_free_p (regno, reload_when_needed[j])
4592: || ! reload_reg_free_before_p (regno,
4593: reload_when_needed[j])))
4594: oldequiv = 0;
4595:
4596: /* If OLDEQUIV is not a spill register,
4597: don't use it if any other reload wants it. */
4598: if (spill_reg_order[regno] < 0)
4599: {
4600: int k;
4601: for (k = 0; k < n_reloads; k++)
4602: if (reload_reg_rtx[k] != 0 && k != j
4603: && reg_overlap_mentioned_p (reload_reg_rtx[k], oldequiv))
4604: {
4605: oldequiv = 0;
4606: break;
4607: }
4608: }
4609: }
4610:
4611: if (oldequiv == 0)
4612: oldequiv = old;
4613: else if (GET_CODE (oldequiv) == REG)
4614: oldequiv_reg = oldequiv;
4615: else if (GET_CODE (oldequiv) == SUBREG)
4616: oldequiv_reg = SUBREG_REG (oldequiv);
4617:
4618: /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
4619: then load RELOADREG from OLDEQUIV. */
4620:
4621: if (GET_MODE (reloadreg) != mode)
4622: reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
4623: while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
4624: oldequiv = SUBREG_REG (oldequiv);
4625: if (GET_MODE (oldequiv) != VOIDmode
4626: && mode != GET_MODE (oldequiv))
4627: oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
4628:
4629: /* Decide where to put reload insn for this reload. */
4630: switch (reload_when_needed[j])
4631: {
4632: case RELOAD_FOR_INPUT:
4633: case RELOAD_OTHER:
4634: where = first_operand_address_reload_insn;
4635: break;
4636: case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
4637: where = first_other_reload_insn;
4638: break;
4639: case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
4640: where = first_output_reload_insn;
4641: break;
4642: case RELOAD_FOR_OPERAND_ADDRESS:
4643: where = before_insn;
4644: }
4645:
4646: special = 0;
4647:
4648: /* Auto-increment addresses must be reloaded in a special way. */
4649: if (GET_CODE (oldequiv) == POST_INC
4650: || GET_CODE (oldequiv) == POST_DEC
4651: || GET_CODE (oldequiv) == PRE_INC
4652: || GET_CODE (oldequiv) == PRE_DEC)
4653: {
4654: /* We are not going to bother supporting the case where a
4655: incremented register can't be copied directly from
4656: OLDEQUIV since this seems highly unlikely. */
4657: if (reload_secondary_reload[j] >= 0)
4658: abort ();
4659: /* Prevent normal processing of this reload. */
4660: special = 1;
4661: /* Output a special code sequence for this case. */
4662: this_reload_insn
4663: = inc_for_reload (reloadreg, oldequiv, reload_inc[j], where);
4664: }
4665:
4666: /* If we are reloading a pseudo-register that was set by the previous
4667: insn, see if we can get rid of that pseudo-register entirely
4668: by redirecting the previous insn into our reload register. */
4669:
4670: else if (optimize && GET_CODE (old) == REG
4671: && REGNO (old) >= FIRST_PSEUDO_REGISTER
4672: && dead_or_set_p (insn, old)
4673: /* This is unsafe if some other reload
4674: uses the same reg first. */
4675: && (reload_when_needed[j] == RELOAD_OTHER
4676: || reload_when_needed[j] == RELOAD_FOR_INPUT
4677: || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS))
4678: {
4679: rtx temp = PREV_INSN (insn);
4680: while (temp && GET_CODE (temp) == NOTE)
4681: temp = PREV_INSN (temp);
4682: if (temp
4683: && GET_CODE (temp) == INSN
4684: && GET_CODE (PATTERN (temp)) == SET
4685: && SET_DEST (PATTERN (temp)) == old
4686: /* Make sure we can access insn_operand_constraint. */
4687: && asm_noperands (PATTERN (temp)) < 0
4688: /* This is unsafe if prev insn rejects our reload reg. */
4689: && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
4690: reloadreg)
4691: /* This is unsafe if operand occurs more than once in current
4692: insn. Perhaps some occurrences aren't reloaded. */
4693: && count_occurrences (PATTERN (insn), old) == 1
4694: /* Don't risk splitting a matching pair of operands. */
4695: && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
4696: {
4697: /* Store into the reload register instead of the pseudo. */
4698: SET_DEST (PATTERN (temp)) = reloadreg;
4699: /* If these are the only uses of the pseudo reg,
4700: pretend for GDB it lives in the reload reg we used. */
4701: if (reg_n_deaths[REGNO (old)] == 1
4702: && reg_n_sets[REGNO (old)] == 1)
4703: {
4704: reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
4705: alter_reg (REGNO (old), -1);
4706: }
4707: special = 1;
4708: }
4709: }
4710:
4711: /* We can't do that, so output an insn to load RELOADREG.
4712: Keep them in the following order:
4713: all reloads for input reload addresses,
4714: all reloads for ordinary input operands,
4715: all reloads for addresses of non-reloaded operands,
4716: the insn being reloaded,
4717: all reloads for addresses of output reloads,
4718: the output reloads. */
4719: if (! special)
4720: {
4721: #ifdef SECONDARY_INPUT_RELOAD_CLASS
4722: rtx second_reload_reg = 0;
4723: enum insn_code icode;
4724:
4725: /* If we have a secondary reload, pick up the secondary register
4726: and icode, if any. If OLDEQUIV and OLD are different or
4727: if this is an in-out reload, recompute whether or not we
4728: still need a secondary register and what the icode should
4729: be. If we still need a secondary register and the class or
4730: icode is different, go back to reloading from OLD if using
4731: OLDEQUIV means that we got the wrong type of register. We
4732: cannot have different class or icode due to an in-out reload
4733: because we don't make such reloads when both the input and
4734: output need secondary reload registers. */
4735:
4736: if (reload_secondary_reload[j] >= 0)
4737: {
4738: int secondary_reload = reload_secondary_reload[j];
1.1.1.2 ! root 4739: rtx real_oldequiv = oldequiv;
! 4740: rtx real_old = old;
! 4741:
! 4742: /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
! 4743: and similarly for OLD.
! 4744: See comments in find_secondary_reload in reload.c. */
! 4745: if (GET_CODE (oldequiv) == REG
! 4746: && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
! 4747: && reg_equiv_mem[REGNO (oldequiv)] != 0)
! 4748: real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
! 4749:
! 4750: if (GET_CODE (old) == REG
! 4751: && REGNO (old) >= FIRST_PSEUDO_REGISTER
! 4752: && reg_equiv_mem[REGNO (old)] != 0)
! 4753: real_old = reg_equiv_mem[REGNO (old)];
! 4754:
1.1 root 4755: second_reload_reg = reload_reg_rtx[secondary_reload];
4756: icode = reload_secondary_icode[j];
4757:
4758: if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
4759: || (reload_in[j] != 0 && reload_out[j] != 0))
4760: {
4761: enum reg_class new_class
4762: = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
1.1.1.2 ! root 4763: mode, real_oldequiv);
1.1 root 4764:
4765: if (new_class == NO_REGS)
4766: second_reload_reg = 0;
4767: else
4768: {
4769: enum insn_code new_icode;
4770: enum machine_mode new_mode;
4771:
4772: if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
4773: REGNO (second_reload_reg)))
1.1.1.2 ! root 4774: oldequiv = old, real_oldequiv = real_old;
1.1 root 4775: else
4776: {
4777: new_icode = reload_in_optab[(int) mode];
4778: if (new_icode != CODE_FOR_nothing
4779: && ((insn_operand_predicate[(int) new_icode][0]
4780: && ! ((*insn_operand_predicate[(int) new_icode][0])
4781: (reloadreg, mode)))
4782: || (insn_operand_predicate[(int) new_icode][1]
4783: && ! ((*insn_operand_predicate[(int) new_icode][1])
1.1.1.2 ! root 4784: (real_oldequiv, mode)))))
1.1 root 4785: new_icode = CODE_FOR_nothing;
4786:
4787: if (new_icode == CODE_FOR_nothing)
4788: new_mode = mode;
4789: else
4790: new_mode = insn_operand_mode[new_icode][2];
4791:
4792: if (GET_MODE (second_reload_reg) != new_mode)
4793: {
4794: if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
4795: new_mode))
1.1.1.2 ! root 4796: oldequiv = old, real_oldequiv = real_old;
1.1 root 4797: else
4798: second_reload_reg
4799: = gen_reg_rtx (REG, new_mode,
4800: REGNO (second_reload_reg));
4801: }
4802: }
4803: }
4804: }
4805:
4806: /* If we still need a secondary reload register, check
4807: to see if it is being used as a scratch or intermediate
1.1.1.2 ! root 4808: register and generate code appropriately. If we need
! 4809: a scratch register, use REAL_OLDEQUIV since the form of
! 4810: the insn may depend on the actual address if it is
! 4811: a MEM. */
1.1 root 4812:
4813: if (second_reload_reg)
4814: {
4815: if (icode != CODE_FOR_nothing)
4816: {
4817: reload_insn = emit_insn_before (GEN_FCN (icode)
1.1.1.2 ! root 4818: (reloadreg,
! 4819: real_oldequiv,
1.1 root 4820: second_reload_reg),
4821: where);
4822: if (this_reload_insn == 0)
4823: this_reload_insn = reload_insn;
4824: special = 1;
4825: }
4826: else
4827: {
4828: /* See if we need a scratch register to load the
4829: intermediate register (a tertiary reload). */
4830: enum insn_code tertiary_icode
4831: = reload_secondary_icode[secondary_reload];
4832:
4833: if (tertiary_icode != CODE_FOR_nothing)
4834: {
4835: rtx third_reload_reg
4836: = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
4837:
4838: reload_insn
4839: = emit_insn_before ((GEN_FCN (tertiary_icode)
4840: (second_reload_reg,
1.1.1.2 ! root 4841: real_oldequiv,
1.1 root 4842: third_reload_reg)),
4843: where);
4844: if (this_reload_insn == 0)
4845: this_reload_insn = reload_insn;
4846: }
4847: else
4848: {
4849: reload_insn
4850: = gen_input_reload (second_reload_reg,
4851: oldequiv, where);
4852: if (this_reload_insn == 0)
4853: this_reload_insn = reload_insn;
4854: oldequiv = second_reload_reg;
4855: }
4856: }
4857: }
4858: }
4859: #endif
4860:
4861: if (! special)
4862: {
4863: reload_insn = gen_input_reload (reloadreg,
4864: oldequiv, where);
4865: if (this_reload_insn == 0)
4866: this_reload_insn = reload_insn;
4867: }
4868:
4869: #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
4870: /* We may have to make a REG_DEAD note for the secondary reload
4871: register in the insns we just made. Find the last insn that
4872: mentioned the register. */
4873: if (! special && second_reload_reg
4874: && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
4875: {
4876: rtx prev;
4877:
4878: for (prev = where;
4879: prev != PREV_INSN (this_reload_insn);
4880: prev = PREV_INSN (prev))
4881: if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
4882: && reg_overlap_mentioned_p (second_reload_reg,
4883: PATTERN (prev)))
4884: {
4885: REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
4886: second_reload_reg,
4887: REG_NOTES (prev));
4888: break;
4889: }
4890: }
4891: #endif
4892: }
4893:
4894: /* Update where to put other reload insns. */
4895: if (this_reload_insn)
4896: switch (reload_when_needed[j])
4897: {
4898: case RELOAD_FOR_INPUT:
4899: case RELOAD_OTHER:
4900: if (first_other_reload_insn == first_operand_address_reload_insn)
4901: first_other_reload_insn = this_reload_insn;
4902: break;
4903: case RELOAD_FOR_OPERAND_ADDRESS:
4904: if (first_operand_address_reload_insn == before_insn)
4905: first_operand_address_reload_insn = this_reload_insn;
4906: if (first_other_reload_insn == before_insn)
4907: first_other_reload_insn = this_reload_insn;
4908: }
4909:
4910: /* reload_inc[j] was formerly processed here. */
4911: }
4912:
4913: /* Add a note saying the input reload reg
4914: dies in this insn, if anyone cares. */
4915: #ifdef PRESERVE_DEATH_INFO_REGNO_P
4916: if (old != 0
4917: && reload_reg_rtx[j] != old
4918: && reload_reg_rtx[j] != 0
4919: && reload_out[j] == 0
4920: && ! reload_inherited[j]
4921: && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
4922: {
4923: register rtx reloadreg = reload_reg_rtx[j];
4924:
4925: #if 0
4926: /* We can't abort here because we need to support this for sched.c.
4927: It's not terrible to miss a REG_DEAD note, but we should try
4928: to figure out how to do this correctly. */
4929: /* The code below is incorrect for address-only reloads. */
4930: if (reload_when_needed[j] != RELOAD_OTHER
4931: && reload_when_needed[j] != RELOAD_FOR_INPUT)
4932: abort ();
4933: #endif
4934:
4935: /* Add a death note to this insn, for an input reload. */
4936:
4937: if ((reload_when_needed[j] == RELOAD_OTHER
4938: || reload_when_needed[j] == RELOAD_FOR_INPUT)
4939: && ! dead_or_set_p (insn, reloadreg))
4940: REG_NOTES (insn)
4941: = gen_rtx (EXPR_LIST, REG_DEAD,
4942: reloadreg, REG_NOTES (insn));
4943: }
4944:
4945: /* When we inherit a reload, the last marked death of the reload reg
4946: may no longer really be a death. */
4947: if (reload_reg_rtx[j] != 0
4948: && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
4949: && reload_inherited[j])
4950: {
4951: /* Handle inheriting an output reload.
4952: Remove the death note from the output reload insn. */
4953: if (reload_spill_index[j] >= 0
4954: && GET_CODE (reload_in[j]) == REG
4955: && spill_reg_store[reload_spill_index[j]] != 0
4956: && find_regno_note (spill_reg_store[reload_spill_index[j]],
4957: REG_DEAD, REGNO (reload_reg_rtx[j])))
4958: remove_death (REGNO (reload_reg_rtx[j]),
4959: spill_reg_store[reload_spill_index[j]]);
4960: /* Likewise for input reloads that were inherited. */
4961: else if (reload_spill_index[j] >= 0
4962: && GET_CODE (reload_in[j]) == REG
4963: && spill_reg_store[reload_spill_index[j]] == 0
4964: && reload_inheritance_insn[j] != 0
4965: && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
4966: REGNO (reload_reg_rtx[j])))
4967: remove_death (REGNO (reload_reg_rtx[j]),
4968: reload_inheritance_insn[j]);
4969: else
4970: {
4971: rtx prev;
4972:
4973: /* We got this register from find_equiv_reg.
4974: Search back for its last death note and get rid of it.
4975: But don't search back too far.
4976: Don't go past a place where this reg is set,
4977: since a death note before that remains valid. */
4978: for (prev = PREV_INSN (insn);
4979: prev && GET_CODE (prev) != CODE_LABEL;
4980: prev = PREV_INSN (prev))
4981: if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
4982: && dead_or_set_p (prev, reload_reg_rtx[j]))
4983: {
4984: if (find_regno_note (prev, REG_DEAD,
4985: REGNO (reload_reg_rtx[j])))
4986: remove_death (REGNO (reload_reg_rtx[j]), prev);
4987: break;
4988: }
4989: }
4990: }
4991:
4992: /* We might have used find_equiv_reg above to choose an alternate
4993: place from which to reload. If so, and it died, we need to remove
4994: that death and move it to one of the insns we just made. */
4995:
4996: if (oldequiv_reg != 0
4997: && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
4998: {
4999: rtx prev, prev1;
5000:
5001: for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
5002: prev = PREV_INSN (prev))
5003: if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5004: && dead_or_set_p (prev, oldequiv_reg))
5005: {
5006: if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
5007: {
5008: for (prev1 = this_reload_insn;
5009: prev1; prev1 = PREV_INSN (prev1))
5010: if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
5011: && reg_overlap_mentioned_p (oldequiv_reg,
5012: PATTERN (prev1)))
5013: {
5014: REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
5015: oldequiv_reg,
5016: REG_NOTES (prev1));
5017: break;
5018: }
5019: remove_death (REGNO (oldequiv_reg), prev);
5020: }
5021: break;
5022: }
5023: }
5024: #endif
5025:
5026: /* If we are reloading a register that was recently stored in with an
5027: output-reload, see if we can prove there was
5028: actually no need to store the old value in it. */
5029:
5030: if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
5031: /* This is unsafe if some other reload uses the same reg first. */
5032: && (reload_when_needed[j] == RELOAD_OTHER
5033: || reload_when_needed[j] == RELOAD_FOR_INPUT
5034: || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS)
5035: && GET_CODE (reload_in[j]) == REG
5036: #if 0
5037: /* There doesn't seem to be any reason to restrict this to pseudos
5038: and doing so loses in the case where we are copying from a
5039: register of the wrong class. */
5040: && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
5041: #endif
5042: && spill_reg_store[reload_spill_index[j]] != 0
5043: && dead_or_set_p (insn, reload_in[j])
5044: /* This is unsafe if operand occurs more than once in current
5045: insn. Perhaps some occurrences weren't reloaded. */
5046: && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5047: delete_output_reload (insn, j,
5048: spill_reg_store[reload_spill_index[j]]);
5049:
5050: /* Input-reloading is done. Now do output-reloading,
5051: storing the value from the reload-register after the main insn
5052: if reload_out[j] is nonzero.
5053:
5054: ??? At some point we need to support handling output reloads of
5055: JUMP_INSNs or insns that set cc0. */
5056: old = reload_out[j];
5057: if (old != 0
5058: && reload_reg_rtx[j] != old
5059: && reload_reg_rtx[j] != 0)
5060: {
5061: register rtx reloadreg = reload_reg_rtx[j];
5062: register rtx second_reloadreg = 0;
5063: rtx prev_insn = PREV_INSN (first_output_reload_insn);
5064: rtx note, p;
5065: enum machine_mode mode;
5066: int special = 0;
5067:
5068: /* An output operand that dies right away does need a reload,
5069: but need not be copied from it. Show the new location in the
5070: REG_UNUSED note. */
5071: if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
5072: && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
5073: {
5074: XEXP (note, 0) = reload_reg_rtx[j];
5075: continue;
5076: }
5077: else if (GET_CODE (old) == SCRATCH)
5078: /* If we aren't optimizing, there won't be a REG_UNUSED note,
5079: but we don't want to make an output reload. */
5080: continue;
5081:
5082: #if 0
5083: /* Strip off of OLD any size-increasing SUBREGs such as
5084: (SUBREG:SI foo:QI 0). */
5085:
5086: while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
5087: && (GET_MODE_SIZE (GET_MODE (old))
5088: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
5089: old = SUBREG_REG (old);
5090: #endif
5091:
5092: /* If is a JUMP_INSN, we can't support output reloads yet. */
5093: if (GET_CODE (insn) == JUMP_INSN)
5094: abort ();
5095:
5096: /* Determine the mode to reload in.
5097: See comments above (for input reloading). */
5098:
5099: mode = GET_MODE (old);
5100: if (mode == VOIDmode)
5101: abort (); /* Should never happen for an output. */
5102:
5103: /* A strict-low-part output operand needs to be reloaded
5104: in the mode of the entire value. */
5105: if (reload_strict_low[j])
5106: {
5107: mode = GET_MODE (SUBREG_REG (reload_out[j]));
5108: /* Encapsulate OLD into that mode. */
5109: /* If OLD is a subreg, then strip it, since the subreg will
5110: be altered by this very reload. */
5111: while (GET_CODE (old) == SUBREG && GET_MODE (old) != mode)
5112: old = SUBREG_REG (old);
5113: if (GET_MODE (old) != VOIDmode
5114: && mode != GET_MODE (old))
5115: old = gen_rtx (SUBREG, mode, old, 0);
5116: }
5117:
5118: if (GET_MODE (reloadreg) != mode)
5119: reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5120:
5121: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5122:
5123: /* If we need two reload regs, set RELOADREG to the intermediate
5124: one, since it will be stored into OUT. We might need a secondary
5125: register only for an input reload, so check again here. */
5126:
1.1.1.2 ! root 5127: if (reload_secondary_reload[j] >= 0)
1.1 root 5128: {
1.1.1.2 ! root 5129: rtx real_old = old;
1.1 root 5130:
1.1.1.2 ! root 5131: if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
! 5132: && reg_equiv_mem[REGNO (old)] != 0)
! 5133: real_old = reg_equiv_mem[REGNO (old)];
1.1 root 5134:
1.1.1.2 ! root 5135: if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
! 5136: mode, real_old)
! 5137: != NO_REGS))
! 5138: {
! 5139: second_reloadreg = reloadreg;
! 5140: reloadreg = reload_reg_rtx[reload_secondary_reload[j]];
1.1 root 5141:
1.1.1.2 ! root 5142: /* See if RELOADREG is to be used as a scratch register
! 5143: or as an intermediate register. */
! 5144: if (reload_secondary_icode[j] != CODE_FOR_nothing)
1.1 root 5145: {
1.1.1.2 ! root 5146: emit_insn_before ((GEN_FCN (reload_secondary_icode[j])
! 5147: (real_old, second_reloadreg,
! 5148: reloadreg)),
! 5149: first_output_reload_insn);
! 5150: special = 1;
1.1 root 5151: }
5152: else
1.1.1.2 ! root 5153: {
! 5154: /* See if we need both a scratch and intermediate reload
! 5155: register. */
! 5156: int secondary_reload = reload_secondary_reload[j];
! 5157: enum insn_code tertiary_icode
! 5158: = reload_secondary_icode[secondary_reload];
! 5159: rtx pat;
! 5160:
! 5161: if (GET_MODE (reloadreg) != mode)
! 5162: reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
1.1 root 5163:
1.1.1.2 ! root 5164: if (tertiary_icode != CODE_FOR_nothing)
! 5165: {
! 5166: rtx third_reloadreg
! 5167: = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
! 5168: pat = (GEN_FCN (tertiary_icode)
! 5169: (reloadreg, second_reloadreg, third_reloadreg));
! 5170: }
! 5171: else
! 5172: pat = gen_move_insn (reloadreg, second_reloadreg);
! 5173:
! 5174: emit_insn_before (pat, first_output_reload_insn);
! 5175: }
1.1 root 5176: }
5177: }
5178: #endif
5179:
5180: /* Output the last reload insn. */
5181: if (! special)
5182: emit_insn_before (gen_move_insn (old, reloadreg),
5183: first_output_reload_insn);
5184:
5185: #ifdef PRESERVE_DEATH_INFO_REGNO_P
5186: /* If final will look at death notes for this reg,
5187: put one on the last output-reload insn to use it. Similarly
5188: for any secondary register. */
5189: if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
5190: for (p = PREV_INSN (first_output_reload_insn);
5191: p != prev_insn; p = PREV_INSN (p))
5192: if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
5193: && reg_overlap_mentioned_p (reloadreg, PATTERN (p)))
5194: REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5195: reloadreg, REG_NOTES (p));
5196:
5197: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5198: if (! special
5199: && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
5200: for (p = PREV_INSN (first_output_reload_insn);
5201: p != prev_insn; p = PREV_INSN (p))
5202: if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
5203: && reg_overlap_mentioned_p (second_reloadreg, PATTERN (p)))
5204: REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5205: second_reloadreg, REG_NOTES (p));
5206: #endif
5207: #endif
5208: /* Look at all insns we emitted, just to be safe. */
5209: for (p = NEXT_INSN (prev_insn); p != first_output_reload_insn;
5210: p = NEXT_INSN (p))
5211: if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
5212: {
5213: /* If this output reload doesn't come from a spill reg,
5214: clear any memory of reloaded copies of the pseudo reg.
5215: If this output reload comes from a spill reg,
5216: reg_has_output_reload will make this do nothing. */
5217: note_stores (PATTERN (p), forget_old_reloads_1);
5218:
5219: if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p)))
5220: store_insn = p;
5221: }
5222:
5223: first_output_reload_insn = NEXT_INSN (prev_insn);
5224: }
5225:
5226: if (reload_spill_index[j] >= 0)
5227: new_spill_reg_store[reload_spill_index[j]] = store_insn;
5228: }
5229:
5230: /* Move death notes from INSN
5231: to output-operand-address and output reload insns. */
5232: #ifdef PRESERVE_DEATH_INFO_REGNO_P
5233: {
5234: rtx insn1;
5235: /* Loop over those insns, last ones first. */
5236: for (insn1 = PREV_INSN (following_insn); insn1 != insn;
5237: insn1 = PREV_INSN (insn1))
5238: if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
5239: {
5240: rtx source = SET_SRC (PATTERN (insn1));
5241: rtx dest = SET_DEST (PATTERN (insn1));
5242:
5243: /* The note we will examine next. */
5244: rtx reg_notes = REG_NOTES (insn);
5245: /* The place that pointed to this note. */
5246: rtx *prev_reg_note = ®_NOTES (insn);
5247:
5248: /* If the note is for something used in the source of this
5249: reload insn, or in the output address, move the note. */
5250: while (reg_notes)
5251: {
5252: rtx next_reg_notes = XEXP (reg_notes, 1);
5253: if (REG_NOTE_KIND (reg_notes) == REG_DEAD
5254: && GET_CODE (XEXP (reg_notes, 0)) == REG
5255: && ((GET_CODE (dest) != REG
5256: && reg_overlap_mentioned_p (XEXP (reg_notes, 0), dest))
5257: || reg_overlap_mentioned_p (XEXP (reg_notes, 0), source)))
5258: {
5259: *prev_reg_note = next_reg_notes;
5260: XEXP (reg_notes, 1) = REG_NOTES (insn1);
5261: REG_NOTES (insn1) = reg_notes;
5262: }
5263: else
5264: prev_reg_note = &XEXP (reg_notes, 1);
5265:
5266: reg_notes = next_reg_notes;
5267: }
5268: }
5269: }
5270: #endif
5271:
5272: /* For all the spill regs newly reloaded in this instruction,
5273: record what they were reloaded from, so subsequent instructions
5274: can inherit the reloads.
5275:
5276: Update spill_reg_store for the reloads of this insn.
5277: Copy the elements that were updated in the loop above. */
5278:
5279: for (j = 0; j < n_reloads; j++)
5280: {
5281: register int r = reload_order[j];
5282: register int i = reload_spill_index[r];
5283:
5284: /* I is nonneg if this reload used one of the spill regs.
5285: If reload_reg_rtx[r] is 0, this is an optional reload
5286: that we opted to ignore. */
5287:
5288: if (i >= 0 && reload_reg_rtx[r] != 0)
5289: {
5290: /* First, clear out memory of what used to be in this spill reg.
5291: If consecutive registers are used, clear them all. */
5292: int nr
5293: = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
5294: int k;
5295:
5296: for (k = 0; k < nr; k++)
5297: {
5298: reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
5299: reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
5300: }
5301:
5302: /* Maybe the spill reg contains a copy of reload_out. */
5303: if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
5304: {
5305: register int nregno = REGNO (reload_out[r]);
5306:
5307: spill_reg_store[i] = new_spill_reg_store[i];
5308: reg_last_reload_reg[nregno] = reload_reg_rtx[r];
5309:
5310: for (k = 0; k < nr; k++)
5311: {
5312: reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5313: = nregno;
5314: reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
5315: }
5316: }
5317:
5318: /* Maybe the spill reg contains a copy of reload_in. */
5319: else if (reload_out[r] == 0
5320: && reload_in[r] != 0
5321: && (GET_CODE (reload_in[r]) == REG
5322: || GET_CODE (reload_in_reg[r]) == REG))
5323: {
5324: register int nregno;
5325: if (GET_CODE (reload_in[r]) == REG)
5326: nregno = REGNO (reload_in[r]);
5327: else
5328: nregno = REGNO (reload_in_reg[r]);
5329:
5330: /* If there are two separate reloads (one in and one out)
5331: for the same (hard or pseudo) reg,
5332: leave reg_last_reload_reg set
5333: based on the output reload.
5334: Otherwise, set it from this input reload. */
5335: if (!reg_has_output_reload[nregno]
5336: /* But don't do so if another input reload
5337: will clobber this one's value. */
5338: && reload_reg_reaches_end_p (spill_regs[i],
5339: reload_when_needed[r]))
5340: {
5341: reg_last_reload_reg[nregno] = reload_reg_rtx[r];
5342:
5343: /* Unless we inherited this reload, show we haven't
5344: recently done a store. */
5345: if (! reload_inherited[r])
5346: spill_reg_store[i] = 0;
5347:
5348: for (k = 0; k < nr; k++)
5349: {
5350: reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5351: = nregno;
5352: reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
5353: = insn;
5354: }
5355: }
5356: }
5357: }
5358:
5359: /* The following if-statement was #if 0'd in 1.34 (or before...).
5360: It's reenabled in 1.35 because supposedly nothing else
5361: deals with this problem. */
5362:
5363: /* If a register gets output-reloaded from a non-spill register,
5364: that invalidates any previous reloaded copy of it.
5365: But forget_old_reloads_1 won't get to see it, because
5366: it thinks only about the original insn. So invalidate it here. */
5367: if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
5368: {
5369: register int nregno = REGNO (reload_out[r]);
5370: reg_last_reload_reg[nregno] = 0;
5371: }
5372: }
5373: }
5374:
5375: /* Emit code before BEFORE_INSN to perform an input reload of IN to RELOADREG.
5376: Returns first insn emitted. */
5377:
5378: rtx
5379: gen_input_reload (reloadreg, in, before_insn)
5380: rtx reloadreg;
5381: rtx in;
5382: rtx before_insn;
5383: {
5384: register rtx prev_insn = PREV_INSN (before_insn);
5385:
5386: /* How to do this reload can get quite tricky. Normally, we are being
5387: asked to reload a simple operand, such as a MEM, a constant, or a pseudo
5388: register that didn't get a hard register. In that case we can just
5389: call emit_move_insn.
5390:
5391: We can also be asked to reload a PLUS that adds either two registers or
5392: a register and a constant or MEM. This can occur during frame pointer
5393: elimination. That case if handled by trying to emit a single insn
5394: to perform the add. If it is not valid, we use a two insn sequence.
5395:
5396: Finally, we could be called to handle an 'o' constraint by putting
5397: an address into a register. In that case, we first try to do this
5398: with a named pattern of "reload_load_address". If no such pattern
5399: exists, we just emit a SET insn and hope for the best (it will normally
5400: be valid on machines that use 'o').
5401:
5402: This entire process is made complex because reload will never
5403: process the insns we generate here and so we must ensure that
5404: they will fit their constraints and also by the fact that parts of
5405: IN might be being reloaded separately and replaced with spill registers.
5406: Because of this, we are, in some sense, just guessing the right approach
5407: here. The one listed above seems to work.
5408:
5409: ??? At some point, this whole thing needs to be rethought. */
5410:
5411: if (GET_CODE (in) == PLUS
5412: && GET_CODE (XEXP (in, 0)) == REG
5413: && (GET_CODE (XEXP (in, 1)) == REG
5414: || CONSTANT_P (XEXP (in, 1))
5415: || GET_CODE (XEXP (in, 1)) == MEM))
5416: {
5417: /* We need to compute the sum of what is either a register and a
5418: constant, a register and memory, or a hard register and a pseudo
5419: register and put it into the reload register. The best possible way
5420: of doing this is if the machine has a three-operand ADD insn that
5421: accepts the required operands.
5422:
5423: The simplest approach is to try to generate such an insn and see if it
5424: is recognized and matches its constraints. If so, it can be used.
5425:
5426: It might be better not to actually emit the insn unless it is valid,
1.1.1.2 ! root 5427: but we need to pass the insn as an operand to `recog' and
! 5428: `insn_extract'and it is simpler to emit and then delete the insn if
! 5429: not valid than to dummy things up. */
1.1 root 5430:
5431: rtx move_operand, other_operand, insn;
5432: int code;
5433:
5434: /* Since constraint checking is strict, commutativity won't be
5435: checked, so we need to do that here to avoid spurious failure
5436: if the add instruction is two-address and the second operand
5437: of the add is the same as the reload reg, which is frequently
5438: the case. If the insn would be A = B + A, rearrange it so
5439: it will be A = A + B as constrain_operands expects. */
5440:
5441: if (GET_CODE (XEXP (in, 1)) == REG
5442: && REGNO (reloadreg) == REGNO (XEXP (in, 1)))
5443: in = gen_rtx (PLUS, GET_MODE (in), XEXP (in, 1), XEXP (in, 0));
5444:
5445: insn = emit_insn_before (gen_rtx (SET, VOIDmode, reloadreg, in),
5446: before_insn);
5447: code = recog_memoized (insn);
5448:
5449: if (code >= 0)
5450: {
5451: insn_extract (insn);
5452: /* We want constrain operands to treat this insn strictly in
5453: its validity determination, i.e., the way it would after reload
5454: has completed. */
5455: if (constrain_operands (code, 1))
5456: return insn;
5457: }
5458:
5459: if (PREV_INSN (insn))
5460: NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
5461: if (NEXT_INSN (insn))
5462: PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
5463:
5464: /* If that failed, we must use a conservative two-insn sequence.
5465: use move to copy constant, MEM, or pseudo register to the reload
5466: register since "move" will be able to handle arbitrary operand, unlike
5467: add which can't, in general. Then add the registers.
5468:
5469: If there is another way to do this for a specific machine, a
5470: DEFINE_PEEPHOLE should be specified that recognizes the sequence
5471: we emit below. */
5472:
5473: if (CONSTANT_P (XEXP (in, 1))
1.1.1.2 ! root 5474: || GET_CODE (XEXP (in, 1)) == MEM
1.1 root 5475: || (GET_CODE (XEXP (in, 1)) == REG
5476: && REGNO (XEXP (in, 1)) >= FIRST_PSEUDO_REGISTER))
5477: move_operand = XEXP (in, 1), other_operand = XEXP (in, 0);
5478: else
5479: move_operand = XEXP (in, 0), other_operand = XEXP (in, 1);
5480:
5481: emit_insn_before (gen_move_insn (reloadreg, move_operand), before_insn);
5482: emit_insn_before (gen_add2_insn (reloadreg, other_operand), before_insn);
5483: }
5484:
5485: /* If IN is a simple operand, use gen_move_insn. */
5486: else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
5487: emit_insn_before (gen_move_insn (reloadreg, in), before_insn);
5488:
5489: #ifdef HAVE_reload_load_address
5490: else if (HAVE_reload_load_address)
5491: emit_insn_before (gen_reload_load_address (reloadreg, in), before_insn);
5492: #endif
5493:
5494: /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */
5495: else
5496: emit_insn_before (gen_rtx (SET, VOIDmode, reloadreg, in), before_insn);
5497:
5498: /* Return the first insn emitted.
5499: We can not just return PREV_INSN (before_insn), because there may have
5500: been multiple instructions emitted. Also note that gen_move_insn may
5501: emit more than one insn itself, so we can not assume that there is one
5502: insn emitted per emit_insn_before call. */
5503:
5504: return NEXT_INSN (prev_insn);
5505: }
5506:
5507: /* Delete a previously made output-reload
5508: whose result we now believe is not needed.
5509: First we double-check.
5510:
5511: INSN is the insn now being processed.
5512: OUTPUT_RELOAD_INSN is the insn of the output reload.
5513: J is the reload-number for this insn. */
5514:
5515: static void
5516: delete_output_reload (insn, j, output_reload_insn)
5517: rtx insn;
5518: int j;
5519: rtx output_reload_insn;
5520: {
5521: register rtx i1;
5522:
5523: /* Get the raw pseudo-register referred to. */
5524:
5525: rtx reg = reload_in[j];
5526: while (GET_CODE (reg) == SUBREG)
5527: reg = SUBREG_REG (reg);
5528:
5529: /* If the pseudo-reg we are reloading is no longer referenced
5530: anywhere between the store into it and here,
5531: and no jumps or labels intervene, then the value can get
5532: here through the reload reg alone.
5533: Otherwise, give up--return. */
5534: for (i1 = NEXT_INSN (output_reload_insn);
5535: i1 != insn; i1 = NEXT_INSN (i1))
5536: {
5537: if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
5538: return;
5539: if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
5540: && reg_mentioned_p (reg, PATTERN (i1)))
5541: return;
5542: }
5543:
5544: /* If this insn will store in the pseudo again,
5545: the previous store can be removed. */
5546: if (reload_out[j] == reload_in[j])
5547: delete_insn (output_reload_insn);
5548:
5549: /* See if the pseudo reg has been completely replaced
5550: with reload regs. If so, delete the store insn
5551: and forget we had a stack slot for the pseudo. */
5552: else if (reg_n_deaths[REGNO (reg)] == 1
5553: && reg_basic_block[REGNO (reg)] >= 0
5554: && find_regno_note (insn, REG_DEAD, REGNO (reg)))
5555: {
5556: rtx i2;
5557:
5558: /* We know that it was used only between here
5559: and the beginning of the current basic block.
5560: (We also know that the last use before INSN was
5561: the output reload we are thinking of deleting, but never mind that.)
5562: Search that range; see if any ref remains. */
5563: for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
5564: {
5565: rtx set = single_set (i2);
5566:
5567: /* Uses which just store in the pseudo don't count,
5568: since if they are the only uses, they are dead. */
5569: if (set != 0 && SET_DEST (set) == reg)
5570: continue;
5571: if (GET_CODE (i2) == CODE_LABEL
5572: || GET_CODE (i2) == JUMP_INSN)
5573: break;
5574: if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
5575: && reg_mentioned_p (reg, PATTERN (i2)))
5576: /* Some other ref remains;
5577: we can't do anything. */
5578: return;
5579: }
5580:
5581: /* Delete the now-dead stores into this pseudo. */
5582: for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
5583: {
5584: rtx set = single_set (i2);
5585:
5586: if (set != 0 && SET_DEST (set) == reg)
5587: delete_insn (i2);
5588: if (GET_CODE (i2) == CODE_LABEL
5589: || GET_CODE (i2) == JUMP_INSN)
5590: break;
5591: }
5592:
5593: /* For the debugging info,
5594: say the pseudo lives in this reload reg. */
5595: reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
5596: alter_reg (REGNO (reg), -1);
5597: }
5598: }
5599:
5600:
5601: /* Output reload-insns to reload VALUE into RELOADREG.
5602: VALUE is a autoincrement or autodecrement RTX whose operand
5603: is a register or memory location;
5604: so reloading involves incrementing that location.
5605:
5606: INC_AMOUNT is the number to increment or decrement by (always positive).
5607: This cannot be deduced from VALUE.
5608:
5609: INSN is the insn before which the new insns should be emitted.
5610:
5611: The return value is the first of the insns emitted. */
5612:
5613: static rtx
5614: inc_for_reload (reloadreg, value, inc_amount, insn)
5615: rtx reloadreg;
5616: rtx value;
5617: int inc_amount;
5618: rtx insn;
5619: {
5620: /* REG or MEM to be copied and incremented. */
5621: rtx incloc = XEXP (value, 0);
5622: /* Nonzero if increment after copying. */
5623: int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
1.1.1.2 ! root 5624: rtx prev = PREV_INSN (insn);
! 5625: rtx inc;
! 5626: rtx add_insn;
! 5627: enum insn_code code;
1.1 root 5628:
5629: /* No hard register is equivalent to this register after
5630: inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
5631: we could inc/dec that register as well (maybe even using it for
5632: the source), but I'm not sure it's worth worrying about. */
5633: if (GET_CODE (incloc) == REG)
5634: reg_last_reload_reg[REGNO (incloc)] = 0;
5635:
5636: if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
5637: inc_amount = - inc_amount;
5638:
1.1.1.2 ! root 5639: inc = gen_rtx (CONST_INT, VOIDmode, inc_amount);
! 5640:
! 5641: /* If this is post-increment, first copy the location to the reload reg. */
! 5642: if (post)
! 5643: emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
! 5644:
! 5645: /* See if we can directly increment INCLOC. Use a method similar to that
! 5646: in gen_input_reload. */
! 5647:
! 5648: add_insn = emit_insn_before (gen_rtx (SET, VOIDmode, incloc,
! 5649: gen_rtx (PLUS, GET_MODE (incloc),
! 5650: incloc, inc)), insn);
! 5651:
! 5652: code = recog_memoized (add_insn);
! 5653: if (code >= 0)
1.1 root 5654: {
1.1.1.2 ! root 5655: insn_extract (add_insn);
! 5656: if (constrain_operands (code, 1))
! 5657: {
! 5658: /* If this is a pre-increment and we have incremented the value
! 5659: where it lives, copy the incremented value to RELOADREG to
! 5660: be used as an address. */
! 5661:
! 5662: if (! post)
! 5663: emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
! 5664: return NEXT_INSN (prev);
1.1 root 5665: }
1.1.1.2 ! root 5666: }
! 5667:
! 5668: if (PREV_INSN (add_insn))
! 5669: NEXT_INSN (PREV_INSN (add_insn)) = NEXT_INSN (add_insn);
! 5670: if (NEXT_INSN (add_insn))
! 5671: PREV_INSN (NEXT_INSN (add_insn)) = PREV_INSN (add_insn);
! 5672:
! 5673: /* If couldn't do the increment directly, must increment in RELOADREG.
! 5674: The way we do this depends on whether this is pre- or post-increment.
! 5675: For pre-increment, copy INCLOC to the reload register, increment it
! 5676: there, then save back. */
! 5677:
! 5678: if (! post)
! 5679: {
! 5680: emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
! 5681: emit_insn_before (gen_add2_insn (reloadreg, inc), insn);
! 5682: emit_insn_before (gen_move_insn (incloc, reloadreg), insn);
! 5683: }
1.1 root 5684: else
5685: {
1.1.1.2 ! root 5686: /* Postincrement.
! 5687: Because this might be a jump insn or a compare, and because RELOADREG
! 5688: may not be available after the insn in an input reload, we must do
! 5689: the incrementation before the insn being reloaded for.
! 5690:
! 5691: We have already copied INCLOC to RELOADREG. Increment the copy in
! 5692: RELOADREG, save that back, then decrement RELOADREG so it has
! 5693: the original value. */
! 5694:
! 5695: emit_insn_before (gen_add2_insn (reloadreg, inc), insn);
! 5696: emit_insn_before (gen_move_insn (incloc, reloadreg), insn);
! 5697: emit_insn_before (gen_add2_insn (reloadreg,
! 5698: gen_rtx (CONST_INT, VOIDmode,
! 5699: -inc_amount)),
! 5700: insn);
1.1 root 5701: }
1.1.1.2 ! root 5702:
! 5703: return NEXT_INSN (prev);
1.1 root 5704: }
5705:
5706: /* Return 1 if we are certain that the constraint-string STRING allows
5707: the hard register REG. Return 0 if we can't be sure of this. */
5708:
5709: static int
5710: constraint_accepts_reg_p (string, reg)
5711: char *string;
5712: rtx reg;
5713: {
5714: int value = 0;
5715: int regno = true_regnum (reg);
5716: int c;
5717:
5718: /* Initialize for first alternative. */
5719: value = 0;
5720: /* Check that each alternative contains `g' or `r'. */
5721: while (1)
5722: switch (c = *string++)
5723: {
5724: case 0:
5725: /* If an alternative lacks `g' or `r', we lose. */
5726: return value;
5727: case ',':
5728: /* If an alternative lacks `g' or `r', we lose. */
5729: if (value == 0)
5730: return 0;
5731: /* Initialize for next alternative. */
5732: value = 0;
5733: break;
5734: case 'g':
5735: case 'r':
5736: /* Any general reg wins for this alternative. */
5737: if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
5738: value = 1;
5739: break;
5740: default:
5741: /* Any reg in specified class wins for this alternative. */
5742: {
5743: int class = REG_CLASS_FROM_LETTER (c);
5744:
5745: if (TEST_HARD_REG_BIT (reg_class_contents[class], regno))
5746: value = 1;
5747: }
5748: }
5749: }
5750:
5751: /* Return the number of places FIND appears within X, but don't count
5752: an occurrence if some SET_DEST is FIND. */
5753:
5754: static int
5755: count_occurrences (x, find)
5756: register rtx x, find;
5757: {
5758: register int i, j;
5759: register enum rtx_code code;
5760: register char *format_ptr;
5761: int count;
5762:
5763: if (x == find)
5764: return 1;
5765: if (x == 0)
5766: return 0;
5767:
5768: code = GET_CODE (x);
5769:
5770: switch (code)
5771: {
5772: case REG:
5773: case QUEUED:
5774: case CONST_INT:
5775: case CONST_DOUBLE:
5776: case SYMBOL_REF:
5777: case CODE_LABEL:
5778: case PC:
5779: case CC0:
5780: return 0;
5781:
5782: case SET:
5783: if (SET_DEST (x) == find)
5784: return count_occurrences (SET_SRC (x), find);
5785: break;
5786: }
5787:
5788: format_ptr = GET_RTX_FORMAT (code);
5789: count = 0;
5790:
5791: for (i = 0; i < GET_RTX_LENGTH (code); i++)
5792: {
5793: switch (*format_ptr++)
5794: {
5795: case 'e':
5796: count += count_occurrences (XEXP (x, i), find);
5797: break;
5798:
5799: case 'E':
5800: if (XVEC (x, i) != NULL)
5801: {
5802: for (j = 0; j < XVECLEN (x, i); j++)
5803: count += count_occurrences (XVECEXP (x, i, j), find);
5804: }
5805: break;
5806: }
5807: }
5808: return count;
5809: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.