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1.1 root 1: /* Reload pseudo regs into hard regs for insns that require hard regs.
2: Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: #include "config.h"
22: #include "rtl.h"
23: #include "obstack.h"
24: #include "insn-config.h"
25: #include "insn-flags.h"
26: #include "insn-codes.h"
27: #include "flags.h"
28: #include "expr.h"
29: #include "regs.h"
30: #include "hard-reg-set.h"
31: #include "reload.h"
32: #include "recog.h"
33: #include "basic-block.h"
34: #include "output.h"
35: #include <stdio.h>
36:
37: /* This file contains the reload pass of the compiler, which is
38: run after register allocation has been done. It checks that
39: each insn is valid (operands required to be in registers really
40: are in registers of the proper class) and fixes up invalid ones
41: by copying values temporarily into registers for the insns
42: that need them.
43:
44: The results of register allocation are described by the vector
45: reg_renumber; the insns still contain pseudo regs, but reg_renumber
46: can be used to find which hard reg, if any, a pseudo reg is in.
47:
48: The technique we always use is to free up a few hard regs that are
49: called ``reload regs'', and for each place where a pseudo reg
50: must be in a hard reg, copy it temporarily into one of the reload regs.
51:
52: All the pseudos that were formerly allocated to the hard regs that
53: are now in use as reload regs must be ``spilled''. This means
54: that they go to other hard regs, or to stack slots if no other
55: available hard regs can be found. Spilling can invalidate more
56: insns, requiring additional need for reloads, so we must keep checking
57: until the process stabilizes.
58:
59: For machines with different classes of registers, we must keep track
60: of the register class needed for each reload, and make sure that
61: we allocate enough reload registers of each class.
62:
63: The file reload.c contains the code that checks one insn for
64: validity and reports the reloads that it needs. This file
65: is in charge of scanning the entire rtl code, accumulating the
66: reload needs, spilling, assigning reload registers to use for
67: fixing up each insn, and generating the new insns to copy values
68: into the reload registers. */
69:
70: /* During reload_as_needed, element N contains a REG rtx for the hard reg
71: into which pseudo reg N has been reloaded (perhaps for a previous insn). */
72: static rtx *reg_last_reload_reg;
73:
74: /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
75: for an output reload that stores into reg N. */
76: static char *reg_has_output_reload;
77:
78: /* Indicates which hard regs are reload-registers for an output reload
79: in the current insn. */
80: static HARD_REG_SET reg_is_output_reload;
81:
82: /* Element N is the constant value to which pseudo reg N is equivalent,
83: or zero if pseudo reg N is not equivalent to a constant.
84: find_reloads looks at this in order to replace pseudo reg N
85: with the constant it stands for. */
86: rtx *reg_equiv_constant;
87:
88: /* Element N is a memory location to which pseudo reg N is equivalent,
89: prior to any register elimination (such as frame pointer to stack
90: pointer). Depending on whether or not it is a valid address, this value
91: is transferred to either reg_equiv_address or reg_equiv_mem. */
1.1.1.3 ! root 92: rtx *reg_equiv_memory_loc;
1.1 root 93:
94: /* Element N is the address of stack slot to which pseudo reg N is equivalent.
95: This is used when the address is not valid as a memory address
96: (because its displacement is too big for the machine.) */
97: rtx *reg_equiv_address;
98:
99: /* Element N is the memory slot to which pseudo reg N is equivalent,
100: or zero if pseudo reg N is not equivalent to a memory slot. */
101: rtx *reg_equiv_mem;
102:
103: /* Widest width in which each pseudo reg is referred to (via subreg). */
104: static int *reg_max_ref_width;
105:
106: /* Element N is the insn that initialized reg N from its equivalent
107: constant or memory slot. */
108: static rtx *reg_equiv_init;
109:
110: /* During reload_as_needed, element N contains the last pseudo regno
111: reloaded into the Nth reload register. This vector is in parallel
112: with spill_regs. If that pseudo reg occupied more than one register,
113: reg_reloaded_contents points to that pseudo for each spill register in
114: use; all of these must remain set for an inheritance to occur. */
115: static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
116:
117: /* During reload_as_needed, element N contains the insn for which
118: the Nth reload register was last used. This vector is in parallel
119: with spill_regs, and its contents are significant only when
120: reg_reloaded_contents is significant. */
121: static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
122:
123: /* Number of spill-regs so far; number of valid elements of spill_regs. */
124: static int n_spills;
125:
126: /* In parallel with spill_regs, contains REG rtx's for those regs.
127: Holds the last rtx used for any given reg, or 0 if it has never
128: been used for spilling yet. This rtx is reused, provided it has
129: the proper mode. */
130: static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
131:
132: /* In parallel with spill_regs, contains nonzero for a spill reg
133: that was stored after the last time it was used.
134: The precise value is the insn generated to do the store. */
135: static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
136:
137: /* This table is the inverse mapping of spill_regs:
138: indexed by hard reg number,
139: it contains the position of that reg in spill_regs,
140: or -1 for something that is not in spill_regs. */
141: static short spill_reg_order[FIRST_PSEUDO_REGISTER];
142:
143: /* This reg set indicates registers that may not be used for retrying global
144: allocation. The registers that may not be used include all spill registers
145: and the frame pointer (if we are using one). */
146: HARD_REG_SET forbidden_regs;
147:
148: /* This reg set indicates registers that are not good for spill registers.
149: They will not be used to complete groups of spill registers. This includes
150: all fixed registers, registers that may be eliminated, and registers
151: explicitly used in the rtl.
152:
153: (spill_reg_order prevents these registers from being used to start a
154: group.) */
155: static HARD_REG_SET bad_spill_regs;
156:
157: /* Describes order of use of registers for reloading
158: of spilled pseudo-registers. `spills' is the number of
159: elements that are actually valid; new ones are added at the end. */
160: static short spill_regs[FIRST_PSEUDO_REGISTER];
161:
162: /* Describes order of preference for putting regs into spill_regs.
163: Contains the numbers of all the hard regs, in order most preferred first.
164: This order is different for each function.
165: It is set up by order_regs_for_reload.
166: Empty elements at the end contain -1. */
167: static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
168:
169: /* 1 for a hard register that appears explicitly in the rtl
170: (for example, function value registers, special registers
171: used by insns, structure value pointer registers). */
172: static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
173:
174: /* Indicates if a register was counted against the need for
175: groups. 0 means it can count against max_nongroup instead. */
176: static HARD_REG_SET counted_for_groups;
177:
178: /* Indicates if a register was counted against the need for
179: non-groups. 0 means it can become part of a new group.
180: During choose_reload_regs, 1 here means don't use this reg
181: as part of a group, even if it seems to be otherwise ok. */
182: static HARD_REG_SET counted_for_nongroups;
183:
184: /* Nonzero if indirect addressing is supported on the machine; this means
185: that spilling (REG n) does not require reloading it into a register in
186: order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
187: value indicates the level of indirect addressing supported, e.g., two
188: means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
189: a hard register. */
190:
191: static char spill_indirect_levels;
192:
193: /* Nonzero if indirect addressing is supported when the innermost MEM is
194: of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
195: which these are valid is the same as spill_indirect_levels, above. */
196:
197: char indirect_symref_ok;
198:
199: /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
200:
201: char double_reg_address_ok;
202:
203: /* Record the stack slot for each spilled hard register. */
204:
205: static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
206:
207: /* Width allocated so far for that stack slot. */
208:
209: static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
210:
211: /* Indexed by register class and basic block number, nonzero if there is
212: any need for a spill register of that class in that basic block.
213: The pointer is 0 if we did stupid allocation and don't know
214: the structure of basic blocks. */
215:
216: char *basic_block_needs[N_REG_CLASSES];
217:
218: /* First uid used by insns created by reload in this function.
219: Used in find_equiv_reg. */
220: int reload_first_uid;
221:
222: /* Flag set by local-alloc or global-alloc if anything is live in
223: a call-clobbered reg across calls. */
224:
225: int caller_save_needed;
226:
227: /* Set to 1 while reload_as_needed is operating.
228: Required by some machines to handle any generated moves differently. */
229:
230: int reload_in_progress = 0;
231:
232: /* These arrays record the insn_code of insns that may be needed to
233: perform input and output reloads of special objects. They provide a
234: place to pass a scratch register. */
235:
236: enum insn_code reload_in_optab[NUM_MACHINE_MODES];
237: enum insn_code reload_out_optab[NUM_MACHINE_MODES];
238:
1.1.1.2 root 239: /* This obstack is used for allocation of rtl during register elimination.
1.1 root 240: The allocated storage can be freed once find_reloads has processed the
241: insn. */
242:
243: struct obstack reload_obstack;
244: char *reload_firstobj;
245:
246: #define obstack_chunk_alloc xmalloc
247: #define obstack_chunk_free free
248:
249: extern int xmalloc ();
250: extern void free ();
251:
252: /* List of labels that must never be deleted. */
253: extern rtx forced_labels;
254:
255: /* This structure is used to record information about register eliminations.
256: Each array entry describes one possible way of eliminating a register
257: in favor of another. If there is more than one way of eliminating a
258: particular register, the most preferred should be specified first. */
259:
260: static struct elim_table
261: {
262: int from; /* Register number to be eliminated. */
263: int to; /* Register number used as replacement. */
264: int initial_offset; /* Initial difference between values. */
265: int can_eliminate; /* Non-zero if this elimination can be done. */
266: int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
267: insns made by reload. */
268: int offset; /* Current offset between the two regs. */
269: int max_offset; /* Maximum offset between the two regs. */
270: int previous_offset; /* Offset at end of previous insn. */
271: int ref_outside_mem; /* "to" has been referenced outside a MEM. */
272: rtx from_rtx; /* REG rtx for the register to be eliminated.
273: We cannot simply compare the number since
274: we might then spuriously replace a hard
275: register corresponding to a pseudo
276: assigned to the reg to be eliminated. */
277: rtx to_rtx; /* REG rtx for the replacement. */
278: } reg_eliminate[] =
279:
280: /* If a set of eliminable registers was specified, define the table from it.
281: Otherwise, default to the normal case of the frame pointer being
282: replaced by the stack pointer. */
283:
284: #ifdef ELIMINABLE_REGS
285: ELIMINABLE_REGS;
286: #else
287: {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
288: #endif
289:
290: #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
291:
292: /* Record the number of pending eliminations that have an offset not equal
293: to their initial offset. If non-zero, we use a new copy of each
294: replacement result in any insns encountered. */
295: static int num_not_at_initial_offset;
296:
297: /* Count the number of registers that we may be able to eliminate. */
298: static int num_eliminable;
299:
300: /* For each label, we record the offset of each elimination. If we reach
301: a label by more than one path and an offset differs, we cannot do the
302: elimination. This information is indexed by the number of the label.
303: The first table is an array of flags that records whether we have yet
304: encountered a label and the second table is an array of arrays, one
305: entry in the latter array for each elimination. */
306:
307: static char *offsets_known_at;
308: static int (*offsets_at)[NUM_ELIMINABLE_REGS];
309:
310: /* Number of labels in the current function. */
311:
312: static int num_labels;
313:
314: void mark_home_live ();
315: static void count_possible_groups ();
316: static int possible_group_p ();
317: static void scan_paradoxical_subregs ();
318: static void reload_as_needed ();
319: static int modes_equiv_for_class_p ();
320: static void alter_reg ();
321: static void delete_dead_insn ();
322: static int new_spill_reg();
323: static void set_label_offsets ();
324: static int eliminate_regs_in_insn ();
325: static void mark_not_eliminable ();
326: static int spill_hard_reg ();
327: static void choose_reload_regs ();
328: static void emit_reload_insns ();
329: static void delete_output_reload ();
330: static void forget_old_reloads_1 ();
331: static void order_regs_for_reload ();
332: static rtx inc_for_reload ();
333: static int constraint_accepts_reg_p ();
334: static int count_occurrences ();
335:
336: extern void remove_death ();
337: extern rtx adj_offsettable_operand ();
338: extern rtx form_sum ();
339:
340: void
341: init_reload ()
342: {
343: register int i;
344:
345: /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
346: Set spill_indirect_levels to the number of levels such addressing is
347: permitted, zero if it is not permitted at all. */
348:
349: register rtx tem
350: = gen_rtx (MEM, Pmode,
351: gen_rtx (PLUS, Pmode,
352: gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
353: gen_rtx (CONST_INT, VOIDmode, 4)));
354: spill_indirect_levels = 0;
355:
356: while (memory_address_p (QImode, tem))
357: {
358: spill_indirect_levels++;
359: tem = gen_rtx (MEM, Pmode, tem);
360: }
361:
362: /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
363:
364: tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
365: indirect_symref_ok = memory_address_p (QImode, tem);
366:
367: /* See if reg+reg is a valid (and offsettable) address. */
368:
369: tem = gen_rtx (PLUS, Pmode,
370: gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM),
371: gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM));
372: /* This way, we make sure that reg+reg is an offsettable address. */
373: tem = plus_constant (tem, 4);
374:
375: double_reg_address_ok = memory_address_p (QImode, tem);
376:
377: /* Initialize obstack for our rtl allocation. */
378: gcc_obstack_init (&reload_obstack);
379: reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
380:
381: #ifdef HAVE_SECONDARY_RELOADS
382:
383: /* Initialize the optabs for doing special input and output reloads. */
384:
385: for (i = 0; i < NUM_MACHINE_MODES; i++)
386: reload_in_optab[i] = reload_out_optab[i] = CODE_FOR_nothing;
387:
388: #ifdef HAVE_reload_inqi
389: if (HAVE_reload_inqi)
390: reload_in_optab[(int) QImode] = CODE_FOR_reload_inqi;
391: #endif
392: #ifdef HAVE_reload_inhi
393: if (HAVE_reload_inhi)
394: reload_in_optab[(int) HImode] = CODE_FOR_reload_inhi;
395: #endif
396: #ifdef HAVE_reload_insi
397: if (HAVE_reload_insi)
398: reload_in_optab[(int) SImode] = CODE_FOR_reload_insi;
399: #endif
400: #ifdef HAVE_reload_indi
401: if (HAVE_reload_indi)
402: reload_in_optab[(int) DImode] = CODE_FOR_reload_indi;
403: #endif
404: #ifdef HAVE_reload_inti
405: if (HAVE_reload_inti)
406: reload_in_optab[(int) TImode] = CODE_FOR_reload_inti;
407: #endif
408: #ifdef HAVE_reload_insf
409: if (HAVE_reload_insf)
410: reload_in_optab[(int) SFmode] = CODE_FOR_reload_insf;
411: #endif
412: #ifdef HAVE_reload_indf
413: if (HAVE_reload_indf)
414: reload_in_optab[(int) DFmode] = CODE_FOR_reload_indf;
415: #endif
416: #ifdef HAVE_reload_inxf
417: if (HAVE_reload_inxf)
418: reload_in_optab[(int) XFmode] = CODE_FOR_reload_inxf;
419: #endif
420: #ifdef HAVE_reload_intf
421: if (HAVE_reload_intf)
422: reload_in_optab[(int) TFmode] = CODE_FOR_reload_intf;
423: #endif
424:
425: #ifdef HAVE_reload_outqi
426: if (HAVE_reload_outqi)
427: reload_out_optab[(int) QImode] = CODE_FOR_reload_outqi;
428: #endif
429: #ifdef HAVE_reload_outhi
430: if (HAVE_reload_outhi)
431: reload_out_optab[(int) HImode] = CODE_FOR_reload_outhi;
432: #endif
433: #ifdef HAVE_reload_outsi
434: if (HAVE_reload_outsi)
435: reload_out_optab[(int) SImode] = CODE_FOR_reload_outsi;
436: #endif
437: #ifdef HAVE_reload_outdi
438: if (HAVE_reload_outdi)
439: reload_out_optab[(int) DImode] = CODE_FOR_reload_outdi;
440: #endif
441: #ifdef HAVE_reload_outti
442: if (HAVE_reload_outti)
443: reload_out_optab[(int) TImode] = CODE_FOR_reload_outti;
444: #endif
445: #ifdef HAVE_reload_outsf
446: if (HAVE_reload_outsf)
447: reload_out_optab[(int) SFmode] = CODE_FOR_reload_outsf;
448: #endif
449: #ifdef HAVE_reload_outdf
450: if (HAVE_reload_outdf)
451: reload_out_optab[(int) DFmode] = CODE_FOR_reload_outdf;
452: #endif
453: #ifdef HAVE_reload_outxf
454: if (HAVE_reload_outxf)
455: reload_out_optab[(int) XFmode] = CODE_FOR_reload_outxf;
456: #endif
457: #ifdef HAVE_reload_outtf
458: if (HAVE_reload_outtf)
459: reload_out_optab[(int) TFmode] = CODE_FOR_reload_outtf;
460: #endif
461:
462: #endif /* HAVE_SECONDARY_RELOADS */
463:
464: }
465:
466: /* Main entry point for the reload pass, and only entry point
467: in this file.
468:
469: FIRST is the first insn of the function being compiled.
470:
471: GLOBAL nonzero means we were called from global_alloc
472: and should attempt to reallocate any pseudoregs that we
473: displace from hard regs we will use for reloads.
474: If GLOBAL is zero, we do not have enough information to do that,
475: so any pseudo reg that is spilled must go to the stack.
476:
477: DUMPFILE is the global-reg debugging dump file stream, or 0.
478: If it is nonzero, messages are written to it to describe
479: which registers are seized as reload regs, which pseudo regs
480: are spilled from them, and where the pseudo regs are reallocated to. */
481:
482: void
483: reload (first, global, dumpfile)
484: rtx first;
485: int global;
486: FILE *dumpfile;
487: {
488: register int class;
489: register int i;
490: register rtx insn;
491: register struct elim_table *ep;
492:
493: int something_changed;
494: int something_needs_reloads;
495: int something_needs_elimination;
496: int new_basic_block_needs;
497: enum reg_class caller_save_spill_class = NO_REGS;
498: int caller_save_group_size = 1;
499:
500: /* The basic block number currently being processed for INSN. */
501: int this_block;
502:
503: /* Make sure even insns with volatile mem refs are recognizable. */
504: init_recog ();
505:
506: /* Enable find_equiv_reg to distinguish insns made by reload. */
507: reload_first_uid = get_max_uid ();
508:
509: for (i = 0; i < N_REG_CLASSES; i++)
510: basic_block_needs[i] = 0;
511:
512: /* Remember which hard regs appear explicitly
513: before we merge into `regs_ever_live' the ones in which
514: pseudo regs have been allocated. */
515: bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
516:
517: /* We don't have a stack slot for any spill reg yet. */
518: bzero (spill_stack_slot, sizeof spill_stack_slot);
519: bzero (spill_stack_slot_width, sizeof spill_stack_slot_width);
520:
521: /* Initialize the save area information for caller-save, in case some
522: are needed. */
523: init_save_areas ();
524:
525: /* Compute which hard registers are now in use
526: as homes for pseudo registers.
527: This is done here rather than (eg) in global_alloc
528: because this point is reached even if not optimizing. */
529:
530: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
531: mark_home_live (i);
532:
533: /* Make sure that the last insn in the chain
534: is not something that needs reloading. */
535: emit_note (0, NOTE_INSN_DELETED);
536:
537: /* Find all the pseudo registers that didn't get hard regs
538: but do have known equivalent constants or memory slots.
539: These include parameters (known equivalent to parameter slots)
540: and cse'd or loop-moved constant memory addresses.
541:
542: Record constant equivalents in reg_equiv_constant
543: so they will be substituted by find_reloads.
544: Record memory equivalents in reg_mem_equiv so they can
545: be substituted eventually by altering the REG-rtx's. */
546:
547: reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
548: bzero (reg_equiv_constant, max_regno * sizeof (rtx));
549: reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
550: bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx));
551: reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
552: bzero (reg_equiv_mem, max_regno * sizeof (rtx));
553: reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
554: bzero (reg_equiv_init, max_regno * sizeof (rtx));
555: reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
556: bzero (reg_equiv_address, max_regno * sizeof (rtx));
557: reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
558: bzero (reg_max_ref_width, max_regno * sizeof (int));
559:
560: /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
561: Also find all paradoxical subregs
562: and find largest such for each pseudo. */
563:
564: for (insn = first; insn; insn = NEXT_INSN (insn))
565: {
566: rtx set = single_set (insn);
567:
568: if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
569: {
570: rtx note = find_reg_note (insn, REG_EQUIV, 0);
571: if (note
572: #ifdef LEGITIMATE_PIC_OPERAND_P
573: && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
574: || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
575: #endif
576: )
577: {
578: rtx x = XEXP (note, 0);
579: i = REGNO (SET_DEST (set));
580: if (i > LAST_VIRTUAL_REGISTER)
581: {
582: if (GET_CODE (x) == MEM)
583: reg_equiv_memory_loc[i] = x;
584: else if (CONSTANT_P (x))
585: {
586: if (LEGITIMATE_CONSTANT_P (x))
587: reg_equiv_constant[i] = x;
588: else
589: reg_equiv_memory_loc[i]
590: = force_const_mem (GET_MODE (SET_DEST (set)), x);
591: }
592: else
593: continue;
594:
595: /* If this register is being made equivalent to a MEM
596: and the MEM is not SET_SRC, the equivalencing insn
597: is one with the MEM as a SET_DEST and it occurs later.
598: So don't mark this insn now. */
599: if (GET_CODE (x) != MEM
600: || rtx_equal_p (SET_SRC (set), x))
601: reg_equiv_init[i] = insn;
602: }
603: }
604: }
605:
606: /* If this insn is setting a MEM from a register equivalent to it,
607: this is the equivalencing insn. */
608: else if (set && GET_CODE (SET_DEST (set)) == MEM
609: && GET_CODE (SET_SRC (set)) == REG
610: && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
611: && rtx_equal_p (SET_DEST (set),
612: reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
613: reg_equiv_init[REGNO (SET_SRC (set))] = insn;
614:
615: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
616: scan_paradoxical_subregs (PATTERN (insn));
617: }
618:
619: /* Does this function require a frame pointer? */
620:
621: frame_pointer_needed = (! flag_omit_frame_pointer
622: #ifdef EXIT_IGNORE_STACK
623: /* ?? If EXIT_IGNORE_STACK is set, we will not save
624: and restore sp for alloca. So we can't eliminate
625: the frame pointer in that case. At some point,
626: we should improve this by emitting the
627: sp-adjusting insns for this case. */
628: || (current_function_calls_alloca
629: && EXIT_IGNORE_STACK)
630: #endif
631: || FRAME_POINTER_REQUIRED);
632:
633: num_eliminable = 0;
634:
635: /* Initialize the table of registers to eliminate. The way we do this
636: depends on how the eliminable registers were defined. */
637: #ifdef ELIMINABLE_REGS
638: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
639: {
640: ep->can_eliminate = ep->can_eliminate_previous
641: = (CAN_ELIMINATE (ep->from, ep->to)
642: && (ep->from != FRAME_POINTER_REGNUM || ! frame_pointer_needed));
643: }
644: #else
645: reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
646: = ! frame_pointer_needed;
647: #endif
648:
649: /* Count the number of eliminable registers and build the FROM and TO
650: REG rtx's. Note that code in gen_rtx will cause, e.g.,
651: gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
652: We depend on this. */
653: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
654: {
655: num_eliminable += ep->can_eliminate;
656: ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
657: ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
658: }
659:
660: num_labels = max_label_num () - get_first_label_num ();
661:
662: /* Allocate the tables used to store offset information at labels. */
663: offsets_known_at = (char *) alloca (num_labels);
664: offsets_at
665: = (int (*)[NUM_ELIMINABLE_REGS])
666: alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
667:
668: offsets_known_at -= get_first_label_num ();
669: offsets_at -= get_first_label_num ();
670:
671: /* Alter each pseudo-reg rtx to contain its hard reg number.
672: Assign stack slots to the pseudos that lack hard regs or equivalents.
673: Do not touch virtual registers. */
674:
675: for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
676: alter_reg (i, -1);
677:
678: /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
679: because the stack size may be a part of the offset computation for
680: register elimination. */
681: assign_stack_local (BLKmode, 0, 0);
682:
683: /* If we have some registers we think can be eliminated, scan all insns to
684: see if there is an insn that sets one of these registers to something
685: other than itself plus a constant. If so, the register cannot be
686: eliminated. Doing this scan here eliminates an extra pass through the
687: main reload loop in the most common case where register elimination
688: cannot be done. */
689: for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
690: if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
691: || GET_CODE (insn) == CALL_INSN)
692: note_stores (PATTERN (insn), mark_not_eliminable);
693:
694: #ifndef REGISTER_CONSTRAINTS
695: /* If all the pseudo regs have hard regs,
696: except for those that are never referenced,
697: we know that no reloads are needed. */
698: /* But that is not true if there are register constraints, since
699: in that case some pseudos might be in the wrong kind of hard reg. */
700:
701: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
702: if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
703: break;
704:
1.1.1.2 root 705: if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
1.1 root 706: return;
707: #endif
708:
709: /* Compute the order of preference for hard registers to spill.
710: Store them by decreasing preference in potential_reload_regs. */
711:
712: order_regs_for_reload ();
713:
714: /* So far, no hard regs have been spilled. */
715: n_spills = 0;
716: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
717: spill_reg_order[i] = -1;
718:
719: /* On most machines, we can't use any register explicitly used in the
720: rtl as a spill register. But on some, we have to. Those will have
721: taken care to keep the life of hard regs as short as possible. */
722:
723: #ifdef SMALL_REGISTER_CLASSES
724: CLEAR_HARD_REG_SET (forbidden_regs);
725: #else
726: COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
727: #endif
728:
729: /* Spill any hard regs that we know we can't eliminate. */
730: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
731: if (! ep->can_eliminate)
732: {
733: spill_hard_reg (ep->from, global, dumpfile, 1);
734: regs_ever_live[ep->from] = 1;
735: }
736:
737: if (global)
738: for (i = 0; i < N_REG_CLASSES; i++)
739: {
740: basic_block_needs[i] = (char *)alloca (n_basic_blocks);
741: bzero (basic_block_needs[i], n_basic_blocks);
742: }
743:
744: /* This loop scans the entire function each go-round
745: and repeats until one repetition spills no additional hard regs. */
746:
1.1.1.2 root 747: /* This flag is set when a pseudo reg is spilled,
1.1 root 748: to require another pass. Note that getting an additional reload
749: reg does not necessarily imply any pseudo reg was spilled;
750: sometimes we find a reload reg that no pseudo reg was allocated in. */
751: something_changed = 1;
752: /* This flag is set if there are any insns that require reloading. */
753: something_needs_reloads = 0;
754: /* This flag is set if there are any insns that require register
755: eliminations. */
756: something_needs_elimination = 0;
757: while (something_changed)
758: {
759: rtx after_call = 0;
760:
761: /* For each class, number of reload regs needed in that class.
762: This is the maximum over all insns of the needs in that class
763: of the individual insn. */
764: int max_needs[N_REG_CLASSES];
765: /* For each class, size of group of consecutive regs
766: that is needed for the reloads of this class. */
767: int group_size[N_REG_CLASSES];
768: /* For each class, max number of consecutive groups needed.
769: (Each group contains group_size[CLASS] consecutive registers.) */
770: int max_groups[N_REG_CLASSES];
771: /* For each class, max number needed of regs that don't belong
772: to any of the groups. */
773: int max_nongroups[N_REG_CLASSES];
774: /* For each class, the machine mode which requires consecutive
775: groups of regs of that class.
776: If two different modes ever require groups of one class,
777: they must be the same size and equally restrictive for that class,
778: otherwise we can't handle the complexity. */
779: enum machine_mode group_mode[N_REG_CLASSES];
780: rtx x;
781:
782: something_changed = 0;
783: bzero (max_needs, sizeof max_needs);
784: bzero (max_groups, sizeof max_groups);
785: bzero (max_nongroups, sizeof max_nongroups);
786: bzero (group_size, sizeof group_size);
787: for (i = 0; i < N_REG_CLASSES; i++)
788: group_mode[i] = VOIDmode;
789:
790: /* Keep track of which basic blocks are needing the reloads. */
791: this_block = 0;
792:
793: /* Remember whether any element of basic_block_needs
794: changes from 0 to 1 in this pass. */
795: new_basic_block_needs = 0;
796:
797: /* Reset all offsets on eliminable registers to their initial values. */
798: #ifdef ELIMINABLE_REGS
799: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
800: {
801: INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
802: ep->previous_offset = ep->offset
803: = ep->max_offset = ep->initial_offset;
804: }
805: #else
806: #ifdef INITIAL_FRAME_POINTER_OFFSET
807: INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
808: #else
809: if (!FRAME_POINTER_REQUIRED)
810: abort ();
811: reg_eliminate[0].initial_offset = 0;
812: #endif
813: reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
814: = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
815: #endif
816:
817: num_not_at_initial_offset = 0;
818:
819: bzero (&offsets_known_at[get_first_label_num ()], num_labels);
820:
821: /* Set a known offset for each forced label to be at the initial offset
822: of each elimination. We do this because we assume that all
823: computed jumps occur from a location where each elimination is
824: at its initial offset. */
825:
826: for (x = forced_labels; x; x = XEXP (x, 1))
827: if (XEXP (x, 0))
828: set_label_offsets (XEXP (x, 0), 0, 1);
829:
830: /* For each pseudo register that has an equivalent location defined,
831: try to eliminate any eliminable registers (such as the frame pointer)
832: assuming initial offsets for the replacement register, which
833: is the normal case.
834:
835: If the resulting location is directly addressable, substitute
836: the MEM we just got directly for the old REG.
837:
838: If it is not addressable but is a constant or the sum of a hard reg
839: and constant, it is probably not addressable because the constant is
840: out of range, in that case record the address; we will generate
841: hairy code to compute the address in a register each time it is
842: needed.
843:
844: If the location is not addressable, but does not have one of the
845: above forms, assign a stack slot. We have to do this to avoid the
846: potential of producing lots of reloads if, e.g., a location involves
847: a pseudo that didn't get a hard register and has an equivalent memory
848: location that also involves a pseudo that didn't get a hard register.
849:
850: Perhaps at some point we will improve reload_when_needed handling
851: so this problem goes away. But that's very hairy. */
852:
853: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
854: if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
855: {
856: rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, 0);
857:
858: if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
859: XEXP (x, 0)))
860: reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
861: else if (CONSTANT_P (XEXP (x, 0))
862: || (GET_CODE (XEXP (x, 0)) == PLUS
863: && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
864: && (REGNO (XEXP (XEXP (x, 0), 0))
865: < FIRST_PSEUDO_REGISTER)
866: && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
867: reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
868: else
869: {
870: /* Make a new stack slot. Then indicate that something
871: changed so we go back and recompute offsets for
872: eliminable registers because the allocation of memory
873: below might change some offset. reg_equiv_{mem,address}
874: will be set up for this pseudo on the next pass around
875: the loop. */
876: reg_equiv_memory_loc[i] = 0;
877: reg_equiv_init[i] = 0;
878: alter_reg (i, -1);
879: something_changed = 1;
880: }
881: }
882:
1.1.1.2 root 883: /* If we allocated another pseudo to the stack, redo elimination
1.1 root 884: bookkeeping. */
885: if (something_changed)
886: continue;
887:
888: /* If caller-saves needs a group, initialize the group to include
889: the size and mode required for caller-saves. */
890:
891: if (caller_save_group_size > 1)
892: {
893: group_mode[(int) caller_save_spill_class] = Pmode;
894: group_size[(int) caller_save_spill_class] = caller_save_group_size;
895: }
896:
897: /* Compute the most additional registers needed by any instruction.
898: Collect information separately for each class of regs. */
899:
900: for (insn = first; insn; insn = NEXT_INSN (insn))
901: {
902: if (global && this_block + 1 < n_basic_blocks
903: && insn == basic_block_head[this_block+1])
904: ++this_block;
905:
906: /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
907: might include REG_LABEL), we need to see what effects this
908: has on the known offsets at labels. */
909:
910: if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
911: || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
912: && REG_NOTES (insn) != 0))
913: set_label_offsets (insn, insn, 0);
914:
915: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
916: {
917: /* Nonzero means don't use a reload reg that overlaps
918: the place where a function value can be returned. */
919: rtx avoid_return_reg = 0;
920:
921: rtx old_body = PATTERN (insn);
922: int old_code = INSN_CODE (insn);
923: rtx old_notes = REG_NOTES (insn);
924: int did_elimination = 0;
925:
926: /* Initially, count RELOAD_OTHER reloads.
927: Later, merge in the other kinds. */
928: int insn_needs[N_REG_CLASSES];
929: int insn_groups[N_REG_CLASSES];
930: int insn_total_groups = 0;
931:
932: /* Count RELOAD_FOR_INPUT_RELOAD_ADDRESS reloads. */
933: int insn_needs_for_inputs[N_REG_CLASSES];
934: int insn_groups_for_inputs[N_REG_CLASSES];
935: int insn_total_groups_for_inputs = 0;
936:
937: /* Count RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reloads. */
938: int insn_needs_for_outputs[N_REG_CLASSES];
939: int insn_groups_for_outputs[N_REG_CLASSES];
940: int insn_total_groups_for_outputs = 0;
941:
942: /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */
943: int insn_needs_for_operands[N_REG_CLASSES];
944: int insn_groups_for_operands[N_REG_CLASSES];
945: int insn_total_groups_for_operands = 0;
946:
947: #if 0 /* This wouldn't work nowadays, since optimize_bit_field
948: looks for non-strict memory addresses. */
949: /* Optimization: a bit-field instruction whose field
950: happens to be a byte or halfword in memory
951: can be changed to a move instruction. */
952:
953: if (GET_CODE (PATTERN (insn)) == SET)
954: {
955: rtx dest = SET_DEST (PATTERN (insn));
956: rtx src = SET_SRC (PATTERN (insn));
957:
958: if (GET_CODE (dest) == ZERO_EXTRACT
959: || GET_CODE (dest) == SIGN_EXTRACT)
960: optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
961: if (GET_CODE (src) == ZERO_EXTRACT
962: || GET_CODE (src) == SIGN_EXTRACT)
963: optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
964: }
965: #endif
966:
967: /* If needed, eliminate any eliminable registers. */
968: if (num_eliminable)
969: did_elimination = eliminate_regs_in_insn (insn, 0);
970:
971: #ifdef SMALL_REGISTER_CLASSES
972: /* Set avoid_return_reg if this is an insn
973: that might use the value of a function call. */
974: if (GET_CODE (insn) == CALL_INSN)
975: {
976: if (GET_CODE (PATTERN (insn)) == SET)
977: after_call = SET_DEST (PATTERN (insn));
978: else if (GET_CODE (PATTERN (insn)) == PARALLEL
979: && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
980: after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
981: else
982: after_call = 0;
983: }
984: else if (after_call != 0
985: && !(GET_CODE (PATTERN (insn)) == SET
986: && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
987: {
988: if (reg_mentioned_p (after_call, PATTERN (insn)))
989: avoid_return_reg = after_call;
990: after_call = 0;
991: }
992: #endif /* SMALL_REGISTER_CLASSES */
993:
994: /* Analyze the instruction. */
995: find_reloads (insn, 0, spill_indirect_levels, global,
996: spill_reg_order);
997:
998: /* Remember for later shortcuts which insns had any reloads or
999: register eliminations.
1000:
1001: One might think that it would be worthwhile to mark insns
1002: that need register replacements but not reloads, but this is
1003: not safe because find_reloads may do some manipulation of
1004: the insn (such as swapping commutative operands), which would
1005: be lost when we restore the old pattern after register
1006: replacement. So the actions of find_reloads must be redone in
1007: subsequent passes or in reload_as_needed.
1008:
1009: However, it is safe to mark insns that need reloads
1010: but not register replacement. */
1011:
1012: PUT_MODE (insn, (did_elimination ? QImode
1013: : n_reloads ? HImode
1014: : VOIDmode));
1015:
1016: /* Discard any register replacements done. */
1017: if (did_elimination)
1018: {
1019: obstack_free (&reload_obstack, reload_firstobj);
1020: PATTERN (insn) = old_body;
1021: INSN_CODE (insn) = old_code;
1022: REG_NOTES (insn) = old_notes;
1023: something_needs_elimination = 1;
1024: }
1025:
1026: /* If this insn has no reloads, we need not do anything except
1027: in the case of a CALL_INSN when we have caller-saves and
1028: caller-save needs reloads. */
1029:
1030: if (n_reloads == 0
1031: && ! (GET_CODE (insn) == CALL_INSN
1032: && caller_save_spill_class != NO_REGS))
1033: continue;
1034:
1035: something_needs_reloads = 1;
1036:
1037: for (i = 0; i < N_REG_CLASSES; i++)
1038: {
1039: insn_needs[i] = 0, insn_groups[i] = 0;
1040: insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0;
1041: insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0;
1042: insn_needs_for_operands[i] = 0, insn_groups_for_operands[i] = 0;
1043: }
1044:
1045: /* Count each reload once in every class
1046: containing the reload's own class. */
1047:
1048: for (i = 0; i < n_reloads; i++)
1049: {
1050: register enum reg_class *p;
1.1.1.3 ! root 1051: enum reg_class class = reload_reg_class[i];
1.1 root 1052: int size;
1053: enum machine_mode mode;
1054: int *this_groups;
1055: int *this_needs;
1056: int *this_total_groups;
1057:
1058: /* Don't count the dummy reloads, for which one of the
1059: regs mentioned in the insn can be used for reloading.
1060: Don't count optional reloads.
1061: Don't count reloads that got combined with others. */
1062: if (reload_reg_rtx[i] != 0
1063: || reload_optional[i] != 0
1064: || (reload_out[i] == 0 && reload_in[i] == 0
1065: && ! reload_secondary_p[i]))
1066: continue;
1067:
1.1.1.3 ! root 1068: /* Show that a reload register of this class is needed
! 1069: in this basic block. We do not use insn_needs and
! 1070: insn_groups because they are overly conservative for
! 1071: this purpose. */
! 1072: if (global && ! basic_block_needs[(int) class][this_block])
! 1073: {
! 1074: basic_block_needs[(int) class][this_block] = 1;
! 1075: new_basic_block_needs = 1;
! 1076: }
! 1077:
1.1 root 1078: /* Decide which time-of-use to count this reload for. */
1079: switch (reload_when_needed[i])
1080: {
1081: case RELOAD_OTHER:
1082: case RELOAD_FOR_OUTPUT:
1083: case RELOAD_FOR_INPUT:
1084: this_needs = insn_needs;
1085: this_groups = insn_groups;
1086: this_total_groups = &insn_total_groups;
1087: break;
1088:
1089: case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
1090: this_needs = insn_needs_for_inputs;
1091: this_groups = insn_groups_for_inputs;
1092: this_total_groups = &insn_total_groups_for_inputs;
1093: break;
1094:
1095: case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
1096: this_needs = insn_needs_for_outputs;
1097: this_groups = insn_groups_for_outputs;
1098: this_total_groups = &insn_total_groups_for_outputs;
1099: break;
1100:
1101: case RELOAD_FOR_OPERAND_ADDRESS:
1102: this_needs = insn_needs_for_operands;
1103: this_groups = insn_groups_for_operands;
1104: this_total_groups = &insn_total_groups_for_operands;
1105: break;
1106: }
1107:
1108: mode = reload_inmode[i];
1109: if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1110: mode = reload_outmode[i];
1.1.1.3 ! root 1111: size = CLASS_MAX_NREGS (class, mode);
1.1 root 1112: if (size > 1)
1113: {
1114: enum machine_mode other_mode, allocate_mode;
1115:
1116: /* Count number of groups needed separately from
1117: number of individual regs needed. */
1.1.1.3 ! root 1118: this_groups[(int) class]++;
! 1119: p = reg_class_superclasses[(int) class];
1.1 root 1120: while (*p != LIM_REG_CLASSES)
1121: this_groups[(int) *p++]++;
1122: (*this_total_groups)++;
1123:
1124: /* Record size and mode of a group of this class. */
1125: /* If more than one size group is needed,
1126: make all groups the largest needed size. */
1.1.1.3 ! root 1127: if (group_size[(int) class] < size)
1.1 root 1128: {
1.1.1.3 ! root 1129: other_mode = group_mode[(int) class];
1.1 root 1130: allocate_mode = mode;
1131:
1.1.1.3 ! root 1132: group_size[(int) class] = size;
! 1133: group_mode[(int) class] = mode;
1.1 root 1134: }
1135: else
1136: {
1137: other_mode = mode;
1.1.1.3 ! root 1138: allocate_mode = group_mode[(int) class];
1.1 root 1139: }
1140:
1141: /* Crash if two dissimilar machine modes both need
1142: groups of consecutive regs of the same class. */
1143:
1144: if (other_mode != VOIDmode
1145: && other_mode != allocate_mode
1146: && ! modes_equiv_for_class_p (allocate_mode,
1147: other_mode,
1.1.1.3 ! root 1148: class))
1.1 root 1149: abort ();
1150: }
1151: else if (size == 1)
1152: {
1.1.1.3 ! root 1153: this_needs[(int) class] += 1;
! 1154: p = reg_class_superclasses[(int) class];
1.1 root 1155: while (*p != LIM_REG_CLASSES)
1156: this_needs[(int) *p++] += 1;
1157: }
1158: else
1159: abort ();
1160: }
1161:
1162: /* All reloads have been counted for this insn;
1163: now merge the various times of use.
1164: This sets insn_needs, etc., to the maximum total number
1165: of registers needed at any point in this insn. */
1166:
1167: for (i = 0; i < N_REG_CLASSES; i++)
1168: {
1169: int this_max;
1170: this_max = insn_needs_for_inputs[i];
1171: if (insn_needs_for_outputs[i] > this_max)
1172: this_max = insn_needs_for_outputs[i];
1173: if (insn_needs_for_operands[i] > this_max)
1174: this_max = insn_needs_for_operands[i];
1175: insn_needs[i] += this_max;
1176: this_max = insn_groups_for_inputs[i];
1177: if (insn_groups_for_outputs[i] > this_max)
1178: this_max = insn_groups_for_outputs[i];
1179: if (insn_groups_for_operands[i] > this_max)
1180: this_max = insn_groups_for_operands[i];
1181: insn_groups[i] += this_max;
1182: }
1183:
1184: insn_total_groups += MAX (insn_total_groups_for_inputs,
1185: MAX (insn_total_groups_for_outputs,
1186: insn_total_groups_for_operands));
1187:
1188: /* If this is a CALL_INSN and caller-saves will need
1189: a spill register, act as if the spill register is
1190: needed for this insn. However, the spill register
1191: can be used by any reload of this insn, so we only
1192: need do something if no need for that class has
1193: been recorded.
1194:
1195: The assumption that every CALL_INSN will trigger a
1196: caller-save is highly conservative, however, the number
1197: of cases where caller-saves will need a spill register but
1198: a block containing a CALL_INSN won't need a spill register
1199: of that class should be quite rare.
1200:
1201: If a group is needed, the size and mode of the group will
1.1.1.2 root 1202: have been set up at the beginning of this loop. */
1.1 root 1203:
1204: if (GET_CODE (insn) == CALL_INSN
1205: && caller_save_spill_class != NO_REGS)
1206: {
1207: int *caller_save_needs
1208: = (caller_save_group_size > 1 ? insn_groups : insn_needs);
1209:
1210: if (caller_save_needs[(int) caller_save_spill_class] == 0)
1211: {
1212: register enum reg_class *p
1213: = reg_class_superclasses[(int) caller_save_spill_class];
1214:
1215: caller_save_needs[(int) caller_save_spill_class]++;
1216:
1217: while (*p != LIM_REG_CLASSES)
1218: caller_save_needs[(int) *p++] += 1;
1219: }
1220:
1221: if (caller_save_group_size > 1)
1222: insn_total_groups = MAX (insn_total_groups, 1);
1223:
1224:
1.1.1.3 ! root 1225: /* Show that this basic block will need a register of
! 1226: this class. */
! 1227:
! 1228: if (global
! 1229: && ! (basic_block_needs[(int) caller_save_spill_class]
! 1230: [this_block]))
! 1231: {
! 1232: basic_block_needs[(int) caller_save_spill_class]
! 1233: [this_block] = 1;
! 1234: new_basic_block_needs = 1;
! 1235: }
! 1236: }
1.1 root 1237:
1238: #ifdef SMALL_REGISTER_CLASSES
1239: /* If this insn stores the value of a function call,
1240: and that value is in a register that has been spilled,
1241: and if the insn needs a reload in a class
1242: that might use that register as the reload register,
1243: then add add an extra need in that class.
1244: This makes sure we have a register available that does
1245: not overlap the return value. */
1246: if (avoid_return_reg)
1247: {
1248: int regno = REGNO (avoid_return_reg);
1249: int nregs
1250: = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1251: int r;
1252: int inc_groups = 0;
1253: for (r = regno; r < regno + nregs; r++)
1254: if (spill_reg_order[r] >= 0)
1255: for (i = 0; i < N_REG_CLASSES; i++)
1256: if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1257: {
1258: if (insn_needs[i] > 0)
1259: insn_needs[i]++;
1260: if (insn_groups[i] > 0
1261: && nregs > 1)
1262: inc_groups = 1;
1263: }
1264: if (inc_groups)
1265: insn_groups[i]++;
1266: }
1267: #endif /* SMALL_REGISTER_CLASSES */
1268:
1269: /* For each class, collect maximum need of any insn. */
1270:
1271: for (i = 0; i < N_REG_CLASSES; i++)
1272: {
1273: if (max_needs[i] < insn_needs[i])
1274: max_needs[i] = insn_needs[i];
1275: if (max_groups[i] < insn_groups[i])
1276: max_groups[i] = insn_groups[i];
1277: if (insn_total_groups > 0)
1278: if (max_nongroups[i] < insn_needs[i])
1279: max_nongroups[i] = insn_needs[i];
1280: }
1281: }
1282: /* Note that there is a continue statement above. */
1283: }
1284:
1285: /* If we have caller-saves, set up the save areas and see if caller-save
1286: will need a spill register. */
1287:
1288: if (caller_save_needed
1289: && ! setup_save_areas (&something_changed)
1290: && caller_save_spill_class == NO_REGS)
1291: {
1292: /* The class we will need depends on whether the machine
1293: supports the sum of two registers for an address; see
1294: find_address_reloads for details. */
1295:
1296: caller_save_spill_class
1297: = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1298: caller_save_group_size
1299: = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1300: something_changed = 1;
1301: }
1302:
1303: /* Now deduct from the needs for the registers already
1304: available (already spilled). */
1305:
1306: CLEAR_HARD_REG_SET (counted_for_groups);
1307: CLEAR_HARD_REG_SET (counted_for_nongroups);
1308:
1309: /* First find all regs alone in their class
1310: and count them (if desired) for non-groups.
1311: We would be screwed if a group took the only reg in a class
1312: for which a non-group reload is needed.
1313: (Note there is still a bug; if a class has 2 regs,
1314: both could be stolen by groups and we would lose the same way.
1315: With luck, no machine will need a nongroup in a 2-reg class.) */
1316:
1317: for (i = 0; i < n_spills; i++)
1318: {
1319: register enum reg_class *p;
1320: class = (int) REGNO_REG_CLASS (spill_regs[i]);
1321:
1322: if (reg_class_size[class] == 1 && max_nongroups[class] > 0)
1323: {
1324: max_needs[class]--;
1325: p = reg_class_superclasses[class];
1326: while (*p != LIM_REG_CLASSES)
1327: max_needs[(int) *p++]--;
1328:
1329: SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1330: max_nongroups[class]--;
1331: p = reg_class_superclasses[class];
1332: while (*p != LIM_REG_CLASSES)
1333: {
1334: if (max_nongroups[(int) *p] > 0)
1335: SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1336: max_nongroups[(int) *p++]--;
1337: }
1338: }
1339: }
1340:
1341: /* Now find all consecutive groups of spilled registers
1342: and mark each group off against the need for such groups.
1343: But don't count them against ordinary need, yet. */
1344:
1345: count_possible_groups (group_size, group_mode, max_groups);
1346:
1347: /* Now count all spill regs against the individual need,
1348: This includes those counted above for groups,
1349: but not those previously counted for nongroups.
1350:
1351: Those that weren't counted_for_groups can also count against
1352: the not-in-group need. */
1353:
1354: for (i = 0; i < n_spills; i++)
1355: {
1356: register enum reg_class *p;
1357: class = (int) REGNO_REG_CLASS (spill_regs[i]);
1358:
1359: /* Those counted at the beginning shouldn't be counted twice. */
1360: if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
1361: {
1362: max_needs[class]--;
1363: p = reg_class_superclasses[class];
1364: while (*p != LIM_REG_CLASSES)
1365: max_needs[(int) *p++]--;
1366:
1367: if (! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i]))
1368: {
1369: if (max_nongroups[class] > 0)
1370: SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1371: max_nongroups[class]--;
1372: p = reg_class_superclasses[class];
1373: while (*p != LIM_REG_CLASSES)
1374: {
1375: if (max_nongroups[(int) *p] > 0)
1376: SET_HARD_REG_BIT (counted_for_nongroups,
1377: spill_regs[i]);
1378: max_nongroups[(int) *p++]--;
1379: }
1380: }
1381: }
1382: }
1383:
1.1.1.2 root 1384: /* See if anything that happened changes which eliminations are valid.
1385: For example, on the Sparc, whether or not the frame pointer can
1386: be eliminated can depend on what registers have been used. We need
1387: not check some conditions again (such as flag_omit_frame_pointer)
1388: since they can't have changed. */
1389:
1390: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1391: if ((ep->from == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1392: #ifdef ELIMINABLE_REGS
1393: || ! CAN_ELIMINATE (ep->from, ep->to)
1394: #endif
1395: )
1396: ep->can_eliminate = 0;
1397:
1.1 root 1398: /* Look for the case where we have discovered that we can't replace
1399: register A with register B and that means that we will now be
1400: trying to replace register A with register C. This means we can
1401: no longer replace register C with register B and we need to disable
1402: such an elimination, if it exists. This occurs often with A == ap,
1403: B == sp, and C == fp. */
1404:
1405: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1406: {
1407: struct elim_table *op;
1408: register int new_to = -1;
1409:
1410: if (! ep->can_eliminate && ep->can_eliminate_previous)
1411: {
1412: /* Find the current elimination for ep->from, if there is a
1413: new one. */
1414: for (op = reg_eliminate;
1415: op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1416: if (op->from == ep->from && op->can_eliminate)
1417: {
1418: new_to = op->to;
1419: break;
1420: }
1421:
1422: /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1423: disable it. */
1424: for (op = reg_eliminate;
1425: op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1426: if (op->from == new_to && op->to == ep->to)
1427: op->can_eliminate = 0;
1428: }
1429: }
1430:
1431: /* See if any registers that we thought we could eliminate the previous
1432: time are no longer eliminable. If so, something has changed and we
1433: must spill the register. Also, recompute the number of eliminable
1434: registers and see if the frame pointer is needed; it is if there is
1435: no elimination of the frame pointer that we can perform. */
1436:
1437: frame_pointer_needed = 1;
1438: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1439: {
1440: if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM)
1441: frame_pointer_needed = 0;
1442:
1443: if (! ep->can_eliminate && ep->can_eliminate_previous)
1444: {
1445: ep->can_eliminate_previous = 0;
1446: spill_hard_reg (ep->from, global, dumpfile, 1);
1447: regs_ever_live[ep->from] = 1;
1448: something_changed = 1;
1449: num_eliminable--;
1450: }
1451: }
1452:
1453: /* If all needs are met, we win. */
1454:
1455: for (i = 0; i < N_REG_CLASSES; i++)
1456: if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1457: break;
1458: if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1459: break;
1460:
1461: /* Not all needs are met; must spill more hard regs. */
1462:
1463: /* If any element of basic_block_needs changed from 0 to 1,
1464: re-spill all the regs already spilled. This may spill
1465: additional pseudos that didn't spill before. */
1466:
1467: if (new_basic_block_needs)
1468: for (i = 0; i < n_spills; i++)
1469: something_changed
1470: |= spill_hard_reg (spill_regs[i], global, dumpfile, 0);
1471:
1472: /* Now find more reload regs to satisfy the remaining need
1473: Do it by ascending class number, since otherwise a reg
1474: might be spilled for a big class and might fail to count
1475: for a smaller class even though it belongs to that class.
1476:
1477: Count spilled regs in `spills', and add entries to
1478: `spill_regs' and `spill_reg_order'.
1479:
1480: ??? Note there is a problem here.
1481: When there is a need for a group in a high-numbered class,
1482: and also need for non-group regs that come from a lower class,
1483: the non-group regs are chosen first. If there aren't many regs,
1484: they might leave no room for a group.
1485:
1486: This was happening on the 386. To fix it, we added the code
1487: that calls possible_group_p, so that the lower class won't
1488: break up the last possible group.
1489:
1490: Really fixing the problem would require changes above
1491: in counting the regs already spilled, and in choose_reload_regs.
1492: It might be hard to avoid introducing bugs there. */
1493:
1494: for (class = 0; class < N_REG_CLASSES; class++)
1495: {
1496: /* First get the groups of registers.
1497: If we got single registers first, we might fragment
1498: possible groups. */
1499: while (max_groups[class] > 0)
1500: {
1501: /* If any single spilled regs happen to form groups,
1502: count them now. Maybe we don't really need
1503: to spill another group. */
1504: count_possible_groups (group_size, group_mode, max_groups);
1505:
1506: /* Groups of size 2 (the only groups used on most machines)
1507: are treated specially. */
1508: if (group_size[class] == 2)
1509: {
1510: /* First, look for a register that will complete a group. */
1511: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1512: {
1513: int j = potential_reload_regs[i];
1514: int other;
1515: if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1516: &&
1517: ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1518: && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1519: && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1520: && HARD_REGNO_MODE_OK (other, group_mode[class])
1521: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1522: other)
1523: /* We don't want one part of another group.
1524: We could get "two groups" that overlap! */
1525: && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1526: ||
1527: (j < FIRST_PSEUDO_REGISTER - 1
1528: && (other = j + 1, spill_reg_order[other] >= 0)
1529: && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1530: && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1531: && HARD_REGNO_MODE_OK (j, group_mode[class])
1532: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1533: other)
1534: && ! TEST_HARD_REG_BIT (counted_for_groups,
1535: other))))
1536: {
1537: register enum reg_class *p;
1538:
1539: /* We have found one that will complete a group,
1540: so count off one group as provided. */
1541: max_groups[class]--;
1542: p = reg_class_superclasses[class];
1543: while (*p != LIM_REG_CLASSES)
1544: max_groups[(int) *p++]--;
1545:
1546: /* Indicate both these regs are part of a group. */
1547: SET_HARD_REG_BIT (counted_for_groups, j);
1548: SET_HARD_REG_BIT (counted_for_groups, other);
1549: break;
1550: }
1551: }
1552: /* We can't complete a group, so start one. */
1553: if (i == FIRST_PSEUDO_REGISTER)
1554: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1555: {
1556: int j = potential_reload_regs[i];
1557: if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1558: && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1559: && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1560: && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1561: && HARD_REGNO_MODE_OK (j, group_mode[class])
1562: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1563: j + 1))
1564: break;
1565: }
1566:
1567: /* I should be the index in potential_reload_regs
1568: of the new reload reg we have found. */
1569:
1570: something_changed
1571: |= new_spill_reg (i, class, max_needs, 0,
1572: global, dumpfile);
1573: }
1574: else
1575: {
1576: /* For groups of more than 2 registers,
1577: look for a sufficient sequence of unspilled registers,
1578: and spill them all at once. */
1579: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1580: {
1581: int j = potential_reload_regs[i];
1582: int k;
1583: if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1584: && HARD_REGNO_MODE_OK (j, group_mode[class]))
1585: {
1586: /* Check each reg in the sequence. */
1587: for (k = 0; k < group_size[class]; k++)
1588: if (! (spill_reg_order[j + k] < 0
1589: && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1590: && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1591: break;
1592: /* We got a full sequence, so spill them all. */
1593: if (k == group_size[class])
1594: {
1595: register enum reg_class *p;
1596: for (k = 0; k < group_size[class]; k++)
1597: {
1598: int idx;
1599: SET_HARD_REG_BIT (counted_for_groups, j + k);
1600: for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1601: if (potential_reload_regs[idx] == j + k)
1602: break;
1603: something_changed
1604: |= new_spill_reg (idx, class, max_needs, 0,
1605: global, dumpfile);
1606: }
1607:
1608: /* We have found one that will complete a group,
1609: so count off one group as provided. */
1610: max_groups[class]--;
1611: p = reg_class_superclasses[class];
1612: while (*p != LIM_REG_CLASSES)
1613: max_groups[(int) *p++]--;
1614:
1615: break;
1616: }
1617: }
1618: }
1.1.1.3 ! root 1619: /* We couldn't find any registers for this reload.
! 1620: Abort to avoid going into an infinite loop. */
! 1621: if (i == FIRST_PSEUDO_REGISTER)
! 1622: abort ();
1.1 root 1623: }
1624: }
1625:
1626: /* Now similarly satisfy all need for single registers. */
1627:
1628: while (max_needs[class] > 0 || max_nongroups[class] > 0)
1629: {
1630: /* Consider the potential reload regs that aren't
1631: yet in use as reload regs, in order of preference.
1632: Find the most preferred one that's in this class. */
1633:
1634: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1635: if (potential_reload_regs[i] >= 0
1636: && TEST_HARD_REG_BIT (reg_class_contents[class],
1637: potential_reload_regs[i])
1638: /* If this reg will not be available for groups,
1639: pick one that does not foreclose possible groups.
1640: This is a kludge, and not very general,
1641: but it should be sufficient to make the 386 work,
1642: and the problem should not occur on machines with
1643: more registers. */
1644: && (max_nongroups[class] == 0
1645: || possible_group_p (potential_reload_regs[i], max_groups)))
1646: break;
1647:
1648: /* I should be the index in potential_reload_regs
1649: of the new reload reg we have found. */
1650:
1651: something_changed
1652: |= new_spill_reg (i, class, max_needs, max_nongroups,
1653: global, dumpfile);
1654: }
1655: }
1656: }
1657:
1658: /* If global-alloc was run, notify it of any register eliminations we have
1659: done. */
1660: if (global)
1661: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1662: if (ep->can_eliminate)
1663: mark_elimination (ep->from, ep->to);
1664:
1665: /* From now on, we need to emit any moves without making new pseudos. */
1666: reload_in_progress = 1;
1667:
1668: /* Insert code to save and restore call-clobbered hard regs
1669: around calls. Tell if what mode to use so that we will process
1670: those insns in reload_as_needed if we have to. */
1671:
1672: if (caller_save_needed)
1673: save_call_clobbered_regs (num_eliminable ? QImode
1674: : caller_save_spill_class != NO_REGS ? HImode
1675: : VOIDmode);
1676:
1677: /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1678: If that insn didn't set the register (i.e., it copied the register to
1679: memory), just delete that insn instead of the equivalencing insn plus
1680: anything now dead. If we call delete_dead_insn on that insn, we may
1681: delete the insn that actually sets the register if the register die
1682: there and that is incorrect. */
1683:
1684: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1685: if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1686: && GET_CODE (reg_equiv_init[i]) != NOTE)
1687: {
1688: if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1689: delete_dead_insn (reg_equiv_init[i]);
1690: else
1691: {
1692: PUT_CODE (reg_equiv_init[i], NOTE);
1693: NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1694: NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1695: }
1696: }
1697:
1698: /* Use the reload registers where necessary
1699: by generating move instructions to move the must-be-register
1700: values into or out of the reload registers. */
1701:
1702: if (something_needs_reloads || something_needs_elimination
1703: || (caller_save_needed && num_eliminable)
1704: || caller_save_spill_class != NO_REGS)
1705: reload_as_needed (first, global);
1706:
1707: reload_in_progress = 0;
1708:
1709: /* Now eliminate all pseudo regs by modifying them into
1710: their equivalent memory references.
1711: The REG-rtx's for the pseudos are modified in place,
1712: so all insns that used to refer to them now refer to memory.
1713:
1714: For a reg that has a reg_equiv_address, all those insns
1715: were changed by reloading so that no insns refer to it any longer;
1716: but the DECL_RTL of a variable decl may refer to it,
1717: and if so this causes the debugging info to mention the variable. */
1718:
1719: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1720: {
1721: rtx addr = 0;
1.1.1.3 ! root 1722: int in_struct = 0;
1.1 root 1723: if (reg_equiv_mem[i])
1.1.1.3 ! root 1724: {
! 1725: addr = XEXP (reg_equiv_mem[i], 0);
! 1726: in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
! 1727: }
1.1 root 1728: if (reg_equiv_address[i])
1729: addr = reg_equiv_address[i];
1730: if (addr)
1731: {
1732: if (reg_renumber[i] < 0)
1733: {
1734: rtx reg = regno_reg_rtx[i];
1735: XEXP (reg, 0) = addr;
1736: REG_USERVAR_P (reg) = 0;
1.1.1.3 ! root 1737: MEM_IN_STRUCT_P (reg) = in_struct;
1.1 root 1738: PUT_CODE (reg, MEM);
1739: }
1740: else if (reg_equiv_mem[i])
1741: XEXP (reg_equiv_mem[i], 0) = addr;
1742: }
1743: }
1744:
1745: #ifdef PRESERVE_DEATH_INFO_REGNO_P
1746: /* Make a pass over all the insns and remove death notes for things that
1747: are no longer registers or no longer die in the insn (e.g., an input
1748: and output pseudo being tied). */
1749:
1750: for (insn = first; insn; insn = NEXT_INSN (insn))
1751: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1752: {
1753: rtx note, next;
1754:
1755: for (note = REG_NOTES (insn); note; note = next)
1756: {
1757: next = XEXP (note, 1);
1758: if (REG_NOTE_KIND (note) == REG_DEAD
1759: && (GET_CODE (XEXP (note, 0)) != REG
1760: || reg_set_p (XEXP (note, 0), PATTERN (insn))))
1761: remove_note (insn, note);
1762: }
1763: }
1764: #endif
1765:
1766: /* Indicate that we no longer have known memory locations or constants. */
1767: reg_equiv_constant = 0;
1768: reg_equiv_memory_loc = 0;
1769: }
1770:
1771: /* Nonzero if, after spilling reg REGNO for non-groups,
1772: it will still be possible to find a group if we still need one. */
1773:
1774: static int
1775: possible_group_p (regno, max_groups)
1776: int regno;
1777: int *max_groups;
1778: {
1779: int i;
1780: int class = (int) NO_REGS;
1781:
1782: for (i = 0; i < (int) N_REG_CLASSES; i++)
1783: if (max_groups[i] > 0)
1784: {
1785: class = i;
1786: break;
1787: }
1788:
1789: if (class == (int) NO_REGS)
1790: return 1;
1791:
1792: /* Consider each pair of consecutive registers. */
1793: for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
1794: {
1795: /* Ignore pairs that include reg REGNO. */
1796: if (i == regno || i + 1 == regno)
1797: continue;
1798:
1799: /* Ignore pairs that are outside the class that needs the group.
1800: ??? Here we fail to handle the case where two different classes
1801: independently need groups. But this never happens with our
1802: current machine descriptions. */
1803: if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
1804: && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
1805: continue;
1806:
1807: /* A pair of consecutive regs we can still spill does the trick. */
1808: if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
1809: && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1810: && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
1811: return 1;
1812:
1813: /* A pair of one already spilled and one we can spill does it
1814: provided the one already spilled is not otherwise reserved. */
1815: if (spill_reg_order[i] < 0
1816: && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1817: && spill_reg_order[i + 1] >= 0
1818: && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
1819: && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
1820: return 1;
1821: if (spill_reg_order[i + 1] < 0
1822: && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
1823: && spill_reg_order[i] >= 0
1824: && ! TEST_HARD_REG_BIT (counted_for_groups, i)
1825: && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
1826: return 1;
1827: }
1828:
1829: return 0;
1830: }
1831:
1832: /* Count any groups that can be formed from the registers recently spilled.
1833: This is done class by class, in order of ascending class number. */
1834:
1835: static void
1836: count_possible_groups (group_size, group_mode, max_groups)
1837: int *group_size, *max_groups;
1838: enum machine_mode *group_mode;
1839: {
1840: int i;
1841: /* Now find all consecutive groups of spilled registers
1842: and mark each group off against the need for such groups.
1843: But don't count them against ordinary need, yet. */
1844:
1845: for (i = 0; i < N_REG_CLASSES; i++)
1846: if (group_size[i] > 1)
1847: {
1848: char regmask[FIRST_PSEUDO_REGISTER];
1849: int j;
1850:
1851: bzero (regmask, sizeof regmask);
1852: /* Make a mask of all the regs that are spill regs in class I. */
1853: for (j = 0; j < n_spills; j++)
1854: if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j])
1855: && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j])
1856: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1857: spill_regs[j]))
1858: regmask[spill_regs[j]] = 1;
1859: /* Find each consecutive group of them. */
1860: for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++)
1861: if (regmask[j] && j + group_size[i] <= FIRST_PSEUDO_REGISTER
1862: /* Next line in case group-mode for this class
1863: demands an even-odd pair. */
1864: && HARD_REGNO_MODE_OK (j, group_mode[i]))
1865: {
1866: int k;
1867: for (k = 1; k < group_size[i]; k++)
1868: if (! regmask[j + k])
1869: break;
1870: if (k == group_size[i])
1871: {
1872: /* We found a group. Mark it off against this class's
1873: need for groups, and against each superclass too. */
1874: register enum reg_class *p;
1875: max_groups[i]--;
1876: p = reg_class_superclasses[i];
1877: while (*p != LIM_REG_CLASSES)
1878: max_groups[(int) *p++]--;
1879: /* Don't count these registers again. */
1880: for (k = 0; k < group_size[i]; k++)
1881: SET_HARD_REG_BIT (counted_for_groups, j + k);
1882: }
1.1.1.3 ! root 1883: /* Skip to the last reg in this group. When j is incremented
! 1884: above, it will then point to the first reg of the next
! 1885: possible group. */
! 1886: j += k - 1;
1.1 root 1887: }
1888: }
1889:
1890: }
1891:
1892: /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
1893: another mode that needs to be reloaded for the same register class CLASS.
1894: If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
1895: ALLOCATE_MODE will never be smaller than OTHER_MODE.
1896:
1897: This code used to also fail if any reg in CLASS allows OTHER_MODE but not
1898: ALLOCATE_MODE. This test is unnecessary, because we will never try to put
1899: something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
1900: causes unnecessary failures on machines requiring alignment of register
1901: groups when the two modes are different sizes, because the larger mode has
1902: more strict alignment rules than the smaller mode. */
1903:
1904: static int
1905: modes_equiv_for_class_p (allocate_mode, other_mode, class)
1906: enum machine_mode allocate_mode, other_mode;
1907: enum reg_class class;
1908: {
1909: register int regno;
1910: for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1911: {
1912: if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
1913: && HARD_REGNO_MODE_OK (regno, allocate_mode)
1914: && ! HARD_REGNO_MODE_OK (regno, other_mode))
1915: return 0;
1916: }
1917: return 1;
1918: }
1919:
1920: /* Add a new register to the tables of available spill-registers
1921: (as well as spilling all pseudos allocated to the register).
1922: I is the index of this register in potential_reload_regs.
1923: CLASS is the regclass whose need is being satisfied.
1924: MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
1925: so that this register can count off against them.
1926: MAX_NONGROUPS is 0 if this register is part of a group.
1927: GLOBAL and DUMPFILE are the same as the args that `reload' got. */
1928:
1929: static int
1930: new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
1931: int i;
1932: int class;
1933: int *max_needs;
1934: int *max_nongroups;
1935: int global;
1936: FILE *dumpfile;
1937: {
1938: register enum reg_class *p;
1939: int val;
1940: int regno = potential_reload_regs[i];
1941:
1942: if (i >= FIRST_PSEUDO_REGISTER)
1943: abort (); /* Caller failed to find any register. */
1944:
1945: if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
1946: fatal ("fixed or forbidden register was spilled.\n\
1947: This may be due to a compiler bug or to impossible asm statements.");
1948:
1949: /* Make reg REGNO an additional reload reg. */
1950:
1951: potential_reload_regs[i] = -1;
1952: spill_regs[n_spills] = regno;
1953: spill_reg_order[regno] = n_spills;
1954: if (dumpfile)
1955: fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
1956:
1957: /* Clear off the needs we just satisfied. */
1958:
1959: max_needs[class]--;
1960: p = reg_class_superclasses[class];
1961: while (*p != LIM_REG_CLASSES)
1962: max_needs[(int) *p++]--;
1963:
1964: if (max_nongroups && max_nongroups[class] > 0)
1965: {
1966: SET_HARD_REG_BIT (counted_for_nongroups, regno);
1967: max_nongroups[class]--;
1968: p = reg_class_superclasses[class];
1969: while (*p != LIM_REG_CLASSES)
1970: max_nongroups[(int) *p++]--;
1971: }
1972:
1973: /* Spill every pseudo reg that was allocated to this reg
1974: or to something that overlaps this reg. */
1975:
1976: val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
1977:
1978: /* If there are some registers still to eliminate and this register
1979: wasn't ever used before, additional stack space may have to be
1980: allocated to store this register. Thus, we may have changed the offset
1981: between the stack and frame pointers, so mark that something has changed.
1982: (If new pseudos were spilled, thus requiring more space, VAL would have
1983: been set non-zero by the call to spill_hard_reg above since additional
1984: reloads may be needed in that case.
1985:
1986: One might think that we need only set VAL to 1 if this is a call-used
1987: register. However, the set of registers that must be saved by the
1988: prologue is not identical to the call-used set. For example, the
1989: register used by the call insn for the return PC is a call-used register,
1990: but must be saved by the prologue. */
1991: if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
1992: val = 1;
1993:
1994: regs_ever_live[spill_regs[n_spills]] = 1;
1995: n_spills++;
1996:
1997: return val;
1998: }
1999:
2000: /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2001: data that is dead in INSN. */
2002:
2003: static void
2004: delete_dead_insn (insn)
2005: rtx insn;
2006: {
2007: rtx prev = prev_real_insn (insn);
2008: rtx prev_dest;
2009:
2010: /* If the previous insn sets a register that dies in our insn, delete it
2011: too. */
2012: if (prev && GET_CODE (PATTERN (prev)) == SET
2013: && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2014: && reg_mentioned_p (prev_dest, PATTERN (insn))
2015: && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2016: delete_dead_insn (prev);
2017:
2018: PUT_CODE (insn, NOTE);
2019: NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2020: NOTE_SOURCE_FILE (insn) = 0;
2021: }
2022:
2023: /* Modify the home of pseudo-reg I.
2024: The new home is present in reg_renumber[I].
2025:
2026: FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2027: or it may be -1, meaning there is none or it is not relevant.
2028: This is used so that all pseudos spilled from a given hard reg
2029: can share one stack slot. */
2030:
2031: static void
2032: alter_reg (i, from_reg)
2033: register int i;
2034: int from_reg;
2035: {
2036: /* When outputting an inline function, this can happen
2037: for a reg that isn't actually used. */
2038: if (regno_reg_rtx[i] == 0)
2039: return;
2040:
2041: /* If the reg got changed to a MEM at rtl-generation time,
2042: ignore it. */
2043: if (GET_CODE (regno_reg_rtx[i]) != REG)
2044: return;
2045:
2046: /* Modify the reg-rtx to contain the new hard reg
2047: number or else to contain its pseudo reg number. */
2048: REGNO (regno_reg_rtx[i])
2049: = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2050:
2051: /* If we have a pseudo that is needed but has no hard reg or equivalent,
2052: allocate a stack slot for it. */
2053:
2054: if (reg_renumber[i] < 0
2055: && reg_n_refs[i] > 0
2056: && reg_equiv_constant[i] == 0
2057: && reg_equiv_memory_loc[i] == 0)
2058: {
2059: register rtx x;
2060: int inherent_size = PSEUDO_REGNO_BYTES (i);
2061: int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2062: int adjust = 0;
2063:
2064: /* Each pseudo reg has an inherent size which comes from its own mode,
2065: and a total size which provides room for paradoxical subregs
2066: which refer to the pseudo reg in wider modes.
2067:
2068: We can use a slot already allocated if it provides both
2069: enough inherent space and enough total space.
2070: Otherwise, we allocate a new slot, making sure that it has no less
2071: inherent space, and no less total space, then the previous slot. */
2072: if (from_reg == -1)
2073: {
2074: /* No known place to spill from => no slot to reuse. */
2075: x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2076: #if BYTES_BIG_ENDIAN
2077: /* Cancel the big-endian correction done in assign_stack_local.
2078: Get the address of the beginning of the slot.
2079: This is so we can do a big-endian correction unconditionally
2080: below. */
2081: adjust = inherent_size - total_size;
2082: #endif
2083: }
2084: /* Reuse a stack slot if possible. */
2085: else if (spill_stack_slot[from_reg] != 0
2086: && spill_stack_slot_width[from_reg] >= total_size
2087: && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2088: >= inherent_size))
2089: x = spill_stack_slot[from_reg];
2090: /* Allocate a bigger slot. */
2091: else
2092: {
2093: /* Compute maximum size needed, both for inherent size
2094: and for total size. */
2095: enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2096: if (spill_stack_slot[from_reg])
2097: {
2098: if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2099: > inherent_size)
2100: mode = GET_MODE (spill_stack_slot[from_reg]);
2101: if (spill_stack_slot_width[from_reg] > total_size)
2102: total_size = spill_stack_slot_width[from_reg];
2103: }
2104: /* Make a slot with that size. */
2105: x = assign_stack_local (mode, total_size, -1);
2106: #if BYTES_BIG_ENDIAN
2107: /* Cancel the big-endian correction done in assign_stack_local.
2108: Get the address of the beginning of the slot.
2109: This is so we can do a big-endian correction unconditionally
2110: below. */
2111: adjust = GET_MODE_SIZE (mode) - total_size;
2112: #endif
2113: spill_stack_slot[from_reg] = x;
2114: spill_stack_slot_width[from_reg] = total_size;
2115: }
2116:
2117: #if BYTES_BIG_ENDIAN
2118: /* On a big endian machine, the "address" of the slot
2119: is the address of the low part that fits its inherent mode. */
2120: if (inherent_size < total_size)
2121: adjust += (total_size - inherent_size);
2122: #endif /* BYTES_BIG_ENDIAN */
2123:
2124: /* If we have any adjustment to make, or if the stack slot is the
2125: wrong mode, make a new stack slot. */
2126: if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2127: {
2128: x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2129: plus_constant (XEXP (x, 0), adjust));
2130: RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2131: }
2132:
2133: /* Save the stack slot for later. */
2134: reg_equiv_memory_loc[i] = x;
2135: }
2136: }
2137:
2138: /* Mark the slots in regs_ever_live for the hard regs
2139: used by pseudo-reg number REGNO. */
2140:
2141: void
2142: mark_home_live (regno)
2143: int regno;
2144: {
2145: register int i, lim;
2146: i = reg_renumber[regno];
2147: if (i < 0)
2148: return;
2149: lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2150: while (i < lim)
2151: regs_ever_live[i++] = 1;
2152: }
2153:
2154: /* This function handles the tracking of elimination offsets around branches.
2155:
2156: X is a piece of RTL being scanned.
2157:
2158: INSN is the insn that it came from, if any.
2159:
2160: INITIAL_P is non-zero if we are to set the offset to be the initial
2161: offset and zero if we are setting the offset of the label to be the
2162: current offset. */
2163:
2164: static void
2165: set_label_offsets (x, insn, initial_p)
2166: rtx x;
2167: rtx insn;
2168: int initial_p;
2169: {
2170: enum rtx_code code = GET_CODE (x);
2171: rtx tem;
2172: int i;
2173: struct elim_table *p;
2174:
2175: switch (code)
2176: {
2177: case LABEL_REF:
2178: x = XEXP (x, 0);
2179:
2180: /* ... fall through ... */
2181:
2182: case CODE_LABEL:
2183: /* If we know nothing about this label, set the desired offsets. Note
2184: that this sets the offset at a label to be the offset before a label
2185: if we don't know anything about the label. This is not correct for
2186: the label after a BARRIER, but is the best guess we can make. If
2187: we guessed wrong, we will suppress an elimination that might have
2188: been possible had we been able to guess correctly. */
2189:
2190: if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2191: {
2192: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2193: offsets_at[CODE_LABEL_NUMBER (x)][i]
2194: = (initial_p ? reg_eliminate[i].initial_offset
2195: : reg_eliminate[i].offset);
2196: offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2197: }
2198:
2199: /* Otherwise, if this is the definition of a label and it is
1.1.1.2 root 2200: preceded by a BARRIER, set our offsets to the known offset of
1.1 root 2201: that label. */
2202:
2203: else if (x == insn
2204: && (tem = prev_nonnote_insn (insn)) != 0
2205: && GET_CODE (tem) == BARRIER)
2206: {
2207: num_not_at_initial_offset = 0;
2208: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2209: {
2210: reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2211: = offsets_at[CODE_LABEL_NUMBER (x)][i];
1.1.1.2 root 2212: if (reg_eliminate[i].can_eliminate
2213: && (reg_eliminate[i].offset
2214: != reg_eliminate[i].initial_offset))
1.1 root 2215: num_not_at_initial_offset++;
2216: }
2217: }
2218:
2219: else
2220: /* If neither of the above cases is true, compare each offset
2221: with those previously recorded and suppress any eliminations
2222: where the offsets disagree. */
2223:
2224: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2225: if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2226: != (initial_p ? reg_eliminate[i].initial_offset
2227: : reg_eliminate[i].offset))
2228: reg_eliminate[i].can_eliminate = 0;
2229:
2230: return;
2231:
2232: case JUMP_INSN:
2233: set_label_offsets (PATTERN (insn), insn, initial_p);
2234:
2235: /* ... fall through ... */
2236:
2237: case INSN:
2238: case CALL_INSN:
2239: /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2240: and hence must have all eliminations at their initial offsets. */
2241: for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2242: if (REG_NOTE_KIND (tem) == REG_LABEL)
2243: set_label_offsets (XEXP (tem, 0), insn, 1);
2244: return;
2245:
2246: case ADDR_VEC:
2247: case ADDR_DIFF_VEC:
2248: /* Each of the labels in the address vector must be at their initial
2249: offsets. We want the first first for ADDR_VEC and the second
2250: field for ADDR_DIFF_VEC. */
2251:
2252: for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2253: set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2254: insn, initial_p);
2255: return;
2256:
2257: case SET:
2258: /* We only care about setting PC. If the source is not RETURN,
2259: IF_THEN_ELSE, or a label, disable any eliminations not at
2260: their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2261: isn't one of those possibilities. For branches to a label,
2262: call ourselves recursively.
2263:
2264: Note that this can disable elimination unnecessarily when we have
2265: a non-local goto since it will look like a non-constant jump to
2266: someplace in the current function. This isn't a significant
2267: problem since such jumps will normally be when all elimination
2268: pairs are back to their initial offsets. */
2269:
2270: if (SET_DEST (x) != pc_rtx)
2271: return;
2272:
2273: switch (GET_CODE (SET_SRC (x)))
2274: {
2275: case PC:
2276: case RETURN:
2277: return;
2278:
2279: case LABEL_REF:
2280: set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2281: return;
2282:
2283: case IF_THEN_ELSE:
2284: tem = XEXP (SET_SRC (x), 1);
2285: if (GET_CODE (tem) == LABEL_REF)
2286: set_label_offsets (XEXP (tem, 0), insn, initial_p);
2287: else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2288: break;
2289:
2290: tem = XEXP (SET_SRC (x), 2);
2291: if (GET_CODE (tem) == LABEL_REF)
2292: set_label_offsets (XEXP (tem, 0), insn, initial_p);
2293: else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2294: break;
2295: return;
2296: }
2297:
2298: /* If we reach here, all eliminations must be at their initial
2299: offset because we are doing a jump to a variable address. */
2300: for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2301: if (p->offset != p->initial_offset)
2302: p->can_eliminate = 0;
2303: }
2304: }
2305:
2306: /* Used for communication between the next two function to properly share
2307: the vector for an ASM_OPERANDS. */
2308:
2309: static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2310:
2311: /* Scan X and replace any eliminable registers (such as fp) with a
2312: replacement (such as sp), plus an offset.
2313:
2314: MEM_MODE is the mode of an enclosing MEM. We need this to know how
2315: much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2316: MEM, we are allowed to replace a sum of a register and the constant zero
2317: with the register, which we cannot do outside a MEM. In addition, we need
2318: to record the fact that a register is referenced outside a MEM.
2319:
2320: If INSN is nonzero, it is the insn containing X. If we replace a REG
2321: in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2322: CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2323: that the REG is being modified.
2324:
2325: If we see a modification to a register we know about, take the
2326: appropriate action (see case SET, below).
2327:
2328: REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2329: replacements done assuming all offsets are at their initial values. If
2330: they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2331: encounter, return the actual location so that find_reloads will do
2332: the proper thing. */
2333:
2334: rtx
2335: eliminate_regs (x, mem_mode, insn)
2336: rtx x;
2337: enum machine_mode mem_mode;
2338: rtx insn;
2339: {
2340: enum rtx_code code = GET_CODE (x);
2341: struct elim_table *ep;
2342: int regno;
2343: rtx new;
2344: int i, j;
2345: char *fmt;
2346: int copied = 0;
2347:
2348: switch (code)
2349: {
2350: case CONST_INT:
2351: case CONST_DOUBLE:
2352: case CONST:
2353: case SYMBOL_REF:
2354: case CODE_LABEL:
2355: case PC:
2356: case CC0:
2357: case ASM_INPUT:
2358: case ADDR_VEC:
2359: case ADDR_DIFF_VEC:
2360: case RETURN:
2361: return x;
2362:
2363: case REG:
2364: regno = REGNO (x);
2365:
2366: /* First handle the case where we encounter a bare register that
2367: is eliminable. Replace it with a PLUS. */
2368: if (regno < FIRST_PSEUDO_REGISTER)
2369: {
2370: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2371: ep++)
2372: if (ep->from_rtx == x && ep->can_eliminate)
2373: {
2374: if (! mem_mode)
2375: ep->ref_outside_mem = 1;
2376: return plus_constant (ep->to_rtx, ep->previous_offset);
2377: }
2378:
2379: }
2380: else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2381: && (reg_equiv_address[regno] || num_not_at_initial_offset))
2382: {
2383: /* In this case, find_reloads would attempt to either use an
2384: incorrect address (if something is not at its initial offset)
2385: or substitute an replaced address into an insn (which loses
2386: if the offset is changed by some later action). So we simply
2387: return the replaced stack slot (assuming it is changed by
2388: elimination) and ignore the fact that this is actually a
2389: reference to the pseudo. Ensure we make a copy of the
2390: address in case it is shared. */
2391: new = eliminate_regs (reg_equiv_memory_loc[regno], mem_mode, 0);
2392: if (new != reg_equiv_memory_loc[regno])
2393: return copy_rtx (new);
2394: }
2395: return x;
2396:
2397: case PLUS:
2398: /* If this is the sum of an eliminable register and a constant, rework
2399: the sum. */
2400: if (GET_CODE (XEXP (x, 0)) == REG
2401: && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2402: && CONSTANT_P (XEXP (x, 1)))
2403: {
2404: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2405: ep++)
2406: if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2407: {
2408: if (! mem_mode)
2409: ep->ref_outside_mem = 1;
2410:
2411: /* The only time we want to replace a PLUS with a REG (this
2412: occurs when the constant operand of the PLUS is the negative
2413: of the offset) is when we are inside a MEM. We won't want
2414: to do so at other times because that would change the
2415: structure of the insn in a way that reload can't handle.
2416: We special-case the commonest situation in
2417: eliminate_regs_in_insn, so just replace a PLUS with a
2418: PLUS here, unless inside a MEM. */
2419: if (mem_mode && GET_CODE (XEXP (x, 1)) == CONST_INT
2420: && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2421: return ep->to_rtx;
2422: else
2423: return gen_rtx (PLUS, Pmode, ep->to_rtx,
2424: plus_constant (XEXP (x, 1),
2425: ep->previous_offset));
2426: }
2427:
2428: /* If the register is not eliminable, we are done since the other
2429: operand is a constant. */
2430: return x;
2431: }
2432:
2433: /* If this is part of an address, we want to bring any constant to the
2434: outermost PLUS. We will do this by doing register replacement in
2435: our operands and seeing if a constant shows up in one of them.
2436:
2437: We assume here this is part of an address (or a "load address" insn)
2438: since an eliminable register is not likely to appear in any other
2439: context.
2440:
2441: If we have (plus (eliminable) (reg)), we want to produce
2442: (plus (plus (replacement) (reg) (const))). If this was part of a
2443: normal add insn, (plus (replacement) (reg)) will be pushed as a
2444: reload. This is the desired action. */
2445:
2446: {
2447: rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, 0);
2448: rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, 0);
2449:
2450: if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2451: {
2452: /* If one side is a PLUS and the other side is a pseudo that
2453: didn't get a hard register but has a reg_equiv_constant,
2454: we must replace the constant here since it may no longer
2455: be in the position of any operand. */
2456: if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2457: && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2458: && reg_renumber[REGNO (new1)] < 0
2459: && reg_equiv_constant != 0
2460: && reg_equiv_constant[REGNO (new1)] != 0)
2461: new1 = reg_equiv_constant[REGNO (new1)];
2462: else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2463: && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2464: && reg_renumber[REGNO (new0)] < 0
2465: && reg_equiv_constant[REGNO (new0)] != 0)
2466: new0 = reg_equiv_constant[REGNO (new0)];
2467:
2468: new = form_sum (new0, new1);
2469:
2470: /* As above, if we are not inside a MEM we do not want to
2471: turn a PLUS into something else. We might try to do so here
2472: for an addition of 0 if we aren't optimizing. */
2473: if (! mem_mode && GET_CODE (new) != PLUS)
2474: return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2475: else
2476: return new;
2477: }
2478: }
2479: return x;
2480:
2481: case EXPR_LIST:
2482: /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2483: if (XEXP (x, 0))
2484: {
2485: new = eliminate_regs (XEXP (x, 0), mem_mode, 0);
2486: if (new != XEXP (x, 0))
2487: x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2488: }
2489:
2490: /* ... fall through ... */
2491:
2492: case INSN_LIST:
2493: /* Now do eliminations in the rest of the chain. If this was
2494: an EXPR_LIST, this might result in allocating more memory than is
2495: strictly needed, but it simplifies the code. */
2496: if (XEXP (x, 1))
2497: {
2498: new = eliminate_regs (XEXP (x, 1), mem_mode, 0);
2499: if (new != XEXP (x, 1))
2500: return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new);
2501: }
2502: return x;
2503:
2504: case CALL:
2505: case COMPARE:
2506: case MINUS:
2507: case MULT:
2508: case DIV: case UDIV:
2509: case MOD: case UMOD:
2510: case AND: case IOR: case XOR:
2511: case LSHIFT: case ASHIFT: case ROTATE:
2512: case ASHIFTRT: case LSHIFTRT: case ROTATERT:
2513: case NE: case EQ:
2514: case GE: case GT: case GEU: case GTU:
2515: case LE: case LT: case LEU: case LTU:
2516: {
2517: rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, 0);
2518: rtx new1 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, 0) : 0;
2519:
2520: if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2521: return gen_rtx (code, GET_MODE (x), new0, new1);
2522: }
2523: return x;
2524:
2525: case PRE_INC:
2526: case POST_INC:
2527: case PRE_DEC:
2528: case POST_DEC:
2529: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2530: if (ep->to_rtx == XEXP (x, 0))
2531: {
2532: if (code == PRE_DEC || code == POST_DEC)
2533: ep->offset += GET_MODE_SIZE (mem_mode);
2534: else
2535: ep->offset -= GET_MODE_SIZE (mem_mode);
2536: }
2537:
2538: /* Fall through to generic unary operation case. */
2539: case USE:
2540: case STRICT_LOW_PART:
2541: case NEG: case NOT:
2542: case SIGN_EXTEND: case ZERO_EXTEND:
2543: case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2544: case FLOAT: case FIX:
2545: case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2546: case ABS:
2547: case SQRT:
2548: case FFS:
2549: new = eliminate_regs (XEXP (x, 0), mem_mode, 0);
2550: if (new != XEXP (x, 0))
2551: return gen_rtx (code, GET_MODE (x), new);
2552: return x;
2553:
2554: case SUBREG:
2555: /* Similar to above processing, but preserve SUBREG_WORD.
2556: Convert (subreg (mem)) to (mem) if not paradoxical.
2557: Also, if we have a non-paradoxical (subreg (pseudo)) and the
2558: pseudo didn't get a hard reg, we must replace this with the
2559: eliminated version of the memory location because push_reloads
2560: may do the replacement in certain circumstances. */
2561: if (GET_CODE (SUBREG_REG (x)) == REG
2562: && (GET_MODE_SIZE (GET_MODE (x))
2563: <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2564: && reg_equiv_memory_loc != 0
2565: && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2566: {
2567: new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2568: mem_mode, 0);
2569:
2570: /* If we didn't change anything, we must retain the pseudo. */
2571: if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2572: new = XEXP (x, 0);
2573: else
2574: /* Otherwise, ensure NEW isn't shared in case we have to reload
2575: it. */
2576: new = copy_rtx (new);
2577: }
2578: else
2579: new = eliminate_regs (SUBREG_REG (x), mem_mode, 0);
2580:
2581: if (new != XEXP (x, 0))
2582: {
2583: if (GET_CODE (new) == MEM
2584: && (GET_MODE_SIZE (GET_MODE (x))
2585: <= GET_MODE_SIZE (GET_MODE (new))))
2586: {
2587: int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2588: enum machine_mode mode = GET_MODE (x);
2589:
2590: #if BYTES_BIG_ENDIAN
2591: offset += (MIN (UNITS_PER_WORD,
2592: GET_MODE_SIZE (GET_MODE (new)))
2593: - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2594: #endif
2595:
2596: PUT_MODE (new, mode);
2597: XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2598: return new;
2599: }
2600: else
2601: return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
2602: }
2603:
2604: return x;
2605:
2606: case CLOBBER:
2607: /* If clobbering a register that is the replacement register for an
1.1.1.2 root 2608: elimination we still think can be performed, note that it cannot
1.1 root 2609: be performed. Otherwise, we need not be concerned about it. */
2610: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2611: if (ep->to_rtx == XEXP (x, 0))
2612: ep->can_eliminate = 0;
2613:
2614: return x;
2615:
2616: case ASM_OPERANDS:
2617: {
2618: rtx *temp_vec;
2619: /* Properly handle sharing input and constraint vectors. */
2620: if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2621: {
2622: /* When we come to a new vector not seen before,
2623: scan all its elements; keep the old vector if none
2624: of them changes; otherwise, make a copy. */
2625: old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
2626: temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
2627: for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2628: temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
2629: mem_mode, 0);
2630:
2631: for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2632: if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
2633: break;
2634:
2635: if (i == ASM_OPERANDS_INPUT_LENGTH (x))
2636: new_asm_operands_vec = old_asm_operands_vec;
2637: else
2638: new_asm_operands_vec
2639: = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
2640: }
2641:
2642: /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2643: if (new_asm_operands_vec == old_asm_operands_vec)
2644: return x;
2645:
2646: new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
2647: ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
2648: ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
2649: ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
2650: ASM_OPERANDS_SOURCE_FILE (x),
2651: ASM_OPERANDS_SOURCE_LINE (x));
2652: new->volatil = x->volatil;
2653: return new;
2654: }
2655:
2656: case SET:
2657: /* Check for setting a register that we know about. */
2658: if (GET_CODE (SET_DEST (x)) == REG)
2659: {
2660: /* See if this is setting the replacement register for an
2661: elimination.
2662:
2663: If DEST is the frame pointer, we do nothing because we assume that
2664: all assignments to the frame pointer are for non-local gotos and
2665: are being done at a time when they are valid and do not disturb
2666: anything else. Some machines want to eliminate a fake argument
2667: pointer with either the frame or stack pointer. Assignments to
2668: the frame pointer must not prevent this elimination. */
2669:
2670: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2671: ep++)
2672: if (ep->to_rtx == SET_DEST (x)
2673: && SET_DEST (x) != frame_pointer_rtx)
2674: {
1.1.1.3 ! root 2675: /* If it is being incremented, adjust the offset. Otherwise,
1.1 root 2676: this elimination can't be done. */
2677: rtx src = SET_SRC (x);
2678:
2679: if (GET_CODE (src) == PLUS
2680: && XEXP (src, 0) == SET_DEST (x)
2681: && GET_CODE (XEXP (src, 1)) == CONST_INT)
2682: ep->offset -= INTVAL (XEXP (src, 1));
2683: else
2684: ep->can_eliminate = 0;
2685: }
2686:
2687: /* Now check to see we are assigning to a register that can be
2688: eliminated. If so, it must be as part of a PARALLEL, since we
2689: will not have been called if this is a single SET. So indicate
2690: that we can no longer eliminate this reg. */
2691: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2692: ep++)
2693: if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
2694: ep->can_eliminate = 0;
2695: }
2696:
2697: /* Now avoid the loop below in this common case. */
2698: {
2699: rtx new0 = eliminate_regs (SET_DEST (x), 0, 0);
2700: rtx new1 = eliminate_regs (SET_SRC (x), 0, 0);
2701:
2702: /* If SET_DEST changed from a REG to a MEM and INSN is non-zero,
2703: write a CLOBBER insn. */
2704: if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
2705: && insn != 0)
2706: emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
2707:
2708: if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
2709: return gen_rtx (SET, VOIDmode, new0, new1);
2710: }
2711:
2712: return x;
2713:
2714: case MEM:
2715: /* Our only special processing is to pass the mode of the MEM to our
2716: recursive call and copy the flags. While we are here, handle this
2717: case more efficiently. */
2718: new = eliminate_regs (XEXP (x, 0), GET_MODE (x), 0);
2719: if (new != XEXP (x, 0))
2720: {
2721: new = gen_rtx (MEM, GET_MODE (x), new);
2722: new->volatil = x->volatil;
2723: new->unchanging = x->unchanging;
2724: new->in_struct = x->in_struct;
2725: return new;
2726: }
2727: else
2728: return x;
2729: }
2730:
2731: /* Process each of our operands recursively. If any have changed, make a
2732: copy of the rtx. */
2733: fmt = GET_RTX_FORMAT (code);
2734: for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2735: {
2736: if (*fmt == 'e')
2737: {
2738: new = eliminate_regs (XEXP (x, i), mem_mode, 0);
2739: if (new != XEXP (x, i) && ! copied)
2740: {
2741: rtx new_x = rtx_alloc (code);
2742: bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2743: + (sizeof (new_x->fld[0])
2744: * GET_RTX_LENGTH (code))));
2745: x = new_x;
2746: copied = 1;
2747: }
2748: XEXP (x, i) = new;
2749: }
2750: else if (*fmt == 'E')
2751: {
2752: int copied_vec = 0;
2753: for (j = 0; j < XVECLEN (x, i); j++)
2754: {
2755: new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2756: if (new != XVECEXP (x, i, j) && ! copied_vec)
2757: {
2758: rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2759: &XVECEXP (x, i, 0));
2760: if (! copied)
2761: {
2762: rtx new_x = rtx_alloc (code);
2763: bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2764: + (sizeof (new_x->fld[0])
2765: * GET_RTX_LENGTH (code))));
2766: x = new_x;
2767: copied = 1;
2768: }
2769: XVEC (x, i) = new_v;
2770: copied_vec = 1;
2771: }
2772: XVECEXP (x, i, j) = new;
2773: }
2774: }
2775: }
2776:
2777: return x;
2778: }
2779:
2780: /* Scan INSN and eliminate all eliminable registers in it.
2781:
2782: If REPLACE is nonzero, do the replacement destructively. Also
2783: delete the insn as dead it if it is setting an eliminable register.
2784:
2785: If REPLACE is zero, do all our allocations in reload_obstack.
2786:
2787: If no eliminations were done and this insn doesn't require any elimination
2788: processing (these are not identical conditions: it might be updating sp,
2789: but not referencing fp; this needs to be seen during reload_as_needed so
2790: that the offset between fp and sp can be taken into consideration), zero
2791: is returned. Otherwise, 1 is returned. */
2792:
2793: static int
2794: eliminate_regs_in_insn (insn, replace)
2795: rtx insn;
2796: int replace;
2797: {
2798: rtx old_body = PATTERN (insn);
2799: rtx new_body;
2800: int val = 0;
2801: struct elim_table *ep;
2802:
2803: if (! replace)
2804: push_obstacks (&reload_obstack, &reload_obstack);
2805:
2806: if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG
2807: && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER)
2808: {
2809: /* Check for setting an eliminable register. */
2810: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2811: if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate)
2812: {
2813: /* In this case this insn isn't serving a useful purpose. We
2814: will delete it in reload_as_needed once we know that this
2815: elimination is, in fact, being done.
2816:
2817: If REPLACE isn't set, we can't delete this insn, but neededn't
2818: process it since it won't be used unless something changes. */
2819: if (replace)
2820: delete_dead_insn (insn);
2821: val = 1;
2822: goto done;
2823: }
2824:
2825: /* Check for (set (reg) (plus (reg from) (offset))) where the offset
2826: in the insn is the negative of the offset in FROM. Substitute
2827: (set (reg) (reg to)) for the insn and change its code.
2828:
2829: We have to do this here, rather than in eliminate_regs, do that we can
2830: change the insn code. */
2831:
2832: if (GET_CODE (SET_SRC (old_body)) == PLUS
2833: && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG
2834: && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT)
2835: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2836: ep++)
2837: if (ep->from_rtx == XEXP (SET_SRC (old_body), 0)
2838: && ep->can_eliminate
2839: && ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1)))
2840: {
2841: PATTERN (insn) = gen_rtx (SET, VOIDmode,
2842: SET_DEST (old_body), ep->to_rtx);
2843: INSN_CODE (insn) = -1;
2844: val = 1;
2845: goto done;
2846: }
2847: }
2848:
2849: old_asm_operands_vec = 0;
2850:
2851: /* Replace the body of this insn with a substituted form. If we changed
2852: something, return non-zero. If this is the final call for this
2853: insn (REPLACE is non-zero), do the elimination in REG_NOTES as well.
2854:
2855: If we are replacing a body that was a (set X (plus Y Z)), try to
2856: re-recognize the insn. We do this in case we had a simple addition
2857: but now can do this as a load-address. This saves an insn in this
2858: common case. */
2859:
2860: new_body = eliminate_regs (old_body, 0, replace ? insn : 0);
2861: if (new_body != old_body)
2862: {
2863: if (GET_CODE (old_body) != SET || GET_CODE (SET_SRC (old_body)) != PLUS
2864: || ! validate_change (insn, &PATTERN (insn), new_body, 0))
2865: PATTERN (insn) = new_body;
2866:
2867: if (replace && REG_NOTES (insn))
2868: REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, 0);
2869: val = 1;
2870: }
2871:
2872: /* Loop through all elimination pairs. See if any have changed and
2873: recalculate the number not at initial offset.
2874:
2875: Compute the maximum offset (minimum offset if the stack does not
2876: grow downward) for each elimination pair.
2877:
2878: We also detect a cases where register elimination cannot be done,
2879: namely, if a register would be both changed and referenced outside a MEM
2880: in the resulting insn since such an insn is often undefined and, even if
2881: not, we cannot know what meaning will be given to it. Note that it is
2882: valid to have a register used in an address in an insn that changes it
2883: (presumably with a pre- or post-increment or decrement).
2884:
2885: If anything changes, return nonzero. */
2886:
2887: num_not_at_initial_offset = 0;
2888: for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2889: {
2890: if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
2891: ep->can_eliminate = 0;
2892:
2893: ep->ref_outside_mem = 0;
2894:
2895: if (ep->previous_offset != ep->offset)
2896: val = 1;
2897:
2898: ep->previous_offset = ep->offset;
2899: if (ep->can_eliminate && ep->offset != ep->initial_offset)
2900: num_not_at_initial_offset++;
2901:
2902: #ifdef STACK_GROWS_DOWNWARD
2903: ep->max_offset = MAX (ep->max_offset, ep->offset);
2904: #else
2905: ep->max_offset = MIN (ep->max_offset, ep->offset);
2906: #endif
2907: }
2908:
2909: done:
2910: if (! replace)
2911: pop_obstacks ();
2912:
2913: return val;
2914: }
2915:
2916: /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
2917: replacement we currently believe is valid, mark it as not eliminable if X
2918: modifies DEST in any way other than by adding a constant integer to it.
2919:
2920: If DEST is the frame pointer, we do nothing because we assume that
2921: all assignments to the frame pointer are nonlocal gotos and are being done
2922: at a time when they are valid and do not disturb anything else.
2923: Some machines want to eliminate a fake argument pointer with either the
2924: frame or stack pointer. Assignments to the frame pointer must not prevent
2925: this elimination.
2926:
2927: Called via note_stores from reload before starting its passes to scan
2928: the insns of the function. */
2929:
2930: static void
2931: mark_not_eliminable (dest, x)
2932: rtx dest;
2933: rtx x;
2934: {
2935: register int i;
2936:
2937: /* A SUBREG of a hard register here is just changing its mode. We should
2938: not see a SUBREG of an eliminable hard register, but check just in
2939: case. */
2940: if (GET_CODE (dest) == SUBREG)
2941: dest = SUBREG_REG (dest);
2942:
2943: if (dest == frame_pointer_rtx)
2944: return;
2945:
2946: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2947: if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
2948: && (GET_CODE (x) != SET
2949: || GET_CODE (SET_SRC (x)) != PLUS
2950: || XEXP (SET_SRC (x), 0) != dest
2951: || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
2952: {
2953: reg_eliminate[i].can_eliminate_previous
2954: = reg_eliminate[i].can_eliminate = 0;
2955: num_eliminable--;
2956: }
2957: }
2958:
2959: /* Kick all pseudos out of hard register REGNO.
2960: If GLOBAL is nonzero, try to find someplace else to put them.
2961: If DUMPFILE is nonzero, log actions taken on that file.
2962:
2963: If CANT_ELIMINATE is nonzero, it means that we are doing this spill
2964: because we found we can't eliminate some register. In the case, no pseudos
2965: are allowed to be in the register, even if they are only in a block that
2966: doesn't require spill registers, unlike the case when we are spilling this
2967: hard reg to produce another spill register.
2968:
2969: Return nonzero if any pseudos needed to be kicked out. */
2970:
2971: static int
2972: spill_hard_reg (regno, global, dumpfile, cant_eliminate)
2973: register int regno;
2974: int global;
2975: FILE *dumpfile;
2976: int cant_eliminate;
2977: {
2978: int something_changed = 0;
2979: register int i;
2980:
2981: SET_HARD_REG_BIT (forbidden_regs, regno);
2982:
2983: /* Spill every pseudo reg that was allocated to this reg
2984: or to something that overlaps this reg. */
2985:
2986: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2987: if (reg_renumber[i] >= 0
2988: && reg_renumber[i] <= regno
2989: && (reg_renumber[i]
2990: + HARD_REGNO_NREGS (reg_renumber[i],
2991: PSEUDO_REGNO_MODE (i))
2992: > regno))
2993: {
2994: enum reg_class class = REGNO_REG_CLASS (regno);
2995:
2996: /* If this register belongs solely to a basic block which needed no
2997: spilling of any class that this register is contained in,
2998: leave it be, unless we are spilling this register because
2999: it was a hard register that can't be eliminated. */
3000:
3001: if (! cant_eliminate
3002: && basic_block_needs[0]
3003: && reg_basic_block[i] >= 0
3004: && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3005: {
3006: enum reg_class *p;
3007:
3008: for (p = reg_class_superclasses[(int) class];
3009: *p != LIM_REG_CLASSES; p++)
3010: if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3011: break;
3012:
3013: if (*p == LIM_REG_CLASSES)
3014: continue;
3015: }
3016:
3017: /* Mark it as no longer having a hard register home. */
3018: reg_renumber[i] = -1;
3019: /* We will need to scan everything again. */
3020: something_changed = 1;
3021: if (global)
3022: retry_global_alloc (i, forbidden_regs);
3023:
3024: alter_reg (i, regno);
3025: if (dumpfile)
3026: {
3027: if (reg_renumber[i] == -1)
3028: fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3029: else
3030: fprintf (dumpfile, " Register %d now in %d.\n\n",
3031: i, reg_renumber[i]);
3032: }
3033: }
3034:
3035: return something_changed;
3036: }
3037:
3038: /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3039:
3040: static void
3041: scan_paradoxical_subregs (x)
3042: register rtx x;
3043: {
3044: register int i;
3045: register char *fmt;
3046: register enum rtx_code code = GET_CODE (x);
3047:
3048: switch (code)
3049: {
3050: case CONST_INT:
3051: case CONST:
3052: case SYMBOL_REF:
3053: case LABEL_REF:
3054: case CONST_DOUBLE:
3055: case CC0:
3056: case PC:
3057: case REG:
3058: case USE:
3059: case CLOBBER:
3060: return;
3061:
3062: case SUBREG:
3063: if (GET_CODE (SUBREG_REG (x)) == REG
3064: && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3065: reg_max_ref_width[REGNO (SUBREG_REG (x))]
3066: = GET_MODE_SIZE (GET_MODE (x));
3067: return;
3068: }
3069:
3070: fmt = GET_RTX_FORMAT (code);
3071: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3072: {
3073: if (fmt[i] == 'e')
3074: scan_paradoxical_subregs (XEXP (x, i));
3075: else if (fmt[i] == 'E')
3076: {
3077: register int j;
3078: for (j = XVECLEN (x, i) - 1; j >=0; j--)
3079: scan_paradoxical_subregs (XVECEXP (x, i, j));
3080: }
3081: }
3082: }
3083:
3084: struct hard_reg_n_uses { int regno; int uses; };
3085:
3086: static int
3087: hard_reg_use_compare (p1, p2)
3088: struct hard_reg_n_uses *p1, *p2;
3089: {
3090: int tem = p1->uses - p2->uses;
3091: if (tem != 0) return tem;
3092: /* If regs are equally good, sort by regno,
3093: so that the results of qsort leave nothing to chance. */
3094: return p1->regno - p2->regno;
3095: }
3096:
3097: /* Choose the order to consider regs for use as reload registers
3098: based on how much trouble would be caused by spilling one.
3099: Store them in order of decreasing preference in potential_reload_regs. */
3100:
3101: static void
3102: order_regs_for_reload ()
3103: {
3104: register int i;
3105: register int o = 0;
3106: int large = 0;
3107:
3108: struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3109:
3110: CLEAR_HARD_REG_SET (bad_spill_regs);
3111:
3112: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3113: potential_reload_regs[i] = -1;
3114:
3115: /* Count number of uses of each hard reg by pseudo regs allocated to it
3116: and then order them by decreasing use. */
3117:
3118: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3119: {
3120: hard_reg_n_uses[i].uses = 0;
3121: hard_reg_n_uses[i].regno = i;
3122: }
3123:
3124: for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3125: {
3126: int regno = reg_renumber[i];
3127: if (regno >= 0)
3128: {
3129: int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3130: while (regno < lim)
3131: hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3132: }
3133: large += reg_n_refs[i];
3134: }
3135:
3136: /* Now fixed registers (which cannot safely be used for reloading)
3137: get a very high use count so they will be considered least desirable.
3138: Registers used explicitly in the rtl code are almost as bad. */
3139:
3140: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3141: {
3142: if (fixed_regs[i])
3143: {
3144: hard_reg_n_uses[i].uses += 2 * large + 2;
3145: SET_HARD_REG_BIT (bad_spill_regs, i);
3146: }
3147: else if (regs_explicitly_used[i])
3148: {
3149: hard_reg_n_uses[i].uses += large + 1;
3150: /* ??? We are doing this here because of the potential that
3151: bad code may be generated if a register explicitly used in
3152: an insn was used as a spill register for that insn. But
3153: not using these are spill registers may lose on some machine.
3154: We'll have to see how this works out. */
3155: SET_HARD_REG_BIT (bad_spill_regs, i);
3156: }
3157: }
3158: hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3159: SET_HARD_REG_BIT (bad_spill_regs, FRAME_POINTER_REGNUM);
3160:
3161: #ifdef ELIMINABLE_REGS
3162: /* If registers other than the frame pointer are eliminable, mark them as
3163: poor choices. */
3164: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3165: {
3166: hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3167: SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3168: }
3169: #endif
3170:
3171: /* Prefer registers not so far used, for use in temporary loading.
3172: Among them, if REG_ALLOC_ORDER is defined, use that order.
3173: Otherwise, prefer registers not preserved by calls. */
3174:
3175: #ifdef REG_ALLOC_ORDER
3176: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3177: {
3178: int regno = reg_alloc_order[i];
3179:
3180: if (hard_reg_n_uses[regno].uses == 0)
3181: potential_reload_regs[o++] = regno;
3182: }
3183: #else
3184: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3185: {
3186: if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3187: potential_reload_regs[o++] = i;
3188: }
3189: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3190: {
3191: if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3192: potential_reload_regs[o++] = i;
3193: }
3194: #endif
3195:
3196: qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3197: sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3198:
3199: /* Now add the regs that are already used,
3200: preferring those used less often. The fixed and otherwise forbidden
3201: registers will be at the end of this list. */
3202:
3203: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3204: if (hard_reg_n_uses[i].uses != 0)
3205: potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3206: }
3207:
3208: /* Reload pseudo-registers into hard regs around each insn as needed.
3209: Additional register load insns are output before the insn that needs it
3210: and perhaps store insns after insns that modify the reloaded pseudo reg.
3211:
3212: reg_last_reload_reg and reg_reloaded_contents keep track of
3213: which pseudo-registers are already available in reload registers.
3214: We update these for the reloads that we perform,
3215: as the insns are scanned. */
3216:
3217: static void
3218: reload_as_needed (first, live_known)
3219: rtx first;
3220: int live_known;
3221: {
3222: register rtx insn;
3223: register int i;
3224: int this_block = 0;
3225: rtx x;
3226: rtx after_call = 0;
3227:
3228: bzero (spill_reg_rtx, sizeof spill_reg_rtx);
3229: reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3230: bzero (reg_last_reload_reg, max_regno * sizeof (rtx));
3231: reg_has_output_reload = (char *) alloca (max_regno);
3232: for (i = 0; i < n_spills; i++)
3233: {
3234: reg_reloaded_contents[i] = -1;
3235: reg_reloaded_insn[i] = 0;
3236: }
3237:
3238: /* Reset all offsets on eliminable registers to their initial values. */
3239: #ifdef ELIMINABLE_REGS
3240: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3241: {
3242: INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3243: reg_eliminate[i].initial_offset)
3244: reg_eliminate[i].previous_offset
3245: = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3246: }
3247: #else
3248: INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3249: reg_eliminate[0].previous_offset
3250: = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3251: #endif
3252:
3253: num_not_at_initial_offset = 0;
3254:
3255: for (insn = first; insn;)
3256: {
3257: register rtx next = NEXT_INSN (insn);
3258:
3259: /* Notice when we move to a new basic block. */
1.1.1.2 root 3260: if (live_known && this_block + 1 < n_basic_blocks
1.1 root 3261: && insn == basic_block_head[this_block+1])
3262: ++this_block;
3263:
3264: /* If we pass a label, copy the offsets from the label information
3265: into the current offsets of each elimination. */
3266: if (GET_CODE (insn) == CODE_LABEL)
3267: {
3268: num_not_at_initial_offset = 0;
3269: for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3270: {
3271: reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3272: = offsets_at[CODE_LABEL_NUMBER (insn)][i];
1.1.1.2 root 3273: if (reg_eliminate[i].can_eliminate
3274: && (reg_eliminate[i].offset
3275: != reg_eliminate[i].initial_offset))
1.1 root 3276: num_not_at_initial_offset++;
3277: }
3278: }
3279:
3280: else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3281: {
3282: rtx avoid_return_reg = 0;
3283:
3284: #ifdef SMALL_REGISTER_CLASSES
3285: /* Set avoid_return_reg if this is an insn
3286: that might use the value of a function call. */
3287: if (GET_CODE (insn) == CALL_INSN)
3288: {
3289: if (GET_CODE (PATTERN (insn)) == SET)
3290: after_call = SET_DEST (PATTERN (insn));
3291: else if (GET_CODE (PATTERN (insn)) == PARALLEL
3292: && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3293: after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3294: else
3295: after_call = 0;
3296: }
3297: else if (after_call != 0
3298: && !(GET_CODE (PATTERN (insn)) == SET
3299: && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3300: {
3301: if (reg_mentioned_p (after_call, PATTERN (insn)))
3302: avoid_return_reg = after_call;
3303: after_call = 0;
3304: }
3305: #endif /* SMALL_REGISTER_CLASSES */
3306:
1.1.1.2 root 3307: /* If this is a USE and CLOBBER of a MEM, ensure that any
3308: references to eliminable registers have been removed. */
3309:
3310: if ((GET_CODE (PATTERN (insn)) == USE
3311: || GET_CODE (PATTERN (insn)) == CLOBBER)
3312: && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3313: XEXP (XEXP (PATTERN (insn), 0), 0)
3314: = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3315: GET_MODE (XEXP (PATTERN (insn), 0)), 0);
3316:
1.1 root 3317: /* If we need to do register elimination processing, do so.
3318: This might delete the insn, in which case we are done. */
3319: if (num_eliminable && GET_MODE (insn) == QImode)
3320: {
3321: eliminate_regs_in_insn (insn, 1);
3322: if (GET_CODE (insn) == NOTE)
3323: {
3324: insn = next;
3325: continue;
3326: }
3327: }
3328:
3329: if (GET_MODE (insn) == VOIDmode)
3330: n_reloads = 0;
3331: /* First find the pseudo regs that must be reloaded for this insn.
3332: This info is returned in the tables reload_... (see reload.h).
3333: Also modify the body of INSN by substituting RELOAD
3334: rtx's for those pseudo regs. */
3335: else
3336: {
3337: bzero (reg_has_output_reload, max_regno);
3338: CLEAR_HARD_REG_SET (reg_is_output_reload);
3339:
3340: find_reloads (insn, 1, spill_indirect_levels, live_known,
3341: spill_reg_order);
3342: }
3343:
3344: if (n_reloads > 0)
3345: {
1.1.1.3 ! root 3346: rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
! 3347: rtx p;
1.1 root 3348: int class;
3349:
3350: /* If this block has not had spilling done for a
3351: particular class, deactivate any optional reloads
3352: of that class lest they try to use a spill-reg which isn't
3353: available here. If we have any non-optionals that need a
3354: spill reg, abort. */
3355:
3356: for (class = 0; class < N_REG_CLASSES; class++)
3357: if (basic_block_needs[class] != 0
3358: && basic_block_needs[class][this_block] == 0)
3359: for (i = 0; i < n_reloads; i++)
3360: if (class == (int) reload_reg_class[i])
3361: {
3362: if (reload_optional[i])
1.1.1.3 ! root 3363: {
! 3364: reload_in[i] = reload_out[i] = 0;
! 3365: reload_secondary_p[i] = 0;
! 3366: }
! 3367: else if (reload_reg_rtx[i] == 0
! 3368: && (reload_in[i] != 0 || reload_out[i] != 0
! 3369: || reload_secondary_p[i] != 0))
1.1 root 3370: abort ();
3371: }
3372:
3373: /* Now compute which reload regs to reload them into. Perhaps
3374: reusing reload regs from previous insns, or else output
3375: load insns to reload them. Maybe output store insns too.
3376: Record the choices of reload reg in reload_reg_rtx. */
3377: choose_reload_regs (insn, avoid_return_reg);
3378:
3379: /* Generate the insns to reload operands into or out of
3380: their reload regs. */
3381: emit_reload_insns (insn);
3382:
3383: /* Substitute the chosen reload regs from reload_reg_rtx
3384: into the insn's body (or perhaps into the bodies of other
3385: load and store insn that we just made for reloading
3386: and that we moved the structure into). */
3387: subst_reloads ();
1.1.1.3 ! root 3388:
! 3389: /* If this was an ASM, make sure that all the reload insns
! 3390: we have generated are valid. If not, give an error
! 3391: and delete them. */
! 3392:
! 3393: if (asm_noperands (PATTERN (insn)) >= 0)
! 3394: for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
! 3395: if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
! 3396: && (recog_memoized (p) < 0
! 3397: || (insn_extract (p),
! 3398: ! constrain_operands (INSN_CODE (p), 1))))
! 3399: {
! 3400: error_for_asm (insn,
! 3401: "`asm' operand requires impossible reload");
! 3402: PUT_CODE (p, NOTE);
! 3403: NOTE_SOURCE_FILE (p) = 0;
! 3404: NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
! 3405: }
1.1 root 3406: }
3407: /* Any previously reloaded spilled pseudo reg, stored in this insn,
3408: is no longer validly lying around to save a future reload.
3409: Note that this does not detect pseudos that were reloaded
3410: for this insn in order to be stored in
3411: (obeying register constraints). That is correct; such reload
3412: registers ARE still valid. */
3413: note_stores (PATTERN (insn), forget_old_reloads_1);
3414:
3415: /* There may have been CLOBBER insns placed after INSN. So scan
3416: between INSN and NEXT and use them to forget old reloads. */
3417: for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3418: if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3419: note_stores (PATTERN (x), forget_old_reloads_1);
3420:
3421: #ifdef AUTO_INC_DEC
3422: /* Likewise for regs altered by auto-increment in this insn.
3423: But note that the reg-notes are not changed by reloading:
3424: they still contain the pseudo-regs, not the spill regs. */
3425: for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3426: if (REG_NOTE_KIND (x) == REG_INC)
3427: {
3428: /* See if this pseudo reg was reloaded in this insn.
3429: If so, its last-reload info is still valid
3430: because it is based on this insn's reload. */
3431: for (i = 0; i < n_reloads; i++)
3432: if (reload_out[i] == XEXP (x, 0))
3433: break;
3434:
3435: if (i != n_reloads)
3436: forget_old_reloads_1 (XEXP (x, 0));
3437: }
3438: #endif
3439: }
3440: /* A reload reg's contents are unknown after a label. */
3441: if (GET_CODE (insn) == CODE_LABEL)
3442: for (i = 0; i < n_spills; i++)
3443: {
3444: reg_reloaded_contents[i] = -1;
3445: reg_reloaded_insn[i] = 0;
3446: }
3447:
3448: /* Don't assume a reload reg is still good after a call insn
3449: if it is a call-used reg. */
3450: if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == CALL_INSN)
3451: for (i = 0; i < n_spills; i++)
3452: if (call_used_regs[spill_regs[i]])
3453: {
3454: reg_reloaded_contents[i] = -1;
3455: reg_reloaded_insn[i] = 0;
3456: }
3457:
3458: /* In case registers overlap, allow certain insns to invalidate
3459: particular hard registers. */
3460:
3461: #ifdef INSN_CLOBBERS_REGNO_P
3462: for (i = 0 ; i < n_spills ; i++)
3463: if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
3464: {
3465: reg_reloaded_contents[i] = -1;
3466: reg_reloaded_insn[i] = 0;
3467: }
3468: #endif
3469:
3470: insn = next;
3471:
3472: #ifdef USE_C_ALLOCA
3473: alloca (0);
3474: #endif
3475: }
3476: }
3477:
3478: /* Discard all record of any value reloaded from X,
3479: or reloaded in X from someplace else;
3480: unless X is an output reload reg of the current insn.
3481:
3482: X may be a hard reg (the reload reg)
3483: or it may be a pseudo reg that was reloaded from. */
3484:
3485: static void
3486: forget_old_reloads_1 (x)
3487: rtx x;
3488: {
3489: register int regno;
3490: int nr;
3491:
3492: if (GET_CODE (x) != REG)
3493: return;
3494:
3495: regno = REGNO (x);
3496:
3497: if (regno >= FIRST_PSEUDO_REGISTER)
3498: nr = 1;
3499: else
3500: {
3501: int i;
3502: nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3503: /* Storing into a spilled-reg invalidates its contents.
3504: This can happen if a block-local pseudo is allocated to that reg
3505: and it wasn't spilled because this block's total need is 0.
3506: Then some insn might have an optional reload and use this reg. */
3507: for (i = 0; i < nr; i++)
3508: if (spill_reg_order[regno + i] >= 0
3509: /* But don't do this if the reg actually serves as an output
3510: reload reg in the current instruction. */
3511: && (n_reloads == 0
3512: || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
3513: {
3514: reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
3515: reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
3516: }
3517: }
3518:
3519: /* Since value of X has changed,
3520: forget any value previously copied from it. */
3521:
3522: while (nr-- > 0)
3523: /* But don't forget a copy if this is the output reload
3524: that establishes the copy's validity. */
3525: if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3526: reg_last_reload_reg[regno + nr] = 0;
3527: }
3528:
3529: /* For each reload, the mode of the reload register. */
3530: static enum machine_mode reload_mode[MAX_RELOADS];
3531:
3532: /* For each reload, the largest number of registers it will require. */
3533: static int reload_nregs[MAX_RELOADS];
3534:
3535: /* Comparison function for qsort to decide which of two reloads
3536: should be handled first. *P1 and *P2 are the reload numbers. */
3537:
3538: static int
3539: reload_reg_class_lower (p1, p2)
3540: short *p1, *p2;
3541: {
3542: register int r1 = *p1, r2 = *p2;
3543: register int t;
3544:
3545: /* Consider required reloads before optional ones. */
3546: t = reload_optional[r1] - reload_optional[r2];
3547: if (t != 0)
3548: return t;
3549:
3550: /* Count all solitary classes before non-solitary ones. */
3551: t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
3552: - (reg_class_size[(int) reload_reg_class[r1]] == 1));
3553: if (t != 0)
3554: return t;
3555:
3556: /* Aside from solitaires, consider all multi-reg groups first. */
3557: t = reload_nregs[r2] - reload_nregs[r1];
3558: if (t != 0)
3559: return t;
3560:
3561: /* Consider reloads in order of increasing reg-class number. */
3562: t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
3563: if (t != 0)
3564: return t;
3565:
3566: /* If reloads are equally urgent, sort by reload number,
3567: so that the results of qsort leave nothing to chance. */
3568: return r1 - r2;
3569: }
3570:
3571: /* The following HARD_REG_SETs indicate when each hard register is
3572: used for a reload of various parts of the current insn. */
3573:
3574: /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3575: static HARD_REG_SET reload_reg_used;
3576: /* If reg is in use for a RELOAD_FOR_INPUT_RELOAD_ADDRESS reload. */
3577: static HARD_REG_SET reload_reg_used_in_input_addr;
3578: /* If reg is in use for a RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reload. */
3579: static HARD_REG_SET reload_reg_used_in_output_addr;
3580: /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
3581: static HARD_REG_SET reload_reg_used_in_op_addr;
3582: /* If reg is in use for a RELOAD_FOR_INPUT reload. */
3583: static HARD_REG_SET reload_reg_used_in_input;
3584: /* If reg is in use for a RELOAD_FOR_OUTPUT reload. */
3585: static HARD_REG_SET reload_reg_used_in_output;
3586:
3587: /* If reg is in use as a reload reg for any sort of reload. */
3588: static HARD_REG_SET reload_reg_used_at_all;
3589:
3590: /* Mark reg REGNO as in use for a reload of the sort spec'd by WHEN_NEEDED.
3591: MODE is used to indicate how many consecutive regs are actually used. */
3592:
3593: static void
3594: mark_reload_reg_in_use (regno, when_needed, mode)
3595: int regno;
3596: enum reload_when_needed when_needed;
3597: enum machine_mode mode;
3598: {
3599: int nregs = HARD_REGNO_NREGS (regno, mode);
3600: int i;
3601:
3602: for (i = regno; i < nregs + regno; i++)
3603: {
3604: switch (when_needed)
3605: {
3606: case RELOAD_OTHER:
3607: SET_HARD_REG_BIT (reload_reg_used, i);
3608: break;
3609:
3610: case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3611: SET_HARD_REG_BIT (reload_reg_used_in_input_addr, i);
3612: break;
3613:
3614: case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3615: SET_HARD_REG_BIT (reload_reg_used_in_output_addr, i);
3616: break;
3617:
3618: case RELOAD_FOR_OPERAND_ADDRESS:
3619: SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
3620: break;
3621:
3622: case RELOAD_FOR_INPUT:
3623: SET_HARD_REG_BIT (reload_reg_used_in_input, i);
3624: break;
3625:
3626: case RELOAD_FOR_OUTPUT:
3627: SET_HARD_REG_BIT (reload_reg_used_in_output, i);
3628: break;
3629: }
3630:
3631: SET_HARD_REG_BIT (reload_reg_used_at_all, i);
3632: }
3633: }
3634:
3635: /* 1 if reg REGNO is free as a reload reg for a reload of the sort
3636: specified by WHEN_NEEDED. */
3637:
3638: static int
3639: reload_reg_free_p (regno, when_needed)
3640: int regno;
3641: enum reload_when_needed when_needed;
3642: {
3643: /* In use for a RELOAD_OTHER means it's not available for anything. */
3644: if (TEST_HARD_REG_BIT (reload_reg_used, regno))
3645: return 0;
3646: switch (when_needed)
3647: {
3648: case RELOAD_OTHER:
3649: /* In use for anything means not available for a RELOAD_OTHER. */
3650: return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno);
3651:
3652: /* The other kinds of use can sometimes share a register. */
3653: case RELOAD_FOR_INPUT:
3654: return (! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno)
3655: && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3656: && ! TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno));
3657: case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3658: return (! TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno)
3659: && ! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno));
3660: case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3661: return (! TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno)
3662: && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3663: case RELOAD_FOR_OPERAND_ADDRESS:
3664: return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3665: && ! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno)
3666: && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3667: case RELOAD_FOR_OUTPUT:
3668: return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3669: && ! TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno)
3670: && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3671: }
3672: abort ();
3673: }
3674:
3675: /* Return 1 if the value in reload reg REGNO, as used by a reload
3676: needed for the part of the insn specified by WHEN_NEEDED,
3677: is not in use for a reload in any prior part of the insn.
3678:
3679: We can assume that the reload reg was already tested for availability
3680: at the time it is needed, and we should not check this again,
3681: in case the reg has already been marked in use. */
3682:
3683: static int
3684: reload_reg_free_before_p (regno, when_needed)
3685: int regno;
3686: enum reload_when_needed when_needed;
3687: {
3688: switch (when_needed)
3689: {
3690: case RELOAD_OTHER:
3691: /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
3692: its use starts from the beginning, so nothing can use it earlier. */
3693: return 1;
3694:
3695: /* If this use is for part of the insn,
3696: check the reg is not in use for any prior part. */
3697: case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3698: if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
3699: return 0;
3700: case RELOAD_FOR_OUTPUT:
3701: if (TEST_HARD_REG_BIT (reload_reg_used_in_input, regno))
3702: return 0;
3703: case RELOAD_FOR_OPERAND_ADDRESS:
3704: if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno))
3705: return 0;
3706: case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3707: case RELOAD_FOR_INPUT:
3708: return 1;
3709: }
3710: abort ();
3711: }
3712:
3713: /* Return 1 if the value in reload reg REGNO, as used by a reload
3714: needed for the part of the insn specified by WHEN_NEEDED,
3715: is still available in REGNO at the end of the insn.
3716:
3717: We can assume that the reload reg was already tested for availability
3718: at the time it is needed, and we should not check this again,
3719: in case the reg has already been marked in use. */
3720:
3721: static int
3722: reload_reg_reaches_end_p (regno, when_needed)
3723: int regno;
3724: enum reload_when_needed when_needed;
3725: {
3726: switch (when_needed)
3727: {
3728: case RELOAD_OTHER:
3729: /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
3730: its value must reach the end. */
3731: return 1;
3732:
3733: /* If this use is for part of the insn,
3734: its value reaches if no subsequent part uses the same register. */
3735: case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3736: case RELOAD_FOR_INPUT:
3737: if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3738: || TEST_HARD_REG_BIT (reload_reg_used_in_output, regno))
3739: return 0;
3740: case RELOAD_FOR_OPERAND_ADDRESS:
3741: if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno))
3742: return 0;
3743: case RELOAD_FOR_OUTPUT:
3744: case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3745: return 1;
3746: }
3747: abort ();
3748: }
3749:
3750: /* Vector of reload-numbers showing the order in which the reloads should
3751: be processed. */
3752: short reload_order[MAX_RELOADS];
3753:
3754: /* Indexed by reload number, 1 if incoming value
3755: inherited from previous insns. */
3756: char reload_inherited[MAX_RELOADS];
3757:
3758: /* For an inherited reload, this is the insn the reload was inherited from,
3759: if we know it. Otherwise, this is 0. */
3760: rtx reload_inheritance_insn[MAX_RELOADS];
3761:
3762: /* If non-zero, this is a place to get the value of the reload,
3763: rather than using reload_in. */
3764: rtx reload_override_in[MAX_RELOADS];
3765:
3766: /* For each reload, the index in spill_regs of the spill register used,
3767: or -1 if we did not need one of the spill registers for this reload. */
3768: int reload_spill_index[MAX_RELOADS];
3769:
3770: /* Index of last register assigned as a spill register. We allocate in
3771: a round-robin fashio. */
3772:
3773: static last_spill_reg = 0;
3774:
3775: /* Find a spill register to use as a reload register for reload R.
3776: LAST_RELOAD is non-zero if this is the last reload for the insn being
3777: processed.
3778:
3779: Set reload_reg_rtx[R] to the register allocated.
3780:
3781: If NOERROR is nonzero, we return 1 if successful,
3782: or 0 if we couldn't find a spill reg and we didn't change anything. */
3783:
3784: static int
3785: allocate_reload_reg (r, insn, last_reload, noerror)
3786: int r;
3787: rtx insn;
3788: int last_reload;
3789: int noerror;
3790: {
3791: int i;
3792: int pass;
3793: int count;
3794: rtx new;
3795: int regno;
3796:
3797: /* If we put this reload ahead, thinking it is a group,
3798: then insist on finding a group. Otherwise we can grab a
3799: reg that some other reload needs.
3800: (That can happen when we have a 68000 DATA_OR_FP_REG
3801: which is a group of data regs or one fp reg.)
3802: We need not be so restrictive if there are no more reloads
3803: for this insn.
3804:
3805: ??? Really it would be nicer to have smarter handling
3806: for that kind of reg class, where a problem like this is normal.
3807: Perhaps those classes should be avoided for reloading
3808: by use of more alternatives. */
3809:
3810: int force_group = reload_nregs[r] > 1 && ! last_reload;
3811:
3812: /* If we want a single register and haven't yet found one,
3813: take any reg in the right class and not in use.
3814: If we want a consecutive group, here is where we look for it.
3815:
3816: We use two passes so we can first look for reload regs to
3817: reuse, which are already in use for other reloads in this insn,
3818: and only then use additional registers.
3819: I think that maximizing reuse is needed to make sure we don't
3820: run out of reload regs. Suppose we have three reloads, and
3821: reloads A and B can share regs. These need two regs.
3822: Suppose A and B are given different regs.
3823: That leaves none for C. */
3824: for (pass = 0; pass < 2; pass++)
3825: {
3826: /* I is the index in spill_regs.
3827: We advance it round-robin between insns to use all spill regs
3828: equally, so that inherited reloads have a chance
3829: of leapfrogging each other. */
3830:
3831: for (count = 0, i = last_spill_reg; count < n_spills; count++)
3832: {
3833: int class = (int) reload_reg_class[r];
3834:
3835: i = (i + 1) % n_spills;
3836:
3837: if (reload_reg_free_p (spill_regs[i], reload_when_needed[r])
3838: && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
3839: && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
3840: /* Look first for regs to share, then for unshared. */
3841: && (pass || TEST_HARD_REG_BIT (reload_reg_used_at_all,
3842: spill_regs[i])))
3843: {
3844: int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
3845: /* Avoid the problem where spilling a GENERAL_OR_FP_REG
3846: (on 68000) got us two FP regs. If NR is 1,
3847: we would reject both of them. */
3848: if (force_group)
3849: nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
3850: /* If we need only one reg, we have already won. */
3851: if (nr == 1)
3852: {
3853: /* But reject a single reg if we demand a group. */
3854: if (force_group)
3855: continue;
3856: break;
3857: }
3858: /* Otherwise check that as many consecutive regs as we need
3859: are available here.
3860: Also, don't use for a group registers that are
3861: needed for nongroups. */
3862: if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
3863: while (nr > 1)
3864: {
3865: regno = spill_regs[i] + nr - 1;
3866: if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
3867: && spill_reg_order[regno] >= 0
3868: && reload_reg_free_p (regno, reload_when_needed[r])
3869: && ! TEST_HARD_REG_BIT (counted_for_nongroups,
3870: regno)))
3871: break;
3872: nr--;
3873: }
3874: if (nr == 1)
3875: break;
3876: }
3877: }
3878:
3879: /* If we found something on pass 1, omit pass 2. */
3880: if (count < n_spills)
3881: break;
3882: }
3883:
3884: /* We should have found a spill register by now. */
3885: if (count == n_spills)
3886: {
3887: if (noerror)
3888: return 0;
3889: abort ();
3890: }
3891:
3892: last_spill_reg = i;
3893:
3894: /* Mark as in use for this insn the reload regs we use for this. */
3895: mark_reload_reg_in_use (spill_regs[i], reload_when_needed[r],
3896: reload_mode[r]);
3897:
3898: new = spill_reg_rtx[i];
3899:
3900: if (new == 0 || GET_MODE (new) != reload_mode[r])
3901: spill_reg_rtx[i] = new = gen_rtx (REG, reload_mode[r], spill_regs[i]);
3902:
3903: reload_reg_rtx[r] = new;
3904: reload_spill_index[r] = i;
3905: regno = true_regnum (new);
3906:
3907: /* Detect when the reload reg can't hold the reload mode.
3908: This used to be one `if', but Sequent compiler can't handle that. */
3909: if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
3910: {
3911: enum machine_mode test_mode = VOIDmode;
3912: if (reload_in[r])
3913: test_mode = GET_MODE (reload_in[r]);
3914: /* If reload_in[r] has VOIDmode, it means we will load it
3915: in whatever mode the reload reg has: to wit, reload_mode[r].
3916: We have already tested that for validity. */
3917: /* Aside from that, we need to test that the expressions
3918: to reload from or into have modes which are valid for this
3919: reload register. Otherwise the reload insns would be invalid. */
3920: if (! (reload_in[r] != 0 && test_mode != VOIDmode
3921: && ! HARD_REGNO_MODE_OK (regno, test_mode)))
3922: if (! (reload_out[r] != 0
3923: && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
3924: /* The reg is OK. */
3925: return 1;
3926: }
3927:
3928: /* The reg is not OK. */
3929: if (noerror)
3930: return 0;
3931:
3932: if (asm_noperands (PATTERN (insn)) < 0)
3933: /* It's the compiler's fault. */
3934: abort ();
3935:
3936: /* It's the user's fault; the operand's mode and constraint
3937: don't match. Disable this reload so we don't crash in final. */
3938: error_for_asm (insn,
3939: "`asm' operand constraint incompatible with operand size");
3940: reload_in[r] = 0;
3941: reload_out[r] = 0;
3942: reload_reg_rtx[r] = 0;
3943: reload_optional[r] = 1;
3944: reload_secondary_p[r] = 1;
3945:
3946: return 1;
3947: }
3948:
3949: /* Assign hard reg targets for the pseudo-registers we must reload
3950: into hard regs for this insn.
3951: Also output the instructions to copy them in and out of the hard regs.
3952:
3953: For machines with register classes, we are responsible for
3954: finding a reload reg in the proper class. */
3955:
3956: static void
3957: choose_reload_regs (insn, avoid_return_reg)
3958: rtx insn;
3959: /* This argument is currently ignored. */
3960: rtx avoid_return_reg;
3961: {
3962: register int i, j;
3963: int max_group_size = 1;
3964: enum reg_class group_class = NO_REGS;
3965: int inheritance;
3966:
3967: rtx save_reload_reg_rtx[MAX_RELOADS];
3968: char save_reload_inherited[MAX_RELOADS];
3969: rtx save_reload_inheritance_insn[MAX_RELOADS];
3970: rtx save_reload_override_in[MAX_RELOADS];
3971: int save_reload_spill_index[MAX_RELOADS];
3972: HARD_REG_SET save_reload_reg_used;
3973: HARD_REG_SET save_reload_reg_used_in_input_addr;
3974: HARD_REG_SET save_reload_reg_used_in_output_addr;
3975: HARD_REG_SET save_reload_reg_used_in_op_addr;
3976: HARD_REG_SET save_reload_reg_used_in_input;
3977: HARD_REG_SET save_reload_reg_used_in_output;
3978: HARD_REG_SET save_reload_reg_used_at_all;
3979:
3980: bzero (reload_inherited, MAX_RELOADS);
3981: bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
3982: bzero (reload_override_in, MAX_RELOADS * sizeof (rtx));
3983:
3984: CLEAR_HARD_REG_SET (reload_reg_used);
3985: CLEAR_HARD_REG_SET (reload_reg_used_at_all);
3986: CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr);
3987: CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr);
3988: CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
3989: CLEAR_HARD_REG_SET (reload_reg_used_in_output);
3990: CLEAR_HARD_REG_SET (reload_reg_used_in_input);
3991:
3992: /* Distinguish output-only and input-only reloads
3993: because they can overlap with other things. */
3994: for (j = 0; j < n_reloads; j++)
3995: if (reload_when_needed[j] == RELOAD_OTHER
3996: && ! reload_needed_for_multiple[j])
3997: {
3998: if (reload_in[j] == 0)
3999: {
4000: /* But earlyclobber operands must stay as RELOAD_OTHER. */
4001: for (i = 0; i < n_earlyclobbers; i++)
4002: if (rtx_equal_p (reload_out[j], reload_earlyclobbers[i]))
4003: break;
4004: if (i == n_earlyclobbers)
4005: reload_when_needed[j] = RELOAD_FOR_OUTPUT;
4006: }
4007: if (reload_out[j] == 0)
4008: reload_when_needed[j] = RELOAD_FOR_INPUT;
4009:
4010: if (reload_secondary_reload[j] >= 0
4011: && ! reload_needed_for_multiple[reload_secondary_reload[j]])
4012: reload_when_needed[reload_secondary_reload[j]]
4013: = reload_when_needed[j];
4014: }
4015:
4016: #ifdef SMALL_REGISTER_CLASSES
4017: /* Don't bother with avoiding the return reg
4018: if we have no mandatory reload that could use it. */
4019: if (avoid_return_reg)
4020: {
4021: int do_avoid = 0;
4022: int regno = REGNO (avoid_return_reg);
4023: int nregs
4024: = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4025: int r;
4026:
4027: for (r = regno; r < regno + nregs; r++)
4028: if (spill_reg_order[r] >= 0)
4029: for (j = 0; j < n_reloads; j++)
4030: if (!reload_optional[j] && reload_reg_rtx[j] == 0
4031: && (reload_in[j] != 0 || reload_out[j] != 0
4032: || reload_secondary_p[j])
4033: &&
4034: TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
4035: do_avoid = 1;
4036: if (!do_avoid)
4037: avoid_return_reg = 0;
4038: }
4039: #endif /* SMALL_REGISTER_CLASSES */
4040:
4041: #if 0 /* Not needed, now that we can always retry without inheritance. */
4042: /* See if we have more mandatory reloads than spill regs.
4043: If so, then we cannot risk optimizations that could prevent
4044: reloads from sharing one spill register.
4045:
4046: Since we will try finding a better register than reload_reg_rtx
4047: unless it is equal to reload_in or reload_out, count such reloads. */
4048:
4049: {
4050: int tem = 0;
4051: #ifdef SMALL_REGISTER_CLASSES
4052: int tem = (avoid_return_reg != 0);
4053: #endif
4054: for (j = 0; j < n_reloads; j++)
4055: if (! reload_optional[j]
4056: && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
4057: && (reload_reg_rtx[j] == 0
4058: || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
4059: && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
4060: tem++;
4061: if (tem > n_spills)
4062: must_reuse = 1;
4063: }
4064: #endif
4065:
4066: #ifdef SMALL_REGISTER_CLASSES
4067: /* Don't use the subroutine call return reg for a reload
4068: if we are supposed to avoid it. */
4069: if (avoid_return_reg)
4070: {
4071: int regno = REGNO (avoid_return_reg);
4072: int nregs
4073: = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4074: int r;
4075:
4076: for (r = regno; r < regno + nregs; r++)
4077: if (spill_reg_order[r] >= 0)
4078: SET_HARD_REG_BIT (reload_reg_used, r);
4079: }
4080: #endif /* SMALL_REGISTER_CLASSES */
4081:
4082: /* In order to be certain of getting the registers we need,
4083: we must sort the reloads into order of increasing register class.
4084: Then our grabbing of reload registers will parallel the process
4085: that provided the reload registers.
4086:
4087: Also note whether any of the reloads wants a consecutive group of regs.
4088: If so, record the maximum size of the group desired and what
4089: register class contains all the groups needed by this insn. */
4090:
4091: for (j = 0; j < n_reloads; j++)
4092: {
4093: reload_order[j] = j;
4094: reload_spill_index[j] = -1;
4095:
4096: reload_mode[j]
4097: = (reload_strict_low[j] && reload_out[j]
4098: ? GET_MODE (SUBREG_REG (reload_out[j]))
4099: : (reload_inmode[j] == VOIDmode
4100: || (GET_MODE_SIZE (reload_outmode[j])
4101: > GET_MODE_SIZE (reload_inmode[j])))
4102: ? reload_outmode[j] : reload_inmode[j]);
4103:
4104: reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
4105:
4106: if (reload_nregs[j] > 1)
4107: {
4108: max_group_size = MAX (reload_nregs[j], max_group_size);
4109: group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
4110: }
4111:
4112: /* If we have already decided to use a certain register,
4113: don't use it in another way. */
4114: if (reload_reg_rtx[j])
4115: mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]),
4116: reload_when_needed[j], reload_mode[j]);
4117: }
4118:
4119: if (n_reloads > 1)
4120: qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
4121:
4122: bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx);
4123: bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
4124: bcopy (reload_inheritance_insn, save_reload_inheritance_insn,
4125: sizeof reload_inheritance_insn);
4126: bcopy (reload_override_in, save_reload_override_in,
4127: sizeof reload_override_in);
4128: bcopy (reload_spill_index, save_reload_spill_index,
4129: sizeof reload_spill_index);
4130: COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
4131: COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
4132: COPY_HARD_REG_SET (save_reload_reg_used_in_output,
4133: reload_reg_used_in_output);
4134: COPY_HARD_REG_SET (save_reload_reg_used_in_input,
4135: reload_reg_used_in_input);
4136: COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr,
4137: reload_reg_used_in_input_addr);
4138: COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr,
4139: reload_reg_used_in_output_addr);
4140: COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
4141: reload_reg_used_in_op_addr);
4142:
4143: /* Try first with inheritance, then turning it off. */
4144:
4145: for (inheritance = 1; inheritance >= 0; inheritance--)
4146: {
4147: /* Process the reloads in order of preference just found.
4148: Beyond this point, subregs can be found in reload_reg_rtx.
4149:
4150: This used to look for an existing reloaded home for all
4151: of the reloads, and only then perform any new reloads.
4152: But that could lose if the reloads were done out of reg-class order
4153: because a later reload with a looser constraint might have an old
4154: home in a register needed by an earlier reload with a tighter constraint.
4155:
4156: To solve this, we make two passes over the reloads, in the order
4157: described above. In the first pass we try to inherit a reload
4158: from a previous insn. If there is a later reload that needs a
4159: class that is a proper subset of the class being processed, we must
4160: also allocate a spill register during the first pass.
4161:
4162: Then make a second pass over the reloads to allocate any reloads
4163: that haven't been given registers yet. */
4164:
4165: for (j = 0; j < n_reloads; j++)
4166: {
4167: register int r = reload_order[j];
4168:
4169: /* Ignore reloads that got marked inoperative. */
4170: if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4171: continue;
4172:
4173: /* If find_reloads chose a to use reload_in or reload_out as a reload
4174: register, we don't need to chose one. Otherwise, try even if it found
4175: one since we might save an insn if we find the value lying around. */
4176: if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
4177: && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
4178: || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
4179: continue;
4180:
4181: #if 0 /* No longer needed for correct operation.
4182: It might give better code, or might not; worth an experiment? */
4183: /* If this is an optional reload, we can't inherit from earlier insns
4184: until we are sure that any non-optional reloads have been allocated.
4185: The following code takes advantage of the fact that optional reloads
4186: are at the end of reload_order. */
4187: if (reload_optional[r] != 0)
4188: for (i = 0; i < j; i++)
4189: if ((reload_out[reload_order[i]] != 0
4190: || reload_in[reload_order[i]] != 0
4191: || reload_secondary_p[reload_order[i]])
4192: && ! reload_optional[reload_order[i]]
4193: && reload_reg_rtx[reload_order[i]] == 0)
4194: allocate_reload_reg (reload_order[i], insn, 0, inheritance);
4195: #endif
4196:
4197: /* First see if this pseudo is already available as reloaded
4198: for a previous insn. We cannot try to inherit for reloads
4199: that are smaller than the maximum number of registers needed
4200: for groups unless the register we would allocate cannot be used
4201: for the groups.
4202:
4203: We could check here to see if this is a secondary reload for
4204: an object that is already in a register of the desired class.
4205: This would avoid the need for the secondary reload register.
4206: But this is complex because we can't easily determine what
4207: objects might want to be loaded via this reload. So let a register
4208: be allocated here. In `emit_reload_insns' we suppress one of the
4209: loads in the case described above. */
4210:
4211: if (inheritance)
4212: {
4213: register int regno = -1;
4214:
4215: if (reload_in[r] == 0)
4216: ;
4217: else if (GET_CODE (reload_in[r]) == REG)
4218: regno = REGNO (reload_in[r]);
4219: else if (GET_CODE (reload_in_reg[r]) == REG)
4220: regno = REGNO (reload_in_reg[r]);
4221: #if 0
4222: /* This won't work, since REGNO can be a pseudo reg number.
4223: Also, it takes much more hair to keep track of all the things
4224: that can invalidate an inherited reload of part of a pseudoreg. */
4225: else if (GET_CODE (reload_in[r]) == SUBREG
4226: && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
4227: regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
4228: #endif
4229:
4230: if (regno >= 0 && reg_last_reload_reg[regno] != 0)
4231: {
4232: i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
4233:
4234: if (reg_reloaded_contents[i] == regno
4235: && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4236: && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4237: spill_regs[i])
4238: && (reload_nregs[r] == max_group_size
4239: || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
4240: spill_regs[i]))
4241: && reload_reg_free_p (spill_regs[i], reload_when_needed[r])
4242: && reload_reg_free_before_p (spill_regs[i],
4243: reload_when_needed[r]))
4244: {
4245: /* If a group is needed, verify that all the subsequent
4246: registers still have their values intact. */
4247: int nr
4248: = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4249: int k;
4250:
4251: for (k = 1; k < nr; k++)
4252: if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
4253: != regno)
4254: break;
4255:
4256: if (k == nr)
4257: {
4258: /* Mark the register as in use for this part of
4259: the insn. */
4260: mark_reload_reg_in_use (spill_regs[i],
4261: reload_when_needed[r],
4262: reload_mode[r]);
4263: reload_reg_rtx[r] = reg_last_reload_reg[regno];
4264: reload_inherited[r] = 1;
4265: reload_inheritance_insn[r] = reg_reloaded_insn[i];
4266: reload_spill_index[r] = i;
4267: }
4268: }
4269: }
4270: }
4271:
4272: /* Here's another way to see if the value is already lying around. */
4273: if (inheritance
4274: && reload_in[r] != 0
4275: && ! reload_inherited[r]
4276: && reload_out[r] == 0
4277: && (CONSTANT_P (reload_in[r])
4278: || GET_CODE (reload_in[r]) == PLUS
4279: || GET_CODE (reload_in[r]) == REG
4280: || GET_CODE (reload_in[r]) == MEM)
4281: && (reload_nregs[r] == max_group_size
4282: || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
4283: {
4284: register rtx equiv
4285: = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
4286: -1, 0, 0, reload_mode[r]);
4287: int regno;
4288:
4289: if (equiv != 0)
4290: {
4291: if (GET_CODE (equiv) == REG)
4292: regno = REGNO (equiv);
4293: else if (GET_CODE (equiv) == SUBREG)
4294: {
4295: regno = REGNO (SUBREG_REG (equiv));
4296: if (regno < FIRST_PSEUDO_REGISTER)
4297: regno += SUBREG_WORD (equiv);
4298: }
4299: else
4300: abort ();
4301: }
4302:
4303: /* If we found a spill reg, reject it unless it is free
4304: and of the desired class. */
4305: if (equiv != 0
4306: && ((spill_reg_order[regno] >= 0
4307: && ! reload_reg_free_before_p (regno,
4308: reload_when_needed[r]))
4309: || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4310: regno)))
4311: equiv = 0;
4312:
4313: if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
4314: equiv = 0;
4315:
4316: if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4317: equiv = 0;
4318:
4319: /* We found a register that contains the value we need.
4320: If this register is the same as an `earlyclobber' operand
4321: of the current insn, just mark it as a place to reload from
4322: since we can't use it as the reload register itself. */
4323:
4324: if (equiv != 0)
4325: for (i = 0; i < n_earlyclobbers; i++)
1.1.1.3 ! root 4326: if (reg_overlap_mentioned_for_reload_p (equiv,
! 4327: reload_earlyclobbers[i]))
1.1 root 4328: {
4329: reload_override_in[r] = equiv;
4330: equiv = 0;
4331: break;
4332: }
4333:
4334: /* JRV: If the equiv register we have found is explicitly
4335: clobbered in the current insn, mark but don't use, as above. */
4336:
4337: if (equiv != 0 && regno_clobbered_p (regno, insn))
4338: {
4339: reload_override_in[r] = equiv;
4340: equiv = 0;
4341: }
4342:
4343: /* If we found an equivalent reg, say no code need be generated
4344: to load it, and use it as our reload reg. */
4345: if (equiv != 0 && regno != FRAME_POINTER_REGNUM)
4346: {
4347: reload_reg_rtx[r] = equiv;
4348: reload_inherited[r] = 1;
4349: /* If it is a spill reg,
4350: mark the spill reg as in use for this insn. */
4351: i = spill_reg_order[regno];
4352: if (i >= 0)
4353: mark_reload_reg_in_use (regno, reload_when_needed[r],
4354: reload_mode[r]);
4355: }
4356: }
4357:
4358: /* If we found a register to use already, or if this is an optional
4359: reload, we are done. */
4360: if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
4361: continue;
4362:
4363: #if 0 /* No longer needed for correct operation. Might or might not
4364: give better code on the average. Want to experiment? */
4365:
4366: /* See if there is a later reload that has a class different from our
4367: class that intersects our class or that requires less register
4368: than our reload. If so, we must allocate a register to this
4369: reload now, since that reload might inherit a previous reload
4370: and take the only available register in our class. Don't do this
4371: for optional reloads since they will force all previous reloads
4372: to be allocated. Also don't do this for reloads that have been
4373: turned off. */
4374:
4375: for (i = j + 1; i < n_reloads; i++)
4376: {
4377: int s = reload_order[i];
4378:
1.1.1.2 root 4379: if ((reload_in[s] == 0 && reload_out[s] == 0
4380: && ! reload_secondary_p[s])
1.1 root 4381: || reload_optional[s])
4382: continue;
4383:
4384: if ((reload_reg_class[s] != reload_reg_class[r]
4385: && reg_classes_intersect_p (reload_reg_class[r],
4386: reload_reg_class[s]))
4387: || reload_nregs[s] < reload_nregs[r])
4388: break;
4389: }
4390:
4391: if (i == n_reloads)
4392: continue;
4393:
4394: allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
4395: #endif
4396: }
4397:
4398: /* Now allocate reload registers for anything non-optional that
4399: didn't get one yet. */
4400: for (j = 0; j < n_reloads; j++)
4401: {
4402: register int r = reload_order[j];
4403:
4404: /* Ignore reloads that got marked inoperative. */
4405: if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4406: continue;
4407:
4408: /* Skip reloads that already have a register allocated or are
4409: optional. */
4410: if (reload_reg_rtx[r] != 0 || reload_optional[r])
4411: continue;
4412:
4413: if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
4414: break;
4415: }
4416:
4417: /* If that loop got all the way, we have won. */
4418: if (j == n_reloads)
4419: break;
4420:
4421: fail:
4422: /* Loop around and try without any inheritance. */
4423: /* First undo everything done by the failed attempt
4424: to allocate with inheritance. */
4425: bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx);
4426: bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited);
4427: bcopy (save_reload_inheritance_insn, reload_inheritance_insn,
4428: sizeof reload_inheritance_insn);
4429: bcopy (save_reload_override_in, reload_override_in,
4430: sizeof reload_override_in);
4431: bcopy (save_reload_spill_index, reload_spill_index,
4432: sizeof reload_spill_index);
4433: COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
4434: COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
4435: COPY_HARD_REG_SET (reload_reg_used_in_input,
4436: save_reload_reg_used_in_input);
4437: COPY_HARD_REG_SET (reload_reg_used_in_output,
4438: save_reload_reg_used_in_output);
4439: COPY_HARD_REG_SET (reload_reg_used_in_input_addr,
4440: save_reload_reg_used_in_input_addr);
4441: COPY_HARD_REG_SET (reload_reg_used_in_output_addr,
4442: save_reload_reg_used_in_output_addr);
4443: COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
4444: save_reload_reg_used_in_op_addr);
4445: }
4446:
4447: /* If we thought we could inherit a reload, because it seemed that
4448: nothing else wanted the same reload register earlier in the insn,
4449: verify that assumption, now that all reloads have been assigned. */
4450:
4451: for (j = 0; j < n_reloads; j++)
4452: {
4453: register int r = reload_order[j];
4454:
4455: if (reload_inherited[r] && reload_reg_rtx[r] != 0
4456: && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
4457: reload_when_needed[r]))
4458: reload_inherited[r] = 0;
4459:
4460: /* If we found a better place to reload from,
4461: validate it in the same fashion, if it is a reload reg. */
4462: if (reload_override_in[r]
4463: && (GET_CODE (reload_override_in[r]) == REG
4464: || GET_CODE (reload_override_in[r]) == SUBREG))
4465: {
4466: int regno = true_regnum (reload_override_in[r]);
4467: if (spill_reg_order[regno] >= 0
4468: && ! reload_reg_free_before_p (regno, reload_when_needed[r]))
4469: reload_override_in[r] = 0;
4470: }
4471: }
4472:
4473: /* Now that reload_override_in is known valid,
4474: actually override reload_in. */
4475: for (j = 0; j < n_reloads; j++)
4476: if (reload_override_in[j])
4477: reload_in[j] = reload_override_in[j];
4478:
4479: /* If this reload won't be done because it has been cancelled or is
4480: optional and not inherited, clear reload_reg_rtx so other
4481: routines (such as subst_reloads) don't get confused. */
4482: for (j = 0; j < n_reloads; j++)
4483: if ((reload_optional[j] && ! reload_inherited[j])
4484: || (reload_in[j] == 0 && reload_out[j] == 0
4485: && ! reload_secondary_p[j]))
4486: reload_reg_rtx[j] = 0;
4487:
4488: /* Record which pseudos and which spill regs have output reloads. */
4489: for (j = 0; j < n_reloads; j++)
4490: {
4491: register int r = reload_order[j];
4492:
4493: i = reload_spill_index[r];
4494:
4495: /* I is nonneg if this reload used one of the spill regs.
4496: If reload_reg_rtx[r] is 0, this is an optional reload
4497: that we opted to ignore. */
4498: if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
4499: && reload_reg_rtx[r] != 0)
4500: {
4501: register int nregno = REGNO (reload_out[r]);
4502: int nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
4503:
4504: while (--nr >= 0)
4505: {
4506: reg_has_output_reload[nregno + nr] = 1;
4507: if (i >= 0)
4508: SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
4509: }
4510:
4511: if (reload_when_needed[r] != RELOAD_OTHER
4512: && reload_when_needed[r] != RELOAD_FOR_OUTPUT)
4513: abort ();
4514: }
4515: }
4516: }
4517:
4518: /* Output insns to reload values in and out of the chosen reload regs. */
4519:
4520: static void
4521: emit_reload_insns (insn)
4522: rtx insn;
4523: {
4524: register int j;
4525: rtx following_insn = NEXT_INSN (insn);
4526: rtx before_insn = insn;
4527: rtx first_output_reload_insn = NEXT_INSN (insn);
4528: rtx first_other_reload_insn = insn;
4529: rtx first_operand_address_reload_insn = insn;
4530: int special;
4531: /* Values to be put in spill_reg_store are put here first. */
4532: rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
4533:
1.1.1.2 root 4534: /* If this is a CALL_INSN preceded by USE insns, any reload insns
1.1 root 4535: must go in front of the first USE insn, not in front of INSN. */
4536:
4537: if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN
4538: && GET_CODE (PATTERN (PREV_INSN (insn))) == USE)
4539: while (GET_CODE (PREV_INSN (before_insn)) == INSN
4540: && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE)
4541: first_other_reload_insn = first_operand_address_reload_insn
4542: = before_insn = PREV_INSN (before_insn);
4543:
4544: /* Now output the instructions to copy the data into and out of the
4545: reload registers. Do these in the order that the reloads were reported,
4546: since reloads of base and index registers precede reloads of operands
4547: and the operands may need the base and index registers reloaded. */
4548:
4549: for (j = 0; j < n_reloads; j++)
4550: {
4551: register rtx old;
4552: rtx oldequiv_reg = 0;
4553: rtx this_reload_insn = 0;
4554: rtx store_insn = 0;
4555:
4556: old = reload_in[j];
4557: if (old != 0 && ! reload_inherited[j]
4558: && ! rtx_equal_p (reload_reg_rtx[j], old)
4559: && reload_reg_rtx[j] != 0)
4560: {
4561: register rtx reloadreg = reload_reg_rtx[j];
4562: rtx oldequiv = 0;
4563: enum machine_mode mode;
4564: rtx where;
4565: rtx reload_insn;
4566:
4567: /* Determine the mode to reload in.
4568: This is very tricky because we have three to choose from.
4569: There is the mode the insn operand wants (reload_inmode[J]).
4570: There is the mode of the reload register RELOADREG.
4571: There is the intrinsic mode of the operand, which we could find
4572: by stripping some SUBREGs.
4573: It turns out that RELOADREG's mode is irrelevant:
4574: we can change that arbitrarily.
4575:
4576: Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
4577: then the reload reg may not support QImode moves, so use SImode.
4578: If foo is in memory due to spilling a pseudo reg, this is safe,
4579: because the QImode value is in the least significant part of a
4580: slot big enough for a SImode. If foo is some other sort of
4581: memory reference, then it is impossible to reload this case,
4582: so previous passes had better make sure this never happens.
4583:
4584: Then consider a one-word union which has SImode and one of its
4585: members is a float, being fetched as (SUBREG:SF union:SI).
4586: We must fetch that as SFmode because we could be loading into
4587: a float-only register. In this case OLD's mode is correct.
4588:
4589: Consider an immediate integer: it has VOIDmode. Here we need
4590: to get a mode from something else.
4591:
4592: In some cases, there is a fourth mode, the operand's
4593: containing mode. If the insn specifies a containing mode for
4594: this operand, it overrides all others.
4595:
4596: I am not sure whether the algorithm here is always right,
4597: but it does the right things in those cases. */
4598:
4599: mode = GET_MODE (old);
4600: if (mode == VOIDmode)
4601: mode = reload_inmode[j];
4602: if (reload_strict_low[j])
4603: mode = GET_MODE (SUBREG_REG (reload_in[j]));
4604:
4605: #ifdef SECONDARY_INPUT_RELOAD_CLASS
4606: /* If we need a secondary register for this operation, see if
4607: the value is already in a register in that class. Don't
4608: do this if the secondary register will be used as a scratch
4609: register. */
4610:
4611: if (reload_secondary_reload[j] >= 0
4612: && reload_secondary_icode[j] == CODE_FOR_nothing)
4613: oldequiv
4614: = find_equiv_reg (old, insn,
4615: reload_reg_class[reload_secondary_reload[j]],
4616: -1, 0, 0, mode);
4617: #endif
4618:
4619: /* If reloading from memory, see if there is a register
4620: that already holds the same value. If so, reload from there.
4621: We can pass 0 as the reload_reg_p argument because
4622: any other reload has either already been emitted,
4623: in which case find_equiv_reg will see the reload-insn,
4624: or has yet to be emitted, in which case it doesn't matter
4625: because we will use this equiv reg right away. */
4626:
4627: if (oldequiv == 0
4628: && (GET_CODE (old) == MEM
4629: || (GET_CODE (old) == REG
4630: && REGNO (old) >= FIRST_PSEUDO_REGISTER
4631: && reg_renumber[REGNO (old)] < 0)))
4632: oldequiv = find_equiv_reg (old, insn, GENERAL_REGS,
4633: -1, 0, 0, mode);
4634:
4635: if (oldequiv)
4636: {
4637: int regno = true_regnum (oldequiv);
4638:
4639: /* If OLDEQUIV is a spill register, don't use it for this
4640: if any other reload needs it at an earlier stage of this insn
4641: or at this stage. */
4642: if (spill_reg_order[regno] >= 0
4643: && (! reload_reg_free_p (regno, reload_when_needed[j])
4644: || ! reload_reg_free_before_p (regno,
4645: reload_when_needed[j])))
4646: oldequiv = 0;
4647:
4648: /* If OLDEQUIV is not a spill register,
4649: don't use it if any other reload wants it. */
4650: if (spill_reg_order[regno] < 0)
4651: {
4652: int k;
4653: for (k = 0; k < n_reloads; k++)
4654: if (reload_reg_rtx[k] != 0 && k != j
1.1.1.3 ! root 4655: && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
! 4656: oldequiv))
1.1 root 4657: {
4658: oldequiv = 0;
4659: break;
4660: }
4661: }
4662: }
4663:
4664: if (oldequiv == 0)
4665: oldequiv = old;
4666: else if (GET_CODE (oldequiv) == REG)
4667: oldequiv_reg = oldequiv;
4668: else if (GET_CODE (oldequiv) == SUBREG)
4669: oldequiv_reg = SUBREG_REG (oldequiv);
4670:
4671: /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
4672: then load RELOADREG from OLDEQUIV. */
4673:
4674: if (GET_MODE (reloadreg) != mode)
4675: reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
4676: while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
4677: oldequiv = SUBREG_REG (oldequiv);
4678: if (GET_MODE (oldequiv) != VOIDmode
4679: && mode != GET_MODE (oldequiv))
4680: oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
4681:
4682: /* Decide where to put reload insn for this reload. */
4683: switch (reload_when_needed[j])
4684: {
4685: case RELOAD_FOR_INPUT:
4686: case RELOAD_OTHER:
4687: where = first_operand_address_reload_insn;
4688: break;
4689: case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
4690: where = first_other_reload_insn;
4691: break;
4692: case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
4693: where = first_output_reload_insn;
4694: break;
4695: case RELOAD_FOR_OPERAND_ADDRESS:
4696: where = before_insn;
4697: }
4698:
4699: special = 0;
4700:
4701: /* Auto-increment addresses must be reloaded in a special way. */
4702: if (GET_CODE (oldequiv) == POST_INC
4703: || GET_CODE (oldequiv) == POST_DEC
4704: || GET_CODE (oldequiv) == PRE_INC
4705: || GET_CODE (oldequiv) == PRE_DEC)
4706: {
4707: /* We are not going to bother supporting the case where a
4708: incremented register can't be copied directly from
4709: OLDEQUIV since this seems highly unlikely. */
4710: if (reload_secondary_reload[j] >= 0)
4711: abort ();
4712: /* Prevent normal processing of this reload. */
4713: special = 1;
4714: /* Output a special code sequence for this case. */
4715: this_reload_insn
4716: = inc_for_reload (reloadreg, oldequiv, reload_inc[j], where);
4717: }
4718:
4719: /* If we are reloading a pseudo-register that was set by the previous
4720: insn, see if we can get rid of that pseudo-register entirely
4721: by redirecting the previous insn into our reload register. */
4722:
4723: else if (optimize && GET_CODE (old) == REG
4724: && REGNO (old) >= FIRST_PSEUDO_REGISTER
4725: && dead_or_set_p (insn, old)
4726: /* This is unsafe if some other reload
4727: uses the same reg first. */
4728: && (reload_when_needed[j] == RELOAD_OTHER
4729: || reload_when_needed[j] == RELOAD_FOR_INPUT
4730: || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS))
4731: {
4732: rtx temp = PREV_INSN (insn);
4733: while (temp && GET_CODE (temp) == NOTE)
4734: temp = PREV_INSN (temp);
4735: if (temp
4736: && GET_CODE (temp) == INSN
4737: && GET_CODE (PATTERN (temp)) == SET
4738: && SET_DEST (PATTERN (temp)) == old
4739: /* Make sure we can access insn_operand_constraint. */
4740: && asm_noperands (PATTERN (temp)) < 0
4741: /* This is unsafe if prev insn rejects our reload reg. */
4742: && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
4743: reloadreg)
4744: /* This is unsafe if operand occurs more than once in current
4745: insn. Perhaps some occurrences aren't reloaded. */
4746: && count_occurrences (PATTERN (insn), old) == 1
4747: /* Don't risk splitting a matching pair of operands. */
4748: && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
4749: {
4750: /* Store into the reload register instead of the pseudo. */
4751: SET_DEST (PATTERN (temp)) = reloadreg;
4752: /* If these are the only uses of the pseudo reg,
4753: pretend for GDB it lives in the reload reg we used. */
4754: if (reg_n_deaths[REGNO (old)] == 1
4755: && reg_n_sets[REGNO (old)] == 1)
4756: {
4757: reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
4758: alter_reg (REGNO (old), -1);
4759: }
4760: special = 1;
4761: }
4762: }
4763:
4764: /* We can't do that, so output an insn to load RELOADREG.
4765: Keep them in the following order:
4766: all reloads for input reload addresses,
4767: all reloads for ordinary input operands,
4768: all reloads for addresses of non-reloaded operands,
4769: the insn being reloaded,
4770: all reloads for addresses of output reloads,
4771: the output reloads. */
4772: if (! special)
4773: {
4774: #ifdef SECONDARY_INPUT_RELOAD_CLASS
4775: rtx second_reload_reg = 0;
4776: enum insn_code icode;
4777:
4778: /* If we have a secondary reload, pick up the secondary register
4779: and icode, if any. If OLDEQUIV and OLD are different or
4780: if this is an in-out reload, recompute whether or not we
4781: still need a secondary register and what the icode should
4782: be. If we still need a secondary register and the class or
4783: icode is different, go back to reloading from OLD if using
4784: OLDEQUIV means that we got the wrong type of register. We
4785: cannot have different class or icode due to an in-out reload
4786: because we don't make such reloads when both the input and
4787: output need secondary reload registers. */
4788:
4789: if (reload_secondary_reload[j] >= 0)
4790: {
4791: int secondary_reload = reload_secondary_reload[j];
1.1.1.2 root 4792: rtx real_oldequiv = oldequiv;
4793: rtx real_old = old;
4794:
4795: /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
4796: and similarly for OLD.
4797: See comments in find_secondary_reload in reload.c. */
4798: if (GET_CODE (oldequiv) == REG
4799: && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
4800: && reg_equiv_mem[REGNO (oldequiv)] != 0)
4801: real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
4802:
4803: if (GET_CODE (old) == REG
4804: && REGNO (old) >= FIRST_PSEUDO_REGISTER
4805: && reg_equiv_mem[REGNO (old)] != 0)
4806: real_old = reg_equiv_mem[REGNO (old)];
4807:
1.1 root 4808: second_reload_reg = reload_reg_rtx[secondary_reload];
4809: icode = reload_secondary_icode[j];
4810:
4811: if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
4812: || (reload_in[j] != 0 && reload_out[j] != 0))
4813: {
4814: enum reg_class new_class
4815: = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
1.1.1.2 root 4816: mode, real_oldequiv);
1.1 root 4817:
4818: if (new_class == NO_REGS)
4819: second_reload_reg = 0;
4820: else
4821: {
4822: enum insn_code new_icode;
4823: enum machine_mode new_mode;
4824:
4825: if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
4826: REGNO (second_reload_reg)))
1.1.1.2 root 4827: oldequiv = old, real_oldequiv = real_old;
1.1 root 4828: else
4829: {
4830: new_icode = reload_in_optab[(int) mode];
4831: if (new_icode != CODE_FOR_nothing
4832: && ((insn_operand_predicate[(int) new_icode][0]
4833: && ! ((*insn_operand_predicate[(int) new_icode][0])
4834: (reloadreg, mode)))
4835: || (insn_operand_predicate[(int) new_icode][1]
4836: && ! ((*insn_operand_predicate[(int) new_icode][1])
1.1.1.2 root 4837: (real_oldequiv, mode)))))
1.1 root 4838: new_icode = CODE_FOR_nothing;
4839:
4840: if (new_icode == CODE_FOR_nothing)
4841: new_mode = mode;
4842: else
4843: new_mode = insn_operand_mode[new_icode][2];
4844:
4845: if (GET_MODE (second_reload_reg) != new_mode)
4846: {
4847: if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
4848: new_mode))
1.1.1.2 root 4849: oldequiv = old, real_oldequiv = real_old;
1.1 root 4850: else
4851: second_reload_reg
4852: = gen_reg_rtx (REG, new_mode,
4853: REGNO (second_reload_reg));
4854: }
4855: }
4856: }
4857: }
4858:
4859: /* If we still need a secondary reload register, check
4860: to see if it is being used as a scratch or intermediate
1.1.1.2 root 4861: register and generate code appropriately. If we need
4862: a scratch register, use REAL_OLDEQUIV since the form of
4863: the insn may depend on the actual address if it is
4864: a MEM. */
1.1 root 4865:
4866: if (second_reload_reg)
4867: {
4868: if (icode != CODE_FOR_nothing)
4869: {
4870: reload_insn = emit_insn_before (GEN_FCN (icode)
1.1.1.2 root 4871: (reloadreg,
4872: real_oldequiv,
1.1 root 4873: second_reload_reg),
4874: where);
4875: if (this_reload_insn == 0)
4876: this_reload_insn = reload_insn;
4877: special = 1;
4878: }
4879: else
4880: {
4881: /* See if we need a scratch register to load the
4882: intermediate register (a tertiary reload). */
4883: enum insn_code tertiary_icode
4884: = reload_secondary_icode[secondary_reload];
4885:
4886: if (tertiary_icode != CODE_FOR_nothing)
4887: {
4888: rtx third_reload_reg
4889: = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
4890:
4891: reload_insn
4892: = emit_insn_before ((GEN_FCN (tertiary_icode)
4893: (second_reload_reg,
1.1.1.2 root 4894: real_oldequiv,
1.1 root 4895: third_reload_reg)),
4896: where);
4897: if (this_reload_insn == 0)
4898: this_reload_insn = reload_insn;
4899: }
4900: else
4901: {
4902: reload_insn
4903: = gen_input_reload (second_reload_reg,
4904: oldequiv, where);
4905: if (this_reload_insn == 0)
4906: this_reload_insn = reload_insn;
4907: oldequiv = second_reload_reg;
4908: }
4909: }
4910: }
4911: }
4912: #endif
4913:
4914: if (! special)
4915: {
1.1.1.3 ! root 4916: reload_insn = gen_input_reload (reloadreg, oldequiv, where);
1.1 root 4917: if (this_reload_insn == 0)
4918: this_reload_insn = reload_insn;
4919: }
4920:
4921: #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
4922: /* We may have to make a REG_DEAD note for the secondary reload
4923: register in the insns we just made. Find the last insn that
4924: mentioned the register. */
4925: if (! special && second_reload_reg
4926: && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
4927: {
4928: rtx prev;
4929:
4930: for (prev = where;
4931: prev != PREV_INSN (this_reload_insn);
4932: prev = PREV_INSN (prev))
4933: if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
1.1.1.3 ! root 4934: && reg_overlap_mentioned_for_reload_p (second_reload_reg,
! 4935: PATTERN (prev)))
1.1 root 4936: {
4937: REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
4938: second_reload_reg,
4939: REG_NOTES (prev));
4940: break;
4941: }
4942: }
4943: #endif
4944: }
4945:
4946: /* Update where to put other reload insns. */
4947: if (this_reload_insn)
4948: switch (reload_when_needed[j])
4949: {
4950: case RELOAD_FOR_INPUT:
4951: case RELOAD_OTHER:
4952: if (first_other_reload_insn == first_operand_address_reload_insn)
4953: first_other_reload_insn = this_reload_insn;
4954: break;
4955: case RELOAD_FOR_OPERAND_ADDRESS:
4956: if (first_operand_address_reload_insn == before_insn)
4957: first_operand_address_reload_insn = this_reload_insn;
4958: if (first_other_reload_insn == before_insn)
4959: first_other_reload_insn = this_reload_insn;
4960: }
4961:
4962: /* reload_inc[j] was formerly processed here. */
4963: }
4964:
4965: /* Add a note saying the input reload reg
4966: dies in this insn, if anyone cares. */
4967: #ifdef PRESERVE_DEATH_INFO_REGNO_P
4968: if (old != 0
4969: && reload_reg_rtx[j] != old
4970: && reload_reg_rtx[j] != 0
4971: && reload_out[j] == 0
4972: && ! reload_inherited[j]
4973: && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
4974: {
4975: register rtx reloadreg = reload_reg_rtx[j];
4976:
4977: #if 0
4978: /* We can't abort here because we need to support this for sched.c.
4979: It's not terrible to miss a REG_DEAD note, but we should try
4980: to figure out how to do this correctly. */
4981: /* The code below is incorrect for address-only reloads. */
4982: if (reload_when_needed[j] != RELOAD_OTHER
4983: && reload_when_needed[j] != RELOAD_FOR_INPUT)
4984: abort ();
4985: #endif
4986:
4987: /* Add a death note to this insn, for an input reload. */
4988:
4989: if ((reload_when_needed[j] == RELOAD_OTHER
4990: || reload_when_needed[j] == RELOAD_FOR_INPUT)
4991: && ! dead_or_set_p (insn, reloadreg))
4992: REG_NOTES (insn)
4993: = gen_rtx (EXPR_LIST, REG_DEAD,
4994: reloadreg, REG_NOTES (insn));
4995: }
4996:
4997: /* When we inherit a reload, the last marked death of the reload reg
4998: may no longer really be a death. */
4999: if (reload_reg_rtx[j] != 0
5000: && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
5001: && reload_inherited[j])
5002: {
5003: /* Handle inheriting an output reload.
5004: Remove the death note from the output reload insn. */
5005: if (reload_spill_index[j] >= 0
5006: && GET_CODE (reload_in[j]) == REG
5007: && spill_reg_store[reload_spill_index[j]] != 0
5008: && find_regno_note (spill_reg_store[reload_spill_index[j]],
5009: REG_DEAD, REGNO (reload_reg_rtx[j])))
5010: remove_death (REGNO (reload_reg_rtx[j]),
5011: spill_reg_store[reload_spill_index[j]]);
5012: /* Likewise for input reloads that were inherited. */
5013: else if (reload_spill_index[j] >= 0
5014: && GET_CODE (reload_in[j]) == REG
5015: && spill_reg_store[reload_spill_index[j]] == 0
5016: && reload_inheritance_insn[j] != 0
5017: && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
5018: REGNO (reload_reg_rtx[j])))
5019: remove_death (REGNO (reload_reg_rtx[j]),
5020: reload_inheritance_insn[j]);
5021: else
5022: {
5023: rtx prev;
5024:
5025: /* We got this register from find_equiv_reg.
5026: Search back for its last death note and get rid of it.
5027: But don't search back too far.
5028: Don't go past a place where this reg is set,
5029: since a death note before that remains valid. */
5030: for (prev = PREV_INSN (insn);
5031: prev && GET_CODE (prev) != CODE_LABEL;
5032: prev = PREV_INSN (prev))
5033: if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5034: && dead_or_set_p (prev, reload_reg_rtx[j]))
5035: {
5036: if (find_regno_note (prev, REG_DEAD,
5037: REGNO (reload_reg_rtx[j])))
5038: remove_death (REGNO (reload_reg_rtx[j]), prev);
5039: break;
5040: }
5041: }
5042: }
5043:
5044: /* We might have used find_equiv_reg above to choose an alternate
5045: place from which to reload. If so, and it died, we need to remove
5046: that death and move it to one of the insns we just made. */
5047:
5048: if (oldequiv_reg != 0
5049: && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
5050: {
5051: rtx prev, prev1;
5052:
5053: for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
5054: prev = PREV_INSN (prev))
5055: if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5056: && dead_or_set_p (prev, oldequiv_reg))
5057: {
5058: if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
5059: {
5060: for (prev1 = this_reload_insn;
5061: prev1; prev1 = PREV_INSN (prev1))
5062: if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
1.1.1.3 ! root 5063: && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
! 5064: PATTERN (prev1)))
1.1 root 5065: {
5066: REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
5067: oldequiv_reg,
5068: REG_NOTES (prev1));
5069: break;
5070: }
5071: remove_death (REGNO (oldequiv_reg), prev);
5072: }
5073: break;
5074: }
5075: }
5076: #endif
5077:
5078: /* If we are reloading a register that was recently stored in with an
5079: output-reload, see if we can prove there was
5080: actually no need to store the old value in it. */
5081:
5082: if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
5083: /* This is unsafe if some other reload uses the same reg first. */
5084: && (reload_when_needed[j] == RELOAD_OTHER
5085: || reload_when_needed[j] == RELOAD_FOR_INPUT
5086: || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS)
5087: && GET_CODE (reload_in[j]) == REG
5088: #if 0
5089: /* There doesn't seem to be any reason to restrict this to pseudos
5090: and doing so loses in the case where we are copying from a
5091: register of the wrong class. */
5092: && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
5093: #endif
5094: && spill_reg_store[reload_spill_index[j]] != 0
5095: && dead_or_set_p (insn, reload_in[j])
5096: /* This is unsafe if operand occurs more than once in current
5097: insn. Perhaps some occurrences weren't reloaded. */
5098: && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5099: delete_output_reload (insn, j,
5100: spill_reg_store[reload_spill_index[j]]);
5101:
5102: /* Input-reloading is done. Now do output-reloading,
5103: storing the value from the reload-register after the main insn
5104: if reload_out[j] is nonzero.
5105:
5106: ??? At some point we need to support handling output reloads of
5107: JUMP_INSNs or insns that set cc0. */
5108: old = reload_out[j];
5109: if (old != 0
5110: && reload_reg_rtx[j] != old
5111: && reload_reg_rtx[j] != 0)
5112: {
5113: register rtx reloadreg = reload_reg_rtx[j];
5114: register rtx second_reloadreg = 0;
5115: rtx prev_insn = PREV_INSN (first_output_reload_insn);
5116: rtx note, p;
5117: enum machine_mode mode;
5118: int special = 0;
5119:
5120: /* An output operand that dies right away does need a reload,
5121: but need not be copied from it. Show the new location in the
5122: REG_UNUSED note. */
5123: if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
5124: && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
5125: {
5126: XEXP (note, 0) = reload_reg_rtx[j];
5127: continue;
5128: }
5129: else if (GET_CODE (old) == SCRATCH)
5130: /* If we aren't optimizing, there won't be a REG_UNUSED note,
5131: but we don't want to make an output reload. */
5132: continue;
5133:
5134: #if 0
5135: /* Strip off of OLD any size-increasing SUBREGs such as
5136: (SUBREG:SI foo:QI 0). */
5137:
5138: while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
5139: && (GET_MODE_SIZE (GET_MODE (old))
5140: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
5141: old = SUBREG_REG (old);
5142: #endif
5143:
5144: /* If is a JUMP_INSN, we can't support output reloads yet. */
5145: if (GET_CODE (insn) == JUMP_INSN)
5146: abort ();
5147:
5148: /* Determine the mode to reload in.
5149: See comments above (for input reloading). */
5150:
5151: mode = GET_MODE (old);
5152: if (mode == VOIDmode)
5153: abort (); /* Should never happen for an output. */
5154:
5155: /* A strict-low-part output operand needs to be reloaded
5156: in the mode of the entire value. */
5157: if (reload_strict_low[j])
5158: {
5159: mode = GET_MODE (SUBREG_REG (reload_out[j]));
5160: /* Encapsulate OLD into that mode. */
5161: /* If OLD is a subreg, then strip it, since the subreg will
5162: be altered by this very reload. */
5163: while (GET_CODE (old) == SUBREG && GET_MODE (old) != mode)
5164: old = SUBREG_REG (old);
5165: if (GET_MODE (old) != VOIDmode
5166: && mode != GET_MODE (old))
5167: old = gen_rtx (SUBREG, mode, old, 0);
5168: }
5169:
5170: if (GET_MODE (reloadreg) != mode)
5171: reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5172:
5173: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5174:
5175: /* If we need two reload regs, set RELOADREG to the intermediate
5176: one, since it will be stored into OUT. We might need a secondary
5177: register only for an input reload, so check again here. */
5178:
1.1.1.2 root 5179: if (reload_secondary_reload[j] >= 0)
1.1 root 5180: {
1.1.1.2 root 5181: rtx real_old = old;
1.1 root 5182:
1.1.1.2 root 5183: if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
5184: && reg_equiv_mem[REGNO (old)] != 0)
5185: real_old = reg_equiv_mem[REGNO (old)];
1.1 root 5186:
1.1.1.2 root 5187: if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
5188: mode, real_old)
5189: != NO_REGS))
5190: {
5191: second_reloadreg = reloadreg;
5192: reloadreg = reload_reg_rtx[reload_secondary_reload[j]];
1.1 root 5193:
1.1.1.2 root 5194: /* See if RELOADREG is to be used as a scratch register
5195: or as an intermediate register. */
5196: if (reload_secondary_icode[j] != CODE_FOR_nothing)
1.1 root 5197: {
1.1.1.2 root 5198: emit_insn_before ((GEN_FCN (reload_secondary_icode[j])
5199: (real_old, second_reloadreg,
5200: reloadreg)),
5201: first_output_reload_insn);
5202: special = 1;
1.1 root 5203: }
5204: else
1.1.1.2 root 5205: {
5206: /* See if we need both a scratch and intermediate reload
5207: register. */
5208: int secondary_reload = reload_secondary_reload[j];
5209: enum insn_code tertiary_icode
5210: = reload_secondary_icode[secondary_reload];
5211: rtx pat;
5212:
5213: if (GET_MODE (reloadreg) != mode)
5214: reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
1.1 root 5215:
1.1.1.2 root 5216: if (tertiary_icode != CODE_FOR_nothing)
5217: {
5218: rtx third_reloadreg
5219: = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5220: pat = (GEN_FCN (tertiary_icode)
5221: (reloadreg, second_reloadreg, third_reloadreg));
5222: }
5223: else
5224: pat = gen_move_insn (reloadreg, second_reloadreg);
5225:
5226: emit_insn_before (pat, first_output_reload_insn);
5227: }
1.1 root 5228: }
5229: }
5230: #endif
5231:
5232: /* Output the last reload insn. */
5233: if (! special)
5234: emit_insn_before (gen_move_insn (old, reloadreg),
5235: first_output_reload_insn);
5236:
5237: #ifdef PRESERVE_DEATH_INFO_REGNO_P
5238: /* If final will look at death notes for this reg,
5239: put one on the last output-reload insn to use it. Similarly
5240: for any secondary register. */
5241: if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
5242: for (p = PREV_INSN (first_output_reload_insn);
5243: p != prev_insn; p = PREV_INSN (p))
5244: if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1.1.1.3 ! root 5245: && reg_overlap_mentioned_for_reload_p (reloadreg,
! 5246: PATTERN (p)))
1.1 root 5247: REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5248: reloadreg, REG_NOTES (p));
5249:
5250: #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5251: if (! special
5252: && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
5253: for (p = PREV_INSN (first_output_reload_insn);
5254: p != prev_insn; p = PREV_INSN (p))
5255: if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1.1.1.3 ! root 5256: && reg_overlap_mentioned_for_reload_p (second_reloadreg,
! 5257: PATTERN (p)))
1.1 root 5258: REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5259: second_reloadreg, REG_NOTES (p));
5260: #endif
5261: #endif
5262: /* Look at all insns we emitted, just to be safe. */
5263: for (p = NEXT_INSN (prev_insn); p != first_output_reload_insn;
5264: p = NEXT_INSN (p))
5265: if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
5266: {
5267: /* If this output reload doesn't come from a spill reg,
5268: clear any memory of reloaded copies of the pseudo reg.
5269: If this output reload comes from a spill reg,
5270: reg_has_output_reload will make this do nothing. */
5271: note_stores (PATTERN (p), forget_old_reloads_1);
5272:
5273: if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p)))
5274: store_insn = p;
5275: }
5276:
5277: first_output_reload_insn = NEXT_INSN (prev_insn);
5278: }
5279:
5280: if (reload_spill_index[j] >= 0)
5281: new_spill_reg_store[reload_spill_index[j]] = store_insn;
5282: }
5283:
5284: /* Move death notes from INSN
5285: to output-operand-address and output reload insns. */
5286: #ifdef PRESERVE_DEATH_INFO_REGNO_P
5287: {
5288: rtx insn1;
5289: /* Loop over those insns, last ones first. */
5290: for (insn1 = PREV_INSN (following_insn); insn1 != insn;
5291: insn1 = PREV_INSN (insn1))
5292: if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
5293: {
5294: rtx source = SET_SRC (PATTERN (insn1));
5295: rtx dest = SET_DEST (PATTERN (insn1));
5296:
5297: /* The note we will examine next. */
5298: rtx reg_notes = REG_NOTES (insn);
5299: /* The place that pointed to this note. */
5300: rtx *prev_reg_note = ®_NOTES (insn);
5301:
5302: /* If the note is for something used in the source of this
5303: reload insn, or in the output address, move the note. */
5304: while (reg_notes)
5305: {
5306: rtx next_reg_notes = XEXP (reg_notes, 1);
5307: if (REG_NOTE_KIND (reg_notes) == REG_DEAD
5308: && GET_CODE (XEXP (reg_notes, 0)) == REG
5309: && ((GET_CODE (dest) != REG
1.1.1.3 ! root 5310: && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
! 5311: dest))
! 5312: || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
! 5313: source)))
1.1 root 5314: {
5315: *prev_reg_note = next_reg_notes;
5316: XEXP (reg_notes, 1) = REG_NOTES (insn1);
5317: REG_NOTES (insn1) = reg_notes;
5318: }
5319: else
5320: prev_reg_note = &XEXP (reg_notes, 1);
5321:
5322: reg_notes = next_reg_notes;
5323: }
5324: }
5325: }
5326: #endif
5327:
5328: /* For all the spill regs newly reloaded in this instruction,
5329: record what they were reloaded from, so subsequent instructions
5330: can inherit the reloads.
5331:
5332: Update spill_reg_store for the reloads of this insn.
5333: Copy the elements that were updated in the loop above. */
5334:
5335: for (j = 0; j < n_reloads; j++)
5336: {
5337: register int r = reload_order[j];
5338: register int i = reload_spill_index[r];
5339:
5340: /* I is nonneg if this reload used one of the spill regs.
5341: If reload_reg_rtx[r] is 0, this is an optional reload
5342: that we opted to ignore. */
5343:
5344: if (i >= 0 && reload_reg_rtx[r] != 0)
5345: {
5346: /* First, clear out memory of what used to be in this spill reg.
5347: If consecutive registers are used, clear them all. */
5348: int nr
5349: = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
5350: int k;
5351:
5352: for (k = 0; k < nr; k++)
5353: {
5354: reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
5355: reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
5356: }
5357:
5358: /* Maybe the spill reg contains a copy of reload_out. */
5359: if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
5360: {
5361: register int nregno = REGNO (reload_out[r]);
5362:
5363: spill_reg_store[i] = new_spill_reg_store[i];
5364: reg_last_reload_reg[nregno] = reload_reg_rtx[r];
5365:
5366: for (k = 0; k < nr; k++)
5367: {
5368: reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5369: = nregno;
5370: reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
5371: }
5372: }
5373:
5374: /* Maybe the spill reg contains a copy of reload_in. */
5375: else if (reload_out[r] == 0
5376: && reload_in[r] != 0
5377: && (GET_CODE (reload_in[r]) == REG
5378: || GET_CODE (reload_in_reg[r]) == REG))
5379: {
5380: register int nregno;
5381: if (GET_CODE (reload_in[r]) == REG)
5382: nregno = REGNO (reload_in[r]);
5383: else
5384: nregno = REGNO (reload_in_reg[r]);
5385:
5386: /* If there are two separate reloads (one in and one out)
5387: for the same (hard or pseudo) reg,
5388: leave reg_last_reload_reg set
5389: based on the output reload.
5390: Otherwise, set it from this input reload. */
5391: if (!reg_has_output_reload[nregno]
5392: /* But don't do so if another input reload
5393: will clobber this one's value. */
5394: && reload_reg_reaches_end_p (spill_regs[i],
5395: reload_when_needed[r]))
5396: {
5397: reg_last_reload_reg[nregno] = reload_reg_rtx[r];
5398:
5399: /* Unless we inherited this reload, show we haven't
5400: recently done a store. */
5401: if (! reload_inherited[r])
5402: spill_reg_store[i] = 0;
5403:
5404: for (k = 0; k < nr; k++)
5405: {
5406: reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5407: = nregno;
5408: reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
5409: = insn;
5410: }
5411: }
5412: }
5413: }
5414:
5415: /* The following if-statement was #if 0'd in 1.34 (or before...).
5416: It's reenabled in 1.35 because supposedly nothing else
5417: deals with this problem. */
5418:
5419: /* If a register gets output-reloaded from a non-spill register,
5420: that invalidates any previous reloaded copy of it.
5421: But forget_old_reloads_1 won't get to see it, because
5422: it thinks only about the original insn. So invalidate it here. */
5423: if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
5424: {
5425: register int nregno = REGNO (reload_out[r]);
5426: reg_last_reload_reg[nregno] = 0;
5427: }
5428: }
5429: }
5430:
5431: /* Emit code before BEFORE_INSN to perform an input reload of IN to RELOADREG.
5432: Returns first insn emitted. */
5433:
5434: rtx
5435: gen_input_reload (reloadreg, in, before_insn)
5436: rtx reloadreg;
5437: rtx in;
5438: rtx before_insn;
5439: {
5440: register rtx prev_insn = PREV_INSN (before_insn);
5441:
5442: /* How to do this reload can get quite tricky. Normally, we are being
5443: asked to reload a simple operand, such as a MEM, a constant, or a pseudo
5444: register that didn't get a hard register. In that case we can just
5445: call emit_move_insn.
5446:
5447: We can also be asked to reload a PLUS that adds either two registers or
5448: a register and a constant or MEM. This can occur during frame pointer
5449: elimination. That case if handled by trying to emit a single insn
5450: to perform the add. If it is not valid, we use a two insn sequence.
5451:
5452: Finally, we could be called to handle an 'o' constraint by putting
5453: an address into a register. In that case, we first try to do this
5454: with a named pattern of "reload_load_address". If no such pattern
5455: exists, we just emit a SET insn and hope for the best (it will normally
5456: be valid on machines that use 'o').
5457:
5458: This entire process is made complex because reload will never
5459: process the insns we generate here and so we must ensure that
5460: they will fit their constraints and also by the fact that parts of
5461: IN might be being reloaded separately and replaced with spill registers.
5462: Because of this, we are, in some sense, just guessing the right approach
5463: here. The one listed above seems to work.
5464:
5465: ??? At some point, this whole thing needs to be rethought. */
5466:
5467: if (GET_CODE (in) == PLUS
5468: && GET_CODE (XEXP (in, 0)) == REG
5469: && (GET_CODE (XEXP (in, 1)) == REG
5470: || CONSTANT_P (XEXP (in, 1))
5471: || GET_CODE (XEXP (in, 1)) == MEM))
5472: {
5473: /* We need to compute the sum of what is either a register and a
5474: constant, a register and memory, or a hard register and a pseudo
5475: register and put it into the reload register. The best possible way
5476: of doing this is if the machine has a three-operand ADD insn that
5477: accepts the required operands.
5478:
5479: The simplest approach is to try to generate such an insn and see if it
5480: is recognized and matches its constraints. If so, it can be used.
5481:
5482: It might be better not to actually emit the insn unless it is valid,
1.1.1.2 root 5483: but we need to pass the insn as an operand to `recog' and
5484: `insn_extract'and it is simpler to emit and then delete the insn if
5485: not valid than to dummy things up. */
1.1 root 5486:
1.1.1.3 ! root 5487: rtx op0, op1, tem, insn;
1.1 root 5488: int code;
5489:
1.1.1.3 ! root 5490: op0 = find_replacement (&XEXP (in, 0));
! 5491: op1 = find_replacement (&XEXP (in, 1));
! 5492:
1.1 root 5493: /* Since constraint checking is strict, commutativity won't be
5494: checked, so we need to do that here to avoid spurious failure
5495: if the add instruction is two-address and the second operand
5496: of the add is the same as the reload reg, which is frequently
5497: the case. If the insn would be A = B + A, rearrange it so
5498: it will be A = A + B as constrain_operands expects. */
5499:
5500: if (GET_CODE (XEXP (in, 1)) == REG
5501: && REGNO (reloadreg) == REGNO (XEXP (in, 1)))
1.1.1.3 ! root 5502: tem = op0, op0 = op1, op1 = tem;
! 5503:
! 5504: if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
! 5505: in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
1.1 root 5506:
5507: insn = emit_insn_before (gen_rtx (SET, VOIDmode, reloadreg, in),
5508: before_insn);
5509: code = recog_memoized (insn);
5510:
5511: if (code >= 0)
5512: {
5513: insn_extract (insn);
5514: /* We want constrain operands to treat this insn strictly in
5515: its validity determination, i.e., the way it would after reload
5516: has completed. */
5517: if (constrain_operands (code, 1))
5518: return insn;
5519: }
5520:
5521: if (PREV_INSN (insn))
5522: NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
5523: if (NEXT_INSN (insn))
5524: PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
5525:
5526: /* If that failed, we must use a conservative two-insn sequence.
5527: use move to copy constant, MEM, or pseudo register to the reload
1.1.1.3 ! root 5528: register since "move" will be able to handle an arbitrary operand,
! 5529: unlike add which can't, in general. Then add the registers.
1.1 root 5530:
5531: If there is another way to do this for a specific machine, a
5532: DEFINE_PEEPHOLE should be specified that recognizes the sequence
5533: we emit below. */
5534:
1.1.1.3 ! root 5535: if (CONSTANT_P (op1) || GET_CODE (op1) == MEM
! 5536: || (GET_CODE (op1) == REG
! 5537: && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
! 5538: tem = op0, op0 = op1, op1 = tem;
1.1 root 5539:
1.1.1.3 ! root 5540: emit_insn_before (gen_move_insn (reloadreg, op0), before_insn);
! 5541: emit_insn_before (gen_add2_insn (reloadreg, op1), before_insn);
1.1 root 5542: }
5543:
5544: /* If IN is a simple operand, use gen_move_insn. */
5545: else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
5546: emit_insn_before (gen_move_insn (reloadreg, in), before_insn);
5547:
5548: #ifdef HAVE_reload_load_address
5549: else if (HAVE_reload_load_address)
5550: emit_insn_before (gen_reload_load_address (reloadreg, in), before_insn);
5551: #endif
5552:
5553: /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */
5554: else
5555: emit_insn_before (gen_rtx (SET, VOIDmode, reloadreg, in), before_insn);
5556:
5557: /* Return the first insn emitted.
5558: We can not just return PREV_INSN (before_insn), because there may have
5559: been multiple instructions emitted. Also note that gen_move_insn may
5560: emit more than one insn itself, so we can not assume that there is one
5561: insn emitted per emit_insn_before call. */
5562:
5563: return NEXT_INSN (prev_insn);
5564: }
5565:
5566: /* Delete a previously made output-reload
5567: whose result we now believe is not needed.
5568: First we double-check.
5569:
5570: INSN is the insn now being processed.
5571: OUTPUT_RELOAD_INSN is the insn of the output reload.
5572: J is the reload-number for this insn. */
5573:
5574: static void
5575: delete_output_reload (insn, j, output_reload_insn)
5576: rtx insn;
5577: int j;
5578: rtx output_reload_insn;
5579: {
5580: register rtx i1;
5581:
5582: /* Get the raw pseudo-register referred to. */
5583:
5584: rtx reg = reload_in[j];
5585: while (GET_CODE (reg) == SUBREG)
5586: reg = SUBREG_REG (reg);
5587:
5588: /* If the pseudo-reg we are reloading is no longer referenced
5589: anywhere between the store into it and here,
5590: and no jumps or labels intervene, then the value can get
5591: here through the reload reg alone.
5592: Otherwise, give up--return. */
5593: for (i1 = NEXT_INSN (output_reload_insn);
5594: i1 != insn; i1 = NEXT_INSN (i1))
5595: {
5596: if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
5597: return;
5598: if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
5599: && reg_mentioned_p (reg, PATTERN (i1)))
5600: return;
5601: }
5602:
5603: /* If this insn will store in the pseudo again,
5604: the previous store can be removed. */
5605: if (reload_out[j] == reload_in[j])
5606: delete_insn (output_reload_insn);
5607:
5608: /* See if the pseudo reg has been completely replaced
5609: with reload regs. If so, delete the store insn
5610: and forget we had a stack slot for the pseudo. */
5611: else if (reg_n_deaths[REGNO (reg)] == 1
5612: && reg_basic_block[REGNO (reg)] >= 0
5613: && find_regno_note (insn, REG_DEAD, REGNO (reg)))
5614: {
5615: rtx i2;
5616:
5617: /* We know that it was used only between here
5618: and the beginning of the current basic block.
5619: (We also know that the last use before INSN was
5620: the output reload we are thinking of deleting, but never mind that.)
5621: Search that range; see if any ref remains. */
5622: for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
5623: {
5624: rtx set = single_set (i2);
5625:
5626: /* Uses which just store in the pseudo don't count,
5627: since if they are the only uses, they are dead. */
5628: if (set != 0 && SET_DEST (set) == reg)
5629: continue;
5630: if (GET_CODE (i2) == CODE_LABEL
5631: || GET_CODE (i2) == JUMP_INSN)
5632: break;
5633: if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
5634: && reg_mentioned_p (reg, PATTERN (i2)))
5635: /* Some other ref remains;
5636: we can't do anything. */
5637: return;
5638: }
5639:
5640: /* Delete the now-dead stores into this pseudo. */
5641: for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
5642: {
5643: rtx set = single_set (i2);
5644:
5645: if (set != 0 && SET_DEST (set) == reg)
5646: delete_insn (i2);
5647: if (GET_CODE (i2) == CODE_LABEL
5648: || GET_CODE (i2) == JUMP_INSN)
5649: break;
5650: }
5651:
5652: /* For the debugging info,
5653: say the pseudo lives in this reload reg. */
5654: reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
5655: alter_reg (REGNO (reg), -1);
5656: }
5657: }
5658:
5659:
5660: /* Output reload-insns to reload VALUE into RELOADREG.
5661: VALUE is a autoincrement or autodecrement RTX whose operand
5662: is a register or memory location;
5663: so reloading involves incrementing that location.
5664:
5665: INC_AMOUNT is the number to increment or decrement by (always positive).
5666: This cannot be deduced from VALUE.
5667:
5668: INSN is the insn before which the new insns should be emitted.
5669:
5670: The return value is the first of the insns emitted. */
5671:
5672: static rtx
5673: inc_for_reload (reloadreg, value, inc_amount, insn)
5674: rtx reloadreg;
5675: rtx value;
5676: int inc_amount;
5677: rtx insn;
5678: {
5679: /* REG or MEM to be copied and incremented. */
5680: rtx incloc = XEXP (value, 0);
5681: /* Nonzero if increment after copying. */
5682: int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
1.1.1.2 root 5683: rtx prev = PREV_INSN (insn);
5684: rtx inc;
5685: rtx add_insn;
1.1.1.3 ! root 5686: int code;
1.1 root 5687:
5688: /* No hard register is equivalent to this register after
5689: inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
5690: we could inc/dec that register as well (maybe even using it for
5691: the source), but I'm not sure it's worth worrying about. */
5692: if (GET_CODE (incloc) == REG)
5693: reg_last_reload_reg[REGNO (incloc)] = 0;
5694:
5695: if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
5696: inc_amount = - inc_amount;
5697:
1.1.1.2 root 5698: inc = gen_rtx (CONST_INT, VOIDmode, inc_amount);
5699:
5700: /* If this is post-increment, first copy the location to the reload reg. */
5701: if (post)
5702: emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
5703:
5704: /* See if we can directly increment INCLOC. Use a method similar to that
5705: in gen_input_reload. */
5706:
5707: add_insn = emit_insn_before (gen_rtx (SET, VOIDmode, incloc,
5708: gen_rtx (PLUS, GET_MODE (incloc),
5709: incloc, inc)), insn);
5710:
5711: code = recog_memoized (add_insn);
5712: if (code >= 0)
1.1 root 5713: {
1.1.1.2 root 5714: insn_extract (add_insn);
5715: if (constrain_operands (code, 1))
5716: {
5717: /* If this is a pre-increment and we have incremented the value
5718: where it lives, copy the incremented value to RELOADREG to
5719: be used as an address. */
5720:
5721: if (! post)
5722: emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
5723: return NEXT_INSN (prev);
1.1 root 5724: }
1.1.1.2 root 5725: }
5726:
5727: if (PREV_INSN (add_insn))
5728: NEXT_INSN (PREV_INSN (add_insn)) = NEXT_INSN (add_insn);
5729: if (NEXT_INSN (add_insn))
5730: PREV_INSN (NEXT_INSN (add_insn)) = PREV_INSN (add_insn);
5731:
5732: /* If couldn't do the increment directly, must increment in RELOADREG.
5733: The way we do this depends on whether this is pre- or post-increment.
5734: For pre-increment, copy INCLOC to the reload register, increment it
5735: there, then save back. */
5736:
5737: if (! post)
5738: {
5739: emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
5740: emit_insn_before (gen_add2_insn (reloadreg, inc), insn);
5741: emit_insn_before (gen_move_insn (incloc, reloadreg), insn);
5742: }
1.1 root 5743: else
5744: {
1.1.1.2 root 5745: /* Postincrement.
5746: Because this might be a jump insn or a compare, and because RELOADREG
5747: may not be available after the insn in an input reload, we must do
5748: the incrementation before the insn being reloaded for.
5749:
5750: We have already copied INCLOC to RELOADREG. Increment the copy in
5751: RELOADREG, save that back, then decrement RELOADREG so it has
5752: the original value. */
5753:
5754: emit_insn_before (gen_add2_insn (reloadreg, inc), insn);
5755: emit_insn_before (gen_move_insn (incloc, reloadreg), insn);
5756: emit_insn_before (gen_add2_insn (reloadreg,
5757: gen_rtx (CONST_INT, VOIDmode,
5758: -inc_amount)),
5759: insn);
1.1 root 5760: }
1.1.1.2 root 5761:
5762: return NEXT_INSN (prev);
1.1 root 5763: }
5764:
5765: /* Return 1 if we are certain that the constraint-string STRING allows
5766: the hard register REG. Return 0 if we can't be sure of this. */
5767:
5768: static int
5769: constraint_accepts_reg_p (string, reg)
5770: char *string;
5771: rtx reg;
5772: {
5773: int value = 0;
5774: int regno = true_regnum (reg);
5775: int c;
5776:
5777: /* Initialize for first alternative. */
5778: value = 0;
5779: /* Check that each alternative contains `g' or `r'. */
5780: while (1)
5781: switch (c = *string++)
5782: {
5783: case 0:
5784: /* If an alternative lacks `g' or `r', we lose. */
5785: return value;
5786: case ',':
5787: /* If an alternative lacks `g' or `r', we lose. */
5788: if (value == 0)
5789: return 0;
5790: /* Initialize for next alternative. */
5791: value = 0;
5792: break;
5793: case 'g':
5794: case 'r':
5795: /* Any general reg wins for this alternative. */
5796: if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
5797: value = 1;
5798: break;
5799: default:
5800: /* Any reg in specified class wins for this alternative. */
5801: {
1.1.1.3 ! root 5802: enum reg_class class = REG_CLASS_FROM_LETTER (c);
1.1 root 5803:
1.1.1.3 ! root 5804: if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
1.1 root 5805: value = 1;
5806: }
5807: }
5808: }
5809:
5810: /* Return the number of places FIND appears within X, but don't count
5811: an occurrence if some SET_DEST is FIND. */
5812:
5813: static int
5814: count_occurrences (x, find)
5815: register rtx x, find;
5816: {
5817: register int i, j;
5818: register enum rtx_code code;
5819: register char *format_ptr;
5820: int count;
5821:
5822: if (x == find)
5823: return 1;
5824: if (x == 0)
5825: return 0;
5826:
5827: code = GET_CODE (x);
5828:
5829: switch (code)
5830: {
5831: case REG:
5832: case QUEUED:
5833: case CONST_INT:
5834: case CONST_DOUBLE:
5835: case SYMBOL_REF:
5836: case CODE_LABEL:
5837: case PC:
5838: case CC0:
5839: return 0;
5840:
5841: case SET:
5842: if (SET_DEST (x) == find)
5843: return count_occurrences (SET_SRC (x), find);
5844: break;
5845: }
5846:
5847: format_ptr = GET_RTX_FORMAT (code);
5848: count = 0;
5849:
5850: for (i = 0; i < GET_RTX_LENGTH (code); i++)
5851: {
5852: switch (*format_ptr++)
5853: {
5854: case 'e':
5855: count += count_occurrences (XEXP (x, i), find);
5856: break;
5857:
5858: case 'E':
5859: if (XVEC (x, i) != NULL)
5860: {
5861: for (j = 0; j < XVECLEN (x, i); j++)
5862: count += count_occurrences (XVECEXP (x, i, j), find);
5863: }
5864: break;
5865: }
5866: }
5867: return count;
5868: }
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