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1.1 root 1: /* Definitions of target machine for GNU compiler. Alliant FX/8 version.
2: Copyright (C) 1987, 1988 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is distributed in the hope that it will be useful,
7: but WITHOUT ANY WARRANTY. No author or distributor
8: accepts responsibility to anyone for the consequences of using it
9: or for whether it serves any particular purpose or works at all,
10: unless he says so in writing. Refer to the GNU CC General Public
11: License for full details.
12:
13: Everyone is granted permission to copy, modify and redistribute
14: GNU CC, but only under the conditions described in the
15: GNU CC General Public License. A copy of this license is
16: supposed to have been given to you along with GNU CC so you
17: can know your rights and responsibilities. It should be in a
18: file named COPYING. Among other things, the copyright notice
19: and this notice must be preserved on all copies. */
20:
21:
22: /* Note that some other tm- files include this one and then override
23: many of the definitions that relate to assembler syntax. */
24:
25:
26: /* Names to predefine in the preprocessor for this target machine. */
27:
28: /* See tm-sun3.h, tm-sun2.h, tm-isi68.h for different CPP_PREDEFINES. */
29:
30: /* Print subsidiary information on the compiler version in use. */
31: #ifdef MOTOROLA
32: #define TARGET_VERSION printf (" (68k, Motorola syntax)");
33: #else
34: #define TARGET_VERSION printf (" (68k, MIT syntax)");
35: #endif
36:
37: /* Run-time compilation parameters selecting different hardware subsets. */
38:
39: extern int target_flags;
40:
41: /* Macros used in the machine description to test the flags. */
42:
43: /* Compile for a 68020 (not a 68000 or 68010). */
44: #define TARGET_68020 (target_flags & 1)
45: /* Compile 68881 insns for floating point (not library calls). */
46: #define TARGET_68881 (target_flags & 2)
47: /* Compile using 68020 bitfield insns. */
48: #define TARGET_BITFIELD (target_flags & 4)
49: /* Compile using rtd insn calling sequence.
50: This will not work unless you use prototypes at least
51: for all functions that can take varying numbers of args. */
52: #define TARGET_RTD (target_flags & 8)
53: /* Compile passing first two args in regs 0 and 1.
54: This exists only to test compiler features that will
55: be needed for RISC chips. It is not usable
56: and is not intended to be usable on this cpu. */
57: #define TARGET_REGPARM (target_flags & 020)
58: /* Compile with 16-bit `int'. */
59: #define TARGET_SHORT (target_flags & 040)
60:
61: /* Compile with special insns for Sun FPA. */
62: #define TARGET_FPA (target_flags & 0100)
63:
64: /* Macro to define tables used to set the flags.
65: This is a list in braces of pairs in braces,
66: each pair being { "NAME", VALUE }
67: where VALUE is the bits to set or minus the bits to clear.
68: An empty string NAME is used to identify the default VALUE. */
69:
70: #define TARGET_SWITCHES \
71: { { "68020", 5}, \
72: { "c68020", 5}, \
73: { "68881", 2}, \
74: { "bitfield", 4}, \
75: { "68000", -5}, \
76: { "c68000", -5}, \
77: { "soft-float", -0102}, \
78: { "nobitfield", -4}, \
79: { "rtd", 8}, \
80: { "nortd", -8}, \
81: { "short", 040}, \
82: { "noshort", -040}, \
83: { "fpa", 0100}, \
84: { "nofpa", -0100}, \
85: { "", TARGET_DEFAULT}}
86:
87: /* TARGET_DEFAULT is defined in tm-sun*.h and tm-isi68.h, etc. */
88:
89: /* Blow away 68881 flag silently on TARGET_FPA (since we can't clear
90: any bits in TARGET_SWITCHES above) */
91: #define OVERRIDE_OPTIONS \
92: { \
93: if (TARGET_FPA) target_flags &= ~2; \
94: }
95:
96: /* target machine storage layout */
97:
98: /* Define this if most significant bit is lowest numbered
99: in instructions that operate on numbered bit-fields.
100: This is true for 68020 insns such as bfins and bfexts.
101: We make it true always by avoiding using the single-bit insns
102: except in special cases with constant bit numbers. */
103: #define BITS_BIG_ENDIAN
104:
105: /* Define this if most significant byte of a word is the lowest numbered. */
106: /* That is true on the 68000. */
107: #define BYTES_BIG_ENDIAN
108:
109: /* Define this if most significant word of a multiword number is numbered. */
110: /* For 68000 we can decide arbitrarily
111: since there are no machine instructions for them. */
112: /* #define WORDS_BIG_ENDIAN */
113:
114: /* number of bits in an addressible storage unit */
115: #define BITS_PER_UNIT 8
116:
117: /* Width in bits of a "word", which is the contents of a machine register.
118: Note that this is not necessarily the width of data type `int';
119: if using 16-bit ints on a 68000, this would still be 32.
120: But on a machine with 16-bit registers, this would be 16. */
121: #define BITS_PER_WORD 32
122:
123: /* Width of a word, in units (bytes). */
124: #define UNITS_PER_WORD 4
125:
126: /* Width in bits of a pointer.
127: See also the macro `Pmode' defined below. */
128: #define POINTER_SIZE 32
129:
130: /* Allocation boundary (in *bits*) for storing pointers in memory. */
131: #define POINTER_BOUNDARY 16
132:
133: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
134: #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
135:
136: /* Boundary (in *bits*) on which stack pointer should be aligned. */
137: #define STACK_BOUNDARY 16
138:
139: /* Allocation boundary (in *bits*) for the code of a function. */
140: #define FUNCTION_BOUNDARY 16
141:
142: /* Alignment of field after `int : 0' in a structure. */
143: #define EMPTY_FIELD_BOUNDARY 16
144:
145: /* No data type wants to be aligned rounder than this. */
146: #define BIGGEST_ALIGNMENT 16
147:
148: /* Define this if move instructions will actually fail to work
149: when given unaligned data. */
150: #define STRICT_ALIGNMENT
151:
152: /* Define number of bits in most basic integer type.
153: (If undefined, default is BITS_PER_WORD). */
154:
155: #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
156:
157: /* Standard register usage. */
158:
159: /* Number of actual hardware registers.
160: The hardware registers are assigned numbers for the compiler
161: from 0 to just below FIRST_PSEUDO_REGISTER.
162: All registers that the compiler knows about must be given numbers,
163: even those that are not normally considered general registers.
164: For the 68000, we give the data registers numbers 0-7,
165: the address registers numbers 010-017,
166: and the 68881 floating point registers numbers 020-027. */
167: #define FIRST_PSEUDO_REGISTER 56
168:
169: /* 1 for registers that have pervasive standard uses
170: and are not available for the register allocator.
171: On the 68000, only the stack pointer is such. */
172: /* fpa0 is also reserved so that it can be used to move shit back and
173: forth between high fpa regs and everything else. */
174: #define FIXED_REGISTERS \
175: {0, 0, 0, 0, 0, 0, 0, 0, \
176: 1, 0, 0, 0, 0, 0, 1, 1, \
177: 0, 0, 0, 0, 0, 0, 0, 0 }
178:
179: /* 1 for registers not available across function calls.
180: These must include the FIXED_REGISTERS and also any
181: registers that can be used without being saved.
182: The latter must include the registers where values are returned
183: and the register where structure-value addresses are passed.
184: Aside from that, you can include as many other registers as you like. */
185:
186: #define CALL_USED_REGISTERS \
187: {1, 1, 1, 1, 1, 1, 1, 1, \
188: 1, 1, 1, 1, 1, 1, 1, 1, \
189: 1, 1, 1, 1, 1, 1, 1, 1 }
190:
191: /* Make sure everything's fine if we *don't* have a given processor.
192: This assumes that putting a register in fixed_regs will keep the
193: compilers mitt's completely off it. We don't bother to zero it out
194: of register classes. If neither TARGET_FPA or TARGET_68881 is set,
195: the compiler won't touch since no instructions that use these
196: registers will be valid. */
197: #define CONDITIONAL_REGISTER_USAGE \
198: { \
199: int i; \
200: HARD_REG_SET x; \
201: if (!TARGET_FPA) \
202: { \
203: COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \
204: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
205: if (TEST_HARD_REG_BIT (x, i)) \
206: fixed_regs[i] = call_used_regs[i] = 1; \
207: } \
208: }
209:
210: /* Return number of consecutive hard regs needed starting at reg REGNO
211: to hold something of mode MODE.
212: This is ordinarily the length in words of a value of mode MODE
213: but can be less for certain modes in special long registers.
214:
215: On the 68000, ordinary registers hold 32 bits worth;
216: for the 68881 registers, a single register is always enough for
217: anything that can be stored in them at all. */
218: #define HARD_REGNO_NREGS(REGNO, MODE) \
219: ((REGNO) >= 16 ? 1 \
220: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
221:
222: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
223: On the 68000, the cpu registers can hold any mode but the 68881 registers
224: can hold only SFmode or DFmode. And the 68881 registers can't hold anything
225: if 68881 use is disabled. However, the Sun FPA register can
226: (apparently) hold whatever you feel like putting in them. */
227: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
228: ((REGNO) < 16 \
229: || ((REGNO) < 24 \
230: ? TARGET_68881 && ((MODE) == SFmode || (MODE) == DFmode) \
231: : ((REGNO) < 56 \
232: ? TARGET_FPA : 0)))
233:
234: /* Value is 1 if it is a good idea to tie two pseudo registers
235: when one has mode MODE1 and one has mode MODE2.
236: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
237: for any hard reg, then this must be 0 for correct output. */
238: #define MODES_TIEABLE_P(MODE1, MODE2) \
239: (! TARGET_68881 \
240: || (((MODE1) == SFmode || (MODE1) == DFmode) \
241: == ((MODE2) == SFmode || (MODE2) == DFmode)))
242:
243: /* Specify the registers used for certain standard purposes.
244: The values of these macros are register numbers. */
245:
246: /* m68000 pc isn't overloaded on a register. */
247: /* #define PC_REGNUM */
248:
249: /* Register to use for pushing function arguments. */
250: #define STACK_POINTER_REGNUM 15
251:
252: /* Base register for access to local variables of the function. */
253: #define FRAME_POINTER_REGNUM 14
254:
255: /* Value should be nonzero if functions must have frame pointers.
256: Zero means the frame pointer need not be set up (and parms
257: may be accessed via the stack pointer) in functions that seem suitable.
258: This is computed in `reload', in reload1.c. */
259: #define FRAME_POINTER_REQUIRED 1
260:
261: /* Base register for access to arguments of the function. */
262: #define ARG_POINTER_REGNUM 8
263:
264: /* Register in which static-chain is passed to a function. */
265: #define STATIC_CHAIN_REGNUM 8
266:
267: /* Register in which address to store a structure value
268: is passed to a function. */
269: #define STRUCT_VALUE_REGNUM 9
270:
271: /* Define the classes of registers for register constraints in the
272: machine description. Also define ranges of constants.
273:
274: One of the classes must always be named ALL_REGS and include all hard regs.
275: If there is more than one class, another class must be named NO_REGS
276: and contain no registers.
277:
278: The name GENERAL_REGS must be the name of a class (or an alias for
279: another name such as ALL_REGS). This is the class of registers
280: that is allowed by "g" or "r" in a register constraint.
281: Also, registers outside this class are allocated only when
282: instructions express preferences for them.
283:
284: The classes must be numbered in nondecreasing order; that is,
285: a larger-numbered class must never be contained completely
286: in a smaller-numbered class.
287:
288: For any two classes, it is very desirable that there be another
289: class that represents their union. */
290:
291: /* The 68000 has three kinds of registers, so eight classes would be
292: a complete set. One of them is not needed. */
293:
294: /*
295: * Notes on final choices:
296: *
297: * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything
298: * else.
299: * 2) Removed all unions that involve address registers with
300: * floating point registers (left in unions of address and data with
301: * floating point).
302: * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS.
303: * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS.
304: * 4) Left in everything else.
305: */
306: enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS,
307: FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS,
308: DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS,
309: GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS,
310: LIM_REG_CLASSES };
311:
312: #define N_REG_CLASSES (int) LIM_REG_CLASSES
313:
314: /* Give names of register classes as strings for dump file. */
315:
316: #define REG_CLASS_NAMES \
317: { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \
318: "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \
319: "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \
320: "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" }
321:
322: /* Define which registers fit in which classes.
323: This is an initializer for a vector of HARD_REG_SET
324: of length N_REG_CLASSES. */
325:
326: #define REG_CLASS_CONTENTS \
327: { \
328: {0, 0}, /* NO_REGS */ \
329: {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \
330: {0xff000000, 0x00ffffff}, /* FPA_REGS */ \
331: {0x00ff0000, 0x00000000}, /* FP_REGS */ \
332: {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \
333: {0x000000ff, 0x00000000}, /* DATA_REGS */ \
334: {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \
335: {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \
336: {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\
337: {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \
338: {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \
339: {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\
340: {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\
341: {0xffffffff, 0x00ffffff} /* ALL_REGS */ \
342: }
343:
344: /* The same information, inverted:
345: Return the class number of the smallest class containing
346: reg number REGNO. This could be a conditional expression
347: or could index an array. */
348:
349: extern enum reg_class regno_reg_class[];
350: #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
351:
352: /* The class value for index registers, and the one for base regs. */
353:
354: #define INDEX_REG_CLASS GENERAL_REGS
355: #define BASE_REG_CLASS ADDR_REGS
356:
357: /* Get reg_class from a letter such as appears in the machine description.
358: We do a trick here to modify the effective constraints on the
359: machine description; we zorch the constraint letters that aren't
360: appropriate for a specific target. This allows us to guarrantee
361: that a specific kind of register will not be used for a given taget
362: without fiddling with the register classes above. */
363:
364: #define REG_CLASS_FROM_LETTER(C) \
365: ((C) == 'a' ? ADDR_REGS : \
366: ((C) == 'd' ? DATA_REGS : \
367: ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
368: NO_REGS) : \
369: ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \
370: NO_REGS) : \
371: ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \
372: NO_REGS) : \
373: NO_REGS)))))
374:
375: /* The letters I, J, K, L and M in a register constraint string
376: can be used to stand for particular ranges of immediate operands.
377: This macro defines what the ranges are.
378: C is the letter, and VALUE is a constant value.
379: Return 1 if VALUE is in the range specified by C.
380:
381: For the 68000, `I' is used for the range 1 to 8
382: allowed as immediate shift counts and in addq.
383: `J' is used for the range of signed numbers that fit in 16 bits.
384: `K' is for numbers that moveq can't handle.
385: `L' is for range -8 to -1, range of values that can be added with subq. */
386:
387: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
388: ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
389: (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
390: (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
391: (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0)
392:
393: /*
394: * A small bit of explanation:
395: * "G" defines all of the floating constants that are *NOT* 68881
396: * constants. this is so 68881 constants get reloaded and the
397: * fpmovecr is used. "H" defines *only* the class of constants that
398: * the fpa can use, because these can be gotten at in any fpa
399: * instruction and there is no need to force reloads.
400: */
401:
402: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
403:
404: /* Given an rtx X being reloaded into a reg required to be
405: in class CLASS, return the class of reg to actually use.
406: In general this is just CLASS; but on some machines
407: in some cases it is preferable to use a more restrictive class.
408: On the 68000 series, use a data reg if possible when the
409: value is a constant in the range where moveq could be used
410: and we ensure that QImodes are reloaded into data regs. */
411:
412: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
413: ((GET_CODE (X) == CONST_INT \
414: && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
415: && (CLASS) != ADDR_REGS) \
416: ? DATA_REGS \
417: : GET_MODE (X) == QImode \
418: ? DATA_REGS \
419: : (CLASS))
420:
421: /* Return the maximum number of consecutive registers
422: needed to represent mode MODE in a register of class CLASS. */
423: /* On the 68000, this is the size of MODE in words,
424: except in the FP regs, where a single reg is always enough. */
425: #define CLASS_MAX_NREGS(CLASS, MODE) \
426: ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \
427: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
428:
429: /* Stack layout; function entry, exit and calling. */
430:
431: /* Define this if pushing a word on the stack
432: makes the stack pointer a smaller address. */
433: #define STACK_GROWS_DOWNWARD
434:
435: /* Define this if the nominal address of the stack frame
436: is at the high-address end of the local variables;
437: that is, each additional local variable allocated
438: goes at a more negative offset in the frame. */
439: #define FRAME_GROWS_DOWNWARD
440:
441: /* Offset within stack frame to start allocating local variables at.
442: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
443: first local allocated. Otherwise, it is the offset to the BEGINNING
444: of the first local allocated. */
445: #define STARTING_FRAME_OFFSET -4
446:
447: /* If we generate an insn to push BYTES bytes,
448: this says how many the stack pointer really advances by.
449: On the 68000, sp@- in a byte insn really pushes a word. */
450: #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
451:
452: /* Offset of first parameter from the argument pointer register value. */
453: #define FIRST_PARM_OFFSET(FNDECL) 0
454:
455: /* Value is 1 if returning from a function call automatically
456: pops the arguments described by the number-of-args field in the call.
457: FUNTYPE is the data type of the function (as a tree),
458: or for a library call it is an identifier node for the subroutine name.
459:
460: On the 68000, the RTS insn cannot pop anything.
461: On the 68010, the RTD insn may be used to pop them if the number
462: of args is fixed, but if the number is variable then the caller
463: must pop them all. RTD can't be used for library calls now
464: because the library is compiled with the Unix compiler.
465: Use of RTD is a selectable option, since it is incompatible with
466: standard Unix calling sequences. If the option is not selected,
467: the caller must always pop the args. */
468:
469: #define RETURN_POPS_ARGS(FUNTYPE) \
470: (TARGET_RTD && TREE_CODE (FUNTYPE) != IDENTIFIER_NODE \
471: && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
472: || TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) == void_type_node))
473:
474: /* Define how to find the value returned by a function.
475: VALTYPE is the data type of the value (as a tree).
476: If the precise function being called is known, FUNC is its FUNCTION_DECL;
477: otherwise, FUNC is 0. */
478:
479: /* On the 68000 the return value is in D0 regardless. */
480:
481: #define FUNCTION_VALUE(VALTYPE, FUNC) \
482: gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
483:
484: /* Define how to find the value returned by a library function
485: assuming the value has mode MODE. */
486:
487: /* On the 68000 the return value is in D0 regardless. */
488:
489: #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
490:
491: /* 1 if N is a possible register number for a function value.
492: On the 68000, d0 is the only register thus used. */
493:
494: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
495:
496: /* 1 if N is a possible register number for function argument passing.
497: On the 68000, no registers are used in this way. */
498:
499: #define FUNCTION_ARG_REGNO_P(N) 0
500:
501: /* Define a data type for recording info about an argument list
502: during the scan of that argument list. This data type should
503: hold all necessary information about the function itself
504: and about the args processed so far, enough to enable macros
505: such as FUNCTION_ARG to determine where the next arg should go.
506:
507: On the m68k, this is a single integer, which is a number of bytes
508: of arguments scanned so far. */
509:
510: #define CUMULATIVE_ARGS int
511:
512: /* Initialize a variable CUM of type CUMULATIVE_ARGS
513: for a call to a function whose data type is FNTYPE.
514: For a library call, FNTYPE is 0.
515:
516: On the m68k, the offset starts at 0. */
517:
518: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE) \
519: ((CUM) = 0)
520:
521: /* Update the data in CUM to advance over an argument
522: of mode MODE and data type TYPE.
523: (TYPE is null for libcalls where that information may not be available.) */
524:
525: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
526: ((CUM) += ((MODE) != BLKmode \
527: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
528: : (int_size_in_bytes (TYPE) + 3) & ~3))
529:
530: /* Define where to put the arguments to a function.
531: Value is zero to push the argument on the stack,
532: or a hard register in which to store the argument.
533:
534: MODE is the argument's machine mode.
535: TYPE is the data type of the argument (as a tree).
536: This is null for libcalls where that information may
537: not be available.
538: CUM is a variable of type CUMULATIVE_ARGS which gives info about
539: the preceding args and about the function being called.
540: NAMED is nonzero if this argument is a named parameter
541: (otherwise it is an extra parameter matching an ellipsis). */
542:
543: /* On the 68000 all args are pushed, except if -mregparm is specified
544: then the first two words of arguments are passed in d0, d1.
545: *NOTE* -mregparm does not work.
546: It exists only to test register calling conventions. */
547:
548: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
549: ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx(REG, (MODE), (CUM)/4) : 0)
550:
551: /* For an arg passed partly in registers and partly in memory,
552: this is the number of registers used.
553: For args passed entirely in registers or entirely in memory, zero. */
554:
555: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
556: ((TARGET_REGPARM && (CUM) < 8 \
557: && 8 < ((CUM) + ((MODE) == BLKmode \
558: ? int_size_in_bytes (TYPE) \
559: : GET_MODE_SIZE (MODE)))) \
560: ? 2 - (CUM) / 4 : 0)
561:
562: /* This macro generates the assembly code for function entry.
563: FILE is a stdio stream to output the code to.
564: SIZE is an int: how many units of temporary storage to allocate.
565: Refer to the array `regs_ever_live' to determine which registers
566: to save; `regs_ever_live[I]' is nonzero if register number I
567: is ever used in the function. This macro is responsible for
568: knowing which registers should not be saved even if used. */
569:
570: /* Note that the order of the bit mask for fmovem is the opposite
571: of the order for movem! */
572:
573: #define FUNCTION_PROLOGUE(FILE, SIZE) \
574: { int fsize = ((SIZE) + 3) & -4; \
575: if (frame_pointer_needed) { \
576: if (TARGET_68020 || fsize < 0x8000) \
577: fprintf(FILE,"\tlink a6,#%d\n", -fsize); \
578: else \
579: fprintf(FILE,"\tlink a6,#0\n\tsubl #%d,sp\n", fsize); } \
580: fprintf(FILE, "\tmovl a0,a6@(-4)\n" ); }
581:
582: /* Output assembler code to FILE to increment profiler label # LABELNO
583: for profiling a function entry. */
584:
585: #define FUNCTION_PROFILER(FILE, LABELNO) \
586: fprintf (FILE, "\tlea LP%d,a0\n\tjsr mcount\n", (LABELNO))
587:
588: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
589: the stack pointer does not matter. The value is tested only in
590: functions that have frame pointers.
591: No definition is equivalent to always zero. */
592:
593: #define EXIT_IGNORE_STACK 1
594:
595: /* This macro generates the assembly code for function exit,
596: on machines that need it. If FUNCTION_EPILOGUE is not defined
597: then individual return instructions are generated for each
598: return statement. Args are same as for FUNCTION_PROLOGUE.
599:
600: The function epilogue should not depend on the current stack pointer!
601: It should use the frame pointer only. This is mandatory because
602: of alloca; we also take advantage of it to omit stack adjustments
603: before returning. */
604:
605: #define FUNCTION_EPILOGUE(FILE, SIZE) \
606: { extern int current_function_pops_args; \
607: extern int current_function_args_size; \
608: if (frame_pointer_needed) \
609: fprintf (FILE, "\tunlk a6\n"); \
610: if (current_function_pops_args && current_function_args_size) \
611: fprintf (FILE, "\trtd #%d\n", current_function_args_size); \
612: else fprintf (FILE, "\trts\n"); }
613:
614: /* If the memory address ADDR is relative to the frame pointer,
615: correct it to be relative to the stack pointer instead.
616: This is for when we don't use a frame pointer.
617: ADDR should be a variable name. */
618:
619: #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \
620: { int offset = -1; \
621: rtx regs = stack_pointer_rtx; \
622: if (ADDR == frame_pointer_rtx) \
623: offset = 0; \
624: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
625: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
626: offset = INTVAL (XEXP (ADDR, 1)); \
627: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
628: { rtx other_reg = XEXP (ADDR, 1); \
629: offset = 0; \
630: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
631: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
632: { rtx other_reg = XEXP (ADDR, 0); \
633: offset = 0; \
634: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
635: else if (GET_CODE (ADDR) == PLUS \
636: && GET_CODE (XEXP (ADDR, 0)) == PLUS \
637: && XEXP (XEXP (ADDR, 0), 0) == frame_pointer_rtx \
638: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
639: { rtx other_reg = XEXP (XEXP (ADDR, 0), 1); \
640: offset = INTVAL (XEXP (ADDR, 1)); \
641: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
642: else if (GET_CODE (ADDR) == PLUS \
643: && GET_CODE (XEXP (ADDR, 0)) == PLUS \
644: && XEXP (XEXP (ADDR, 0), 1) == frame_pointer_rtx \
645: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
646: { rtx other_reg = XEXP (XEXP (ADDR, 0), 0); \
647: offset = INTVAL (XEXP (ADDR, 1)); \
648: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
649: if (offset >= 0) \
650: { int regno; \
651: extern char call_used_regs[]; \
652: for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
653: if (regs_ever_live[regno] && ! call_used_regs[regno]) \
654: offset += 12; \
655: for (regno = 0; regno < 16; regno++) \
656: if (regs_ever_live[regno] && ! call_used_regs[regno]) \
657: offset += 4; \
658: offset -= 4; \
659: ADDR = plus_constant (regs, offset + (DEPTH)); } } \
660:
661: /* Addressing modes, and classification of registers for them. */
662:
663: #define HAVE_POST_INCREMENT
664: /* #define HAVE_POST_DECREMENT */
665:
666: #define HAVE_PRE_DECREMENT
667: /* #define HAVE_PRE_INCREMENT */
668:
669: /* Macros to check register numbers against specific register classes. */
670:
671: /* These assume that REGNO is a hard or pseudo reg number.
672: They give nonzero only if REGNO is a hard reg of the suitable class
673: or a pseudo reg currently allocated to a suitable hard reg.
674: Since they use reg_renumber, they are safe only once reg_renumber
675: has been allocated, which happens in local-alloc.c. */
676:
677: #define REGNO_OK_FOR_INDEX_P(REGNO) \
678: ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
679: #define REGNO_OK_FOR_BASE_P(REGNO) \
680: (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
681: #define REGNO_OK_FOR_DATA_P(REGNO) \
682: ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
683: #define REGNO_OK_FOR_FP_P(REGNO) \
684: (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
685:
686: #define REGNO_OK_FOR_FPA_P(REGNO) 0
687:
688: /* Now macros that check whether X is a register and also,
689: strictly, whether it is in a specified class.
690:
691: These macros are specific to the 68000, and may be used only
692: in code for printing assembler insns and in conditions for
693: define_optimization. */
694:
695: /* 1 if X is a data register. */
696:
697: #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
698:
699: /* 1 if X is an fp register. */
700:
701: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
702:
703: /* 1 if X is an address register */
704:
705: #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
706:
707: /* 1 if X is a register in the Sun FPA. */
708: #define FPA_REG_P(X) 0
709:
710: /* Maximum number of registers that can appear in a valid memory address. */
711:
712: #define MAX_REGS_PER_ADDRESS 2
713:
714: /* Recognize any constant value that is a valid address. */
715:
716: #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
717:
718: /* Nonzero if the constant value X is a legitimate general operand.
719: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
720:
721: #define LEGITIMATE_CONSTANT_P(X) 1
722:
723: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
724: and check its validity for a certain class.
725: We have two alternate definitions for each of them.
726: The usual definition accepts all pseudo regs; the other rejects
727: them unless they have been allocated suitable hard regs.
728: The symbol REG_OK_STRICT causes the latter definition to be used.
729:
730: Most source files want to accept pseudo regs in the hope that
731: they will get allocated to the class that the insn wants them to be in.
732: Source files for reload pass need to be strict.
733: After reload, it makes no difference, since pseudo regs have
734: been eliminated by then. */
735:
736: #ifndef REG_OK_STRICT
737:
738: /* Nonzero if X is a hard reg that can be used as an index
739: or if it is a pseudo reg. */
740: #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
741: /* Nonzero if X is a hard reg that can be used as a base reg
742: or if it is a pseudo reg. */
743: #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
744:
745: #else
746:
747: /* Nonzero if X is a hard reg that can be used as an index. */
748: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
749: /* Nonzero if X is a hard reg that can be used as a base reg. */
750: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
751:
752: #endif
753:
754: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
755: that is a valid memory address for an instruction.
756: The MODE argument is the machine mode for the MEM expression
757: that wants to use this address.
758:
759: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
760:
761: #define INDIRECTABLE_1_ADDRESS_P(X) \
762: (CONSTANT_ADDRESS_P (X) \
763: || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
764: || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
765: && REG_P (XEXP (X, 0)) \
766: && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
767: || (GET_CODE (X) == PLUS \
768: && REG_P (XEXP (X, 0)) && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
769: && GET_CODE (XEXP (X, 1)) == CONST_INT \
770: && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000))
771:
772: #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
773: { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
774:
775: #define GO_IF_INDEXABLE_BASE(X, ADDR) \
776: { if (GET_CODE (X) == LABEL_REF) goto ADDR; \
777: if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; }
778:
779: #define GO_IF_INDEXING(X, ADDR) \
780: { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
781: { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
782: if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
783: { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
784:
785: #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
786: { GO_IF_INDEXING (X, ADDR); \
787: if (GET_CODE (X) == PLUS) \
788: { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
789: && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \
790: { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
791: if (GET_CODE (XEXP (X, 0)) == CONST_INT \
792: && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \
793: { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
794:
795: #define LEGITIMATE_INDEX_REG_P(X) \
796: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
797: || (GET_CODE (X) == SIGN_EXTEND \
798: && GET_CODE (XEXP (X, 0)) == REG \
799: && GET_MODE (XEXP (X, 0)) == HImode \
800: && REG_OK_FOR_INDEX_P (XEXP (X, 0))))
801:
802: #define LEGITIMATE_INDEX_P(X) \
803: (LEGITIMATE_INDEX_REG_P (X) \
804: || (TARGET_68020 && GET_CODE (X) == MULT \
805: && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
806: && GET_CODE (XEXP (X, 1)) == CONST_INT \
807: && (INTVAL (XEXP (X, 1)) == 2 \
808: || INTVAL (XEXP (X, 1)) == 4 \
809: || INTVAL (XEXP (X, 1)) == 8)))
810:
811: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
812: { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
813: GO_IF_INDEXED_ADDRESS (X, ADDR); }
814:
815: /* Try machine-dependent ways of modifying an illegitimate address
816: to be legitimate. If we find one, return the new, valid address.
817: This macro is used in only one place: `memory_address' in explow.c.
818:
819: OLDX is the address as it was before break_out_memory_refs was called.
820: In some cases it is useful to look at this to decide what needs to be done.
821:
822: MODE and WIN are passed so that this macro can use
823: GO_IF_LEGITIMATE_ADDRESS.
824:
825: It is always safe for this macro to do nothing. It exists to recognize
826: opportunities to optimize the output.
827:
828: For the 68000, we handle X+REG by loading X into a register R and
829: using R+REG. R will go in an address reg and indexing will be used.
830: However, if REG is a broken-out memory address or multiplication,
831: nothing needs to be done because REG can certainly go in an address reg. */
832:
833: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
834: { register int ch = (X) != (OLDX); \
835: if (GET_CODE (X) == PLUS) \
836: { if (GET_CODE (XEXP (X, 0)) == MULT) \
837: ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \
838: if (GET_CODE (XEXP (X, 1)) == MULT) \
839: ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \
840: if (ch && GET_CODE (XEXP (X, 1)) == REG \
841: && GET_CODE (XEXP (X, 0)) == REG) \
842: return X; \
843: if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
844: if (GET_CODE (XEXP (X, 0)) == REG \
845: || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
846: && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
847: && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
848: { register rtx temp = gen_reg_rtx (Pmode); \
849: register rtx val = force_operand (XEXP (X, 1), 0); \
850: emit_move_insn (temp, val); \
851: XEXP (X, 1) = temp; \
852: return X; } \
853: else if (GET_CODE (XEXP (X, 1)) == REG \
854: || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
855: && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
856: && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
857: { register rtx temp = gen_reg_rtx (Pmode); \
858: register rtx val = force_operand (XEXP (X, 0), 0); \
859: emit_move_insn (temp, val); \
860: XEXP (X, 0) = temp; \
861: return X; }}}
862:
863: /* Go to LABEL if ADDR (a legitimate address expression)
864: has an effect that depends on the machine mode it is used for.
865: On the 68000, only predecrement and postincrement address depend thus
866: (the amount of decrement or increment being the length of the operand). */
867:
868: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
869: if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
870:
871: /* Specify the machine mode that this machine uses
872: for the index in the tablejump instruction. */
873: #define CASE_VECTOR_MODE HImode
874:
875: /* Define this if the tablejump instruction expects the table
876: to contain offsets from the address of the table.
877: Do not define this if the table should contain absolute addresses. */
878: #define CASE_VECTOR_PC_RELATIVE
879:
880: /* Specify the tree operation to be used to convert reals to integers. */
881: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
882:
883: /* This is the kind of divide that is easiest to do in the general case. */
884: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
885:
886: /* Define this as 1 if `char' should by default be signed; else as 0. */
887: #define DEFAULT_SIGNED_CHAR 1
888:
889: /* Max number of bytes we can move from memory to memory
890: in one reasonably fast instruction. */
891: #define MOVE_MAX 4
892:
893: /* Define this if zero-extension is slow (more than one real instruction). */
894: #define SLOW_ZERO_EXTEND
895:
896: /* Nonzero if access to memory by bytes is slow and undesirable. */
897: #define SLOW_BYTE_ACCESS 0
898:
899: /* Define if shifts truncate the shift count
900: which implies one can omit a sign-extension or zero-extension
901: of a shift count. */
902: #define SHIFT_COUNT_TRUNCATED
903:
904: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
905: is done just by pretending it is already truncated. */
906: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
907:
908: /* We assume that the store-condition-codes instructions store 0 for false
909: and some other value for true. This is the value stored for true. */
910:
911: #define STORE_FLAG_VALUE -1
912:
913: /* When a prototype says `char' or `short', really pass an `int'. */
914: #define PROMOTE_PROTOTYPES
915:
916: /* Specify the machine mode that pointers have.
917: After generation of rtl, the compiler makes no further distinction
918: between pointers and any other objects of this machine mode. */
919: #define Pmode SImode
920:
921: /* A function address in a call instruction
922: is a byte address (for indexing purposes)
923: so give the MEM rtx a byte's mode. */
924: #define FUNCTION_MODE QImode
925:
926: /* Compute the cost of computing a constant rtl expression RTX
927: whose rtx-code is CODE. The body of this macro is a portion
928: of a switch statement. If the code is computed here,
929: return it with a return statement. Otherwise, break from the switch. */
930:
931: #define CONST_COSTS(RTX,CODE) \
932: case CONST_INT: \
933: /* Constant zero is super cheap due to clr instruction. */ \
934: if (RTX == const0_rtx) return 0; \
935: if ((unsigned) INTVAL (RTX) < 077) return 1; \
936: case CONST: \
937: case LABEL_REF: \
938: case SYMBOL_REF: \
939: return 3; \
940: case CONST_DOUBLE: \
941: return 5;
942:
943: /* Tell final.c how to eliminate redundant test instructions. */
944:
945: /* Here we define machine-dependent flags and fields in cc_status
946: (see `conditions.h'). */
947:
948: /* On the Alliant, floating-point instructions do not modify the
949: ordinary CC register. Only fcmp and ftest instructions modify the
950: floating-point CC register. We should actually keep track of what
951: both kinds of CC registers contain, but for now we only consider
952: the most recent instruction that has set either register. */
953:
954: /* Set if the cc value came from a floating point test, so a floating
955: point conditional branch must be output. */
956: #define CC_IN_68881 04000
957:
958: /* Store in cc_status the expressions
959: that the condition codes will describe
960: after execution of an instruction whose pattern is EXP.
961: Do not alter them if the instruction would not alter the cc's. */
962:
963: /* On the 68000, all the insns to store in an address register
964: fail to set the cc's. However, in some cases these instructions
965: can make it possibly invalid to use the saved cc's. In those
966: cases we clear out some or all of the saved cc's so they won't be used. */
967:
968: #define NOTICE_UPDATE_CC(EXP, INSN) \
969: { \
970: if (GET_CODE (EXP) == SET) \
971: { if (ADDRESS_REG_P (XEXP (EXP, 0))) \
972: { if (cc_status.value1 \
973: && reg_overlap_mentioned_p (XEXP (EXP, 0), cc_status.value1)) \
974: cc_status.value1 = 0; \
975: if (cc_status.value2 \
976: && reg_overlap_mentioned_p (XEXP (EXP, 0), cc_status.value2)) \
977: cc_status.value2 = 0; } \
978: else if (FP_REG_P (XEXP (EXP,0)) \
979: || (FP_REG_P (XEXP (EXP,1)) \
980: && XEXP (EXP, 0) != cc0_rtx)) \
981: { } \
982: else if (!FP_REG_P (XEXP (EXP, 0)) \
983: && XEXP (EXP, 0) != cc0_rtx \
984: && (FP_REG_P (XEXP (EXP, 1)) \
985: || GET_CODE (XEXP (EXP, 1)) == FIX \
986: || GET_CODE (XEXP (EXP, 1)) == FLOAT_TRUNCATE \
987: || GET_CODE (XEXP (EXP, 1)) == FLOAT_EXTEND)) \
988: { CC_STATUS_INIT; } \
989: else if (GET_CODE (SET_SRC (EXP)) == CALL) \
990: { CC_STATUS_INIT; } \
991: else if (XEXP (EXP, 0) != pc_rtx) \
992: { cc_status.flags = 0; \
993: cc_status.value1 = XEXP (EXP, 0); \
994: cc_status.value2 = XEXP (EXP, 1); } } \
995: else if (GET_CODE (EXP) == PARALLEL \
996: && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \
997: { \
998: if (ADDRESS_REG_P (XEXP (XVECEXP (EXP, 0, 0), 0))) \
999: CC_STATUS_INIT; \
1000: else if (XEXP (XVECEXP (EXP, 0, 0), 0) != pc_rtx) \
1001: { cc_status.flags = 0; \
1002: cc_status.value1 = XEXP (XVECEXP (EXP, 0, 0), 0); \
1003: cc_status.value2 = XEXP (XVECEXP (EXP, 0, 0), 1); } } \
1004: else CC_STATUS_INIT; \
1005: if (cc_status.value2 != 0 \
1006: && ADDRESS_REG_P (cc_status.value2) \
1007: && GET_MODE (cc_status.value2) == QImode) \
1008: CC_STATUS_INIT; \
1009: if (cc_status.value2 != 0 \
1010: && !(cc_status.value1 && FPA_REG_P (cc_status.value1))) \
1011: switch (GET_CODE (cc_status.value2)) \
1012: { case PLUS: case MINUS: case MULT: case UMULT: \
1013: case DIV: case UDIV: case MOD: case UMOD: case NEG: \
1014: case ASHIFT: case LSHIFT: case ASHIFTRT: case LSHIFTRT: \
1015: case ROTATE: case ROTATERT: \
1016: if (GET_MODE (cc_status.value2) != VOIDmode) \
1017: cc_status.flags |= CC_NO_OVERFLOW; \
1018: break; \
1019: case ZERO_EXTEND: \
1020: /* (SET r1 (ZERO_EXTEND r2)) on this machine
1021: ends with a move insn moving r2 in r2's mode.
1022: Thus, the cc's are set for r2.
1023: This can set N bit spuriously. */ \
1024: cc_status.flags |= CC_NOT_NEGATIVE; } \
1025: if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \
1026: && cc_status.value2 \
1027: && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \
1028: cc_status.value2 = 0; \
1029: if ((cc_status.value1 && FP_REG_P (cc_status.value1)) \
1030: || (cc_status.value2 && FP_REG_P (cc_status.value2))) \
1031: cc_status.flags = CC_IN_68881; }
1032:
1033: #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1034: { if (cc_prev_status.flags & CC_IN_68881) \
1035: return FLOAT; \
1036: if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1037: return NO_OV; \
1038: return NORMAL; }
1039:
1040: /* Control the assembler format that we output. */
1041:
1042: /* Output at beginning of assembler file. */
1043:
1044: #define ASM_FILE_START(FILE) fprintf (FILE, "#NO_APP\n");
1045:
1046: /* Output to assembler file text saying following lines
1047: may contain character constants, extra white space, comments, etc. */
1048:
1049: #define ASM_APP_ON "#APP\n"
1050:
1051: /* Output to assembler file text saying following lines
1052: no longer contain unusual constructs. */
1053:
1054: #define ASM_APP_OFF "#NO_APP\n"
1055:
1056: /* Output before read-only data. */
1057:
1058: #define TEXT_SECTION_ASM_OP "\t.text"
1059:
1060: /* Output before writable data. */
1061:
1062: #define DATA_SECTION_ASM_OP "\t.data"
1063:
1064: /* How to refer to registers in assembler output.
1065: This sequence is indexed by compiler's hard-register-number (see above). */
1066:
1067: #define REGISTER_NAMES \
1068: {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1069: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1070: "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1071:
1072: /* How to renumber registers for dbx and gdb.
1073: On the Sun-3, the floating point registers have numbers
1074: 18 to 25, not 16 to 23 as they do in the compiler. */
1075:
1076: #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1077:
1078: /* This is how to output the definition of a user-level label named NAME,
1079: such as the label on a static function or variable NAME. */
1080:
1081: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1082: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1083:
1084: /* This is how to output a command to make the user-level label named NAME
1085: defined for reference from other files. */
1086:
1087: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1088: do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1089:
1090: /* This is how to output a reference to a user-level label named NAME.
1091: `assemble_name' uses this. */
1092:
1093: #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1094: fprintf (FILE, "_%s", NAME)
1095:
1096: /* This is how to output an internal numbered label where
1097: PREFIX is the class of label and NUM is the number within the class. */
1098:
1099: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1100: fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1101:
1102: /* This is how to store into the string LABEL
1103: the symbol_ref name of an internal numbered label where
1104: PREFIX is the class of label and NUM is the number within the class.
1105: This is suitable for output with `assemble_name'. */
1106:
1107: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1108: sprintf (LABEL, "*%s%d", PREFIX, NUM)
1109:
1110: /* This is how to output an assembler line defining a `double' constant. */
1111:
1112: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1113: do { union { double d; long v[2];} tem; \
1114: tem.d = (VALUE); \
1115: fprintf (FILE, "\t.long 0x%x,0x%x\n", tem.v[0], tem.v[1]); \
1116: } while (0)
1117:
1118: /* This is how to output an assembler line defining a `float' constant. */
1119:
1120: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1121: do { union { float f; long l;} tem; \
1122: tem.f = (VALUE); \
1123: fprintf (FILE, "\t.long 0x%x\n", tem.l); \
1124: } while (0)
1125:
1126: /* This is how to output an assembler line defining an `int' constant. */
1127:
1128: #define ASM_OUTPUT_INT(FILE,VALUE) \
1129: ( fprintf (FILE, "\t.long "), \
1130: output_addr_const (FILE, (VALUE)), \
1131: fprintf (FILE, "\n"))
1132:
1133: /* Likewise for `char' and `short' constants. */
1134:
1135: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1136: ( fprintf (FILE, "\t.word "), \
1137: output_addr_const (FILE, (VALUE)), \
1138: fprintf (FILE, "\n"))
1139:
1140: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1141: ( fprintf (FILE, "\t.byte "), \
1142: output_addr_const (FILE, (VALUE)), \
1143: fprintf (FILE, "\n"))
1144:
1145: #define ASM_OUTPUT_ASCII(FILE,PTR,SIZE) \
1146: { int i; unsigned char *pp = (unsigned char *) PTR; \
1147: fprintf(FILE, "\t.byte %d", (unsigned int)*pp++); \
1148: for (i = 1; i < SIZE; ++i, ++pp) { \
1149: if ((i % 8) == 0) \
1150: fprintf(FILE, "\n\t.byte %d", (unsigned int) *pp); \
1151: else \
1152: fprintf(FILE, ",%d", (unsigned int) *pp); } \
1153: fprintf (FILE, "\n"); }
1154:
1155: /* This is how to output an assembler line for a numeric constant byte. */
1156:
1157: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1158: fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1159:
1160: /* This is how to output an insn to push a register on the stack.
1161: It need not be very fast code. */
1162:
1163: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1164: fprintf (FILE, "\tmovl %s,sp@-\n", reg_names[REGNO])
1165:
1166: /* This is how to output an insn to pop a register from the stack.
1167: It need not be very fast code. */
1168:
1169: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1170: fprintf (FILE, "\tmovl sp@+,%s\n", reg_names[REGNO])
1171:
1172: /* This is how to output an element of a case-vector that is absolute.
1173: (The 68000 does not use such vectors,
1174: but we must define this macro anyway.) */
1175:
1176: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1177: fprintf (FILE, "\t.long L%d\n", VALUE)
1178:
1179: /* This is how to output an element of a case-vector that is relative. */
1180:
1181: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1182: fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1183:
1184: /* This is how to output an assembler line
1185: that says to advance the location counter
1186: to a multiple of 2**LOG bytes. */
1187:
1188: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1189: if ((LOG) == 1) \
1190: fprintf (FILE, "\t.even\n"); \
1191: else if ((LOG) != 0) \
1192: fprintf (FILE, "\t.align %dn", (LOG));
1193:
1194: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1195: fprintf (FILE, "\t. = . + %d\n", (SIZE))
1196:
1197: /* This says how to output an assembler line
1198: to define a global common symbol. */
1199:
1200: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1201: ( fputs ("\t.comm ", (FILE)), \
1202: assemble_name ((FILE), (NAME)), \
1203: fprintf ((FILE), ",%d\n", (ROUNDED)))
1204:
1205: /* This says how to output an assembler line
1206: to define a local common symbol. */
1207:
1208: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1209: ( fputs ("\t.lcomm ", (FILE)), \
1210: assemble_name ((FILE), (NAME)), \
1211: fprintf ((FILE), ",%d\n", (ROUNDED)))
1212:
1213: /* Store in OUTPUT a string (made with alloca) containing
1214: an assembler-name for a local static variable named NAME.
1215: LABELNO is an integer which is different for each call. */
1216:
1217: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1218: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1219: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1220:
1221: /* Define the parentheses used to group arithmetic operations
1222: in assembler code. */
1223:
1224: #define ASM_OPEN_PAREN "("
1225: #define ASM_CLOSE_PAREN ")"
1226:
1227: /* Define results of standard character escape sequences. */
1228: #define TARGET_BELL 007
1229: #define TARGET_BS 010
1230: #define TARGET_TAB 011
1231: #define TARGET_NEWLINE 012
1232: #define TARGET_VT 013
1233: #define TARGET_FF 014
1234: #define TARGET_CR 015
1235:
1236: /* Print operand X (an rtx) in assembler syntax to file FILE.
1237: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1238: For `%' followed by punctuation, CODE is the punctuation and X is null.
1239:
1240: On the 68000, we use several CODE characters:
1241: 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1242: 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1243: '.' for dot needed in Motorola-style opcode names.
1244: '-' for an operand pushing on the stack:
1245: sp@-, -(sp) or -(%sp) depending on the style of syntax.
1246: '+' for an operand pushing on the stack:
1247: sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1248: 's' for a reference to the top word on the stack:
1249: sp@, (sp) or (%sp) depending on the style of syntax.
1250: '#' for an immediate operand prefix (# in MIT and Motorola syntax
1251: but & in SGS syntax).
1252: '!' for the cc register (used in an `and to cc' insn).
1253:
1254: 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
1255: than directly). Second part of 'y' below.
1256: 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1257: or print pair of registers as rx:ry.
1258: 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
1259: CONST_DOUBLE's as SunFPA constant RAM registers if
1260: possible, so it should not be used except for the SunFPA. */
1261:
1262: #define PRINT_OPERAND(FILE, X, CODE) \
1263: { int i; \
1264: if (CODE == '.') ; \
1265: else if (CODE == '#') fprintf (FILE, "#"); \
1266: else if (CODE == '-') fprintf (FILE, "sp@-"); \
1267: else if (CODE == '+') fprintf (FILE, "sp@+"); \
1268: else if (CODE == 's') fprintf (FILE, "sp@"); \
1269: else if (CODE == '!') fprintf (FILE, "cc"); \
1270: else if ((X) == 0 ) ; \
1271: else if (GET_CODE (X) == REG) \
1272: { if (REGNO (X) < 16 && (CODE == 'y' || CODE == 'x') && GET_MODE (X) == DFmode) \
1273: fprintf (FILE, "%s,%s", reg_name [REGNO (X)], reg_name [REGNO (X)+1]); \
1274: else \
1275: fprintf (FILE, "%s", reg_name[REGNO (X)]); \
1276: } \
1277: else if (GET_CODE (X) == MEM) \
1278: output_address (XEXP (X, 0)); \
1279: else if ((CODE == 'y' || CODE == 'w') \
1280: && GET_CODE(X) == CONST_DOUBLE \
1281: && (i = standard_SunFPA_constant_p (X))) \
1282: fprintf(FILE, "%%%d", i & 0x1ff); \
1283: else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \
1284: { union { double d; int i[2]; } u; \
1285: union { float f; int i; } u1; \
1286: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1287: u1.f = u.d; \
1288: if (CODE == 'f') \
1289: fprintf (FILE, "#0r%.9g", u1.f); \
1290: else \
1291: fprintf (FILE, "#0x%x", u1.i[0]); } \
1292: else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != DImode) \
1293: { union { double d; int i[2]; } u; \
1294: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1295: fprintf (FILE, "#0r%.20g", u.d); } \
1296: else { putc ('#', FILE); output_addr_const (FILE, X); }}
1297:
1298: /* Note that this contains a kludge that knows that the only reason
1299: we have an address (plus (label_ref...) (reg...))
1300: is in the insn before a tablejump, and we know that m68k.md
1301: generates a label LInnn: on such an insn. */
1302: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1303: { register rtx reg1, reg2, breg, ireg; \
1304: register rtx addr = ADDR; \
1305: static char *sz = ".BW.L...D"; \
1306: rtx offset; \
1307: switch (GET_CODE (addr)) \
1308: { \
1309: case REG: \
1310: fprintf (FILE, "%s@", reg_name [REGNO (addr)]); \
1311: break; \
1312: case PRE_DEC: \
1313: fprintf (FILE, "%s@-", reg_name [REGNO (XEXP (addr, 0))]); \
1314: break; \
1315: case POST_INC: \
1316: fprintf (FILE, "%s@+", reg_name [REGNO (XEXP (addr, 0))]); \
1317: break; \
1318: case PLUS: \
1319: reg1 = 0; reg2 = 0; \
1320: ireg = 0; breg = 0; \
1321: offset = 0; \
1322: if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \
1323: { \
1324: offset = XEXP (addr, 0); \
1325: addr = XEXP (addr, 1); \
1326: } \
1327: else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \
1328: { \
1329: offset = XEXP (addr, 1); \
1330: addr = XEXP (addr, 0); \
1331: } \
1332: if (GET_CODE (addr) != PLUS) ; \
1333: else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \
1334: { \
1335: reg1 = XEXP (addr, 0); \
1336: addr = XEXP (addr, 1); \
1337: } \
1338: else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \
1339: { \
1340: reg1 = XEXP (addr, 1); \
1341: addr = XEXP (addr, 0); \
1342: } \
1343: else if (GET_CODE (XEXP (addr, 0)) == MULT) \
1344: { \
1345: reg1 = XEXP (addr, 0); \
1346: addr = XEXP (addr, 1); \
1347: } \
1348: else if (GET_CODE (XEXP (addr, 1)) == MULT) \
1349: { \
1350: reg1 = XEXP (addr, 1); \
1351: addr = XEXP (addr, 0); \
1352: } \
1353: else if (GET_CODE (XEXP (addr, 0)) == REG) \
1354: { \
1355: reg1 = XEXP (addr, 0); \
1356: addr = XEXP (addr, 1); \
1357: } \
1358: else if (GET_CODE (XEXP (addr, 1)) == REG) \
1359: { \
1360: reg1 = XEXP (addr, 1); \
1361: addr = XEXP (addr, 0); \
1362: } \
1363: if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \
1364: || GET_CODE (addr) == SIGN_EXTEND) \
1365: { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \
1366: /* for OLD_INDEXING \
1367: else if (GET_CODE (addr) == PLUS) \
1368: { \
1369: if (GET_CODE (XEXP (addr, 0)) == REG) \
1370: { \
1371: reg2 = XEXP (addr, 0); \
1372: addr = XEXP (addr, 1); \
1373: } \
1374: else if (GET_CODE (XEXP (addr, 1)) == REG) \
1375: { \
1376: reg2 = XEXP (addr, 1); \
1377: addr = XEXP (addr, 0); \
1378: } \
1379: } \
1380: */ \
1381: if (offset != 0) { if (addr != 0) abort (); addr = offset; } \
1382: if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \
1383: || GET_CODE (reg1) == MULT)) \
1384: || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \
1385: { breg = reg2; ireg = reg1; } \
1386: else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \
1387: { breg = reg1; ireg = reg2; } \
1388: if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \
1389: { int scale = 1; \
1390: if (GET_CODE (ireg) == MULT) \
1391: { scale = INTVAL (XEXP (ireg, 1)); \
1392: ireg = XEXP (ireg, 0); } \
1393: if (GET_CODE (ireg) == SIGN_EXTEND) \
1394: fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:W", \
1395: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1396: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1397: reg_name[REGNO (XEXP (ireg, 0))]); \
1398: else \
1399: fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L", \
1400: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1401: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1402: reg_name[REGNO (ireg)]); \
1403: fprintf (FILE, ":%c", sz[scale]); \
1404: putc (']', FILE); \
1405: break; } \
1406: if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \
1407: { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \
1408: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1409: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1410: reg_name[REGNO (breg)]); \
1411: break; } \
1412: if (ireg != 0 || breg != 0) \
1413: { int scale = 1; \
1414: if (breg == 0) \
1415: abort (); \
1416: if (addr && GET_CODE (addr) == LABEL_REF) abort (); \
1417: fprintf (FILE, "%s@", reg_name[REGNO (breg)]); \
1418: if (addr != 0) { \
1419: putc( '(', FILE ); \
1420: output_addr_const (FILE, addr); \
1421: if (ireg != 0) { \
1422: if (GET_CODE(addr) == CONST_INT) { \
1423: int size_of = 1, val = INTVAL(addr); \
1424: if (val < -0x8000 || val >= 0x8000) \
1425: size_of = 4; \
1426: else if (val < -0x80 || val >= 0x80) \
1427: size_of = 2; \
1428: fprintf(FILE, ":%c", sz[size_of]); \
1429: } \
1430: else \
1431: fprintf(FILE, ":L"); } \
1432: putc( ')', FILE ); } \
1433: if (ireg != 0) { \
1434: putc ('[', FILE); \
1435: if (ireg != 0 && GET_CODE (ireg) == MULT) \
1436: { scale = INTVAL (XEXP (ireg, 1)); \
1437: ireg = XEXP (ireg, 0); } \
1438: if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \
1439: fprintf (FILE, "%s:W", reg_name[REGNO (XEXP (ireg, 0))]); \
1440: else if (ireg != 0) \
1441: fprintf (FILE, "%s:L", reg_name[REGNO (ireg)]); \
1442: fprintf (FILE, ":%c", sz[scale]); \
1443: putc (']', FILE); \
1444: } \
1445: break; \
1446: } \
1447: else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \
1448: { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \
1449: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1450: CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1451: reg_name[REGNO (reg1)]); \
1452: break; } \
1453: default: \
1454: if (GET_CODE (addr) == CONST_INT \
1455: && INTVAL (addr) < 0x8000 \
1456: && INTVAL (addr) >= -0x8000) \
1457: fprintf (FILE, "%d:W", INTVAL (addr)); \
1458: else \
1459: output_addr_const (FILE, addr); \
1460: }}
1461:
1462: /*
1463: Local variables:
1464: version-control: t
1465: End:
1466: */
1467: /* See tm-m68k.h. 3 means 68020 with 68881. */
1468:
1469: #define TARGET_DEFAULT 3
1470:
1471: /* Define __HAVE_FPA__ or __HAVE_68881__ in preprocessor,
1472: according to the -m flags.
1473: This will control the use of inline 68881 insns in certain macros.
1474: Also inform the program which CPU this is for. */
1475:
1476: #if TARGET_DEFAULT & 02
1477:
1478: /* -m68881 is the default */
1479: #define CPP_SPEC \
1480: "%{!msoft-float:%{mfpa:-D__HAVE_FPA__ }%{!mfpa:-D__HAVE_68881__ }}\
1481: %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
1482:
1483: #else
1484: #if TARGET_DEFAULT & 0100
1485:
1486: /* -mfpa is the default */
1487: #define CPP_SPEC \
1488: "%{!msoft-float:%{m68881:-D__HAVE_68881__ }%{!m68881:-D__HAVE_FPA__ }}\
1489: %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
1490:
1491: #else
1492:
1493: /* -msoft-float is the default */
1494: #define CPP_SPEC \
1495: "%{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }\
1496: %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
1497:
1498: #endif
1499: #endif
1500:
1501: /* Names to predefine in the preprocessor for this target machine. */
1502:
1503: #define CPP_PREDEFINES "-Dmc68000 -Dalliant -Dunix"
1504:
1505: /* Every structure or union's size must be a multiple of 2 bytes. */
1506:
1507: #define STRUCTURE_SIZE_BOUNDARY 16
1508:
1509: /* This is BSD, so it wants DBX format. */
1510:
1511: #define DBX_DEBUGGING_INFO
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