![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to tm-alliant.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GCC 1.x] / gcc|
Return to tm-alliant.h CVS log | Up to [GCC 1.x] / gcc |
1.1 root 1: /* Definitions of target machine for GNU compiler. Alliant FX/8 version. 1.1.1.2 ! root 2: Copyright (C) 1987, 1989 Free Software Foundation, Inc. 1.1 root 3: 4: This file is part of GNU CC. 5: 1.1.1.2 ! root 6: GNU CC is free software; you can redistribute it and/or modify ! 7: it under the terms of the GNU General Public License as published by ! 8: the Free Software Foundation; either version 1, or (at your option) ! 9: any later version. ! 10: 1.1 root 11: GNU CC is distributed in the hope that it will be useful, 1.1.1.2 ! root 12: but WITHOUT ANY WARRANTY; without even the implied warranty of ! 13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 14: GNU General Public License for more details. ! 15: ! 16: You should have received a copy of the GNU General Public License ! 17: along with GNU CC; see the file COPYING. If not, write to ! 18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 1.1 root 19: 20: 21: /* Note that some other tm- files include this one and then override 22: many of the definitions that relate to assembler syntax. */ 23: 24: 25: /* Names to predefine in the preprocessor for this target machine. */ 26: 27: /* See tm-sun3.h, tm-sun2.h, tm-isi68.h for different CPP_PREDEFINES. */ 28: 29: /* Print subsidiary information on the compiler version in use. */ 30: #ifdef MOTOROLA 31: #define TARGET_VERSION printf (" (68k, Motorola syntax)"); 32: #else 33: #define TARGET_VERSION printf (" (68k, MIT syntax)"); 34: #endif 35: 36: /* Run-time compilation parameters selecting different hardware subsets. */ 37: 38: extern int target_flags; 39: 40: /* Macros used in the machine description to test the flags. */ 41: 42: /* Compile for a 68020 (not a 68000 or 68010). */ 43: #define TARGET_68020 (target_flags & 1) 44: /* Compile 68881 insns for floating point (not library calls). */ 45: #define TARGET_68881 (target_flags & 2) 46: /* Compile using 68020 bitfield insns. */ 47: #define TARGET_BITFIELD (target_flags & 4) 48: /* Compile using rtd insn calling sequence. 49: This will not work unless you use prototypes at least 50: for all functions that can take varying numbers of args. */ 51: #define TARGET_RTD (target_flags & 8) 52: /* Compile passing first two args in regs 0 and 1. 53: This exists only to test compiler features that will 54: be needed for RISC chips. It is not usable 55: and is not intended to be usable on this cpu. */ 56: #define TARGET_REGPARM (target_flags & 020) 57: /* Compile with 16-bit `int'. */ 58: #define TARGET_SHORT (target_flags & 040) 59: 60: /* Compile with special insns for Sun FPA. */ 61: #define TARGET_FPA (target_flags & 0100) 62: 63: /* Macro to define tables used to set the flags. 64: This is a list in braces of pairs in braces, 65: each pair being { "NAME", VALUE } 66: where VALUE is the bits to set or minus the bits to clear. 67: An empty string NAME is used to identify the default VALUE. */ 68: 69: #define TARGET_SWITCHES \ 70: { { "68020", 5}, \ 71: { "c68020", 5}, \ 72: { "68881", 2}, \ 73: { "bitfield", 4}, \ 74: { "68000", -5}, \ 75: { "c68000", -5}, \ 76: { "soft-float", -0102}, \ 77: { "nobitfield", -4}, \ 78: { "rtd", 8}, \ 79: { "nortd", -8}, \ 80: { "short", 040}, \ 81: { "noshort", -040}, \ 82: { "fpa", 0100}, \ 83: { "nofpa", -0100}, \ 84: { "", TARGET_DEFAULT}} 85: 86: /* TARGET_DEFAULT is defined in tm-sun*.h and tm-isi68.h, etc. */ 87: 88: /* Blow away 68881 flag silently on TARGET_FPA (since we can't clear 89: any bits in TARGET_SWITCHES above) */ 90: #define OVERRIDE_OPTIONS \ 91: { \ 92: if (TARGET_FPA) target_flags &= ~2; \ 93: } 94: 95: /* target machine storage layout */ 96: 97: /* Define this if most significant bit is lowest numbered 98: in instructions that operate on numbered bit-fields. 99: This is true for 68020 insns such as bfins and bfexts. 100: We make it true always by avoiding using the single-bit insns 101: except in special cases with constant bit numbers. */ 102: #define BITS_BIG_ENDIAN 103: 104: /* Define this if most significant byte of a word is the lowest numbered. */ 105: /* That is true on the 68000. */ 106: #define BYTES_BIG_ENDIAN 107: 108: /* Define this if most significant word of a multiword number is numbered. */ 109: /* For 68000 we can decide arbitrarily 110: since there are no machine instructions for them. */ 111: /* #define WORDS_BIG_ENDIAN */ 112: 113: /* number of bits in an addressible storage unit */ 114: #define BITS_PER_UNIT 8 115: 116: /* Width in bits of a "word", which is the contents of a machine register. 117: Note that this is not necessarily the width of data type `int'; 118: if using 16-bit ints on a 68000, this would still be 32. 119: But on a machine with 16-bit registers, this would be 16. */ 120: #define BITS_PER_WORD 32 121: 122: /* Width of a word, in units (bytes). */ 123: #define UNITS_PER_WORD 4 124: 125: /* Width in bits of a pointer. 126: See also the macro `Pmode' defined below. */ 127: #define POINTER_SIZE 32 128: 129: /* Allocation boundary (in *bits*) for storing pointers in memory. */ 130: #define POINTER_BOUNDARY 16 131: 132: /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 133: #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) 134: 135: /* Boundary (in *bits*) on which stack pointer should be aligned. */ 136: #define STACK_BOUNDARY 16 137: 138: /* Allocation boundary (in *bits*) for the code of a function. */ 139: #define FUNCTION_BOUNDARY 16 140: 141: /* Alignment of field after `int : 0' in a structure. */ 142: #define EMPTY_FIELD_BOUNDARY 16 143: 144: /* No data type wants to be aligned rounder than this. */ 145: #define BIGGEST_ALIGNMENT 16 146: 147: /* Define this if move instructions will actually fail to work 148: when given unaligned data. */ 149: #define STRICT_ALIGNMENT 150: 151: /* Define number of bits in most basic integer type. 152: (If undefined, default is BITS_PER_WORD). */ 153: 154: #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) 155: 156: /* Standard register usage. */ 157: 158: /* Number of actual hardware registers. 159: The hardware registers are assigned numbers for the compiler 160: from 0 to just below FIRST_PSEUDO_REGISTER. 161: All registers that the compiler knows about must be given numbers, 162: even those that are not normally considered general registers. 163: For the 68000, we give the data registers numbers 0-7, 164: the address registers numbers 010-017, 165: and the 68881 floating point registers numbers 020-027. */ 166: #define FIRST_PSEUDO_REGISTER 56 167: 168: /* 1 for registers that have pervasive standard uses 169: and are not available for the register allocator. 170: On the 68000, only the stack pointer is such. */ 171: /* fpa0 is also reserved so that it can be used to move shit back and 172: forth between high fpa regs and everything else. */ 173: #define FIXED_REGISTERS \ 174: {0, 0, 0, 0, 0, 0, 0, 0, \ 175: 1, 0, 0, 0, 0, 0, 1, 1, \ 176: 0, 0, 0, 0, 0, 0, 0, 0 } 177: 178: /* 1 for registers not available across function calls. 179: These must include the FIXED_REGISTERS and also any 180: registers that can be used without being saved. 181: The latter must include the registers where values are returned 182: and the register where structure-value addresses are passed. 183: Aside from that, you can include as many other registers as you like. */ 184: 185: #define CALL_USED_REGISTERS \ 186: {1, 1, 1, 1, 1, 1, 1, 1, \ 187: 1, 1, 1, 1, 1, 1, 1, 1, \ 188: 1, 1, 1, 1, 1, 1, 1, 1 } 189: 190: /* Make sure everything's fine if we *don't* have a given processor. 191: This assumes that putting a register in fixed_regs will keep the 192: compilers mitt's completely off it. We don't bother to zero it out 193: of register classes. If neither TARGET_FPA or TARGET_68881 is set, 194: the compiler won't touch since no instructions that use these 195: registers will be valid. */ 196: #define CONDITIONAL_REGISTER_USAGE \ 197: { \ 198: int i; \ 199: HARD_REG_SET x; \ 200: if (!TARGET_FPA) \ 201: { \ 202: COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \ 203: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ 204: if (TEST_HARD_REG_BIT (x, i)) \ 205: fixed_regs[i] = call_used_regs[i] = 1; \ 206: } \ 207: } 208: 209: /* Return number of consecutive hard regs needed starting at reg REGNO 210: to hold something of mode MODE. 211: This is ordinarily the length in words of a value of mode MODE 212: but can be less for certain modes in special long registers. 213: 214: On the 68000, ordinary registers hold 32 bits worth; 215: for the 68881 registers, a single register is always enough for 216: anything that can be stored in them at all. */ 217: #define HARD_REGNO_NREGS(REGNO, MODE) \ 218: ((REGNO) >= 16 ? 1 \ 219: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 220: 221: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 222: On the 68000, the cpu registers can hold any mode but the 68881 registers 223: can hold only SFmode or DFmode. And the 68881 registers can't hold anything 224: if 68881 use is disabled. However, the Sun FPA register can 225: (apparently) hold whatever you feel like putting in them. */ 226: #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 227: ((REGNO) < 16 \ 228: || ((REGNO) < 24 \ 229: ? TARGET_68881 && ((MODE) == SFmode || (MODE) == DFmode) \ 230: : ((REGNO) < 56 \ 231: ? TARGET_FPA : 0))) 232: 233: /* Value is 1 if it is a good idea to tie two pseudo registers 234: when one has mode MODE1 and one has mode MODE2. 235: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 236: for any hard reg, then this must be 0 for correct output. */ 237: #define MODES_TIEABLE_P(MODE1, MODE2) \ 238: (! TARGET_68881 \ 239: || (((MODE1) == SFmode || (MODE1) == DFmode) \ 240: == ((MODE2) == SFmode || (MODE2) == DFmode))) 241: 242: /* Specify the registers used for certain standard purposes. 243: The values of these macros are register numbers. */ 244: 245: /* m68000 pc isn't overloaded on a register. */ 246: /* #define PC_REGNUM */ 247: 248: /* Register to use for pushing function arguments. */ 249: #define STACK_POINTER_REGNUM 15 250: 251: /* Base register for access to local variables of the function. */ 252: #define FRAME_POINTER_REGNUM 14 253: 254: /* Value should be nonzero if functions must have frame pointers. 255: Zero means the frame pointer need not be set up (and parms 256: may be accessed via the stack pointer) in functions that seem suitable. 257: This is computed in `reload', in reload1.c. */ 258: #define FRAME_POINTER_REQUIRED 1 259: 260: /* Base register for access to arguments of the function. */ 261: #define ARG_POINTER_REGNUM 8 262: 263: /* Register in which static-chain is passed to a function. */ 264: #define STATIC_CHAIN_REGNUM 8 265: 266: /* Register in which address to store a structure value 267: is passed to a function. */ 268: #define STRUCT_VALUE_REGNUM 9 269: 270: /* Define the classes of registers for register constraints in the 271: machine description. Also define ranges of constants. 272: 273: One of the classes must always be named ALL_REGS and include all hard regs. 274: If there is more than one class, another class must be named NO_REGS 275: and contain no registers. 276: 277: The name GENERAL_REGS must be the name of a class (or an alias for 278: another name such as ALL_REGS). This is the class of registers 279: that is allowed by "g" or "r" in a register constraint. 280: Also, registers outside this class are allocated only when 281: instructions express preferences for them. 282: 283: The classes must be numbered in nondecreasing order; that is, 284: a larger-numbered class must never be contained completely 285: in a smaller-numbered class. 286: 287: For any two classes, it is very desirable that there be another 288: class that represents their union. */ 289: 290: /* The 68000 has three kinds of registers, so eight classes would be 291: a complete set. One of them is not needed. */ 292: 293: /* 294: * Notes on final choices: 295: * 296: * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything 297: * else. 298: * 2) Removed all unions that involve address registers with 299: * floating point registers (left in unions of address and data with 300: * floating point). 301: * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS. 302: * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS. 303: * 4) Left in everything else. 304: */ 305: enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS, 306: FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS, 307: DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS, 308: GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS, 309: LIM_REG_CLASSES }; 310: 311: #define N_REG_CLASSES (int) LIM_REG_CLASSES 312: 313: /* Give names of register classes as strings for dump file. */ 314: 315: #define REG_CLASS_NAMES \ 316: { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \ 317: "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \ 318: "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \ 319: "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" } 320: 321: /* Define which registers fit in which classes. 322: This is an initializer for a vector of HARD_REG_SET 323: of length N_REG_CLASSES. */ 324: 325: #define REG_CLASS_CONTENTS \ 326: { \ 327: {0, 0}, /* NO_REGS */ \ 328: {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \ 329: {0xff000000, 0x00ffffff}, /* FPA_REGS */ \ 330: {0x00ff0000, 0x00000000}, /* FP_REGS */ \ 331: {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \ 332: {0x000000ff, 0x00000000}, /* DATA_REGS */ \ 333: {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \ 334: {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \ 335: {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\ 336: {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \ 337: {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \ 338: {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\ 339: {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\ 340: {0xffffffff, 0x00ffffff} /* ALL_REGS */ \ 341: } 342: 343: /* The same information, inverted: 344: Return the class number of the smallest class containing 345: reg number REGNO. This could be a conditional expression 346: or could index an array. */ 347: 348: extern enum reg_class regno_reg_class[]; 349: #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3]) 350: 351: /* The class value for index registers, and the one for base regs. */ 352: 353: #define INDEX_REG_CLASS GENERAL_REGS 354: #define BASE_REG_CLASS ADDR_REGS 355: 356: /* Get reg_class from a letter such as appears in the machine description. 357: We do a trick here to modify the effective constraints on the 358: machine description; we zorch the constraint letters that aren't 359: appropriate for a specific target. This allows us to guarrantee 360: that a specific kind of register will not be used for a given taget 361: without fiddling with the register classes above. */ 362: 363: #define REG_CLASS_FROM_LETTER(C) \ 364: ((C) == 'a' ? ADDR_REGS : \ 365: ((C) == 'd' ? DATA_REGS : \ 366: ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ 367: NO_REGS) : \ 368: ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \ 369: NO_REGS) : \ 370: ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \ 371: NO_REGS) : \ 372: NO_REGS))))) 373: 374: /* The letters I, J, K, L and M in a register constraint string 375: can be used to stand for particular ranges of immediate operands. 376: This macro defines what the ranges are. 377: C is the letter, and VALUE is a constant value. 378: Return 1 if VALUE is in the range specified by C. 379: 380: For the 68000, `I' is used for the range 1 to 8 381: allowed as immediate shift counts and in addq. 382: `J' is used for the range of signed numbers that fit in 16 bits. 383: `K' is for numbers that moveq can't handle. 384: `L' is for range -8 to -1, range of values that can be added with subq. */ 385: 386: #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 387: ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ 388: (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ 389: (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ 390: (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0) 391: 392: /* 393: * A small bit of explanation: 394: * "G" defines all of the floating constants that are *NOT* 68881 395: * constants. this is so 68881 constants get reloaded and the 396: * fpmovecr is used. "H" defines *only* the class of constants that 397: * the fpa can use, because these can be gotten at in any fpa 398: * instruction and there is no need to force reloads. 399: */ 400: 401: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0 402: 403: /* Given an rtx X being reloaded into a reg required to be 404: in class CLASS, return the class of reg to actually use. 405: In general this is just CLASS; but on some machines 406: in some cases it is preferable to use a more restrictive class. 407: On the 68000 series, use a data reg if possible when the 408: value is a constant in the range where moveq could be used 409: and we ensure that QImodes are reloaded into data regs. */ 410: 411: #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 412: ((GET_CODE (X) == CONST_INT \ 413: && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ 414: && (CLASS) != ADDR_REGS) \ 415: ? DATA_REGS \ 416: : GET_MODE (X) == QImode \ 417: ? DATA_REGS \ 418: : (CLASS)) 419: 420: /* Return the maximum number of consecutive registers 421: needed to represent mode MODE in a register of class CLASS. */ 422: /* On the 68000, this is the size of MODE in words, 423: except in the FP regs, where a single reg is always enough. */ 424: #define CLASS_MAX_NREGS(CLASS, MODE) \ 425: ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \ 426: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 427: 428: /* Stack layout; function entry, exit and calling. */ 429: 430: /* Define this if pushing a word on the stack 431: makes the stack pointer a smaller address. */ 432: #define STACK_GROWS_DOWNWARD 433: 434: /* Define this if the nominal address of the stack frame 435: is at the high-address end of the local variables; 436: that is, each additional local variable allocated 437: goes at a more negative offset in the frame. */ 438: #define FRAME_GROWS_DOWNWARD 439: 1.1.1.2 ! root 440: /* Define this if should default to -fcaller-saves. */ ! 441: ! 442: #define DEFAULT_CALLER_SAVES ! 443: 1.1 root 444: /* Offset within stack frame to start allocating local variables at. 445: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 446: first local allocated. Otherwise, it is the offset to the BEGINNING 447: of the first local allocated. */ 448: #define STARTING_FRAME_OFFSET -4 449: 450: /* If we generate an insn to push BYTES bytes, 451: this says how many the stack pointer really advances by. 452: On the 68000, sp@- in a byte insn really pushes a word. */ 453: #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) 454: 455: /* Offset of first parameter from the argument pointer register value. */ 456: #define FIRST_PARM_OFFSET(FNDECL) 0 457: 458: /* Value is 1 if returning from a function call automatically 459: pops the arguments described by the number-of-args field in the call. 460: FUNTYPE is the data type of the function (as a tree), 461: or for a library call it is an identifier node for the subroutine name. 462: 463: On the 68000, the RTS insn cannot pop anything. 464: On the 68010, the RTD insn may be used to pop them if the number 465: of args is fixed, but if the number is variable then the caller 466: must pop them all. RTD can't be used for library calls now 467: because the library is compiled with the Unix compiler. 468: Use of RTD is a selectable option, since it is incompatible with 469: standard Unix calling sequences. If the option is not selected, 470: the caller must always pop the args. */ 471: 472: #define RETURN_POPS_ARGS(FUNTYPE) \ 473: (TARGET_RTD && TREE_CODE (FUNTYPE) != IDENTIFIER_NODE \ 474: && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ 475: || TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) == void_type_node)) 476: 477: /* Define how to find the value returned by a function. 478: VALTYPE is the data type of the value (as a tree). 479: If the precise function being called is known, FUNC is its FUNCTION_DECL; 480: otherwise, FUNC is 0. */ 481: 482: /* On the 68000 the return value is in D0 regardless. */ 483: 484: #define FUNCTION_VALUE(VALTYPE, FUNC) \ 485: gen_rtx (REG, TYPE_MODE (VALTYPE), 0) 486: 487: /* Define how to find the value returned by a library function 488: assuming the value has mode MODE. */ 489: 490: /* On the 68000 the return value is in D0 regardless. */ 491: 492: #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0) 493: 1.1.1.2 ! root 494: /* Define this if PCC uses the nonreentrant convention for returning ! 495: structure and union values. */ ! 496: ! 497: #define PCC_STATIC_STRUCT_RETURN ! 498: 1.1 root 499: /* 1 if N is a possible register number for a function value. 500: On the 68000, d0 is the only register thus used. */ 501: 502: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) 503: 504: /* 1 if N is a possible register number for function argument passing. 505: On the 68000, no registers are used in this way. */ 506: 507: #define FUNCTION_ARG_REGNO_P(N) 0 508: 509: /* Define a data type for recording info about an argument list 510: during the scan of that argument list. This data type should 511: hold all necessary information about the function itself 512: and about the args processed so far, enough to enable macros 513: such as FUNCTION_ARG to determine where the next arg should go. 514: 515: On the m68k, this is a single integer, which is a number of bytes 516: of arguments scanned so far. */ 517: 518: #define CUMULATIVE_ARGS int 519: 520: /* Initialize a variable CUM of type CUMULATIVE_ARGS 521: for a call to a function whose data type is FNTYPE. 522: For a library call, FNTYPE is 0. 523: 524: On the m68k, the offset starts at 0. */ 525: 526: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE) \ 527: ((CUM) = 0) 528: 529: /* Update the data in CUM to advance over an argument 530: of mode MODE and data type TYPE. 531: (TYPE is null for libcalls where that information may not be available.) */ 532: 533: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 534: ((CUM) += ((MODE) != BLKmode \ 535: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ 536: : (int_size_in_bytes (TYPE) + 3) & ~3)) 537: 538: /* Define where to put the arguments to a function. 539: Value is zero to push the argument on the stack, 540: or a hard register in which to store the argument. 541: 542: MODE is the argument's machine mode. 543: TYPE is the data type of the argument (as a tree). 544: This is null for libcalls where that information may 545: not be available. 546: CUM is a variable of type CUMULATIVE_ARGS which gives info about 547: the preceding args and about the function being called. 548: NAMED is nonzero if this argument is a named parameter 549: (otherwise it is an extra parameter matching an ellipsis). */ 550: 551: /* On the 68000 all args are pushed, except if -mregparm is specified 552: then the first two words of arguments are passed in d0, d1. 553: *NOTE* -mregparm does not work. 554: It exists only to test register calling conventions. */ 555: 556: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 557: ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx(REG, (MODE), (CUM)/4) : 0) 558: 559: /* For an arg passed partly in registers and partly in memory, 560: this is the number of registers used. 561: For args passed entirely in registers or entirely in memory, zero. */ 562: 563: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 564: ((TARGET_REGPARM && (CUM) < 8 \ 565: && 8 < ((CUM) + ((MODE) == BLKmode \ 566: ? int_size_in_bytes (TYPE) \ 567: : GET_MODE_SIZE (MODE)))) \ 568: ? 2 - (CUM) / 4 : 0) 569: 570: /* This macro generates the assembly code for function entry. 571: FILE is a stdio stream to output the code to. 572: SIZE is an int: how many units of temporary storage to allocate. 573: Refer to the array `regs_ever_live' to determine which registers 574: to save; `regs_ever_live[I]' is nonzero if register number I 575: is ever used in the function. This macro is responsible for 576: knowing which registers should not be saved even if used. */ 577: 578: /* Note that the order of the bit mask for fmovem is the opposite 579: of the order for movem! */ 580: 581: #define FUNCTION_PROLOGUE(FILE, SIZE) \ 582: { int fsize = ((SIZE) + 3) & -4; \ 583: if (frame_pointer_needed) { \ 584: if (TARGET_68020 || fsize < 0x8000) \ 585: fprintf(FILE,"\tlink a6,#%d\n", -fsize); \ 586: else \ 587: fprintf(FILE,"\tlink a6,#0\n\tsubl #%d,sp\n", fsize); } \ 588: fprintf(FILE, "\tmovl a0,a6@(-4)\n" ); } 589: 590: /* Output assembler code to FILE to increment profiler label # LABELNO 591: for profiling a function entry. */ 592: 593: #define FUNCTION_PROFILER(FILE, LABELNO) \ 594: fprintf (FILE, "\tlea LP%d,a0\n\tjsr mcount\n", (LABELNO)) 595: 596: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 597: the stack pointer does not matter. The value is tested only in 598: functions that have frame pointers. 599: No definition is equivalent to always zero. */ 600: 601: #define EXIT_IGNORE_STACK 1 602: 603: /* This macro generates the assembly code for function exit, 604: on machines that need it. If FUNCTION_EPILOGUE is not defined 605: then individual return instructions are generated for each 606: return statement. Args are same as for FUNCTION_PROLOGUE. 607: 608: The function epilogue should not depend on the current stack pointer! 609: It should use the frame pointer only. This is mandatory because 610: of alloca; we also take advantage of it to omit stack adjustments 611: before returning. */ 612: 613: #define FUNCTION_EPILOGUE(FILE, SIZE) \ 614: { extern int current_function_pops_args; \ 615: extern int current_function_args_size; \ 616: if (frame_pointer_needed) \ 617: fprintf (FILE, "\tunlk a6\n"); \ 618: if (current_function_pops_args && current_function_args_size) \ 619: fprintf (FILE, "\trtd #%d\n", current_function_args_size); \ 620: else fprintf (FILE, "\trts\n"); } 621: 622: /* If the memory address ADDR is relative to the frame pointer, 623: correct it to be relative to the stack pointer instead. 624: This is for when we don't use a frame pointer. 625: ADDR should be a variable name. */ 626: 627: #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \ 628: { int offset = -1; \ 629: rtx regs = stack_pointer_rtx; \ 630: if (ADDR == frame_pointer_rtx) \ 631: offset = 0; \ 632: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \ 633: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \ 634: offset = INTVAL (XEXP (ADDR, 1)); \ 635: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \ 636: { rtx other_reg = XEXP (ADDR, 1); \ 637: offset = 0; \ 638: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \ 639: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \ 640: { rtx other_reg = XEXP (ADDR, 0); \ 641: offset = 0; \ 642: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \ 643: else if (GET_CODE (ADDR) == PLUS \ 644: && GET_CODE (XEXP (ADDR, 0)) == PLUS \ 645: && XEXP (XEXP (ADDR, 0), 0) == frame_pointer_rtx \ 646: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \ 647: { rtx other_reg = XEXP (XEXP (ADDR, 0), 1); \ 648: offset = INTVAL (XEXP (ADDR, 1)); \ 649: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \ 650: else if (GET_CODE (ADDR) == PLUS \ 651: && GET_CODE (XEXP (ADDR, 0)) == PLUS \ 652: && XEXP (XEXP (ADDR, 0), 1) == frame_pointer_rtx \ 653: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \ 654: { rtx other_reg = XEXP (XEXP (ADDR, 0), 0); \ 655: offset = INTVAL (XEXP (ADDR, 1)); \ 656: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \ 657: if (offset >= 0) \ 658: { int regno; \ 659: extern char call_used_regs[]; \ 660: for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ 661: if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 662: offset += 12; \ 663: for (regno = 0; regno < 16; regno++) \ 664: if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 665: offset += 4; \ 666: offset -= 4; \ 667: ADDR = plus_constant (regs, offset + (DEPTH)); } } \ 668: 669: /* Addressing modes, and classification of registers for them. */ 670: 671: #define HAVE_POST_INCREMENT 672: /* #define HAVE_POST_DECREMENT */ 673: 674: #define HAVE_PRE_DECREMENT 675: /* #define HAVE_PRE_INCREMENT */ 676: 677: /* Macros to check register numbers against specific register classes. */ 678: 679: /* These assume that REGNO is a hard or pseudo reg number. 680: They give nonzero only if REGNO is a hard reg of the suitable class 681: or a pseudo reg currently allocated to a suitable hard reg. 682: Since they use reg_renumber, they are safe only once reg_renumber 683: has been allocated, which happens in local-alloc.c. */ 684: 685: #define REGNO_OK_FOR_INDEX_P(REGNO) \ 686: ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) 687: #define REGNO_OK_FOR_BASE_P(REGNO) \ 688: (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) 689: #define REGNO_OK_FOR_DATA_P(REGNO) \ 690: ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) 691: #define REGNO_OK_FOR_FP_P(REGNO) \ 692: (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) 693: 694: #define REGNO_OK_FOR_FPA_P(REGNO) 0 695: 696: /* Now macros that check whether X is a register and also, 697: strictly, whether it is in a specified class. 698: 699: These macros are specific to the 68000, and may be used only 700: in code for printing assembler insns and in conditions for 701: define_optimization. */ 702: 703: /* 1 if X is a data register. */ 704: 705: #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) 706: 707: /* 1 if X is an fp register. */ 708: 709: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 710: 711: /* 1 if X is an address register */ 712: 713: #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) 714: 715: /* 1 if X is a register in the Sun FPA. */ 716: #define FPA_REG_P(X) 0 717: 718: /* Maximum number of registers that can appear in a valid memory address. */ 719: 720: #define MAX_REGS_PER_ADDRESS 2 721: 722: /* Recognize any constant value that is a valid address. */ 723: 724: #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X) 725: 726: /* Nonzero if the constant value X is a legitimate general operand. 727: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 728: 729: #define LEGITIMATE_CONSTANT_P(X) 1 730: 731: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 732: and check its validity for a certain class. 733: We have two alternate definitions for each of them. 734: The usual definition accepts all pseudo regs; the other rejects 735: them unless they have been allocated suitable hard regs. 736: The symbol REG_OK_STRICT causes the latter definition to be used. 737: 738: Most source files want to accept pseudo regs in the hope that 739: they will get allocated to the class that the insn wants them to be in. 740: Source files for reload pass need to be strict. 741: After reload, it makes no difference, since pseudo regs have 742: been eliminated by then. */ 743: 744: #ifndef REG_OK_STRICT 745: 746: /* Nonzero if X is a hard reg that can be used as an index 747: or if it is a pseudo reg. */ 748: #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) 749: /* Nonzero if X is a hard reg that can be used as a base reg 750: or if it is a pseudo reg. */ 751: #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) 752: 753: #else 754: 755: /* Nonzero if X is a hard reg that can be used as an index. */ 756: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 757: /* Nonzero if X is a hard reg that can be used as a base reg. */ 758: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 759: 760: #endif 761: 762: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 763: that is a valid memory address for an instruction. 764: The MODE argument is the machine mode for the MEM expression 765: that wants to use this address. 766: 767: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 768: 769: #define INDIRECTABLE_1_ADDRESS_P(X) \ 770: (CONSTANT_ADDRESS_P (X) \ 771: || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 772: || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ 773: && REG_P (XEXP (X, 0)) \ 774: && REG_OK_FOR_BASE_P (XEXP (X, 0))) \ 775: || (GET_CODE (X) == PLUS \ 776: && REG_P (XEXP (X, 0)) && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ 777: && GET_CODE (XEXP (X, 1)) == CONST_INT \ 778: && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) 779: 780: #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ 781: { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } 782: 783: #define GO_IF_INDEXABLE_BASE(X, ADDR) \ 784: { if (GET_CODE (X) == LABEL_REF) goto ADDR; \ 785: if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; } 786: 787: #define GO_IF_INDEXING(X, ADDR) \ 788: { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ 789: { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ 790: if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ 791: { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } 792: 793: #define GO_IF_INDEXED_ADDRESS(X, ADDR) \ 794: { GO_IF_INDEXING (X, ADDR); \ 795: if (GET_CODE (X) == PLUS) \ 796: { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 797: && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \ 798: { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ 799: if (GET_CODE (XEXP (X, 0)) == CONST_INT \ 800: && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \ 801: { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } 802: 803: #define LEGITIMATE_INDEX_REG_P(X) \ 804: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 805: || (GET_CODE (X) == SIGN_EXTEND \ 806: && GET_CODE (XEXP (X, 0)) == REG \ 807: && GET_MODE (XEXP (X, 0)) == HImode \ 808: && REG_OK_FOR_INDEX_P (XEXP (X, 0)))) 809: 810: #define LEGITIMATE_INDEX_P(X) \ 811: (LEGITIMATE_INDEX_REG_P (X) \ 812: || (TARGET_68020 && GET_CODE (X) == MULT \ 813: && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ 814: && GET_CODE (XEXP (X, 1)) == CONST_INT \ 815: && (INTVAL (XEXP (X, 1)) == 2 \ 816: || INTVAL (XEXP (X, 1)) == 4 \ 817: || INTVAL (XEXP (X, 1)) == 8))) 818: 819: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 820: { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ 821: GO_IF_INDEXED_ADDRESS (X, ADDR); } 822: 823: /* Try machine-dependent ways of modifying an illegitimate address 824: to be legitimate. If we find one, return the new, valid address. 825: This macro is used in only one place: `memory_address' in explow.c. 826: 827: OLDX is the address as it was before break_out_memory_refs was called. 828: In some cases it is useful to look at this to decide what needs to be done. 829: 830: MODE and WIN are passed so that this macro can use 831: GO_IF_LEGITIMATE_ADDRESS. 832: 833: It is always safe for this macro to do nothing. It exists to recognize 834: opportunities to optimize the output. 835: 836: For the 68000, we handle X+REG by loading X into a register R and 837: using R+REG. R will go in an address reg and indexing will be used. 838: However, if REG is a broken-out memory address or multiplication, 839: nothing needs to be done because REG can certainly go in an address reg. */ 840: 841: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 842: { register int ch = (X) != (OLDX); \ 843: if (GET_CODE (X) == PLUS) \ 844: { if (GET_CODE (XEXP (X, 0)) == MULT) \ 845: ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \ 846: if (GET_CODE (XEXP (X, 1)) == MULT) \ 847: ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \ 848: if (ch && GET_CODE (XEXP (X, 1)) == REG \ 849: && GET_CODE (XEXP (X, 0)) == REG) \ 850: return X; \ 851: if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ 852: if (GET_CODE (XEXP (X, 0)) == REG \ 853: || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ 854: && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ 855: && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ 856: { register rtx temp = gen_reg_rtx (Pmode); \ 857: register rtx val = force_operand (XEXP (X, 1), 0); \ 858: emit_move_insn (temp, val); \ 859: XEXP (X, 1) = temp; \ 860: return X; } \ 861: else if (GET_CODE (XEXP (X, 1)) == REG \ 862: || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ 863: && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ 864: && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ 865: { register rtx temp = gen_reg_rtx (Pmode); \ 866: register rtx val = force_operand (XEXP (X, 0), 0); \ 867: emit_move_insn (temp, val); \ 868: XEXP (X, 0) = temp; \ 869: return X; }}} 870: 871: /* Go to LABEL if ADDR (a legitimate address expression) 872: has an effect that depends on the machine mode it is used for. 873: On the 68000, only predecrement and postincrement address depend thus 874: (the amount of decrement or increment being the length of the operand). */ 875: 876: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 877: if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL 878: 879: /* Specify the machine mode that this machine uses 880: for the index in the tablejump instruction. */ 881: #define CASE_VECTOR_MODE HImode 882: 883: /* Define this if the tablejump instruction expects the table 884: to contain offsets from the address of the table. 885: Do not define this if the table should contain absolute addresses. */ 886: #define CASE_VECTOR_PC_RELATIVE 887: 888: /* Specify the tree operation to be used to convert reals to integers. */ 889: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 890: 891: /* This is the kind of divide that is easiest to do in the general case. */ 892: #define EASY_DIV_EXPR TRUNC_DIV_EXPR 893: 894: /* Define this as 1 if `char' should by default be signed; else as 0. */ 895: #define DEFAULT_SIGNED_CHAR 1 896: 897: /* Max number of bytes we can move from memory to memory 898: in one reasonably fast instruction. */ 899: #define MOVE_MAX 4 900: 901: /* Define this if zero-extension is slow (more than one real instruction). */ 902: #define SLOW_ZERO_EXTEND 903: 904: /* Nonzero if access to memory by bytes is slow and undesirable. */ 905: #define SLOW_BYTE_ACCESS 0 906: 907: /* Define if shifts truncate the shift count 908: which implies one can omit a sign-extension or zero-extension 909: of a shift count. */ 910: #define SHIFT_COUNT_TRUNCATED 911: 912: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 913: is done just by pretending it is already truncated. */ 914: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 915: 916: /* We assume that the store-condition-codes instructions store 0 for false 917: and some other value for true. This is the value stored for true. */ 918: 919: #define STORE_FLAG_VALUE -1 920: 921: /* When a prototype says `char' or `short', really pass an `int'. */ 922: #define PROMOTE_PROTOTYPES 923: 924: /* Specify the machine mode that pointers have. 925: After generation of rtl, the compiler makes no further distinction 926: between pointers and any other objects of this machine mode. */ 927: #define Pmode SImode 928: 929: /* A function address in a call instruction 930: is a byte address (for indexing purposes) 931: so give the MEM rtx a byte's mode. */ 932: #define FUNCTION_MODE QImode 933: 934: /* Compute the cost of computing a constant rtl expression RTX 935: whose rtx-code is CODE. The body of this macro is a portion 936: of a switch statement. If the code is computed here, 937: return it with a return statement. Otherwise, break from the switch. */ 938: 939: #define CONST_COSTS(RTX,CODE) \ 940: case CONST_INT: \ 941: /* Constant zero is super cheap due to clr instruction. */ \ 942: if (RTX == const0_rtx) return 0; \ 943: if ((unsigned) INTVAL (RTX) < 077) return 1; \ 944: case CONST: \ 945: case LABEL_REF: \ 946: case SYMBOL_REF: \ 947: return 3; \ 948: case CONST_DOUBLE: \ 949: return 5; 950: 951: /* Tell final.c how to eliminate redundant test instructions. */ 952: 953: /* Here we define machine-dependent flags and fields in cc_status 954: (see `conditions.h'). */ 955: 956: /* On the Alliant, floating-point instructions do not modify the 957: ordinary CC register. Only fcmp and ftest instructions modify the 958: floating-point CC register. We should actually keep track of what 959: both kinds of CC registers contain, but for now we only consider 960: the most recent instruction that has set either register. */ 961: 962: /* Set if the cc value came from a floating point test, so a floating 963: point conditional branch must be output. */ 964: #define CC_IN_68881 04000 965: 966: /* Store in cc_status the expressions 967: that the condition codes will describe 968: after execution of an instruction whose pattern is EXP. 969: Do not alter them if the instruction would not alter the cc's. */ 970: 971: /* On the 68000, all the insns to store in an address register 972: fail to set the cc's. However, in some cases these instructions 973: can make it possibly invalid to use the saved cc's. In those 974: cases we clear out some or all of the saved cc's so they won't be used. */ 975: 976: #define NOTICE_UPDATE_CC(EXP, INSN) \ 977: { \ 978: if (GET_CODE (EXP) == SET) \ 979: { if (ADDRESS_REG_P (XEXP (EXP, 0))) \ 980: { if (cc_status.value1 \ 981: && reg_overlap_mentioned_p (XEXP (EXP, 0), cc_status.value1)) \ 982: cc_status.value1 = 0; \ 983: if (cc_status.value2 \ 984: && reg_overlap_mentioned_p (XEXP (EXP, 0), cc_status.value2)) \ 985: cc_status.value2 = 0; } \ 986: else if (FP_REG_P (XEXP (EXP,0)) \ 987: || (FP_REG_P (XEXP (EXP,1)) \ 988: && XEXP (EXP, 0) != cc0_rtx)) \ 989: { } \ 990: else if (!FP_REG_P (XEXP (EXP, 0)) \ 991: && XEXP (EXP, 0) != cc0_rtx \ 992: && (FP_REG_P (XEXP (EXP, 1)) \ 993: || GET_CODE (XEXP (EXP, 1)) == FIX \ 994: || GET_CODE (XEXP (EXP, 1)) == FLOAT_TRUNCATE \ 995: || GET_CODE (XEXP (EXP, 1)) == FLOAT_EXTEND)) \ 996: { CC_STATUS_INIT; } \ 997: else if (GET_CODE (SET_SRC (EXP)) == CALL) \ 998: { CC_STATUS_INIT; } \ 999: else if (XEXP (EXP, 0) != pc_rtx) \ 1000: { cc_status.flags = 0; \ 1001: cc_status.value1 = XEXP (EXP, 0); \ 1002: cc_status.value2 = XEXP (EXP, 1); } } \ 1003: else if (GET_CODE (EXP) == PARALLEL \ 1004: && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \ 1005: { \ 1006: if (ADDRESS_REG_P (XEXP (XVECEXP (EXP, 0, 0), 0))) \ 1007: CC_STATUS_INIT; \ 1008: else if (XEXP (XVECEXP (EXP, 0, 0), 0) != pc_rtx) \ 1009: { cc_status.flags = 0; \ 1010: cc_status.value1 = XEXP (XVECEXP (EXP, 0, 0), 0); \ 1011: cc_status.value2 = XEXP (XVECEXP (EXP, 0, 0), 1); } } \ 1012: else CC_STATUS_INIT; \ 1013: if (cc_status.value2 != 0 \ 1014: && ADDRESS_REG_P (cc_status.value2) \ 1015: && GET_MODE (cc_status.value2) == QImode) \ 1016: CC_STATUS_INIT; \ 1017: if (cc_status.value2 != 0 \ 1018: && !(cc_status.value1 && FPA_REG_P (cc_status.value1))) \ 1019: switch (GET_CODE (cc_status.value2)) \ 1020: { case PLUS: case MINUS: case MULT: case UMULT: \ 1021: case DIV: case UDIV: case MOD: case UMOD: case NEG: \ 1022: case ASHIFT: case LSHIFT: case ASHIFTRT: case LSHIFTRT: \ 1023: case ROTATE: case ROTATERT: \ 1024: if (GET_MODE (cc_status.value2) != VOIDmode) \ 1025: cc_status.flags |= CC_NO_OVERFLOW; \ 1026: break; \ 1027: case ZERO_EXTEND: \ 1028: /* (SET r1 (ZERO_EXTEND r2)) on this machine 1029: ends with a move insn moving r2 in r2's mode. 1030: Thus, the cc's are set for r2. 1031: This can set N bit spuriously. */ \ 1032: cc_status.flags |= CC_NOT_NEGATIVE; } \ 1033: if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \ 1034: && cc_status.value2 \ 1035: && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \ 1036: cc_status.value2 = 0; \ 1037: if ((cc_status.value1 && FP_REG_P (cc_status.value1)) \ 1038: || (cc_status.value2 && FP_REG_P (cc_status.value2))) \ 1039: cc_status.flags = CC_IN_68881; } 1040: 1041: #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ 1042: { if (cc_prev_status.flags & CC_IN_68881) \ 1043: return FLOAT; \ 1044: if (cc_prev_status.flags & CC_NO_OVERFLOW) \ 1045: return NO_OV; \ 1046: return NORMAL; } 1047: 1048: /* Control the assembler format that we output. */ 1049: 1050: /* Output at beginning of assembler file. */ 1051: 1052: #define ASM_FILE_START(FILE) fprintf (FILE, "#NO_APP\n"); 1053: 1054: /* Output to assembler file text saying following lines 1055: may contain character constants, extra white space, comments, etc. */ 1056: 1057: #define ASM_APP_ON "#APP\n" 1058: 1059: /* Output to assembler file text saying following lines 1060: no longer contain unusual constructs. */ 1061: 1062: #define ASM_APP_OFF "#NO_APP\n" 1063: 1064: /* Output before read-only data. */ 1065: 1066: #define TEXT_SECTION_ASM_OP "\t.text" 1067: 1068: /* Output before writable data. */ 1069: 1070: #define DATA_SECTION_ASM_OP "\t.data" 1071: 1072: /* How to refer to registers in assembler output. 1073: This sequence is indexed by compiler's hard-register-number (see above). */ 1074: 1075: #define REGISTER_NAMES \ 1076: {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ 1077: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ 1078: "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" } 1079: 1080: /* How to renumber registers for dbx and gdb. 1081: On the Sun-3, the floating point registers have numbers 1082: 18 to 25, not 16 to 23 as they do in the compiler. */ 1083: 1084: #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) 1085: 1086: /* This is how to output the definition of a user-level label named NAME, 1087: such as the label on a static function or variable NAME. */ 1088: 1089: #define ASM_OUTPUT_LABEL(FILE,NAME) \ 1090: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 1091: 1092: /* This is how to output a command to make the user-level label named NAME 1093: defined for reference from other files. */ 1094: 1095: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ 1096: do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) 1097: 1098: /* This is how to output a reference to a user-level label named NAME. 1099: `assemble_name' uses this. */ 1100: 1101: #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1102: fprintf (FILE, "_%s", NAME) 1103: 1104: /* This is how to output an internal numbered label where 1105: PREFIX is the class of label and NUM is the number within the class. */ 1106: 1107: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 1108: fprintf (FILE, "%s%d:\n", PREFIX, NUM) 1109: 1110: /* This is how to store into the string LABEL 1111: the symbol_ref name of an internal numbered label where 1112: PREFIX is the class of label and NUM is the number within the class. 1113: This is suitable for output with `assemble_name'. */ 1114: 1115: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1116: sprintf (LABEL, "*%s%d", PREFIX, NUM) 1117: 1118: /* This is how to output an assembler line defining a `double' constant. */ 1119: 1120: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ 1121: do { union { double d; long v[2];} tem; \ 1122: tem.d = (VALUE); \ 1123: fprintf (FILE, "\t.long 0x%x,0x%x\n", tem.v[0], tem.v[1]); \ 1124: } while (0) 1125: 1126: /* This is how to output an assembler line defining a `float' constant. */ 1127: 1128: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ 1129: do { union { float f; long l;} tem; \ 1130: tem.f = (VALUE); \ 1131: fprintf (FILE, "\t.long 0x%x\n", tem.l); \ 1132: } while (0) 1133: 1134: /* This is how to output an assembler line defining an `int' constant. */ 1135: 1136: #define ASM_OUTPUT_INT(FILE,VALUE) \ 1137: ( fprintf (FILE, "\t.long "), \ 1138: output_addr_const (FILE, (VALUE)), \ 1139: fprintf (FILE, "\n")) 1140: 1141: /* Likewise for `char' and `short' constants. */ 1142: 1143: #define ASM_OUTPUT_SHORT(FILE,VALUE) \ 1144: ( fprintf (FILE, "\t.word "), \ 1145: output_addr_const (FILE, (VALUE)), \ 1146: fprintf (FILE, "\n")) 1147: 1148: #define ASM_OUTPUT_CHAR(FILE,VALUE) \ 1149: ( fprintf (FILE, "\t.byte "), \ 1150: output_addr_const (FILE, (VALUE)), \ 1151: fprintf (FILE, "\n")) 1152: 1153: #define ASM_OUTPUT_ASCII(FILE,PTR,SIZE) \ 1154: { int i; unsigned char *pp = (unsigned char *) PTR; \ 1155: fprintf(FILE, "\t.byte %d", (unsigned int)*pp++); \ 1156: for (i = 1; i < SIZE; ++i, ++pp) { \ 1157: if ((i % 8) == 0) \ 1158: fprintf(FILE, "\n\t.byte %d", (unsigned int) *pp); \ 1159: else \ 1160: fprintf(FILE, ",%d", (unsigned int) *pp); } \ 1161: fprintf (FILE, "\n"); } 1162: 1163: /* This is how to output an assembler line for a numeric constant byte. */ 1164: 1165: #define ASM_OUTPUT_BYTE(FILE,VALUE) \ 1166: fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) 1167: 1168: /* This is how to output an insn to push a register on the stack. 1169: It need not be very fast code. */ 1170: 1171: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 1172: fprintf (FILE, "\tmovl %s,sp@-\n", reg_names[REGNO]) 1173: 1174: /* This is how to output an insn to pop a register from the stack. 1175: It need not be very fast code. */ 1176: 1177: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 1178: fprintf (FILE, "\tmovl sp@+,%s\n", reg_names[REGNO]) 1179: 1180: /* This is how to output an element of a case-vector that is absolute. 1181: (The 68000 does not use such vectors, 1182: but we must define this macro anyway.) */ 1183: 1184: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1185: fprintf (FILE, "\t.long L%d\n", VALUE) 1186: 1187: /* This is how to output an element of a case-vector that is relative. */ 1188: 1189: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 1190: fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL) 1191: 1192: /* This is how to output an assembler line 1193: that says to advance the location counter 1194: to a multiple of 2**LOG bytes. */ 1195: 1196: #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1197: if ((LOG) == 1) \ 1198: fprintf (FILE, "\t.even\n"); \ 1199: else if ((LOG) != 0) \ 1200: fprintf (FILE, "\t.align %dn", (LOG)); 1201: 1202: #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1203: fprintf (FILE, "\t. = . + %d\n", (SIZE)) 1204: 1205: /* This says how to output an assembler line 1206: to define a global common symbol. */ 1207: 1208: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1209: ( fputs ("\t.comm ", (FILE)), \ 1210: assemble_name ((FILE), (NAME)), \ 1211: fprintf ((FILE), ",%d\n", (ROUNDED))) 1212: 1213: /* This says how to output an assembler line 1214: to define a local common symbol. */ 1215: 1216: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1217: ( fputs ("\t.lcomm ", (FILE)), \ 1218: assemble_name ((FILE), (NAME)), \ 1219: fprintf ((FILE), ",%d\n", (ROUNDED))) 1220: 1221: /* Store in OUTPUT a string (made with alloca) containing 1222: an assembler-name for a local static variable named NAME. 1223: LABELNO is an integer which is different for each call. */ 1224: 1225: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 1226: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 1227: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 1228: 1229: /* Define the parentheses used to group arithmetic operations 1230: in assembler code. */ 1231: 1232: #define ASM_OPEN_PAREN "(" 1233: #define ASM_CLOSE_PAREN ")" 1234: 1235: /* Define results of standard character escape sequences. */ 1236: #define TARGET_BELL 007 1237: #define TARGET_BS 010 1238: #define TARGET_TAB 011 1239: #define TARGET_NEWLINE 012 1240: #define TARGET_VT 013 1241: #define TARGET_FF 014 1242: #define TARGET_CR 015 1243: 1244: /* Print operand X (an rtx) in assembler syntax to file FILE. 1245: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1246: For `%' followed by punctuation, CODE is the punctuation and X is null. 1247: 1248: On the 68000, we use several CODE characters: 1249: 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 1250: 'b' for byte insn (no effect, on the Sun; this is for the ISI). 1251: '.' for dot needed in Motorola-style opcode names. 1252: '-' for an operand pushing on the stack: 1253: sp@-, -(sp) or -(%sp) depending on the style of syntax. 1254: '+' for an operand pushing on the stack: 1255: sp@+, (sp)+ or (%sp)+ depending on the style of syntax. 1256: 's' for a reference to the top word on the stack: 1257: sp@, (sp) or (%sp) depending on the style of syntax. 1258: '#' for an immediate operand prefix (# in MIT and Motorola syntax 1259: but & in SGS syntax). 1260: '!' for the cc register (used in an `and to cc' insn). 1261: 1262: 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather 1263: than directly). Second part of 'y' below. 1264: 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), 1265: or print pair of registers as rx:ry. 1266: 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs 1267: CONST_DOUBLE's as SunFPA constant RAM registers if 1268: possible, so it should not be used except for the SunFPA. */ 1269: 1270: #define PRINT_OPERAND(FILE, X, CODE) \ 1271: { int i; \ 1272: if (CODE == '.') ; \ 1273: else if (CODE == '#') fprintf (FILE, "#"); \ 1274: else if (CODE == '-') fprintf (FILE, "sp@-"); \ 1275: else if (CODE == '+') fprintf (FILE, "sp@+"); \ 1276: else if (CODE == 's') fprintf (FILE, "sp@"); \ 1277: else if (CODE == '!') fprintf (FILE, "cc"); \ 1278: else if ((X) == 0 ) ; \ 1279: else if (GET_CODE (X) == REG) \ 1280: { if (REGNO (X) < 16 && (CODE == 'y' || CODE == 'x') && GET_MODE (X) == DFmode) \ 1281: fprintf (FILE, "%s,%s", reg_name [REGNO (X)], reg_name [REGNO (X)+1]); \ 1282: else \ 1283: fprintf (FILE, "%s", reg_name[REGNO (X)]); \ 1284: } \ 1285: else if (GET_CODE (X) == MEM) \ 1286: output_address (XEXP (X, 0)); \ 1287: else if ((CODE == 'y' || CODE == 'w') \ 1288: && GET_CODE(X) == CONST_DOUBLE \ 1289: && (i = standard_SunFPA_constant_p (X))) \ 1290: fprintf(FILE, "%%%d", i & 0x1ff); \ 1291: else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \ 1292: { union { double d; int i[2]; } u; \ 1293: union { float f; int i; } u1; \ 1294: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \ 1295: u1.f = u.d; \ 1296: if (CODE == 'f') \ 1297: fprintf (FILE, "#0r%.9g", u1.f); \ 1298: else \ 1.1.1.2 ! root 1299: fprintf (FILE, "#0x%x", u1.i); } \ 1.1 root 1300: else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != DImode) \ 1301: { union { double d; int i[2]; } u; \ 1302: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \ 1303: fprintf (FILE, "#0r%.20g", u.d); } \ 1304: else { putc ('#', FILE); output_addr_const (FILE, X); }} 1305: 1306: /* Note that this contains a kludge that knows that the only reason 1307: we have an address (plus (label_ref...) (reg...)) 1308: is in the insn before a tablejump, and we know that m68k.md 1309: generates a label LInnn: on such an insn. */ 1310: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1311: { register rtx reg1, reg2, breg, ireg; \ 1312: register rtx addr = ADDR; \ 1313: static char *sz = ".BW.L...D"; \ 1314: rtx offset; \ 1315: switch (GET_CODE (addr)) \ 1316: { \ 1317: case REG: \ 1318: fprintf (FILE, "%s@", reg_name [REGNO (addr)]); \ 1319: break; \ 1320: case PRE_DEC: \ 1321: fprintf (FILE, "%s@-", reg_name [REGNO (XEXP (addr, 0))]); \ 1322: break; \ 1323: case POST_INC: \ 1324: fprintf (FILE, "%s@+", reg_name [REGNO (XEXP (addr, 0))]); \ 1325: break; \ 1326: case PLUS: \ 1327: reg1 = 0; reg2 = 0; \ 1328: ireg = 0; breg = 0; \ 1329: offset = 0; \ 1330: if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ 1331: { \ 1332: offset = XEXP (addr, 0); \ 1333: addr = XEXP (addr, 1); \ 1334: } \ 1335: else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ 1336: { \ 1337: offset = XEXP (addr, 1); \ 1338: addr = XEXP (addr, 0); \ 1339: } \ 1340: if (GET_CODE (addr) != PLUS) ; \ 1341: else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ 1342: { \ 1343: reg1 = XEXP (addr, 0); \ 1344: addr = XEXP (addr, 1); \ 1345: } \ 1346: else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ 1347: { \ 1348: reg1 = XEXP (addr, 1); \ 1349: addr = XEXP (addr, 0); \ 1350: } \ 1351: else if (GET_CODE (XEXP (addr, 0)) == MULT) \ 1352: { \ 1353: reg1 = XEXP (addr, 0); \ 1354: addr = XEXP (addr, 1); \ 1355: } \ 1356: else if (GET_CODE (XEXP (addr, 1)) == MULT) \ 1357: { \ 1358: reg1 = XEXP (addr, 1); \ 1359: addr = XEXP (addr, 0); \ 1360: } \ 1361: else if (GET_CODE (XEXP (addr, 0)) == REG) \ 1362: { \ 1363: reg1 = XEXP (addr, 0); \ 1364: addr = XEXP (addr, 1); \ 1365: } \ 1366: else if (GET_CODE (XEXP (addr, 1)) == REG) \ 1367: { \ 1368: reg1 = XEXP (addr, 1); \ 1369: addr = XEXP (addr, 0); \ 1370: } \ 1371: if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ 1372: || GET_CODE (addr) == SIGN_EXTEND) \ 1373: { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ 1374: /* for OLD_INDEXING \ 1375: else if (GET_CODE (addr) == PLUS) \ 1376: { \ 1377: if (GET_CODE (XEXP (addr, 0)) == REG) \ 1378: { \ 1379: reg2 = XEXP (addr, 0); \ 1380: addr = XEXP (addr, 1); \ 1381: } \ 1382: else if (GET_CODE (XEXP (addr, 1)) == REG) \ 1383: { \ 1384: reg2 = XEXP (addr, 1); \ 1385: addr = XEXP (addr, 0); \ 1386: } \ 1387: } \ 1388: */ \ 1389: if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ 1390: if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ 1391: || GET_CODE (reg1) == MULT)) \ 1392: || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ 1393: { breg = reg2; ireg = reg1; } \ 1394: else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ 1395: { breg = reg1; ireg = reg2; } \ 1396: if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ 1397: { int scale = 1; \ 1398: if (GET_CODE (ireg) == MULT) \ 1399: { scale = INTVAL (XEXP (ireg, 1)); \ 1400: ireg = XEXP (ireg, 0); } \ 1401: if (GET_CODE (ireg) == SIGN_EXTEND) \ 1402: fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:W", \ 1403: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1404: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1405: reg_name[REGNO (XEXP (ireg, 0))]); \ 1406: else \ 1407: fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L", \ 1408: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1409: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1410: reg_name[REGNO (ireg)]); \ 1411: fprintf (FILE, ":%c", sz[scale]); \ 1412: putc (']', FILE); \ 1413: break; } \ 1414: if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \ 1415: { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \ 1416: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1417: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1418: reg_name[REGNO (breg)]); \ 1419: break; } \ 1420: if (ireg != 0 || breg != 0) \ 1421: { int scale = 1; \ 1422: if (breg == 0) \ 1423: abort (); \ 1424: if (addr && GET_CODE (addr) == LABEL_REF) abort (); \ 1425: fprintf (FILE, "%s@", reg_name[REGNO (breg)]); \ 1426: if (addr != 0) { \ 1427: putc( '(', FILE ); \ 1428: output_addr_const (FILE, addr); \ 1429: if (ireg != 0) { \ 1430: if (GET_CODE(addr) == CONST_INT) { \ 1431: int size_of = 1, val = INTVAL(addr); \ 1432: if (val < -0x8000 || val >= 0x8000) \ 1433: size_of = 4; \ 1434: else if (val < -0x80 || val >= 0x80) \ 1435: size_of = 2; \ 1436: fprintf(FILE, ":%c", sz[size_of]); \ 1437: } \ 1438: else \ 1439: fprintf(FILE, ":L"); } \ 1440: putc( ')', FILE ); } \ 1441: if (ireg != 0) { \ 1442: putc ('[', FILE); \ 1443: if (ireg != 0 && GET_CODE (ireg) == MULT) \ 1444: { scale = INTVAL (XEXP (ireg, 1)); \ 1445: ireg = XEXP (ireg, 0); } \ 1446: if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ 1447: fprintf (FILE, "%s:W", reg_name[REGNO (XEXP (ireg, 0))]); \ 1448: else if (ireg != 0) \ 1449: fprintf (FILE, "%s:L", reg_name[REGNO (ireg)]); \ 1450: fprintf (FILE, ":%c", sz[scale]); \ 1451: putc (']', FILE); \ 1452: } \ 1453: break; \ 1454: } \ 1455: else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ 1456: { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \ 1457: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1458: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1459: reg_name[REGNO (reg1)]); \ 1460: break; } \ 1461: default: \ 1462: if (GET_CODE (addr) == CONST_INT \ 1463: && INTVAL (addr) < 0x8000 \ 1464: && INTVAL (addr) >= -0x8000) \ 1465: fprintf (FILE, "%d:W", INTVAL (addr)); \ 1466: else \ 1467: output_addr_const (FILE, addr); \ 1468: }} 1469: 1470: /* 1471: Local variables: 1472: version-control: t 1473: End: 1474: */ 1475: /* See tm-m68k.h. 3 means 68020 with 68881. */ 1476: 1477: #define TARGET_DEFAULT 3 1478: 1479: /* Define __HAVE_FPA__ or __HAVE_68881__ in preprocessor, 1480: according to the -m flags. 1481: This will control the use of inline 68881 insns in certain macros. 1482: Also inform the program which CPU this is for. */ 1483: 1484: #if TARGET_DEFAULT & 02 1485: 1486: /* -m68881 is the default */ 1487: #define CPP_SPEC \ 1488: "%{!msoft-float:%{mfpa:-D__HAVE_FPA__ }%{!mfpa:-D__HAVE_68881__ }}\ 1489: %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}" 1490: 1491: #else 1492: #if TARGET_DEFAULT & 0100 1493: 1494: /* -mfpa is the default */ 1495: #define CPP_SPEC \ 1496: "%{!msoft-float:%{m68881:-D__HAVE_68881__ }%{!m68881:-D__HAVE_FPA__ }}\ 1497: %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}" 1498: 1499: #else 1500: 1501: /* -msoft-float is the default */ 1502: #define CPP_SPEC \ 1503: "%{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }\ 1504: %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}" 1505: 1506: #endif 1507: #endif 1508: 1509: /* Names to predefine in the preprocessor for this target machine. */ 1510: 1511: #define CPP_PREDEFINES "-Dmc68000 -Dalliant -Dunix" 1512: 1513: /* Every structure or union's size must be a multiple of 2 bytes. */ 1514: 1515: #define STRUCTURE_SIZE_BOUNDARY 16 1516: 1517: /* This is BSD, so it wants DBX format. */ 1518: 1519: #define DBX_DEBUGGING_INFO
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.