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1.1 root 1: ;;- Machine description for GNU compiler
2: ;;- Vax Version
3: ;; Copyright (C) 1987 Free Software Foundation, Inc.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is distributed in the hope that it will be useful,
8: ;; but WITHOUT ANY WARRANTY. No author or distributor
9: ;; accepts responsibility to anyone for the consequences of using it
10: ;; or for whether it serves any particular purpose or works at all,
11: ;; unless he says so in writing. Refer to the GNU CC General Public
12: ;; License for full details.
13:
14: ;; Everyone is granted permission to copy, modify and redistribute
15: ;; GNU CC, but only under the conditions described in the
16: ;; GNU CC General Public License. A copy of this license is
17: ;; supposed to have been given to you along with GNU CC so you
18: ;; can know your rights and responsibilities. It should be in a
19: ;; file named COPYING. Among other things, the copyright notice
20: ;; and this notice must be preserved on all copies.
21:
22:
23: ;;- Instruction patterns. When multiple patterns apply,
24: ;;- the first one in the file is chosen.
25: ;;-
26: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
27: ;;-
28: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29: ;;- updates for most instructions.
30:
31: (define_insn "tstdf"
32: [(set (cc0)
33: (match_operand:DF 0 "general_operand" "gF"))]
34: ""
35: "tstd %0")
36:
37: (define_insn "tstsf"
38: [(set (cc0)
39: (match_operand:SF 0 "general_operand" "gF"))]
40: ""
41: "tstf %0")
42:
43: (define_insn "tstsi"
44: [(set (cc0)
45: (match_operand:SI 0 "general_operand" "g"))]
46: ""
47: "tstl %0")
48:
49: (define_insn "tsthi"
50: [(set (cc0)
51: (match_operand:HI 0 "general_operand" "g"))]
52: ""
53: "tstw %0")
54:
55: (define_insn "tstqi"
56: [(set (cc0)
57: (match_operand:QI 0 "general_operand" "g"))]
58: ""
59: "tstb %0")
60:
61: (define_insn "cmpdf"
62: [(set (cc0)
63: (minus (match_operand:DF 0 "general_operand" "gF")
64: (match_operand:DF 1 "general_operand" "gF")))]
65: ""
66: "cmpd %0,%1")
67:
68: (define_insn "cmpsf"
69: [(set (cc0)
70: (minus (match_operand:SF 0 "general_operand" "gF")
71: (match_operand:SF 1 "general_operand" "gF")))]
72: ""
73: "cmpf %0,%1")
74:
75: (define_insn "cmpsi"
76: [(set (cc0)
77: (minus (match_operand:SI 0 "general_operand" "g")
78: (match_operand:SI 1 "general_operand" "g")))]
79: ""
80: "cmpl %0,%1")
81:
82: (define_insn "cmphi"
83: [(set (cc0)
84: (minus (match_operand:HI 0 "general_operand" "g")
85: (match_operand:HI 1 "general_operand" "g")))]
86: ""
87: "cmpw %0,%1")
88:
89: (define_insn "cmpqi"
90: [(set (cc0)
91: (minus (match_operand:QI 0 "general_operand" "g")
92: (match_operand:QI 1 "general_operand" "g")))]
93: ""
94: "cmpb %0,%1")
95:
96: (define_insn ""
97: [(set (cc0)
98: (and:SI (match_operand:SI 0 "general_operand" "g")
99: (match_operand:SI 1 "general_operand" "g")))]
100: ""
101: "bitl %0,%1")
102:
103: (define_insn ""
104: [(set (cc0)
105: (and:HI (match_operand:HI 0 "general_operand" "g")
106: (match_operand:HI 1 "general_operand" "g")))]
107: ""
108: "bitw %0,%1")
109:
110: (define_insn ""
111: [(set (cc0)
112: (and:QI (match_operand:QI 0 "general_operand" "g")
113: (match_operand:QI 1 "general_operand" "g")))]
114: ""
115: "bitb %0,%1")
116:
117: (define_insn "movdf"
118: [(set (match_operand:DF 0 "general_operand" "=g")
119: (match_operand:DF 1 "general_operand" "gF"))]
120: ""
121: "*
122: {
123: if (operands[1] == dconst0_rtx)
124: return \"clrd %0\";
125: return \"movd %1,%0\";
126: }")
127:
128: (define_insn "movsf"
129: [(set (match_operand:SF 0 "general_operand" "=g")
130: (match_operand:SF 1 "general_operand" "gF"))]
131: ""
132: "*
133: {
134: if (operands[1] == fconst0_rtx)
135: return \"clrf %0\";
136: return \"movf %1,%0\";
137: }")
138:
139: (define_insn "movti"
140: [(set (match_operand:TI 0 "general_operand" "=g")
141: (match_operand:TI 1 "general_operand" "g"))]
142: ""
143: "movh %1,%0")
144:
145: (define_insn "movdi"
146: [(set (match_operand:DI 0 "general_operand" "=g")
147: (match_operand:DI 1 "general_operand" "g"))]
148: ""
149: "movd %1,%0")
150:
151: (define_insn "movsi"
152: [(set (match_operand:SI 0 "general_operand" "=g")
153: (match_operand:SI 1 "general_operand" "g"))]
154: ""
155: "*
156: { if (operands[1] == const1_rtx
157: && GET_MODE (REG_NOTES (insn)) == (enum machine_mode) REG_WAS_0)
158: return \"incl %0\";
159: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
160: {
161: if (push_operand (operands[0], SImode))
162: return \"pushab %a1\";
163: return \"movab %a1,%0\";
164: }
165: if (operands[1] == const0_rtx)
166: return \"clrl %0\";
167: if (GET_CODE (operands[1]) == CONST_INT
168: && (unsigned) INTVAL (operands[1]) >= 64)
169: {
170: int i = INTVAL (operands[1]);
171: if ((unsigned)(-i) < 64)
172: {
173: operands[1] = gen_rtx (CONST_INT, VOIDmode, -i);
174: return \"mnegl %1,%0\";
175: }
176: if ((unsigned)i < 0x100)
177: return \"movzbl %1,%0\";
178: if (i >= -0x80 && i < 0)
179: return \"cvtbl %1,%0\";
180: if ((unsigned)i < 0x10000)
181: return \"movzwl %1,%0\";
182: if (i >= -0x8000 && i < 0)
183: return \"cvtwl %1,%0\";
184: }
185: if (push_operand (operands[0], SImode))
186: return \"pushl %1\";
187: return \"movl %1,%0\";
188: }")
189:
190: (define_insn "movhi"
191: [(set (match_operand:HI 0 "general_operand" "=g")
192: (match_operand:HI 1 "general_operand" "g"))]
193: ""
194: "*
195: {
196: if (operands[1] == const1_rtx
197: && GET_MODE (REG_NOTES (insn)) == (enum machine_mode) REG_WAS_0)
198: return \"incw %0\";
199: if (operands[1] == const0_rtx)
200: return \"clrw %0\";
201: if (GET_CODE (operands[1]) == CONST_INT
202: && (unsigned) INTVAL (operands[1]) >= 64)
203: {
204: int i = INTVAL (operands[1]);
205: if ((unsigned)(-i) < 64)
206: {
207: operands[1] = gen_rtx (CONST_INT, VOIDmode, -i);
208: return \"mnegw %1,%0\";
209: }
210: if ((unsigned)i < 0x100)
211: return \"movzbw %1,%0\";
212: if (i >= -0x80 && i < 0)
213: return \"cvtbw %1,%0\";
214: }
215: return \"movw %1,%0\";
216: }")
217:
218: (define_insn "movqi"
219: [(set (match_operand:QI 0 "general_operand" "=g")
220: (match_operand:QI 1 "general_operand" "g"))]
221: ""
222: "*
223: {
224: if (operands[1] == const0_rtx)
225: return \"clrb %0\";
226: return \"movb %1,%0\";
227: }")
228:
229: ;; The definition of this insn does not really explain what it does,
230: ;; but it should suffice
231: ;; that anything generated as this insn will be recognized as one
232: ;; and that it won't successfully combine with anything.
233: (define_insn "movstrhi"
234: [(set (match_operand:BLK 0 "general_operand" "=g")
235: (match_operand:BLK 1 "general_operand" "g"))
236: (use (match_operand:HI 2 "general_operand" "g"))
237: (clobber (nil)) ;;- Clobber everything in memory
238: (clobber (reg 0))
239: (clobber (reg 1))
240: (clobber (reg 2))
241: (clobber (reg 3))
242: (clobber (reg 4))
243: (clobber (reg 5))]
244: ""
245: "movc3 %2,%1,%0")
246:
247: ;;- load or push effective address
248: ;; These come after the move patterns
249: ;; because we don't want pushl $1 turned into pushad 1.
250:
251: (define_insn ""
252: [(set (match_operand:SI 0 "general_operand" "=g")
253: (match_operand:QI 1 "address_operand" "p"))]
254: ""
255: "*
256: {
257: if (push_operand (operands[0], SImode))
258: return \"pushab %a1\";
259: return \"movab %a1,%0\";
260: }")
261:
262: (define_insn ""
263: [(set (match_operand:SI 0 "general_operand" "=g")
264: (match_operand:HI 1 "address_operand" "p"))]
265: ""
266: "*
267: {
268: if (push_operand (operands[0], SImode))
269: return \"pushaw %a1\";
270: return \"movaw %a1,%0\";
271: }")
272:
273: (define_insn ""
274: [(set (match_operand:SI 0 "general_operand" "=g")
275: (match_operand:SI 1 "address_operand" "p"))]
276: ""
277: "*
278: {
279: if (push_operand (operands[0], SImode))
280: return \"pushal %a1\";
281: return \"moval %a1,%0\";
282: }")
283:
284: (define_insn ""
285: [(set (match_operand:SI 0 "general_operand" "=g")
286: (match_operand:SF 1 "address_operand" "p"))]
287: ""
288: "*
289: {
290: if (push_operand (operands[0], SImode))
291: return \"pushaf %a1\";
292: return \"movaf %a1,%0\";
293: }")
294:
295: (define_insn ""
296: [(set (match_operand:SI 0 "general_operand" "=g")
297: (match_operand:DF 1 "address_operand" "p"))]
298: ""
299: "*
300: {
301: if (push_operand (operands[0], SImode))
302: return \"pushad %a1\";
303: return \"movad %a1,%0\";
304: }")
305:
306: (define_insn "extendqihi2"
307: [(set (match_operand:HI 0 "general_operand" "=g")
308: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
309: ""
310: "cvtbw %1,%0")
311:
312: (define_insn "extendqisi2"
313: [(set (match_operand:SI 0 "general_operand" "=g")
314: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
315: ""
316: "cvtbl %1,%0")
317:
318: (define_insn "floatqisf2"
319: [(set (match_operand:SF 0 "general_operand" "=g")
320: (float:SF (match_operand:QI 1 "general_operand" "g")))]
321: ""
322: "cvtbf %1,%0")
323:
324: (define_insn "floatqidf2"
325: [(set (match_operand:DF 0 "general_operand" "=g")
326: (float:DF (match_operand:QI 1 "general_operand" "g")))]
327: ""
328: "cvtbd %1,%0")
329:
330: (define_insn "trunchiqi2"
331: [(set (match_operand:QI 0 "general_operand" "=g")
332: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
333: ""
334: "cvtwb %1,%0")
335:
336: (define_insn "extendhisi2"
337: [(set (match_operand:SI 0 "general_operand" "=g")
338: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
339: ""
340: "cvtwl %1,%0")
341:
342: (define_insn "floathisf2"
343: [(set (match_operand:SF 0 "general_operand" "=g")
344: (float:SF (match_operand:HI 1 "general_operand" "g")))]
345: ""
346: "cvtwf %1,%0")
347:
348: (define_insn "floathidf2"
349: [(set (match_operand:DF 0 "general_operand" "=g")
350: (float:DF (match_operand:HI 1 "general_operand" "g")))]
351: ""
352: "cvtwd %1,%0")
353:
354: (define_insn "truncsiqi2"
355: [(set (match_operand:QI 0 "general_operand" "=g")
356: (truncate:QI (match_operand:SI 1 "general_operand" "g")))]
357: ""
358: "cvtlb %1,%0")
359:
360: (define_insn "truncsihi2"
361: [(set (match_operand:HI 0 "general_operand" "=g")
362: (truncate:HI (match_operand:SI 1 "general_operand" "g")))]
363: ""
364: "cvtlw %1,%0")
365:
366: (define_insn "floatsisf2"
367: [(set (match_operand:SF 0 "general_operand" "=g")
368: (float:SF (match_operand:SI 1 "general_operand" "g")))]
369: ""
370: "cvtlf %1,%0")
371:
372: (define_insn "floatsidf2"
373: [(set (match_operand:DF 0 "general_operand" "=g")
374: (float:DF (match_operand:SI 1 "general_operand" "g")))]
375: ""
376: "cvtld %1,%0")
377:
378: (define_insn "fixsfqi2"
379: [(set (match_operand:QI 0 "general_operand" "=g")
380: (fix:QI (match_operand:SF 1 "general_operand" "gF")))]
381: ""
382: "cvtfb %1,%0")
383:
384: (define_insn "fixsfhi2"
385: [(set (match_operand:HI 0 "general_operand" "=g")
386: (fix:HI (match_operand:SF 1 "general_operand" "gF")))]
387: ""
388: "cvtfw %1,%0")
389:
390: (define_insn "fixsfsi2"
391: [(set (match_operand:SI 0 "general_operand" "=g")
392: (fix:SI (match_operand:SF 1 "general_operand" "gF")))]
393: ""
394: "cvtfl %1,%0")
395:
396: (define_insn "extendsfdf2"
397: [(set (match_operand:DF 0 "general_operand" "=g")
398: (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
399: ""
400: "cvtfd %1,%0")
401:
402: (define_insn "fixdfqi2"
403: [(set (match_operand:QI 0 "general_operand" "=g")
404: (fix:QI (match_operand:DF 1 "general_operand" "gF")))]
405: ""
406: "cvtdb %1,%0")
407:
408: (define_insn "fixdfhi2"
409: [(set (match_operand:HI 0 "general_operand" "=g")
410: (fix:HI (match_operand:DF 1 "general_operand" "gF")))]
411: ""
412: "cvtdw %1,%0")
413:
414: (define_insn "fixdfsi2"
415: [(set (match_operand:SI 0 "general_operand" "=g")
416: (fix:SI (match_operand:DF 1 "general_operand" "gF")))]
417: ""
418: "cvtdl %1,%0")
419:
420: (define_insn "truncdfsf2"
421: [(set (match_operand:SF 0 "general_operand" "=g")
422: (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
423: ""
424: "cvtdf %1,%0")
425:
426: (define_insn "zero_extendqihi2"
427: [(set (match_operand:HI 0 "general_operand" "=g")
428: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
429: ""
430: "movzbw %1,%0")
431:
432: (define_insn "zero_extendqisi2"
433: [(set (match_operand:SI 0 "general_operand" "=g")
434: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
435: ""
436: "movzbl %1,%0")
437:
438: (define_insn "zero_extendhisi2"
439: [(set (match_operand:SI 0 "general_operand" "=g")
440: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
441: ""
442: "movzwl %1,%0")
443:
444: ;;- All kinds of add instructions.
445:
446: (define_insn "adddf3"
447: [(set (match_operand:DF 0 "general_operand" "=g")
448: (plus:DF (match_operand:DF 1 "general_operand" "gF")
449: (match_operand:DF 2 "general_operand" "gF")))]
450: ""
451: "*
452: {
453: if (rtx_equal_p (operands[0], operands[1]))
454: return \"addd2 %2,%0\";
455: if (rtx_equal_p (operands[0], operands[2]))
456: return \"addd2 %1,%0\";
457: return \"addd3 %1,%2,%0\";
458: }")
459:
460: (define_insn "addsf3"
461: [(set (match_operand:SF 0 "general_operand" "=g")
462: (plus:SF (match_operand:SF 1 "general_operand" "gF")
463: (match_operand:SF 2 "general_operand" "gF")))]
464: ""
465: "*
466: {
467: if (rtx_equal_p (operands[0], operands[1]))
468: return \"addf2 %2,%0\";
469: if (rtx_equal_p (operands[0], operands[2]))
470: return \"addf2 %1,%0\";
471: return \"addf3 %1,%2,%0\";
472: }")
473:
474: (define_insn "addsi3"
475: [(set (match_operand:SI 0 "general_operand" "=g")
476: (plus:SI (match_operand:SI 1 "general_operand" "g")
477: (match_operand:SI 2 "general_operand" "g")))]
478: ""
479: "*
480: {
481: if (rtx_equal_p (operands[0], operands[1]))
482: {
483: if (operands[2] == const1_rtx)
484: return \"incl %0\";
485: if (GET_CODE (operands[1]) == CONST_INT
486: && INTVAL (operands[1]) == -1)
487: return \"decl %0\";
488: if (GET_CODE (operands[2]) == CONST_INT
489: && (unsigned) (- INTVAL (operands[2])) < 64)
490: return \"subl2 $%n2,%0\";
491: return \"addl2 %2,%0\";
492: }
493: if (rtx_equal_p (operands[0], operands[2]))
494: return \"addl2 %1,%0\";
495: if (GET_CODE (operands[2]) == CONST_INT
496: && GET_CODE (operands[1]) == REG)
497: {
498: if (push_operand (operands[0], SImode))
499: return \"pushab %c2(%1)\";
500: return \"movab %c2(%1),%0\";
501: }
502: if (GET_CODE (operands[2]) == CONST_INT
503: && (unsigned) (- INTVAL (operands[2])) < 64)
504: return \"subl3 $%n2,%1,%0\";
505: return \"addl3 %1,%2,%0\";
506: }")
507:
508: (define_insn "addhi3"
509: [(set (match_operand:HI 0 "general_operand" "=g")
510: (plus:HI (match_operand:HI 1 "general_operand" "g")
511: (match_operand:HI 2 "general_operand" "g")))]
512: ""
513: "*
514: {
515: if (rtx_equal_p (operands[0], operands[1]))
516: {
517: if (operands[2] == const1_rtx)
518: return \"incw %0\";
519: if (GET_CODE (operands[1]) == CONST_INT
520: && INTVAL (operands[1]) == -1)
521: return \"decw %0\";
522: if (GET_CODE (operands[2]) == CONST_INT
523: && (unsigned) (- INTVAL (operands[2])) < 64)
524: return \"subw2 $%n2,%0\";
525: return \"addw2 %2,%0\";
526: }
527: if (rtx_equal_p (operands[0], operands[2]))
528: return \"addw2 %1,%0\";
529: if (GET_CODE (operands[2]) == CONST_INT
530: && (unsigned) (- INTVAL (operands[2])) < 64)
531: return \"subw3 $%n2,%1,%0\";
532: return \"addw3 %1,%2,%0\";
533: }")
534:
535: (define_insn "addqi3"
536: [(set (match_operand:QI 0 "general_operand" "=g")
537: (plus:QI (match_operand:QI 1 "general_operand" "g")
538: (match_operand:QI 2 "general_operand" "g")))]
539: ""
540: "*
541: {
542: if (rtx_equal_p (operands[0], operands[1]))
543: {
544: if (operands[2] == const1_rtx)
545: return \"incb %0\";
546: if (GET_CODE (operands[1]) == CONST_INT
547: && INTVAL (operands[1]) == -1)
548: return \"decb %0\";
549: if (GET_CODE (operands[2]) == CONST_INT
550: && (unsigned) (- INTVAL (operands[2])) < 64)
551: return \"subb2 $%n2,%0\";
552: return \"addb2 %2,%0\";
553: }
554: if (rtx_equal_p (operands[0], operands[2]))
555: return \"addb2 %1,%0\";
556: if (GET_CODE (operands[2]) == CONST_INT
557: && (unsigned) (- INTVAL (operands[2])) < 64)
558: return \"subb3 $%n2,%1,%0\";
559: return \"addb3 %1,%2,%0\";
560: }")
561:
562: ;;- All kinds of subtract instructions.
563:
564: (define_insn "subdf3"
565: [(set (match_operand:DF 0 "general_operand" "=g")
566: (minus:DF (match_operand:DF 1 "general_operand" "gF")
567: (match_operand:DF 2 "general_operand" "gF")))]
568: ""
569: "*
570: {
571: if (rtx_equal_p (operands[0], operands[1]))
572: return \"subd2 %2,%0\";
573: return \"subd3 %2,%1,%0\";
574: }")
575:
576: (define_insn "subsf3"
577: [(set (match_operand:SF 0 "general_operand" "=g")
578: (minus:SF (match_operand:SF 1 "general_operand" "gF")
579: (match_operand:SF 2 "general_operand" "gF")))]
580: ""
581: "*
582: {
583: if (rtx_equal_p (operands[0], operands[1]))
584: return \"subf2 %2,%0\";
585: return \"subf3 %2,%1,%0\";
586: }")
587:
588: (define_insn "subsi3"
589: [(set (match_operand:SI 0 "general_operand" "=g")
590: (minus:SI (match_operand:SI 1 "general_operand" "g")
591: (match_operand:SI 2 "general_operand" "g")))]
592: ""
593: "*
594: {
595: if (rtx_equal_p (operands[0], operands[1]))
596: {
597: if (operands[2] == const1_rtx)
598: return \"decl %0\";
599: return \"subl2 %2,%0\";
600: }
601: return \"subl3 %2,%1,%0\";
602: }")
603:
604: (define_insn "subhi3"
605: [(set (match_operand:HI 0 "general_operand" "=g")
606: (minus:HI (match_operand:HI 1 "general_operand" "g")
607: (match_operand:HI 2 "general_operand" "g")))]
608: ""
609: "*
610: {
611: if (rtx_equal_p (operands[0], operands[1]))
612: {
613: if (operands[2] == const1_rtx)
614: return \"decw %0\";
615: return \"subw2 %2,%0\";
616: }
617: return \"subw3 %2,%1,%0\";
618: }")
619:
620: (define_insn "subqi3"
621: [(set (match_operand:QI 0 "general_operand" "=g")
622: (minus:QI (match_operand:QI 1 "general_operand" "g")
623: (match_operand:QI 2 "general_operand" "g")))]
624: ""
625: "*
626: {
627: if (rtx_equal_p (operands[0], operands[1]))
628: {
629: if (operands[2] == const1_rtx)
630: return \"decb %0\";
631: return \"subb2 %2,%0\";
632: }
633: return \"subb3 %2,%1,%0\";
634: }")
635:
636: ;;- Multiply instructions.
637:
638: (define_insn "muldf3"
639: [(set (match_operand:DF 0 "general_operand" "=g")
640: (mult:DF (match_operand:DF 1 "general_operand" "gF")
641: (match_operand:DF 2 "general_operand" "gF")))]
642: ""
643: "*
644: {
645: if (rtx_equal_p (operands[0], operands[1]))
646: return \"muld2 %2,%0\";
647: if (rtx_equal_p (operands[0], operands[2]))
648: return \"muld2 %1,%0\";
649: return \"muld3 %1,%2,%0\";
650: }")
651:
652: (define_insn "mulsf3"
653: [(set (match_operand:SF 0 "general_operand" "=g")
654: (mult:SF (match_operand:SF 1 "general_operand" "gF")
655: (match_operand:SF 2 "general_operand" "gF")))]
656: ""
657: "*
658: {
659: if (rtx_equal_p (operands[0], operands[1]))
660: return \"mulf2 %2,%0\";
661: if (rtx_equal_p (operands[0], operands[2]))
662: return \"mulf2 %1,%0\";
663: return \"mulf3 %1,%2,%0\";
664: }")
665:
666: (define_insn "mulsi3"
667: [(set (match_operand:SI 0 "general_operand" "=g")
668: (mult:SI (match_operand:SI 1 "general_operand" "g")
669: (match_operand:SI 2 "general_operand" "g")))]
670: ""
671: "*
672: {
673: if (rtx_equal_p (operands[0], operands[1]))
674: return \"mull2 %2,%0\";
675: if (rtx_equal_p (operands[0], operands[2]))
676: return \"mull2 %1,%0\";
677: return \"mull3 %1,%2,%0\";
678: }")
679:
680: (define_insn "mulhi3"
681: [(set (match_operand:HI 0 "general_operand" "=g")
682: (mult:HI (match_operand:HI 1 "general_operand" "g")
683: (match_operand:HI 2 "general_operand" "g")))]
684: ""
685: "*
686: {
687: if (rtx_equal_p (operands[0], operands[1]))
688: return \"mulw2 %2,%0\";
689: if (rtx_equal_p (operands[0], operands[2]))
690: return \"mulw2 %1,%0\";
691: return \"mulw3 %1,%2,%0\";
692: }")
693:
694: (define_insn "mulqi3"
695: [(set (match_operand:QI 0 "general_operand" "=g")
696: (mult:QI (match_operand:QI 1 "general_operand" "g")
697: (match_operand:QI 2 "general_operand" "g")))]
698: ""
699: "*
700: {
701: if (rtx_equal_p (operands[0], operands[1]))
702: return \"mulb2 %2,%0\";
703: if (rtx_equal_p (operands[0], operands[2]))
704: return \"mulb2 %1,%0\";
705: return \"mulb3 %1,%2,%0\";
706: }")
707:
708: ;;- Divide instructions.
709:
710: (define_insn "divdf3"
711: [(set (match_operand:DF 0 "general_operand" "=g")
712: (div:DF (match_operand:DF 1 "general_operand" "gF")
713: (match_operand:DF 2 "general_operand" "gF")))]
714: ""
715: "*
716: {
717: if (rtx_equal_p (operands[0], operands[1]))
718: return \"divd2 %2,%0\";
719: return \"divd3 %2,%1,%0\";
720: }")
721:
722: (define_insn "divsf3"
723: [(set (match_operand:SF 0 "general_operand" "=g")
724: (div:SF (match_operand:SF 1 "general_operand" "gF")
725: (match_operand:SF 2 "general_operand" "gF")))]
726: ""
727: "*
728: {
729: if (rtx_equal_p (operands[0], operands[1]))
730: return \"divf2 %2,%0\";
731: return \"divf3 %2,%1,%0\";
732: }")
733:
734: (define_insn "divsi3"
735: [(set (match_operand:SI 0 "general_operand" "=g")
736: (div:SI (match_operand:SI 1 "general_operand" "g")
737: (match_operand:SI 2 "general_operand" "g")))]
738: ""
739: "*
740: {
741: if (rtx_equal_p (operands[0], operands[1]))
742: return \"divl2 %2,%0\";
743: return \"divl3 %2,%1,%0\";
744: }")
745:
746: (define_insn "divhi3"
747: [(set (match_operand:HI 0 "general_operand" "=g")
748: (div:HI (match_operand:HI 1 "general_operand" "g")
749: (match_operand:HI 2 "general_operand" "g")))]
750: ""
751: "*
752: {
753: if (rtx_equal_p (operands[0], operands[1]))
754: return \"divw2 %2,%0\";
755: return \"divw3 %2,%1,%0\";
756: }")
757:
758: (define_insn "divqi3"
759: [(set (match_operand:QI 0 "general_operand" "=g")
760: (div:QI (match_operand:QI 1 "general_operand" "g")
761: (match_operand:QI 2 "general_operand" "g")))]
762: ""
763: "*
764: {
765: if (rtx_equal_p (operands[0], operands[1]))
766: return \"divb2 %2,%0\";
767: return \"divb3 %2,%1,%0\";
768: }")
769:
770: ;This is left out because it is very slow;
771: ;we are better off programming around the "lack" of this insn.
772: ;(define_insn "divmoddisi4"
773: ; [(set (match_operand:SI 0 "general_operand" "=g")
774: ; (div:SI (match_operand:DI 1 "general_operand" "g")
775: ; (match_operand:SI 2 "general_operand" "g")))
776: ; (set (match_operand:SI 3 "general_operand" "=g")
777: ; (mod:SI (match_operand:DI 1 "general_operand" "g")
778: ; (match_operand:SI 2 "general_operand" "g")))]
779: ; ""
780: ; "ediv %2,%1,%0,%3")
781:
782: (define_insn "andcbsi3"
783: [(set (match_operand:SI 0 "general_operand" "=g")
784: (and:SI (match_operand:SI 1 "general_operand" "g")
785: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
786: ""
787: "*
788: {
789: if (rtx_equal_p (operands[0], operands[1]))
790: return \"bicl2 %2,%0\";
791: return \"bicl3 %2,%1,%0\";
792: }")
793:
794: (define_insn "andcbhi3"
795: [(set (match_operand:HI 0 "general_operand" "=g")
796: (and:HI (match_operand:HI 1 "general_operand" "g")
797: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
798: ""
799: "*
800: {
801: if (rtx_equal_p (operands[0], operands[1]))
802: return \"bicw2 %2,%0\";
803: return \"bicw3 %2,%1,%0\";
804: }")
805:
806: (define_insn "andcbqi3"
807: [(set (match_operand:QI 0 "general_operand" "=g")
808: (and:QI (match_operand:QI 1 "general_operand" "g")
809: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
810: ""
811: "*
812: {
813: if (rtx_equal_p (operands[0], operands[1]))
814: return \"bicb2 %2,%0\";
815: return \"bicb3 %2,%1,%0\";
816: }")
817:
818: ;; The following are needed because constant propagation can
819: ;; create them starting from the bic insn patterns above.
820:
821: (define_insn ""
822: [(set (match_operand:SI 0 "general_operand" "=g")
823: (and:SI (match_operand:SI 1 "general_operand" "g")
824: (match_operand:SI 2 "general_operand" "g")))]
825: "GET_CODE (operands[2]) == CONST_INT"
826: "*
827: { operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
828: if (rtx_equal_p (operands[1], operands[0]))
829: return \"bicl2 %2,%0\";
830: return \"bicl3 %2,%1,%0\";
831: }")
832:
833: (define_insn ""
834: [(set (match_operand:HI 0 "general_operand" "=g")
835: (and:HI (match_operand:HI 1 "general_operand" "g")
836: (match_operand:HI 2 "general_operand" "g")))]
837: "GET_CODE (operands[2]) == CONST_INT"
838: "*
839: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xffff & ~INTVAL (operands[2]));
840: if (rtx_equal_p (operands[1], operands[0]))
841: return \"bicw2 %2,%0\";
842: return \"bicw3 %2,%1,%0\";
843: }")
844:
845: (define_insn ""
846: [(set (match_operand:QI 0 "general_operand" "=g")
847: (and:QI (match_operand:QI 1 "general_operand" "g")
848: (match_operand:QI 2 "general_operand" "g")))]
849: "GET_CODE (operands[2]) == CONST_INT"
850: "*
851: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xff & ~INTVAL (operands[2]));
852: if (rtx_equal_p (operands[1], operands[0]))
853: return \"bicb2 %2,%0\";
854: return \"bicb3 %2,%1,%0\";
855: }")
856:
857: ;;- Bit set instructions.
858:
859: (define_insn "iorsi3"
860: [(set (match_operand:SI 0 "general_operand" "=g")
861: (ior:SI (match_operand:SI 1 "general_operand" "g")
862: (match_operand:SI 2 "general_operand" "g")))]
863: ""
864: "*
865: {
866: if (rtx_equal_p (operands[0], operands[1]))
867: return \"bisl2 %2,%0\";
868: if (rtx_equal_p (operands[0], operands[2]))
869: return \"bisl2 %1,%0\";
870: return \"bisl3 %2,%1,%0\";
871: }")
872:
873: (define_insn "iorhi3"
874: [(set (match_operand:HI 0 "general_operand" "=g")
875: (ior:HI (match_operand:HI 1 "general_operand" "g")
876: (match_operand:HI 2 "general_operand" "g")))]
877: ""
878: "*
879: {
880: if (rtx_equal_p (operands[0], operands[1]))
881: return \"bisw2 %2,%0\";
882: if (rtx_equal_p (operands[0], operands[2]))
883: return \"bisw2 %1,%0\";
884: return \"bisw3 %2,%1,%0\";
885: }")
886:
887: (define_insn "iorqi3"
888: [(set (match_operand:QI 0 "general_operand" "=g")
889: (ior:QI (match_operand:QI 1 "general_operand" "g")
890: (match_operand:QI 2 "general_operand" "g")))]
891: ""
892: "*
893: {
894: if (rtx_equal_p (operands[0], operands[1]))
895: return \"bisb2 %2,%0\";
896: if (rtx_equal_p (operands[0], operands[2]))
897: return \"bisb2 %1,%0\";
898: return \"bisb3 %2,%1,%0\";
899: }")
900:
901: ;;- xor instructions.
902:
903: (define_insn "xorsi3"
904: [(set (match_operand:SI 0 "general_operand" "=g")
905: (xor:SI (match_operand:SI 1 "general_operand" "g")
906: (match_operand:SI 2 "general_operand" "g")))]
907: ""
908: "*
909: {
910: if (rtx_equal_p (operands[0], operands[1]))
911: return \"xorl2 %2,%0\";
912: if (rtx_equal_p (operands[0], operands[2]))
913: return \"xorl2 %1,%0\";
914: return \"xorl3 %2,%1,%0\";
915: }")
916:
917: (define_insn "xorhi3"
918: [(set (match_operand:HI 0 "general_operand" "=g")
919: (xor:HI (match_operand:HI 1 "general_operand" "g")
920: (match_operand:HI 2 "general_operand" "g")))]
921: ""
922: "*
923: {
924: if (rtx_equal_p (operands[0], operands[1]))
925: return \"xorw2 %2,%0\";
926: if (rtx_equal_p (operands[0], operands[2]))
927: return \"xorw2 %1,%0\";
928: return \"xorw3 %2,%1,%0\";
929: }")
930:
931: (define_insn "xorqi3"
932: [(set (match_operand:QI 0 "general_operand" "=g")
933: (xor:QI (match_operand:QI 1 "general_operand" "g")
934: (match_operand:QI 2 "general_operand" "g")))]
935: ""
936: "*
937: {
938: if (rtx_equal_p (operands[0], operands[1]))
939: return \"xorb2 %2,%0\";
940: if (rtx_equal_p (operands[0], operands[2]))
941: return \"xorb2 %1,%0\";
942: return \"xorb3 %2,%1,%0\";
943: }")
944:
945: (define_insn "negdf2"
946: [(set (match_operand:DF 0 "general_operand" "=g")
947: (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
948: ""
949: "mnegd %1,%0")
950:
951: (define_insn "negsf2"
952: [(set (match_operand:SF 0 "general_operand" "=g")
953: (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
954: ""
955: "mnegf %1,%0")
956:
957: (define_insn "negsi2"
958: [(set (match_operand:SI 0 "general_operand" "=g")
959: (neg:SI (match_operand:SI 1 "general_operand" "g")))]
960: ""
961: "mnegl %1,%0")
962:
963: (define_insn "neghi2"
964: [(set (match_operand:HI 0 "general_operand" "=g")
965: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
966: ""
967: "mnegw %1,%0")
968:
969: (define_insn "negqi2"
970: [(set (match_operand:QI 0 "general_operand" "=g")
971: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
972: ""
973: "mnegb %1,%0")
974:
975: (define_insn "one_cmplsi2"
976: [(set (match_operand:SI 0 "general_operand" "=g")
977: (not:SI (match_operand:SI 1 "general_operand" "g")))]
978: ""
979: "mcoml %1,%0")
980:
981: (define_insn "one_cmplhi2"
982: [(set (match_operand:HI 0 "general_operand" "=g")
983: (not:HI (match_operand:HI 1 "general_operand" "g")))]
984: ""
985: "mcomw %1,%0")
986:
987: (define_insn "one_cmplqi2"
988: [(set (match_operand:QI 0 "general_operand" "=g")
989: (not:QI (match_operand:QI 1 "general_operand" "g")))]
990: ""
991: "mcomb %1,%0")
992:
993: (define_insn "ashlsi3"
994: [(set (match_operand:SI 0 "general_operand" "=g")
995: (ashift:SI (match_operand:SI 1 "general_operand" "g")
996: (match_operand:QI 2 "general_operand" "g")))]
997: ""
998: "ashl %2,%1,%0")
999:
1000: (define_insn "ashldi3"
1001: [(set (match_operand:DI 0 "general_operand" "=g")
1002: (ashift:DI (match_operand:DI 1 "general_operand" "g")
1003: (match_operand:QI 2 "general_operand" "g")))]
1004: ""
1005: "ashq %2,%1,%0")
1006:
1007: (define_insn "rotlsi3"
1008: [(set (match_operand:SI 0 "general_operand" "=g")
1009: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1010: (match_operand:QI 2 "general_operand" "g")))]
1011: ""
1012: "rotl %2,%1,%0")
1013:
1014: (define_insn "rotldi3"
1015: [(set (match_operand:DI 0 "general_operand" "=g")
1016: (rotate:DI (match_operand:DI 1 "general_operand" "g")
1017: (match_operand:QI 2 "general_operand" "g")))]
1018: ""
1019: "rotq %2,%1,%0")
1020:
1021: (define_insn ""
1022: [(set (match_operand:SI 0 "general_operand" "=g")
1023: (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1024: (match_operand:SI 2 "general_operand" "g"))
1025: (match_operand:SI 3 "general_operand" "g")))]
1026: ""
1027: "index %1,$??,$??,%3,%2,%0")
1028:
1029: (define_insn ""
1030: [(set (cc0)
1031: (minus
1032: (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1033: (match_operand:SI 1 "general_operand" "g")
1034: (match_operand:SI 2 "general_operand" "g"))
1035: (match_operand:SI 3 "general_operand" "g")))]
1036: ""
1037: "cmpv %2,%1,%0,%3")
1038:
1039: (define_insn ""
1040: [(set (cc0)
1041: (minus
1042: (zero_extract:SI (match_operand:QI 0 "general_operand" "g")
1043: (match_operand:SI 1 "general_operand" "g")
1044: (match_operand:SI 2 "general_operand" "g"))
1045: (match_operand:SI 3 "general_operand" "g")))]
1046: ""
1047: "cmpzv %2,%1,%0,%3")
1048:
1049: (define_insn "extv"
1050: [(set (match_operand:SI 0 "general_operand" "=g")
1051: (sign_extract:SI (match_operand:QI 1 "general_operand" "g")
1052: (match_operand:SI 2 "general_operand" "g")
1053: (match_operand:SI 3 "general_operand" "g")))]
1054: ""
1055: "extv %3,%2,%1,%0")
1056:
1057: (define_insn "extzv"
1058: [(set (match_operand:SI 0 "general_operand" "=g")
1059: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1060: (match_operand:SI 2 "general_operand" "g")
1061: (match_operand:SI 3 "general_operand" "g")))]
1062: ""
1063: "extzv %3,%2,%1,%0")
1064:
1065: (define_insn ""
1066: [(set (match_operand:SI 0 "general_operand" "=g")
1067: (sign_extract:SI (match_operand:SI 1 "general_operand" "r")
1068: (match_operand:SI 2 "general_operand" "g")
1069: (match_operand:SI 3 "general_operand" "g")))]
1070: ""
1071: "extv %3,%2,%1,%0")
1072:
1073: (define_insn ""
1074: [(set (match_operand:SI 0 "general_operand" "=g")
1075: (zero_extract:SI (match_operand:SI 1 "general_operand" "r")
1076: (match_operand:SI 2 "general_operand" "g")
1077: (match_operand:SI 3 "general_operand" "g")))]
1078: ""
1079: "extzv %3,%2,%1,%0")
1080:
1081: (define_insn "insv"
1082: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g")
1083: (match_operand:SI 1 "general_operand" "g")
1084: (match_operand:SI 2 "general_operand" "g"))
1085: (match_operand:SI 3 "general_operand" "g"))]
1086: ""
1087: "insv %3,%2,%1,%0")
1088:
1089: (define_insn ""
1090: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "=r")
1091: (match_operand:SI 1 "general_operand" "g")
1092: (match_operand:SI 2 "general_operand" "g"))
1093: (match_operand:SI 3 "general_operand" "g"))]
1094: ""
1095: "insv %3,%2,%1,%0")
1096:
1097: (define_insn "jump"
1098: [(set (pc)
1099: (label_ref (match_operand 0 "" "")))]
1100: ""
1101: "jbr %l0")
1102:
1103: (define_insn "beq"
1104: [(set (pc)
1105: (if_then_else (eq (cc0)
1106: (const_int 0))
1107: (label_ref (match_operand 0 "" ""))
1108: (pc)))]
1109: ""
1110: "jeql %l0")
1111:
1112: (define_insn "bne"
1113: [(set (pc)
1114: (if_then_else (ne (cc0)
1115: (const_int 0))
1116: (label_ref (match_operand 0 "" ""))
1117: (pc)))]
1118: ""
1119: "jneq %l0")
1120:
1121: (define_insn "bgt"
1122: [(set (pc)
1123: (if_then_else (gt (cc0)
1124: (const_int 0))
1125: (label_ref (match_operand 0 "" ""))
1126: (pc)))]
1127: ""
1128: "jgtr %l0")
1129:
1130: (define_insn "bgtu"
1131: [(set (pc)
1132: (if_then_else (gtu (cc0)
1133: (const_int 0))
1134: (label_ref (match_operand 0 "" ""))
1135: (pc)))]
1136: ""
1137: "jgtru %l0")
1138:
1139: (define_insn "blt"
1140: [(set (pc)
1141: (if_then_else (lt (cc0)
1142: (const_int 0))
1143: (label_ref (match_operand 0 "" ""))
1144: (pc)))]
1145: ""
1146: "jlss %l0")
1147:
1148: (define_insn "bltu"
1149: [(set (pc)
1150: (if_then_else (ltu (cc0)
1151: (const_int 0))
1152: (label_ref (match_operand 0 "" ""))
1153: (pc)))]
1154: ""
1155: "jlssu %l0")
1156:
1157: (define_insn "bge"
1158: [(set (pc)
1159: (if_then_else (ge (cc0)
1160: (const_int 0))
1161: (label_ref (match_operand 0 "" ""))
1162: (pc)))]
1163: ""
1164: "jgeq %l0")
1165:
1166: (define_insn "bgeu"
1167: [(set (pc)
1168: (if_then_else (geu (cc0)
1169: (const_int 0))
1170: (label_ref (match_operand 0 "" ""))
1171: (pc)))]
1172: ""
1173: "jgequ %l0")
1174:
1175: (define_insn "ble"
1176: [(set (pc)
1177: (if_then_else (le (cc0)
1178: (const_int 0))
1179: (label_ref (match_operand 0 "" ""))
1180: (pc)))]
1181: ""
1182: "jleq %l0")
1183:
1184: (define_insn "bleu"
1185: [(set (pc)
1186: (if_then_else (leu (cc0)
1187: (const_int 0))
1188: (label_ref (match_operand 0 "" ""))
1189: (pc)))]
1190: ""
1191: "jlequ %l0")
1192:
1193: (define_insn ""
1194: [(set (pc)
1195: (if_then_else (eq (cc0)
1196: (const_int 0))
1197: (pc)
1198: (label_ref (match_operand 0 "" ""))))]
1199: ""
1200: "jneq %l0")
1201:
1202: (define_insn ""
1203: [(set (pc)
1204: (if_then_else (ne (cc0)
1205: (const_int 0))
1206: (pc)
1207: (label_ref (match_operand 0 "" ""))))]
1208: ""
1209: "jeql %l0")
1210:
1211: (define_insn ""
1212: [(set (pc)
1213: (if_then_else (gt (cc0)
1214: (const_int 0))
1215: (pc)
1216: (label_ref (match_operand 0 "" ""))))]
1217: ""
1218: "jleq %l0")
1219:
1220: (define_insn ""
1221: [(set (pc)
1222: (if_then_else (gtu (cc0)
1223: (const_int 0))
1224: (pc)
1225: (label_ref (match_operand 0 "" ""))))]
1226: ""
1227: "jlequ %l0")
1228:
1229: (define_insn ""
1230: [(set (pc)
1231: (if_then_else (lt (cc0)
1232: (const_int 0))
1233: (pc)
1234: (label_ref (match_operand 0 "" ""))))]
1235: ""
1236: "jgeq %l0")
1237:
1238: (define_insn ""
1239: [(set (pc)
1240: (if_then_else (ltu (cc0)
1241: (const_int 0))
1242: (pc)
1243: (label_ref (match_operand 0 "" ""))))]
1244: ""
1245: "jgequ %l0")
1246:
1247: (define_insn ""
1248: [(set (pc)
1249: (if_then_else (ge (cc0)
1250: (const_int 0))
1251: (pc)
1252: (label_ref (match_operand 0 "" ""))))]
1253: ""
1254: "jlss %l0")
1255:
1256: (define_insn ""
1257: [(set (pc)
1258: (if_then_else (geu (cc0)
1259: (const_int 0))
1260: (pc)
1261: (label_ref (match_operand 0 "" ""))))]
1262: ""
1263: "jlssu %l0")
1264:
1265: (define_insn ""
1266: [(set (pc)
1267: (if_then_else (le (cc0)
1268: (const_int 0))
1269: (pc)
1270: (label_ref (match_operand 0 "" ""))))]
1271: ""
1272: "jgtr %l0")
1273:
1274: (define_insn ""
1275: [(set (pc)
1276: (if_then_else (leu (cc0)
1277: (const_int 0))
1278: (pc)
1279: (label_ref (match_operand 0 "" ""))))]
1280: ""
1281: "jgtru %l0")
1282:
1283: ;; Recognize jbs and jbc instructions.
1284:
1285: (define_insn ""
1286: [(set (pc)
1287: (if_then_else
1288: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1289: (const_int 1)
1290: (match_operand:SI 1 "general_operand" "g"))
1291: (const_int 0))
1292: (label_ref (match_operand 2 "" ""))
1293: (pc)))]
1294: ""
1295: "jbs %1,%0,%l2")
1296:
1297: (define_insn ""
1298: [(set (pc)
1299: (if_then_else
1300: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1301: (const_int 1)
1302: (match_operand:SI 1 "general_operand" "g"))
1303: (const_int 0))
1304: (label_ref (match_operand 2 "" ""))
1305: (pc)))]
1306: ""
1307: "jbc %1,%0,%l2")
1308:
1309: (define_insn ""
1310: [(set (pc)
1311: (if_then_else
1312: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1313: (const_int 1)
1314: (match_operand:SI 1 "general_operand" "g"))
1315: (const_int 0))
1316: (pc)
1317: (label_ref (match_operand 2 "" ""))))]
1318: ""
1319: "jbc %1,%0,%l2")
1320:
1321: (define_insn ""
1322: [(set (pc)
1323: (if_then_else
1324: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1325: (const_int 1)
1326: (match_operand:SI 1 "general_operand" "g"))
1327: (const_int 0))
1328: (pc)
1329: (label_ref (match_operand 2 "" ""))))]
1330: ""
1331: "jbs %1,%0,%l2")
1332:
1333: (define_insn ""
1334: [(set (pc)
1335: (if_then_else
1336: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1337: (const_int 1)
1338: (match_operand:SI 1 "general_operand" "g"))
1339: (const_int 0))
1340: (label_ref (match_operand 2 "" ""))
1341: (pc)))]
1342: ""
1343: "jbs %1,%0,%l2")
1344:
1345: (define_insn ""
1346: [(set (pc)
1347: (if_then_else
1348: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1349: (const_int 1)
1350: (match_operand:SI 1 "general_operand" "g"))
1351: (const_int 0))
1352: (label_ref (match_operand 2 "" ""))
1353: (pc)))]
1354: ""
1355: "jbc %1,%0,%l2")
1356:
1357: (define_insn ""
1358: [(set (pc)
1359: (if_then_else
1360: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1361: (const_int 1)
1362: (match_operand:SI 1 "general_operand" "g"))
1363: (const_int 0))
1364: (pc)
1365: (label_ref (match_operand 2 "" ""))))]
1366: ""
1367: "jbc %1,%0,%l2")
1368:
1369: (define_insn ""
1370: [(set (pc)
1371: (if_then_else
1372: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1373: (const_int 1)
1374: (match_operand:SI 1 "general_operand" "g"))
1375: (const_int 0))
1376: (pc)
1377: (label_ref (match_operand 2 "" ""))))]
1378: ""
1379: "jbs %1,%0,%l2")
1380:
1381: (define_insn ""
1382: [(set (pc)
1383: (if_then_else
1384: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1385: (const_int 1))
1386: (const_int 0))
1387: (label_ref (match_operand 1 "" ""))
1388: (pc)))]
1389: ""
1390: "jlbs %0,%l1")
1391:
1392: (define_insn ""
1393: [(set (pc)
1394: (if_then_else
1395: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1396: (const_int 1))
1397: (const_int 0))
1398: (label_ref (match_operand 1 "" ""))
1399: (pc)))]
1400: ""
1401: "jlbc %0,%l1")
1402:
1403: (define_insn ""
1404: [(set (pc)
1405: (if_then_else
1406: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1407: (const_int 1))
1408: (const_int 0))
1409: (pc)
1410: (label_ref (match_operand 1 "" ""))))]
1411: ""
1412: "jlbc %0,%l1")
1413:
1414: (define_insn ""
1415: [(set (pc)
1416: (if_then_else
1417: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1418: (const_int 1))
1419: (const_int 0))
1420: (pc)
1421: (label_ref (match_operand 1 "" ""))))]
1422: ""
1423: "jlbs %0,%l1")
1424:
1425: ;; These four entries allow a jlbc or jlbs to be made
1426: ;; by combination with a bic.
1427: (define_insn ""
1428: [(set (pc)
1429: (if_then_else
1430: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1431: (not:SI (const_int -2)))
1432: (const_int 0))
1433: (label_ref (match_operand 1 "" ""))
1434: (pc)))]
1435: ""
1436: "jlbs %0,%l1")
1437:
1438: (define_insn ""
1439: [(set (pc)
1440: (if_then_else
1441: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1442: (not:SI (const_int -2)))
1443: (const_int 0))
1444: (label_ref (match_operand 1 "" ""))
1445: (pc)))]
1446: ""
1447: "jlbc %0,%l1")
1448:
1449: (define_insn ""
1450: [(set (pc)
1451: (if_then_else
1452: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1453: (not:SI (const_int -2)))
1454: (const_int 0))
1455: (pc)
1456: (label_ref (match_operand 1 "" ""))))]
1457: ""
1458: "jlbc %0,%l1")
1459:
1460: (define_insn ""
1461: [(set (pc)
1462: (if_then_else
1463: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1464: (not:SI (const_int -2)))
1465: (const_int 0))
1466: (pc)
1467: (label_ref (match_operand 1 "" ""))))]
1468: ""
1469: "jlbs %0,%l1")
1470:
1471: ;; Subtract-and-jump and Add-and-jump insns.
1472: ;; These are not used when output is for the Unix assembler
1473: ;; because it does not know how to modify them to reach far.
1474:
1475: ;; Normal sob insns.
1476:
1477: (define_insn ""
1478: [(set (pc)
1479: (if_then_else
1480: (gt (minus:SI (match_operand:SI 0 "general_operand" "+g")
1481: (const_int 1))
1482: (const_int 0))
1483: (label_ref (match_operand 1 "" ""))
1484: (pc)))
1485: (set (match_dup 0)
1486: (minus:SI (match_dup 0)
1487: (const_int 1)))]
1488: "!TARGET_UNIX_ASM"
1489: "jsobgtr %0,%l1")
1490:
1491: (define_insn ""
1492: [(set (pc)
1493: (if_then_else
1494: (ge (minus:SI (match_operand:SI 0 "general_operand" "+g")
1495: (const_int 1))
1496: (const_int 0))
1497: (label_ref (match_operand 1 "" ""))
1498: (pc)))
1499: (set (match_dup 0)
1500: (minus:SI (match_dup 0)
1501: (const_int 1)))]
1502: "!TARGET_UNIX_ASM"
1503: "jsobgeq %0,%l1")
1504:
1505: ;; Reversed sob insns.
1506:
1507: (define_insn ""
1508: [(set (pc)
1509: (if_then_else
1510: (le (minus:SI (match_operand:SI 0 "general_operand" "+g")
1511: (const_int 1))
1512: (const_int 0))
1513: (pc)
1514: (label_ref (match_operand 1 "" ""))))
1515: (set (match_dup 0)
1516: (minus:SI (match_dup 0)
1517: (const_int 1)))]
1518: "!TARGET_UNIX_ASM"
1519: "jsobgtr %0,%l1")
1520:
1521: (define_insn ""
1522: [(set (pc)
1523: (if_then_else
1524: (lt (minus:SI (match_operand:SI 0 "general_operand" "+g")
1525: (const_int 1))
1526: (const_int 0))
1527: (pc)
1528: (label_ref (match_operand 1 "" ""))))
1529: (set (match_dup 0)
1530: (minus:SI (match_dup 0)
1531: (const_int 1)))]
1532: "!TARGET_UNIX_ASM"
1533: "jsobgeq %0,%l1")
1534:
1535: ;; Normal aob insns.
1536: (define_insn ""
1537: [(set (pc)
1538: (if_then_else
1539: (lt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1540: (const_int 1))
1541: (match_operand:SI 1 "general_operand" "g"))
1542: (const_int 0))
1543: (label_ref (match_operand 2 "" ""))
1544: (pc)))
1545: (set (match_dup 0)
1546: (plus:SI (match_dup 0)
1547: (const_int 1)))]
1548: "!TARGET_UNIX_ASM"
1549: "jaoblss %1,%0,%l2")
1550:
1551: (define_insn ""
1552: [(set (pc)
1553: (if_then_else
1554: (le (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1555: (const_int 1))
1556: (match_operand:SI 1 "general_operand" "g"))
1557: (const_int 0))
1558: (label_ref (match_operand 2 "" ""))
1559: (pc)))
1560: (set (match_dup 0)
1561: (plus:SI (match_dup 0)
1562: (const_int 1)))]
1563: "!TARGET_UNIX_ASM"
1564: "jaobleq %1,%0,%l2")
1565:
1566: ;; Reverse aob insns.
1567: (define_insn ""
1568: [(set (pc)
1569: (if_then_else
1570: (ge (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1571: (const_int 1))
1572: (match_operand:SI 1 "general_operand" "g"))
1573: (const_int 0))
1574: (pc)
1575: (label_ref (match_operand 2 "" ""))))
1576: (set (match_dup 0)
1577: (plus:SI (match_dup 0)
1578: (const_int 1)))]
1579: "!TARGET_UNIX_ASM"
1580: "jaoblss %1,%0,%l2")
1581:
1582: (define_insn ""
1583: [(set (pc)
1584: (if_then_else
1585: (gt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1586: (const_int 1))
1587: (match_operand:SI 1 "general_operand" "g"))
1588: (const_int 0))
1589: (pc)
1590: (label_ref (match_operand 2 "" ""))))
1591: (set (match_dup 0)
1592: (plus:SI (match_dup 0)
1593: (const_int 1)))]
1594: "!TARGET_UNIX_ASM"
1595: "jaobleq %1,%0,%l2")
1596:
1597: (define_insn "call"
1598: [(call (match_operand:QI 0 "general_operand" "g")
1599: (match_operand:QI 1 "general_operand" "g"))]
1600: ""
1601: "calls %1,%0")
1602:
1603: (define_insn "return"
1604: [(return)]
1605: ""
1606: "ret")
1607:
1608: (define_insn "casesi"
1609: [(set (pc)
1610: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
1611: (match_operand:SI 1 "general_operand" "g"))
1612: (match_operand:SI 2 "general_operand" "g"))
1613: (plus:SI (label_ref:SI (match_operand 3 "" ""))
1614: (sign_extend:SI
1615: (mem:HI (plus:SI (pc)
1616: (minus:SI (match_dup 0)
1617: (match_dup 1))))))
1618: (pc)))]
1619: ""
1620: "casel %0,%1,%2")
1621:
1622: ;; This arises from the preceding by simplification if operand 1 is zero.
1623: (define_insn ""
1624: [(set (pc)
1625: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1626: (match_operand:SI 1 "general_operand" "g"))
1627: (plus:SI (label_ref:SI (match_operand 3 "" ""))
1628: (sign_extend:SI
1629: (mem:HI (plus:SI (pc)
1630: (match_dup 0)))))
1631: (pc)))]
1632: ""
1633: "casel %0,$0,%1")
1634:
1635: ;;- Local variables:
1636: ;;- mode:emacs-lisp
1637: ;;- comment-start: ";;- "
1638: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
1639: ;;- eval: (modify-syntax-entry ?[ "(]")
1640: ;;- eval: (modify-syntax-entry ?] ")[")
1641: ;;- eval: (modify-syntax-entry ?{ "(}")
1642: ;;- eval: (modify-syntax-entry ?} "){")
1643: ;;- End:
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