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1.1.1.4 root 1:
1.1 root 2: ;;- Machine description for GNU compiler
3: ;;- Vax Version
4: ;; Copyright (C) 1987 Free Software Foundation, Inc.
5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is distributed in the hope that it will be useful,
9: ;; but WITHOUT ANY WARRANTY. No author or distributor
10: ;; accepts responsibility to anyone for the consequences of using it
11: ;; or for whether it serves any particular purpose or works at all,
12: ;; unless he says so in writing. Refer to the GNU CC General Public
13: ;; License for full details.
14:
15: ;; Everyone is granted permission to copy, modify and redistribute
16: ;; GNU CC, but only under the conditions described in the
17: ;; GNU CC General Public License. A copy of this license is
18: ;; supposed to have been given to you along with GNU CC so you
19: ;; can know your rights and responsibilities. It should be in a
20: ;; file named COPYING. Among other things, the copyright notice
21: ;; and this notice must be preserved on all copies.
22:
23:
24: ;;- Instruction patterns. When multiple patterns apply,
25: ;;- the first one in the file is chosen.
26: ;;-
27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28: ;;-
29: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
30: ;;- updates for most instructions.
31:
1.1.1.2 root 32: ; tstsi is first test insn so that it is the one to match
33: ; a constant argument.
1.1 root 34:
35: (define_insn "tstsi"
36: [(set (cc0)
37: (match_operand:SI 0 "general_operand" "g"))]
38: ""
39: "tstl %0")
40:
41: (define_insn "tsthi"
42: [(set (cc0)
43: (match_operand:HI 0 "general_operand" "g"))]
44: ""
45: "tstw %0")
46:
47: (define_insn "tstqi"
48: [(set (cc0)
49: (match_operand:QI 0 "general_operand" "g"))]
50: ""
51: "tstb %0")
52:
1.1.1.2 root 53: (define_insn "tstdf"
1.1 root 54: [(set (cc0)
1.1.1.2 root 55: (match_operand:DF 0 "general_operand" "gF"))]
1.1 root 56: ""
1.1.1.3 root 57: "tst%# %0")
1.1 root 58:
1.1.1.2 root 59: (define_insn "tstsf"
1.1 root 60: [(set (cc0)
1.1.1.2 root 61: (match_operand:SF 0 "general_operand" "gF"))]
1.1 root 62: ""
1.1.1.2 root 63: "tstf %0")
1.1 root 64:
65: (define_insn "cmpsi"
66: [(set (cc0)
67: (minus (match_operand:SI 0 "general_operand" "g")
68: (match_operand:SI 1 "general_operand" "g")))]
69: ""
70: "cmpl %0,%1")
71:
72: (define_insn "cmphi"
73: [(set (cc0)
74: (minus (match_operand:HI 0 "general_operand" "g")
75: (match_operand:HI 1 "general_operand" "g")))]
76: ""
77: "cmpw %0,%1")
78:
79: (define_insn "cmpqi"
80: [(set (cc0)
81: (minus (match_operand:QI 0 "general_operand" "g")
82: (match_operand:QI 1 "general_operand" "g")))]
83: ""
84: "cmpb %0,%1")
85:
1.1.1.2 root 86: (define_insn "cmpdf"
87: [(set (cc0)
88: (minus (match_operand:DF 0 "general_operand" "gF")
89: (match_operand:DF 1 "general_operand" "gF")))]
90: ""
1.1.1.3 root 91: "cmp%# %0,%1")
1.1.1.2 root 92:
93: (define_insn "cmpsf"
94: [(set (cc0)
95: (minus (match_operand:SF 0 "general_operand" "gF")
96: (match_operand:SF 1 "general_operand" "gF")))]
97: ""
98: "cmpf %0,%1")
99:
1.1 root 100: (define_insn ""
101: [(set (cc0)
102: (and:SI (match_operand:SI 0 "general_operand" "g")
103: (match_operand:SI 1 "general_operand" "g")))]
104: ""
105: "bitl %0,%1")
106:
107: (define_insn ""
108: [(set (cc0)
109: (and:HI (match_operand:HI 0 "general_operand" "g")
110: (match_operand:HI 1 "general_operand" "g")))]
111: ""
112: "bitw %0,%1")
113:
114: (define_insn ""
115: [(set (cc0)
116: (and:QI (match_operand:QI 0 "general_operand" "g")
117: (match_operand:QI 1 "general_operand" "g")))]
118: ""
119: "bitb %0,%1")
120:
121: (define_insn "movdf"
122: [(set (match_operand:DF 0 "general_operand" "=g")
123: (match_operand:DF 1 "general_operand" "gF"))]
124: ""
125: "*
126: {
127: if (operands[1] == dconst0_rtx)
1.1.1.3 root 128: return \"clr%# %0\";
129: return \"mov%# %1,%0\";
1.1 root 130: }")
131:
132: (define_insn "movsf"
133: [(set (match_operand:SF 0 "general_operand" "=g")
134: (match_operand:SF 1 "general_operand" "gF"))]
135: ""
136: "*
137: {
138: if (operands[1] == fconst0_rtx)
139: return \"clrf %0\";
140: return \"movf %1,%0\";
141: }")
142:
1.1.1.2 root 143: ;; Some vaxes don't support this instruction.
144: ;;(define_insn "movti"
145: ;; [(set (match_operand:TI 0 "general_operand" "=g")
146: ;; (match_operand:TI 1 "general_operand" "g"))]
147: ;; ""
148: ;; "movh %1,%0")
1.1 root 149:
150: (define_insn "movdi"
151: [(set (match_operand:DI 0 "general_operand" "=g")
152: (match_operand:DI 1 "general_operand" "g"))]
153: ""
1.1.1.2 root 154: "movq %1,%0")
1.1 root 155:
156: (define_insn "movsi"
157: [(set (match_operand:SI 0 "general_operand" "=g")
158: (match_operand:SI 1 "general_operand" "g"))]
159: ""
160: "*
1.1.1.8 root 161: {
162: rtx link;
163: if (operands[1] == const1_rtx
164: && (link = find_reg_note (insn, REG_WAS_0, 0))
1.1.1.2 root 165: /* Make sure the insn that stored the 0 is still present. */
1.1.1.8 root 166: && ! XEXP (link, 0)->volatil
167: && GET_CODE (XEXP (link, 0)) != NOTE
1.1.1.5 root 168: /* Make sure cross jumping didn't happen here. */
1.1.1.8 root 169: && no_labels_between_p (XEXP (link, 0), insn))
1.1.1.2 root 170: /* Fastest way to change a 0 to a 1. */
1.1 root 171: return \"incl %0\";
172: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
173: {
174: if (push_operand (operands[0], SImode))
175: return \"pushab %a1\";
176: return \"movab %a1,%0\";
177: }
1.1.1.8 root 178: /* this is slower than a movl, except when pushing an operand */
1.1 root 179: if (operands[1] == const0_rtx)
180: return \"clrl %0\";
181: if (GET_CODE (operands[1]) == CONST_INT
182: && (unsigned) INTVAL (operands[1]) >= 64)
183: {
184: int i = INTVAL (operands[1]);
1.1.1.8 root 185: if ((unsigned)(~i) < 64)
1.1 root 186: {
1.1.1.8 root 187: operands[1] = gen_rtx (CONST_INT, VOIDmode, ~i);
188: return \"mcoml %1,%0\";
1.1 root 189: }
1.1.1.8 root 190: if ((unsigned)i < 127)
191: {
192: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
193: operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63);
194: return \"addl3 %2,%1,%0\";
195: }
196: /* trading speed for space */
1.1 root 197: if ((unsigned)i < 0x100)
198: return \"movzbl %1,%0\";
199: if (i >= -0x80 && i < 0)
200: return \"cvtbl %1,%0\";
201: if ((unsigned)i < 0x10000)
202: return \"movzwl %1,%0\";
203: if (i >= -0x8000 && i < 0)
204: return \"cvtwl %1,%0\";
205: }
206: if (push_operand (operands[0], SImode))
207: return \"pushl %1\";
208: return \"movl %1,%0\";
209: }")
210:
211: (define_insn "movhi"
212: [(set (match_operand:HI 0 "general_operand" "=g")
213: (match_operand:HI 1 "general_operand" "g"))]
214: ""
215: "*
216: {
1.1.1.8 root 217: rtx link;
218: if (operands[1] == const1_rtx
219: && (link = find_reg_note (insn, REG_WAS_0, 0))
220: /* Make sure the insn that stored the 0 is still present. */
221: && ! XEXP (link, 0)->volatil
222: && GET_CODE (XEXP (link, 0)) != NOTE
223: /* Make sure cross jumping didn't happen here. */
224: && no_labels_between_p (XEXP (link, 0), insn))
225: /* Fastest way to change a 0 to a 1. */
1.1 root 226: return \"incw %0\";
227: if (operands[1] == const0_rtx)
228: return \"clrw %0\";
229: if (GET_CODE (operands[1]) == CONST_INT
230: && (unsigned) INTVAL (operands[1]) >= 64)
231: {
232: int i = INTVAL (operands[1]);
1.1.1.9 root 233: if ((unsigned)((~i) & 0xffff) < 64)
1.1 root 234: {
1.1.1.9 root 235: operands[1] = gen_rtx (CONST_INT, VOIDmode, (~i) & 0xffff);
1.1.1.8 root 236: return \"mcomw %1,%0\";
1.1 root 237: }
1.1.1.8 root 238: if ((unsigned)(i & 0xffff) < 127)
239: {
240: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
1.1.1.9 root 241: operands[2] = gen_rtx (CONST_INT, VOIDmode, (i-63) & 0xffff);
1.1.1.8 root 242: return \"addw3 %2,%1,%0\";
243: }
244: /* this is a lot slower, and only saves 1 measly byte! */
245: /* if ((unsigned)i < 0x100)
246: return \"movzbw %1,%0\"; */
247: /* if (i >= -0x80 && i < 0)
248: return \"cvtbw %1,%0\"; */
1.1 root 249: }
250: return \"movw %1,%0\";
251: }")
252:
253: (define_insn "movqi"
254: [(set (match_operand:QI 0 "general_operand" "=g")
255: (match_operand:QI 1 "general_operand" "g"))]
256: ""
257: "*
258: {
259: if (operands[1] == const0_rtx)
260: return \"clrb %0\";
1.1.1.8 root 261: if (GET_CODE (operands[1]) == CONST_INT
262: && (unsigned) INTVAL (operands[1]) >= 64)
263: {
264: int i = INTVAL (operands[1]);
1.1.1.10! root 265: if ((unsigned)((~i) & 0xff) < 64)
1.1.1.8 root 266: {
1.1.1.10! root 267: operands[1] = gen_rtx (CONST_INT, VOIDmode, (~i) & 0xff);
1.1.1.8 root 268: return \"mcomb %1,%0\";
269: }
270: #if 0
271: /* ASCII alphabetics */
272: if (((unsigned) INTVAL (operands[1]) &0xff) < 127)
273: {
274: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
275: operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63);
276: return \"addb3 %2,%1,%0\";
277: }
278: #endif
279: }
1.1 root 280: return \"movb %1,%0\";
281: }")
282:
283: ;; The definition of this insn does not really explain what it does,
284: ;; but it should suffice
285: ;; that anything generated as this insn will be recognized as one
286: ;; and that it won't successfully combine with anything.
287: (define_insn "movstrhi"
288: [(set (match_operand:BLK 0 "general_operand" "=g")
289: (match_operand:BLK 1 "general_operand" "g"))
290: (use (match_operand:HI 2 "general_operand" "g"))
1.1.1.2 root 291: (clobber (reg:SI 0))
292: (clobber (reg:SI 1))
293: (clobber (reg:SI 2))
294: (clobber (reg:SI 3))
295: (clobber (reg:SI 4))
296: (clobber (reg:SI 5))]
1.1 root 297: ""
298: "movc3 %2,%1,%0")
299:
300: ;;- load or push effective address
301: ;; These come after the move patterns
302: ;; because we don't want pushl $1 turned into pushad 1.
303:
304: (define_insn ""
305: [(set (match_operand:SI 0 "general_operand" "=g")
306: (match_operand:QI 1 "address_operand" "p"))]
307: ""
308: "*
309: {
310: if (push_operand (operands[0], SImode))
311: return \"pushab %a1\";
312: return \"movab %a1,%0\";
313: }")
314:
315: (define_insn ""
316: [(set (match_operand:SI 0 "general_operand" "=g")
317: (match_operand:HI 1 "address_operand" "p"))]
318: ""
319: "*
320: {
321: if (push_operand (operands[0], SImode))
322: return \"pushaw %a1\";
323: return \"movaw %a1,%0\";
324: }")
325:
326: (define_insn ""
327: [(set (match_operand:SI 0 "general_operand" "=g")
328: (match_operand:SI 1 "address_operand" "p"))]
329: ""
330: "*
331: {
332: if (push_operand (operands[0], SImode))
333: return \"pushal %a1\";
334: return \"moval %a1,%0\";
335: }")
336:
337: (define_insn ""
338: [(set (match_operand:SI 0 "general_operand" "=g")
339: (match_operand:SF 1 "address_operand" "p"))]
340: ""
341: "*
342: {
343: if (push_operand (operands[0], SImode))
344: return \"pushaf %a1\";
345: return \"movaf %a1,%0\";
346: }")
347:
348: (define_insn ""
349: [(set (match_operand:SI 0 "general_operand" "=g")
350: (match_operand:DF 1 "address_operand" "p"))]
351: ""
352: "*
353: {
354: if (push_operand (operands[0], SImode))
355: return \"pushad %a1\";
356: return \"movad %a1,%0\";
357: }")
358:
1.1.1.2 root 359: ;; Extension and truncation insns.
360: ;; Those for integer source operand
361: ;; are ordered widest source type first.
1.1 root 362:
1.1.1.2 root 363: (define_insn "truncsiqi2"
364: [(set (match_operand:QI 0 "general_operand" "=g")
365: (truncate:QI (match_operand:SI 1 "general_operand" "g")))]
1.1 root 366: ""
1.1.1.2 root 367: "cvtlb %1,%0")
1.1 root 368:
1.1.1.2 root 369: (define_insn "truncsihi2"
370: [(set (match_operand:HI 0 "general_operand" "=g")
371: (truncate:HI (match_operand:SI 1 "general_operand" "g")))]
1.1 root 372: ""
1.1.1.2 root 373: "cvtlw %1,%0")
1.1 root 374:
375: (define_insn "trunchiqi2"
376: [(set (match_operand:QI 0 "general_operand" "=g")
377: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
378: ""
379: "cvtwb %1,%0")
380:
381: (define_insn "extendhisi2"
382: [(set (match_operand:SI 0 "general_operand" "=g")
383: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
384: ""
385: "cvtwl %1,%0")
386:
1.1.1.2 root 387: (define_insn "extendqihi2"
388: [(set (match_operand:HI 0 "general_operand" "=g")
389: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1.1 root 390: ""
1.1.1.2 root 391: "cvtbw %1,%0")
1.1 root 392:
1.1.1.2 root 393: (define_insn "extendqisi2"
394: [(set (match_operand:SI 0 "general_operand" "=g")
395: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
396: ""
397: "cvtbl %1,%0")
398:
399: (define_insn "extendsfdf2"
1.1 root 400: [(set (match_operand:DF 0 "general_operand" "=g")
1.1.1.2 root 401: (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
1.1 root 402: ""
1.1.1.3 root 403: "cvtf%# %1,%0")
1.1 root 404:
1.1.1.2 root 405: (define_insn "truncdfsf2"
406: [(set (match_operand:SF 0 "general_operand" "=g")
407: (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
1.1 root 408: ""
1.1.1.3 root 409: "cvt%#f %1,%0")
1.1 root 410:
1.1.1.2 root 411: (define_insn "zero_extendhisi2"
412: [(set (match_operand:SI 0 "general_operand" "=g")
413: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
414: ""
415: "movzwl %1,%0")
416:
417: (define_insn "zero_extendqihi2"
1.1 root 418: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 419: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1.1 root 420: ""
1.1.1.2 root 421: "movzbw %1,%0")
422:
423: (define_insn "zero_extendqisi2"
424: [(set (match_operand:SI 0 "general_operand" "=g")
425: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
426: ""
427: "movzbl %1,%0")
428:
429: ;; Fix-to-float conversion insns.
430: ;; Note that the ones that start with SImode come first.
431: ;; That is so that an operand that is a CONST_INT
432: ;; (and therefore lacks a specific machine mode).
433: ;; will be recognized as SImode (which is always valid)
434: ;; rather than as QImode or HImode.
1.1 root 435:
436: (define_insn "floatsisf2"
437: [(set (match_operand:SF 0 "general_operand" "=g")
438: (float:SF (match_operand:SI 1 "general_operand" "g")))]
439: ""
440: "cvtlf %1,%0")
441:
442: (define_insn "floatsidf2"
443: [(set (match_operand:DF 0 "general_operand" "=g")
444: (float:DF (match_operand:SI 1 "general_operand" "g")))]
445: ""
1.1.1.3 root 446: "cvtl%# %1,%0")
1.1 root 447:
1.1.1.2 root 448: (define_insn "floathisf2"
449: [(set (match_operand:SF 0 "general_operand" "=g")
450: (float:SF (match_operand:HI 1 "general_operand" "g")))]
1.1 root 451: ""
1.1.1.2 root 452: "cvtwf %1,%0")
1.1 root 453:
1.1.1.2 root 454: (define_insn "floathidf2"
455: [(set (match_operand:DF 0 "general_operand" "=g")
456: (float:DF (match_operand:HI 1 "general_operand" "g")))]
1.1 root 457: ""
1.1.1.3 root 458: "cvtw%# %1,%0")
1.1 root 459:
1.1.1.2 root 460: (define_insn "floatqisf2"
461: [(set (match_operand:SF 0 "general_operand" "=g")
462: (float:SF (match_operand:QI 1 "general_operand" "g")))]
1.1 root 463: ""
1.1.1.2 root 464: "cvtbf %1,%0")
1.1 root 465:
1.1.1.2 root 466: (define_insn "floatqidf2"
1.1 root 467: [(set (match_operand:DF 0 "general_operand" "=g")
1.1.1.2 root 468: (float:DF (match_operand:QI 1 "general_operand" "g")))]
1.1 root 469: ""
1.1.1.3 root 470: "cvtb%# %1,%0")
1.1.1.2 root 471:
472: ;; Float-to-fix conversion insns.
1.1 root 473:
1.1.1.2 root 474: (define_insn "fix_truncsfqi2"
1.1 root 475: [(set (match_operand:QI 0 "general_operand" "=g")
1.1.1.2 root 476: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 477: ""
1.1.1.2 root 478: "cvtfb %1,%0")
1.1 root 479:
1.1.1.2 root 480: (define_insn "fix_truncsfhi2"
1.1 root 481: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 482: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 483: ""
1.1.1.2 root 484: "cvtfw %1,%0")
1.1 root 485:
1.1.1.2 root 486: (define_insn "fix_truncsfsi2"
1.1 root 487: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 488: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 489: ""
1.1.1.2 root 490: "cvtfl %1,%0")
1.1 root 491:
1.1.1.2 root 492: (define_insn "fix_truncdfqi2"
493: [(set (match_operand:QI 0 "general_operand" "=g")
494: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 495: ""
1.1.1.8 root 496: "cvt%#b %1,%0")
1.1 root 497:
1.1.1.2 root 498: (define_insn "fix_truncdfhi2"
1.1 root 499: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 500: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 501: ""
1.1.1.3 root 502: "cvt%#w %1,%0")
1.1 root 503:
1.1.1.2 root 504: (define_insn "fix_truncdfsi2"
1.1 root 505: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 506: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 507: ""
1.1.1.3 root 508: "cvt%#l %1,%0")
1.1 root 509:
510: ;;- All kinds of add instructions.
511:
512: (define_insn "adddf3"
513: [(set (match_operand:DF 0 "general_operand" "=g")
514: (plus:DF (match_operand:DF 1 "general_operand" "gF")
515: (match_operand:DF 2 "general_operand" "gF")))]
516: ""
517: "*
518: {
519: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 520: return \"add%#2 %2,%0\";
1.1 root 521: if (rtx_equal_p (operands[0], operands[2]))
1.1.1.3 root 522: return \"add%#2 %1,%0\";
523: return \"add%#3 %1,%2,%0\";
1.1 root 524: }")
525:
526: (define_insn "addsf3"
527: [(set (match_operand:SF 0 "general_operand" "=g")
528: (plus:SF (match_operand:SF 1 "general_operand" "gF")
529: (match_operand:SF 2 "general_operand" "gF")))]
530: ""
531: "*
532: {
533: if (rtx_equal_p (operands[0], operands[1]))
534: return \"addf2 %2,%0\";
535: if (rtx_equal_p (operands[0], operands[2]))
536: return \"addf2 %1,%0\";
537: return \"addf3 %1,%2,%0\";
538: }")
539:
540: (define_insn "addsi3"
541: [(set (match_operand:SI 0 "general_operand" "=g")
542: (plus:SI (match_operand:SI 1 "general_operand" "g")
543: (match_operand:SI 2 "general_operand" "g")))]
544: ""
545: "*
546: {
547: if (rtx_equal_p (operands[0], operands[1]))
548: {
549: if (operands[2] == const1_rtx)
550: return \"incl %0\";
1.1.1.2 root 551: if (GET_CODE (operands[2]) == CONST_INT
552: && INTVAL (operands[2]) == -1)
1.1 root 553: return \"decl %0\";
554: if (GET_CODE (operands[2]) == CONST_INT
555: && (unsigned) (- INTVAL (operands[2])) < 64)
556: return \"subl2 $%n2,%0\";
1.1.1.8 root 557: if (GET_CODE (operands[2]) == CONST_INT
558: && (unsigned) INTVAL (operands[2]) >= 64
559: && GET_CODE (operands[1]) == REG)
560: return \"movab %c2(%1),%0\";
1.1 root 561: return \"addl2 %2,%0\";
562: }
563: if (rtx_equal_p (operands[0], operands[2]))
564: return \"addl2 %1,%0\";
565: if (GET_CODE (operands[2]) == CONST_INT
1.1.1.8 root 566: && (unsigned) (- INTVAL (operands[2])) < 64)
567: return \"subl3 $%n2,%1,%0\";
568: if (GET_CODE (operands[2]) == CONST_INT
569: && (unsigned) INTVAL (operands[2]) >= 64
1.1 root 570: && GET_CODE (operands[1]) == REG)
571: {
572: if (push_operand (operands[0], SImode))
1.1.1.8 root 573: return \"pushab %c2(%1)\";
1.1 root 574: return \"movab %c2(%1),%0\";
575: }
576: return \"addl3 %1,%2,%0\";
577: }")
578:
579: (define_insn "addhi3"
580: [(set (match_operand:HI 0 "general_operand" "=g")
581: (plus:HI (match_operand:HI 1 "general_operand" "g")
582: (match_operand:HI 2 "general_operand" "g")))]
583: ""
584: "*
585: {
586: if (rtx_equal_p (operands[0], operands[1]))
587: {
588: if (operands[2] == const1_rtx)
589: return \"incw %0\";
590: if (GET_CODE (operands[1]) == CONST_INT
591: && INTVAL (operands[1]) == -1)
592: return \"decw %0\";
593: if (GET_CODE (operands[2]) == CONST_INT
594: && (unsigned) (- INTVAL (operands[2])) < 64)
595: return \"subw2 $%n2,%0\";
596: return \"addw2 %2,%0\";
597: }
598: if (rtx_equal_p (operands[0], operands[2]))
599: return \"addw2 %1,%0\";
600: if (GET_CODE (operands[2]) == CONST_INT
601: && (unsigned) (- INTVAL (operands[2])) < 64)
602: return \"subw3 $%n2,%1,%0\";
603: return \"addw3 %1,%2,%0\";
604: }")
605:
606: (define_insn "addqi3"
607: [(set (match_operand:QI 0 "general_operand" "=g")
608: (plus:QI (match_operand:QI 1 "general_operand" "g")
609: (match_operand:QI 2 "general_operand" "g")))]
610: ""
611: "*
612: {
613: if (rtx_equal_p (operands[0], operands[1]))
614: {
615: if (operands[2] == const1_rtx)
616: return \"incb %0\";
617: if (GET_CODE (operands[1]) == CONST_INT
618: && INTVAL (operands[1]) == -1)
619: return \"decb %0\";
620: if (GET_CODE (operands[2]) == CONST_INT
621: && (unsigned) (- INTVAL (operands[2])) < 64)
622: return \"subb2 $%n2,%0\";
623: return \"addb2 %2,%0\";
624: }
625: if (rtx_equal_p (operands[0], operands[2]))
626: return \"addb2 %1,%0\";
627: if (GET_CODE (operands[2]) == CONST_INT
628: && (unsigned) (- INTVAL (operands[2])) < 64)
629: return \"subb3 $%n2,%1,%0\";
630: return \"addb3 %1,%2,%0\";
631: }")
632:
633: ;;- All kinds of subtract instructions.
634:
635: (define_insn "subdf3"
636: [(set (match_operand:DF 0 "general_operand" "=g")
637: (minus:DF (match_operand:DF 1 "general_operand" "gF")
638: (match_operand:DF 2 "general_operand" "gF")))]
639: ""
640: "*
641: {
642: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 643: return \"sub%#2 %2,%0\";
644: return \"sub%#3 %2,%1,%0\";
1.1 root 645: }")
646:
647: (define_insn "subsf3"
648: [(set (match_operand:SF 0 "general_operand" "=g")
649: (minus:SF (match_operand:SF 1 "general_operand" "gF")
650: (match_operand:SF 2 "general_operand" "gF")))]
651: ""
652: "*
653: {
654: if (rtx_equal_p (operands[0], operands[1]))
655: return \"subf2 %2,%0\";
656: return \"subf3 %2,%1,%0\";
657: }")
658:
659: (define_insn "subsi3"
660: [(set (match_operand:SI 0 "general_operand" "=g")
661: (minus:SI (match_operand:SI 1 "general_operand" "g")
662: (match_operand:SI 2 "general_operand" "g")))]
663: ""
664: "*
665: {
666: if (rtx_equal_p (operands[0], operands[1]))
667: {
668: if (operands[2] == const1_rtx)
669: return \"decl %0\";
670: return \"subl2 %2,%0\";
671: }
672: return \"subl3 %2,%1,%0\";
673: }")
674:
675: (define_insn "subhi3"
676: [(set (match_operand:HI 0 "general_operand" "=g")
677: (minus:HI (match_operand:HI 1 "general_operand" "g")
678: (match_operand:HI 2 "general_operand" "g")))]
679: ""
680: "*
681: {
682: if (rtx_equal_p (operands[0], operands[1]))
683: {
684: if (operands[2] == const1_rtx)
685: return \"decw %0\";
686: return \"subw2 %2,%0\";
687: }
688: return \"subw3 %2,%1,%0\";
689: }")
690:
691: (define_insn "subqi3"
692: [(set (match_operand:QI 0 "general_operand" "=g")
693: (minus:QI (match_operand:QI 1 "general_operand" "g")
694: (match_operand:QI 2 "general_operand" "g")))]
695: ""
696: "*
697: {
698: if (rtx_equal_p (operands[0], operands[1]))
699: {
700: if (operands[2] == const1_rtx)
701: return \"decb %0\";
702: return \"subb2 %2,%0\";
703: }
704: return \"subb3 %2,%1,%0\";
705: }")
706:
707: ;;- Multiply instructions.
708:
709: (define_insn "muldf3"
710: [(set (match_operand:DF 0 "general_operand" "=g")
711: (mult:DF (match_operand:DF 1 "general_operand" "gF")
712: (match_operand:DF 2 "general_operand" "gF")))]
713: ""
714: "*
715: {
716: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 717: return \"mul%#2 %2,%0\";
1.1 root 718: if (rtx_equal_p (operands[0], operands[2]))
1.1.1.3 root 719: return \"mul%#2 %1,%0\";
720: return \"mul%#3 %1,%2,%0\";
1.1 root 721: }")
722:
723: (define_insn "mulsf3"
724: [(set (match_operand:SF 0 "general_operand" "=g")
725: (mult:SF (match_operand:SF 1 "general_operand" "gF")
726: (match_operand:SF 2 "general_operand" "gF")))]
727: ""
728: "*
729: {
730: if (rtx_equal_p (operands[0], operands[1]))
731: return \"mulf2 %2,%0\";
732: if (rtx_equal_p (operands[0], operands[2]))
733: return \"mulf2 %1,%0\";
734: return \"mulf3 %1,%2,%0\";
735: }")
736:
737: (define_insn "mulsi3"
738: [(set (match_operand:SI 0 "general_operand" "=g")
739: (mult:SI (match_operand:SI 1 "general_operand" "g")
740: (match_operand:SI 2 "general_operand" "g")))]
741: ""
742: "*
743: {
744: if (rtx_equal_p (operands[0], operands[1]))
745: return \"mull2 %2,%0\";
746: if (rtx_equal_p (operands[0], operands[2]))
747: return \"mull2 %1,%0\";
748: return \"mull3 %1,%2,%0\";
749: }")
750:
751: (define_insn "mulhi3"
752: [(set (match_operand:HI 0 "general_operand" "=g")
753: (mult:HI (match_operand:HI 1 "general_operand" "g")
754: (match_operand:HI 2 "general_operand" "g")))]
755: ""
756: "*
757: {
758: if (rtx_equal_p (operands[0], operands[1]))
759: return \"mulw2 %2,%0\";
760: if (rtx_equal_p (operands[0], operands[2]))
761: return \"mulw2 %1,%0\";
762: return \"mulw3 %1,%2,%0\";
763: }")
764:
765: (define_insn "mulqi3"
766: [(set (match_operand:QI 0 "general_operand" "=g")
767: (mult:QI (match_operand:QI 1 "general_operand" "g")
768: (match_operand:QI 2 "general_operand" "g")))]
769: ""
770: "*
771: {
772: if (rtx_equal_p (operands[0], operands[1]))
773: return \"mulb2 %2,%0\";
774: if (rtx_equal_p (operands[0], operands[2]))
775: return \"mulb2 %1,%0\";
776: return \"mulb3 %1,%2,%0\";
777: }")
778:
779: ;;- Divide instructions.
780:
781: (define_insn "divdf3"
782: [(set (match_operand:DF 0 "general_operand" "=g")
783: (div:DF (match_operand:DF 1 "general_operand" "gF")
784: (match_operand:DF 2 "general_operand" "gF")))]
785: ""
786: "*
787: {
788: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 789: return \"div%#2 %2,%0\";
790: return \"div%#3 %2,%1,%0\";
1.1 root 791: }")
792:
793: (define_insn "divsf3"
794: [(set (match_operand:SF 0 "general_operand" "=g")
795: (div:SF (match_operand:SF 1 "general_operand" "gF")
796: (match_operand:SF 2 "general_operand" "gF")))]
797: ""
798: "*
799: {
800: if (rtx_equal_p (operands[0], operands[1]))
801: return \"divf2 %2,%0\";
802: return \"divf3 %2,%1,%0\";
803: }")
804:
805: (define_insn "divsi3"
806: [(set (match_operand:SI 0 "general_operand" "=g")
807: (div:SI (match_operand:SI 1 "general_operand" "g")
808: (match_operand:SI 2 "general_operand" "g")))]
809: ""
810: "*
811: {
812: if (rtx_equal_p (operands[0], operands[1]))
813: return \"divl2 %2,%0\";
814: return \"divl3 %2,%1,%0\";
815: }")
816:
817: (define_insn "divhi3"
818: [(set (match_operand:HI 0 "general_operand" "=g")
819: (div:HI (match_operand:HI 1 "general_operand" "g")
820: (match_operand:HI 2 "general_operand" "g")))]
821: ""
822: "*
823: {
824: if (rtx_equal_p (operands[0], operands[1]))
825: return \"divw2 %2,%0\";
826: return \"divw3 %2,%1,%0\";
827: }")
828:
829: (define_insn "divqi3"
830: [(set (match_operand:QI 0 "general_operand" "=g")
831: (div:QI (match_operand:QI 1 "general_operand" "g")
832: (match_operand:QI 2 "general_operand" "g")))]
833: ""
834: "*
835: {
836: if (rtx_equal_p (operands[0], operands[1]))
837: return \"divb2 %2,%0\";
838: return \"divb3 %2,%1,%0\";
839: }")
840:
841: ;This is left out because it is very slow;
842: ;we are better off programming around the "lack" of this insn.
843: ;(define_insn "divmoddisi4"
844: ; [(set (match_operand:SI 0 "general_operand" "=g")
845: ; (div:SI (match_operand:DI 1 "general_operand" "g")
846: ; (match_operand:SI 2 "general_operand" "g")))
847: ; (set (match_operand:SI 3 "general_operand" "=g")
848: ; (mod:SI (match_operand:DI 1 "general_operand" "g")
849: ; (match_operand:SI 2 "general_operand" "g")))]
850: ; ""
851: ; "ediv %2,%1,%0,%3")
852:
1.1.1.8 root 853: ;; Bit-and on the vax is done with a clear-bits insn.
854: (define_expand "andsi3"
855: [(set (match_operand:SI 0 "general_operand" "=g")
856: (and:SI (match_operand:SI 1 "general_operand" "g")
857: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
858: ""
859: "
860: {
861: extern rtx expand_unop ();
862: if (GET_CODE (operands[2]) == CONST_INT)
863: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
864: else
865: operands[2] = expand_unop (SImode, one_cmpl_optab, operands[2], 0, 1);
866: }")
867:
868: (define_expand "andhi3"
869: [(set (match_operand:HI 0 "general_operand" "=g")
870: (and:HI (match_operand:HI 1 "general_operand" "g")
871: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
872: ""
873: "
874: {
875: extern rtx expand_unop ();
876: rtx op = operands[2];
877: if (GET_CODE (op) == CONST_INT)
878: operands[2] = gen_rtx (CONST_INT, VOIDmode,
879: ((1 << 16) - 1) & ~INTVAL (op));
880: else
881: operands[2] = expand_unop (HImode, one_cmpl_optab, op, 0, 1);
882: }")
883:
884: (define_expand "andqi3"
885: [(set (match_operand:QI 0 "general_operand" "=g")
886: (and:QI (match_operand:QI 1 "general_operand" "g")
887: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
888: ""
889: "
890: {
891: extern rtx expand_unop ();
892: rtx op = operands[2];
893: if (GET_CODE (op) == CONST_INT)
894: operands[2] = gen_rtx (CONST_INT, VOIDmode,
895: ((1 << 8) - 1) & ~INTVAL (op));
896: else
897: operands[2] = expand_unop (QImode, one_cmpl_optab, op, 0, 1);
898: }")
899:
1.1 root 900: (define_insn "andcbsi3"
901: [(set (match_operand:SI 0 "general_operand" "=g")
902: (and:SI (match_operand:SI 1 "general_operand" "g")
903: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
904: ""
905: "*
906: {
907: if (rtx_equal_p (operands[0], operands[1]))
908: return \"bicl2 %2,%0\";
909: return \"bicl3 %2,%1,%0\";
910: }")
911:
912: (define_insn "andcbhi3"
913: [(set (match_operand:HI 0 "general_operand" "=g")
914: (and:HI (match_operand:HI 1 "general_operand" "g")
915: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
916: ""
917: "*
918: {
919: if (rtx_equal_p (operands[0], operands[1]))
920: return \"bicw2 %2,%0\";
921: return \"bicw3 %2,%1,%0\";
922: }")
923:
924: (define_insn "andcbqi3"
925: [(set (match_operand:QI 0 "general_operand" "=g")
926: (and:QI (match_operand:QI 1 "general_operand" "g")
927: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
928: ""
929: "*
930: {
931: if (rtx_equal_p (operands[0], operands[1]))
932: return \"bicb2 %2,%0\";
933: return \"bicb3 %2,%1,%0\";
934: }")
935:
936: ;; The following are needed because constant propagation can
937: ;; create them starting from the bic insn patterns above.
938:
939: (define_insn ""
940: [(set (match_operand:SI 0 "general_operand" "=g")
941: (and:SI (match_operand:SI 1 "general_operand" "g")
942: (match_operand:SI 2 "general_operand" "g")))]
943: "GET_CODE (operands[2]) == CONST_INT"
944: "*
945: { operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
946: if (rtx_equal_p (operands[1], operands[0]))
947: return \"bicl2 %2,%0\";
948: return \"bicl3 %2,%1,%0\";
949: }")
950:
951: (define_insn ""
952: [(set (match_operand:HI 0 "general_operand" "=g")
953: (and:HI (match_operand:HI 1 "general_operand" "g")
954: (match_operand:HI 2 "general_operand" "g")))]
955: "GET_CODE (operands[2]) == CONST_INT"
956: "*
957: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xffff & ~INTVAL (operands[2]));
958: if (rtx_equal_p (operands[1], operands[0]))
959: return \"bicw2 %2,%0\";
960: return \"bicw3 %2,%1,%0\";
961: }")
962:
963: (define_insn ""
964: [(set (match_operand:QI 0 "general_operand" "=g")
965: (and:QI (match_operand:QI 1 "general_operand" "g")
966: (match_operand:QI 2 "general_operand" "g")))]
967: "GET_CODE (operands[2]) == CONST_INT"
968: "*
969: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xff & ~INTVAL (operands[2]));
970: if (rtx_equal_p (operands[1], operands[0]))
971: return \"bicb2 %2,%0\";
972: return \"bicb3 %2,%1,%0\";
973: }")
974:
975: ;;- Bit set instructions.
976:
977: (define_insn "iorsi3"
978: [(set (match_operand:SI 0 "general_operand" "=g")
979: (ior:SI (match_operand:SI 1 "general_operand" "g")
980: (match_operand:SI 2 "general_operand" "g")))]
981: ""
982: "*
983: {
984: if (rtx_equal_p (operands[0], operands[1]))
985: return \"bisl2 %2,%0\";
986: if (rtx_equal_p (operands[0], operands[2]))
987: return \"bisl2 %1,%0\";
988: return \"bisl3 %2,%1,%0\";
989: }")
990:
991: (define_insn "iorhi3"
992: [(set (match_operand:HI 0 "general_operand" "=g")
993: (ior:HI (match_operand:HI 1 "general_operand" "g")
994: (match_operand:HI 2 "general_operand" "g")))]
995: ""
996: "*
997: {
998: if (rtx_equal_p (operands[0], operands[1]))
999: return \"bisw2 %2,%0\";
1000: if (rtx_equal_p (operands[0], operands[2]))
1001: return \"bisw2 %1,%0\";
1002: return \"bisw3 %2,%1,%0\";
1003: }")
1004:
1005: (define_insn "iorqi3"
1006: [(set (match_operand:QI 0 "general_operand" "=g")
1007: (ior:QI (match_operand:QI 1 "general_operand" "g")
1008: (match_operand:QI 2 "general_operand" "g")))]
1009: ""
1010: "*
1011: {
1012: if (rtx_equal_p (operands[0], operands[1]))
1013: return \"bisb2 %2,%0\";
1014: if (rtx_equal_p (operands[0], operands[2]))
1015: return \"bisb2 %1,%0\";
1016: return \"bisb3 %2,%1,%0\";
1017: }")
1018:
1019: ;;- xor instructions.
1020:
1021: (define_insn "xorsi3"
1022: [(set (match_operand:SI 0 "general_operand" "=g")
1023: (xor:SI (match_operand:SI 1 "general_operand" "g")
1024: (match_operand:SI 2 "general_operand" "g")))]
1025: ""
1026: "*
1027: {
1028: if (rtx_equal_p (operands[0], operands[1]))
1029: return \"xorl2 %2,%0\";
1030: if (rtx_equal_p (operands[0], operands[2]))
1031: return \"xorl2 %1,%0\";
1032: return \"xorl3 %2,%1,%0\";
1033: }")
1034:
1035: (define_insn "xorhi3"
1036: [(set (match_operand:HI 0 "general_operand" "=g")
1037: (xor:HI (match_operand:HI 1 "general_operand" "g")
1038: (match_operand:HI 2 "general_operand" "g")))]
1039: ""
1040: "*
1041: {
1042: if (rtx_equal_p (operands[0], operands[1]))
1043: return \"xorw2 %2,%0\";
1044: if (rtx_equal_p (operands[0], operands[2]))
1045: return \"xorw2 %1,%0\";
1046: return \"xorw3 %2,%1,%0\";
1047: }")
1048:
1049: (define_insn "xorqi3"
1050: [(set (match_operand:QI 0 "general_operand" "=g")
1051: (xor:QI (match_operand:QI 1 "general_operand" "g")
1052: (match_operand:QI 2 "general_operand" "g")))]
1053: ""
1054: "*
1055: {
1056: if (rtx_equal_p (operands[0], operands[1]))
1057: return \"xorb2 %2,%0\";
1058: if (rtx_equal_p (operands[0], operands[2]))
1059: return \"xorb2 %1,%0\";
1060: return \"xorb3 %2,%1,%0\";
1061: }")
1062:
1063: (define_insn "negdf2"
1064: [(set (match_operand:DF 0 "general_operand" "=g")
1065: (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
1066: ""
1.1.1.3 root 1067: "mneg%# %1,%0")
1.1 root 1068:
1069: (define_insn "negsf2"
1070: [(set (match_operand:SF 0 "general_operand" "=g")
1071: (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
1072: ""
1073: "mnegf %1,%0")
1074:
1075: (define_insn "negsi2"
1076: [(set (match_operand:SI 0 "general_operand" "=g")
1077: (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1078: ""
1079: "mnegl %1,%0")
1080:
1081: (define_insn "neghi2"
1082: [(set (match_operand:HI 0 "general_operand" "=g")
1083: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1084: ""
1085: "mnegw %1,%0")
1086:
1087: (define_insn "negqi2"
1088: [(set (match_operand:QI 0 "general_operand" "=g")
1089: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1090: ""
1091: "mnegb %1,%0")
1092:
1093: (define_insn "one_cmplsi2"
1094: [(set (match_operand:SI 0 "general_operand" "=g")
1095: (not:SI (match_operand:SI 1 "general_operand" "g")))]
1096: ""
1097: "mcoml %1,%0")
1098:
1099: (define_insn "one_cmplhi2"
1100: [(set (match_operand:HI 0 "general_operand" "=g")
1101: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1102: ""
1103: "mcomw %1,%0")
1104:
1105: (define_insn "one_cmplqi2"
1106: [(set (match_operand:QI 0 "general_operand" "=g")
1107: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1108: ""
1109: "mcomb %1,%0")
1110:
1.1.1.8 root 1111: ;; Arithmetic right shift on the vax works by negating the shift count.
1112: (define_expand "ashrsi3"
1113: [(set (match_operand:SI 0 "general_operand" "=g")
1114: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1115: (match_operand:QI 2 "general_operand" "g")))]
1116: ""
1117: "
1118: {
1.1.1.9 root 1119: operands[2] = negate_rtx (QImode, operands[2]);
1.1.1.8 root 1120: }")
1121:
1.1 root 1122: (define_insn "ashlsi3"
1123: [(set (match_operand:SI 0 "general_operand" "=g")
1124: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1125: (match_operand:QI 2 "general_operand" "g")))]
1126: ""
1.1.1.2 root 1127: "*
1128: {
1129: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1130: return \"addl2 %0,%0\";
1.1.1.8 root 1131: if (GET_CODE (operands[1]) == REG
1132: && GET_CODE (operands[2]) == CONST_INT)
1133: {
1134: int i = INTVAL (operands[2]);
1135: if (i == 1)
1136: return \"addl3 %1,%1,%0\";
1137: if (i == 2)
1138: return \"moval 0[%1],%0\";
1139: if (i == 3)
1140: return \"movad 0[%1],%0\";
1141: }
1.1.1.2 root 1142: return \"ashl %2,%1,%0\";
1143: }")
1.1 root 1144:
1.1.1.8 root 1145: ;; Arithmetic right shift on the vax works by negating the shift count.
1146: (define_expand "ashrdi3"
1147: [(set (match_operand:DI 0 "general_operand" "=g")
1148: (ashift:DI (match_operand:DI 1 "general_operand" "g")
1149: (match_operand:QI 2 "general_operand" "g")))]
1150: ""
1151: "
1152: {
1.1.1.9 root 1153: operands[2] = negate_rtx (QImode, operands[2]);
1.1.1.8 root 1154: }")
1155:
1.1 root 1156: (define_insn "ashldi3"
1157: [(set (match_operand:DI 0 "general_operand" "=g")
1158: (ashift:DI (match_operand:DI 1 "general_operand" "g")
1159: (match_operand:QI 2 "general_operand" "g")))]
1160: ""
1161: "ashq %2,%1,%0")
1162:
1.1.1.8 root 1163: ;; Rotate right on the vax works by negating the shift count.
1164: (define_expand "rotrsi3"
1.1 root 1165: [(set (match_operand:SI 0 "general_operand" "=g")
1166: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1167: (match_operand:QI 2 "general_operand" "g")))]
1168: ""
1.1.1.8 root 1169: "
1170: {
1.1.1.9 root 1171: operands[2] = negate_rtx (QImode, operands[2]);
1.1.1.8 root 1172: }")
1.1 root 1173:
1.1.1.8 root 1174: (define_insn "rotlsi3"
1175: [(set (match_operand:SI 0 "general_operand" "=g")
1176: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1.1 root 1177: (match_operand:QI 2 "general_operand" "g")))]
1178: ""
1.1.1.8 root 1179: "rotl %2,%1,%0")
1.1 root 1180:
1.1.1.2 root 1181: ;This insn is probably slower than a multiply and an add.
1182: ;(define_insn ""
1183: ; [(set (match_operand:SI 0 "general_operand" "=g")
1184: ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1185: ; (match_operand:SI 2 "general_operand" "g"))
1186: ; (match_operand:SI 3 "general_operand" "g")))]
1187: ; ""
1188: ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1.1.1.4 root 1189:
1190: ;; Special cases of bit-field insns which we should
1191: ;; recognize in preference to the general case.
1192: ;; These handle aligned 8-bit and 16-bit fields,
1193: ;; which can usually be done with move instructions.
1194:
1195: (define_insn ""
1196: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro")
1197: (match_operand:SI 1 "immediate_operand" "i")
1198: (match_operand:SI 2 "immediate_operand" "i"))
1199: (match_operand:SI 3 "general_operand" "g"))]
1200: "GET_CODE (operands[1]) == CONST_INT
1201: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1202: && GET_CODE (operands[2]) == CONST_INT
1203: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1204: && (GET_CODE (operands[0]) == REG
1205: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1206: "*
1207: {
1208: if (REG_P (operands[0]))
1209: {
1210: if (INTVAL (operands[2]) != 0)
1211: return \"insv %3,%2,%1,%0\";
1212: }
1213: else
1214: operands[0]
1215: = adj_offsetable_operand (operands[0], INTVAL (operands[2]) / 8);
1216:
1217: if (INTVAL (operands[1]) == 8)
1218: return \"movb %3,%0\";
1219: return \"movw %3,%0\";
1220: }")
1221:
1222: (define_insn ""
1223: [(set (match_operand:SI 0 "general_operand" "=&g")
1224: (zero_extract:SI (match_operand:SI 1 "general_operand" "ro")
1225: (match_operand:SI 2 "immediate_operand" "i")
1226: (match_operand:SI 3 "immediate_operand" "i")))]
1227: "GET_CODE (operands[2]) == CONST_INT
1228: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1229: && GET_CODE (operands[3]) == CONST_INT
1230: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1231: && (GET_CODE (operands[1]) == REG
1232: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1233: "*
1234: {
1235: if (REG_P (operands[1]))
1236: {
1237: if (INTVAL (operands[3]) != 0)
1238: return \"extzv %3,%2,%1,%0\";
1239: }
1240: else
1241: operands[1]
1242: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8);
1243:
1244: if (INTVAL (operands[2]) == 8)
1245: return \"movzbl %1,%0\";
1246: return \"movzwl %1,%0\";
1247: }")
1248:
1249: (define_insn ""
1250: [(set (match_operand:SI 0 "general_operand" "=g")
1251: (sign_extract:SI (match_operand:SI 1 "general_operand" "ro")
1252: (match_operand:SI 2 "immediate_operand" "i")
1253: (match_operand:SI 3 "immediate_operand" "i")))]
1254: "GET_CODE (operands[2]) == CONST_INT
1255: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1256: && GET_CODE (operands[3]) == CONST_INT
1257: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1258: && (GET_CODE (operands[1]) == REG
1259: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1260: "*
1261: {
1262: if (REG_P (operands[1]))
1263: {
1264: if (INTVAL (operands[3]) != 0)
1265: return \"extv %3,%2,%1,%0\";
1266: }
1267: else
1268: operands[1]
1269: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8);
1270:
1271: if (INTVAL (operands[2]) == 8)
1272: return \"cvtbl %1,%0\";
1273: return \"cvtwl %1,%0\";
1274: }")
1275:
1276: ;; Register-only SImode cases of bit-field insns.
1.1 root 1277:
1278: (define_insn ""
1279: [(set (cc0)
1280: (minus
1.1.1.4 root 1281: (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1.1 root 1282: (match_operand:SI 1 "general_operand" "g")
1283: (match_operand:SI 2 "general_operand" "g"))
1284: (match_operand:SI 3 "general_operand" "g")))]
1285: ""
1286: "cmpv %2,%1,%0,%3")
1287:
1288: (define_insn ""
1289: [(set (cc0)
1290: (minus
1.1.1.4 root 1291: (zero_extract:SI (match_operand:SI 0 "general_operand" "r")
1.1 root 1292: (match_operand:SI 1 "general_operand" "g")
1293: (match_operand:SI 2 "general_operand" "g"))
1294: (match_operand:SI 3 "general_operand" "g")))]
1295: ""
1296: "cmpzv %2,%1,%0,%3")
1297:
1.1.1.4 root 1298: (define_insn ""
1.1 root 1299: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1300: (sign_extract:SI (match_operand:SI 1 "general_operand" "r")
1.1 root 1301: (match_operand:SI 2 "general_operand" "g")
1302: (match_operand:SI 3 "general_operand" "g")))]
1303: ""
1304: "extv %3,%2,%1,%0")
1305:
1.1.1.4 root 1306: (define_insn ""
1.1 root 1307: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1308: (zero_extract:SI (match_operand:SI 1 "general_operand" "r")
1.1 root 1309: (match_operand:SI 2 "general_operand" "g")
1310: (match_operand:SI 3 "general_operand" "g")))]
1311: ""
1312: "extzv %3,%2,%1,%0")
1313:
1.1.1.4 root 1314: ;; Non-register cases.
1315: ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1316: ;; don't match these (and therefore match the cases above instead).
1317:
1.1 root 1318: (define_insn ""
1.1.1.4 root 1319: [(set (cc0)
1320: (minus
1321: (sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1322: (match_operand:SI 1 "general_operand" "g")
1323: (match_operand:SI 2 "general_operand" "g"))
1324: (match_operand:SI 3 "general_operand" "g")))]
1325: ""
1326: "cmpv %2,%1,%0,%3")
1327:
1328: (define_insn ""
1329: [(set (cc0)
1330: (minus
1331: (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1332: (match_operand:SI 1 "general_operand" "g")
1333: (match_operand:SI 2 "general_operand" "g"))
1334: (match_operand:SI 3 "general_operand" "g")))]
1335: ""
1336: "cmpzv %2,%1,%0,%3")
1337:
1338: (define_insn "extv"
1.1 root 1339: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1340: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1.1 root 1341: (match_operand:SI 2 "general_operand" "g")
1342: (match_operand:SI 3 "general_operand" "g")))]
1343: ""
1344: "extv %3,%2,%1,%0")
1345:
1.1.1.4 root 1346: (define_insn "extzv"
1.1 root 1347: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1348: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1.1 root 1349: (match_operand:SI 2 "general_operand" "g")
1350: (match_operand:SI 3 "general_operand" "g")))]
1351: ""
1352: "extzv %3,%2,%1,%0")
1353:
1354: (define_insn "insv"
1.1.1.2 root 1355: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1.1 root 1356: (match_operand:SI 1 "general_operand" "g")
1357: (match_operand:SI 2 "general_operand" "g"))
1358: (match_operand:SI 3 "general_operand" "g"))]
1359: ""
1360: "insv %3,%2,%1,%0")
1361:
1362: (define_insn ""
1.1.1.2 root 1363: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1.1 root 1364: (match_operand:SI 1 "general_operand" "g")
1365: (match_operand:SI 2 "general_operand" "g"))
1366: (match_operand:SI 3 "general_operand" "g"))]
1367: ""
1368: "insv %3,%2,%1,%0")
1369:
1370: (define_insn "jump"
1371: [(set (pc)
1372: (label_ref (match_operand 0 "" "")))]
1373: ""
1374: "jbr %l0")
1375:
1376: (define_insn "beq"
1377: [(set (pc)
1378: (if_then_else (eq (cc0)
1379: (const_int 0))
1380: (label_ref (match_operand 0 "" ""))
1381: (pc)))]
1382: ""
1383: "jeql %l0")
1384:
1385: (define_insn "bne"
1386: [(set (pc)
1387: (if_then_else (ne (cc0)
1388: (const_int 0))
1389: (label_ref (match_operand 0 "" ""))
1390: (pc)))]
1391: ""
1392: "jneq %l0")
1393:
1394: (define_insn "bgt"
1395: [(set (pc)
1396: (if_then_else (gt (cc0)
1397: (const_int 0))
1398: (label_ref (match_operand 0 "" ""))
1399: (pc)))]
1400: ""
1401: "jgtr %l0")
1402:
1403: (define_insn "bgtu"
1404: [(set (pc)
1405: (if_then_else (gtu (cc0)
1406: (const_int 0))
1407: (label_ref (match_operand 0 "" ""))
1408: (pc)))]
1409: ""
1410: "jgtru %l0")
1411:
1412: (define_insn "blt"
1413: [(set (pc)
1414: (if_then_else (lt (cc0)
1415: (const_int 0))
1416: (label_ref (match_operand 0 "" ""))
1417: (pc)))]
1418: ""
1419: "jlss %l0")
1420:
1421: (define_insn "bltu"
1422: [(set (pc)
1423: (if_then_else (ltu (cc0)
1424: (const_int 0))
1425: (label_ref (match_operand 0 "" ""))
1426: (pc)))]
1427: ""
1428: "jlssu %l0")
1429:
1430: (define_insn "bge"
1431: [(set (pc)
1432: (if_then_else (ge (cc0)
1433: (const_int 0))
1434: (label_ref (match_operand 0 "" ""))
1435: (pc)))]
1436: ""
1437: "jgeq %l0")
1438:
1439: (define_insn "bgeu"
1440: [(set (pc)
1441: (if_then_else (geu (cc0)
1442: (const_int 0))
1443: (label_ref (match_operand 0 "" ""))
1444: (pc)))]
1445: ""
1446: "jgequ %l0")
1447:
1448: (define_insn "ble"
1449: [(set (pc)
1450: (if_then_else (le (cc0)
1451: (const_int 0))
1452: (label_ref (match_operand 0 "" ""))
1453: (pc)))]
1454: ""
1455: "jleq %l0")
1456:
1457: (define_insn "bleu"
1458: [(set (pc)
1459: (if_then_else (leu (cc0)
1460: (const_int 0))
1461: (label_ref (match_operand 0 "" ""))
1462: (pc)))]
1463: ""
1464: "jlequ %l0")
1465:
1466: (define_insn ""
1467: [(set (pc)
1468: (if_then_else (eq (cc0)
1469: (const_int 0))
1470: (pc)
1471: (label_ref (match_operand 0 "" ""))))]
1472: ""
1473: "jneq %l0")
1474:
1475: (define_insn ""
1476: [(set (pc)
1477: (if_then_else (ne (cc0)
1478: (const_int 0))
1479: (pc)
1480: (label_ref (match_operand 0 "" ""))))]
1481: ""
1482: "jeql %l0")
1483:
1484: (define_insn ""
1485: [(set (pc)
1486: (if_then_else (gt (cc0)
1487: (const_int 0))
1488: (pc)
1489: (label_ref (match_operand 0 "" ""))))]
1490: ""
1491: "jleq %l0")
1492:
1493: (define_insn ""
1494: [(set (pc)
1495: (if_then_else (gtu (cc0)
1496: (const_int 0))
1497: (pc)
1498: (label_ref (match_operand 0 "" ""))))]
1499: ""
1500: "jlequ %l0")
1501:
1502: (define_insn ""
1503: [(set (pc)
1504: (if_then_else (lt (cc0)
1505: (const_int 0))
1506: (pc)
1507: (label_ref (match_operand 0 "" ""))))]
1508: ""
1509: "jgeq %l0")
1510:
1511: (define_insn ""
1512: [(set (pc)
1513: (if_then_else (ltu (cc0)
1514: (const_int 0))
1515: (pc)
1516: (label_ref (match_operand 0 "" ""))))]
1517: ""
1518: "jgequ %l0")
1519:
1520: (define_insn ""
1521: [(set (pc)
1522: (if_then_else (ge (cc0)
1523: (const_int 0))
1524: (pc)
1525: (label_ref (match_operand 0 "" ""))))]
1526: ""
1527: "jlss %l0")
1528:
1529: (define_insn ""
1530: [(set (pc)
1531: (if_then_else (geu (cc0)
1532: (const_int 0))
1533: (pc)
1534: (label_ref (match_operand 0 "" ""))))]
1535: ""
1536: "jlssu %l0")
1537:
1538: (define_insn ""
1539: [(set (pc)
1540: (if_then_else (le (cc0)
1541: (const_int 0))
1542: (pc)
1543: (label_ref (match_operand 0 "" ""))))]
1544: ""
1545: "jgtr %l0")
1546:
1547: (define_insn ""
1548: [(set (pc)
1549: (if_then_else (leu (cc0)
1550: (const_int 0))
1551: (pc)
1552: (label_ref (match_operand 0 "" ""))))]
1553: ""
1554: "jgtru %l0")
1555:
1556: ;; Recognize jbs and jbc instructions.
1557:
1558: (define_insn ""
1559: [(set (pc)
1560: (if_then_else
1561: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1562: (const_int 1)
1563: (match_operand:SI 1 "general_operand" "g"))
1564: (const_int 0))
1565: (label_ref (match_operand 2 "" ""))
1566: (pc)))]
1567: ""
1568: "jbs %1,%0,%l2")
1569:
1570: (define_insn ""
1571: [(set (pc)
1572: (if_then_else
1573: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1574: (const_int 1)
1575: (match_operand:SI 1 "general_operand" "g"))
1576: (const_int 0))
1577: (label_ref (match_operand 2 "" ""))
1578: (pc)))]
1579: ""
1580: "jbc %1,%0,%l2")
1581:
1582: (define_insn ""
1583: [(set (pc)
1584: (if_then_else
1585: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1586: (const_int 1)
1587: (match_operand:SI 1 "general_operand" "g"))
1588: (const_int 0))
1589: (pc)
1590: (label_ref (match_operand 2 "" ""))))]
1591: ""
1592: "jbc %1,%0,%l2")
1593:
1594: (define_insn ""
1595: [(set (pc)
1596: (if_then_else
1597: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1598: (const_int 1)
1599: (match_operand:SI 1 "general_operand" "g"))
1600: (const_int 0))
1601: (pc)
1602: (label_ref (match_operand 2 "" ""))))]
1603: ""
1604: "jbs %1,%0,%l2")
1605:
1606: (define_insn ""
1607: [(set (pc)
1608: (if_then_else
1609: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1610: (const_int 1)
1611: (match_operand:SI 1 "general_operand" "g"))
1612: (const_int 0))
1613: (label_ref (match_operand 2 "" ""))
1614: (pc)))]
1.1.1.2 root 1615: "GET_CODE (operands[0]) != MEM
1616: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1617: "jbs %1,%0,%l2")
1618:
1619: (define_insn ""
1620: [(set (pc)
1621: (if_then_else
1622: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1623: (const_int 1)
1624: (match_operand:SI 1 "general_operand" "g"))
1625: (const_int 0))
1626: (label_ref (match_operand 2 "" ""))
1627: (pc)))]
1.1.1.2 root 1628: "GET_CODE (operands[0]) != MEM
1629: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1630: "jbc %1,%0,%l2")
1631:
1632: (define_insn ""
1633: [(set (pc)
1634: (if_then_else
1.1.1.2 root 1635: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1636: (match_operand:SI 1 "general_operand" "g"))
1637: (const_int 0))
1638: (pc)
1639: (label_ref (match_operand 2 "" ""))))]
1640: "GET_CODE (operands[1]) == CONST_INT
1641: && exact_log2 (INTVAL (operands[1])) >= 0
1642: && (GET_CODE (operands[0]) != MEM
1643: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1644: "*
1645: {
1646: operands[1]
1647: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1648: return \"jbs %1,%0,%l2\";
1649: }")
1650:
1651: (define_insn ""
1652: [(set (pc)
1653: (if_then_else
1654: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1655: (match_operand:SI 1 "general_operand" "g"))
1656: (const_int 0))
1657: (label_ref (match_operand 2 "" ""))
1658: (pc)))]
1659: "GET_CODE (operands[1]) == CONST_INT
1660: && exact_log2 (INTVAL (operands[1])) >= 0
1661: && (GET_CODE (operands[0]) != MEM
1662: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1663: "*
1664: {
1665: operands[1]
1666: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1667: return \"jbc %1,%0,%l2\";
1668: }")
1669:
1670: (define_insn ""
1671: [(set (pc)
1672: (if_then_else
1673: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1674: (match_operand:SI 1 "general_operand" "g"))
1675: (const_int 0))
1676: (pc)
1677: (label_ref (match_operand 2 "" ""))))]
1678: "GET_CODE (operands[1]) == CONST_INT
1679: && exact_log2 (INTVAL (operands[1])) >= 0
1680: && (GET_CODE (operands[0]) != MEM
1681: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1682: "*
1683: {
1684: operands[1]
1685: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1686: return \"jbc %1,%0,%l2\";
1687: }")
1688:
1689: (define_insn ""
1690: [(set (pc)
1691: (if_then_else
1692: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1693: (match_operand:SI 1 "general_operand" "g"))
1694: (const_int 0))
1695: (label_ref (match_operand 2 "" ""))
1696: (pc)))]
1697: "GET_CODE (operands[1]) == CONST_INT
1698: && exact_log2 (INTVAL (operands[1])) >= 0
1699: && (GET_CODE (operands[0]) != MEM
1700: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1701: "*
1702: {
1703: operands[1]
1704: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1705: return \"jbs %1,%0,%l2\";
1706: }")
1707:
1708: (define_insn ""
1709: [(set (pc)
1710: (if_then_else
1.1 root 1711: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1712: (const_int 1)
1713: (match_operand:SI 1 "general_operand" "g"))
1714: (const_int 0))
1715: (pc)
1716: (label_ref (match_operand 2 "" ""))))]
1.1.1.2 root 1717: "GET_CODE (operands[0]) != MEM
1718: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1719: "jbc %1,%0,%l2")
1720:
1721: (define_insn ""
1722: [(set (pc)
1723: (if_then_else
1724: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1725: (const_int 1)
1726: (match_operand:SI 1 "general_operand" "g"))
1727: (const_int 0))
1728: (pc)
1729: (label_ref (match_operand 2 "" ""))))]
1.1.1.2 root 1730: "GET_CODE (operands[0]) != MEM
1731: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1732: "jbs %1,%0,%l2")
1733:
1734: (define_insn ""
1735: [(set (pc)
1736: (if_then_else
1737: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1738: (const_int 1))
1739: (const_int 0))
1740: (label_ref (match_operand 1 "" ""))
1741: (pc)))]
1.1.1.2 root 1742: "GET_CODE (operands[0]) != MEM
1743: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1744: "jlbs %0,%l1")
1745:
1746: (define_insn ""
1747: [(set (pc)
1748: (if_then_else
1749: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1750: (const_int 1))
1751: (const_int 0))
1752: (label_ref (match_operand 1 "" ""))
1753: (pc)))]
1.1.1.2 root 1754: "GET_CODE (operands[0]) != MEM
1755: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1756: "jlbc %0,%l1")
1757:
1758: (define_insn ""
1759: [(set (pc)
1760: (if_then_else
1761: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1762: (const_int 1))
1763: (const_int 0))
1764: (pc)
1765: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1766: "GET_CODE (operands[0]) != MEM
1767: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1768: "jlbc %0,%l1")
1769:
1770: (define_insn ""
1771: [(set (pc)
1772: (if_then_else
1773: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1774: (const_int 1))
1775: (const_int 0))
1776: (pc)
1777: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1778: "GET_CODE (operands[0]) != MEM
1779: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1780: "jlbs %0,%l1")
1781:
1782: ;; These four entries allow a jlbc or jlbs to be made
1783: ;; by combination with a bic.
1784: (define_insn ""
1785: [(set (pc)
1786: (if_then_else
1787: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1788: (not:SI (const_int -2)))
1789: (const_int 0))
1790: (label_ref (match_operand 1 "" ""))
1791: (pc)))]
1.1.1.2 root 1792: "GET_CODE (operands[0]) != MEM
1793: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1794: "jlbs %0,%l1")
1795:
1796: (define_insn ""
1797: [(set (pc)
1798: (if_then_else
1799: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1800: (not:SI (const_int -2)))
1801: (const_int 0))
1802: (label_ref (match_operand 1 "" ""))
1803: (pc)))]
1.1.1.2 root 1804: "GET_CODE (operands[0]) != MEM
1805: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1806: "jlbc %0,%l1")
1807:
1808: (define_insn ""
1809: [(set (pc)
1810: (if_then_else
1811: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1812: (not:SI (const_int -2)))
1813: (const_int 0))
1814: (pc)
1815: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1816: "GET_CODE (operands[0]) != MEM
1817: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1818: "jlbc %0,%l1")
1819:
1820: (define_insn ""
1821: [(set (pc)
1822: (if_then_else
1823: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1824: (not:SI (const_int -2)))
1825: (const_int 0))
1826: (pc)
1827: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1828: "GET_CODE (operands[0]) != MEM
1829: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1830: "jlbs %0,%l1")
1831:
1832: ;; Subtract-and-jump and Add-and-jump insns.
1833: ;; These are not used when output is for the Unix assembler
1834: ;; because it does not know how to modify them to reach far.
1835:
1836: ;; Normal sob insns.
1837:
1838: (define_insn ""
1839: [(set (pc)
1840: (if_then_else
1.1.1.8 root 1841: (gt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1842: (const_int -1))
1.1 root 1843: (const_int 0))
1844: (label_ref (match_operand 1 "" ""))
1845: (pc)))
1846: (set (match_dup 0)
1.1.1.2 root 1847: (plus:SI (match_dup 0)
1848: (const_int -1)))]
1.1 root 1849: "!TARGET_UNIX_ASM"
1850: "jsobgtr %0,%l1")
1851:
1852: (define_insn ""
1853: [(set (pc)
1854: (if_then_else
1.1.1.8 root 1855: (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")
1856: (const_int -1))
1.1 root 1857: (const_int 0))
1858: (label_ref (match_operand 1 "" ""))
1859: (pc)))
1860: (set (match_dup 0)
1.1.1.2 root 1861: (plus:SI (match_dup 0)
1862: (const_int -1)))]
1.1 root 1863: "!TARGET_UNIX_ASM"
1864: "jsobgeq %0,%l1")
1865:
1866: ;; Reversed sob insns.
1867:
1868: (define_insn ""
1869: [(set (pc)
1870: (if_then_else
1.1.1.8 root 1871: (le (plus:SI (match_operand:SI 0 "general_operand" "+g")
1872: (const_int -1))
1.1 root 1873: (const_int 0))
1874: (pc)
1875: (label_ref (match_operand 1 "" ""))))
1876: (set (match_dup 0)
1.1.1.2 root 1877: (plus:SI (match_dup 0)
1878: (const_int -1)))]
1.1 root 1879: "!TARGET_UNIX_ASM"
1880: "jsobgtr %0,%l1")
1881:
1882: (define_insn ""
1883: [(set (pc)
1884: (if_then_else
1.1.1.8 root 1885: (lt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1886: (const_int -1))
1.1 root 1887: (const_int 0))
1888: (pc)
1889: (label_ref (match_operand 1 "" ""))))
1890: (set (match_dup 0)
1.1.1.2 root 1891: (plus:SI (match_dup 0)
1892: (const_int -1)))]
1.1 root 1893: "!TARGET_UNIX_ASM"
1894: "jsobgeq %0,%l1")
1895:
1896: ;; Normal aob insns.
1897: (define_insn ""
1898: [(set (pc)
1899: (if_then_else
1900: (lt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1901: (const_int 1))
1902: (match_operand:SI 1 "general_operand" "g"))
1903: (const_int 0))
1904: (label_ref (match_operand 2 "" ""))
1905: (pc)))
1906: (set (match_dup 0)
1907: (plus:SI (match_dup 0)
1908: (const_int 1)))]
1909: "!TARGET_UNIX_ASM"
1910: "jaoblss %1,%0,%l2")
1911:
1912: (define_insn ""
1913: [(set (pc)
1914: (if_then_else
1915: (le (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1916: (const_int 1))
1917: (match_operand:SI 1 "general_operand" "g"))
1918: (const_int 0))
1919: (label_ref (match_operand 2 "" ""))
1920: (pc)))
1921: (set (match_dup 0)
1922: (plus:SI (match_dup 0)
1923: (const_int 1)))]
1924: "!TARGET_UNIX_ASM"
1925: "jaobleq %1,%0,%l2")
1926:
1927: ;; Reverse aob insns.
1928: (define_insn ""
1929: [(set (pc)
1930: (if_then_else
1931: (ge (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1932: (const_int 1))
1933: (match_operand:SI 1 "general_operand" "g"))
1934: (const_int 0))
1935: (pc)
1936: (label_ref (match_operand 2 "" ""))))
1937: (set (match_dup 0)
1938: (plus:SI (match_dup 0)
1939: (const_int 1)))]
1940: "!TARGET_UNIX_ASM"
1941: "jaoblss %1,%0,%l2")
1942:
1943: (define_insn ""
1944: [(set (pc)
1945: (if_then_else
1946: (gt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1947: (const_int 1))
1948: (match_operand:SI 1 "general_operand" "g"))
1949: (const_int 0))
1950: (pc)
1951: (label_ref (match_operand 2 "" ""))))
1952: (set (match_dup 0)
1953: (plus:SI (match_dup 0)
1954: (const_int 1)))]
1955: "!TARGET_UNIX_ASM"
1956: "jaobleq %1,%0,%l2")
1.1.1.5 root 1957:
1958: ;; Something like a sob insn, but compares against -1.
1959: ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1960:
1961: (define_insn ""
1962: [(set (pc)
1963: (if_then_else
1964: (ne (minus (plus:SI (match_operand:SI 0 "general_operand" "g")
1965: (const_int -1))
1966: (const_int -1))
1967: (const_int 0))
1968: (label_ref (match_operand 1 "" ""))
1969: (pc)))
1970: (set (match_dup 0)
1971: (plus:SI (match_dup 0)
1972: (const_int -1)))]
1973: ""
1974: "decl %0\;jgequ %l1")
1.1 root 1975:
1.1.1.2 root 1976: ;; Note that operand 1 is total size of args, in bytes,
1977: ;; and what the call insn wants is the number of words.
1.1 root 1978: (define_insn "call"
1979: [(call (match_operand:QI 0 "general_operand" "g")
1980: (match_operand:QI 1 "general_operand" "g"))]
1981: ""
1.1.1.2 root 1982: "*
1.1.1.5 root 1983: if (INTVAL (operands[1]) > 255 * 4)
1984: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1985: return \"calls $0,%0\;addl2 %1,sp\";
1.1.1.2 root 1986: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);
1987: return \"calls %1,%0\";
1988: ")
1989:
1990: (define_insn "call_value"
1991: [(set (match_operand 0 "" "g")
1992: (call (match_operand:QI 1 "general_operand" "g")
1993: (match_operand:QI 2 "general_operand" "g")))]
1994: ""
1995: "*
1.1.1.7 root 1996: if (INTVAL (operands[2]) > 255 * 4)
1.1.1.6 root 1997: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1998: return \"calls $0,%1\;addl2 %2,sp\";
1.1.1.2 root 1999: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4);
2000: return \"calls %2,%1\";
2001: ")
1.1 root 2002:
2003: (define_insn "return"
2004: [(return)]
2005: ""
2006: "ret")
2007:
2008: (define_insn "casesi"
2009: [(set (pc)
2010: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
2011: (match_operand:SI 1 "general_operand" "g"))
2012: (match_operand:SI 2 "general_operand" "g"))
1.1.1.2 root 2013: (plus:SI (sign_extend:SI
1.1 root 2014: (mem:HI (plus:SI (pc)
2015: (minus:SI (match_dup 0)
1.1.1.2 root 2016: (match_dup 1)))))
2017: (label_ref:SI (match_operand 3 "" "")))
1.1 root 2018: (pc)))]
2019: ""
2020: "casel %0,%1,%2")
2021:
1.1.1.2 root 2022: ;; This used to arise from the preceding by simplification
2023: ;; if operand 1 is zero. Perhaps it is no longer necessary.
2024: (define_insn ""
2025: [(set (pc)
2026: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
2027: (match_operand:SI 1 "general_operand" "g"))
2028: (plus:SI (sign_extend:SI
2029: (mem:HI (plus:SI (pc)
2030: (minus:SI (match_dup 0)
2031: (const_int 0)))))
2032: (label_ref:SI (match_operand 3 "" "")))
2033: (pc)))]
2034: ""
2035: "casel %0,$0,%1")
2036:
1.1 root 2037: ;; This arises from the preceding by simplification if operand 1 is zero.
2038: (define_insn ""
2039: [(set (pc)
2040: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
2041: (match_operand:SI 1 "general_operand" "g"))
1.1.1.2 root 2042: (plus:SI (sign_extend:SI
1.1 root 2043: (mem:HI (plus:SI (pc)
1.1.1.2 root 2044: (match_dup 0))))
2045: (label_ref:SI (match_operand 3 "" "")))
1.1 root 2046: (pc)))]
2047: ""
2048: "casel %0,$0,%1")
2049:
1.1.1.2 root 2050: ;; Optimize extzv ...,z; andl2 ...,z
2051: ;; with other operands constant.
2052: (define_peephole
2053: [(set (match_operand:SI 0 "general_operand" "g")
2054: (zero_extract:SI (match_operand:SI 1 "general_operand" "g")
2055: (match_operand:SI 2 "general_operand" "g")
2056: (match_operand:SI 3 "general_operand" "g")))
2057: (set (match_operand:SI 4 "general_operand" "g")
2058: (and:SI (match_dup 0)
2059: (match_operand:SI 5 "general_operand" "g")))]
2060: "GET_CODE (operands[2]) == CONST_INT
2061: && GET_CODE (operands[3]) == CONST_INT
2062: && (INTVAL (operands[2]) + INTVAL (operands[3])) == 32
2063: && GET_CODE (operands[5]) == CONST_INT
2064: && dead_or_set_p (insn, operands[0])"
2065: "*
2066: {
2067: unsigned long mask = INTVAL (operands[5]);
2068: operands[3] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[3]));
2069:
2070: if ((floor_log2 (mask) + 1) >= INTVAL (operands[2]))
2071: mask &= ((1 << INTVAL (operands[2])) - 1);
2072:
2073: operands[5] = gen_rtx (CONST_INT, VOIDmode, ~mask);
2074: if (push_operand (operands[4], SImode))
2075: {
2076: output_asm_insn (\"rotl %3,%1,%0\", operands);
2077: return \"bicl3 %5,%0,%4\";
2078: }
2079: else
2080: {
2081: output_asm_insn (\"rotl %3,%1,%4\", operands);
2082: return \"bicl2 %5,%4\";
2083: }
2084: }")
2085:
2086: ;; Optimize andl3 x,y,z; extzv z,....,z
2087:
2088: (define_peephole
2089: [(set (match_operand:SI 0 "general_operand" "g")
2090: (and:SI (match_operand:SI 1 "general_operand" "g")
2091: (match_operand:SI 2 "general_operand" "g")))
2092: (set (match_operand 3 "general_operand" "g")
2093: (zero_extract:SI (match_dup 0)
2094: (match_operand:SI 4 "general_operand" "g")
2095: (match_operand:SI 5 "general_operand" "g")))]
2096: "GET_CODE (operands[2]) == CONST_INT
2097: && GET_CODE (operands[4]) == CONST_INT
2098: && GET_CODE (operands[5]) == CONST_INT
2099: && (INTVAL (operands[4]) + INTVAL (operands[5])) == 32
2100: && dead_or_set_p (insn, operands[0])"
2101: "*
2102: {
2103: unsigned long mask = INTVAL (operands[2]);
2104:
2105: mask &= ~((1 << INTVAL (operands[5])) - 1);
2106: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~mask);
2107:
2108: operands[5] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[5]));
2109:
2110: if (rtx_equal_p (operands[0], operands[1]))
2111: output_asm_insn (\"bicl2 %2,%0\", operands);
2112: else
2113: output_asm_insn (\"bicl3 %2,%1,%0\", operands);
2114: return \"rotl %5,%0,%3\";
2115: }")
2116:
1.1 root 2117: ;;- Local variables:
2118: ;;- mode:emacs-lisp
2119: ;;- comment-start: ";;- "
2120: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2121: ;;- eval: (modify-syntax-entry ?[ "(]")
2122: ;;- eval: (modify-syntax-entry ?] ")[")
2123: ;;- eval: (modify-syntax-entry ?{ "(}")
2124: ;;- eval: (modify-syntax-entry ?} "){")
2125: ;;- End:
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