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1.1.1.4 root 1:
1.1 root 2: ;;- Machine description for GNU compiler
3: ;;- Vax Version
4: ;; Copyright (C) 1987 Free Software Foundation, Inc.
5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is distributed in the hope that it will be useful,
9: ;; but WITHOUT ANY WARRANTY. No author or distributor
10: ;; accepts responsibility to anyone for the consequences of using it
11: ;; or for whether it serves any particular purpose or works at all,
12: ;; unless he says so in writing. Refer to the GNU CC General Public
13: ;; License for full details.
14:
15: ;; Everyone is granted permission to copy, modify and redistribute
16: ;; GNU CC, but only under the conditions described in the
17: ;; GNU CC General Public License. A copy of this license is
18: ;; supposed to have been given to you along with GNU CC so you
19: ;; can know your rights and responsibilities. It should be in a
20: ;; file named COPYING. Among other things, the copyright notice
21: ;; and this notice must be preserved on all copies.
22:
23:
24: ;;- Instruction patterns. When multiple patterns apply,
25: ;;- the first one in the file is chosen.
26: ;;-
27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28: ;;-
29: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
30: ;;- updates for most instructions.
31:
1.1.1.2 root 32: ; tstsi is first test insn so that it is the one to match
33: ; a constant argument.
1.1 root 34:
35: (define_insn "tstsi"
36: [(set (cc0)
37: (match_operand:SI 0 "general_operand" "g"))]
38: ""
39: "tstl %0")
40:
41: (define_insn "tsthi"
42: [(set (cc0)
43: (match_operand:HI 0 "general_operand" "g"))]
44: ""
45: "tstw %0")
46:
47: (define_insn "tstqi"
48: [(set (cc0)
49: (match_operand:QI 0 "general_operand" "g"))]
50: ""
51: "tstb %0")
52:
1.1.1.2 root 53: (define_insn "tstdf"
1.1 root 54: [(set (cc0)
1.1.1.2 root 55: (match_operand:DF 0 "general_operand" "gF"))]
1.1 root 56: ""
1.1.1.3 root 57: "tst%# %0")
1.1 root 58:
1.1.1.2 root 59: (define_insn "tstsf"
1.1 root 60: [(set (cc0)
1.1.1.2 root 61: (match_operand:SF 0 "general_operand" "gF"))]
1.1 root 62: ""
1.1.1.2 root 63: "tstf %0")
1.1 root 64:
65: (define_insn "cmpsi"
66: [(set (cc0)
67: (minus (match_operand:SI 0 "general_operand" "g")
68: (match_operand:SI 1 "general_operand" "g")))]
69: ""
70: "cmpl %0,%1")
71:
72: (define_insn "cmphi"
73: [(set (cc0)
74: (minus (match_operand:HI 0 "general_operand" "g")
75: (match_operand:HI 1 "general_operand" "g")))]
76: ""
77: "cmpw %0,%1")
78:
79: (define_insn "cmpqi"
80: [(set (cc0)
81: (minus (match_operand:QI 0 "general_operand" "g")
82: (match_operand:QI 1 "general_operand" "g")))]
83: ""
84: "cmpb %0,%1")
85:
1.1.1.2 root 86: (define_insn "cmpdf"
87: [(set (cc0)
88: (minus (match_operand:DF 0 "general_operand" "gF")
89: (match_operand:DF 1 "general_operand" "gF")))]
90: ""
1.1.1.3 root 91: "cmp%# %0,%1")
1.1.1.2 root 92:
93: (define_insn "cmpsf"
94: [(set (cc0)
95: (minus (match_operand:SF 0 "general_operand" "gF")
96: (match_operand:SF 1 "general_operand" "gF")))]
97: ""
98: "cmpf %0,%1")
99:
1.1 root 100: (define_insn ""
101: [(set (cc0)
102: (and:SI (match_operand:SI 0 "general_operand" "g")
103: (match_operand:SI 1 "general_operand" "g")))]
104: ""
105: "bitl %0,%1")
106:
107: (define_insn ""
108: [(set (cc0)
109: (and:HI (match_operand:HI 0 "general_operand" "g")
110: (match_operand:HI 1 "general_operand" "g")))]
111: ""
112: "bitw %0,%1")
113:
114: (define_insn ""
115: [(set (cc0)
116: (and:QI (match_operand:QI 0 "general_operand" "g")
117: (match_operand:QI 1 "general_operand" "g")))]
118: ""
119: "bitb %0,%1")
120:
121: (define_insn "movdf"
122: [(set (match_operand:DF 0 "general_operand" "=g")
123: (match_operand:DF 1 "general_operand" "gF"))]
124: ""
125: "*
126: {
127: if (operands[1] == dconst0_rtx)
1.1.1.3 root 128: return \"clr%# %0\";
129: return \"mov%# %1,%0\";
1.1 root 130: }")
131:
132: (define_insn "movsf"
133: [(set (match_operand:SF 0 "general_operand" "=g")
134: (match_operand:SF 1 "general_operand" "gF"))]
135: ""
136: "*
137: {
138: if (operands[1] == fconst0_rtx)
139: return \"clrf %0\";
140: return \"movf %1,%0\";
141: }")
142:
1.1.1.2 root 143: ;; Some vaxes don't support this instruction.
144: ;;(define_insn "movti"
145: ;; [(set (match_operand:TI 0 "general_operand" "=g")
146: ;; (match_operand:TI 1 "general_operand" "g"))]
147: ;; ""
148: ;; "movh %1,%0")
1.1 root 149:
150: (define_insn "movdi"
151: [(set (match_operand:DI 0 "general_operand" "=g")
152: (match_operand:DI 1 "general_operand" "g"))]
153: ""
1.1.1.2 root 154: "movq %1,%0")
1.1 root 155:
156: (define_insn "movsi"
157: [(set (match_operand:SI 0 "general_operand" "=g")
158: (match_operand:SI 1 "general_operand" "g"))]
159: ""
160: "*
1.1.1.8 root 161: {
162: rtx link;
163: if (operands[1] == const1_rtx
164: && (link = find_reg_note (insn, REG_WAS_0, 0))
1.1.1.2 root 165: /* Make sure the insn that stored the 0 is still present. */
1.1.1.8 root 166: && ! XEXP (link, 0)->volatil
167: && GET_CODE (XEXP (link, 0)) != NOTE
1.1.1.5 root 168: /* Make sure cross jumping didn't happen here. */
1.1.1.8 root 169: && no_labels_between_p (XEXP (link, 0), insn))
1.1.1.2 root 170: /* Fastest way to change a 0 to a 1. */
1.1 root 171: return \"incl %0\";
172: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
173: {
174: if (push_operand (operands[0], SImode))
175: return \"pushab %a1\";
176: return \"movab %a1,%0\";
177: }
1.1.1.8 root 178: /* this is slower than a movl, except when pushing an operand */
1.1 root 179: if (operands[1] == const0_rtx)
180: return \"clrl %0\";
181: if (GET_CODE (operands[1]) == CONST_INT
182: && (unsigned) INTVAL (operands[1]) >= 64)
183: {
184: int i = INTVAL (operands[1]);
1.1.1.8 root 185: if ((unsigned)(~i) < 64)
1.1 root 186: {
1.1.1.8 root 187: operands[1] = gen_rtx (CONST_INT, VOIDmode, ~i);
188: return \"mcoml %1,%0\";
1.1 root 189: }
1.1.1.8 root 190: if ((unsigned)i < 127)
191: {
192: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
193: operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63);
194: return \"addl3 %2,%1,%0\";
195: }
196: /* trading speed for space */
1.1 root 197: if ((unsigned)i < 0x100)
198: return \"movzbl %1,%0\";
199: if (i >= -0x80 && i < 0)
200: return \"cvtbl %1,%0\";
201: if ((unsigned)i < 0x10000)
202: return \"movzwl %1,%0\";
203: if (i >= -0x8000 && i < 0)
204: return \"cvtwl %1,%0\";
205: }
206: if (push_operand (operands[0], SImode))
207: return \"pushl %1\";
208: return \"movl %1,%0\";
209: }")
210:
211: (define_insn "movhi"
212: [(set (match_operand:HI 0 "general_operand" "=g")
213: (match_operand:HI 1 "general_operand" "g"))]
214: ""
215: "*
216: {
1.1.1.8 root 217: rtx link;
218: if (operands[1] == const1_rtx
219: && (link = find_reg_note (insn, REG_WAS_0, 0))
220: /* Make sure the insn that stored the 0 is still present. */
221: && ! XEXP (link, 0)->volatil
222: && GET_CODE (XEXP (link, 0)) != NOTE
223: /* Make sure cross jumping didn't happen here. */
224: && no_labels_between_p (XEXP (link, 0), insn))
225: /* Fastest way to change a 0 to a 1. */
1.1 root 226: return \"incw %0\";
227: if (operands[1] == const0_rtx)
228: return \"clrw %0\";
229: if (GET_CODE (operands[1]) == CONST_INT
230: && (unsigned) INTVAL (operands[1]) >= 64)
231: {
232: int i = INTVAL (operands[1]);
1.1.1.9 root 233: if ((unsigned)((~i) & 0xffff) < 64)
1.1 root 234: {
1.1.1.9 root 235: operands[1] = gen_rtx (CONST_INT, VOIDmode, (~i) & 0xffff);
1.1.1.8 root 236: return \"mcomw %1,%0\";
1.1 root 237: }
1.1.1.8 root 238: if ((unsigned)(i & 0xffff) < 127)
239: {
240: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
1.1.1.9 root 241: operands[2] = gen_rtx (CONST_INT, VOIDmode, (i-63) & 0xffff);
1.1.1.8 root 242: return \"addw3 %2,%1,%0\";
243: }
244: /* this is a lot slower, and only saves 1 measly byte! */
245: /* if ((unsigned)i < 0x100)
246: return \"movzbw %1,%0\"; */
247: /* if (i >= -0x80 && i < 0)
248: return \"cvtbw %1,%0\"; */
1.1 root 249: }
250: return \"movw %1,%0\";
251: }")
252:
253: (define_insn "movqi"
254: [(set (match_operand:QI 0 "general_operand" "=g")
255: (match_operand:QI 1 "general_operand" "g"))]
256: ""
257: "*
258: {
259: if (operands[1] == const0_rtx)
260: return \"clrb %0\";
1.1.1.8 root 261: if (GET_CODE (operands[1]) == CONST_INT
262: && (unsigned) INTVAL (operands[1]) >= 64)
263: {
264: int i = INTVAL (operands[1]);
1.1.1.10 root 265: if ((unsigned)((~i) & 0xff) < 64)
1.1.1.8 root 266: {
1.1.1.10 root 267: operands[1] = gen_rtx (CONST_INT, VOIDmode, (~i) & 0xff);
1.1.1.8 root 268: return \"mcomb %1,%0\";
269: }
270: #if 0
271: /* ASCII alphabetics */
272: if (((unsigned) INTVAL (operands[1]) &0xff) < 127)
273: {
274: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
275: operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63);
276: return \"addb3 %2,%1,%0\";
277: }
278: #endif
279: }
1.1 root 280: return \"movb %1,%0\";
281: }")
282:
283: ;; The definition of this insn does not really explain what it does,
284: ;; but it should suffice
285: ;; that anything generated as this insn will be recognized as one
286: ;; and that it won't successfully combine with anything.
287: (define_insn "movstrhi"
288: [(set (match_operand:BLK 0 "general_operand" "=g")
289: (match_operand:BLK 1 "general_operand" "g"))
290: (use (match_operand:HI 2 "general_operand" "g"))
1.1.1.2 root 291: (clobber (reg:SI 0))
292: (clobber (reg:SI 1))
293: (clobber (reg:SI 2))
294: (clobber (reg:SI 3))
295: (clobber (reg:SI 4))
296: (clobber (reg:SI 5))]
1.1 root 297: ""
298: "movc3 %2,%1,%0")
299:
1.1.1.2 root 300: ;; Extension and truncation insns.
301: ;; Those for integer source operand
302: ;; are ordered widest source type first.
1.1 root 303:
1.1.1.2 root 304: (define_insn "truncsiqi2"
305: [(set (match_operand:QI 0 "general_operand" "=g")
306: (truncate:QI (match_operand:SI 1 "general_operand" "g")))]
1.1 root 307: ""
1.1.1.2 root 308: "cvtlb %1,%0")
1.1 root 309:
1.1.1.2 root 310: (define_insn "truncsihi2"
311: [(set (match_operand:HI 0 "general_operand" "=g")
312: (truncate:HI (match_operand:SI 1 "general_operand" "g")))]
1.1 root 313: ""
1.1.1.2 root 314: "cvtlw %1,%0")
1.1 root 315:
316: (define_insn "trunchiqi2"
317: [(set (match_operand:QI 0 "general_operand" "=g")
318: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
319: ""
320: "cvtwb %1,%0")
321:
322: (define_insn "extendhisi2"
323: [(set (match_operand:SI 0 "general_operand" "=g")
324: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
325: ""
326: "cvtwl %1,%0")
327:
1.1.1.2 root 328: (define_insn "extendqihi2"
329: [(set (match_operand:HI 0 "general_operand" "=g")
330: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1.1 root 331: ""
1.1.1.2 root 332: "cvtbw %1,%0")
1.1 root 333:
1.1.1.2 root 334: (define_insn "extendqisi2"
335: [(set (match_operand:SI 0 "general_operand" "=g")
336: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
337: ""
338: "cvtbl %1,%0")
339:
340: (define_insn "extendsfdf2"
1.1 root 341: [(set (match_operand:DF 0 "general_operand" "=g")
1.1.1.2 root 342: (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
1.1 root 343: ""
1.1.1.3 root 344: "cvtf%# %1,%0")
1.1 root 345:
1.1.1.2 root 346: (define_insn "truncdfsf2"
347: [(set (match_operand:SF 0 "general_operand" "=g")
348: (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
1.1 root 349: ""
1.1.1.3 root 350: "cvt%#f %1,%0")
1.1 root 351:
1.1.1.2 root 352: (define_insn "zero_extendhisi2"
353: [(set (match_operand:SI 0 "general_operand" "=g")
354: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
355: ""
356: "movzwl %1,%0")
357:
358: (define_insn "zero_extendqihi2"
1.1 root 359: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 360: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1.1 root 361: ""
1.1.1.2 root 362: "movzbw %1,%0")
363:
364: (define_insn "zero_extendqisi2"
365: [(set (match_operand:SI 0 "general_operand" "=g")
366: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
367: ""
368: "movzbl %1,%0")
369:
370: ;; Fix-to-float conversion insns.
371: ;; Note that the ones that start with SImode come first.
372: ;; That is so that an operand that is a CONST_INT
373: ;; (and therefore lacks a specific machine mode).
374: ;; will be recognized as SImode (which is always valid)
375: ;; rather than as QImode or HImode.
1.1 root 376:
377: (define_insn "floatsisf2"
378: [(set (match_operand:SF 0 "general_operand" "=g")
379: (float:SF (match_operand:SI 1 "general_operand" "g")))]
380: ""
381: "cvtlf %1,%0")
382:
383: (define_insn "floatsidf2"
384: [(set (match_operand:DF 0 "general_operand" "=g")
385: (float:DF (match_operand:SI 1 "general_operand" "g")))]
386: ""
1.1.1.3 root 387: "cvtl%# %1,%0")
1.1 root 388:
1.1.1.2 root 389: (define_insn "floathisf2"
390: [(set (match_operand:SF 0 "general_operand" "=g")
391: (float:SF (match_operand:HI 1 "general_operand" "g")))]
1.1 root 392: ""
1.1.1.2 root 393: "cvtwf %1,%0")
1.1 root 394:
1.1.1.2 root 395: (define_insn "floathidf2"
396: [(set (match_operand:DF 0 "general_operand" "=g")
397: (float:DF (match_operand:HI 1 "general_operand" "g")))]
1.1 root 398: ""
1.1.1.3 root 399: "cvtw%# %1,%0")
1.1 root 400:
1.1.1.2 root 401: (define_insn "floatqisf2"
402: [(set (match_operand:SF 0 "general_operand" "=g")
403: (float:SF (match_operand:QI 1 "general_operand" "g")))]
1.1 root 404: ""
1.1.1.2 root 405: "cvtbf %1,%0")
1.1 root 406:
1.1.1.2 root 407: (define_insn "floatqidf2"
1.1 root 408: [(set (match_operand:DF 0 "general_operand" "=g")
1.1.1.2 root 409: (float:DF (match_operand:QI 1 "general_operand" "g")))]
1.1 root 410: ""
1.1.1.3 root 411: "cvtb%# %1,%0")
1.1.1.2 root 412:
413: ;; Float-to-fix conversion insns.
1.1 root 414:
1.1.1.2 root 415: (define_insn "fix_truncsfqi2"
1.1 root 416: [(set (match_operand:QI 0 "general_operand" "=g")
1.1.1.2 root 417: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 418: ""
1.1.1.2 root 419: "cvtfb %1,%0")
1.1 root 420:
1.1.1.2 root 421: (define_insn "fix_truncsfhi2"
1.1 root 422: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 423: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 424: ""
1.1.1.2 root 425: "cvtfw %1,%0")
1.1 root 426:
1.1.1.2 root 427: (define_insn "fix_truncsfsi2"
1.1 root 428: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 429: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 430: ""
1.1.1.2 root 431: "cvtfl %1,%0")
1.1 root 432:
1.1.1.2 root 433: (define_insn "fix_truncdfqi2"
434: [(set (match_operand:QI 0 "general_operand" "=g")
435: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 436: ""
1.1.1.8 root 437: "cvt%#b %1,%0")
1.1 root 438:
1.1.1.2 root 439: (define_insn "fix_truncdfhi2"
1.1 root 440: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 441: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 442: ""
1.1.1.3 root 443: "cvt%#w %1,%0")
1.1 root 444:
1.1.1.2 root 445: (define_insn "fix_truncdfsi2"
1.1 root 446: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 447: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 448: ""
1.1.1.3 root 449: "cvt%#l %1,%0")
1.1 root 450:
451: ;;- All kinds of add instructions.
452:
453: (define_insn "adddf3"
454: [(set (match_operand:DF 0 "general_operand" "=g")
455: (plus:DF (match_operand:DF 1 "general_operand" "gF")
456: (match_operand:DF 2 "general_operand" "gF")))]
457: ""
458: "*
459: {
460: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 461: return \"add%#2 %2,%0\";
1.1 root 462: if (rtx_equal_p (operands[0], operands[2]))
1.1.1.3 root 463: return \"add%#2 %1,%0\";
464: return \"add%#3 %1,%2,%0\";
1.1 root 465: }")
466:
467: (define_insn "addsf3"
468: [(set (match_operand:SF 0 "general_operand" "=g")
469: (plus:SF (match_operand:SF 1 "general_operand" "gF")
470: (match_operand:SF 2 "general_operand" "gF")))]
471: ""
472: "*
473: {
474: if (rtx_equal_p (operands[0], operands[1]))
475: return \"addf2 %2,%0\";
476: if (rtx_equal_p (operands[0], operands[2]))
477: return \"addf2 %1,%0\";
478: return \"addf3 %1,%2,%0\";
479: }")
480:
481: (define_insn "addsi3"
482: [(set (match_operand:SI 0 "general_operand" "=g")
483: (plus:SI (match_operand:SI 1 "general_operand" "g")
484: (match_operand:SI 2 "general_operand" "g")))]
485: ""
486: "*
487: {
488: if (rtx_equal_p (operands[0], operands[1]))
489: {
490: if (operands[2] == const1_rtx)
491: return \"incl %0\";
1.1.1.2 root 492: if (GET_CODE (operands[2]) == CONST_INT
493: && INTVAL (operands[2]) == -1)
1.1 root 494: return \"decl %0\";
495: if (GET_CODE (operands[2]) == CONST_INT
496: && (unsigned) (- INTVAL (operands[2])) < 64)
497: return \"subl2 $%n2,%0\";
1.1.1.8 root 498: if (GET_CODE (operands[2]) == CONST_INT
499: && (unsigned) INTVAL (operands[2]) >= 64
500: && GET_CODE (operands[1]) == REG)
501: return \"movab %c2(%1),%0\";
1.1 root 502: return \"addl2 %2,%0\";
503: }
504: if (rtx_equal_p (operands[0], operands[2]))
505: return \"addl2 %1,%0\";
506: if (GET_CODE (operands[2]) == CONST_INT
1.1.1.8 root 507: && (unsigned) (- INTVAL (operands[2])) < 64)
508: return \"subl3 $%n2,%1,%0\";
509: if (GET_CODE (operands[2]) == CONST_INT
510: && (unsigned) INTVAL (operands[2]) >= 64
1.1 root 511: && GET_CODE (operands[1]) == REG)
512: {
513: if (push_operand (operands[0], SImode))
1.1.1.8 root 514: return \"pushab %c2(%1)\";
1.1 root 515: return \"movab %c2(%1),%0\";
516: }
517: return \"addl3 %1,%2,%0\";
518: }")
519:
520: (define_insn "addhi3"
521: [(set (match_operand:HI 0 "general_operand" "=g")
522: (plus:HI (match_operand:HI 1 "general_operand" "g")
523: (match_operand:HI 2 "general_operand" "g")))]
524: ""
525: "*
526: {
527: if (rtx_equal_p (operands[0], operands[1]))
528: {
529: if (operands[2] == const1_rtx)
530: return \"incw %0\";
531: if (GET_CODE (operands[1]) == CONST_INT
532: && INTVAL (operands[1]) == -1)
533: return \"decw %0\";
534: if (GET_CODE (operands[2]) == CONST_INT
535: && (unsigned) (- INTVAL (operands[2])) < 64)
536: return \"subw2 $%n2,%0\";
537: return \"addw2 %2,%0\";
538: }
539: if (rtx_equal_p (operands[0], operands[2]))
540: return \"addw2 %1,%0\";
541: if (GET_CODE (operands[2]) == CONST_INT
542: && (unsigned) (- INTVAL (operands[2])) < 64)
543: return \"subw3 $%n2,%1,%0\";
544: return \"addw3 %1,%2,%0\";
545: }")
546:
547: (define_insn "addqi3"
548: [(set (match_operand:QI 0 "general_operand" "=g")
549: (plus:QI (match_operand:QI 1 "general_operand" "g")
550: (match_operand:QI 2 "general_operand" "g")))]
551: ""
552: "*
553: {
554: if (rtx_equal_p (operands[0], operands[1]))
555: {
556: if (operands[2] == const1_rtx)
557: return \"incb %0\";
558: if (GET_CODE (operands[1]) == CONST_INT
559: && INTVAL (operands[1]) == -1)
560: return \"decb %0\";
561: if (GET_CODE (operands[2]) == CONST_INT
562: && (unsigned) (- INTVAL (operands[2])) < 64)
563: return \"subb2 $%n2,%0\";
564: return \"addb2 %2,%0\";
565: }
566: if (rtx_equal_p (operands[0], operands[2]))
567: return \"addb2 %1,%0\";
568: if (GET_CODE (operands[2]) == CONST_INT
569: && (unsigned) (- INTVAL (operands[2])) < 64)
570: return \"subb3 $%n2,%1,%0\";
571: return \"addb3 %1,%2,%0\";
572: }")
573:
574: ;;- All kinds of subtract instructions.
575:
576: (define_insn "subdf3"
577: [(set (match_operand:DF 0 "general_operand" "=g")
578: (minus:DF (match_operand:DF 1 "general_operand" "gF")
579: (match_operand:DF 2 "general_operand" "gF")))]
580: ""
581: "*
582: {
583: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 584: return \"sub%#2 %2,%0\";
585: return \"sub%#3 %2,%1,%0\";
1.1 root 586: }")
587:
588: (define_insn "subsf3"
589: [(set (match_operand:SF 0 "general_operand" "=g")
590: (minus:SF (match_operand:SF 1 "general_operand" "gF")
591: (match_operand:SF 2 "general_operand" "gF")))]
592: ""
593: "*
594: {
595: if (rtx_equal_p (operands[0], operands[1]))
596: return \"subf2 %2,%0\";
597: return \"subf3 %2,%1,%0\";
598: }")
599:
600: (define_insn "subsi3"
601: [(set (match_operand:SI 0 "general_operand" "=g")
602: (minus:SI (match_operand:SI 1 "general_operand" "g")
603: (match_operand:SI 2 "general_operand" "g")))]
604: ""
605: "*
606: {
607: if (rtx_equal_p (operands[0], operands[1]))
608: {
609: if (operands[2] == const1_rtx)
610: return \"decl %0\";
611: return \"subl2 %2,%0\";
612: }
613: return \"subl3 %2,%1,%0\";
614: }")
615:
616: (define_insn "subhi3"
617: [(set (match_operand:HI 0 "general_operand" "=g")
618: (minus:HI (match_operand:HI 1 "general_operand" "g")
619: (match_operand:HI 2 "general_operand" "g")))]
620: ""
621: "*
622: {
623: if (rtx_equal_p (operands[0], operands[1]))
624: {
625: if (operands[2] == const1_rtx)
626: return \"decw %0\";
627: return \"subw2 %2,%0\";
628: }
629: return \"subw3 %2,%1,%0\";
630: }")
631:
632: (define_insn "subqi3"
633: [(set (match_operand:QI 0 "general_operand" "=g")
634: (minus:QI (match_operand:QI 1 "general_operand" "g")
635: (match_operand:QI 2 "general_operand" "g")))]
636: ""
637: "*
638: {
639: if (rtx_equal_p (operands[0], operands[1]))
640: {
641: if (operands[2] == const1_rtx)
642: return \"decb %0\";
643: return \"subb2 %2,%0\";
644: }
645: return \"subb3 %2,%1,%0\";
646: }")
647:
648: ;;- Multiply instructions.
649:
650: (define_insn "muldf3"
651: [(set (match_operand:DF 0 "general_operand" "=g")
652: (mult:DF (match_operand:DF 1 "general_operand" "gF")
653: (match_operand:DF 2 "general_operand" "gF")))]
654: ""
655: "*
656: {
657: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 658: return \"mul%#2 %2,%0\";
1.1 root 659: if (rtx_equal_p (operands[0], operands[2]))
1.1.1.3 root 660: return \"mul%#2 %1,%0\";
661: return \"mul%#3 %1,%2,%0\";
1.1 root 662: }")
663:
664: (define_insn "mulsf3"
665: [(set (match_operand:SF 0 "general_operand" "=g")
666: (mult:SF (match_operand:SF 1 "general_operand" "gF")
667: (match_operand:SF 2 "general_operand" "gF")))]
668: ""
669: "*
670: {
671: if (rtx_equal_p (operands[0], operands[1]))
672: return \"mulf2 %2,%0\";
673: if (rtx_equal_p (operands[0], operands[2]))
674: return \"mulf2 %1,%0\";
675: return \"mulf3 %1,%2,%0\";
676: }")
677:
678: (define_insn "mulsi3"
679: [(set (match_operand:SI 0 "general_operand" "=g")
680: (mult:SI (match_operand:SI 1 "general_operand" "g")
681: (match_operand:SI 2 "general_operand" "g")))]
682: ""
683: "*
684: {
685: if (rtx_equal_p (operands[0], operands[1]))
686: return \"mull2 %2,%0\";
687: if (rtx_equal_p (operands[0], operands[2]))
688: return \"mull2 %1,%0\";
689: return \"mull3 %1,%2,%0\";
690: }")
691:
692: (define_insn "mulhi3"
693: [(set (match_operand:HI 0 "general_operand" "=g")
694: (mult:HI (match_operand:HI 1 "general_operand" "g")
695: (match_operand:HI 2 "general_operand" "g")))]
696: ""
697: "*
698: {
699: if (rtx_equal_p (operands[0], operands[1]))
700: return \"mulw2 %2,%0\";
701: if (rtx_equal_p (operands[0], operands[2]))
702: return \"mulw2 %1,%0\";
703: return \"mulw3 %1,%2,%0\";
704: }")
705:
706: (define_insn "mulqi3"
707: [(set (match_operand:QI 0 "general_operand" "=g")
708: (mult:QI (match_operand:QI 1 "general_operand" "g")
709: (match_operand:QI 2 "general_operand" "g")))]
710: ""
711: "*
712: {
713: if (rtx_equal_p (operands[0], operands[1]))
714: return \"mulb2 %2,%0\";
715: if (rtx_equal_p (operands[0], operands[2]))
716: return \"mulb2 %1,%0\";
717: return \"mulb3 %1,%2,%0\";
718: }")
719:
720: ;;- Divide instructions.
721:
722: (define_insn "divdf3"
723: [(set (match_operand:DF 0 "general_operand" "=g")
724: (div:DF (match_operand:DF 1 "general_operand" "gF")
725: (match_operand:DF 2 "general_operand" "gF")))]
726: ""
727: "*
728: {
729: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 730: return \"div%#2 %2,%0\";
731: return \"div%#3 %2,%1,%0\";
1.1 root 732: }")
733:
734: (define_insn "divsf3"
735: [(set (match_operand:SF 0 "general_operand" "=g")
736: (div:SF (match_operand:SF 1 "general_operand" "gF")
737: (match_operand:SF 2 "general_operand" "gF")))]
738: ""
739: "*
740: {
741: if (rtx_equal_p (operands[0], operands[1]))
742: return \"divf2 %2,%0\";
743: return \"divf3 %2,%1,%0\";
744: }")
745:
746: (define_insn "divsi3"
747: [(set (match_operand:SI 0 "general_operand" "=g")
748: (div:SI (match_operand:SI 1 "general_operand" "g")
749: (match_operand:SI 2 "general_operand" "g")))]
750: ""
751: "*
752: {
753: if (rtx_equal_p (operands[0], operands[1]))
754: return \"divl2 %2,%0\";
755: return \"divl3 %2,%1,%0\";
756: }")
757:
758: (define_insn "divhi3"
759: [(set (match_operand:HI 0 "general_operand" "=g")
760: (div:HI (match_operand:HI 1 "general_operand" "g")
761: (match_operand:HI 2 "general_operand" "g")))]
762: ""
763: "*
764: {
765: if (rtx_equal_p (operands[0], operands[1]))
766: return \"divw2 %2,%0\";
767: return \"divw3 %2,%1,%0\";
768: }")
769:
770: (define_insn "divqi3"
771: [(set (match_operand:QI 0 "general_operand" "=g")
772: (div:QI (match_operand:QI 1 "general_operand" "g")
773: (match_operand:QI 2 "general_operand" "g")))]
774: ""
775: "*
776: {
777: if (rtx_equal_p (operands[0], operands[1]))
778: return \"divb2 %2,%0\";
779: return \"divb3 %2,%1,%0\";
780: }")
781:
782: ;This is left out because it is very slow;
783: ;we are better off programming around the "lack" of this insn.
784: ;(define_insn "divmoddisi4"
785: ; [(set (match_operand:SI 0 "general_operand" "=g")
786: ; (div:SI (match_operand:DI 1 "general_operand" "g")
787: ; (match_operand:SI 2 "general_operand" "g")))
788: ; (set (match_operand:SI 3 "general_operand" "=g")
789: ; (mod:SI (match_operand:DI 1 "general_operand" "g")
790: ; (match_operand:SI 2 "general_operand" "g")))]
791: ; ""
792: ; "ediv %2,%1,%0,%3")
793:
1.1.1.8 root 794: ;; Bit-and on the vax is done with a clear-bits insn.
795: (define_expand "andsi3"
796: [(set (match_operand:SI 0 "general_operand" "=g")
797: (and:SI (match_operand:SI 1 "general_operand" "g")
798: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
799: ""
800: "
801: {
802: extern rtx expand_unop ();
803: if (GET_CODE (operands[2]) == CONST_INT)
804: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
805: else
806: operands[2] = expand_unop (SImode, one_cmpl_optab, operands[2], 0, 1);
807: }")
808:
809: (define_expand "andhi3"
810: [(set (match_operand:HI 0 "general_operand" "=g")
811: (and:HI (match_operand:HI 1 "general_operand" "g")
812: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
813: ""
814: "
815: {
816: extern rtx expand_unop ();
817: rtx op = operands[2];
818: if (GET_CODE (op) == CONST_INT)
819: operands[2] = gen_rtx (CONST_INT, VOIDmode,
820: ((1 << 16) - 1) & ~INTVAL (op));
821: else
822: operands[2] = expand_unop (HImode, one_cmpl_optab, op, 0, 1);
823: }")
824:
825: (define_expand "andqi3"
826: [(set (match_operand:QI 0 "general_operand" "=g")
827: (and:QI (match_operand:QI 1 "general_operand" "g")
828: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
829: ""
830: "
831: {
832: extern rtx expand_unop ();
833: rtx op = operands[2];
834: if (GET_CODE (op) == CONST_INT)
835: operands[2] = gen_rtx (CONST_INT, VOIDmode,
836: ((1 << 8) - 1) & ~INTVAL (op));
837: else
838: operands[2] = expand_unop (QImode, one_cmpl_optab, op, 0, 1);
839: }")
840:
1.1 root 841: (define_insn "andcbsi3"
842: [(set (match_operand:SI 0 "general_operand" "=g")
843: (and:SI (match_operand:SI 1 "general_operand" "g")
844: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
845: ""
846: "*
847: {
848: if (rtx_equal_p (operands[0], operands[1]))
849: return \"bicl2 %2,%0\";
850: return \"bicl3 %2,%1,%0\";
851: }")
852:
853: (define_insn "andcbhi3"
854: [(set (match_operand:HI 0 "general_operand" "=g")
855: (and:HI (match_operand:HI 1 "general_operand" "g")
856: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
857: ""
858: "*
859: {
860: if (rtx_equal_p (operands[0], operands[1]))
861: return \"bicw2 %2,%0\";
862: return \"bicw3 %2,%1,%0\";
863: }")
864:
865: (define_insn "andcbqi3"
866: [(set (match_operand:QI 0 "general_operand" "=g")
867: (and:QI (match_operand:QI 1 "general_operand" "g")
868: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
869: ""
870: "*
871: {
872: if (rtx_equal_p (operands[0], operands[1]))
873: return \"bicb2 %2,%0\";
874: return \"bicb3 %2,%1,%0\";
875: }")
876:
877: ;; The following are needed because constant propagation can
878: ;; create them starting from the bic insn patterns above.
879:
880: (define_insn ""
881: [(set (match_operand:SI 0 "general_operand" "=g")
882: (and:SI (match_operand:SI 1 "general_operand" "g")
883: (match_operand:SI 2 "general_operand" "g")))]
884: "GET_CODE (operands[2]) == CONST_INT"
885: "*
886: { operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
887: if (rtx_equal_p (operands[1], operands[0]))
888: return \"bicl2 %2,%0\";
889: return \"bicl3 %2,%1,%0\";
890: }")
891:
892: (define_insn ""
893: [(set (match_operand:HI 0 "general_operand" "=g")
894: (and:HI (match_operand:HI 1 "general_operand" "g")
895: (match_operand:HI 2 "general_operand" "g")))]
896: "GET_CODE (operands[2]) == CONST_INT"
897: "*
898: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xffff & ~INTVAL (operands[2]));
899: if (rtx_equal_p (operands[1], operands[0]))
900: return \"bicw2 %2,%0\";
901: return \"bicw3 %2,%1,%0\";
902: }")
903:
904: (define_insn ""
905: [(set (match_operand:QI 0 "general_operand" "=g")
906: (and:QI (match_operand:QI 1 "general_operand" "g")
907: (match_operand:QI 2 "general_operand" "g")))]
908: "GET_CODE (operands[2]) == CONST_INT"
909: "*
910: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xff & ~INTVAL (operands[2]));
911: if (rtx_equal_p (operands[1], operands[0]))
912: return \"bicb2 %2,%0\";
913: return \"bicb3 %2,%1,%0\";
914: }")
915:
916: ;;- Bit set instructions.
917:
918: (define_insn "iorsi3"
919: [(set (match_operand:SI 0 "general_operand" "=g")
920: (ior:SI (match_operand:SI 1 "general_operand" "g")
921: (match_operand:SI 2 "general_operand" "g")))]
922: ""
923: "*
924: {
925: if (rtx_equal_p (operands[0], operands[1]))
926: return \"bisl2 %2,%0\";
927: if (rtx_equal_p (operands[0], operands[2]))
928: return \"bisl2 %1,%0\";
929: return \"bisl3 %2,%1,%0\";
930: }")
931:
932: (define_insn "iorhi3"
933: [(set (match_operand:HI 0 "general_operand" "=g")
934: (ior:HI (match_operand:HI 1 "general_operand" "g")
935: (match_operand:HI 2 "general_operand" "g")))]
936: ""
937: "*
938: {
939: if (rtx_equal_p (operands[0], operands[1]))
940: return \"bisw2 %2,%0\";
941: if (rtx_equal_p (operands[0], operands[2]))
942: return \"bisw2 %1,%0\";
943: return \"bisw3 %2,%1,%0\";
944: }")
945:
946: (define_insn "iorqi3"
947: [(set (match_operand:QI 0 "general_operand" "=g")
948: (ior:QI (match_operand:QI 1 "general_operand" "g")
949: (match_operand:QI 2 "general_operand" "g")))]
950: ""
951: "*
952: {
953: if (rtx_equal_p (operands[0], operands[1]))
954: return \"bisb2 %2,%0\";
955: if (rtx_equal_p (operands[0], operands[2]))
956: return \"bisb2 %1,%0\";
957: return \"bisb3 %2,%1,%0\";
958: }")
959:
960: ;;- xor instructions.
961:
962: (define_insn "xorsi3"
963: [(set (match_operand:SI 0 "general_operand" "=g")
964: (xor:SI (match_operand:SI 1 "general_operand" "g")
965: (match_operand:SI 2 "general_operand" "g")))]
966: ""
967: "*
968: {
969: if (rtx_equal_p (operands[0], operands[1]))
970: return \"xorl2 %2,%0\";
971: if (rtx_equal_p (operands[0], operands[2]))
972: return \"xorl2 %1,%0\";
973: return \"xorl3 %2,%1,%0\";
974: }")
975:
976: (define_insn "xorhi3"
977: [(set (match_operand:HI 0 "general_operand" "=g")
978: (xor:HI (match_operand:HI 1 "general_operand" "g")
979: (match_operand:HI 2 "general_operand" "g")))]
980: ""
981: "*
982: {
983: if (rtx_equal_p (operands[0], operands[1]))
984: return \"xorw2 %2,%0\";
985: if (rtx_equal_p (operands[0], operands[2]))
986: return \"xorw2 %1,%0\";
987: return \"xorw3 %2,%1,%0\";
988: }")
989:
990: (define_insn "xorqi3"
991: [(set (match_operand:QI 0 "general_operand" "=g")
992: (xor:QI (match_operand:QI 1 "general_operand" "g")
993: (match_operand:QI 2 "general_operand" "g")))]
994: ""
995: "*
996: {
997: if (rtx_equal_p (operands[0], operands[1]))
998: return \"xorb2 %2,%0\";
999: if (rtx_equal_p (operands[0], operands[2]))
1000: return \"xorb2 %1,%0\";
1001: return \"xorb3 %2,%1,%0\";
1002: }")
1003:
1004: (define_insn "negdf2"
1005: [(set (match_operand:DF 0 "general_operand" "=g")
1006: (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
1007: ""
1.1.1.3 root 1008: "mneg%# %1,%0")
1.1 root 1009:
1010: (define_insn "negsf2"
1011: [(set (match_operand:SF 0 "general_operand" "=g")
1012: (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
1013: ""
1014: "mnegf %1,%0")
1015:
1016: (define_insn "negsi2"
1017: [(set (match_operand:SI 0 "general_operand" "=g")
1018: (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1019: ""
1020: "mnegl %1,%0")
1021:
1022: (define_insn "neghi2"
1023: [(set (match_operand:HI 0 "general_operand" "=g")
1024: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1025: ""
1026: "mnegw %1,%0")
1027:
1028: (define_insn "negqi2"
1029: [(set (match_operand:QI 0 "general_operand" "=g")
1030: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1031: ""
1032: "mnegb %1,%0")
1033:
1034: (define_insn "one_cmplsi2"
1035: [(set (match_operand:SI 0 "general_operand" "=g")
1036: (not:SI (match_operand:SI 1 "general_operand" "g")))]
1037: ""
1038: "mcoml %1,%0")
1039:
1040: (define_insn "one_cmplhi2"
1041: [(set (match_operand:HI 0 "general_operand" "=g")
1042: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1043: ""
1044: "mcomw %1,%0")
1045:
1046: (define_insn "one_cmplqi2"
1047: [(set (match_operand:QI 0 "general_operand" "=g")
1048: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1049: ""
1050: "mcomb %1,%0")
1051:
1.1.1.8 root 1052: ;; Arithmetic right shift on the vax works by negating the shift count.
1053: (define_expand "ashrsi3"
1054: [(set (match_operand:SI 0 "general_operand" "=g")
1055: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1056: (match_operand:QI 2 "general_operand" "g")))]
1057: ""
1058: "
1059: {
1.1.1.9 root 1060: operands[2] = negate_rtx (QImode, operands[2]);
1.1.1.8 root 1061: }")
1062:
1.1 root 1063: (define_insn "ashlsi3"
1064: [(set (match_operand:SI 0 "general_operand" "=g")
1065: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1066: (match_operand:QI 2 "general_operand" "g")))]
1067: ""
1.1.1.2 root 1068: "*
1069: {
1070: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1071: return \"addl2 %0,%0\";
1.1.1.8 root 1072: if (GET_CODE (operands[1]) == REG
1073: && GET_CODE (operands[2]) == CONST_INT)
1074: {
1075: int i = INTVAL (operands[2]);
1076: if (i == 1)
1077: return \"addl3 %1,%1,%0\";
1078: if (i == 2)
1079: return \"moval 0[%1],%0\";
1080: if (i == 3)
1081: return \"movad 0[%1],%0\";
1082: }
1.1.1.2 root 1083: return \"ashl %2,%1,%0\";
1084: }")
1.1 root 1085:
1.1.1.8 root 1086: ;; Arithmetic right shift on the vax works by negating the shift count.
1087: (define_expand "ashrdi3"
1088: [(set (match_operand:DI 0 "general_operand" "=g")
1089: (ashift:DI (match_operand:DI 1 "general_operand" "g")
1090: (match_operand:QI 2 "general_operand" "g")))]
1091: ""
1092: "
1093: {
1.1.1.9 root 1094: operands[2] = negate_rtx (QImode, operands[2]);
1.1.1.8 root 1095: }")
1096:
1.1 root 1097: (define_insn "ashldi3"
1098: [(set (match_operand:DI 0 "general_operand" "=g")
1099: (ashift:DI (match_operand:DI 1 "general_operand" "g")
1100: (match_operand:QI 2 "general_operand" "g")))]
1101: ""
1102: "ashq %2,%1,%0")
1103:
1.1.1.8 root 1104: ;; Rotate right on the vax works by negating the shift count.
1105: (define_expand "rotrsi3"
1.1 root 1106: [(set (match_operand:SI 0 "general_operand" "=g")
1107: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1108: (match_operand:QI 2 "general_operand" "g")))]
1109: ""
1.1.1.8 root 1110: "
1111: {
1.1.1.9 root 1112: operands[2] = negate_rtx (QImode, operands[2]);
1.1.1.8 root 1113: }")
1.1 root 1114:
1.1.1.8 root 1115: (define_insn "rotlsi3"
1116: [(set (match_operand:SI 0 "general_operand" "=g")
1117: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1.1 root 1118: (match_operand:QI 2 "general_operand" "g")))]
1119: ""
1.1.1.8 root 1120: "rotl %2,%1,%0")
1.1 root 1121:
1.1.1.2 root 1122: ;This insn is probably slower than a multiply and an add.
1123: ;(define_insn ""
1124: ; [(set (match_operand:SI 0 "general_operand" "=g")
1125: ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1126: ; (match_operand:SI 2 "general_operand" "g"))
1127: ; (match_operand:SI 3 "general_operand" "g")))]
1128: ; ""
1129: ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1.1.1.4 root 1130:
1131: ;; Special cases of bit-field insns which we should
1132: ;; recognize in preference to the general case.
1133: ;; These handle aligned 8-bit and 16-bit fields,
1134: ;; which can usually be done with move instructions.
1135:
1136: (define_insn ""
1137: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro")
1138: (match_operand:SI 1 "immediate_operand" "i")
1139: (match_operand:SI 2 "immediate_operand" "i"))
1140: (match_operand:SI 3 "general_operand" "g"))]
1141: "GET_CODE (operands[1]) == CONST_INT
1142: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1143: && GET_CODE (operands[2]) == CONST_INT
1144: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1145: && (GET_CODE (operands[0]) == REG
1146: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1147: "*
1148: {
1149: if (REG_P (operands[0]))
1150: {
1151: if (INTVAL (operands[2]) != 0)
1152: return \"insv %3,%2,%1,%0\";
1153: }
1154: else
1155: operands[0]
1156: = adj_offsetable_operand (operands[0], INTVAL (operands[2]) / 8);
1157:
1158: if (INTVAL (operands[1]) == 8)
1159: return \"movb %3,%0\";
1160: return \"movw %3,%0\";
1161: }")
1162:
1163: (define_insn ""
1164: [(set (match_operand:SI 0 "general_operand" "=&g")
1165: (zero_extract:SI (match_operand:SI 1 "general_operand" "ro")
1166: (match_operand:SI 2 "immediate_operand" "i")
1167: (match_operand:SI 3 "immediate_operand" "i")))]
1168: "GET_CODE (operands[2]) == CONST_INT
1169: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1170: && GET_CODE (operands[3]) == CONST_INT
1171: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1172: && (GET_CODE (operands[1]) == REG
1173: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1174: "*
1175: {
1176: if (REG_P (operands[1]))
1177: {
1178: if (INTVAL (operands[3]) != 0)
1179: return \"extzv %3,%2,%1,%0\";
1180: }
1181: else
1182: operands[1]
1183: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8);
1184:
1185: if (INTVAL (operands[2]) == 8)
1186: return \"movzbl %1,%0\";
1187: return \"movzwl %1,%0\";
1188: }")
1189:
1190: (define_insn ""
1191: [(set (match_operand:SI 0 "general_operand" "=g")
1192: (sign_extract:SI (match_operand:SI 1 "general_operand" "ro")
1193: (match_operand:SI 2 "immediate_operand" "i")
1194: (match_operand:SI 3 "immediate_operand" "i")))]
1195: "GET_CODE (operands[2]) == CONST_INT
1196: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1197: && GET_CODE (operands[3]) == CONST_INT
1198: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1199: && (GET_CODE (operands[1]) == REG
1200: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1201: "*
1202: {
1203: if (REG_P (operands[1]))
1204: {
1205: if (INTVAL (operands[3]) != 0)
1206: return \"extv %3,%2,%1,%0\";
1207: }
1208: else
1209: operands[1]
1210: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8);
1211:
1212: if (INTVAL (operands[2]) == 8)
1213: return \"cvtbl %1,%0\";
1214: return \"cvtwl %1,%0\";
1215: }")
1216:
1217: ;; Register-only SImode cases of bit-field insns.
1.1 root 1218:
1219: (define_insn ""
1220: [(set (cc0)
1221: (minus
1.1.1.4 root 1222: (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1.1 root 1223: (match_operand:SI 1 "general_operand" "g")
1224: (match_operand:SI 2 "general_operand" "g"))
1225: (match_operand:SI 3 "general_operand" "g")))]
1226: ""
1227: "cmpv %2,%1,%0,%3")
1228:
1229: (define_insn ""
1230: [(set (cc0)
1231: (minus
1.1.1.4 root 1232: (zero_extract:SI (match_operand:SI 0 "general_operand" "r")
1.1 root 1233: (match_operand:SI 1 "general_operand" "g")
1234: (match_operand:SI 2 "general_operand" "g"))
1235: (match_operand:SI 3 "general_operand" "g")))]
1236: ""
1237: "cmpzv %2,%1,%0,%3")
1238:
1.1.1.4 root 1239: (define_insn ""
1.1 root 1240: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1241: (sign_extract:SI (match_operand:SI 1 "general_operand" "r")
1.1 root 1242: (match_operand:SI 2 "general_operand" "g")
1243: (match_operand:SI 3 "general_operand" "g")))]
1244: ""
1245: "extv %3,%2,%1,%0")
1246:
1.1.1.4 root 1247: (define_insn ""
1.1 root 1248: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1249: (zero_extract:SI (match_operand:SI 1 "general_operand" "r")
1.1 root 1250: (match_operand:SI 2 "general_operand" "g")
1251: (match_operand:SI 3 "general_operand" "g")))]
1252: ""
1253: "extzv %3,%2,%1,%0")
1254:
1.1.1.4 root 1255: ;; Non-register cases.
1256: ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1257: ;; don't match these (and therefore match the cases above instead).
1258:
1.1 root 1259: (define_insn ""
1.1.1.4 root 1260: [(set (cc0)
1261: (minus
1262: (sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1263: (match_operand:SI 1 "general_operand" "g")
1264: (match_operand:SI 2 "general_operand" "g"))
1265: (match_operand:SI 3 "general_operand" "g")))]
1266: ""
1267: "cmpv %2,%1,%0,%3")
1268:
1269: (define_insn ""
1270: [(set (cc0)
1271: (minus
1272: (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1273: (match_operand:SI 1 "general_operand" "g")
1274: (match_operand:SI 2 "general_operand" "g"))
1275: (match_operand:SI 3 "general_operand" "g")))]
1276: ""
1277: "cmpzv %2,%1,%0,%3")
1278:
1279: (define_insn "extv"
1.1 root 1280: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1281: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1.1 root 1282: (match_operand:SI 2 "general_operand" "g")
1283: (match_operand:SI 3 "general_operand" "g")))]
1284: ""
1285: "extv %3,%2,%1,%0")
1286:
1.1.1.4 root 1287: (define_insn "extzv"
1.1 root 1288: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1289: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1.1 root 1290: (match_operand:SI 2 "general_operand" "g")
1291: (match_operand:SI 3 "general_operand" "g")))]
1292: ""
1293: "extzv %3,%2,%1,%0")
1294:
1295: (define_insn "insv"
1.1.1.2 root 1296: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1.1 root 1297: (match_operand:SI 1 "general_operand" "g")
1298: (match_operand:SI 2 "general_operand" "g"))
1299: (match_operand:SI 3 "general_operand" "g"))]
1300: ""
1301: "insv %3,%2,%1,%0")
1302:
1303: (define_insn ""
1.1.1.2 root 1304: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1.1 root 1305: (match_operand:SI 1 "general_operand" "g")
1306: (match_operand:SI 2 "general_operand" "g"))
1307: (match_operand:SI 3 "general_operand" "g"))]
1308: ""
1309: "insv %3,%2,%1,%0")
1310:
1311: (define_insn "jump"
1312: [(set (pc)
1313: (label_ref (match_operand 0 "" "")))]
1314: ""
1315: "jbr %l0")
1316:
1317: (define_insn "beq"
1318: [(set (pc)
1319: (if_then_else (eq (cc0)
1320: (const_int 0))
1321: (label_ref (match_operand 0 "" ""))
1322: (pc)))]
1323: ""
1324: "jeql %l0")
1325:
1326: (define_insn "bne"
1327: [(set (pc)
1328: (if_then_else (ne (cc0)
1329: (const_int 0))
1330: (label_ref (match_operand 0 "" ""))
1331: (pc)))]
1332: ""
1333: "jneq %l0")
1334:
1335: (define_insn "bgt"
1336: [(set (pc)
1337: (if_then_else (gt (cc0)
1338: (const_int 0))
1339: (label_ref (match_operand 0 "" ""))
1340: (pc)))]
1341: ""
1342: "jgtr %l0")
1343:
1344: (define_insn "bgtu"
1345: [(set (pc)
1346: (if_then_else (gtu (cc0)
1347: (const_int 0))
1348: (label_ref (match_operand 0 "" ""))
1349: (pc)))]
1350: ""
1351: "jgtru %l0")
1352:
1353: (define_insn "blt"
1354: [(set (pc)
1355: (if_then_else (lt (cc0)
1356: (const_int 0))
1357: (label_ref (match_operand 0 "" ""))
1358: (pc)))]
1359: ""
1360: "jlss %l0")
1361:
1362: (define_insn "bltu"
1363: [(set (pc)
1364: (if_then_else (ltu (cc0)
1365: (const_int 0))
1366: (label_ref (match_operand 0 "" ""))
1367: (pc)))]
1368: ""
1369: "jlssu %l0")
1370:
1371: (define_insn "bge"
1372: [(set (pc)
1373: (if_then_else (ge (cc0)
1374: (const_int 0))
1375: (label_ref (match_operand 0 "" ""))
1376: (pc)))]
1377: ""
1378: "jgeq %l0")
1379:
1380: (define_insn "bgeu"
1381: [(set (pc)
1382: (if_then_else (geu (cc0)
1383: (const_int 0))
1384: (label_ref (match_operand 0 "" ""))
1385: (pc)))]
1386: ""
1387: "jgequ %l0")
1388:
1389: (define_insn "ble"
1390: [(set (pc)
1391: (if_then_else (le (cc0)
1392: (const_int 0))
1393: (label_ref (match_operand 0 "" ""))
1394: (pc)))]
1395: ""
1396: "jleq %l0")
1397:
1398: (define_insn "bleu"
1399: [(set (pc)
1400: (if_then_else (leu (cc0)
1401: (const_int 0))
1402: (label_ref (match_operand 0 "" ""))
1403: (pc)))]
1404: ""
1405: "jlequ %l0")
1406:
1407: (define_insn ""
1408: [(set (pc)
1409: (if_then_else (eq (cc0)
1410: (const_int 0))
1411: (pc)
1412: (label_ref (match_operand 0 "" ""))))]
1413: ""
1414: "jneq %l0")
1415:
1416: (define_insn ""
1417: [(set (pc)
1418: (if_then_else (ne (cc0)
1419: (const_int 0))
1420: (pc)
1421: (label_ref (match_operand 0 "" ""))))]
1422: ""
1423: "jeql %l0")
1424:
1425: (define_insn ""
1426: [(set (pc)
1427: (if_then_else (gt (cc0)
1428: (const_int 0))
1429: (pc)
1430: (label_ref (match_operand 0 "" ""))))]
1431: ""
1432: "jleq %l0")
1433:
1434: (define_insn ""
1435: [(set (pc)
1436: (if_then_else (gtu (cc0)
1437: (const_int 0))
1438: (pc)
1439: (label_ref (match_operand 0 "" ""))))]
1440: ""
1441: "jlequ %l0")
1442:
1443: (define_insn ""
1444: [(set (pc)
1445: (if_then_else (lt (cc0)
1446: (const_int 0))
1447: (pc)
1448: (label_ref (match_operand 0 "" ""))))]
1449: ""
1450: "jgeq %l0")
1451:
1452: (define_insn ""
1453: [(set (pc)
1454: (if_then_else (ltu (cc0)
1455: (const_int 0))
1456: (pc)
1457: (label_ref (match_operand 0 "" ""))))]
1458: ""
1459: "jgequ %l0")
1460:
1461: (define_insn ""
1462: [(set (pc)
1463: (if_then_else (ge (cc0)
1464: (const_int 0))
1465: (pc)
1466: (label_ref (match_operand 0 "" ""))))]
1467: ""
1468: "jlss %l0")
1469:
1470: (define_insn ""
1471: [(set (pc)
1472: (if_then_else (geu (cc0)
1473: (const_int 0))
1474: (pc)
1475: (label_ref (match_operand 0 "" ""))))]
1476: ""
1477: "jlssu %l0")
1478:
1479: (define_insn ""
1480: [(set (pc)
1481: (if_then_else (le (cc0)
1482: (const_int 0))
1483: (pc)
1484: (label_ref (match_operand 0 "" ""))))]
1485: ""
1486: "jgtr %l0")
1487:
1488: (define_insn ""
1489: [(set (pc)
1490: (if_then_else (leu (cc0)
1491: (const_int 0))
1492: (pc)
1493: (label_ref (match_operand 0 "" ""))))]
1494: ""
1495: "jgtru %l0")
1496:
1497: ;; Recognize jbs and jbc instructions.
1498:
1499: (define_insn ""
1500: [(set (pc)
1501: (if_then_else
1502: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1503: (const_int 1)
1504: (match_operand:SI 1 "general_operand" "g"))
1505: (const_int 0))
1506: (label_ref (match_operand 2 "" ""))
1507: (pc)))]
1508: ""
1509: "jbs %1,%0,%l2")
1510:
1511: (define_insn ""
1512: [(set (pc)
1513: (if_then_else
1514: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1515: (const_int 1)
1516: (match_operand:SI 1 "general_operand" "g"))
1517: (const_int 0))
1518: (label_ref (match_operand 2 "" ""))
1519: (pc)))]
1520: ""
1521: "jbc %1,%0,%l2")
1522:
1523: (define_insn ""
1524: [(set (pc)
1525: (if_then_else
1526: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1527: (const_int 1)
1528: (match_operand:SI 1 "general_operand" "g"))
1529: (const_int 0))
1530: (pc)
1531: (label_ref (match_operand 2 "" ""))))]
1532: ""
1533: "jbc %1,%0,%l2")
1534:
1535: (define_insn ""
1536: [(set (pc)
1537: (if_then_else
1538: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1539: (const_int 1)
1540: (match_operand:SI 1 "general_operand" "g"))
1541: (const_int 0))
1542: (pc)
1543: (label_ref (match_operand 2 "" ""))))]
1544: ""
1545: "jbs %1,%0,%l2")
1546:
1547: (define_insn ""
1548: [(set (pc)
1549: (if_then_else
1550: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1551: (const_int 1)
1552: (match_operand:SI 1 "general_operand" "g"))
1553: (const_int 0))
1554: (label_ref (match_operand 2 "" ""))
1555: (pc)))]
1.1.1.2 root 1556: "GET_CODE (operands[0]) != MEM
1557: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1558: "jbs %1,%0,%l2")
1559:
1560: (define_insn ""
1561: [(set (pc)
1562: (if_then_else
1563: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1564: (const_int 1)
1565: (match_operand:SI 1 "general_operand" "g"))
1566: (const_int 0))
1567: (label_ref (match_operand 2 "" ""))
1568: (pc)))]
1.1.1.2 root 1569: "GET_CODE (operands[0]) != MEM
1570: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1571: "jbc %1,%0,%l2")
1572:
1573: (define_insn ""
1574: [(set (pc)
1575: (if_then_else
1.1.1.2 root 1576: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1577: (match_operand:SI 1 "general_operand" "g"))
1578: (const_int 0))
1579: (pc)
1580: (label_ref (match_operand 2 "" ""))))]
1581: "GET_CODE (operands[1]) == CONST_INT
1582: && exact_log2 (INTVAL (operands[1])) >= 0
1583: && (GET_CODE (operands[0]) != MEM
1584: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1585: "*
1586: {
1587: operands[1]
1588: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1589: return \"jbs %1,%0,%l2\";
1590: }")
1591:
1592: (define_insn ""
1593: [(set (pc)
1594: (if_then_else
1595: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1596: (match_operand:SI 1 "general_operand" "g"))
1597: (const_int 0))
1598: (label_ref (match_operand 2 "" ""))
1599: (pc)))]
1600: "GET_CODE (operands[1]) == CONST_INT
1601: && exact_log2 (INTVAL (operands[1])) >= 0
1602: && (GET_CODE (operands[0]) != MEM
1603: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1604: "*
1605: {
1606: operands[1]
1607: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1608: return \"jbc %1,%0,%l2\";
1609: }")
1610:
1611: (define_insn ""
1612: [(set (pc)
1613: (if_then_else
1614: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1615: (match_operand:SI 1 "general_operand" "g"))
1616: (const_int 0))
1617: (pc)
1618: (label_ref (match_operand 2 "" ""))))]
1619: "GET_CODE (operands[1]) == CONST_INT
1620: && exact_log2 (INTVAL (operands[1])) >= 0
1621: && (GET_CODE (operands[0]) != MEM
1622: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1623: "*
1624: {
1625: operands[1]
1626: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1627: return \"jbc %1,%0,%l2\";
1628: }")
1629:
1630: (define_insn ""
1631: [(set (pc)
1632: (if_then_else
1633: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1634: (match_operand:SI 1 "general_operand" "g"))
1635: (const_int 0))
1636: (label_ref (match_operand 2 "" ""))
1637: (pc)))]
1638: "GET_CODE (operands[1]) == CONST_INT
1639: && exact_log2 (INTVAL (operands[1])) >= 0
1640: && (GET_CODE (operands[0]) != MEM
1641: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1642: "*
1643: {
1644: operands[1]
1645: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1646: return \"jbs %1,%0,%l2\";
1647: }")
1648:
1649: (define_insn ""
1650: [(set (pc)
1651: (if_then_else
1.1 root 1652: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1653: (const_int 1)
1654: (match_operand:SI 1 "general_operand" "g"))
1655: (const_int 0))
1656: (pc)
1657: (label_ref (match_operand 2 "" ""))))]
1.1.1.2 root 1658: "GET_CODE (operands[0]) != MEM
1659: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1660: "jbc %1,%0,%l2")
1661:
1662: (define_insn ""
1663: [(set (pc)
1664: (if_then_else
1665: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1666: (const_int 1)
1667: (match_operand:SI 1 "general_operand" "g"))
1668: (const_int 0))
1669: (pc)
1670: (label_ref (match_operand 2 "" ""))))]
1.1.1.2 root 1671: "GET_CODE (operands[0]) != MEM
1672: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1673: "jbs %1,%0,%l2")
1674:
1675: (define_insn ""
1676: [(set (pc)
1677: (if_then_else
1678: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1679: (const_int 1))
1680: (const_int 0))
1681: (label_ref (match_operand 1 "" ""))
1682: (pc)))]
1.1.1.2 root 1683: "GET_CODE (operands[0]) != MEM
1684: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1685: "jlbs %0,%l1")
1686:
1687: (define_insn ""
1688: [(set (pc)
1689: (if_then_else
1690: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1691: (const_int 1))
1692: (const_int 0))
1693: (label_ref (match_operand 1 "" ""))
1694: (pc)))]
1.1.1.2 root 1695: "GET_CODE (operands[0]) != MEM
1696: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1697: "jlbc %0,%l1")
1698:
1699: (define_insn ""
1700: [(set (pc)
1701: (if_then_else
1702: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1703: (const_int 1))
1704: (const_int 0))
1705: (pc)
1706: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1707: "GET_CODE (operands[0]) != MEM
1708: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1709: "jlbc %0,%l1")
1710:
1711: (define_insn ""
1712: [(set (pc)
1713: (if_then_else
1714: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1715: (const_int 1))
1716: (const_int 0))
1717: (pc)
1718: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1719: "GET_CODE (operands[0]) != MEM
1720: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1721: "jlbs %0,%l1")
1722:
1723: ;; These four entries allow a jlbc or jlbs to be made
1724: ;; by combination with a bic.
1725: (define_insn ""
1726: [(set (pc)
1727: (if_then_else
1728: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1729: (not:SI (const_int -2)))
1730: (const_int 0))
1731: (label_ref (match_operand 1 "" ""))
1732: (pc)))]
1.1.1.2 root 1733: "GET_CODE (operands[0]) != MEM
1734: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1735: "jlbs %0,%l1")
1736:
1737: (define_insn ""
1738: [(set (pc)
1739: (if_then_else
1740: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1741: (not:SI (const_int -2)))
1742: (const_int 0))
1743: (label_ref (match_operand 1 "" ""))
1744: (pc)))]
1.1.1.2 root 1745: "GET_CODE (operands[0]) != MEM
1746: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1747: "jlbc %0,%l1")
1748:
1749: (define_insn ""
1750: [(set (pc)
1751: (if_then_else
1752: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1753: (not:SI (const_int -2)))
1754: (const_int 0))
1755: (pc)
1756: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1757: "GET_CODE (operands[0]) != MEM
1758: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1759: "jlbc %0,%l1")
1760:
1761: (define_insn ""
1762: [(set (pc)
1763: (if_then_else
1764: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1765: (not:SI (const_int -2)))
1766: (const_int 0))
1767: (pc)
1768: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1769: "GET_CODE (operands[0]) != MEM
1770: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1771: "jlbs %0,%l1")
1772:
1773: ;; Subtract-and-jump and Add-and-jump insns.
1774: ;; These are not used when output is for the Unix assembler
1775: ;; because it does not know how to modify them to reach far.
1776:
1777: ;; Normal sob insns.
1778:
1779: (define_insn ""
1780: [(set (pc)
1781: (if_then_else
1.1.1.8 root 1782: (gt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1783: (const_int -1))
1.1 root 1784: (const_int 0))
1785: (label_ref (match_operand 1 "" ""))
1786: (pc)))
1787: (set (match_dup 0)
1.1.1.2 root 1788: (plus:SI (match_dup 0)
1789: (const_int -1)))]
1.1 root 1790: "!TARGET_UNIX_ASM"
1791: "jsobgtr %0,%l1")
1792:
1793: (define_insn ""
1794: [(set (pc)
1795: (if_then_else
1.1.1.8 root 1796: (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")
1797: (const_int -1))
1.1 root 1798: (const_int 0))
1799: (label_ref (match_operand 1 "" ""))
1800: (pc)))
1801: (set (match_dup 0)
1.1.1.2 root 1802: (plus:SI (match_dup 0)
1803: (const_int -1)))]
1.1 root 1804: "!TARGET_UNIX_ASM"
1805: "jsobgeq %0,%l1")
1806:
1807: ;; Reversed sob insns.
1808:
1809: (define_insn ""
1810: [(set (pc)
1811: (if_then_else
1.1.1.8 root 1812: (le (plus:SI (match_operand:SI 0 "general_operand" "+g")
1813: (const_int -1))
1.1 root 1814: (const_int 0))
1815: (pc)
1816: (label_ref (match_operand 1 "" ""))))
1817: (set (match_dup 0)
1.1.1.2 root 1818: (plus:SI (match_dup 0)
1819: (const_int -1)))]
1.1 root 1820: "!TARGET_UNIX_ASM"
1821: "jsobgtr %0,%l1")
1822:
1823: (define_insn ""
1824: [(set (pc)
1825: (if_then_else
1.1.1.8 root 1826: (lt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1827: (const_int -1))
1.1 root 1828: (const_int 0))
1829: (pc)
1830: (label_ref (match_operand 1 "" ""))))
1831: (set (match_dup 0)
1.1.1.2 root 1832: (plus:SI (match_dup 0)
1833: (const_int -1)))]
1.1 root 1834: "!TARGET_UNIX_ASM"
1835: "jsobgeq %0,%l1")
1836:
1837: ;; Normal aob insns.
1838: (define_insn ""
1839: [(set (pc)
1840: (if_then_else
1841: (lt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1842: (const_int 1))
1843: (match_operand:SI 1 "general_operand" "g"))
1844: (const_int 0))
1845: (label_ref (match_operand 2 "" ""))
1846: (pc)))
1847: (set (match_dup 0)
1848: (plus:SI (match_dup 0)
1849: (const_int 1)))]
1850: "!TARGET_UNIX_ASM"
1851: "jaoblss %1,%0,%l2")
1852:
1853: (define_insn ""
1854: [(set (pc)
1855: (if_then_else
1856: (le (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1857: (const_int 1))
1858: (match_operand:SI 1 "general_operand" "g"))
1859: (const_int 0))
1860: (label_ref (match_operand 2 "" ""))
1861: (pc)))
1862: (set (match_dup 0)
1863: (plus:SI (match_dup 0)
1864: (const_int 1)))]
1865: "!TARGET_UNIX_ASM"
1866: "jaobleq %1,%0,%l2")
1867:
1868: ;; Reverse aob insns.
1869: (define_insn ""
1870: [(set (pc)
1871: (if_then_else
1872: (ge (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1873: (const_int 1))
1874: (match_operand:SI 1 "general_operand" "g"))
1875: (const_int 0))
1876: (pc)
1877: (label_ref (match_operand 2 "" ""))))
1878: (set (match_dup 0)
1879: (plus:SI (match_dup 0)
1880: (const_int 1)))]
1881: "!TARGET_UNIX_ASM"
1882: "jaoblss %1,%0,%l2")
1883:
1884: (define_insn ""
1885: [(set (pc)
1886: (if_then_else
1887: (gt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1888: (const_int 1))
1889: (match_operand:SI 1 "general_operand" "g"))
1890: (const_int 0))
1891: (pc)
1892: (label_ref (match_operand 2 "" ""))))
1893: (set (match_dup 0)
1894: (plus:SI (match_dup 0)
1895: (const_int 1)))]
1896: "!TARGET_UNIX_ASM"
1897: "jaobleq %1,%0,%l2")
1.1.1.5 root 1898:
1899: ;; Something like a sob insn, but compares against -1.
1900: ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1901:
1902: (define_insn ""
1903: [(set (pc)
1904: (if_then_else
1905: (ne (minus (plus:SI (match_operand:SI 0 "general_operand" "g")
1906: (const_int -1))
1907: (const_int -1))
1908: (const_int 0))
1909: (label_ref (match_operand 1 "" ""))
1910: (pc)))
1911: (set (match_dup 0)
1912: (plus:SI (match_dup 0)
1913: (const_int -1)))]
1914: ""
1915: "decl %0\;jgequ %l1")
1.1 root 1916:
1.1.1.2 root 1917: ;; Note that operand 1 is total size of args, in bytes,
1918: ;; and what the call insn wants is the number of words.
1.1 root 1919: (define_insn "call"
1920: [(call (match_operand:QI 0 "general_operand" "g")
1921: (match_operand:QI 1 "general_operand" "g"))]
1922: ""
1.1.1.2 root 1923: "*
1.1.1.5 root 1924: if (INTVAL (operands[1]) > 255 * 4)
1925: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1926: return \"calls $0,%0\;addl2 %1,sp\";
1.1.1.2 root 1927: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);
1928: return \"calls %1,%0\";
1929: ")
1930:
1931: (define_insn "call_value"
1932: [(set (match_operand 0 "" "g")
1933: (call (match_operand:QI 1 "general_operand" "g")
1934: (match_operand:QI 2 "general_operand" "g")))]
1935: ""
1936: "*
1.1.1.7 root 1937: if (INTVAL (operands[2]) > 255 * 4)
1.1.1.6 root 1938: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1939: return \"calls $0,%1\;addl2 %2,sp\";
1.1.1.2 root 1940: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4);
1941: return \"calls %2,%1\";
1942: ")
1.1 root 1943:
1944: (define_insn "return"
1945: [(return)]
1946: ""
1947: "ret")
1948:
1949: (define_insn "casesi"
1950: [(set (pc)
1951: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
1952: (match_operand:SI 1 "general_operand" "g"))
1953: (match_operand:SI 2 "general_operand" "g"))
1.1.1.2 root 1954: (plus:SI (sign_extend:SI
1.1 root 1955: (mem:HI (plus:SI (pc)
1956: (minus:SI (match_dup 0)
1.1.1.2 root 1957: (match_dup 1)))))
1958: (label_ref:SI (match_operand 3 "" "")))
1.1 root 1959: (pc)))]
1960: ""
1961: "casel %0,%1,%2")
1962:
1.1.1.2 root 1963: ;; This used to arise from the preceding by simplification
1964: ;; if operand 1 is zero. Perhaps it is no longer necessary.
1965: (define_insn ""
1966: [(set (pc)
1967: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1968: (match_operand:SI 1 "general_operand" "g"))
1969: (plus:SI (sign_extend:SI
1970: (mem:HI (plus:SI (pc)
1971: (minus:SI (match_dup 0)
1972: (const_int 0)))))
1973: (label_ref:SI (match_operand 3 "" "")))
1974: (pc)))]
1975: ""
1976: "casel %0,$0,%1")
1977:
1.1 root 1978: ;; This arises from the preceding by simplification if operand 1 is zero.
1979: (define_insn ""
1980: [(set (pc)
1981: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1982: (match_operand:SI 1 "general_operand" "g"))
1.1.1.2 root 1983: (plus:SI (sign_extend:SI
1.1 root 1984: (mem:HI (plus:SI (pc)
1.1.1.2 root 1985: (match_dup 0))))
1986: (label_ref:SI (match_operand 3 "" "")))
1.1 root 1987: (pc)))]
1988: ""
1989: "casel %0,$0,%1")
1990:
1.1.1.11! root 1991: ;;- load or push effective address
! 1992: ;; These come after the move and add/sub patterns
! 1993: ;; because we don't want pushl $1 turned into pushad 1.
! 1994: ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
! 1995:
! 1996: (define_insn ""
! 1997: [(set (match_operand:SI 0 "general_operand" "=g")
! 1998: (match_operand:QI 1 "address_operand" "p"))]
! 1999: ""
! 2000: "*
! 2001: {
! 2002: if (push_operand (operands[0], SImode))
! 2003: return \"pushab %a1\";
! 2004: return \"movab %a1,%0\";
! 2005: }")
! 2006:
! 2007: (define_insn ""
! 2008: [(set (match_operand:SI 0 "general_operand" "=g")
! 2009: (match_operand:HI 1 "address_operand" "p"))]
! 2010: ""
! 2011: "*
! 2012: {
! 2013: if (push_operand (operands[0], SImode))
! 2014: return \"pushaw %a1\";
! 2015: return \"movaw %a1,%0\";
! 2016: }")
! 2017:
! 2018: (define_insn ""
! 2019: [(set (match_operand:SI 0 "general_operand" "=g")
! 2020: (match_operand:SI 1 "address_operand" "p"))]
! 2021: ""
! 2022: "*
! 2023: {
! 2024: if (push_operand (operands[0], SImode))
! 2025: return \"pushal %a1\";
! 2026: return \"moval %a1,%0\";
! 2027: }")
! 2028:
! 2029: (define_insn ""
! 2030: [(set (match_operand:SI 0 "general_operand" "=g")
! 2031: (match_operand:SF 1 "address_operand" "p"))]
! 2032: ""
! 2033: "*
! 2034: {
! 2035: if (push_operand (operands[0], SImode))
! 2036: return \"pushaf %a1\";
! 2037: return \"movaf %a1,%0\";
! 2038: }")
! 2039:
! 2040: (define_insn ""
! 2041: [(set (match_operand:SI 0 "general_operand" "=g")
! 2042: (match_operand:DF 1 "address_operand" "p"))]
! 2043: ""
! 2044: "*
! 2045: {
! 2046: if (push_operand (operands[0], SImode))
! 2047: return \"pushad %a1\";
! 2048: return \"movad %a1,%0\";
! 2049: }")
! 2050:
1.1.1.2 root 2051: ;; Optimize extzv ...,z; andl2 ...,z
2052: ;; with other operands constant.
2053: (define_peephole
2054: [(set (match_operand:SI 0 "general_operand" "g")
2055: (zero_extract:SI (match_operand:SI 1 "general_operand" "g")
2056: (match_operand:SI 2 "general_operand" "g")
2057: (match_operand:SI 3 "general_operand" "g")))
2058: (set (match_operand:SI 4 "general_operand" "g")
2059: (and:SI (match_dup 0)
2060: (match_operand:SI 5 "general_operand" "g")))]
2061: "GET_CODE (operands[2]) == CONST_INT
2062: && GET_CODE (operands[3]) == CONST_INT
2063: && (INTVAL (operands[2]) + INTVAL (operands[3])) == 32
2064: && GET_CODE (operands[5]) == CONST_INT
2065: && dead_or_set_p (insn, operands[0])"
2066: "*
2067: {
2068: unsigned long mask = INTVAL (operands[5]);
2069: operands[3] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[3]));
2070:
2071: if ((floor_log2 (mask) + 1) >= INTVAL (operands[2]))
2072: mask &= ((1 << INTVAL (operands[2])) - 1);
2073:
2074: operands[5] = gen_rtx (CONST_INT, VOIDmode, ~mask);
2075: if (push_operand (operands[4], SImode))
2076: {
2077: output_asm_insn (\"rotl %3,%1,%0\", operands);
2078: return \"bicl3 %5,%0,%4\";
2079: }
2080: else
2081: {
2082: output_asm_insn (\"rotl %3,%1,%4\", operands);
2083: return \"bicl2 %5,%4\";
2084: }
2085: }")
2086:
2087: ;; Optimize andl3 x,y,z; extzv z,....,z
2088:
2089: (define_peephole
2090: [(set (match_operand:SI 0 "general_operand" "g")
2091: (and:SI (match_operand:SI 1 "general_operand" "g")
2092: (match_operand:SI 2 "general_operand" "g")))
2093: (set (match_operand 3 "general_operand" "g")
2094: (zero_extract:SI (match_dup 0)
2095: (match_operand:SI 4 "general_operand" "g")
2096: (match_operand:SI 5 "general_operand" "g")))]
2097: "GET_CODE (operands[2]) == CONST_INT
2098: && GET_CODE (operands[4]) == CONST_INT
2099: && GET_CODE (operands[5]) == CONST_INT
2100: && (INTVAL (operands[4]) + INTVAL (operands[5])) == 32
2101: && dead_or_set_p (insn, operands[0])"
2102: "*
2103: {
2104: unsigned long mask = INTVAL (operands[2]);
2105:
2106: mask &= ~((1 << INTVAL (operands[5])) - 1);
2107: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~mask);
2108:
2109: operands[5] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[5]));
2110:
2111: if (rtx_equal_p (operands[0], operands[1]))
2112: output_asm_insn (\"bicl2 %2,%0\", operands);
2113: else
2114: output_asm_insn (\"bicl3 %2,%1,%0\", operands);
2115: return \"rotl %5,%0,%3\";
2116: }")
2117:
1.1 root 2118: ;;- Local variables:
2119: ;;- mode:emacs-lisp
2120: ;;- comment-start: ";;- "
2121: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2122: ;;- eval: (modify-syntax-entry ?[ "(]")
2123: ;;- eval: (modify-syntax-entry ?] ")[")
2124: ;;- eval: (modify-syntax-entry ?{ "(}")
2125: ;;- eval: (modify-syntax-entry ?} "){")
2126: ;;- End:
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