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1.1 root 1: ;;- Machine description for GNU compiler
2: ;;- Vax Version
3: ;; Copyright (C) 1987 Free Software Foundation, Inc.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is distributed in the hope that it will be useful,
8: ;; but WITHOUT ANY WARRANTY. No author or distributor
9: ;; accepts responsibility to anyone for the consequences of using it
10: ;; or for whether it serves any particular purpose or works at all,
11: ;; unless he says so in writing. Refer to the GNU CC General Public
12: ;; License for full details.
13:
14: ;; Everyone is granted permission to copy, modify and redistribute
15: ;; GNU CC, but only under the conditions described in the
16: ;; GNU CC General Public License. A copy of this license is
17: ;; supposed to have been given to you along with GNU CC so you
18: ;; can know your rights and responsibilities. It should be in a
19: ;; file named COPYING. Among other things, the copyright notice
20: ;; and this notice must be preserved on all copies.
21:
22:
23: ;;- Instruction patterns. When multiple patterns apply,
24: ;;- the first one in the file is chosen.
25: ;;-
26: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
27: ;;-
28: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29: ;;- updates for most instructions.
30:
1.1.1.2 root 31: ; tstsi is first test insn so that it is the one to match
32: ; a constant argument.
1.1 root 33:
34: (define_insn "tstsi"
35: [(set (cc0)
36: (match_operand:SI 0 "general_operand" "g"))]
37: ""
38: "tstl %0")
39:
40: (define_insn "tsthi"
41: [(set (cc0)
42: (match_operand:HI 0 "general_operand" "g"))]
43: ""
44: "tstw %0")
45:
46: (define_insn "tstqi"
47: [(set (cc0)
48: (match_operand:QI 0 "general_operand" "g"))]
49: ""
50: "tstb %0")
51:
1.1.1.2 root 52: (define_insn "tstdf"
1.1 root 53: [(set (cc0)
1.1.1.2 root 54: (match_operand:DF 0 "general_operand" "gF"))]
1.1 root 55: ""
1.1.1.3 ! root 56: "tst%# %0")
1.1 root 57:
1.1.1.2 root 58: (define_insn "tstsf"
1.1 root 59: [(set (cc0)
1.1.1.2 root 60: (match_operand:SF 0 "general_operand" "gF"))]
1.1 root 61: ""
1.1.1.2 root 62: "tstf %0")
1.1 root 63:
64: (define_insn "cmpsi"
65: [(set (cc0)
66: (minus (match_operand:SI 0 "general_operand" "g")
67: (match_operand:SI 1 "general_operand" "g")))]
68: ""
69: "cmpl %0,%1")
70:
71: (define_insn "cmphi"
72: [(set (cc0)
73: (minus (match_operand:HI 0 "general_operand" "g")
74: (match_operand:HI 1 "general_operand" "g")))]
75: ""
76: "cmpw %0,%1")
77:
78: (define_insn "cmpqi"
79: [(set (cc0)
80: (minus (match_operand:QI 0 "general_operand" "g")
81: (match_operand:QI 1 "general_operand" "g")))]
82: ""
83: "cmpb %0,%1")
84:
1.1.1.2 root 85: (define_insn "cmpdf"
86: [(set (cc0)
87: (minus (match_operand:DF 0 "general_operand" "gF")
88: (match_operand:DF 1 "general_operand" "gF")))]
89: ""
1.1.1.3 ! root 90: "cmp%# %0,%1")
1.1.1.2 root 91:
92: (define_insn "cmpsf"
93: [(set (cc0)
94: (minus (match_operand:SF 0 "general_operand" "gF")
95: (match_operand:SF 1 "general_operand" "gF")))]
96: ""
97: "cmpf %0,%1")
98:
1.1 root 99: (define_insn ""
100: [(set (cc0)
101: (and:SI (match_operand:SI 0 "general_operand" "g")
102: (match_operand:SI 1 "general_operand" "g")))]
103: ""
104: "bitl %0,%1")
105:
106: (define_insn ""
107: [(set (cc0)
108: (and:HI (match_operand:HI 0 "general_operand" "g")
109: (match_operand:HI 1 "general_operand" "g")))]
110: ""
111: "bitw %0,%1")
112:
113: (define_insn ""
114: [(set (cc0)
115: (and:QI (match_operand:QI 0 "general_operand" "g")
116: (match_operand:QI 1 "general_operand" "g")))]
117: ""
118: "bitb %0,%1")
119:
120: (define_insn "movdf"
121: [(set (match_operand:DF 0 "general_operand" "=g")
122: (match_operand:DF 1 "general_operand" "gF"))]
123: ""
124: "*
125: {
126: if (operands[1] == dconst0_rtx)
1.1.1.3 ! root 127: return \"clr%# %0\";
! 128: return \"mov%# %1,%0\";
1.1 root 129: }")
130:
131: (define_insn "movsf"
132: [(set (match_operand:SF 0 "general_operand" "=g")
133: (match_operand:SF 1 "general_operand" "gF"))]
134: ""
135: "*
136: {
137: if (operands[1] == fconst0_rtx)
138: return \"clrf %0\";
139: return \"movf %1,%0\";
140: }")
141:
1.1.1.2 root 142: ;; Some vaxes don't support this instruction.
143: ;;(define_insn "movti"
144: ;; [(set (match_operand:TI 0 "general_operand" "=g")
145: ;; (match_operand:TI 1 "general_operand" "g"))]
146: ;; ""
147: ;; "movh %1,%0")
1.1 root 148:
149: (define_insn "movdi"
150: [(set (match_operand:DI 0 "general_operand" "=g")
151: (match_operand:DI 1 "general_operand" "g"))]
152: ""
1.1.1.2 root 153: "movq %1,%0")
1.1 root 154:
155: (define_insn "movsi"
156: [(set (match_operand:SI 0 "general_operand" "=g")
157: (match_operand:SI 1 "general_operand" "g"))]
158: ""
159: "*
160: { if (operands[1] == const1_rtx
1.1.1.2 root 161: && REG_NOTES (insn)
162: && GET_MODE (REG_NOTES (insn)) == (enum machine_mode) REG_WAS_0
163: /* Make sure the insn that stored the 0 is still present. */
164: && ! XEXP (REG_NOTES (insn), 0)->volatil
165: && GET_CODE (XEXP (REG_NOTES (insn), 0)) != NOTE)
166: /* Fastest way to change a 0 to a 1. */
1.1 root 167: return \"incl %0\";
168: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
169: {
170: if (push_operand (operands[0], SImode))
171: return \"pushab %a1\";
172: return \"movab %a1,%0\";
173: }
174: if (operands[1] == const0_rtx)
175: return \"clrl %0\";
176: if (GET_CODE (operands[1]) == CONST_INT
177: && (unsigned) INTVAL (operands[1]) >= 64)
178: {
179: int i = INTVAL (operands[1]);
180: if ((unsigned)(-i) < 64)
181: {
182: operands[1] = gen_rtx (CONST_INT, VOIDmode, -i);
183: return \"mnegl %1,%0\";
184: }
185: if ((unsigned)i < 0x100)
186: return \"movzbl %1,%0\";
187: if (i >= -0x80 && i < 0)
188: return \"cvtbl %1,%0\";
189: if ((unsigned)i < 0x10000)
190: return \"movzwl %1,%0\";
191: if (i >= -0x8000 && i < 0)
192: return \"cvtwl %1,%0\";
193: }
194: if (push_operand (operands[0], SImode))
195: return \"pushl %1\";
196: return \"movl %1,%0\";
197: }")
198:
199: (define_insn "movhi"
200: [(set (match_operand:HI 0 "general_operand" "=g")
201: (match_operand:HI 1 "general_operand" "g"))]
202: ""
203: "*
204: {
205: if (operands[1] == const1_rtx
1.1.1.2 root 206: && REG_NOTES (insn)
1.1 root 207: && GET_MODE (REG_NOTES (insn)) == (enum machine_mode) REG_WAS_0)
208: return \"incw %0\";
209: if (operands[1] == const0_rtx)
210: return \"clrw %0\";
211: if (GET_CODE (operands[1]) == CONST_INT
212: && (unsigned) INTVAL (operands[1]) >= 64)
213: {
214: int i = INTVAL (operands[1]);
215: if ((unsigned)(-i) < 64)
216: {
217: operands[1] = gen_rtx (CONST_INT, VOIDmode, -i);
218: return \"mnegw %1,%0\";
219: }
220: if ((unsigned)i < 0x100)
221: return \"movzbw %1,%0\";
222: if (i >= -0x80 && i < 0)
223: return \"cvtbw %1,%0\";
224: }
225: return \"movw %1,%0\";
226: }")
227:
228: (define_insn "movqi"
229: [(set (match_operand:QI 0 "general_operand" "=g")
230: (match_operand:QI 1 "general_operand" "g"))]
231: ""
232: "*
233: {
234: if (operands[1] == const0_rtx)
235: return \"clrb %0\";
236: return \"movb %1,%0\";
237: }")
238:
239: ;; The definition of this insn does not really explain what it does,
240: ;; but it should suffice
241: ;; that anything generated as this insn will be recognized as one
242: ;; and that it won't successfully combine with anything.
243: (define_insn "movstrhi"
244: [(set (match_operand:BLK 0 "general_operand" "=g")
245: (match_operand:BLK 1 "general_operand" "g"))
246: (use (match_operand:HI 2 "general_operand" "g"))
1.1.1.2 root 247: (clobber (reg:SI 0))
248: (clobber (reg:SI 1))
249: (clobber (reg:SI 2))
250: (clobber (reg:SI 3))
251: (clobber (reg:SI 4))
252: (clobber (reg:SI 5))]
1.1 root 253: ""
254: "movc3 %2,%1,%0")
255:
256: ;;- load or push effective address
257: ;; These come after the move patterns
258: ;; because we don't want pushl $1 turned into pushad 1.
259:
260: (define_insn ""
261: [(set (match_operand:SI 0 "general_operand" "=g")
262: (match_operand:QI 1 "address_operand" "p"))]
263: ""
264: "*
265: {
266: if (push_operand (operands[0], SImode))
267: return \"pushab %a1\";
268: return \"movab %a1,%0\";
269: }")
270:
271: (define_insn ""
272: [(set (match_operand:SI 0 "general_operand" "=g")
273: (match_operand:HI 1 "address_operand" "p"))]
274: ""
275: "*
276: {
277: if (push_operand (operands[0], SImode))
278: return \"pushaw %a1\";
279: return \"movaw %a1,%0\";
280: }")
281:
282: (define_insn ""
283: [(set (match_operand:SI 0 "general_operand" "=g")
284: (match_operand:SI 1 "address_operand" "p"))]
285: ""
286: "*
287: {
288: if (push_operand (operands[0], SImode))
289: return \"pushal %a1\";
290: return \"moval %a1,%0\";
291: }")
292:
293: (define_insn ""
294: [(set (match_operand:SI 0 "general_operand" "=g")
295: (match_operand:SF 1 "address_operand" "p"))]
296: ""
297: "*
298: {
299: if (push_operand (operands[0], SImode))
300: return \"pushaf %a1\";
301: return \"movaf %a1,%0\";
302: }")
303:
304: (define_insn ""
305: [(set (match_operand:SI 0 "general_operand" "=g")
306: (match_operand:DF 1 "address_operand" "p"))]
307: ""
308: "*
309: {
310: if (push_operand (operands[0], SImode))
311: return \"pushad %a1\";
312: return \"movad %a1,%0\";
313: }")
314:
1.1.1.2 root 315: ;; Extension and truncation insns.
316: ;; Those for integer source operand
317: ;; are ordered widest source type first.
1.1 root 318:
1.1.1.2 root 319: (define_insn "truncsiqi2"
320: [(set (match_operand:QI 0 "general_operand" "=g")
321: (truncate:QI (match_operand:SI 1 "general_operand" "g")))]
1.1 root 322: ""
1.1.1.2 root 323: "cvtlb %1,%0")
1.1 root 324:
1.1.1.2 root 325: (define_insn "truncsihi2"
326: [(set (match_operand:HI 0 "general_operand" "=g")
327: (truncate:HI (match_operand:SI 1 "general_operand" "g")))]
1.1 root 328: ""
1.1.1.2 root 329: "cvtlw %1,%0")
1.1 root 330:
331: (define_insn "trunchiqi2"
332: [(set (match_operand:QI 0 "general_operand" "=g")
333: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
334: ""
335: "cvtwb %1,%0")
336:
337: (define_insn "extendhisi2"
338: [(set (match_operand:SI 0 "general_operand" "=g")
339: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
340: ""
341: "cvtwl %1,%0")
342:
1.1.1.2 root 343: (define_insn "extendqihi2"
344: [(set (match_operand:HI 0 "general_operand" "=g")
345: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1.1 root 346: ""
1.1.1.2 root 347: "cvtbw %1,%0")
1.1 root 348:
1.1.1.2 root 349: (define_insn "extendqisi2"
350: [(set (match_operand:SI 0 "general_operand" "=g")
351: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
352: ""
353: "cvtbl %1,%0")
354:
355: (define_insn "extendsfdf2"
1.1 root 356: [(set (match_operand:DF 0 "general_operand" "=g")
1.1.1.2 root 357: (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
1.1 root 358: ""
1.1.1.3 ! root 359: "cvtf%# %1,%0")
1.1 root 360:
1.1.1.2 root 361: (define_insn "truncdfsf2"
362: [(set (match_operand:SF 0 "general_operand" "=g")
363: (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
1.1 root 364: ""
1.1.1.3 ! root 365: "cvt%#f %1,%0")
1.1 root 366:
1.1.1.2 root 367: (define_insn "zero_extendhisi2"
368: [(set (match_operand:SI 0 "general_operand" "=g")
369: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
370: ""
371: "movzwl %1,%0")
372:
373: (define_insn "zero_extendqihi2"
1.1 root 374: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 375: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1.1 root 376: ""
1.1.1.2 root 377: "movzbw %1,%0")
378:
379: (define_insn "zero_extendqisi2"
380: [(set (match_operand:SI 0 "general_operand" "=g")
381: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
382: ""
383: "movzbl %1,%0")
384:
385: ;; Fix-to-float conversion insns.
386: ;; Note that the ones that start with SImode come first.
387: ;; That is so that an operand that is a CONST_INT
388: ;; (and therefore lacks a specific machine mode).
389: ;; will be recognized as SImode (which is always valid)
390: ;; rather than as QImode or HImode.
1.1 root 391:
392: (define_insn "floatsisf2"
393: [(set (match_operand:SF 0 "general_operand" "=g")
394: (float:SF (match_operand:SI 1 "general_operand" "g")))]
395: ""
396: "cvtlf %1,%0")
397:
398: (define_insn "floatsidf2"
399: [(set (match_operand:DF 0 "general_operand" "=g")
400: (float:DF (match_operand:SI 1 "general_operand" "g")))]
401: ""
1.1.1.3 ! root 402: "cvtl%# %1,%0")
1.1 root 403:
1.1.1.2 root 404: (define_insn "floathisf2"
405: [(set (match_operand:SF 0 "general_operand" "=g")
406: (float:SF (match_operand:HI 1 "general_operand" "g")))]
1.1 root 407: ""
1.1.1.2 root 408: "cvtwf %1,%0")
1.1 root 409:
1.1.1.2 root 410: (define_insn "floathidf2"
411: [(set (match_operand:DF 0 "general_operand" "=g")
412: (float:DF (match_operand:HI 1 "general_operand" "g")))]
1.1 root 413: ""
1.1.1.3 ! root 414: "cvtw%# %1,%0")
1.1 root 415:
1.1.1.2 root 416: (define_insn "floatqisf2"
417: [(set (match_operand:SF 0 "general_operand" "=g")
418: (float:SF (match_operand:QI 1 "general_operand" "g")))]
1.1 root 419: ""
1.1.1.2 root 420: "cvtbf %1,%0")
1.1 root 421:
1.1.1.2 root 422: (define_insn "floatqidf2"
1.1 root 423: [(set (match_operand:DF 0 "general_operand" "=g")
1.1.1.2 root 424: (float:DF (match_operand:QI 1 "general_operand" "g")))]
1.1 root 425: ""
1.1.1.3 ! root 426: "cvtb%# %1,%0")
1.1.1.2 root 427:
428: ;; Float-to-fix conversion insns.
1.1 root 429:
1.1.1.2 root 430: (define_insn "fix_truncsfqi2"
1.1 root 431: [(set (match_operand:QI 0 "general_operand" "=g")
1.1.1.2 root 432: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 433: ""
1.1.1.2 root 434: "cvtfb %1,%0")
1.1 root 435:
1.1.1.2 root 436: (define_insn "fix_truncsfhi2"
1.1 root 437: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 438: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 439: ""
1.1.1.2 root 440: "cvtfw %1,%0")
1.1 root 441:
1.1.1.2 root 442: (define_insn "fix_truncsfsi2"
1.1 root 443: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 444: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 445: ""
1.1.1.2 root 446: "cvtfl %1,%0")
1.1 root 447:
1.1.1.2 root 448: (define_insn "fix_truncdfqi2"
449: [(set (match_operand:QI 0 "general_operand" "=g")
450: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 451: ""
1.1.1.2 root 452: "cvtdb %1,%0")
1.1 root 453:
1.1.1.2 root 454: (define_insn "fix_truncdfhi2"
1.1 root 455: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 456: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 457: ""
1.1.1.3 ! root 458: "cvt%#w %1,%0")
1.1 root 459:
1.1.1.2 root 460: (define_insn "fix_truncdfsi2"
1.1 root 461: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 462: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 463: ""
1.1.1.3 ! root 464: "cvt%#l %1,%0")
1.1 root 465:
466: ;;- All kinds of add instructions.
467:
468: (define_insn "adddf3"
469: [(set (match_operand:DF 0 "general_operand" "=g")
470: (plus:DF (match_operand:DF 1 "general_operand" "gF")
471: (match_operand:DF 2 "general_operand" "gF")))]
472: ""
473: "*
474: {
475: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 ! root 476: return \"add%#2 %2,%0\";
1.1 root 477: if (rtx_equal_p (operands[0], operands[2]))
1.1.1.3 ! root 478: return \"add%#2 %1,%0\";
! 479: return \"add%#3 %1,%2,%0\";
1.1 root 480: }")
481:
482: (define_insn "addsf3"
483: [(set (match_operand:SF 0 "general_operand" "=g")
484: (plus:SF (match_operand:SF 1 "general_operand" "gF")
485: (match_operand:SF 2 "general_operand" "gF")))]
486: ""
487: "*
488: {
489: if (rtx_equal_p (operands[0], operands[1]))
490: return \"addf2 %2,%0\";
491: if (rtx_equal_p (operands[0], operands[2]))
492: return \"addf2 %1,%0\";
493: return \"addf3 %1,%2,%0\";
494: }")
495:
496: (define_insn "addsi3"
497: [(set (match_operand:SI 0 "general_operand" "=g")
498: (plus:SI (match_operand:SI 1 "general_operand" "g")
499: (match_operand:SI 2 "general_operand" "g")))]
500: ""
501: "*
502: {
503: if (rtx_equal_p (operands[0], operands[1]))
504: {
505: if (operands[2] == const1_rtx)
506: return \"incl %0\";
1.1.1.2 root 507: if (GET_CODE (operands[2]) == CONST_INT
508: && INTVAL (operands[2]) == -1)
1.1 root 509: return \"decl %0\";
510: if (GET_CODE (operands[2]) == CONST_INT
511: && (unsigned) (- INTVAL (operands[2])) < 64)
512: return \"subl2 $%n2,%0\";
513: return \"addl2 %2,%0\";
514: }
515: if (rtx_equal_p (operands[0], operands[2]))
516: return \"addl2 %1,%0\";
517: if (GET_CODE (operands[2]) == CONST_INT
518: && GET_CODE (operands[1]) == REG)
519: {
520: if (push_operand (operands[0], SImode))
521: return \"pushab %c2(%1)\";
522: return \"movab %c2(%1),%0\";
523: }
524: if (GET_CODE (operands[2]) == CONST_INT
525: && (unsigned) (- INTVAL (operands[2])) < 64)
526: return \"subl3 $%n2,%1,%0\";
527: return \"addl3 %1,%2,%0\";
528: }")
529:
530: (define_insn "addhi3"
531: [(set (match_operand:HI 0 "general_operand" "=g")
532: (plus:HI (match_operand:HI 1 "general_operand" "g")
533: (match_operand:HI 2 "general_operand" "g")))]
534: ""
535: "*
536: {
537: if (rtx_equal_p (operands[0], operands[1]))
538: {
539: if (operands[2] == const1_rtx)
540: return \"incw %0\";
541: if (GET_CODE (operands[1]) == CONST_INT
542: && INTVAL (operands[1]) == -1)
543: return \"decw %0\";
544: if (GET_CODE (operands[2]) == CONST_INT
545: && (unsigned) (- INTVAL (operands[2])) < 64)
546: return \"subw2 $%n2,%0\";
547: return \"addw2 %2,%0\";
548: }
549: if (rtx_equal_p (operands[0], operands[2]))
550: return \"addw2 %1,%0\";
551: if (GET_CODE (operands[2]) == CONST_INT
552: && (unsigned) (- INTVAL (operands[2])) < 64)
553: return \"subw3 $%n2,%1,%0\";
554: return \"addw3 %1,%2,%0\";
555: }")
556:
557: (define_insn "addqi3"
558: [(set (match_operand:QI 0 "general_operand" "=g")
559: (plus:QI (match_operand:QI 1 "general_operand" "g")
560: (match_operand:QI 2 "general_operand" "g")))]
561: ""
562: "*
563: {
564: if (rtx_equal_p (operands[0], operands[1]))
565: {
566: if (operands[2] == const1_rtx)
567: return \"incb %0\";
568: if (GET_CODE (operands[1]) == CONST_INT
569: && INTVAL (operands[1]) == -1)
570: return \"decb %0\";
571: if (GET_CODE (operands[2]) == CONST_INT
572: && (unsigned) (- INTVAL (operands[2])) < 64)
573: return \"subb2 $%n2,%0\";
574: return \"addb2 %2,%0\";
575: }
576: if (rtx_equal_p (operands[0], operands[2]))
577: return \"addb2 %1,%0\";
578: if (GET_CODE (operands[2]) == CONST_INT
579: && (unsigned) (- INTVAL (operands[2])) < 64)
580: return \"subb3 $%n2,%1,%0\";
581: return \"addb3 %1,%2,%0\";
582: }")
583:
584: ;;- All kinds of subtract instructions.
585:
586: (define_insn "subdf3"
587: [(set (match_operand:DF 0 "general_operand" "=g")
588: (minus:DF (match_operand:DF 1 "general_operand" "gF")
589: (match_operand:DF 2 "general_operand" "gF")))]
590: ""
591: "*
592: {
593: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 ! root 594: return \"sub%#2 %2,%0\";
! 595: return \"sub%#3 %2,%1,%0\";
1.1 root 596: }")
597:
598: (define_insn "subsf3"
599: [(set (match_operand:SF 0 "general_operand" "=g")
600: (minus:SF (match_operand:SF 1 "general_operand" "gF")
601: (match_operand:SF 2 "general_operand" "gF")))]
602: ""
603: "*
604: {
605: if (rtx_equal_p (operands[0], operands[1]))
606: return \"subf2 %2,%0\";
607: return \"subf3 %2,%1,%0\";
608: }")
609:
610: (define_insn "subsi3"
611: [(set (match_operand:SI 0 "general_operand" "=g")
612: (minus:SI (match_operand:SI 1 "general_operand" "g")
613: (match_operand:SI 2 "general_operand" "g")))]
614: ""
615: "*
616: {
617: if (rtx_equal_p (operands[0], operands[1]))
618: {
619: if (operands[2] == const1_rtx)
620: return \"decl %0\";
621: return \"subl2 %2,%0\";
622: }
623: return \"subl3 %2,%1,%0\";
624: }")
625:
626: (define_insn "subhi3"
627: [(set (match_operand:HI 0 "general_operand" "=g")
628: (minus:HI (match_operand:HI 1 "general_operand" "g")
629: (match_operand:HI 2 "general_operand" "g")))]
630: ""
631: "*
632: {
633: if (rtx_equal_p (operands[0], operands[1]))
634: {
635: if (operands[2] == const1_rtx)
636: return \"decw %0\";
637: return \"subw2 %2,%0\";
638: }
639: return \"subw3 %2,%1,%0\";
640: }")
641:
642: (define_insn "subqi3"
643: [(set (match_operand:QI 0 "general_operand" "=g")
644: (minus:QI (match_operand:QI 1 "general_operand" "g")
645: (match_operand:QI 2 "general_operand" "g")))]
646: ""
647: "*
648: {
649: if (rtx_equal_p (operands[0], operands[1]))
650: {
651: if (operands[2] == const1_rtx)
652: return \"decb %0\";
653: return \"subb2 %2,%0\";
654: }
655: return \"subb3 %2,%1,%0\";
656: }")
657:
658: ;;- Multiply instructions.
659:
660: (define_insn "muldf3"
661: [(set (match_operand:DF 0 "general_operand" "=g")
662: (mult:DF (match_operand:DF 1 "general_operand" "gF")
663: (match_operand:DF 2 "general_operand" "gF")))]
664: ""
665: "*
666: {
667: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 ! root 668: return \"mul%#2 %2,%0\";
1.1 root 669: if (rtx_equal_p (operands[0], operands[2]))
1.1.1.3 ! root 670: return \"mul%#2 %1,%0\";
! 671: return \"mul%#3 %1,%2,%0\";
1.1 root 672: }")
673:
674: (define_insn "mulsf3"
675: [(set (match_operand:SF 0 "general_operand" "=g")
676: (mult:SF (match_operand:SF 1 "general_operand" "gF")
677: (match_operand:SF 2 "general_operand" "gF")))]
678: ""
679: "*
680: {
681: if (rtx_equal_p (operands[0], operands[1]))
682: return \"mulf2 %2,%0\";
683: if (rtx_equal_p (operands[0], operands[2]))
684: return \"mulf2 %1,%0\";
685: return \"mulf3 %1,%2,%0\";
686: }")
687:
688: (define_insn "mulsi3"
689: [(set (match_operand:SI 0 "general_operand" "=g")
690: (mult:SI (match_operand:SI 1 "general_operand" "g")
691: (match_operand:SI 2 "general_operand" "g")))]
692: ""
693: "*
694: {
695: if (rtx_equal_p (operands[0], operands[1]))
696: return \"mull2 %2,%0\";
697: if (rtx_equal_p (operands[0], operands[2]))
698: return \"mull2 %1,%0\";
699: return \"mull3 %1,%2,%0\";
700: }")
701:
702: (define_insn "mulhi3"
703: [(set (match_operand:HI 0 "general_operand" "=g")
704: (mult:HI (match_operand:HI 1 "general_operand" "g")
705: (match_operand:HI 2 "general_operand" "g")))]
706: ""
707: "*
708: {
709: if (rtx_equal_p (operands[0], operands[1]))
710: return \"mulw2 %2,%0\";
711: if (rtx_equal_p (operands[0], operands[2]))
712: return \"mulw2 %1,%0\";
713: return \"mulw3 %1,%2,%0\";
714: }")
715:
716: (define_insn "mulqi3"
717: [(set (match_operand:QI 0 "general_operand" "=g")
718: (mult:QI (match_operand:QI 1 "general_operand" "g")
719: (match_operand:QI 2 "general_operand" "g")))]
720: ""
721: "*
722: {
723: if (rtx_equal_p (operands[0], operands[1]))
724: return \"mulb2 %2,%0\";
725: if (rtx_equal_p (operands[0], operands[2]))
726: return \"mulb2 %1,%0\";
727: return \"mulb3 %1,%2,%0\";
728: }")
729:
730: ;;- Divide instructions.
731:
732: (define_insn "divdf3"
733: [(set (match_operand:DF 0 "general_operand" "=g")
734: (div:DF (match_operand:DF 1 "general_operand" "gF")
735: (match_operand:DF 2 "general_operand" "gF")))]
736: ""
737: "*
738: {
739: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 ! root 740: return \"div%#2 %2,%0\";
! 741: return \"div%#3 %2,%1,%0\";
1.1 root 742: }")
743:
744: (define_insn "divsf3"
745: [(set (match_operand:SF 0 "general_operand" "=g")
746: (div:SF (match_operand:SF 1 "general_operand" "gF")
747: (match_operand:SF 2 "general_operand" "gF")))]
748: ""
749: "*
750: {
751: if (rtx_equal_p (operands[0], operands[1]))
752: return \"divf2 %2,%0\";
753: return \"divf3 %2,%1,%0\";
754: }")
755:
756: (define_insn "divsi3"
757: [(set (match_operand:SI 0 "general_operand" "=g")
758: (div:SI (match_operand:SI 1 "general_operand" "g")
759: (match_operand:SI 2 "general_operand" "g")))]
760: ""
761: "*
762: {
763: if (rtx_equal_p (operands[0], operands[1]))
764: return \"divl2 %2,%0\";
765: return \"divl3 %2,%1,%0\";
766: }")
767:
768: (define_insn "divhi3"
769: [(set (match_operand:HI 0 "general_operand" "=g")
770: (div:HI (match_operand:HI 1 "general_operand" "g")
771: (match_operand:HI 2 "general_operand" "g")))]
772: ""
773: "*
774: {
775: if (rtx_equal_p (operands[0], operands[1]))
776: return \"divw2 %2,%0\";
777: return \"divw3 %2,%1,%0\";
778: }")
779:
780: (define_insn "divqi3"
781: [(set (match_operand:QI 0 "general_operand" "=g")
782: (div:QI (match_operand:QI 1 "general_operand" "g")
783: (match_operand:QI 2 "general_operand" "g")))]
784: ""
785: "*
786: {
787: if (rtx_equal_p (operands[0], operands[1]))
788: return \"divb2 %2,%0\";
789: return \"divb3 %2,%1,%0\";
790: }")
791:
792: ;This is left out because it is very slow;
793: ;we are better off programming around the "lack" of this insn.
794: ;(define_insn "divmoddisi4"
795: ; [(set (match_operand:SI 0 "general_operand" "=g")
796: ; (div:SI (match_operand:DI 1 "general_operand" "g")
797: ; (match_operand:SI 2 "general_operand" "g")))
798: ; (set (match_operand:SI 3 "general_operand" "=g")
799: ; (mod:SI (match_operand:DI 1 "general_operand" "g")
800: ; (match_operand:SI 2 "general_operand" "g")))]
801: ; ""
802: ; "ediv %2,%1,%0,%3")
803:
804: (define_insn "andcbsi3"
805: [(set (match_operand:SI 0 "general_operand" "=g")
806: (and:SI (match_operand:SI 1 "general_operand" "g")
807: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
808: ""
809: "*
810: {
811: if (rtx_equal_p (operands[0], operands[1]))
812: return \"bicl2 %2,%0\";
813: return \"bicl3 %2,%1,%0\";
814: }")
815:
816: (define_insn "andcbhi3"
817: [(set (match_operand:HI 0 "general_operand" "=g")
818: (and:HI (match_operand:HI 1 "general_operand" "g")
819: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
820: ""
821: "*
822: {
823: if (rtx_equal_p (operands[0], operands[1]))
824: return \"bicw2 %2,%0\";
825: return \"bicw3 %2,%1,%0\";
826: }")
827:
828: (define_insn "andcbqi3"
829: [(set (match_operand:QI 0 "general_operand" "=g")
830: (and:QI (match_operand:QI 1 "general_operand" "g")
831: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
832: ""
833: "*
834: {
835: if (rtx_equal_p (operands[0], operands[1]))
836: return \"bicb2 %2,%0\";
837: return \"bicb3 %2,%1,%0\";
838: }")
839:
840: ;; The following are needed because constant propagation can
841: ;; create them starting from the bic insn patterns above.
842:
843: (define_insn ""
844: [(set (match_operand:SI 0 "general_operand" "=g")
845: (and:SI (match_operand:SI 1 "general_operand" "g")
846: (match_operand:SI 2 "general_operand" "g")))]
847: "GET_CODE (operands[2]) == CONST_INT"
848: "*
849: { operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
850: if (rtx_equal_p (operands[1], operands[0]))
851: return \"bicl2 %2,%0\";
852: return \"bicl3 %2,%1,%0\";
853: }")
854:
855: (define_insn ""
856: [(set (match_operand:HI 0 "general_operand" "=g")
857: (and:HI (match_operand:HI 1 "general_operand" "g")
858: (match_operand:HI 2 "general_operand" "g")))]
859: "GET_CODE (operands[2]) == CONST_INT"
860: "*
861: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xffff & ~INTVAL (operands[2]));
862: if (rtx_equal_p (operands[1], operands[0]))
863: return \"bicw2 %2,%0\";
864: return \"bicw3 %2,%1,%0\";
865: }")
866:
867: (define_insn ""
868: [(set (match_operand:QI 0 "general_operand" "=g")
869: (and:QI (match_operand:QI 1 "general_operand" "g")
870: (match_operand:QI 2 "general_operand" "g")))]
871: "GET_CODE (operands[2]) == CONST_INT"
872: "*
873: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xff & ~INTVAL (operands[2]));
874: if (rtx_equal_p (operands[1], operands[0]))
875: return \"bicb2 %2,%0\";
876: return \"bicb3 %2,%1,%0\";
877: }")
878:
879: ;;- Bit set instructions.
880:
881: (define_insn "iorsi3"
882: [(set (match_operand:SI 0 "general_operand" "=g")
883: (ior:SI (match_operand:SI 1 "general_operand" "g")
884: (match_operand:SI 2 "general_operand" "g")))]
885: ""
886: "*
887: {
888: if (rtx_equal_p (operands[0], operands[1]))
889: return \"bisl2 %2,%0\";
890: if (rtx_equal_p (operands[0], operands[2]))
891: return \"bisl2 %1,%0\";
892: return \"bisl3 %2,%1,%0\";
893: }")
894:
895: (define_insn "iorhi3"
896: [(set (match_operand:HI 0 "general_operand" "=g")
897: (ior:HI (match_operand:HI 1 "general_operand" "g")
898: (match_operand:HI 2 "general_operand" "g")))]
899: ""
900: "*
901: {
902: if (rtx_equal_p (operands[0], operands[1]))
903: return \"bisw2 %2,%0\";
904: if (rtx_equal_p (operands[0], operands[2]))
905: return \"bisw2 %1,%0\";
906: return \"bisw3 %2,%1,%0\";
907: }")
908:
909: (define_insn "iorqi3"
910: [(set (match_operand:QI 0 "general_operand" "=g")
911: (ior:QI (match_operand:QI 1 "general_operand" "g")
912: (match_operand:QI 2 "general_operand" "g")))]
913: ""
914: "*
915: {
916: if (rtx_equal_p (operands[0], operands[1]))
917: return \"bisb2 %2,%0\";
918: if (rtx_equal_p (operands[0], operands[2]))
919: return \"bisb2 %1,%0\";
920: return \"bisb3 %2,%1,%0\";
921: }")
922:
923: ;;- xor instructions.
924:
925: (define_insn "xorsi3"
926: [(set (match_operand:SI 0 "general_operand" "=g")
927: (xor:SI (match_operand:SI 1 "general_operand" "g")
928: (match_operand:SI 2 "general_operand" "g")))]
929: ""
930: "*
931: {
932: if (rtx_equal_p (operands[0], operands[1]))
933: return \"xorl2 %2,%0\";
934: if (rtx_equal_p (operands[0], operands[2]))
935: return \"xorl2 %1,%0\";
936: return \"xorl3 %2,%1,%0\";
937: }")
938:
939: (define_insn "xorhi3"
940: [(set (match_operand:HI 0 "general_operand" "=g")
941: (xor:HI (match_operand:HI 1 "general_operand" "g")
942: (match_operand:HI 2 "general_operand" "g")))]
943: ""
944: "*
945: {
946: if (rtx_equal_p (operands[0], operands[1]))
947: return \"xorw2 %2,%0\";
948: if (rtx_equal_p (operands[0], operands[2]))
949: return \"xorw2 %1,%0\";
950: return \"xorw3 %2,%1,%0\";
951: }")
952:
953: (define_insn "xorqi3"
954: [(set (match_operand:QI 0 "general_operand" "=g")
955: (xor:QI (match_operand:QI 1 "general_operand" "g")
956: (match_operand:QI 2 "general_operand" "g")))]
957: ""
958: "*
959: {
960: if (rtx_equal_p (operands[0], operands[1]))
961: return \"xorb2 %2,%0\";
962: if (rtx_equal_p (operands[0], operands[2]))
963: return \"xorb2 %1,%0\";
964: return \"xorb3 %2,%1,%0\";
965: }")
966:
967: (define_insn "negdf2"
968: [(set (match_operand:DF 0 "general_operand" "=g")
969: (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
970: ""
1.1.1.3 ! root 971: "mneg%# %1,%0")
1.1 root 972:
973: (define_insn "negsf2"
974: [(set (match_operand:SF 0 "general_operand" "=g")
975: (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
976: ""
977: "mnegf %1,%0")
978:
979: (define_insn "negsi2"
980: [(set (match_operand:SI 0 "general_operand" "=g")
981: (neg:SI (match_operand:SI 1 "general_operand" "g")))]
982: ""
983: "mnegl %1,%0")
984:
985: (define_insn "neghi2"
986: [(set (match_operand:HI 0 "general_operand" "=g")
987: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
988: ""
989: "mnegw %1,%0")
990:
991: (define_insn "negqi2"
992: [(set (match_operand:QI 0 "general_operand" "=g")
993: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
994: ""
995: "mnegb %1,%0")
996:
997: (define_insn "one_cmplsi2"
998: [(set (match_operand:SI 0 "general_operand" "=g")
999: (not:SI (match_operand:SI 1 "general_operand" "g")))]
1000: ""
1001: "mcoml %1,%0")
1002:
1003: (define_insn "one_cmplhi2"
1004: [(set (match_operand:HI 0 "general_operand" "=g")
1005: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1006: ""
1007: "mcomw %1,%0")
1008:
1009: (define_insn "one_cmplqi2"
1010: [(set (match_operand:QI 0 "general_operand" "=g")
1011: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1012: ""
1013: "mcomb %1,%0")
1014:
1015: (define_insn "ashlsi3"
1016: [(set (match_operand:SI 0 "general_operand" "=g")
1017: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1018: (match_operand:QI 2 "general_operand" "g")))]
1019: ""
1.1.1.2 root 1020: "*
1021: {
1022: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1023: return \"addl2 %0,%0\";
1024: return \"ashl %2,%1,%0\";
1025: }")
1.1 root 1026:
1027: (define_insn "ashldi3"
1028: [(set (match_operand:DI 0 "general_operand" "=g")
1029: (ashift:DI (match_operand:DI 1 "general_operand" "g")
1030: (match_operand:QI 2 "general_operand" "g")))]
1031: ""
1032: "ashq %2,%1,%0")
1033:
1034: (define_insn "rotlsi3"
1035: [(set (match_operand:SI 0 "general_operand" "=g")
1036: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1037: (match_operand:QI 2 "general_operand" "g")))]
1038: ""
1039: "rotl %2,%1,%0")
1040:
1041: (define_insn "rotldi3"
1042: [(set (match_operand:DI 0 "general_operand" "=g")
1043: (rotate:DI (match_operand:DI 1 "general_operand" "g")
1044: (match_operand:QI 2 "general_operand" "g")))]
1045: ""
1046: "rotq %2,%1,%0")
1047:
1.1.1.2 root 1048: ;This insn is probably slower than a multiply and an add.
1049: ;(define_insn ""
1050: ; [(set (match_operand:SI 0 "general_operand" "=g")
1051: ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1052: ; (match_operand:SI 2 "general_operand" "g"))
1053: ; (match_operand:SI 3 "general_operand" "g")))]
1054: ; ""
1055: ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1.1 root 1056:
1057: (define_insn ""
1058: [(set (cc0)
1059: (minus
1060: (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1061: (match_operand:SI 1 "general_operand" "g")
1062: (match_operand:SI 2 "general_operand" "g"))
1063: (match_operand:SI 3 "general_operand" "g")))]
1064: ""
1065: "cmpv %2,%1,%0,%3")
1066:
1067: (define_insn ""
1068: [(set (cc0)
1069: (minus
1070: (zero_extract:SI (match_operand:QI 0 "general_operand" "g")
1071: (match_operand:SI 1 "general_operand" "g")
1072: (match_operand:SI 2 "general_operand" "g"))
1073: (match_operand:SI 3 "general_operand" "g")))]
1074: ""
1075: "cmpzv %2,%1,%0,%3")
1076:
1077: (define_insn "extv"
1078: [(set (match_operand:SI 0 "general_operand" "=g")
1079: (sign_extract:SI (match_operand:QI 1 "general_operand" "g")
1080: (match_operand:SI 2 "general_operand" "g")
1081: (match_operand:SI 3 "general_operand" "g")))]
1082: ""
1083: "extv %3,%2,%1,%0")
1084:
1085: (define_insn "extzv"
1086: [(set (match_operand:SI 0 "general_operand" "=g")
1087: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1088: (match_operand:SI 2 "general_operand" "g")
1089: (match_operand:SI 3 "general_operand" "g")))]
1090: ""
1091: "extzv %3,%2,%1,%0")
1092:
1093: (define_insn ""
1094: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 1095: (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
1.1 root 1096: (match_operand:SI 2 "general_operand" "g")
1097: (match_operand:SI 3 "general_operand" "g")))]
1098: ""
1099: "extv %3,%2,%1,%0")
1100:
1101: (define_insn ""
1102: [(set (match_operand:SI 0 "general_operand" "=g")
1103: (zero_extract:SI (match_operand:SI 1 "general_operand" "r")
1104: (match_operand:SI 2 "general_operand" "g")
1105: (match_operand:SI 3 "general_operand" "g")))]
1106: ""
1107: "extzv %3,%2,%1,%0")
1108:
1109: (define_insn "insv"
1.1.1.2 root 1110: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1.1 root 1111: (match_operand:SI 1 "general_operand" "g")
1112: (match_operand:SI 2 "general_operand" "g"))
1113: (match_operand:SI 3 "general_operand" "g"))]
1114: ""
1115: "insv %3,%2,%1,%0")
1116:
1117: (define_insn ""
1.1.1.2 root 1118: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1.1 root 1119: (match_operand:SI 1 "general_operand" "g")
1120: (match_operand:SI 2 "general_operand" "g"))
1121: (match_operand:SI 3 "general_operand" "g"))]
1122: ""
1123: "insv %3,%2,%1,%0")
1124:
1125: (define_insn "jump"
1126: [(set (pc)
1127: (label_ref (match_operand 0 "" "")))]
1128: ""
1129: "jbr %l0")
1130:
1131: (define_insn "beq"
1132: [(set (pc)
1133: (if_then_else (eq (cc0)
1134: (const_int 0))
1135: (label_ref (match_operand 0 "" ""))
1136: (pc)))]
1137: ""
1138: "jeql %l0")
1139:
1140: (define_insn "bne"
1141: [(set (pc)
1142: (if_then_else (ne (cc0)
1143: (const_int 0))
1144: (label_ref (match_operand 0 "" ""))
1145: (pc)))]
1146: ""
1147: "jneq %l0")
1148:
1149: (define_insn "bgt"
1150: [(set (pc)
1151: (if_then_else (gt (cc0)
1152: (const_int 0))
1153: (label_ref (match_operand 0 "" ""))
1154: (pc)))]
1155: ""
1156: "jgtr %l0")
1157:
1158: (define_insn "bgtu"
1159: [(set (pc)
1160: (if_then_else (gtu (cc0)
1161: (const_int 0))
1162: (label_ref (match_operand 0 "" ""))
1163: (pc)))]
1164: ""
1165: "jgtru %l0")
1166:
1167: (define_insn "blt"
1168: [(set (pc)
1169: (if_then_else (lt (cc0)
1170: (const_int 0))
1171: (label_ref (match_operand 0 "" ""))
1172: (pc)))]
1173: ""
1174: "jlss %l0")
1175:
1176: (define_insn "bltu"
1177: [(set (pc)
1178: (if_then_else (ltu (cc0)
1179: (const_int 0))
1180: (label_ref (match_operand 0 "" ""))
1181: (pc)))]
1182: ""
1183: "jlssu %l0")
1184:
1185: (define_insn "bge"
1186: [(set (pc)
1187: (if_then_else (ge (cc0)
1188: (const_int 0))
1189: (label_ref (match_operand 0 "" ""))
1190: (pc)))]
1191: ""
1192: "jgeq %l0")
1193:
1194: (define_insn "bgeu"
1195: [(set (pc)
1196: (if_then_else (geu (cc0)
1197: (const_int 0))
1198: (label_ref (match_operand 0 "" ""))
1199: (pc)))]
1200: ""
1201: "jgequ %l0")
1202:
1203: (define_insn "ble"
1204: [(set (pc)
1205: (if_then_else (le (cc0)
1206: (const_int 0))
1207: (label_ref (match_operand 0 "" ""))
1208: (pc)))]
1209: ""
1210: "jleq %l0")
1211:
1212: (define_insn "bleu"
1213: [(set (pc)
1214: (if_then_else (leu (cc0)
1215: (const_int 0))
1216: (label_ref (match_operand 0 "" ""))
1217: (pc)))]
1218: ""
1219: "jlequ %l0")
1220:
1221: (define_insn ""
1222: [(set (pc)
1223: (if_then_else (eq (cc0)
1224: (const_int 0))
1225: (pc)
1226: (label_ref (match_operand 0 "" ""))))]
1227: ""
1228: "jneq %l0")
1229:
1230: (define_insn ""
1231: [(set (pc)
1232: (if_then_else (ne (cc0)
1233: (const_int 0))
1234: (pc)
1235: (label_ref (match_operand 0 "" ""))))]
1236: ""
1237: "jeql %l0")
1238:
1239: (define_insn ""
1240: [(set (pc)
1241: (if_then_else (gt (cc0)
1242: (const_int 0))
1243: (pc)
1244: (label_ref (match_operand 0 "" ""))))]
1245: ""
1246: "jleq %l0")
1247:
1248: (define_insn ""
1249: [(set (pc)
1250: (if_then_else (gtu (cc0)
1251: (const_int 0))
1252: (pc)
1253: (label_ref (match_operand 0 "" ""))))]
1254: ""
1255: "jlequ %l0")
1256:
1257: (define_insn ""
1258: [(set (pc)
1259: (if_then_else (lt (cc0)
1260: (const_int 0))
1261: (pc)
1262: (label_ref (match_operand 0 "" ""))))]
1263: ""
1264: "jgeq %l0")
1265:
1266: (define_insn ""
1267: [(set (pc)
1268: (if_then_else (ltu (cc0)
1269: (const_int 0))
1270: (pc)
1271: (label_ref (match_operand 0 "" ""))))]
1272: ""
1273: "jgequ %l0")
1274:
1275: (define_insn ""
1276: [(set (pc)
1277: (if_then_else (ge (cc0)
1278: (const_int 0))
1279: (pc)
1280: (label_ref (match_operand 0 "" ""))))]
1281: ""
1282: "jlss %l0")
1283:
1284: (define_insn ""
1285: [(set (pc)
1286: (if_then_else (geu (cc0)
1287: (const_int 0))
1288: (pc)
1289: (label_ref (match_operand 0 "" ""))))]
1290: ""
1291: "jlssu %l0")
1292:
1293: (define_insn ""
1294: [(set (pc)
1295: (if_then_else (le (cc0)
1296: (const_int 0))
1297: (pc)
1298: (label_ref (match_operand 0 "" ""))))]
1299: ""
1300: "jgtr %l0")
1301:
1302: (define_insn ""
1303: [(set (pc)
1304: (if_then_else (leu (cc0)
1305: (const_int 0))
1306: (pc)
1307: (label_ref (match_operand 0 "" ""))))]
1308: ""
1309: "jgtru %l0")
1310:
1311: ;; Recognize jbs and jbc instructions.
1312:
1313: (define_insn ""
1314: [(set (pc)
1315: (if_then_else
1316: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1317: (const_int 1)
1318: (match_operand:SI 1 "general_operand" "g"))
1319: (const_int 0))
1320: (label_ref (match_operand 2 "" ""))
1321: (pc)))]
1322: ""
1323: "jbs %1,%0,%l2")
1324:
1325: (define_insn ""
1326: [(set (pc)
1327: (if_then_else
1328: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1329: (const_int 1)
1330: (match_operand:SI 1 "general_operand" "g"))
1331: (const_int 0))
1332: (label_ref (match_operand 2 "" ""))
1333: (pc)))]
1334: ""
1335: "jbc %1,%0,%l2")
1336:
1337: (define_insn ""
1338: [(set (pc)
1339: (if_then_else
1340: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1341: (const_int 1)
1342: (match_operand:SI 1 "general_operand" "g"))
1343: (const_int 0))
1344: (pc)
1345: (label_ref (match_operand 2 "" ""))))]
1346: ""
1347: "jbc %1,%0,%l2")
1348:
1349: (define_insn ""
1350: [(set (pc)
1351: (if_then_else
1352: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1353: (const_int 1)
1354: (match_operand:SI 1 "general_operand" "g"))
1355: (const_int 0))
1356: (pc)
1357: (label_ref (match_operand 2 "" ""))))]
1358: ""
1359: "jbs %1,%0,%l2")
1360:
1361: (define_insn ""
1362: [(set (pc)
1363: (if_then_else
1364: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1365: (const_int 1)
1366: (match_operand:SI 1 "general_operand" "g"))
1367: (const_int 0))
1368: (label_ref (match_operand 2 "" ""))
1369: (pc)))]
1.1.1.2 root 1370: "GET_CODE (operands[0]) != MEM
1371: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1372: "jbs %1,%0,%l2")
1373:
1374: (define_insn ""
1375: [(set (pc)
1376: (if_then_else
1377: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1378: (const_int 1)
1379: (match_operand:SI 1 "general_operand" "g"))
1380: (const_int 0))
1381: (label_ref (match_operand 2 "" ""))
1382: (pc)))]
1.1.1.2 root 1383: "GET_CODE (operands[0]) != MEM
1384: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1385: "jbc %1,%0,%l2")
1386:
1387: (define_insn ""
1388: [(set (pc)
1389: (if_then_else
1.1.1.2 root 1390: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1391: (match_operand:SI 1 "general_operand" "g"))
1392: (const_int 0))
1393: (pc)
1394: (label_ref (match_operand 2 "" ""))))]
1395: "GET_CODE (operands[1]) == CONST_INT
1396: && exact_log2 (INTVAL (operands[1])) >= 0
1397: && (GET_CODE (operands[0]) != MEM
1398: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1399: "*
1400: {
1401: operands[1]
1402: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1403: return \"jbs %1,%0,%l2\";
1404: }")
1405:
1406: (define_insn ""
1407: [(set (pc)
1408: (if_then_else
1409: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1410: (match_operand:SI 1 "general_operand" "g"))
1411: (const_int 0))
1412: (label_ref (match_operand 2 "" ""))
1413: (pc)))]
1414: "GET_CODE (operands[1]) == CONST_INT
1415: && exact_log2 (INTVAL (operands[1])) >= 0
1416: && (GET_CODE (operands[0]) != MEM
1417: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1418: "*
1419: {
1420: operands[1]
1421: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1422: return \"jbc %1,%0,%l2\";
1423: }")
1424:
1425: (define_insn ""
1426: [(set (pc)
1427: (if_then_else
1428: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1429: (match_operand:SI 1 "general_operand" "g"))
1430: (const_int 0))
1431: (pc)
1432: (label_ref (match_operand 2 "" ""))))]
1433: "GET_CODE (operands[1]) == CONST_INT
1434: && exact_log2 (INTVAL (operands[1])) >= 0
1435: && (GET_CODE (operands[0]) != MEM
1436: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1437: "*
1438: {
1439: operands[1]
1440: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1441: return \"jbc %1,%0,%l2\";
1442: }")
1443:
1444: (define_insn ""
1445: [(set (pc)
1446: (if_then_else
1447: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1448: (match_operand:SI 1 "general_operand" "g"))
1449: (const_int 0))
1450: (label_ref (match_operand 2 "" ""))
1451: (pc)))]
1452: "GET_CODE (operands[1]) == CONST_INT
1453: && exact_log2 (INTVAL (operands[1])) >= 0
1454: && (GET_CODE (operands[0]) != MEM
1455: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1456: "*
1457: {
1458: operands[1]
1459: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1460: return \"jbs %1,%0,%l2\";
1461: }")
1462:
1463: (define_insn ""
1464: [(set (pc)
1465: (if_then_else
1.1 root 1466: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1467: (const_int 1)
1468: (match_operand:SI 1 "general_operand" "g"))
1469: (const_int 0))
1470: (pc)
1471: (label_ref (match_operand 2 "" ""))))]
1.1.1.2 root 1472: "GET_CODE (operands[0]) != MEM
1473: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1474: "jbc %1,%0,%l2")
1475:
1476: (define_insn ""
1477: [(set (pc)
1478: (if_then_else
1479: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1480: (const_int 1)
1481: (match_operand:SI 1 "general_operand" "g"))
1482: (const_int 0))
1483: (pc)
1484: (label_ref (match_operand 2 "" ""))))]
1.1.1.2 root 1485: "GET_CODE (operands[0]) != MEM
1486: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1487: "jbs %1,%0,%l2")
1488:
1489: (define_insn ""
1490: [(set (pc)
1491: (if_then_else
1492: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1493: (const_int 1))
1494: (const_int 0))
1495: (label_ref (match_operand 1 "" ""))
1496: (pc)))]
1.1.1.2 root 1497: "GET_CODE (operands[0]) != MEM
1498: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1499: "jlbs %0,%l1")
1500:
1501: (define_insn ""
1502: [(set (pc)
1503: (if_then_else
1504: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1505: (const_int 1))
1506: (const_int 0))
1507: (label_ref (match_operand 1 "" ""))
1508: (pc)))]
1.1.1.2 root 1509: "GET_CODE (operands[0]) != MEM
1510: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1511: "jlbc %0,%l1")
1512:
1513: (define_insn ""
1514: [(set (pc)
1515: (if_then_else
1516: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1517: (const_int 1))
1518: (const_int 0))
1519: (pc)
1520: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1521: "GET_CODE (operands[0]) != MEM
1522: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1523: "jlbc %0,%l1")
1524:
1525: (define_insn ""
1526: [(set (pc)
1527: (if_then_else
1528: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1529: (const_int 1))
1530: (const_int 0))
1531: (pc)
1532: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1533: "GET_CODE (operands[0]) != MEM
1534: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1535: "jlbs %0,%l1")
1536:
1537: ;; These four entries allow a jlbc or jlbs to be made
1538: ;; by combination with a bic.
1539: (define_insn ""
1540: [(set (pc)
1541: (if_then_else
1542: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1543: (not:SI (const_int -2)))
1544: (const_int 0))
1545: (label_ref (match_operand 1 "" ""))
1546: (pc)))]
1.1.1.2 root 1547: "GET_CODE (operands[0]) != MEM
1548: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1549: "jlbs %0,%l1")
1550:
1551: (define_insn ""
1552: [(set (pc)
1553: (if_then_else
1554: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1555: (not:SI (const_int -2)))
1556: (const_int 0))
1557: (label_ref (match_operand 1 "" ""))
1558: (pc)))]
1.1.1.2 root 1559: "GET_CODE (operands[0]) != MEM
1560: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1561: "jlbc %0,%l1")
1562:
1563: (define_insn ""
1564: [(set (pc)
1565: (if_then_else
1566: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1567: (not:SI (const_int -2)))
1568: (const_int 0))
1569: (pc)
1570: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1571: "GET_CODE (operands[0]) != MEM
1572: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1573: "jlbc %0,%l1")
1574:
1575: (define_insn ""
1576: [(set (pc)
1577: (if_then_else
1578: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1579: (not:SI (const_int -2)))
1580: (const_int 0))
1581: (pc)
1582: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1583: "GET_CODE (operands[0]) != MEM
1584: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1585: "jlbs %0,%l1")
1586:
1587: ;; Subtract-and-jump and Add-and-jump insns.
1588: ;; These are not used when output is for the Unix assembler
1589: ;; because it does not know how to modify them to reach far.
1590:
1591: ;; Normal sob insns.
1592:
1593: (define_insn ""
1594: [(set (pc)
1595: (if_then_else
1596: (gt (minus:SI (match_operand:SI 0 "general_operand" "+g")
1597: (const_int 1))
1598: (const_int 0))
1599: (label_ref (match_operand 1 "" ""))
1600: (pc)))
1601: (set (match_dup 0)
1.1.1.2 root 1602: (plus:SI (match_dup 0)
1603: (const_int -1)))]
1.1 root 1604: "!TARGET_UNIX_ASM"
1605: "jsobgtr %0,%l1")
1606:
1607: (define_insn ""
1608: [(set (pc)
1609: (if_then_else
1610: (ge (minus:SI (match_operand:SI 0 "general_operand" "+g")
1611: (const_int 1))
1612: (const_int 0))
1613: (label_ref (match_operand 1 "" ""))
1614: (pc)))
1615: (set (match_dup 0)
1.1.1.2 root 1616: (plus:SI (match_dup 0)
1617: (const_int -1)))]
1.1 root 1618: "!TARGET_UNIX_ASM"
1619: "jsobgeq %0,%l1")
1620:
1621: ;; Reversed sob insns.
1622:
1623: (define_insn ""
1624: [(set (pc)
1625: (if_then_else
1626: (le (minus:SI (match_operand:SI 0 "general_operand" "+g")
1627: (const_int 1))
1628: (const_int 0))
1629: (pc)
1630: (label_ref (match_operand 1 "" ""))))
1631: (set (match_dup 0)
1.1.1.2 root 1632: (plus:SI (match_dup 0)
1633: (const_int -1)))]
1.1 root 1634: "!TARGET_UNIX_ASM"
1635: "jsobgtr %0,%l1")
1636:
1637: (define_insn ""
1638: [(set (pc)
1639: (if_then_else
1640: (lt (minus:SI (match_operand:SI 0 "general_operand" "+g")
1641: (const_int 1))
1642: (const_int 0))
1643: (pc)
1644: (label_ref (match_operand 1 "" ""))))
1645: (set (match_dup 0)
1.1.1.2 root 1646: (plus:SI (match_dup 0)
1647: (const_int -1)))]
1.1 root 1648: "!TARGET_UNIX_ASM"
1649: "jsobgeq %0,%l1")
1650:
1651: ;; Normal aob insns.
1652: (define_insn ""
1653: [(set (pc)
1654: (if_then_else
1655: (lt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1656: (const_int 1))
1657: (match_operand:SI 1 "general_operand" "g"))
1658: (const_int 0))
1659: (label_ref (match_operand 2 "" ""))
1660: (pc)))
1661: (set (match_dup 0)
1662: (plus:SI (match_dup 0)
1663: (const_int 1)))]
1664: "!TARGET_UNIX_ASM"
1665: "jaoblss %1,%0,%l2")
1666:
1667: (define_insn ""
1668: [(set (pc)
1669: (if_then_else
1670: (le (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1671: (const_int 1))
1672: (match_operand:SI 1 "general_operand" "g"))
1673: (const_int 0))
1674: (label_ref (match_operand 2 "" ""))
1675: (pc)))
1676: (set (match_dup 0)
1677: (plus:SI (match_dup 0)
1678: (const_int 1)))]
1679: "!TARGET_UNIX_ASM"
1680: "jaobleq %1,%0,%l2")
1681:
1682: ;; Reverse aob insns.
1683: (define_insn ""
1684: [(set (pc)
1685: (if_then_else
1686: (ge (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1687: (const_int 1))
1688: (match_operand:SI 1 "general_operand" "g"))
1689: (const_int 0))
1690: (pc)
1691: (label_ref (match_operand 2 "" ""))))
1692: (set (match_dup 0)
1693: (plus:SI (match_dup 0)
1694: (const_int 1)))]
1695: "!TARGET_UNIX_ASM"
1696: "jaoblss %1,%0,%l2")
1697:
1698: (define_insn ""
1699: [(set (pc)
1700: (if_then_else
1701: (gt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1702: (const_int 1))
1703: (match_operand:SI 1 "general_operand" "g"))
1704: (const_int 0))
1705: (pc)
1706: (label_ref (match_operand 2 "" ""))))
1707: (set (match_dup 0)
1708: (plus:SI (match_dup 0)
1709: (const_int 1)))]
1710: "!TARGET_UNIX_ASM"
1711: "jaobleq %1,%0,%l2")
1712:
1.1.1.2 root 1713: ;; Note that operand 1 is total size of args, in bytes,
1714: ;; and what the call insn wants is the number of words.
1.1 root 1715: (define_insn "call"
1716: [(call (match_operand:QI 0 "general_operand" "g")
1717: (match_operand:QI 1 "general_operand" "g"))]
1718: ""
1.1.1.2 root 1719: "*
1720: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);
1721: return \"calls %1,%0\";
1722: ")
1723:
1724: (define_insn "call_value"
1725: [(set (match_operand 0 "" "g")
1726: (call (match_operand:QI 1 "general_operand" "g")
1727: (match_operand:QI 2 "general_operand" "g")))]
1728: ""
1729: "*
1730: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4);
1731: return \"calls %2,%1\";
1732: ")
1.1 root 1733:
1734: (define_insn "return"
1735: [(return)]
1736: ""
1737: "ret")
1738:
1739: (define_insn "casesi"
1740: [(set (pc)
1741: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
1742: (match_operand:SI 1 "general_operand" "g"))
1743: (match_operand:SI 2 "general_operand" "g"))
1.1.1.2 root 1744: (plus:SI (sign_extend:SI
1.1 root 1745: (mem:HI (plus:SI (pc)
1746: (minus:SI (match_dup 0)
1.1.1.2 root 1747: (match_dup 1)))))
1748: (label_ref:SI (match_operand 3 "" "")))
1.1 root 1749: (pc)))]
1750: ""
1751: "casel %0,%1,%2")
1752:
1.1.1.2 root 1753: ;; This used to arise from the preceding by simplification
1754: ;; if operand 1 is zero. Perhaps it is no longer necessary.
1755: (define_insn ""
1756: [(set (pc)
1757: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1758: (match_operand:SI 1 "general_operand" "g"))
1759: (plus:SI (sign_extend:SI
1760: (mem:HI (plus:SI (pc)
1761: (minus:SI (match_dup 0)
1762: (const_int 0)))))
1763: (label_ref:SI (match_operand 3 "" "")))
1764: (pc)))]
1765: ""
1766: "casel %0,$0,%1")
1767:
1.1 root 1768: ;; This arises from the preceding by simplification if operand 1 is zero.
1769: (define_insn ""
1770: [(set (pc)
1771: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1772: (match_operand:SI 1 "general_operand" "g"))
1.1.1.2 root 1773: (plus:SI (sign_extend:SI
1.1 root 1774: (mem:HI (plus:SI (pc)
1.1.1.2 root 1775: (match_dup 0))))
1776: (label_ref:SI (match_operand 3 "" "")))
1.1 root 1777: (pc)))]
1778: ""
1779: "casel %0,$0,%1")
1780:
1.1.1.2 root 1781: ;; Optimize extzv ...,z; andl2 ...,z
1782: ;; with other operands constant.
1783: (define_peephole
1784: [(set (match_operand:SI 0 "general_operand" "g")
1785: (zero_extract:SI (match_operand:SI 1 "general_operand" "g")
1786: (match_operand:SI 2 "general_operand" "g")
1787: (match_operand:SI 3 "general_operand" "g")))
1788: (set (match_operand:SI 4 "general_operand" "g")
1789: (and:SI (match_dup 0)
1790: (match_operand:SI 5 "general_operand" "g")))]
1791: "GET_CODE (operands[2]) == CONST_INT
1792: && GET_CODE (operands[3]) == CONST_INT
1793: && (INTVAL (operands[2]) + INTVAL (operands[3])) == 32
1794: && GET_CODE (operands[5]) == CONST_INT
1795: && dead_or_set_p (insn, operands[0])"
1796: "*
1797: {
1798: unsigned long mask = INTVAL (operands[5]);
1799: operands[3] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[3]));
1800:
1801: if ((floor_log2 (mask) + 1) >= INTVAL (operands[2]))
1802: mask &= ((1 << INTVAL (operands[2])) - 1);
1803:
1804: operands[5] = gen_rtx (CONST_INT, VOIDmode, ~mask);
1805: if (push_operand (operands[4], SImode))
1806: {
1807: output_asm_insn (\"rotl %3,%1,%0\", operands);
1808: return \"bicl3 %5,%0,%4\";
1809: }
1810: else
1811: {
1812: output_asm_insn (\"rotl %3,%1,%4\", operands);
1813: return \"bicl2 %5,%4\";
1814: }
1815: }")
1816:
1817: ;; Optimize andl3 x,y,z; extzv z,....,z
1818:
1819: (define_peephole
1820: [(set (match_operand:SI 0 "general_operand" "g")
1821: (and:SI (match_operand:SI 1 "general_operand" "g")
1822: (match_operand:SI 2 "general_operand" "g")))
1823: (set (match_operand 3 "general_operand" "g")
1824: (zero_extract:SI (match_dup 0)
1825: (match_operand:SI 4 "general_operand" "g")
1826: (match_operand:SI 5 "general_operand" "g")))]
1827: "GET_CODE (operands[2]) == CONST_INT
1828: && GET_CODE (operands[4]) == CONST_INT
1829: && GET_CODE (operands[5]) == CONST_INT
1830: && (INTVAL (operands[4]) + INTVAL (operands[5])) == 32
1831: && dead_or_set_p (insn, operands[0])"
1832: "*
1833: {
1834: unsigned long mask = INTVAL (operands[2]);
1835:
1836: mask &= ~((1 << INTVAL (operands[5])) - 1);
1837: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~mask);
1838:
1839: operands[5] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[5]));
1840:
1841: if (rtx_equal_p (operands[0], operands[1]))
1842: output_asm_insn (\"bicl2 %2,%0\", operands);
1843: else
1844: output_asm_insn (\"bicl3 %2,%1,%0\", operands);
1845: return \"rotl %5,%0,%3\";
1846: }")
1847:
1.1 root 1848: ;;- Local variables:
1849: ;;- mode:emacs-lisp
1850: ;;- comment-start: ";;- "
1851: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
1852: ;;- eval: (modify-syntax-entry ?[ "(]")
1853: ;;- eval: (modify-syntax-entry ?] ")[")
1854: ;;- eval: (modify-syntax-entry ?{ "(}")
1855: ;;- eval: (modify-syntax-entry ?} "){")
1856: ;;- End:
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