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1.1.1.4 ! root 1: 1.1 root 2: ;;- Machine description for GNU compiler 3: ;;- Vax Version 4: ;; Copyright (C) 1987 Free Software Foundation, Inc. 5: 6: ;; This file is part of GNU CC. 7: 8: ;; GNU CC is distributed in the hope that it will be useful, 9: ;; but WITHOUT ANY WARRANTY. No author or distributor 10: ;; accepts responsibility to anyone for the consequences of using it 11: ;; or for whether it serves any particular purpose or works at all, 12: ;; unless he says so in writing. Refer to the GNU CC General Public 13: ;; License for full details. 14: 15: ;; Everyone is granted permission to copy, modify and redistribute 16: ;; GNU CC, but only under the conditions described in the 17: ;; GNU CC General Public License. A copy of this license is 18: ;; supposed to have been given to you along with GNU CC so you 19: ;; can know your rights and responsibilities. It should be in a 20: ;; file named COPYING. Among other things, the copyright notice 21: ;; and this notice must be preserved on all copies. 22: 23: 24: ;;- Instruction patterns. When multiple patterns apply, 25: ;;- the first one in the file is chosen. 26: ;;- 27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 28: ;;- 29: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code 30: ;;- updates for most instructions. 31: 1.1.1.2 root 32: ; tstsi is first test insn so that it is the one to match 33: ; a constant argument. 1.1 root 34: 35: (define_insn "tstsi" 36: [(set (cc0) 37: (match_operand:SI 0 "general_operand" "g"))] 38: "" 39: "tstl %0") 40: 41: (define_insn "tsthi" 42: [(set (cc0) 43: (match_operand:HI 0 "general_operand" "g"))] 44: "" 45: "tstw %0") 46: 47: (define_insn "tstqi" 48: [(set (cc0) 49: (match_operand:QI 0 "general_operand" "g"))] 50: "" 51: "tstb %0") 52: 1.1.1.2 root 53: (define_insn "tstdf" 1.1 root 54: [(set (cc0) 1.1.1.2 root 55: (match_operand:DF 0 "general_operand" "gF"))] 1.1 root 56: "" 1.1.1.3 root 57: "tst%# %0") 1.1 root 58: 1.1.1.2 root 59: (define_insn "tstsf" 1.1 root 60: [(set (cc0) 1.1.1.2 root 61: (match_operand:SF 0 "general_operand" "gF"))] 1.1 root 62: "" 1.1.1.2 root 63: "tstf %0") 1.1 root 64: 65: (define_insn "cmpsi" 66: [(set (cc0) 67: (minus (match_operand:SI 0 "general_operand" "g") 68: (match_operand:SI 1 "general_operand" "g")))] 69: "" 70: "cmpl %0,%1") 71: 72: (define_insn "cmphi" 73: [(set (cc0) 74: (minus (match_operand:HI 0 "general_operand" "g") 75: (match_operand:HI 1 "general_operand" "g")))] 76: "" 77: "cmpw %0,%1") 78: 79: (define_insn "cmpqi" 80: [(set (cc0) 81: (minus (match_operand:QI 0 "general_operand" "g") 82: (match_operand:QI 1 "general_operand" "g")))] 83: "" 84: "cmpb %0,%1") 85: 1.1.1.2 root 86: (define_insn "cmpdf" 87: [(set (cc0) 88: (minus (match_operand:DF 0 "general_operand" "gF") 89: (match_operand:DF 1 "general_operand" "gF")))] 90: "" 1.1.1.3 root 91: "cmp%# %0,%1") 1.1.1.2 root 92: 93: (define_insn "cmpsf" 94: [(set (cc0) 95: (minus (match_operand:SF 0 "general_operand" "gF") 96: (match_operand:SF 1 "general_operand" "gF")))] 97: "" 98: "cmpf %0,%1") 99: 1.1 root 100: (define_insn "" 101: [(set (cc0) 102: (and:SI (match_operand:SI 0 "general_operand" "g") 103: (match_operand:SI 1 "general_operand" "g")))] 104: "" 105: "bitl %0,%1") 106: 107: (define_insn "" 108: [(set (cc0) 109: (and:HI (match_operand:HI 0 "general_operand" "g") 110: (match_operand:HI 1 "general_operand" "g")))] 111: "" 112: "bitw %0,%1") 113: 114: (define_insn "" 115: [(set (cc0) 116: (and:QI (match_operand:QI 0 "general_operand" "g") 117: (match_operand:QI 1 "general_operand" "g")))] 118: "" 119: "bitb %0,%1") 120: 121: (define_insn "movdf" 122: [(set (match_operand:DF 0 "general_operand" "=g") 123: (match_operand:DF 1 "general_operand" "gF"))] 124: "" 125: "* 126: { 127: if (operands[1] == dconst0_rtx) 1.1.1.3 root 128: return \"clr%# %0\"; 129: return \"mov%# %1,%0\"; 1.1 root 130: }") 131: 132: (define_insn "movsf" 133: [(set (match_operand:SF 0 "general_operand" "=g") 134: (match_operand:SF 1 "general_operand" "gF"))] 135: "" 136: "* 137: { 138: if (operands[1] == fconst0_rtx) 139: return \"clrf %0\"; 140: return \"movf %1,%0\"; 141: }") 142: 1.1.1.2 root 143: ;; Some vaxes don't support this instruction. 144: ;;(define_insn "movti" 145: ;; [(set (match_operand:TI 0 "general_operand" "=g") 146: ;; (match_operand:TI 1 "general_operand" "g"))] 147: ;; "" 148: ;; "movh %1,%0") 1.1 root 149: 150: (define_insn "movdi" 151: [(set (match_operand:DI 0 "general_operand" "=g") 152: (match_operand:DI 1 "general_operand" "g"))] 153: "" 1.1.1.2 root 154: "movq %1,%0") 1.1 root 155: 156: (define_insn "movsi" 157: [(set (match_operand:SI 0 "general_operand" "=g") 158: (match_operand:SI 1 "general_operand" "g"))] 159: "" 160: "* 161: { if (operands[1] == const1_rtx 1.1.1.2 root 162: && REG_NOTES (insn) 163: && GET_MODE (REG_NOTES (insn)) == (enum machine_mode) REG_WAS_0 164: /* Make sure the insn that stored the 0 is still present. */ 165: && ! XEXP (REG_NOTES (insn), 0)->volatil 166: && GET_CODE (XEXP (REG_NOTES (insn), 0)) != NOTE) 167: /* Fastest way to change a 0 to a 1. */ 1.1 root 168: return \"incl %0\"; 169: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) 170: { 171: if (push_operand (operands[0], SImode)) 172: return \"pushab %a1\"; 173: return \"movab %a1,%0\"; 174: } 175: if (operands[1] == const0_rtx) 176: return \"clrl %0\"; 177: if (GET_CODE (operands[1]) == CONST_INT 178: && (unsigned) INTVAL (operands[1]) >= 64) 179: { 180: int i = INTVAL (operands[1]); 181: if ((unsigned)(-i) < 64) 182: { 183: operands[1] = gen_rtx (CONST_INT, VOIDmode, -i); 184: return \"mnegl %1,%0\"; 185: } 186: if ((unsigned)i < 0x100) 187: return \"movzbl %1,%0\"; 188: if (i >= -0x80 && i < 0) 189: return \"cvtbl %1,%0\"; 190: if ((unsigned)i < 0x10000) 191: return \"movzwl %1,%0\"; 192: if (i >= -0x8000 && i < 0) 193: return \"cvtwl %1,%0\"; 194: } 195: if (push_operand (operands[0], SImode)) 196: return \"pushl %1\"; 197: return \"movl %1,%0\"; 198: }") 199: 200: (define_insn "movhi" 201: [(set (match_operand:HI 0 "general_operand" "=g") 202: (match_operand:HI 1 "general_operand" "g"))] 203: "" 204: "* 205: { 206: if (operands[1] == const1_rtx 1.1.1.2 root 207: && REG_NOTES (insn) 1.1 root 208: && GET_MODE (REG_NOTES (insn)) == (enum machine_mode) REG_WAS_0) 209: return \"incw %0\"; 210: if (operands[1] == const0_rtx) 211: return \"clrw %0\"; 212: if (GET_CODE (operands[1]) == CONST_INT 213: && (unsigned) INTVAL (operands[1]) >= 64) 214: { 215: int i = INTVAL (operands[1]); 216: if ((unsigned)(-i) < 64) 217: { 218: operands[1] = gen_rtx (CONST_INT, VOIDmode, -i); 219: return \"mnegw %1,%0\"; 220: } 221: if ((unsigned)i < 0x100) 222: return \"movzbw %1,%0\"; 223: if (i >= -0x80 && i < 0) 224: return \"cvtbw %1,%0\"; 225: } 226: return \"movw %1,%0\"; 227: }") 228: 229: (define_insn "movqi" 230: [(set (match_operand:QI 0 "general_operand" "=g") 231: (match_operand:QI 1 "general_operand" "g"))] 232: "" 233: "* 234: { 235: if (operands[1] == const0_rtx) 236: return \"clrb %0\"; 237: return \"movb %1,%0\"; 238: }") 239: 240: ;; The definition of this insn does not really explain what it does, 241: ;; but it should suffice 242: ;; that anything generated as this insn will be recognized as one 243: ;; and that it won't successfully combine with anything. 244: (define_insn "movstrhi" 245: [(set (match_operand:BLK 0 "general_operand" "=g") 246: (match_operand:BLK 1 "general_operand" "g")) 247: (use (match_operand:HI 2 "general_operand" "g")) 1.1.1.2 root 248: (clobber (reg:SI 0)) 249: (clobber (reg:SI 1)) 250: (clobber (reg:SI 2)) 251: (clobber (reg:SI 3)) 252: (clobber (reg:SI 4)) 253: (clobber (reg:SI 5))] 1.1 root 254: "" 255: "movc3 %2,%1,%0") 256: 257: ;;- load or push effective address 258: ;; These come after the move patterns 259: ;; because we don't want pushl $1 turned into pushad 1. 260: 261: (define_insn "" 262: [(set (match_operand:SI 0 "general_operand" "=g") 263: (match_operand:QI 1 "address_operand" "p"))] 264: "" 265: "* 266: { 267: if (push_operand (operands[0], SImode)) 268: return \"pushab %a1\"; 269: return \"movab %a1,%0\"; 270: }") 271: 272: (define_insn "" 273: [(set (match_operand:SI 0 "general_operand" "=g") 274: (match_operand:HI 1 "address_operand" "p"))] 275: "" 276: "* 277: { 278: if (push_operand (operands[0], SImode)) 279: return \"pushaw %a1\"; 280: return \"movaw %a1,%0\"; 281: }") 282: 283: (define_insn "" 284: [(set (match_operand:SI 0 "general_operand" "=g") 285: (match_operand:SI 1 "address_operand" "p"))] 286: "" 287: "* 288: { 289: if (push_operand (operands[0], SImode)) 290: return \"pushal %a1\"; 291: return \"moval %a1,%0\"; 292: }") 293: 294: (define_insn "" 295: [(set (match_operand:SI 0 "general_operand" "=g") 296: (match_operand:SF 1 "address_operand" "p"))] 297: "" 298: "* 299: { 300: if (push_operand (operands[0], SImode)) 301: return \"pushaf %a1\"; 302: return \"movaf %a1,%0\"; 303: }") 304: 305: (define_insn "" 306: [(set (match_operand:SI 0 "general_operand" "=g") 307: (match_operand:DF 1 "address_operand" "p"))] 308: "" 309: "* 310: { 311: if (push_operand (operands[0], SImode)) 312: return \"pushad %a1\"; 313: return \"movad %a1,%0\"; 314: }") 315: 1.1.1.2 root 316: ;; Extension and truncation insns. 317: ;; Those for integer source operand 318: ;; are ordered widest source type first. 1.1 root 319: 1.1.1.2 root 320: (define_insn "truncsiqi2" 321: [(set (match_operand:QI 0 "general_operand" "=g") 322: (truncate:QI (match_operand:SI 1 "general_operand" "g")))] 1.1 root 323: "" 1.1.1.2 root 324: "cvtlb %1,%0") 1.1 root 325: 1.1.1.2 root 326: (define_insn "truncsihi2" 327: [(set (match_operand:HI 0 "general_operand" "=g") 328: (truncate:HI (match_operand:SI 1 "general_operand" "g")))] 1.1 root 329: "" 1.1.1.2 root 330: "cvtlw %1,%0") 1.1 root 331: 332: (define_insn "trunchiqi2" 333: [(set (match_operand:QI 0 "general_operand" "=g") 334: (truncate:QI (match_operand:HI 1 "general_operand" "g")))] 335: "" 336: "cvtwb %1,%0") 337: 338: (define_insn "extendhisi2" 339: [(set (match_operand:SI 0 "general_operand" "=g") 340: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))] 341: "" 342: "cvtwl %1,%0") 343: 1.1.1.2 root 344: (define_insn "extendqihi2" 345: [(set (match_operand:HI 0 "general_operand" "=g") 346: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))] 1.1 root 347: "" 1.1.1.2 root 348: "cvtbw %1,%0") 1.1 root 349: 1.1.1.2 root 350: (define_insn "extendqisi2" 351: [(set (match_operand:SI 0 "general_operand" "=g") 352: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))] 353: "" 354: "cvtbl %1,%0") 355: 356: (define_insn "extendsfdf2" 1.1 root 357: [(set (match_operand:DF 0 "general_operand" "=g") 1.1.1.2 root 358: (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))] 1.1 root 359: "" 1.1.1.3 root 360: "cvtf%# %1,%0") 1.1 root 361: 1.1.1.2 root 362: (define_insn "truncdfsf2" 363: [(set (match_operand:SF 0 "general_operand" "=g") 364: (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))] 1.1 root 365: "" 1.1.1.3 root 366: "cvt%#f %1,%0") 1.1 root 367: 1.1.1.2 root 368: (define_insn "zero_extendhisi2" 369: [(set (match_operand:SI 0 "general_operand" "=g") 370: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))] 371: "" 372: "movzwl %1,%0") 373: 374: (define_insn "zero_extendqihi2" 1.1 root 375: [(set (match_operand:HI 0 "general_operand" "=g") 1.1.1.2 root 376: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))] 1.1 root 377: "" 1.1.1.2 root 378: "movzbw %1,%0") 379: 380: (define_insn "zero_extendqisi2" 381: [(set (match_operand:SI 0 "general_operand" "=g") 382: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))] 383: "" 384: "movzbl %1,%0") 385: 386: ;; Fix-to-float conversion insns. 387: ;; Note that the ones that start with SImode come first. 388: ;; That is so that an operand that is a CONST_INT 389: ;; (and therefore lacks a specific machine mode). 390: ;; will be recognized as SImode (which is always valid) 391: ;; rather than as QImode or HImode. 1.1 root 392: 393: (define_insn "floatsisf2" 394: [(set (match_operand:SF 0 "general_operand" "=g") 395: (float:SF (match_operand:SI 1 "general_operand" "g")))] 396: "" 397: "cvtlf %1,%0") 398: 399: (define_insn "floatsidf2" 400: [(set (match_operand:DF 0 "general_operand" "=g") 401: (float:DF (match_operand:SI 1 "general_operand" "g")))] 402: "" 1.1.1.3 root 403: "cvtl%# %1,%0") 1.1 root 404: 1.1.1.2 root 405: (define_insn "floathisf2" 406: [(set (match_operand:SF 0 "general_operand" "=g") 407: (float:SF (match_operand:HI 1 "general_operand" "g")))] 1.1 root 408: "" 1.1.1.2 root 409: "cvtwf %1,%0") 1.1 root 410: 1.1.1.2 root 411: (define_insn "floathidf2" 412: [(set (match_operand:DF 0 "general_operand" "=g") 413: (float:DF (match_operand:HI 1 "general_operand" "g")))] 1.1 root 414: "" 1.1.1.3 root 415: "cvtw%# %1,%0") 1.1 root 416: 1.1.1.2 root 417: (define_insn "floatqisf2" 418: [(set (match_operand:SF 0 "general_operand" "=g") 419: (float:SF (match_operand:QI 1 "general_operand" "g")))] 1.1 root 420: "" 1.1.1.2 root 421: "cvtbf %1,%0") 1.1 root 422: 1.1.1.2 root 423: (define_insn "floatqidf2" 1.1 root 424: [(set (match_operand:DF 0 "general_operand" "=g") 1.1.1.2 root 425: (float:DF (match_operand:QI 1 "general_operand" "g")))] 1.1 root 426: "" 1.1.1.3 root 427: "cvtb%# %1,%0") 1.1.1.2 root 428: 429: ;; Float-to-fix conversion insns. 1.1 root 430: 1.1.1.2 root 431: (define_insn "fix_truncsfqi2" 1.1 root 432: [(set (match_operand:QI 0 "general_operand" "=g") 1.1.1.2 root 433: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))] 1.1 root 434: "" 1.1.1.2 root 435: "cvtfb %1,%0") 1.1 root 436: 1.1.1.2 root 437: (define_insn "fix_truncsfhi2" 1.1 root 438: [(set (match_operand:HI 0 "general_operand" "=g") 1.1.1.2 root 439: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))] 1.1 root 440: "" 1.1.1.2 root 441: "cvtfw %1,%0") 1.1 root 442: 1.1.1.2 root 443: (define_insn "fix_truncsfsi2" 1.1 root 444: [(set (match_operand:SI 0 "general_operand" "=g") 1.1.1.2 root 445: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))] 1.1 root 446: "" 1.1.1.2 root 447: "cvtfl %1,%0") 1.1 root 448: 1.1.1.2 root 449: (define_insn "fix_truncdfqi2" 450: [(set (match_operand:QI 0 "general_operand" "=g") 451: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))] 1.1 root 452: "" 1.1.1.2 root 453: "cvtdb %1,%0") 1.1 root 454: 1.1.1.2 root 455: (define_insn "fix_truncdfhi2" 1.1 root 456: [(set (match_operand:HI 0 "general_operand" "=g") 1.1.1.2 root 457: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))] 1.1 root 458: "" 1.1.1.3 root 459: "cvt%#w %1,%0") 1.1 root 460: 1.1.1.2 root 461: (define_insn "fix_truncdfsi2" 1.1 root 462: [(set (match_operand:SI 0 "general_operand" "=g") 1.1.1.2 root 463: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))] 1.1 root 464: "" 1.1.1.3 root 465: "cvt%#l %1,%0") 1.1 root 466: 467: ;;- All kinds of add instructions. 468: 469: (define_insn "adddf3" 470: [(set (match_operand:DF 0 "general_operand" "=g") 471: (plus:DF (match_operand:DF 1 "general_operand" "gF") 472: (match_operand:DF 2 "general_operand" "gF")))] 473: "" 474: "* 475: { 476: if (rtx_equal_p (operands[0], operands[1])) 1.1.1.3 root 477: return \"add%#2 %2,%0\"; 1.1 root 478: if (rtx_equal_p (operands[0], operands[2])) 1.1.1.3 root 479: return \"add%#2 %1,%0\"; 480: return \"add%#3 %1,%2,%0\"; 1.1 root 481: }") 482: 483: (define_insn "addsf3" 484: [(set (match_operand:SF 0 "general_operand" "=g") 485: (plus:SF (match_operand:SF 1 "general_operand" "gF") 486: (match_operand:SF 2 "general_operand" "gF")))] 487: "" 488: "* 489: { 490: if (rtx_equal_p (operands[0], operands[1])) 491: return \"addf2 %2,%0\"; 492: if (rtx_equal_p (operands[0], operands[2])) 493: return \"addf2 %1,%0\"; 494: return \"addf3 %1,%2,%0\"; 495: }") 496: 497: (define_insn "addsi3" 498: [(set (match_operand:SI 0 "general_operand" "=g") 499: (plus:SI (match_operand:SI 1 "general_operand" "g") 500: (match_operand:SI 2 "general_operand" "g")))] 501: "" 502: "* 503: { 504: if (rtx_equal_p (operands[0], operands[1])) 505: { 506: if (operands[2] == const1_rtx) 507: return \"incl %0\"; 1.1.1.2 root 508: if (GET_CODE (operands[2]) == CONST_INT 509: && INTVAL (operands[2]) == -1) 1.1 root 510: return \"decl %0\"; 511: if (GET_CODE (operands[2]) == CONST_INT 512: && (unsigned) (- INTVAL (operands[2])) < 64) 513: return \"subl2 $%n2,%0\"; 514: return \"addl2 %2,%0\"; 515: } 516: if (rtx_equal_p (operands[0], operands[2])) 517: return \"addl2 %1,%0\"; 518: if (GET_CODE (operands[2]) == CONST_INT 519: && GET_CODE (operands[1]) == REG) 520: { 521: if (push_operand (operands[0], SImode)) 522: return \"pushab %c2(%1)\"; 523: return \"movab %c2(%1),%0\"; 524: } 525: if (GET_CODE (operands[2]) == CONST_INT 526: && (unsigned) (- INTVAL (operands[2])) < 64) 527: return \"subl3 $%n2,%1,%0\"; 528: return \"addl3 %1,%2,%0\"; 529: }") 530: 531: (define_insn "addhi3" 532: [(set (match_operand:HI 0 "general_operand" "=g") 533: (plus:HI (match_operand:HI 1 "general_operand" "g") 534: (match_operand:HI 2 "general_operand" "g")))] 535: "" 536: "* 537: { 538: if (rtx_equal_p (operands[0], operands[1])) 539: { 540: if (operands[2] == const1_rtx) 541: return \"incw %0\"; 542: if (GET_CODE (operands[1]) == CONST_INT 543: && INTVAL (operands[1]) == -1) 544: return \"decw %0\"; 545: if (GET_CODE (operands[2]) == CONST_INT 546: && (unsigned) (- INTVAL (operands[2])) < 64) 547: return \"subw2 $%n2,%0\"; 548: return \"addw2 %2,%0\"; 549: } 550: if (rtx_equal_p (operands[0], operands[2])) 551: return \"addw2 %1,%0\"; 552: if (GET_CODE (operands[2]) == CONST_INT 553: && (unsigned) (- INTVAL (operands[2])) < 64) 554: return \"subw3 $%n2,%1,%0\"; 555: return \"addw3 %1,%2,%0\"; 556: }") 557: 558: (define_insn "addqi3" 559: [(set (match_operand:QI 0 "general_operand" "=g") 560: (plus:QI (match_operand:QI 1 "general_operand" "g") 561: (match_operand:QI 2 "general_operand" "g")))] 562: "" 563: "* 564: { 565: if (rtx_equal_p (operands[0], operands[1])) 566: { 567: if (operands[2] == const1_rtx) 568: return \"incb %0\"; 569: if (GET_CODE (operands[1]) == CONST_INT 570: && INTVAL (operands[1]) == -1) 571: return \"decb %0\"; 572: if (GET_CODE (operands[2]) == CONST_INT 573: && (unsigned) (- INTVAL (operands[2])) < 64) 574: return \"subb2 $%n2,%0\"; 575: return \"addb2 %2,%0\"; 576: } 577: if (rtx_equal_p (operands[0], operands[2])) 578: return \"addb2 %1,%0\"; 579: if (GET_CODE (operands[2]) == CONST_INT 580: && (unsigned) (- INTVAL (operands[2])) < 64) 581: return \"subb3 $%n2,%1,%0\"; 582: return \"addb3 %1,%2,%0\"; 583: }") 584: 585: ;;- All kinds of subtract instructions. 586: 587: (define_insn "subdf3" 588: [(set (match_operand:DF 0 "general_operand" "=g") 589: (minus:DF (match_operand:DF 1 "general_operand" "gF") 590: (match_operand:DF 2 "general_operand" "gF")))] 591: "" 592: "* 593: { 594: if (rtx_equal_p (operands[0], operands[1])) 1.1.1.3 root 595: return \"sub%#2 %2,%0\"; 596: return \"sub%#3 %2,%1,%0\"; 1.1 root 597: }") 598: 599: (define_insn "subsf3" 600: [(set (match_operand:SF 0 "general_operand" "=g") 601: (minus:SF (match_operand:SF 1 "general_operand" "gF") 602: (match_operand:SF 2 "general_operand" "gF")))] 603: "" 604: "* 605: { 606: if (rtx_equal_p (operands[0], operands[1])) 607: return \"subf2 %2,%0\"; 608: return \"subf3 %2,%1,%0\"; 609: }") 610: 611: (define_insn "subsi3" 612: [(set (match_operand:SI 0 "general_operand" "=g") 613: (minus:SI (match_operand:SI 1 "general_operand" "g") 614: (match_operand:SI 2 "general_operand" "g")))] 615: "" 616: "* 617: { 618: if (rtx_equal_p (operands[0], operands[1])) 619: { 620: if (operands[2] == const1_rtx) 621: return \"decl %0\"; 622: return \"subl2 %2,%0\"; 623: } 624: return \"subl3 %2,%1,%0\"; 625: }") 626: 627: (define_insn "subhi3" 628: [(set (match_operand:HI 0 "general_operand" "=g") 629: (minus:HI (match_operand:HI 1 "general_operand" "g") 630: (match_operand:HI 2 "general_operand" "g")))] 631: "" 632: "* 633: { 634: if (rtx_equal_p (operands[0], operands[1])) 635: { 636: if (operands[2] == const1_rtx) 637: return \"decw %0\"; 638: return \"subw2 %2,%0\"; 639: } 640: return \"subw3 %2,%1,%0\"; 641: }") 642: 643: (define_insn "subqi3" 644: [(set (match_operand:QI 0 "general_operand" "=g") 645: (minus:QI (match_operand:QI 1 "general_operand" "g") 646: (match_operand:QI 2 "general_operand" "g")))] 647: "" 648: "* 649: { 650: if (rtx_equal_p (operands[0], operands[1])) 651: { 652: if (operands[2] == const1_rtx) 653: return \"decb %0\"; 654: return \"subb2 %2,%0\"; 655: } 656: return \"subb3 %2,%1,%0\"; 657: }") 658: 659: ;;- Multiply instructions. 660: 661: (define_insn "muldf3" 662: [(set (match_operand:DF 0 "general_operand" "=g") 663: (mult:DF (match_operand:DF 1 "general_operand" "gF") 664: (match_operand:DF 2 "general_operand" "gF")))] 665: "" 666: "* 667: { 668: if (rtx_equal_p (operands[0], operands[1])) 1.1.1.3 root 669: return \"mul%#2 %2,%0\"; 1.1 root 670: if (rtx_equal_p (operands[0], operands[2])) 1.1.1.3 root 671: return \"mul%#2 %1,%0\"; 672: return \"mul%#3 %1,%2,%0\"; 1.1 root 673: }") 674: 675: (define_insn "mulsf3" 676: [(set (match_operand:SF 0 "general_operand" "=g") 677: (mult:SF (match_operand:SF 1 "general_operand" "gF") 678: (match_operand:SF 2 "general_operand" "gF")))] 679: "" 680: "* 681: { 682: if (rtx_equal_p (operands[0], operands[1])) 683: return \"mulf2 %2,%0\"; 684: if (rtx_equal_p (operands[0], operands[2])) 685: return \"mulf2 %1,%0\"; 686: return \"mulf3 %1,%2,%0\"; 687: }") 688: 689: (define_insn "mulsi3" 690: [(set (match_operand:SI 0 "general_operand" "=g") 691: (mult:SI (match_operand:SI 1 "general_operand" "g") 692: (match_operand:SI 2 "general_operand" "g")))] 693: "" 694: "* 695: { 696: if (rtx_equal_p (operands[0], operands[1])) 697: return \"mull2 %2,%0\"; 698: if (rtx_equal_p (operands[0], operands[2])) 699: return \"mull2 %1,%0\"; 700: return \"mull3 %1,%2,%0\"; 701: }") 702: 703: (define_insn "mulhi3" 704: [(set (match_operand:HI 0 "general_operand" "=g") 705: (mult:HI (match_operand:HI 1 "general_operand" "g") 706: (match_operand:HI 2 "general_operand" "g")))] 707: "" 708: "* 709: { 710: if (rtx_equal_p (operands[0], operands[1])) 711: return \"mulw2 %2,%0\"; 712: if (rtx_equal_p (operands[0], operands[2])) 713: return \"mulw2 %1,%0\"; 714: return \"mulw3 %1,%2,%0\"; 715: }") 716: 717: (define_insn "mulqi3" 718: [(set (match_operand:QI 0 "general_operand" "=g") 719: (mult:QI (match_operand:QI 1 "general_operand" "g") 720: (match_operand:QI 2 "general_operand" "g")))] 721: "" 722: "* 723: { 724: if (rtx_equal_p (operands[0], operands[1])) 725: return \"mulb2 %2,%0\"; 726: if (rtx_equal_p (operands[0], operands[2])) 727: return \"mulb2 %1,%0\"; 728: return \"mulb3 %1,%2,%0\"; 729: }") 730: 731: ;;- Divide instructions. 732: 733: (define_insn "divdf3" 734: [(set (match_operand:DF 0 "general_operand" "=g") 735: (div:DF (match_operand:DF 1 "general_operand" "gF") 736: (match_operand:DF 2 "general_operand" "gF")))] 737: "" 738: "* 739: { 740: if (rtx_equal_p (operands[0], operands[1])) 1.1.1.3 root 741: return \"div%#2 %2,%0\"; 742: return \"div%#3 %2,%1,%0\"; 1.1 root 743: }") 744: 745: (define_insn "divsf3" 746: [(set (match_operand:SF 0 "general_operand" "=g") 747: (div:SF (match_operand:SF 1 "general_operand" "gF") 748: (match_operand:SF 2 "general_operand" "gF")))] 749: "" 750: "* 751: { 752: if (rtx_equal_p (operands[0], operands[1])) 753: return \"divf2 %2,%0\"; 754: return \"divf3 %2,%1,%0\"; 755: }") 756: 757: (define_insn "divsi3" 758: [(set (match_operand:SI 0 "general_operand" "=g") 759: (div:SI (match_operand:SI 1 "general_operand" "g") 760: (match_operand:SI 2 "general_operand" "g")))] 761: "" 762: "* 763: { 764: if (rtx_equal_p (operands[0], operands[1])) 765: return \"divl2 %2,%0\"; 766: return \"divl3 %2,%1,%0\"; 767: }") 768: 769: (define_insn "divhi3" 770: [(set (match_operand:HI 0 "general_operand" "=g") 771: (div:HI (match_operand:HI 1 "general_operand" "g") 772: (match_operand:HI 2 "general_operand" "g")))] 773: "" 774: "* 775: { 776: if (rtx_equal_p (operands[0], operands[1])) 777: return \"divw2 %2,%0\"; 778: return \"divw3 %2,%1,%0\"; 779: }") 780: 781: (define_insn "divqi3" 782: [(set (match_operand:QI 0 "general_operand" "=g") 783: (div:QI (match_operand:QI 1 "general_operand" "g") 784: (match_operand:QI 2 "general_operand" "g")))] 785: "" 786: "* 787: { 788: if (rtx_equal_p (operands[0], operands[1])) 789: return \"divb2 %2,%0\"; 790: return \"divb3 %2,%1,%0\"; 791: }") 792: 793: ;This is left out because it is very slow; 794: ;we are better off programming around the "lack" of this insn. 795: ;(define_insn "divmoddisi4" 796: ; [(set (match_operand:SI 0 "general_operand" "=g") 797: ; (div:SI (match_operand:DI 1 "general_operand" "g") 798: ; (match_operand:SI 2 "general_operand" "g"))) 799: ; (set (match_operand:SI 3 "general_operand" "=g") 800: ; (mod:SI (match_operand:DI 1 "general_operand" "g") 801: ; (match_operand:SI 2 "general_operand" "g")))] 802: ; "" 803: ; "ediv %2,%1,%0,%3") 804: 805: (define_insn "andcbsi3" 806: [(set (match_operand:SI 0 "general_operand" "=g") 807: (and:SI (match_operand:SI 1 "general_operand" "g") 808: (not:SI (match_operand:SI 2 "general_operand" "g"))))] 809: "" 810: "* 811: { 812: if (rtx_equal_p (operands[0], operands[1])) 813: return \"bicl2 %2,%0\"; 814: return \"bicl3 %2,%1,%0\"; 815: }") 816: 817: (define_insn "andcbhi3" 818: [(set (match_operand:HI 0 "general_operand" "=g") 819: (and:HI (match_operand:HI 1 "general_operand" "g") 820: (not:HI (match_operand:HI 2 "general_operand" "g"))))] 821: "" 822: "* 823: { 824: if (rtx_equal_p (operands[0], operands[1])) 825: return \"bicw2 %2,%0\"; 826: return \"bicw3 %2,%1,%0\"; 827: }") 828: 829: (define_insn "andcbqi3" 830: [(set (match_operand:QI 0 "general_operand" "=g") 831: (and:QI (match_operand:QI 1 "general_operand" "g") 832: (not:QI (match_operand:QI 2 "general_operand" "g"))))] 833: "" 834: "* 835: { 836: if (rtx_equal_p (operands[0], operands[1])) 837: return \"bicb2 %2,%0\"; 838: return \"bicb3 %2,%1,%0\"; 839: }") 840: 841: ;; The following are needed because constant propagation can 842: ;; create them starting from the bic insn patterns above. 843: 844: (define_insn "" 845: [(set (match_operand:SI 0 "general_operand" "=g") 846: (and:SI (match_operand:SI 1 "general_operand" "g") 847: (match_operand:SI 2 "general_operand" "g")))] 848: "GET_CODE (operands[2]) == CONST_INT" 849: "* 850: { operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2])); 851: if (rtx_equal_p (operands[1], operands[0])) 852: return \"bicl2 %2,%0\"; 853: return \"bicl3 %2,%1,%0\"; 854: }") 855: 856: (define_insn "" 857: [(set (match_operand:HI 0 "general_operand" "=g") 858: (and:HI (match_operand:HI 1 "general_operand" "g") 859: (match_operand:HI 2 "general_operand" "g")))] 860: "GET_CODE (operands[2]) == CONST_INT" 861: "* 862: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xffff & ~INTVAL (operands[2])); 863: if (rtx_equal_p (operands[1], operands[0])) 864: return \"bicw2 %2,%0\"; 865: return \"bicw3 %2,%1,%0\"; 866: }") 867: 868: (define_insn "" 869: [(set (match_operand:QI 0 "general_operand" "=g") 870: (and:QI (match_operand:QI 1 "general_operand" "g") 871: (match_operand:QI 2 "general_operand" "g")))] 872: "GET_CODE (operands[2]) == CONST_INT" 873: "* 874: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xff & ~INTVAL (operands[2])); 875: if (rtx_equal_p (operands[1], operands[0])) 876: return \"bicb2 %2,%0\"; 877: return \"bicb3 %2,%1,%0\"; 878: }") 879: 880: ;;- Bit set instructions. 881: 882: (define_insn "iorsi3" 883: [(set (match_operand:SI 0 "general_operand" "=g") 884: (ior:SI (match_operand:SI 1 "general_operand" "g") 885: (match_operand:SI 2 "general_operand" "g")))] 886: "" 887: "* 888: { 889: if (rtx_equal_p (operands[0], operands[1])) 890: return \"bisl2 %2,%0\"; 891: if (rtx_equal_p (operands[0], operands[2])) 892: return \"bisl2 %1,%0\"; 893: return \"bisl3 %2,%1,%0\"; 894: }") 895: 896: (define_insn "iorhi3" 897: [(set (match_operand:HI 0 "general_operand" "=g") 898: (ior:HI (match_operand:HI 1 "general_operand" "g") 899: (match_operand:HI 2 "general_operand" "g")))] 900: "" 901: "* 902: { 903: if (rtx_equal_p (operands[0], operands[1])) 904: return \"bisw2 %2,%0\"; 905: if (rtx_equal_p (operands[0], operands[2])) 906: return \"bisw2 %1,%0\"; 907: return \"bisw3 %2,%1,%0\"; 908: }") 909: 910: (define_insn "iorqi3" 911: [(set (match_operand:QI 0 "general_operand" "=g") 912: (ior:QI (match_operand:QI 1 "general_operand" "g") 913: (match_operand:QI 2 "general_operand" "g")))] 914: "" 915: "* 916: { 917: if (rtx_equal_p (operands[0], operands[1])) 918: return \"bisb2 %2,%0\"; 919: if (rtx_equal_p (operands[0], operands[2])) 920: return \"bisb2 %1,%0\"; 921: return \"bisb3 %2,%1,%0\"; 922: }") 923: 924: ;;- xor instructions. 925: 926: (define_insn "xorsi3" 927: [(set (match_operand:SI 0 "general_operand" "=g") 928: (xor:SI (match_operand:SI 1 "general_operand" "g") 929: (match_operand:SI 2 "general_operand" "g")))] 930: "" 931: "* 932: { 933: if (rtx_equal_p (operands[0], operands[1])) 934: return \"xorl2 %2,%0\"; 935: if (rtx_equal_p (operands[0], operands[2])) 936: return \"xorl2 %1,%0\"; 937: return \"xorl3 %2,%1,%0\"; 938: }") 939: 940: (define_insn "xorhi3" 941: [(set (match_operand:HI 0 "general_operand" "=g") 942: (xor:HI (match_operand:HI 1 "general_operand" "g") 943: (match_operand:HI 2 "general_operand" "g")))] 944: "" 945: "* 946: { 947: if (rtx_equal_p (operands[0], operands[1])) 948: return \"xorw2 %2,%0\"; 949: if (rtx_equal_p (operands[0], operands[2])) 950: return \"xorw2 %1,%0\"; 951: return \"xorw3 %2,%1,%0\"; 952: }") 953: 954: (define_insn "xorqi3" 955: [(set (match_operand:QI 0 "general_operand" "=g") 956: (xor:QI (match_operand:QI 1 "general_operand" "g") 957: (match_operand:QI 2 "general_operand" "g")))] 958: "" 959: "* 960: { 961: if (rtx_equal_p (operands[0], operands[1])) 962: return \"xorb2 %2,%0\"; 963: if (rtx_equal_p (operands[0], operands[2])) 964: return \"xorb2 %1,%0\"; 965: return \"xorb3 %2,%1,%0\"; 966: }") 967: 968: (define_insn "negdf2" 969: [(set (match_operand:DF 0 "general_operand" "=g") 970: (neg:DF (match_operand:DF 1 "general_operand" "gF")))] 971: "" 1.1.1.3 root 972: "mneg%# %1,%0") 1.1 root 973: 974: (define_insn "negsf2" 975: [(set (match_operand:SF 0 "general_operand" "=g") 976: (neg:SF (match_operand:SF 1 "general_operand" "gF")))] 977: "" 978: "mnegf %1,%0") 979: 980: (define_insn "negsi2" 981: [(set (match_operand:SI 0 "general_operand" "=g") 982: (neg:SI (match_operand:SI 1 "general_operand" "g")))] 983: "" 984: "mnegl %1,%0") 985: 986: (define_insn "neghi2" 987: [(set (match_operand:HI 0 "general_operand" "=g") 988: (neg:HI (match_operand:HI 1 "general_operand" "g")))] 989: "" 990: "mnegw %1,%0") 991: 992: (define_insn "negqi2" 993: [(set (match_operand:QI 0 "general_operand" "=g") 994: (neg:QI (match_operand:QI 1 "general_operand" "g")))] 995: "" 996: "mnegb %1,%0") 997: 998: (define_insn "one_cmplsi2" 999: [(set (match_operand:SI 0 "general_operand" "=g") 1000: (not:SI (match_operand:SI 1 "general_operand" "g")))] 1001: "" 1002: "mcoml %1,%0") 1003: 1004: (define_insn "one_cmplhi2" 1005: [(set (match_operand:HI 0 "general_operand" "=g") 1006: (not:HI (match_operand:HI 1 "general_operand" "g")))] 1007: "" 1008: "mcomw %1,%0") 1009: 1010: (define_insn "one_cmplqi2" 1011: [(set (match_operand:QI 0 "general_operand" "=g") 1012: (not:QI (match_operand:QI 1 "general_operand" "g")))] 1013: "" 1014: "mcomb %1,%0") 1015: 1016: (define_insn "ashlsi3" 1017: [(set (match_operand:SI 0 "general_operand" "=g") 1018: (ashift:SI (match_operand:SI 1 "general_operand" "g") 1019: (match_operand:QI 2 "general_operand" "g")))] 1020: "" 1.1.1.2 root 1021: "* 1022: { 1023: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1])) 1024: return \"addl2 %0,%0\"; 1025: return \"ashl %2,%1,%0\"; 1026: }") 1.1 root 1027: 1028: (define_insn "ashldi3" 1029: [(set (match_operand:DI 0 "general_operand" "=g") 1030: (ashift:DI (match_operand:DI 1 "general_operand" "g") 1031: (match_operand:QI 2 "general_operand" "g")))] 1032: "" 1033: "ashq %2,%1,%0") 1034: 1035: (define_insn "rotlsi3" 1036: [(set (match_operand:SI 0 "general_operand" "=g") 1037: (rotate:SI (match_operand:SI 1 "general_operand" "g") 1038: (match_operand:QI 2 "general_operand" "g")))] 1039: "" 1040: "rotl %2,%1,%0") 1041: 1042: (define_insn "rotldi3" 1043: [(set (match_operand:DI 0 "general_operand" "=g") 1044: (rotate:DI (match_operand:DI 1 "general_operand" "g") 1045: (match_operand:QI 2 "general_operand" "g")))] 1046: "" 1047: "rotq %2,%1,%0") 1048: 1.1.1.2 root 1049: ;This insn is probably slower than a multiply and an add. 1050: ;(define_insn "" 1051: ; [(set (match_operand:SI 0 "general_operand" "=g") 1052: ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g") 1053: ; (match_operand:SI 2 "general_operand" "g")) 1054: ; (match_operand:SI 3 "general_operand" "g")))] 1055: ; "" 1056: ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0") 1.1.1.4 ! root 1057: ! 1058: ;; Special cases of bit-field insns which we should ! 1059: ;; recognize in preference to the general case. ! 1060: ;; These handle aligned 8-bit and 16-bit fields, ! 1061: ;; which can usually be done with move instructions. ! 1062: ! 1063: (define_insn "" ! 1064: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro") ! 1065: (match_operand:SI 1 "immediate_operand" "i") ! 1066: (match_operand:SI 2 "immediate_operand" "i")) ! 1067: (match_operand:SI 3 "general_operand" "g"))] ! 1068: "GET_CODE (operands[1]) == CONST_INT ! 1069: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) ! 1070: && GET_CODE (operands[2]) == CONST_INT ! 1071: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 ! 1072: && (GET_CODE (operands[0]) == REG ! 1073: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" ! 1074: "* ! 1075: { ! 1076: if (REG_P (operands[0])) ! 1077: { ! 1078: if (INTVAL (operands[2]) != 0) ! 1079: return \"insv %3,%2,%1,%0\"; ! 1080: } ! 1081: else ! 1082: operands[0] ! 1083: = adj_offsetable_operand (operands[0], INTVAL (operands[2]) / 8); ! 1084: ! 1085: if (INTVAL (operands[1]) == 8) ! 1086: return \"movb %3,%0\"; ! 1087: return \"movw %3,%0\"; ! 1088: }") ! 1089: ! 1090: (define_insn "" ! 1091: [(set (match_operand:SI 0 "general_operand" "=&g") ! 1092: (zero_extract:SI (match_operand:SI 1 "general_operand" "ro") ! 1093: (match_operand:SI 2 "immediate_operand" "i") ! 1094: (match_operand:SI 3 "immediate_operand" "i")))] ! 1095: "GET_CODE (operands[2]) == CONST_INT ! 1096: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) ! 1097: && GET_CODE (operands[3]) == CONST_INT ! 1098: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 ! 1099: && (GET_CODE (operands[1]) == REG ! 1100: || ! mode_dependent_address_p (XEXP (operands[1], 0)))" ! 1101: "* ! 1102: { ! 1103: if (REG_P (operands[1])) ! 1104: { ! 1105: if (INTVAL (operands[3]) != 0) ! 1106: return \"extzv %3,%2,%1,%0\"; ! 1107: } ! 1108: else ! 1109: operands[1] ! 1110: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8); ! 1111: ! 1112: if (INTVAL (operands[2]) == 8) ! 1113: return \"movzbl %1,%0\"; ! 1114: return \"movzwl %1,%0\"; ! 1115: }") ! 1116: ! 1117: (define_insn "" ! 1118: [(set (match_operand:SI 0 "general_operand" "=g") ! 1119: (sign_extract:SI (match_operand:SI 1 "general_operand" "ro") ! 1120: (match_operand:SI 2 "immediate_operand" "i") ! 1121: (match_operand:SI 3 "immediate_operand" "i")))] ! 1122: "GET_CODE (operands[2]) == CONST_INT ! 1123: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) ! 1124: && GET_CODE (operands[3]) == CONST_INT ! 1125: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 ! 1126: && (GET_CODE (operands[1]) == REG ! 1127: || ! mode_dependent_address_p (XEXP (operands[1], 0)))" ! 1128: "* ! 1129: { ! 1130: if (REG_P (operands[1])) ! 1131: { ! 1132: if (INTVAL (operands[3]) != 0) ! 1133: return \"extv %3,%2,%1,%0\"; ! 1134: } ! 1135: else ! 1136: operands[1] ! 1137: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8); ! 1138: ! 1139: if (INTVAL (operands[2]) == 8) ! 1140: return \"cvtbl %1,%0\"; ! 1141: return \"cvtwl %1,%0\"; ! 1142: }") ! 1143: ! 1144: ;; Register-only SImode cases of bit-field insns. 1.1 root 1145: 1146: (define_insn "" 1147: [(set (cc0) 1148: (minus 1.1.1.4 ! root 1149: (sign_extract:SI (match_operand:SI 0 "general_operand" "r") 1.1 root 1150: (match_operand:SI 1 "general_operand" "g") 1151: (match_operand:SI 2 "general_operand" "g")) 1152: (match_operand:SI 3 "general_operand" "g")))] 1153: "" 1154: "cmpv %2,%1,%0,%3") 1155: 1156: (define_insn "" 1157: [(set (cc0) 1158: (minus 1.1.1.4 ! root 1159: (zero_extract:SI (match_operand:SI 0 "general_operand" "r") 1.1 root 1160: (match_operand:SI 1 "general_operand" "g") 1161: (match_operand:SI 2 "general_operand" "g")) 1162: (match_operand:SI 3 "general_operand" "g")))] 1163: "" 1164: "cmpzv %2,%1,%0,%3") 1165: 1.1.1.4 ! root 1166: (define_insn "" 1.1 root 1167: [(set (match_operand:SI 0 "general_operand" "=g") 1.1.1.4 ! root 1168: (sign_extract:SI (match_operand:SI 1 "general_operand" "r") 1.1 root 1169: (match_operand:SI 2 "general_operand" "g") 1170: (match_operand:SI 3 "general_operand" "g")))] 1171: "" 1172: "extv %3,%2,%1,%0") 1173: 1.1.1.4 ! root 1174: (define_insn "" 1.1 root 1175: [(set (match_operand:SI 0 "general_operand" "=g") 1.1.1.4 ! root 1176: (zero_extract:SI (match_operand:SI 1 "general_operand" "r") 1.1 root 1177: (match_operand:SI 2 "general_operand" "g") 1178: (match_operand:SI 3 "general_operand" "g")))] 1179: "" 1180: "extzv %3,%2,%1,%0") 1181: 1.1.1.4 ! root 1182: ;; Non-register cases. ! 1183: ;; nonimmediate_operand is used to make sure that mode-ambiguous cases ! 1184: ;; don't match these (and therefore match the cases above instead). ! 1185: 1.1 root 1186: (define_insn "" 1.1.1.4 ! root 1187: [(set (cc0) ! 1188: (minus ! 1189: (sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm") ! 1190: (match_operand:SI 1 "general_operand" "g") ! 1191: (match_operand:SI 2 "general_operand" "g")) ! 1192: (match_operand:SI 3 "general_operand" "g")))] ! 1193: "" ! 1194: "cmpv %2,%1,%0,%3") ! 1195: ! 1196: (define_insn "" ! 1197: [(set (cc0) ! 1198: (minus ! 1199: (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm") ! 1200: (match_operand:SI 1 "general_operand" "g") ! 1201: (match_operand:SI 2 "general_operand" "g")) ! 1202: (match_operand:SI 3 "general_operand" "g")))] ! 1203: "" ! 1204: "cmpzv %2,%1,%0,%3") ! 1205: ! 1206: (define_insn "extv" 1.1 root 1207: [(set (match_operand:SI 0 "general_operand" "=g") 1.1.1.4 ! root 1208: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm") 1.1 root 1209: (match_operand:SI 2 "general_operand" "g") 1210: (match_operand:SI 3 "general_operand" "g")))] 1211: "" 1212: "extv %3,%2,%1,%0") 1213: 1.1.1.4 ! root 1214: (define_insn "extzv" 1.1 root 1215: [(set (match_operand:SI 0 "general_operand" "=g") 1.1.1.4 ! root 1216: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm") 1.1 root 1217: (match_operand:SI 2 "general_operand" "g") 1218: (match_operand:SI 3 "general_operand" "g")))] 1219: "" 1220: "extzv %3,%2,%1,%0") 1221: 1222: (define_insn "insv" 1.1.1.2 root 1223: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g") 1.1 root 1224: (match_operand:SI 1 "general_operand" "g") 1225: (match_operand:SI 2 "general_operand" "g")) 1226: (match_operand:SI 3 "general_operand" "g"))] 1227: "" 1228: "insv %3,%2,%1,%0") 1229: 1230: (define_insn "" 1.1.1.2 root 1231: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 1.1 root 1232: (match_operand:SI 1 "general_operand" "g") 1233: (match_operand:SI 2 "general_operand" "g")) 1234: (match_operand:SI 3 "general_operand" "g"))] 1235: "" 1236: "insv %3,%2,%1,%0") 1237: 1238: (define_insn "jump" 1239: [(set (pc) 1240: (label_ref (match_operand 0 "" "")))] 1241: "" 1242: "jbr %l0") 1243: 1244: (define_insn "beq" 1245: [(set (pc) 1246: (if_then_else (eq (cc0) 1247: (const_int 0)) 1248: (label_ref (match_operand 0 "" "")) 1249: (pc)))] 1250: "" 1251: "jeql %l0") 1252: 1253: (define_insn "bne" 1254: [(set (pc) 1255: (if_then_else (ne (cc0) 1256: (const_int 0)) 1257: (label_ref (match_operand 0 "" "")) 1258: (pc)))] 1259: "" 1260: "jneq %l0") 1261: 1262: (define_insn "bgt" 1263: [(set (pc) 1264: (if_then_else (gt (cc0) 1265: (const_int 0)) 1266: (label_ref (match_operand 0 "" "")) 1267: (pc)))] 1268: "" 1269: "jgtr %l0") 1270: 1271: (define_insn "bgtu" 1272: [(set (pc) 1273: (if_then_else (gtu (cc0) 1274: (const_int 0)) 1275: (label_ref (match_operand 0 "" "")) 1276: (pc)))] 1277: "" 1278: "jgtru %l0") 1279: 1280: (define_insn "blt" 1281: [(set (pc) 1282: (if_then_else (lt (cc0) 1283: (const_int 0)) 1284: (label_ref (match_operand 0 "" "")) 1285: (pc)))] 1286: "" 1287: "jlss %l0") 1288: 1289: (define_insn "bltu" 1290: [(set (pc) 1291: (if_then_else (ltu (cc0) 1292: (const_int 0)) 1293: (label_ref (match_operand 0 "" "")) 1294: (pc)))] 1295: "" 1296: "jlssu %l0") 1297: 1298: (define_insn "bge" 1299: [(set (pc) 1300: (if_then_else (ge (cc0) 1301: (const_int 0)) 1302: (label_ref (match_operand 0 "" "")) 1303: (pc)))] 1304: "" 1305: "jgeq %l0") 1306: 1307: (define_insn "bgeu" 1308: [(set (pc) 1309: (if_then_else (geu (cc0) 1310: (const_int 0)) 1311: (label_ref (match_operand 0 "" "")) 1312: (pc)))] 1313: "" 1314: "jgequ %l0") 1315: 1316: (define_insn "ble" 1317: [(set (pc) 1318: (if_then_else (le (cc0) 1319: (const_int 0)) 1320: (label_ref (match_operand 0 "" "")) 1321: (pc)))] 1322: "" 1323: "jleq %l0") 1324: 1325: (define_insn "bleu" 1326: [(set (pc) 1327: (if_then_else (leu (cc0) 1328: (const_int 0)) 1329: (label_ref (match_operand 0 "" "")) 1330: (pc)))] 1331: "" 1332: "jlequ %l0") 1333: 1334: (define_insn "" 1335: [(set (pc) 1336: (if_then_else (eq (cc0) 1337: (const_int 0)) 1338: (pc) 1339: (label_ref (match_operand 0 "" ""))))] 1340: "" 1341: "jneq %l0") 1342: 1343: (define_insn "" 1344: [(set (pc) 1345: (if_then_else (ne (cc0) 1346: (const_int 0)) 1347: (pc) 1348: (label_ref (match_operand 0 "" ""))))] 1349: "" 1350: "jeql %l0") 1351: 1352: (define_insn "" 1353: [(set (pc) 1354: (if_then_else (gt (cc0) 1355: (const_int 0)) 1356: (pc) 1357: (label_ref (match_operand 0 "" ""))))] 1358: "" 1359: "jleq %l0") 1360: 1361: (define_insn "" 1362: [(set (pc) 1363: (if_then_else (gtu (cc0) 1364: (const_int 0)) 1365: (pc) 1366: (label_ref (match_operand 0 "" ""))))] 1367: "" 1368: "jlequ %l0") 1369: 1370: (define_insn "" 1371: [(set (pc) 1372: (if_then_else (lt (cc0) 1373: (const_int 0)) 1374: (pc) 1375: (label_ref (match_operand 0 "" ""))))] 1376: "" 1377: "jgeq %l0") 1378: 1379: (define_insn "" 1380: [(set (pc) 1381: (if_then_else (ltu (cc0) 1382: (const_int 0)) 1383: (pc) 1384: (label_ref (match_operand 0 "" ""))))] 1385: "" 1386: "jgequ %l0") 1387: 1388: (define_insn "" 1389: [(set (pc) 1390: (if_then_else (ge (cc0) 1391: (const_int 0)) 1392: (pc) 1393: (label_ref (match_operand 0 "" ""))))] 1394: "" 1395: "jlss %l0") 1396: 1397: (define_insn "" 1398: [(set (pc) 1399: (if_then_else (geu (cc0) 1400: (const_int 0)) 1401: (pc) 1402: (label_ref (match_operand 0 "" ""))))] 1403: "" 1404: "jlssu %l0") 1405: 1406: (define_insn "" 1407: [(set (pc) 1408: (if_then_else (le (cc0) 1409: (const_int 0)) 1410: (pc) 1411: (label_ref (match_operand 0 "" ""))))] 1412: "" 1413: "jgtr %l0") 1414: 1415: (define_insn "" 1416: [(set (pc) 1417: (if_then_else (leu (cc0) 1418: (const_int 0)) 1419: (pc) 1420: (label_ref (match_operand 0 "" ""))))] 1421: "" 1422: "jgtru %l0") 1423: 1424: ;; Recognize jbs and jbc instructions. 1425: 1426: (define_insn "" 1427: [(set (pc) 1428: (if_then_else 1429: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g") 1430: (const_int 1) 1431: (match_operand:SI 1 "general_operand" "g")) 1432: (const_int 0)) 1433: (label_ref (match_operand 2 "" "")) 1434: (pc)))] 1435: "" 1436: "jbs %1,%0,%l2") 1437: 1438: (define_insn "" 1439: [(set (pc) 1440: (if_then_else 1441: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g") 1442: (const_int 1) 1443: (match_operand:SI 1 "general_operand" "g")) 1444: (const_int 0)) 1445: (label_ref (match_operand 2 "" "")) 1446: (pc)))] 1447: "" 1448: "jbc %1,%0,%l2") 1449: 1450: (define_insn "" 1451: [(set (pc) 1452: (if_then_else 1453: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g") 1454: (const_int 1) 1455: (match_operand:SI 1 "general_operand" "g")) 1456: (const_int 0)) 1457: (pc) 1458: (label_ref (match_operand 2 "" ""))))] 1459: "" 1460: "jbc %1,%0,%l2") 1461: 1462: (define_insn "" 1463: [(set (pc) 1464: (if_then_else 1465: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g") 1466: (const_int 1) 1467: (match_operand:SI 1 "general_operand" "g")) 1468: (const_int 0)) 1469: (pc) 1470: (label_ref (match_operand 2 "" ""))))] 1471: "" 1472: "jbs %1,%0,%l2") 1473: 1474: (define_insn "" 1475: [(set (pc) 1476: (if_then_else 1477: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r") 1478: (const_int 1) 1479: (match_operand:SI 1 "general_operand" "g")) 1480: (const_int 0)) 1481: (label_ref (match_operand 2 "" "")) 1482: (pc)))] 1.1.1.2 root 1483: "GET_CODE (operands[0]) != MEM 1484: || ! mode_dependent_address_p (XEXP (operands[0], 0))" 1.1 root 1485: "jbs %1,%0,%l2") 1486: 1487: (define_insn "" 1488: [(set (pc) 1489: (if_then_else 1490: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r") 1491: (const_int 1) 1492: (match_operand:SI 1 "general_operand" "g")) 1493: (const_int 0)) 1494: (label_ref (match_operand 2 "" "")) 1495: (pc)))] 1.1.1.2 root 1496: "GET_CODE (operands[0]) != MEM 1497: || ! mode_dependent_address_p (XEXP (operands[0], 0))" 1.1 root 1498: "jbc %1,%0,%l2") 1499: 1500: (define_insn "" 1501: [(set (pc) 1502: (if_then_else 1.1.1.2 root 1503: (eq (and:SI (match_operand:SI 0 "general_operand" "g") 1504: (match_operand:SI 1 "general_operand" "g")) 1505: (const_int 0)) 1506: (pc) 1507: (label_ref (match_operand 2 "" ""))))] 1508: "GET_CODE (operands[1]) == CONST_INT 1509: && exact_log2 (INTVAL (operands[1])) >= 0 1510: && (GET_CODE (operands[0]) != MEM 1511: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" 1512: "* 1513: { 1514: operands[1] 1515: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); 1516: return \"jbs %1,%0,%l2\"; 1517: }") 1518: 1519: (define_insn "" 1520: [(set (pc) 1521: (if_then_else 1522: (eq (and:SI (match_operand:SI 0 "general_operand" "g") 1523: (match_operand:SI 1 "general_operand" "g")) 1524: (const_int 0)) 1525: (label_ref (match_operand 2 "" "")) 1526: (pc)))] 1527: "GET_CODE (operands[1]) == CONST_INT 1528: && exact_log2 (INTVAL (operands[1])) >= 0 1529: && (GET_CODE (operands[0]) != MEM 1530: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" 1531: "* 1532: { 1533: operands[1] 1534: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); 1535: return \"jbc %1,%0,%l2\"; 1536: }") 1537: 1538: (define_insn "" 1539: [(set (pc) 1540: (if_then_else 1541: (ne (and:SI (match_operand:SI 0 "general_operand" "g") 1542: (match_operand:SI 1 "general_operand" "g")) 1543: (const_int 0)) 1544: (pc) 1545: (label_ref (match_operand 2 "" ""))))] 1546: "GET_CODE (operands[1]) == CONST_INT 1547: && exact_log2 (INTVAL (operands[1])) >= 0 1548: && (GET_CODE (operands[0]) != MEM 1549: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" 1550: "* 1551: { 1552: operands[1] 1553: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); 1554: return \"jbc %1,%0,%l2\"; 1555: }") 1556: 1557: (define_insn "" 1558: [(set (pc) 1559: (if_then_else 1560: (ne (and:SI (match_operand:SI 0 "general_operand" "g") 1561: (match_operand:SI 1 "general_operand" "g")) 1562: (const_int 0)) 1563: (label_ref (match_operand 2 "" "")) 1564: (pc)))] 1565: "GET_CODE (operands[1]) == CONST_INT 1566: && exact_log2 (INTVAL (operands[1])) >= 0 1567: && (GET_CODE (operands[0]) != MEM 1568: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" 1569: "* 1570: { 1571: operands[1] 1572: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); 1573: return \"jbs %1,%0,%l2\"; 1574: }") 1575: 1576: (define_insn "" 1577: [(set (pc) 1578: (if_then_else 1.1 root 1579: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r") 1580: (const_int 1) 1581: (match_operand:SI 1 "general_operand" "g")) 1582: (const_int 0)) 1583: (pc) 1584: (label_ref (match_operand 2 "" ""))))] 1.1.1.2 root 1585: "GET_CODE (operands[0]) != MEM 1586: || ! mode_dependent_address_p (XEXP (operands[0], 0))" 1.1 root 1587: "jbc %1,%0,%l2") 1588: 1589: (define_insn "" 1590: [(set (pc) 1591: (if_then_else 1592: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r") 1593: (const_int 1) 1594: (match_operand:SI 1 "general_operand" "g")) 1595: (const_int 0)) 1596: (pc) 1597: (label_ref (match_operand 2 "" ""))))] 1.1.1.2 root 1598: "GET_CODE (operands[0]) != MEM 1599: || ! mode_dependent_address_p (XEXP (operands[0], 0))" 1.1 root 1600: "jbs %1,%0,%l2") 1601: 1602: (define_insn "" 1603: [(set (pc) 1604: (if_then_else 1605: (ne (and:SI (match_operand:SI 0 "general_operand" "g") 1606: (const_int 1)) 1607: (const_int 0)) 1608: (label_ref (match_operand 1 "" "")) 1609: (pc)))] 1.1.1.2 root 1610: "GET_CODE (operands[0]) != MEM 1611: || ! mode_dependent_address_p (XEXP (operands[0], 0))" 1.1 root 1612: "jlbs %0,%l1") 1613: 1614: (define_insn "" 1615: [(set (pc) 1616: (if_then_else 1617: (eq (and:SI (match_operand:SI 0 "general_operand" "g") 1618: (const_int 1)) 1619: (const_int 0)) 1620: (label_ref (match_operand 1 "" "")) 1621: (pc)))] 1.1.1.2 root 1622: "GET_CODE (operands[0]) != MEM 1623: || ! mode_dependent_address_p (XEXP (operands[0], 0))" 1.1 root 1624: "jlbc %0,%l1") 1625: 1626: (define_insn "" 1627: [(set (pc) 1628: (if_then_else 1629: (ne (and:SI (match_operand:SI 0 "general_operand" "g") 1630: (const_int 1)) 1631: (const_int 0)) 1632: (pc) 1633: (label_ref (match_operand 1 "" ""))))] 1.1.1.2 root 1634: "GET_CODE (operands[0]) != MEM 1635: || ! mode_dependent_address_p (XEXP (operands[0], 0))" 1.1 root 1636: "jlbc %0,%l1") 1637: 1638: (define_insn "" 1639: [(set (pc) 1640: (if_then_else 1641: (eq (and:SI (match_operand:SI 0 "general_operand" "g") 1642: (const_int 1)) 1643: (const_int 0)) 1644: (pc) 1645: (label_ref (match_operand 1 "" ""))))] 1.1.1.2 root 1646: "GET_CODE (operands[0]) != MEM 1647: || ! mode_dependent_address_p (XEXP (operands[0], 0))" 1.1 root 1648: "jlbs %0,%l1") 1649: 1650: ;; These four entries allow a jlbc or jlbs to be made 1651: ;; by combination with a bic. 1652: (define_insn "" 1653: [(set (pc) 1654: (if_then_else 1655: (ne (and:SI (match_operand:SI 0 "general_operand" "g") 1656: (not:SI (const_int -2))) 1657: (const_int 0)) 1658: (label_ref (match_operand 1 "" "")) 1659: (pc)))] 1.1.1.2 root 1660: "GET_CODE (operands[0]) != MEM 1661: || ! mode_dependent_address_p (XEXP (operands[0], 0))" 1.1 root 1662: "jlbs %0,%l1") 1663: 1664: (define_insn "" 1665: [(set (pc) 1666: (if_then_else 1667: (eq (and:SI (match_operand:SI 0 "general_operand" "g") 1668: (not:SI (const_int -2))) 1669: (const_int 0)) 1670: (label_ref (match_operand 1 "" "")) 1671: (pc)))] 1.1.1.2 root 1672: "GET_CODE (operands[0]) != MEM 1673: || ! mode_dependent_address_p (XEXP (operands[0], 0))" 1.1 root 1674: "jlbc %0,%l1") 1675: 1676: (define_insn "" 1677: [(set (pc) 1678: (if_then_else 1679: (ne (and:SI (match_operand:SI 0 "general_operand" "g") 1680: (not:SI (const_int -2))) 1681: (const_int 0)) 1682: (pc) 1683: (label_ref (match_operand 1 "" ""))))] 1.1.1.2 root 1684: "GET_CODE (operands[0]) != MEM 1685: || ! mode_dependent_address_p (XEXP (operands[0], 0))" 1.1 root 1686: "jlbc %0,%l1") 1687: 1688: (define_insn "" 1689: [(set (pc) 1690: (if_then_else 1691: (eq (and:SI (match_operand:SI 0 "general_operand" "g") 1692: (not:SI (const_int -2))) 1693: (const_int 0)) 1694: (pc) 1695: (label_ref (match_operand 1 "" ""))))] 1.1.1.2 root 1696: "GET_CODE (operands[0]) != MEM 1697: || ! mode_dependent_address_p (XEXP (operands[0], 0))" 1.1 root 1698: "jlbs %0,%l1") 1699: 1700: ;; Subtract-and-jump and Add-and-jump insns. 1701: ;; These are not used when output is for the Unix assembler 1702: ;; because it does not know how to modify them to reach far. 1703: 1704: ;; Normal sob insns. 1705: 1706: (define_insn "" 1707: [(set (pc) 1708: (if_then_else 1709: (gt (minus:SI (match_operand:SI 0 "general_operand" "+g") 1710: (const_int 1)) 1711: (const_int 0)) 1712: (label_ref (match_operand 1 "" "")) 1713: (pc))) 1714: (set (match_dup 0) 1.1.1.2 root 1715: (plus:SI (match_dup 0) 1716: (const_int -1)))] 1.1 root 1717: "!TARGET_UNIX_ASM" 1718: "jsobgtr %0,%l1") 1719: 1720: (define_insn "" 1721: [(set (pc) 1722: (if_then_else 1723: (ge (minus:SI (match_operand:SI 0 "general_operand" "+g") 1724: (const_int 1)) 1725: (const_int 0)) 1726: (label_ref (match_operand 1 "" "")) 1727: (pc))) 1728: (set (match_dup 0) 1.1.1.2 root 1729: (plus:SI (match_dup 0) 1730: (const_int -1)))] 1.1 root 1731: "!TARGET_UNIX_ASM" 1732: "jsobgeq %0,%l1") 1733: 1734: ;; Reversed sob insns. 1735: 1736: (define_insn "" 1737: [(set (pc) 1738: (if_then_else 1739: (le (minus:SI (match_operand:SI 0 "general_operand" "+g") 1740: (const_int 1)) 1741: (const_int 0)) 1742: (pc) 1743: (label_ref (match_operand 1 "" "")))) 1744: (set (match_dup 0) 1.1.1.2 root 1745: (plus:SI (match_dup 0) 1746: (const_int -1)))] 1.1 root 1747: "!TARGET_UNIX_ASM" 1748: "jsobgtr %0,%l1") 1749: 1750: (define_insn "" 1751: [(set (pc) 1752: (if_then_else 1753: (lt (minus:SI (match_operand:SI 0 "general_operand" "+g") 1754: (const_int 1)) 1755: (const_int 0)) 1756: (pc) 1757: (label_ref (match_operand 1 "" "")))) 1758: (set (match_dup 0) 1.1.1.2 root 1759: (plus:SI (match_dup 0) 1760: (const_int -1)))] 1.1 root 1761: "!TARGET_UNIX_ASM" 1762: "jsobgeq %0,%l1") 1763: 1764: ;; Normal aob insns. 1765: (define_insn "" 1766: [(set (pc) 1767: (if_then_else 1768: (lt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g") 1769: (const_int 1)) 1770: (match_operand:SI 1 "general_operand" "g")) 1771: (const_int 0)) 1772: (label_ref (match_operand 2 "" "")) 1773: (pc))) 1774: (set (match_dup 0) 1775: (plus:SI (match_dup 0) 1776: (const_int 1)))] 1777: "!TARGET_UNIX_ASM" 1778: "jaoblss %1,%0,%l2") 1779: 1780: (define_insn "" 1781: [(set (pc) 1782: (if_then_else 1783: (le (minus (plus:SI (match_operand:SI 0 "general_operand" "+g") 1784: (const_int 1)) 1785: (match_operand:SI 1 "general_operand" "g")) 1786: (const_int 0)) 1787: (label_ref (match_operand 2 "" "")) 1788: (pc))) 1789: (set (match_dup 0) 1790: (plus:SI (match_dup 0) 1791: (const_int 1)))] 1792: "!TARGET_UNIX_ASM" 1793: "jaobleq %1,%0,%l2") 1794: 1795: ;; Reverse aob insns. 1796: (define_insn "" 1797: [(set (pc) 1798: (if_then_else 1799: (ge (minus (plus:SI (match_operand:SI 0 "general_operand" "+g") 1800: (const_int 1)) 1801: (match_operand:SI 1 "general_operand" "g")) 1802: (const_int 0)) 1803: (pc) 1804: (label_ref (match_operand 2 "" "")))) 1805: (set (match_dup 0) 1806: (plus:SI (match_dup 0) 1807: (const_int 1)))] 1808: "!TARGET_UNIX_ASM" 1809: "jaoblss %1,%0,%l2") 1810: 1811: (define_insn "" 1812: [(set (pc) 1813: (if_then_else 1814: (gt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g") 1815: (const_int 1)) 1816: (match_operand:SI 1 "general_operand" "g")) 1817: (const_int 0)) 1818: (pc) 1819: (label_ref (match_operand 2 "" "")))) 1820: (set (match_dup 0) 1821: (plus:SI (match_dup 0) 1822: (const_int 1)))] 1823: "!TARGET_UNIX_ASM" 1824: "jaobleq %1,%0,%l2") 1825: 1.1.1.2 root 1826: ;; Note that operand 1 is total size of args, in bytes, 1827: ;; and what the call insn wants is the number of words. 1.1 root 1828: (define_insn "call" 1829: [(call (match_operand:QI 0 "general_operand" "g") 1830: (match_operand:QI 1 "general_operand" "g"))] 1831: "" 1.1.1.2 root 1832: "* 1833: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4); 1834: return \"calls %1,%0\"; 1835: ") 1836: 1837: (define_insn "call_value" 1838: [(set (match_operand 0 "" "g") 1839: (call (match_operand:QI 1 "general_operand" "g") 1840: (match_operand:QI 2 "general_operand" "g")))] 1841: "" 1842: "* 1843: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4); 1844: return \"calls %2,%1\"; 1845: ") 1.1 root 1846: 1847: (define_insn "return" 1848: [(return)] 1849: "" 1850: "ret") 1851: 1852: (define_insn "casesi" 1853: [(set (pc) 1854: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g") 1855: (match_operand:SI 1 "general_operand" "g")) 1856: (match_operand:SI 2 "general_operand" "g")) 1.1.1.2 root 1857: (plus:SI (sign_extend:SI 1.1 root 1858: (mem:HI (plus:SI (pc) 1859: (minus:SI (match_dup 0) 1.1.1.2 root 1860: (match_dup 1))))) 1861: (label_ref:SI (match_operand 3 "" ""))) 1.1 root 1862: (pc)))] 1863: "" 1864: "casel %0,%1,%2") 1865: 1.1.1.2 root 1866: ;; This used to arise from the preceding by simplification 1867: ;; if operand 1 is zero. Perhaps it is no longer necessary. 1868: (define_insn "" 1869: [(set (pc) 1870: (if_then_else (le (match_operand:SI 0 "general_operand" "g") 1871: (match_operand:SI 1 "general_operand" "g")) 1872: (plus:SI (sign_extend:SI 1873: (mem:HI (plus:SI (pc) 1874: (minus:SI (match_dup 0) 1875: (const_int 0))))) 1876: (label_ref:SI (match_operand 3 "" ""))) 1877: (pc)))] 1878: "" 1879: "casel %0,$0,%1") 1880: 1.1 root 1881: ;; This arises from the preceding by simplification if operand 1 is zero. 1882: (define_insn "" 1883: [(set (pc) 1884: (if_then_else (le (match_operand:SI 0 "general_operand" "g") 1885: (match_operand:SI 1 "general_operand" "g")) 1.1.1.2 root 1886: (plus:SI (sign_extend:SI 1.1 root 1887: (mem:HI (plus:SI (pc) 1.1.1.2 root 1888: (match_dup 0)))) 1889: (label_ref:SI (match_operand 3 "" ""))) 1.1 root 1890: (pc)))] 1891: "" 1892: "casel %0,$0,%1") 1893: 1.1.1.2 root 1894: ;; Optimize extzv ...,z; andl2 ...,z 1895: ;; with other operands constant. 1896: (define_peephole 1897: [(set (match_operand:SI 0 "general_operand" "g") 1898: (zero_extract:SI (match_operand:SI 1 "general_operand" "g") 1899: (match_operand:SI 2 "general_operand" "g") 1900: (match_operand:SI 3 "general_operand" "g"))) 1901: (set (match_operand:SI 4 "general_operand" "g") 1902: (and:SI (match_dup 0) 1903: (match_operand:SI 5 "general_operand" "g")))] 1904: "GET_CODE (operands[2]) == CONST_INT 1905: && GET_CODE (operands[3]) == CONST_INT 1906: && (INTVAL (operands[2]) + INTVAL (operands[3])) == 32 1907: && GET_CODE (operands[5]) == CONST_INT 1908: && dead_or_set_p (insn, operands[0])" 1909: "* 1910: { 1911: unsigned long mask = INTVAL (operands[5]); 1912: operands[3] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[3])); 1913: 1914: if ((floor_log2 (mask) + 1) >= INTVAL (operands[2])) 1915: mask &= ((1 << INTVAL (operands[2])) - 1); 1916: 1917: operands[5] = gen_rtx (CONST_INT, VOIDmode, ~mask); 1918: if (push_operand (operands[4], SImode)) 1919: { 1920: output_asm_insn (\"rotl %3,%1,%0\", operands); 1921: return \"bicl3 %5,%0,%4\"; 1922: } 1923: else 1924: { 1925: output_asm_insn (\"rotl %3,%1,%4\", operands); 1926: return \"bicl2 %5,%4\"; 1927: } 1928: }") 1929: 1930: ;; Optimize andl3 x,y,z; extzv z,....,z 1931: 1932: (define_peephole 1933: [(set (match_operand:SI 0 "general_operand" "g") 1934: (and:SI (match_operand:SI 1 "general_operand" "g") 1935: (match_operand:SI 2 "general_operand" "g"))) 1936: (set (match_operand 3 "general_operand" "g") 1937: (zero_extract:SI (match_dup 0) 1938: (match_operand:SI 4 "general_operand" "g") 1939: (match_operand:SI 5 "general_operand" "g")))] 1940: "GET_CODE (operands[2]) == CONST_INT 1941: && GET_CODE (operands[4]) == CONST_INT 1942: && GET_CODE (operands[5]) == CONST_INT 1943: && (INTVAL (operands[4]) + INTVAL (operands[5])) == 32 1944: && dead_or_set_p (insn, operands[0])" 1945: "* 1946: { 1947: unsigned long mask = INTVAL (operands[2]); 1948: 1949: mask &= ~((1 << INTVAL (operands[5])) - 1); 1950: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~mask); 1951: 1952: operands[5] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[5])); 1953: 1954: if (rtx_equal_p (operands[0], operands[1])) 1955: output_asm_insn (\"bicl2 %2,%0\", operands); 1956: else 1957: output_asm_insn (\"bicl3 %2,%1,%0\", operands); 1958: return \"rotl %5,%0,%3\"; 1959: }") 1960: 1.1 root 1961: ;;- Local variables: 1962: ;;- mode:emacs-lisp 1963: ;;- comment-start: ";;- " 1964: ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) 1965: ;;- eval: (modify-syntax-entry ?[ "(]") 1966: ;;- eval: (modify-syntax-entry ?] ")[") 1967: ;;- eval: (modify-syntax-entry ?{ "(}") 1968: ;;- eval: (modify-syntax-entry ?} "){") 1969: ;;- End:
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