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1.1.1.4 root 1:
1.1 root 2: ;;- Machine description for GNU compiler
3: ;;- Vax Version
4: ;; Copyright (C) 1987 Free Software Foundation, Inc.
5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is distributed in the hope that it will be useful,
9: ;; but WITHOUT ANY WARRANTY. No author or distributor
10: ;; accepts responsibility to anyone for the consequences of using it
11: ;; or for whether it serves any particular purpose or works at all,
12: ;; unless he says so in writing. Refer to the GNU CC General Public
13: ;; License for full details.
14:
15: ;; Everyone is granted permission to copy, modify and redistribute
16: ;; GNU CC, but only under the conditions described in the
17: ;; GNU CC General Public License. A copy of this license is
18: ;; supposed to have been given to you along with GNU CC so you
19: ;; can know your rights and responsibilities. It should be in a
20: ;; file named COPYING. Among other things, the copyright notice
21: ;; and this notice must be preserved on all copies.
22:
23:
24: ;;- Instruction patterns. When multiple patterns apply,
25: ;;- the first one in the file is chosen.
26: ;;-
27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28: ;;-
29: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
30: ;;- updates for most instructions.
31:
1.1.1.2 root 32: ; tstsi is first test insn so that it is the one to match
33: ; a constant argument.
1.1 root 34:
35: (define_insn "tstsi"
36: [(set (cc0)
37: (match_operand:SI 0 "general_operand" "g"))]
38: ""
39: "tstl %0")
40:
41: (define_insn "tsthi"
42: [(set (cc0)
43: (match_operand:HI 0 "general_operand" "g"))]
44: ""
45: "tstw %0")
46:
47: (define_insn "tstqi"
48: [(set (cc0)
49: (match_operand:QI 0 "general_operand" "g"))]
50: ""
51: "tstb %0")
52:
1.1.1.2 root 53: (define_insn "tstdf"
1.1 root 54: [(set (cc0)
1.1.1.2 root 55: (match_operand:DF 0 "general_operand" "gF"))]
1.1 root 56: ""
1.1.1.3 root 57: "tst%# %0")
1.1 root 58:
1.1.1.2 root 59: (define_insn "tstsf"
1.1 root 60: [(set (cc0)
1.1.1.2 root 61: (match_operand:SF 0 "general_operand" "gF"))]
1.1 root 62: ""
1.1.1.2 root 63: "tstf %0")
1.1 root 64:
65: (define_insn "cmpsi"
66: [(set (cc0)
67: (minus (match_operand:SI 0 "general_operand" "g")
68: (match_operand:SI 1 "general_operand" "g")))]
69: ""
70: "cmpl %0,%1")
71:
72: (define_insn "cmphi"
73: [(set (cc0)
74: (minus (match_operand:HI 0 "general_operand" "g")
75: (match_operand:HI 1 "general_operand" "g")))]
76: ""
77: "cmpw %0,%1")
78:
79: (define_insn "cmpqi"
80: [(set (cc0)
81: (minus (match_operand:QI 0 "general_operand" "g")
82: (match_operand:QI 1 "general_operand" "g")))]
83: ""
84: "cmpb %0,%1")
85:
1.1.1.2 root 86: (define_insn "cmpdf"
87: [(set (cc0)
88: (minus (match_operand:DF 0 "general_operand" "gF")
89: (match_operand:DF 1 "general_operand" "gF")))]
90: ""
1.1.1.3 root 91: "cmp%# %0,%1")
1.1.1.2 root 92:
93: (define_insn "cmpsf"
94: [(set (cc0)
95: (minus (match_operand:SF 0 "general_operand" "gF")
96: (match_operand:SF 1 "general_operand" "gF")))]
97: ""
98: "cmpf %0,%1")
99:
1.1 root 100: (define_insn ""
101: [(set (cc0)
102: (and:SI (match_operand:SI 0 "general_operand" "g")
103: (match_operand:SI 1 "general_operand" "g")))]
104: ""
105: "bitl %0,%1")
106:
107: (define_insn ""
108: [(set (cc0)
109: (and:HI (match_operand:HI 0 "general_operand" "g")
110: (match_operand:HI 1 "general_operand" "g")))]
111: ""
112: "bitw %0,%1")
113:
114: (define_insn ""
115: [(set (cc0)
116: (and:QI (match_operand:QI 0 "general_operand" "g")
117: (match_operand:QI 1 "general_operand" "g")))]
118: ""
119: "bitb %0,%1")
120:
121: (define_insn "movdf"
122: [(set (match_operand:DF 0 "general_operand" "=g")
123: (match_operand:DF 1 "general_operand" "gF"))]
124: ""
125: "*
126: {
127: if (operands[1] == dconst0_rtx)
1.1.1.3 root 128: return \"clr%# %0\";
129: return \"mov%# %1,%0\";
1.1 root 130: }")
131:
132: (define_insn "movsf"
133: [(set (match_operand:SF 0 "general_operand" "=g")
134: (match_operand:SF 1 "general_operand" "gF"))]
135: ""
136: "*
137: {
138: if (operands[1] == fconst0_rtx)
139: return \"clrf %0\";
140: return \"movf %1,%0\";
141: }")
142:
1.1.1.2 root 143: ;; Some vaxes don't support this instruction.
144: ;;(define_insn "movti"
145: ;; [(set (match_operand:TI 0 "general_operand" "=g")
146: ;; (match_operand:TI 1 "general_operand" "g"))]
147: ;; ""
148: ;; "movh %1,%0")
1.1 root 149:
150: (define_insn "movdi"
151: [(set (match_operand:DI 0 "general_operand" "=g")
152: (match_operand:DI 1 "general_operand" "g"))]
153: ""
1.1.1.2 root 154: "movq %1,%0")
1.1 root 155:
156: (define_insn "movsi"
157: [(set (match_operand:SI 0 "general_operand" "=g")
158: (match_operand:SI 1 "general_operand" "g"))]
159: ""
160: "*
161: { if (operands[1] == const1_rtx
1.1.1.2 root 162: && REG_NOTES (insn)
163: && GET_MODE (REG_NOTES (insn)) == (enum machine_mode) REG_WAS_0
164: /* Make sure the insn that stored the 0 is still present. */
165: && ! XEXP (REG_NOTES (insn), 0)->volatil
1.1.1.5 root 166: && GET_CODE (XEXP (REG_NOTES (insn), 0)) != NOTE
167: /* Make sure cross jumping didn't happen here. */
168: && no_labels_between_p (XEXP (REG_NOTES (insn), 0), insn))
1.1.1.2 root 169: /* Fastest way to change a 0 to a 1. */
1.1 root 170: return \"incl %0\";
171: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
172: {
173: if (push_operand (operands[0], SImode))
174: return \"pushab %a1\";
175: return \"movab %a1,%0\";
176: }
177: if (operands[1] == const0_rtx)
178: return \"clrl %0\";
179: if (GET_CODE (operands[1]) == CONST_INT
180: && (unsigned) INTVAL (operands[1]) >= 64)
181: {
182: int i = INTVAL (operands[1]);
183: if ((unsigned)(-i) < 64)
184: {
185: operands[1] = gen_rtx (CONST_INT, VOIDmode, -i);
186: return \"mnegl %1,%0\";
187: }
188: if ((unsigned)i < 0x100)
189: return \"movzbl %1,%0\";
190: if (i >= -0x80 && i < 0)
191: return \"cvtbl %1,%0\";
192: if ((unsigned)i < 0x10000)
193: return \"movzwl %1,%0\";
194: if (i >= -0x8000 && i < 0)
195: return \"cvtwl %1,%0\";
196: }
197: if (push_operand (operands[0], SImode))
198: return \"pushl %1\";
199: return \"movl %1,%0\";
200: }")
201:
202: (define_insn "movhi"
203: [(set (match_operand:HI 0 "general_operand" "=g")
204: (match_operand:HI 1 "general_operand" "g"))]
205: ""
206: "*
207: {
208: if (operands[1] == const1_rtx
1.1.1.2 root 209: && REG_NOTES (insn)
1.1 root 210: && GET_MODE (REG_NOTES (insn)) == (enum machine_mode) REG_WAS_0)
211: return \"incw %0\";
212: if (operands[1] == const0_rtx)
213: return \"clrw %0\";
214: if (GET_CODE (operands[1]) == CONST_INT
215: && (unsigned) INTVAL (operands[1]) >= 64)
216: {
217: int i = INTVAL (operands[1]);
218: if ((unsigned)(-i) < 64)
219: {
220: operands[1] = gen_rtx (CONST_INT, VOIDmode, -i);
221: return \"mnegw %1,%0\";
222: }
223: if ((unsigned)i < 0x100)
224: return \"movzbw %1,%0\";
225: if (i >= -0x80 && i < 0)
226: return \"cvtbw %1,%0\";
227: }
228: return \"movw %1,%0\";
229: }")
230:
231: (define_insn "movqi"
232: [(set (match_operand:QI 0 "general_operand" "=g")
233: (match_operand:QI 1 "general_operand" "g"))]
234: ""
235: "*
236: {
237: if (operands[1] == const0_rtx)
238: return \"clrb %0\";
239: return \"movb %1,%0\";
240: }")
241:
242: ;; The definition of this insn does not really explain what it does,
243: ;; but it should suffice
244: ;; that anything generated as this insn will be recognized as one
245: ;; and that it won't successfully combine with anything.
246: (define_insn "movstrhi"
247: [(set (match_operand:BLK 0 "general_operand" "=g")
248: (match_operand:BLK 1 "general_operand" "g"))
249: (use (match_operand:HI 2 "general_operand" "g"))
1.1.1.2 root 250: (clobber (reg:SI 0))
251: (clobber (reg:SI 1))
252: (clobber (reg:SI 2))
253: (clobber (reg:SI 3))
254: (clobber (reg:SI 4))
255: (clobber (reg:SI 5))]
1.1 root 256: ""
257: "movc3 %2,%1,%0")
258:
259: ;;- load or push effective address
260: ;; These come after the move patterns
261: ;; because we don't want pushl $1 turned into pushad 1.
262:
263: (define_insn ""
264: [(set (match_operand:SI 0 "general_operand" "=g")
265: (match_operand:QI 1 "address_operand" "p"))]
266: ""
267: "*
268: {
269: if (push_operand (operands[0], SImode))
270: return \"pushab %a1\";
271: return \"movab %a1,%0\";
272: }")
273:
274: (define_insn ""
275: [(set (match_operand:SI 0 "general_operand" "=g")
276: (match_operand:HI 1 "address_operand" "p"))]
277: ""
278: "*
279: {
280: if (push_operand (operands[0], SImode))
281: return \"pushaw %a1\";
282: return \"movaw %a1,%0\";
283: }")
284:
285: (define_insn ""
286: [(set (match_operand:SI 0 "general_operand" "=g")
287: (match_operand:SI 1 "address_operand" "p"))]
288: ""
289: "*
290: {
291: if (push_operand (operands[0], SImode))
292: return \"pushal %a1\";
293: return \"moval %a1,%0\";
294: }")
295:
296: (define_insn ""
297: [(set (match_operand:SI 0 "general_operand" "=g")
298: (match_operand:SF 1 "address_operand" "p"))]
299: ""
300: "*
301: {
302: if (push_operand (operands[0], SImode))
303: return \"pushaf %a1\";
304: return \"movaf %a1,%0\";
305: }")
306:
307: (define_insn ""
308: [(set (match_operand:SI 0 "general_operand" "=g")
309: (match_operand:DF 1 "address_operand" "p"))]
310: ""
311: "*
312: {
313: if (push_operand (operands[0], SImode))
314: return \"pushad %a1\";
315: return \"movad %a1,%0\";
316: }")
317:
1.1.1.2 root 318: ;; Extension and truncation insns.
319: ;; Those for integer source operand
320: ;; are ordered widest source type first.
1.1 root 321:
1.1.1.2 root 322: (define_insn "truncsiqi2"
323: [(set (match_operand:QI 0 "general_operand" "=g")
324: (truncate:QI (match_operand:SI 1 "general_operand" "g")))]
1.1 root 325: ""
1.1.1.2 root 326: "cvtlb %1,%0")
1.1 root 327:
1.1.1.2 root 328: (define_insn "truncsihi2"
329: [(set (match_operand:HI 0 "general_operand" "=g")
330: (truncate:HI (match_operand:SI 1 "general_operand" "g")))]
1.1 root 331: ""
1.1.1.2 root 332: "cvtlw %1,%0")
1.1 root 333:
334: (define_insn "trunchiqi2"
335: [(set (match_operand:QI 0 "general_operand" "=g")
336: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
337: ""
338: "cvtwb %1,%0")
339:
340: (define_insn "extendhisi2"
341: [(set (match_operand:SI 0 "general_operand" "=g")
342: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
343: ""
344: "cvtwl %1,%0")
345:
1.1.1.2 root 346: (define_insn "extendqihi2"
347: [(set (match_operand:HI 0 "general_operand" "=g")
348: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1.1 root 349: ""
1.1.1.2 root 350: "cvtbw %1,%0")
1.1 root 351:
1.1.1.2 root 352: (define_insn "extendqisi2"
353: [(set (match_operand:SI 0 "general_operand" "=g")
354: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
355: ""
356: "cvtbl %1,%0")
357:
358: (define_insn "extendsfdf2"
1.1 root 359: [(set (match_operand:DF 0 "general_operand" "=g")
1.1.1.2 root 360: (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
1.1 root 361: ""
1.1.1.3 root 362: "cvtf%# %1,%0")
1.1 root 363:
1.1.1.2 root 364: (define_insn "truncdfsf2"
365: [(set (match_operand:SF 0 "general_operand" "=g")
366: (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
1.1 root 367: ""
1.1.1.3 root 368: "cvt%#f %1,%0")
1.1 root 369:
1.1.1.2 root 370: (define_insn "zero_extendhisi2"
371: [(set (match_operand:SI 0 "general_operand" "=g")
372: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
373: ""
374: "movzwl %1,%0")
375:
376: (define_insn "zero_extendqihi2"
1.1 root 377: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 378: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1.1 root 379: ""
1.1.1.2 root 380: "movzbw %1,%0")
381:
382: (define_insn "zero_extendqisi2"
383: [(set (match_operand:SI 0 "general_operand" "=g")
384: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
385: ""
386: "movzbl %1,%0")
387:
388: ;; Fix-to-float conversion insns.
389: ;; Note that the ones that start with SImode come first.
390: ;; That is so that an operand that is a CONST_INT
391: ;; (and therefore lacks a specific machine mode).
392: ;; will be recognized as SImode (which is always valid)
393: ;; rather than as QImode or HImode.
1.1 root 394:
395: (define_insn "floatsisf2"
396: [(set (match_operand:SF 0 "general_operand" "=g")
397: (float:SF (match_operand:SI 1 "general_operand" "g")))]
398: ""
399: "cvtlf %1,%0")
400:
401: (define_insn "floatsidf2"
402: [(set (match_operand:DF 0 "general_operand" "=g")
403: (float:DF (match_operand:SI 1 "general_operand" "g")))]
404: ""
1.1.1.3 root 405: "cvtl%# %1,%0")
1.1 root 406:
1.1.1.2 root 407: (define_insn "floathisf2"
408: [(set (match_operand:SF 0 "general_operand" "=g")
409: (float:SF (match_operand:HI 1 "general_operand" "g")))]
1.1 root 410: ""
1.1.1.2 root 411: "cvtwf %1,%0")
1.1 root 412:
1.1.1.2 root 413: (define_insn "floathidf2"
414: [(set (match_operand:DF 0 "general_operand" "=g")
415: (float:DF (match_operand:HI 1 "general_operand" "g")))]
1.1 root 416: ""
1.1.1.3 root 417: "cvtw%# %1,%0")
1.1 root 418:
1.1.1.2 root 419: (define_insn "floatqisf2"
420: [(set (match_operand:SF 0 "general_operand" "=g")
421: (float:SF (match_operand:QI 1 "general_operand" "g")))]
1.1 root 422: ""
1.1.1.2 root 423: "cvtbf %1,%0")
1.1 root 424:
1.1.1.2 root 425: (define_insn "floatqidf2"
1.1 root 426: [(set (match_operand:DF 0 "general_operand" "=g")
1.1.1.2 root 427: (float:DF (match_operand:QI 1 "general_operand" "g")))]
1.1 root 428: ""
1.1.1.3 root 429: "cvtb%# %1,%0")
1.1.1.2 root 430:
431: ;; Float-to-fix conversion insns.
1.1 root 432:
1.1.1.2 root 433: (define_insn "fix_truncsfqi2"
1.1 root 434: [(set (match_operand:QI 0 "general_operand" "=g")
1.1.1.2 root 435: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 436: ""
1.1.1.2 root 437: "cvtfb %1,%0")
1.1 root 438:
1.1.1.2 root 439: (define_insn "fix_truncsfhi2"
1.1 root 440: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 441: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 442: ""
1.1.1.2 root 443: "cvtfw %1,%0")
1.1 root 444:
1.1.1.2 root 445: (define_insn "fix_truncsfsi2"
1.1 root 446: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 447: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 448: ""
1.1.1.2 root 449: "cvtfl %1,%0")
1.1 root 450:
1.1.1.2 root 451: (define_insn "fix_truncdfqi2"
452: [(set (match_operand:QI 0 "general_operand" "=g")
453: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 454: ""
1.1.1.2 root 455: "cvtdb %1,%0")
1.1 root 456:
1.1.1.2 root 457: (define_insn "fix_truncdfhi2"
1.1 root 458: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 459: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 460: ""
1.1.1.3 root 461: "cvt%#w %1,%0")
1.1 root 462:
1.1.1.2 root 463: (define_insn "fix_truncdfsi2"
1.1 root 464: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 465: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 466: ""
1.1.1.3 root 467: "cvt%#l %1,%0")
1.1 root 468:
469: ;;- All kinds of add instructions.
470:
471: (define_insn "adddf3"
472: [(set (match_operand:DF 0 "general_operand" "=g")
473: (plus:DF (match_operand:DF 1 "general_operand" "gF")
474: (match_operand:DF 2 "general_operand" "gF")))]
475: ""
476: "*
477: {
478: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 479: return \"add%#2 %2,%0\";
1.1 root 480: if (rtx_equal_p (operands[0], operands[2]))
1.1.1.3 root 481: return \"add%#2 %1,%0\";
482: return \"add%#3 %1,%2,%0\";
1.1 root 483: }")
484:
485: (define_insn "addsf3"
486: [(set (match_operand:SF 0 "general_operand" "=g")
487: (plus:SF (match_operand:SF 1 "general_operand" "gF")
488: (match_operand:SF 2 "general_operand" "gF")))]
489: ""
490: "*
491: {
492: if (rtx_equal_p (operands[0], operands[1]))
493: return \"addf2 %2,%0\";
494: if (rtx_equal_p (operands[0], operands[2]))
495: return \"addf2 %1,%0\";
496: return \"addf3 %1,%2,%0\";
497: }")
498:
499: (define_insn "addsi3"
500: [(set (match_operand:SI 0 "general_operand" "=g")
501: (plus:SI (match_operand:SI 1 "general_operand" "g")
502: (match_operand:SI 2 "general_operand" "g")))]
503: ""
504: "*
505: {
506: if (rtx_equal_p (operands[0], operands[1]))
507: {
508: if (operands[2] == const1_rtx)
509: return \"incl %0\";
1.1.1.2 root 510: if (GET_CODE (operands[2]) == CONST_INT
511: && INTVAL (operands[2]) == -1)
1.1 root 512: return \"decl %0\";
513: if (GET_CODE (operands[2]) == CONST_INT
514: && (unsigned) (- INTVAL (operands[2])) < 64)
515: return \"subl2 $%n2,%0\";
516: return \"addl2 %2,%0\";
517: }
518: if (rtx_equal_p (operands[0], operands[2]))
519: return \"addl2 %1,%0\";
520: if (GET_CODE (operands[2]) == CONST_INT
521: && GET_CODE (operands[1]) == REG)
522: {
523: if (push_operand (operands[0], SImode))
524: return \"pushab %c2(%1)\";
525: return \"movab %c2(%1),%0\";
526: }
527: if (GET_CODE (operands[2]) == CONST_INT
528: && (unsigned) (- INTVAL (operands[2])) < 64)
529: return \"subl3 $%n2,%1,%0\";
530: return \"addl3 %1,%2,%0\";
531: }")
532:
533: (define_insn "addhi3"
534: [(set (match_operand:HI 0 "general_operand" "=g")
535: (plus:HI (match_operand:HI 1 "general_operand" "g")
536: (match_operand:HI 2 "general_operand" "g")))]
537: ""
538: "*
539: {
540: if (rtx_equal_p (operands[0], operands[1]))
541: {
542: if (operands[2] == const1_rtx)
543: return \"incw %0\";
544: if (GET_CODE (operands[1]) == CONST_INT
545: && INTVAL (operands[1]) == -1)
546: return \"decw %0\";
547: if (GET_CODE (operands[2]) == CONST_INT
548: && (unsigned) (- INTVAL (operands[2])) < 64)
549: return \"subw2 $%n2,%0\";
550: return \"addw2 %2,%0\";
551: }
552: if (rtx_equal_p (operands[0], operands[2]))
553: return \"addw2 %1,%0\";
554: if (GET_CODE (operands[2]) == CONST_INT
555: && (unsigned) (- INTVAL (operands[2])) < 64)
556: return \"subw3 $%n2,%1,%0\";
557: return \"addw3 %1,%2,%0\";
558: }")
559:
560: (define_insn "addqi3"
561: [(set (match_operand:QI 0 "general_operand" "=g")
562: (plus:QI (match_operand:QI 1 "general_operand" "g")
563: (match_operand:QI 2 "general_operand" "g")))]
564: ""
565: "*
566: {
567: if (rtx_equal_p (operands[0], operands[1]))
568: {
569: if (operands[2] == const1_rtx)
570: return \"incb %0\";
571: if (GET_CODE (operands[1]) == CONST_INT
572: && INTVAL (operands[1]) == -1)
573: return \"decb %0\";
574: if (GET_CODE (operands[2]) == CONST_INT
575: && (unsigned) (- INTVAL (operands[2])) < 64)
576: return \"subb2 $%n2,%0\";
577: return \"addb2 %2,%0\";
578: }
579: if (rtx_equal_p (operands[0], operands[2]))
580: return \"addb2 %1,%0\";
581: if (GET_CODE (operands[2]) == CONST_INT
582: && (unsigned) (- INTVAL (operands[2])) < 64)
583: return \"subb3 $%n2,%1,%0\";
584: return \"addb3 %1,%2,%0\";
585: }")
586:
587: ;;- All kinds of subtract instructions.
588:
589: (define_insn "subdf3"
590: [(set (match_operand:DF 0 "general_operand" "=g")
591: (minus:DF (match_operand:DF 1 "general_operand" "gF")
592: (match_operand:DF 2 "general_operand" "gF")))]
593: ""
594: "*
595: {
596: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 597: return \"sub%#2 %2,%0\";
598: return \"sub%#3 %2,%1,%0\";
1.1 root 599: }")
600:
601: (define_insn "subsf3"
602: [(set (match_operand:SF 0 "general_operand" "=g")
603: (minus:SF (match_operand:SF 1 "general_operand" "gF")
604: (match_operand:SF 2 "general_operand" "gF")))]
605: ""
606: "*
607: {
608: if (rtx_equal_p (operands[0], operands[1]))
609: return \"subf2 %2,%0\";
610: return \"subf3 %2,%1,%0\";
611: }")
612:
613: (define_insn "subsi3"
614: [(set (match_operand:SI 0 "general_operand" "=g")
615: (minus:SI (match_operand:SI 1 "general_operand" "g")
616: (match_operand:SI 2 "general_operand" "g")))]
617: ""
618: "*
619: {
620: if (rtx_equal_p (operands[0], operands[1]))
621: {
622: if (operands[2] == const1_rtx)
623: return \"decl %0\";
624: return \"subl2 %2,%0\";
625: }
626: return \"subl3 %2,%1,%0\";
627: }")
628:
629: (define_insn "subhi3"
630: [(set (match_operand:HI 0 "general_operand" "=g")
631: (minus:HI (match_operand:HI 1 "general_operand" "g")
632: (match_operand:HI 2 "general_operand" "g")))]
633: ""
634: "*
635: {
636: if (rtx_equal_p (operands[0], operands[1]))
637: {
638: if (operands[2] == const1_rtx)
639: return \"decw %0\";
640: return \"subw2 %2,%0\";
641: }
642: return \"subw3 %2,%1,%0\";
643: }")
644:
645: (define_insn "subqi3"
646: [(set (match_operand:QI 0 "general_operand" "=g")
647: (minus:QI (match_operand:QI 1 "general_operand" "g")
648: (match_operand:QI 2 "general_operand" "g")))]
649: ""
650: "*
651: {
652: if (rtx_equal_p (operands[0], operands[1]))
653: {
654: if (operands[2] == const1_rtx)
655: return \"decb %0\";
656: return \"subb2 %2,%0\";
657: }
658: return \"subb3 %2,%1,%0\";
659: }")
660:
661: ;;- Multiply instructions.
662:
663: (define_insn "muldf3"
664: [(set (match_operand:DF 0 "general_operand" "=g")
665: (mult:DF (match_operand:DF 1 "general_operand" "gF")
666: (match_operand:DF 2 "general_operand" "gF")))]
667: ""
668: "*
669: {
670: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 671: return \"mul%#2 %2,%0\";
1.1 root 672: if (rtx_equal_p (operands[0], operands[2]))
1.1.1.3 root 673: return \"mul%#2 %1,%0\";
674: return \"mul%#3 %1,%2,%0\";
1.1 root 675: }")
676:
677: (define_insn "mulsf3"
678: [(set (match_operand:SF 0 "general_operand" "=g")
679: (mult:SF (match_operand:SF 1 "general_operand" "gF")
680: (match_operand:SF 2 "general_operand" "gF")))]
681: ""
682: "*
683: {
684: if (rtx_equal_p (operands[0], operands[1]))
685: return \"mulf2 %2,%0\";
686: if (rtx_equal_p (operands[0], operands[2]))
687: return \"mulf2 %1,%0\";
688: return \"mulf3 %1,%2,%0\";
689: }")
690:
691: (define_insn "mulsi3"
692: [(set (match_operand:SI 0 "general_operand" "=g")
693: (mult:SI (match_operand:SI 1 "general_operand" "g")
694: (match_operand:SI 2 "general_operand" "g")))]
695: ""
696: "*
697: {
698: if (rtx_equal_p (operands[0], operands[1]))
699: return \"mull2 %2,%0\";
700: if (rtx_equal_p (operands[0], operands[2]))
701: return \"mull2 %1,%0\";
702: return \"mull3 %1,%2,%0\";
703: }")
704:
705: (define_insn "mulhi3"
706: [(set (match_operand:HI 0 "general_operand" "=g")
707: (mult:HI (match_operand:HI 1 "general_operand" "g")
708: (match_operand:HI 2 "general_operand" "g")))]
709: ""
710: "*
711: {
712: if (rtx_equal_p (operands[0], operands[1]))
713: return \"mulw2 %2,%0\";
714: if (rtx_equal_p (operands[0], operands[2]))
715: return \"mulw2 %1,%0\";
716: return \"mulw3 %1,%2,%0\";
717: }")
718:
719: (define_insn "mulqi3"
720: [(set (match_operand:QI 0 "general_operand" "=g")
721: (mult:QI (match_operand:QI 1 "general_operand" "g")
722: (match_operand:QI 2 "general_operand" "g")))]
723: ""
724: "*
725: {
726: if (rtx_equal_p (operands[0], operands[1]))
727: return \"mulb2 %2,%0\";
728: if (rtx_equal_p (operands[0], operands[2]))
729: return \"mulb2 %1,%0\";
730: return \"mulb3 %1,%2,%0\";
731: }")
732:
733: ;;- Divide instructions.
734:
735: (define_insn "divdf3"
736: [(set (match_operand:DF 0 "general_operand" "=g")
737: (div:DF (match_operand:DF 1 "general_operand" "gF")
738: (match_operand:DF 2 "general_operand" "gF")))]
739: ""
740: "*
741: {
742: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 743: return \"div%#2 %2,%0\";
744: return \"div%#3 %2,%1,%0\";
1.1 root 745: }")
746:
747: (define_insn "divsf3"
748: [(set (match_operand:SF 0 "general_operand" "=g")
749: (div:SF (match_operand:SF 1 "general_operand" "gF")
750: (match_operand:SF 2 "general_operand" "gF")))]
751: ""
752: "*
753: {
754: if (rtx_equal_p (operands[0], operands[1]))
755: return \"divf2 %2,%0\";
756: return \"divf3 %2,%1,%0\";
757: }")
758:
759: (define_insn "divsi3"
760: [(set (match_operand:SI 0 "general_operand" "=g")
761: (div:SI (match_operand:SI 1 "general_operand" "g")
762: (match_operand:SI 2 "general_operand" "g")))]
763: ""
764: "*
765: {
766: if (rtx_equal_p (operands[0], operands[1]))
767: return \"divl2 %2,%0\";
768: return \"divl3 %2,%1,%0\";
769: }")
770:
771: (define_insn "divhi3"
772: [(set (match_operand:HI 0 "general_operand" "=g")
773: (div:HI (match_operand:HI 1 "general_operand" "g")
774: (match_operand:HI 2 "general_operand" "g")))]
775: ""
776: "*
777: {
778: if (rtx_equal_p (operands[0], operands[1]))
779: return \"divw2 %2,%0\";
780: return \"divw3 %2,%1,%0\";
781: }")
782:
783: (define_insn "divqi3"
784: [(set (match_operand:QI 0 "general_operand" "=g")
785: (div:QI (match_operand:QI 1 "general_operand" "g")
786: (match_operand:QI 2 "general_operand" "g")))]
787: ""
788: "*
789: {
790: if (rtx_equal_p (operands[0], operands[1]))
791: return \"divb2 %2,%0\";
792: return \"divb3 %2,%1,%0\";
793: }")
794:
795: ;This is left out because it is very slow;
796: ;we are better off programming around the "lack" of this insn.
797: ;(define_insn "divmoddisi4"
798: ; [(set (match_operand:SI 0 "general_operand" "=g")
799: ; (div:SI (match_operand:DI 1 "general_operand" "g")
800: ; (match_operand:SI 2 "general_operand" "g")))
801: ; (set (match_operand:SI 3 "general_operand" "=g")
802: ; (mod:SI (match_operand:DI 1 "general_operand" "g")
803: ; (match_operand:SI 2 "general_operand" "g")))]
804: ; ""
805: ; "ediv %2,%1,%0,%3")
806:
807: (define_insn "andcbsi3"
808: [(set (match_operand:SI 0 "general_operand" "=g")
809: (and:SI (match_operand:SI 1 "general_operand" "g")
810: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
811: ""
812: "*
813: {
814: if (rtx_equal_p (operands[0], operands[1]))
815: return \"bicl2 %2,%0\";
816: return \"bicl3 %2,%1,%0\";
817: }")
818:
819: (define_insn "andcbhi3"
820: [(set (match_operand:HI 0 "general_operand" "=g")
821: (and:HI (match_operand:HI 1 "general_operand" "g")
822: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
823: ""
824: "*
825: {
826: if (rtx_equal_p (operands[0], operands[1]))
827: return \"bicw2 %2,%0\";
828: return \"bicw3 %2,%1,%0\";
829: }")
830:
831: (define_insn "andcbqi3"
832: [(set (match_operand:QI 0 "general_operand" "=g")
833: (and:QI (match_operand:QI 1 "general_operand" "g")
834: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
835: ""
836: "*
837: {
838: if (rtx_equal_p (operands[0], operands[1]))
839: return \"bicb2 %2,%0\";
840: return \"bicb3 %2,%1,%0\";
841: }")
842:
843: ;; The following are needed because constant propagation can
844: ;; create them starting from the bic insn patterns above.
845:
846: (define_insn ""
847: [(set (match_operand:SI 0 "general_operand" "=g")
848: (and:SI (match_operand:SI 1 "general_operand" "g")
849: (match_operand:SI 2 "general_operand" "g")))]
850: "GET_CODE (operands[2]) == CONST_INT"
851: "*
852: { operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
853: if (rtx_equal_p (operands[1], operands[0]))
854: return \"bicl2 %2,%0\";
855: return \"bicl3 %2,%1,%0\";
856: }")
857:
858: (define_insn ""
859: [(set (match_operand:HI 0 "general_operand" "=g")
860: (and:HI (match_operand:HI 1 "general_operand" "g")
861: (match_operand:HI 2 "general_operand" "g")))]
862: "GET_CODE (operands[2]) == CONST_INT"
863: "*
864: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xffff & ~INTVAL (operands[2]));
865: if (rtx_equal_p (operands[1], operands[0]))
866: return \"bicw2 %2,%0\";
867: return \"bicw3 %2,%1,%0\";
868: }")
869:
870: (define_insn ""
871: [(set (match_operand:QI 0 "general_operand" "=g")
872: (and:QI (match_operand:QI 1 "general_operand" "g")
873: (match_operand:QI 2 "general_operand" "g")))]
874: "GET_CODE (operands[2]) == CONST_INT"
875: "*
876: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xff & ~INTVAL (operands[2]));
877: if (rtx_equal_p (operands[1], operands[0]))
878: return \"bicb2 %2,%0\";
879: return \"bicb3 %2,%1,%0\";
880: }")
881:
882: ;;- Bit set instructions.
883:
884: (define_insn "iorsi3"
885: [(set (match_operand:SI 0 "general_operand" "=g")
886: (ior:SI (match_operand:SI 1 "general_operand" "g")
887: (match_operand:SI 2 "general_operand" "g")))]
888: ""
889: "*
890: {
891: if (rtx_equal_p (operands[0], operands[1]))
892: return \"bisl2 %2,%0\";
893: if (rtx_equal_p (operands[0], operands[2]))
894: return \"bisl2 %1,%0\";
895: return \"bisl3 %2,%1,%0\";
896: }")
897:
898: (define_insn "iorhi3"
899: [(set (match_operand:HI 0 "general_operand" "=g")
900: (ior:HI (match_operand:HI 1 "general_operand" "g")
901: (match_operand:HI 2 "general_operand" "g")))]
902: ""
903: "*
904: {
905: if (rtx_equal_p (operands[0], operands[1]))
906: return \"bisw2 %2,%0\";
907: if (rtx_equal_p (operands[0], operands[2]))
908: return \"bisw2 %1,%0\";
909: return \"bisw3 %2,%1,%0\";
910: }")
911:
912: (define_insn "iorqi3"
913: [(set (match_operand:QI 0 "general_operand" "=g")
914: (ior:QI (match_operand:QI 1 "general_operand" "g")
915: (match_operand:QI 2 "general_operand" "g")))]
916: ""
917: "*
918: {
919: if (rtx_equal_p (operands[0], operands[1]))
920: return \"bisb2 %2,%0\";
921: if (rtx_equal_p (operands[0], operands[2]))
922: return \"bisb2 %1,%0\";
923: return \"bisb3 %2,%1,%0\";
924: }")
925:
926: ;;- xor instructions.
927:
928: (define_insn "xorsi3"
929: [(set (match_operand:SI 0 "general_operand" "=g")
930: (xor:SI (match_operand:SI 1 "general_operand" "g")
931: (match_operand:SI 2 "general_operand" "g")))]
932: ""
933: "*
934: {
935: if (rtx_equal_p (operands[0], operands[1]))
936: return \"xorl2 %2,%0\";
937: if (rtx_equal_p (operands[0], operands[2]))
938: return \"xorl2 %1,%0\";
939: return \"xorl3 %2,%1,%0\";
940: }")
941:
942: (define_insn "xorhi3"
943: [(set (match_operand:HI 0 "general_operand" "=g")
944: (xor:HI (match_operand:HI 1 "general_operand" "g")
945: (match_operand:HI 2 "general_operand" "g")))]
946: ""
947: "*
948: {
949: if (rtx_equal_p (operands[0], operands[1]))
950: return \"xorw2 %2,%0\";
951: if (rtx_equal_p (operands[0], operands[2]))
952: return \"xorw2 %1,%0\";
953: return \"xorw3 %2,%1,%0\";
954: }")
955:
956: (define_insn "xorqi3"
957: [(set (match_operand:QI 0 "general_operand" "=g")
958: (xor:QI (match_operand:QI 1 "general_operand" "g")
959: (match_operand:QI 2 "general_operand" "g")))]
960: ""
961: "*
962: {
963: if (rtx_equal_p (operands[0], operands[1]))
964: return \"xorb2 %2,%0\";
965: if (rtx_equal_p (operands[0], operands[2]))
966: return \"xorb2 %1,%0\";
967: return \"xorb3 %2,%1,%0\";
968: }")
969:
970: (define_insn "negdf2"
971: [(set (match_operand:DF 0 "general_operand" "=g")
972: (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
973: ""
1.1.1.3 root 974: "mneg%# %1,%0")
1.1 root 975:
976: (define_insn "negsf2"
977: [(set (match_operand:SF 0 "general_operand" "=g")
978: (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
979: ""
980: "mnegf %1,%0")
981:
982: (define_insn "negsi2"
983: [(set (match_operand:SI 0 "general_operand" "=g")
984: (neg:SI (match_operand:SI 1 "general_operand" "g")))]
985: ""
986: "mnegl %1,%0")
987:
988: (define_insn "neghi2"
989: [(set (match_operand:HI 0 "general_operand" "=g")
990: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
991: ""
992: "mnegw %1,%0")
993:
994: (define_insn "negqi2"
995: [(set (match_operand:QI 0 "general_operand" "=g")
996: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
997: ""
998: "mnegb %1,%0")
999:
1000: (define_insn "one_cmplsi2"
1001: [(set (match_operand:SI 0 "general_operand" "=g")
1002: (not:SI (match_operand:SI 1 "general_operand" "g")))]
1003: ""
1004: "mcoml %1,%0")
1005:
1006: (define_insn "one_cmplhi2"
1007: [(set (match_operand:HI 0 "general_operand" "=g")
1008: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1009: ""
1010: "mcomw %1,%0")
1011:
1012: (define_insn "one_cmplqi2"
1013: [(set (match_operand:QI 0 "general_operand" "=g")
1014: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1015: ""
1016: "mcomb %1,%0")
1017:
1018: (define_insn "ashlsi3"
1019: [(set (match_operand:SI 0 "general_operand" "=g")
1020: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1021: (match_operand:QI 2 "general_operand" "g")))]
1022: ""
1.1.1.2 root 1023: "*
1024: {
1025: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1026: return \"addl2 %0,%0\";
1027: return \"ashl %2,%1,%0\";
1028: }")
1.1 root 1029:
1030: (define_insn "ashldi3"
1031: [(set (match_operand:DI 0 "general_operand" "=g")
1032: (ashift:DI (match_operand:DI 1 "general_operand" "g")
1033: (match_operand:QI 2 "general_operand" "g")))]
1034: ""
1035: "ashq %2,%1,%0")
1036:
1037: (define_insn "rotlsi3"
1038: [(set (match_operand:SI 0 "general_operand" "=g")
1039: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1040: (match_operand:QI 2 "general_operand" "g")))]
1041: ""
1042: "rotl %2,%1,%0")
1043:
1044: (define_insn "rotldi3"
1045: [(set (match_operand:DI 0 "general_operand" "=g")
1046: (rotate:DI (match_operand:DI 1 "general_operand" "g")
1047: (match_operand:QI 2 "general_operand" "g")))]
1048: ""
1049: "rotq %2,%1,%0")
1050:
1.1.1.2 root 1051: ;This insn is probably slower than a multiply and an add.
1052: ;(define_insn ""
1053: ; [(set (match_operand:SI 0 "general_operand" "=g")
1054: ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1055: ; (match_operand:SI 2 "general_operand" "g"))
1056: ; (match_operand:SI 3 "general_operand" "g")))]
1057: ; ""
1058: ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1.1.1.4 root 1059:
1060: ;; Special cases of bit-field insns which we should
1061: ;; recognize in preference to the general case.
1062: ;; These handle aligned 8-bit and 16-bit fields,
1063: ;; which can usually be done with move instructions.
1064:
1065: (define_insn ""
1066: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro")
1067: (match_operand:SI 1 "immediate_operand" "i")
1068: (match_operand:SI 2 "immediate_operand" "i"))
1069: (match_operand:SI 3 "general_operand" "g"))]
1070: "GET_CODE (operands[1]) == CONST_INT
1071: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1072: && GET_CODE (operands[2]) == CONST_INT
1073: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1074: && (GET_CODE (operands[0]) == REG
1075: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1076: "*
1077: {
1078: if (REG_P (operands[0]))
1079: {
1080: if (INTVAL (operands[2]) != 0)
1081: return \"insv %3,%2,%1,%0\";
1082: }
1083: else
1084: operands[0]
1085: = adj_offsetable_operand (operands[0], INTVAL (operands[2]) / 8);
1086:
1087: if (INTVAL (operands[1]) == 8)
1088: return \"movb %3,%0\";
1089: return \"movw %3,%0\";
1090: }")
1091:
1092: (define_insn ""
1093: [(set (match_operand:SI 0 "general_operand" "=&g")
1094: (zero_extract:SI (match_operand:SI 1 "general_operand" "ro")
1095: (match_operand:SI 2 "immediate_operand" "i")
1096: (match_operand:SI 3 "immediate_operand" "i")))]
1097: "GET_CODE (operands[2]) == CONST_INT
1098: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1099: && GET_CODE (operands[3]) == CONST_INT
1100: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1101: && (GET_CODE (operands[1]) == REG
1102: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1103: "*
1104: {
1105: if (REG_P (operands[1]))
1106: {
1107: if (INTVAL (operands[3]) != 0)
1108: return \"extzv %3,%2,%1,%0\";
1109: }
1110: else
1111: operands[1]
1112: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8);
1113:
1114: if (INTVAL (operands[2]) == 8)
1115: return \"movzbl %1,%0\";
1116: return \"movzwl %1,%0\";
1117: }")
1118:
1119: (define_insn ""
1120: [(set (match_operand:SI 0 "general_operand" "=g")
1121: (sign_extract:SI (match_operand:SI 1 "general_operand" "ro")
1122: (match_operand:SI 2 "immediate_operand" "i")
1123: (match_operand:SI 3 "immediate_operand" "i")))]
1124: "GET_CODE (operands[2]) == CONST_INT
1125: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1126: && GET_CODE (operands[3]) == CONST_INT
1127: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1128: && (GET_CODE (operands[1]) == REG
1129: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1130: "*
1131: {
1132: if (REG_P (operands[1]))
1133: {
1134: if (INTVAL (operands[3]) != 0)
1135: return \"extv %3,%2,%1,%0\";
1136: }
1137: else
1138: operands[1]
1139: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8);
1140:
1141: if (INTVAL (operands[2]) == 8)
1142: return \"cvtbl %1,%0\";
1143: return \"cvtwl %1,%0\";
1144: }")
1145:
1146: ;; Register-only SImode cases of bit-field insns.
1.1 root 1147:
1148: (define_insn ""
1149: [(set (cc0)
1150: (minus
1.1.1.4 root 1151: (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1.1 root 1152: (match_operand:SI 1 "general_operand" "g")
1153: (match_operand:SI 2 "general_operand" "g"))
1154: (match_operand:SI 3 "general_operand" "g")))]
1155: ""
1156: "cmpv %2,%1,%0,%3")
1157:
1158: (define_insn ""
1159: [(set (cc0)
1160: (minus
1.1.1.4 root 1161: (zero_extract:SI (match_operand:SI 0 "general_operand" "r")
1.1 root 1162: (match_operand:SI 1 "general_operand" "g")
1163: (match_operand:SI 2 "general_operand" "g"))
1164: (match_operand:SI 3 "general_operand" "g")))]
1165: ""
1166: "cmpzv %2,%1,%0,%3")
1167:
1.1.1.4 root 1168: (define_insn ""
1.1 root 1169: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1170: (sign_extract:SI (match_operand:SI 1 "general_operand" "r")
1.1 root 1171: (match_operand:SI 2 "general_operand" "g")
1172: (match_operand:SI 3 "general_operand" "g")))]
1173: ""
1174: "extv %3,%2,%1,%0")
1175:
1.1.1.4 root 1176: (define_insn ""
1.1 root 1177: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1178: (zero_extract:SI (match_operand:SI 1 "general_operand" "r")
1.1 root 1179: (match_operand:SI 2 "general_operand" "g")
1180: (match_operand:SI 3 "general_operand" "g")))]
1181: ""
1182: "extzv %3,%2,%1,%0")
1183:
1.1.1.4 root 1184: ;; Non-register cases.
1185: ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1186: ;; don't match these (and therefore match the cases above instead).
1187:
1.1 root 1188: (define_insn ""
1.1.1.4 root 1189: [(set (cc0)
1190: (minus
1191: (sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1192: (match_operand:SI 1 "general_operand" "g")
1193: (match_operand:SI 2 "general_operand" "g"))
1194: (match_operand:SI 3 "general_operand" "g")))]
1195: ""
1196: "cmpv %2,%1,%0,%3")
1197:
1198: (define_insn ""
1199: [(set (cc0)
1200: (minus
1201: (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1202: (match_operand:SI 1 "general_operand" "g")
1203: (match_operand:SI 2 "general_operand" "g"))
1204: (match_operand:SI 3 "general_operand" "g")))]
1205: ""
1206: "cmpzv %2,%1,%0,%3")
1207:
1208: (define_insn "extv"
1.1 root 1209: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1210: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1.1 root 1211: (match_operand:SI 2 "general_operand" "g")
1212: (match_operand:SI 3 "general_operand" "g")))]
1213: ""
1214: "extv %3,%2,%1,%0")
1215:
1.1.1.4 root 1216: (define_insn "extzv"
1.1 root 1217: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1218: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1.1 root 1219: (match_operand:SI 2 "general_operand" "g")
1220: (match_operand:SI 3 "general_operand" "g")))]
1221: ""
1222: "extzv %3,%2,%1,%0")
1223:
1224: (define_insn "insv"
1.1.1.2 root 1225: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1.1 root 1226: (match_operand:SI 1 "general_operand" "g")
1227: (match_operand:SI 2 "general_operand" "g"))
1228: (match_operand:SI 3 "general_operand" "g"))]
1229: ""
1230: "insv %3,%2,%1,%0")
1231:
1232: (define_insn ""
1.1.1.2 root 1233: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1.1 root 1234: (match_operand:SI 1 "general_operand" "g")
1235: (match_operand:SI 2 "general_operand" "g"))
1236: (match_operand:SI 3 "general_operand" "g"))]
1237: ""
1238: "insv %3,%2,%1,%0")
1239:
1240: (define_insn "jump"
1241: [(set (pc)
1242: (label_ref (match_operand 0 "" "")))]
1243: ""
1244: "jbr %l0")
1245:
1246: (define_insn "beq"
1247: [(set (pc)
1248: (if_then_else (eq (cc0)
1249: (const_int 0))
1250: (label_ref (match_operand 0 "" ""))
1251: (pc)))]
1252: ""
1253: "jeql %l0")
1254:
1255: (define_insn "bne"
1256: [(set (pc)
1257: (if_then_else (ne (cc0)
1258: (const_int 0))
1259: (label_ref (match_operand 0 "" ""))
1260: (pc)))]
1261: ""
1262: "jneq %l0")
1263:
1264: (define_insn "bgt"
1265: [(set (pc)
1266: (if_then_else (gt (cc0)
1267: (const_int 0))
1268: (label_ref (match_operand 0 "" ""))
1269: (pc)))]
1270: ""
1271: "jgtr %l0")
1272:
1273: (define_insn "bgtu"
1274: [(set (pc)
1275: (if_then_else (gtu (cc0)
1276: (const_int 0))
1277: (label_ref (match_operand 0 "" ""))
1278: (pc)))]
1279: ""
1280: "jgtru %l0")
1281:
1282: (define_insn "blt"
1283: [(set (pc)
1284: (if_then_else (lt (cc0)
1285: (const_int 0))
1286: (label_ref (match_operand 0 "" ""))
1287: (pc)))]
1288: ""
1289: "jlss %l0")
1290:
1291: (define_insn "bltu"
1292: [(set (pc)
1293: (if_then_else (ltu (cc0)
1294: (const_int 0))
1295: (label_ref (match_operand 0 "" ""))
1296: (pc)))]
1297: ""
1298: "jlssu %l0")
1299:
1300: (define_insn "bge"
1301: [(set (pc)
1302: (if_then_else (ge (cc0)
1303: (const_int 0))
1304: (label_ref (match_operand 0 "" ""))
1305: (pc)))]
1306: ""
1307: "jgeq %l0")
1308:
1309: (define_insn "bgeu"
1310: [(set (pc)
1311: (if_then_else (geu (cc0)
1312: (const_int 0))
1313: (label_ref (match_operand 0 "" ""))
1314: (pc)))]
1315: ""
1316: "jgequ %l0")
1317:
1318: (define_insn "ble"
1319: [(set (pc)
1320: (if_then_else (le (cc0)
1321: (const_int 0))
1322: (label_ref (match_operand 0 "" ""))
1323: (pc)))]
1324: ""
1325: "jleq %l0")
1326:
1327: (define_insn "bleu"
1328: [(set (pc)
1329: (if_then_else (leu (cc0)
1330: (const_int 0))
1331: (label_ref (match_operand 0 "" ""))
1332: (pc)))]
1333: ""
1334: "jlequ %l0")
1335:
1336: (define_insn ""
1337: [(set (pc)
1338: (if_then_else (eq (cc0)
1339: (const_int 0))
1340: (pc)
1341: (label_ref (match_operand 0 "" ""))))]
1342: ""
1343: "jneq %l0")
1344:
1345: (define_insn ""
1346: [(set (pc)
1347: (if_then_else (ne (cc0)
1348: (const_int 0))
1349: (pc)
1350: (label_ref (match_operand 0 "" ""))))]
1351: ""
1352: "jeql %l0")
1353:
1354: (define_insn ""
1355: [(set (pc)
1356: (if_then_else (gt (cc0)
1357: (const_int 0))
1358: (pc)
1359: (label_ref (match_operand 0 "" ""))))]
1360: ""
1361: "jleq %l0")
1362:
1363: (define_insn ""
1364: [(set (pc)
1365: (if_then_else (gtu (cc0)
1366: (const_int 0))
1367: (pc)
1368: (label_ref (match_operand 0 "" ""))))]
1369: ""
1370: "jlequ %l0")
1371:
1372: (define_insn ""
1373: [(set (pc)
1374: (if_then_else (lt (cc0)
1375: (const_int 0))
1376: (pc)
1377: (label_ref (match_operand 0 "" ""))))]
1378: ""
1379: "jgeq %l0")
1380:
1381: (define_insn ""
1382: [(set (pc)
1383: (if_then_else (ltu (cc0)
1384: (const_int 0))
1385: (pc)
1386: (label_ref (match_operand 0 "" ""))))]
1387: ""
1388: "jgequ %l0")
1389:
1390: (define_insn ""
1391: [(set (pc)
1392: (if_then_else (ge (cc0)
1393: (const_int 0))
1394: (pc)
1395: (label_ref (match_operand 0 "" ""))))]
1396: ""
1397: "jlss %l0")
1398:
1399: (define_insn ""
1400: [(set (pc)
1401: (if_then_else (geu (cc0)
1402: (const_int 0))
1403: (pc)
1404: (label_ref (match_operand 0 "" ""))))]
1405: ""
1406: "jlssu %l0")
1407:
1408: (define_insn ""
1409: [(set (pc)
1410: (if_then_else (le (cc0)
1411: (const_int 0))
1412: (pc)
1413: (label_ref (match_operand 0 "" ""))))]
1414: ""
1415: "jgtr %l0")
1416:
1417: (define_insn ""
1418: [(set (pc)
1419: (if_then_else (leu (cc0)
1420: (const_int 0))
1421: (pc)
1422: (label_ref (match_operand 0 "" ""))))]
1423: ""
1424: "jgtru %l0")
1425:
1426: ;; Recognize jbs and jbc instructions.
1427:
1428: (define_insn ""
1429: [(set (pc)
1430: (if_then_else
1431: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1432: (const_int 1)
1433: (match_operand:SI 1 "general_operand" "g"))
1434: (const_int 0))
1435: (label_ref (match_operand 2 "" ""))
1436: (pc)))]
1437: ""
1438: "jbs %1,%0,%l2")
1439:
1440: (define_insn ""
1441: [(set (pc)
1442: (if_then_else
1443: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1444: (const_int 1)
1445: (match_operand:SI 1 "general_operand" "g"))
1446: (const_int 0))
1447: (label_ref (match_operand 2 "" ""))
1448: (pc)))]
1449: ""
1450: "jbc %1,%0,%l2")
1451:
1452: (define_insn ""
1453: [(set (pc)
1454: (if_then_else
1455: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1456: (const_int 1)
1457: (match_operand:SI 1 "general_operand" "g"))
1458: (const_int 0))
1459: (pc)
1460: (label_ref (match_operand 2 "" ""))))]
1461: ""
1462: "jbc %1,%0,%l2")
1463:
1464: (define_insn ""
1465: [(set (pc)
1466: (if_then_else
1467: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1468: (const_int 1)
1469: (match_operand:SI 1 "general_operand" "g"))
1470: (const_int 0))
1471: (pc)
1472: (label_ref (match_operand 2 "" ""))))]
1473: ""
1474: "jbs %1,%0,%l2")
1475:
1476: (define_insn ""
1477: [(set (pc)
1478: (if_then_else
1479: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1480: (const_int 1)
1481: (match_operand:SI 1 "general_operand" "g"))
1482: (const_int 0))
1483: (label_ref (match_operand 2 "" ""))
1484: (pc)))]
1.1.1.2 root 1485: "GET_CODE (operands[0]) != MEM
1486: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1487: "jbs %1,%0,%l2")
1488:
1489: (define_insn ""
1490: [(set (pc)
1491: (if_then_else
1492: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1493: (const_int 1)
1494: (match_operand:SI 1 "general_operand" "g"))
1495: (const_int 0))
1496: (label_ref (match_operand 2 "" ""))
1497: (pc)))]
1.1.1.2 root 1498: "GET_CODE (operands[0]) != MEM
1499: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1500: "jbc %1,%0,%l2")
1501:
1502: (define_insn ""
1503: [(set (pc)
1504: (if_then_else
1.1.1.2 root 1505: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1506: (match_operand:SI 1 "general_operand" "g"))
1507: (const_int 0))
1508: (pc)
1509: (label_ref (match_operand 2 "" ""))))]
1510: "GET_CODE (operands[1]) == CONST_INT
1511: && exact_log2 (INTVAL (operands[1])) >= 0
1512: && (GET_CODE (operands[0]) != MEM
1513: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1514: "*
1515: {
1516: operands[1]
1517: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1518: return \"jbs %1,%0,%l2\";
1519: }")
1520:
1521: (define_insn ""
1522: [(set (pc)
1523: (if_then_else
1524: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1525: (match_operand:SI 1 "general_operand" "g"))
1526: (const_int 0))
1527: (label_ref (match_operand 2 "" ""))
1528: (pc)))]
1529: "GET_CODE (operands[1]) == CONST_INT
1530: && exact_log2 (INTVAL (operands[1])) >= 0
1531: && (GET_CODE (operands[0]) != MEM
1532: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1533: "*
1534: {
1535: operands[1]
1536: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1537: return \"jbc %1,%0,%l2\";
1538: }")
1539:
1540: (define_insn ""
1541: [(set (pc)
1542: (if_then_else
1543: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1544: (match_operand:SI 1 "general_operand" "g"))
1545: (const_int 0))
1546: (pc)
1547: (label_ref (match_operand 2 "" ""))))]
1548: "GET_CODE (operands[1]) == CONST_INT
1549: && exact_log2 (INTVAL (operands[1])) >= 0
1550: && (GET_CODE (operands[0]) != MEM
1551: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1552: "*
1553: {
1554: operands[1]
1555: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1556: return \"jbc %1,%0,%l2\";
1557: }")
1558:
1559: (define_insn ""
1560: [(set (pc)
1561: (if_then_else
1562: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1563: (match_operand:SI 1 "general_operand" "g"))
1564: (const_int 0))
1565: (label_ref (match_operand 2 "" ""))
1566: (pc)))]
1567: "GET_CODE (operands[1]) == CONST_INT
1568: && exact_log2 (INTVAL (operands[1])) >= 0
1569: && (GET_CODE (operands[0]) != MEM
1570: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1571: "*
1572: {
1573: operands[1]
1574: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1575: return \"jbs %1,%0,%l2\";
1576: }")
1577:
1578: (define_insn ""
1579: [(set (pc)
1580: (if_then_else
1.1 root 1581: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1582: (const_int 1)
1583: (match_operand:SI 1 "general_operand" "g"))
1584: (const_int 0))
1585: (pc)
1586: (label_ref (match_operand 2 "" ""))))]
1.1.1.2 root 1587: "GET_CODE (operands[0]) != MEM
1588: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1589: "jbc %1,%0,%l2")
1590:
1591: (define_insn ""
1592: [(set (pc)
1593: (if_then_else
1594: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1595: (const_int 1)
1596: (match_operand:SI 1 "general_operand" "g"))
1597: (const_int 0))
1598: (pc)
1599: (label_ref (match_operand 2 "" ""))))]
1.1.1.2 root 1600: "GET_CODE (operands[0]) != MEM
1601: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1602: "jbs %1,%0,%l2")
1603:
1604: (define_insn ""
1605: [(set (pc)
1606: (if_then_else
1607: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1608: (const_int 1))
1609: (const_int 0))
1610: (label_ref (match_operand 1 "" ""))
1611: (pc)))]
1.1.1.2 root 1612: "GET_CODE (operands[0]) != MEM
1613: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1614: "jlbs %0,%l1")
1615:
1616: (define_insn ""
1617: [(set (pc)
1618: (if_then_else
1619: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1620: (const_int 1))
1621: (const_int 0))
1622: (label_ref (match_operand 1 "" ""))
1623: (pc)))]
1.1.1.2 root 1624: "GET_CODE (operands[0]) != MEM
1625: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1626: "jlbc %0,%l1")
1627:
1628: (define_insn ""
1629: [(set (pc)
1630: (if_then_else
1631: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1632: (const_int 1))
1633: (const_int 0))
1634: (pc)
1635: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1636: "GET_CODE (operands[0]) != MEM
1637: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1638: "jlbc %0,%l1")
1639:
1640: (define_insn ""
1641: [(set (pc)
1642: (if_then_else
1643: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1644: (const_int 1))
1645: (const_int 0))
1646: (pc)
1647: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1648: "GET_CODE (operands[0]) != MEM
1649: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1650: "jlbs %0,%l1")
1651:
1652: ;; These four entries allow a jlbc or jlbs to be made
1653: ;; by combination with a bic.
1654: (define_insn ""
1655: [(set (pc)
1656: (if_then_else
1657: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1658: (not:SI (const_int -2)))
1659: (const_int 0))
1660: (label_ref (match_operand 1 "" ""))
1661: (pc)))]
1.1.1.2 root 1662: "GET_CODE (operands[0]) != MEM
1663: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1664: "jlbs %0,%l1")
1665:
1666: (define_insn ""
1667: [(set (pc)
1668: (if_then_else
1669: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1670: (not:SI (const_int -2)))
1671: (const_int 0))
1672: (label_ref (match_operand 1 "" ""))
1673: (pc)))]
1.1.1.2 root 1674: "GET_CODE (operands[0]) != MEM
1675: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1676: "jlbc %0,%l1")
1677:
1678: (define_insn ""
1679: [(set (pc)
1680: (if_then_else
1681: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1682: (not:SI (const_int -2)))
1683: (const_int 0))
1684: (pc)
1685: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1686: "GET_CODE (operands[0]) != MEM
1687: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1688: "jlbc %0,%l1")
1689:
1690: (define_insn ""
1691: [(set (pc)
1692: (if_then_else
1693: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1694: (not:SI (const_int -2)))
1695: (const_int 0))
1696: (pc)
1697: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1698: "GET_CODE (operands[0]) != MEM
1699: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1700: "jlbs %0,%l1")
1701:
1702: ;; Subtract-and-jump and Add-and-jump insns.
1703: ;; These are not used when output is for the Unix assembler
1704: ;; because it does not know how to modify them to reach far.
1705:
1706: ;; Normal sob insns.
1707:
1708: (define_insn ""
1709: [(set (pc)
1710: (if_then_else
1711: (gt (minus:SI (match_operand:SI 0 "general_operand" "+g")
1712: (const_int 1))
1713: (const_int 0))
1714: (label_ref (match_operand 1 "" ""))
1715: (pc)))
1716: (set (match_dup 0)
1.1.1.2 root 1717: (plus:SI (match_dup 0)
1718: (const_int -1)))]
1.1 root 1719: "!TARGET_UNIX_ASM"
1720: "jsobgtr %0,%l1")
1721:
1722: (define_insn ""
1723: [(set (pc)
1724: (if_then_else
1725: (ge (minus:SI (match_operand:SI 0 "general_operand" "+g")
1726: (const_int 1))
1727: (const_int 0))
1728: (label_ref (match_operand 1 "" ""))
1729: (pc)))
1730: (set (match_dup 0)
1.1.1.2 root 1731: (plus:SI (match_dup 0)
1732: (const_int -1)))]
1.1 root 1733: "!TARGET_UNIX_ASM"
1734: "jsobgeq %0,%l1")
1735:
1736: ;; Reversed sob insns.
1737:
1738: (define_insn ""
1739: [(set (pc)
1740: (if_then_else
1741: (le (minus:SI (match_operand:SI 0 "general_operand" "+g")
1742: (const_int 1))
1743: (const_int 0))
1744: (pc)
1745: (label_ref (match_operand 1 "" ""))))
1746: (set (match_dup 0)
1.1.1.2 root 1747: (plus:SI (match_dup 0)
1748: (const_int -1)))]
1.1 root 1749: "!TARGET_UNIX_ASM"
1750: "jsobgtr %0,%l1")
1751:
1752: (define_insn ""
1753: [(set (pc)
1754: (if_then_else
1755: (lt (minus:SI (match_operand:SI 0 "general_operand" "+g")
1756: (const_int 1))
1757: (const_int 0))
1758: (pc)
1759: (label_ref (match_operand 1 "" ""))))
1760: (set (match_dup 0)
1.1.1.2 root 1761: (plus:SI (match_dup 0)
1762: (const_int -1)))]
1.1 root 1763: "!TARGET_UNIX_ASM"
1764: "jsobgeq %0,%l1")
1765:
1766: ;; Normal aob insns.
1767: (define_insn ""
1768: [(set (pc)
1769: (if_then_else
1770: (lt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1771: (const_int 1))
1772: (match_operand:SI 1 "general_operand" "g"))
1773: (const_int 0))
1774: (label_ref (match_operand 2 "" ""))
1775: (pc)))
1776: (set (match_dup 0)
1777: (plus:SI (match_dup 0)
1778: (const_int 1)))]
1779: "!TARGET_UNIX_ASM"
1780: "jaoblss %1,%0,%l2")
1781:
1782: (define_insn ""
1783: [(set (pc)
1784: (if_then_else
1785: (le (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1786: (const_int 1))
1787: (match_operand:SI 1 "general_operand" "g"))
1788: (const_int 0))
1789: (label_ref (match_operand 2 "" ""))
1790: (pc)))
1791: (set (match_dup 0)
1792: (plus:SI (match_dup 0)
1793: (const_int 1)))]
1794: "!TARGET_UNIX_ASM"
1795: "jaobleq %1,%0,%l2")
1796:
1797: ;; Reverse aob insns.
1798: (define_insn ""
1799: [(set (pc)
1800: (if_then_else
1801: (ge (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1802: (const_int 1))
1803: (match_operand:SI 1 "general_operand" "g"))
1804: (const_int 0))
1805: (pc)
1806: (label_ref (match_operand 2 "" ""))))
1807: (set (match_dup 0)
1808: (plus:SI (match_dup 0)
1809: (const_int 1)))]
1810: "!TARGET_UNIX_ASM"
1811: "jaoblss %1,%0,%l2")
1812:
1813: (define_insn ""
1814: [(set (pc)
1815: (if_then_else
1816: (gt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1817: (const_int 1))
1818: (match_operand:SI 1 "general_operand" "g"))
1819: (const_int 0))
1820: (pc)
1821: (label_ref (match_operand 2 "" ""))))
1822: (set (match_dup 0)
1823: (plus:SI (match_dup 0)
1824: (const_int 1)))]
1825: "!TARGET_UNIX_ASM"
1826: "jaobleq %1,%0,%l2")
1.1.1.5 root 1827:
1828: ;; Something like a sob insn, but compares against -1.
1829: ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1830:
1831: (define_insn ""
1832: [(set (pc)
1833: (if_then_else
1834: (ne (minus (plus:SI (match_operand:SI 0 "general_operand" "g")
1835: (const_int -1))
1836: (const_int -1))
1837: (const_int 0))
1838: (label_ref (match_operand 1 "" ""))
1839: (pc)))
1840: (set (match_dup 0)
1841: (plus:SI (match_dup 0)
1842: (const_int -1)))]
1843: ""
1844: "decl %0\;jgequ %l1")
1.1 root 1845:
1.1.1.2 root 1846: ;; Note that operand 1 is total size of args, in bytes,
1847: ;; and what the call insn wants is the number of words.
1.1 root 1848: (define_insn "call"
1849: [(call (match_operand:QI 0 "general_operand" "g")
1850: (match_operand:QI 1 "general_operand" "g"))]
1851: ""
1.1.1.2 root 1852: "*
1.1.1.5 root 1853: if (INTVAL (operands[1]) > 255 * 4)
1854: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1855: return \"calls $0,%0\;addl2 %1,sp\";
1.1.1.2 root 1856: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);
1857: return \"calls %1,%0\";
1858: ")
1859:
1860: (define_insn "call_value"
1861: [(set (match_operand 0 "" "g")
1862: (call (match_operand:QI 1 "general_operand" "g")
1863: (match_operand:QI 2 "general_operand" "g")))]
1864: ""
1865: "*
1.1.1.6 ! root 1866: if (INTVAL (operands[1]) > 255 * 4)
! 1867: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
! 1868: return \"calls $0,%1\;addl2 %2,sp\";
1.1.1.2 root 1869: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4);
1870: return \"calls %2,%1\";
1871: ")
1.1 root 1872:
1873: (define_insn "return"
1874: [(return)]
1875: ""
1876: "ret")
1877:
1878: (define_insn "casesi"
1879: [(set (pc)
1880: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
1881: (match_operand:SI 1 "general_operand" "g"))
1882: (match_operand:SI 2 "general_operand" "g"))
1.1.1.2 root 1883: (plus:SI (sign_extend:SI
1.1 root 1884: (mem:HI (plus:SI (pc)
1885: (minus:SI (match_dup 0)
1.1.1.2 root 1886: (match_dup 1)))))
1887: (label_ref:SI (match_operand 3 "" "")))
1.1 root 1888: (pc)))]
1889: ""
1890: "casel %0,%1,%2")
1891:
1.1.1.2 root 1892: ;; This used to arise from the preceding by simplification
1893: ;; if operand 1 is zero. Perhaps it is no longer necessary.
1894: (define_insn ""
1895: [(set (pc)
1896: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1897: (match_operand:SI 1 "general_operand" "g"))
1898: (plus:SI (sign_extend:SI
1899: (mem:HI (plus:SI (pc)
1900: (minus:SI (match_dup 0)
1901: (const_int 0)))))
1902: (label_ref:SI (match_operand 3 "" "")))
1903: (pc)))]
1904: ""
1905: "casel %0,$0,%1")
1906:
1.1 root 1907: ;; This arises from the preceding by simplification if operand 1 is zero.
1908: (define_insn ""
1909: [(set (pc)
1910: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1911: (match_operand:SI 1 "general_operand" "g"))
1.1.1.2 root 1912: (plus:SI (sign_extend:SI
1.1 root 1913: (mem:HI (plus:SI (pc)
1.1.1.2 root 1914: (match_dup 0))))
1915: (label_ref:SI (match_operand 3 "" "")))
1.1 root 1916: (pc)))]
1917: ""
1918: "casel %0,$0,%1")
1919:
1.1.1.2 root 1920: ;; Optimize extzv ...,z; andl2 ...,z
1921: ;; with other operands constant.
1922: (define_peephole
1923: [(set (match_operand:SI 0 "general_operand" "g")
1924: (zero_extract:SI (match_operand:SI 1 "general_operand" "g")
1925: (match_operand:SI 2 "general_operand" "g")
1926: (match_operand:SI 3 "general_operand" "g")))
1927: (set (match_operand:SI 4 "general_operand" "g")
1928: (and:SI (match_dup 0)
1929: (match_operand:SI 5 "general_operand" "g")))]
1930: "GET_CODE (operands[2]) == CONST_INT
1931: && GET_CODE (operands[3]) == CONST_INT
1932: && (INTVAL (operands[2]) + INTVAL (operands[3])) == 32
1933: && GET_CODE (operands[5]) == CONST_INT
1934: && dead_or_set_p (insn, operands[0])"
1935: "*
1936: {
1937: unsigned long mask = INTVAL (operands[5]);
1938: operands[3] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[3]));
1939:
1940: if ((floor_log2 (mask) + 1) >= INTVAL (operands[2]))
1941: mask &= ((1 << INTVAL (operands[2])) - 1);
1942:
1943: operands[5] = gen_rtx (CONST_INT, VOIDmode, ~mask);
1944: if (push_operand (operands[4], SImode))
1945: {
1946: output_asm_insn (\"rotl %3,%1,%0\", operands);
1947: return \"bicl3 %5,%0,%4\";
1948: }
1949: else
1950: {
1951: output_asm_insn (\"rotl %3,%1,%4\", operands);
1952: return \"bicl2 %5,%4\";
1953: }
1954: }")
1955:
1956: ;; Optimize andl3 x,y,z; extzv z,....,z
1957:
1958: (define_peephole
1959: [(set (match_operand:SI 0 "general_operand" "g")
1960: (and:SI (match_operand:SI 1 "general_operand" "g")
1961: (match_operand:SI 2 "general_operand" "g")))
1962: (set (match_operand 3 "general_operand" "g")
1963: (zero_extract:SI (match_dup 0)
1964: (match_operand:SI 4 "general_operand" "g")
1965: (match_operand:SI 5 "general_operand" "g")))]
1966: "GET_CODE (operands[2]) == CONST_INT
1967: && GET_CODE (operands[4]) == CONST_INT
1968: && GET_CODE (operands[5]) == CONST_INT
1969: && (INTVAL (operands[4]) + INTVAL (operands[5])) == 32
1970: && dead_or_set_p (insn, operands[0])"
1971: "*
1972: {
1973: unsigned long mask = INTVAL (operands[2]);
1974:
1975: mask &= ~((1 << INTVAL (operands[5])) - 1);
1976: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~mask);
1977:
1978: operands[5] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[5]));
1979:
1980: if (rtx_equal_p (operands[0], operands[1]))
1981: output_asm_insn (\"bicl2 %2,%0\", operands);
1982: else
1983: output_asm_insn (\"bicl3 %2,%1,%0\", operands);
1984: return \"rotl %5,%0,%3\";
1985: }")
1986:
1.1 root 1987: ;;- Local variables:
1988: ;;- mode:emacs-lisp
1989: ;;- comment-start: ";;- "
1990: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
1991: ;;- eval: (modify-syntax-entry ?[ "(]")
1992: ;;- eval: (modify-syntax-entry ?] ")[")
1993: ;;- eval: (modify-syntax-entry ?{ "(}")
1994: ;;- eval: (modify-syntax-entry ?} "){")
1995: ;;- End:
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