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1.1.1.4 root 1:
1.1 root 2: ;;- Machine description for GNU compiler
3: ;;- Vax Version
4: ;; Copyright (C) 1987 Free Software Foundation, Inc.
5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is distributed in the hope that it will be useful,
9: ;; but WITHOUT ANY WARRANTY. No author or distributor
10: ;; accepts responsibility to anyone for the consequences of using it
11: ;; or for whether it serves any particular purpose or works at all,
12: ;; unless he says so in writing. Refer to the GNU CC General Public
13: ;; License for full details.
14:
15: ;; Everyone is granted permission to copy, modify and redistribute
16: ;; GNU CC, but only under the conditions described in the
17: ;; GNU CC General Public License. A copy of this license is
18: ;; supposed to have been given to you along with GNU CC so you
19: ;; can know your rights and responsibilities. It should be in a
20: ;; file named COPYING. Among other things, the copyright notice
21: ;; and this notice must be preserved on all copies.
22:
23:
24: ;;- Instruction patterns. When multiple patterns apply,
25: ;;- the first one in the file is chosen.
26: ;;-
27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28: ;;-
29: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
30: ;;- updates for most instructions.
31:
1.1.1.2 root 32: ; tstsi is first test insn so that it is the one to match
33: ; a constant argument.
1.1 root 34:
35: (define_insn "tstsi"
36: [(set (cc0)
37: (match_operand:SI 0 "general_operand" "g"))]
38: ""
39: "tstl %0")
40:
41: (define_insn "tsthi"
42: [(set (cc0)
43: (match_operand:HI 0 "general_operand" "g"))]
44: ""
45: "tstw %0")
46:
47: (define_insn "tstqi"
48: [(set (cc0)
49: (match_operand:QI 0 "general_operand" "g"))]
50: ""
51: "tstb %0")
52:
1.1.1.2 root 53: (define_insn "tstdf"
1.1 root 54: [(set (cc0)
1.1.1.2 root 55: (match_operand:DF 0 "general_operand" "gF"))]
1.1 root 56: ""
1.1.1.3 root 57: "tst%# %0")
1.1 root 58:
1.1.1.2 root 59: (define_insn "tstsf"
1.1 root 60: [(set (cc0)
1.1.1.2 root 61: (match_operand:SF 0 "general_operand" "gF"))]
1.1 root 62: ""
1.1.1.2 root 63: "tstf %0")
1.1 root 64:
65: (define_insn "cmpsi"
66: [(set (cc0)
67: (minus (match_operand:SI 0 "general_operand" "g")
68: (match_operand:SI 1 "general_operand" "g")))]
69: ""
70: "cmpl %0,%1")
71:
72: (define_insn "cmphi"
73: [(set (cc0)
74: (minus (match_operand:HI 0 "general_operand" "g")
75: (match_operand:HI 1 "general_operand" "g")))]
76: ""
77: "cmpw %0,%1")
78:
79: (define_insn "cmpqi"
80: [(set (cc0)
81: (minus (match_operand:QI 0 "general_operand" "g")
82: (match_operand:QI 1 "general_operand" "g")))]
83: ""
84: "cmpb %0,%1")
85:
1.1.1.2 root 86: (define_insn "cmpdf"
87: [(set (cc0)
88: (minus (match_operand:DF 0 "general_operand" "gF")
89: (match_operand:DF 1 "general_operand" "gF")))]
90: ""
1.1.1.3 root 91: "cmp%# %0,%1")
1.1.1.2 root 92:
93: (define_insn "cmpsf"
94: [(set (cc0)
95: (minus (match_operand:SF 0 "general_operand" "gF")
96: (match_operand:SF 1 "general_operand" "gF")))]
97: ""
98: "cmpf %0,%1")
99:
1.1 root 100: (define_insn ""
101: [(set (cc0)
102: (and:SI (match_operand:SI 0 "general_operand" "g")
103: (match_operand:SI 1 "general_operand" "g")))]
104: ""
105: "bitl %0,%1")
106:
107: (define_insn ""
108: [(set (cc0)
109: (and:HI (match_operand:HI 0 "general_operand" "g")
110: (match_operand:HI 1 "general_operand" "g")))]
111: ""
112: "bitw %0,%1")
113:
114: (define_insn ""
115: [(set (cc0)
116: (and:QI (match_operand:QI 0 "general_operand" "g")
117: (match_operand:QI 1 "general_operand" "g")))]
118: ""
119: "bitb %0,%1")
120:
121: (define_insn "movdf"
122: [(set (match_operand:DF 0 "general_operand" "=g")
123: (match_operand:DF 1 "general_operand" "gF"))]
124: ""
125: "*
126: {
127: if (operands[1] == dconst0_rtx)
1.1.1.3 root 128: return \"clr%# %0\";
129: return \"mov%# %1,%0\";
1.1 root 130: }")
131:
132: (define_insn "movsf"
133: [(set (match_operand:SF 0 "general_operand" "=g")
134: (match_operand:SF 1 "general_operand" "gF"))]
135: ""
136: "*
137: {
138: if (operands[1] == fconst0_rtx)
139: return \"clrf %0\";
1.1.1.7 ! root 140: if (GET_CODE (operands[1]) != CONST_DOUBLE)
! 141: return \"movl %1,%0\";
1.1 root 142: return \"movf %1,%0\";
143: }")
144:
1.1.1.2 root 145: ;; Some vaxes don't support this instruction.
146: ;;(define_insn "movti"
147: ;; [(set (match_operand:TI 0 "general_operand" "=g")
148: ;; (match_operand:TI 1 "general_operand" "g"))]
149: ;; ""
150: ;; "movh %1,%0")
1.1 root 151:
152: (define_insn "movdi"
153: [(set (match_operand:DI 0 "general_operand" "=g")
154: (match_operand:DI 1 "general_operand" "g"))]
155: ""
1.1.1.2 root 156: "movq %1,%0")
1.1 root 157:
158: (define_insn "movsi"
159: [(set (match_operand:SI 0 "general_operand" "=g")
160: (match_operand:SI 1 "general_operand" "g"))]
161: ""
162: "*
163: { if (operands[1] == const1_rtx
1.1.1.2 root 164: && REG_NOTES (insn)
165: && GET_MODE (REG_NOTES (insn)) == (enum machine_mode) REG_WAS_0
166: /* Make sure the insn that stored the 0 is still present. */
167: && ! XEXP (REG_NOTES (insn), 0)->volatil
1.1.1.5 root 168: && GET_CODE (XEXP (REG_NOTES (insn), 0)) != NOTE
169: /* Make sure cross jumping didn't happen here. */
170: && no_labels_between_p (XEXP (REG_NOTES (insn), 0), insn))
1.1.1.2 root 171: /* Fastest way to change a 0 to a 1. */
1.1 root 172: return \"incl %0\";
173: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
174: {
175: if (push_operand (operands[0], SImode))
176: return \"pushab %a1\";
177: return \"movab %a1,%0\";
178: }
179: if (operands[1] == const0_rtx)
180: return \"clrl %0\";
181: if (GET_CODE (operands[1]) == CONST_INT
182: && (unsigned) INTVAL (operands[1]) >= 64)
183: {
184: int i = INTVAL (operands[1]);
185: if ((unsigned)(-i) < 64)
186: {
187: operands[1] = gen_rtx (CONST_INT, VOIDmode, -i);
188: return \"mnegl %1,%0\";
189: }
190: if ((unsigned)i < 0x100)
191: return \"movzbl %1,%0\";
192: if (i >= -0x80 && i < 0)
193: return \"cvtbl %1,%0\";
194: if ((unsigned)i < 0x10000)
195: return \"movzwl %1,%0\";
196: if (i >= -0x8000 && i < 0)
197: return \"cvtwl %1,%0\";
198: }
199: if (push_operand (operands[0], SImode))
200: return \"pushl %1\";
201: return \"movl %1,%0\";
202: }")
203:
204: (define_insn "movhi"
205: [(set (match_operand:HI 0 "general_operand" "=g")
206: (match_operand:HI 1 "general_operand" "g"))]
207: ""
208: "*
209: {
210: if (operands[1] == const1_rtx
1.1.1.2 root 211: && REG_NOTES (insn)
1.1 root 212: && GET_MODE (REG_NOTES (insn)) == (enum machine_mode) REG_WAS_0)
213: return \"incw %0\";
214: if (operands[1] == const0_rtx)
215: return \"clrw %0\";
216: if (GET_CODE (operands[1]) == CONST_INT
217: && (unsigned) INTVAL (operands[1]) >= 64)
218: {
219: int i = INTVAL (operands[1]);
220: if ((unsigned)(-i) < 64)
221: {
222: operands[1] = gen_rtx (CONST_INT, VOIDmode, -i);
223: return \"mnegw %1,%0\";
224: }
225: if ((unsigned)i < 0x100)
226: return \"movzbw %1,%0\";
227: if (i >= -0x80 && i < 0)
228: return \"cvtbw %1,%0\";
229: }
230: return \"movw %1,%0\";
231: }")
232:
233: (define_insn "movqi"
234: [(set (match_operand:QI 0 "general_operand" "=g")
235: (match_operand:QI 1 "general_operand" "g"))]
236: ""
237: "*
238: {
239: if (operands[1] == const0_rtx)
240: return \"clrb %0\";
241: return \"movb %1,%0\";
242: }")
243:
244: ;; The definition of this insn does not really explain what it does,
245: ;; but it should suffice
246: ;; that anything generated as this insn will be recognized as one
247: ;; and that it won't successfully combine with anything.
248: (define_insn "movstrhi"
249: [(set (match_operand:BLK 0 "general_operand" "=g")
250: (match_operand:BLK 1 "general_operand" "g"))
251: (use (match_operand:HI 2 "general_operand" "g"))
1.1.1.2 root 252: (clobber (reg:SI 0))
253: (clobber (reg:SI 1))
254: (clobber (reg:SI 2))
255: (clobber (reg:SI 3))
256: (clobber (reg:SI 4))
257: (clobber (reg:SI 5))]
1.1 root 258: ""
259: "movc3 %2,%1,%0")
260:
261: ;;- load or push effective address
262: ;; These come after the move patterns
263: ;; because we don't want pushl $1 turned into pushad 1.
264:
265: (define_insn ""
266: [(set (match_operand:SI 0 "general_operand" "=g")
267: (match_operand:QI 1 "address_operand" "p"))]
268: ""
269: "*
270: {
271: if (push_operand (operands[0], SImode))
272: return \"pushab %a1\";
273: return \"movab %a1,%0\";
274: }")
275:
276: (define_insn ""
277: [(set (match_operand:SI 0 "general_operand" "=g")
278: (match_operand:HI 1 "address_operand" "p"))]
279: ""
280: "*
281: {
282: if (push_operand (operands[0], SImode))
283: return \"pushaw %a1\";
284: return \"movaw %a1,%0\";
285: }")
286:
287: (define_insn ""
288: [(set (match_operand:SI 0 "general_operand" "=g")
289: (match_operand:SI 1 "address_operand" "p"))]
290: ""
291: "*
292: {
293: if (push_operand (operands[0], SImode))
294: return \"pushal %a1\";
295: return \"moval %a1,%0\";
296: }")
297:
298: (define_insn ""
299: [(set (match_operand:SI 0 "general_operand" "=g")
300: (match_operand:SF 1 "address_operand" "p"))]
301: ""
302: "*
303: {
304: if (push_operand (operands[0], SImode))
305: return \"pushaf %a1\";
306: return \"movaf %a1,%0\";
307: }")
308:
309: (define_insn ""
310: [(set (match_operand:SI 0 "general_operand" "=g")
311: (match_operand:DF 1 "address_operand" "p"))]
312: ""
313: "*
314: {
315: if (push_operand (operands[0], SImode))
316: return \"pushad %a1\";
317: return \"movad %a1,%0\";
318: }")
319:
1.1.1.2 root 320: ;; Extension and truncation insns.
321: ;; Those for integer source operand
322: ;; are ordered widest source type first.
1.1 root 323:
1.1.1.2 root 324: (define_insn "truncsiqi2"
325: [(set (match_operand:QI 0 "general_operand" "=g")
326: (truncate:QI (match_operand:SI 1 "general_operand" "g")))]
1.1 root 327: ""
1.1.1.2 root 328: "cvtlb %1,%0")
1.1 root 329:
1.1.1.2 root 330: (define_insn "truncsihi2"
331: [(set (match_operand:HI 0 "general_operand" "=g")
332: (truncate:HI (match_operand:SI 1 "general_operand" "g")))]
1.1 root 333: ""
1.1.1.2 root 334: "cvtlw %1,%0")
1.1 root 335:
336: (define_insn "trunchiqi2"
337: [(set (match_operand:QI 0 "general_operand" "=g")
338: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
339: ""
340: "cvtwb %1,%0")
341:
342: (define_insn "extendhisi2"
343: [(set (match_operand:SI 0 "general_operand" "=g")
344: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
345: ""
346: "cvtwl %1,%0")
347:
1.1.1.2 root 348: (define_insn "extendqihi2"
349: [(set (match_operand:HI 0 "general_operand" "=g")
350: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1.1 root 351: ""
1.1.1.2 root 352: "cvtbw %1,%0")
1.1 root 353:
1.1.1.2 root 354: (define_insn "extendqisi2"
355: [(set (match_operand:SI 0 "general_operand" "=g")
356: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
357: ""
358: "cvtbl %1,%0")
359:
360: (define_insn "extendsfdf2"
1.1 root 361: [(set (match_operand:DF 0 "general_operand" "=g")
1.1.1.2 root 362: (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
1.1 root 363: ""
1.1.1.3 root 364: "cvtf%# %1,%0")
1.1 root 365:
1.1.1.2 root 366: (define_insn "truncdfsf2"
367: [(set (match_operand:SF 0 "general_operand" "=g")
368: (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
1.1 root 369: ""
1.1.1.3 root 370: "cvt%#f %1,%0")
1.1 root 371:
1.1.1.2 root 372: (define_insn "zero_extendhisi2"
373: [(set (match_operand:SI 0 "general_operand" "=g")
374: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
375: ""
376: "movzwl %1,%0")
377:
378: (define_insn "zero_extendqihi2"
1.1 root 379: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 380: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1.1 root 381: ""
1.1.1.2 root 382: "movzbw %1,%0")
383:
384: (define_insn "zero_extendqisi2"
385: [(set (match_operand:SI 0 "general_operand" "=g")
386: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
387: ""
388: "movzbl %1,%0")
389:
390: ;; Fix-to-float conversion insns.
391: ;; Note that the ones that start with SImode come first.
392: ;; That is so that an operand that is a CONST_INT
393: ;; (and therefore lacks a specific machine mode).
394: ;; will be recognized as SImode (which is always valid)
395: ;; rather than as QImode or HImode.
1.1 root 396:
397: (define_insn "floatsisf2"
398: [(set (match_operand:SF 0 "general_operand" "=g")
399: (float:SF (match_operand:SI 1 "general_operand" "g")))]
400: ""
401: "cvtlf %1,%0")
402:
403: (define_insn "floatsidf2"
404: [(set (match_operand:DF 0 "general_operand" "=g")
405: (float:DF (match_operand:SI 1 "general_operand" "g")))]
406: ""
1.1.1.3 root 407: "cvtl%# %1,%0")
1.1 root 408:
1.1.1.2 root 409: (define_insn "floathisf2"
410: [(set (match_operand:SF 0 "general_operand" "=g")
411: (float:SF (match_operand:HI 1 "general_operand" "g")))]
1.1 root 412: ""
1.1.1.2 root 413: "cvtwf %1,%0")
1.1 root 414:
1.1.1.2 root 415: (define_insn "floathidf2"
416: [(set (match_operand:DF 0 "general_operand" "=g")
417: (float:DF (match_operand:HI 1 "general_operand" "g")))]
1.1 root 418: ""
1.1.1.3 root 419: "cvtw%# %1,%0")
1.1 root 420:
1.1.1.2 root 421: (define_insn "floatqisf2"
422: [(set (match_operand:SF 0 "general_operand" "=g")
423: (float:SF (match_operand:QI 1 "general_operand" "g")))]
1.1 root 424: ""
1.1.1.2 root 425: "cvtbf %1,%0")
1.1 root 426:
1.1.1.2 root 427: (define_insn "floatqidf2"
1.1 root 428: [(set (match_operand:DF 0 "general_operand" "=g")
1.1.1.2 root 429: (float:DF (match_operand:QI 1 "general_operand" "g")))]
1.1 root 430: ""
1.1.1.3 root 431: "cvtb%# %1,%0")
1.1.1.2 root 432:
433: ;; Float-to-fix conversion insns.
1.1 root 434:
1.1.1.2 root 435: (define_insn "fix_truncsfqi2"
1.1 root 436: [(set (match_operand:QI 0 "general_operand" "=g")
1.1.1.2 root 437: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 438: ""
1.1.1.2 root 439: "cvtfb %1,%0")
1.1 root 440:
1.1.1.2 root 441: (define_insn "fix_truncsfhi2"
1.1 root 442: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 443: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 444: ""
1.1.1.2 root 445: "cvtfw %1,%0")
1.1 root 446:
1.1.1.2 root 447: (define_insn "fix_truncsfsi2"
1.1 root 448: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 449: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 450: ""
1.1.1.2 root 451: "cvtfl %1,%0")
1.1 root 452:
1.1.1.2 root 453: (define_insn "fix_truncdfqi2"
454: [(set (match_operand:QI 0 "general_operand" "=g")
455: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 456: ""
1.1.1.2 root 457: "cvtdb %1,%0")
1.1 root 458:
1.1.1.2 root 459: (define_insn "fix_truncdfhi2"
1.1 root 460: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 461: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 462: ""
1.1.1.3 root 463: "cvt%#w %1,%0")
1.1 root 464:
1.1.1.2 root 465: (define_insn "fix_truncdfsi2"
1.1 root 466: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 467: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 468: ""
1.1.1.3 root 469: "cvt%#l %1,%0")
1.1 root 470:
471: ;;- All kinds of add instructions.
472:
473: (define_insn "adddf3"
474: [(set (match_operand:DF 0 "general_operand" "=g")
475: (plus:DF (match_operand:DF 1 "general_operand" "gF")
476: (match_operand:DF 2 "general_operand" "gF")))]
477: ""
478: "*
479: {
480: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 481: return \"add%#2 %2,%0\";
1.1 root 482: if (rtx_equal_p (operands[0], operands[2]))
1.1.1.3 root 483: return \"add%#2 %1,%0\";
484: return \"add%#3 %1,%2,%0\";
1.1 root 485: }")
486:
487: (define_insn "addsf3"
488: [(set (match_operand:SF 0 "general_operand" "=g")
489: (plus:SF (match_operand:SF 1 "general_operand" "gF")
490: (match_operand:SF 2 "general_operand" "gF")))]
491: ""
492: "*
493: {
494: if (rtx_equal_p (operands[0], operands[1]))
495: return \"addf2 %2,%0\";
496: if (rtx_equal_p (operands[0], operands[2]))
497: return \"addf2 %1,%0\";
498: return \"addf3 %1,%2,%0\";
499: }")
500:
501: (define_insn "addsi3"
502: [(set (match_operand:SI 0 "general_operand" "=g")
503: (plus:SI (match_operand:SI 1 "general_operand" "g")
504: (match_operand:SI 2 "general_operand" "g")))]
505: ""
506: "*
507: {
508: if (rtx_equal_p (operands[0], operands[1]))
509: {
510: if (operands[2] == const1_rtx)
511: return \"incl %0\";
1.1.1.2 root 512: if (GET_CODE (operands[2]) == CONST_INT
513: && INTVAL (operands[2]) == -1)
1.1 root 514: return \"decl %0\";
515: if (GET_CODE (operands[2]) == CONST_INT
516: && (unsigned) (- INTVAL (operands[2])) < 64)
517: return \"subl2 $%n2,%0\";
518: return \"addl2 %2,%0\";
519: }
520: if (rtx_equal_p (operands[0], operands[2]))
521: return \"addl2 %1,%0\";
522: if (GET_CODE (operands[2]) == CONST_INT
523: && GET_CODE (operands[1]) == REG)
524: {
525: if (push_operand (operands[0], SImode))
526: return \"pushab %c2(%1)\";
527: return \"movab %c2(%1),%0\";
528: }
529: if (GET_CODE (operands[2]) == CONST_INT
530: && (unsigned) (- INTVAL (operands[2])) < 64)
531: return \"subl3 $%n2,%1,%0\";
532: return \"addl3 %1,%2,%0\";
533: }")
534:
535: (define_insn "addhi3"
536: [(set (match_operand:HI 0 "general_operand" "=g")
537: (plus:HI (match_operand:HI 1 "general_operand" "g")
538: (match_operand:HI 2 "general_operand" "g")))]
539: ""
540: "*
541: {
542: if (rtx_equal_p (operands[0], operands[1]))
543: {
544: if (operands[2] == const1_rtx)
545: return \"incw %0\";
546: if (GET_CODE (operands[1]) == CONST_INT
547: && INTVAL (operands[1]) == -1)
548: return \"decw %0\";
549: if (GET_CODE (operands[2]) == CONST_INT
550: && (unsigned) (- INTVAL (operands[2])) < 64)
551: return \"subw2 $%n2,%0\";
552: return \"addw2 %2,%0\";
553: }
554: if (rtx_equal_p (operands[0], operands[2]))
555: return \"addw2 %1,%0\";
556: if (GET_CODE (operands[2]) == CONST_INT
557: && (unsigned) (- INTVAL (operands[2])) < 64)
558: return \"subw3 $%n2,%1,%0\";
559: return \"addw3 %1,%2,%0\";
560: }")
561:
562: (define_insn "addqi3"
563: [(set (match_operand:QI 0 "general_operand" "=g")
564: (plus:QI (match_operand:QI 1 "general_operand" "g")
565: (match_operand:QI 2 "general_operand" "g")))]
566: ""
567: "*
568: {
569: if (rtx_equal_p (operands[0], operands[1]))
570: {
571: if (operands[2] == const1_rtx)
572: return \"incb %0\";
573: if (GET_CODE (operands[1]) == CONST_INT
574: && INTVAL (operands[1]) == -1)
575: return \"decb %0\";
576: if (GET_CODE (operands[2]) == CONST_INT
577: && (unsigned) (- INTVAL (operands[2])) < 64)
578: return \"subb2 $%n2,%0\";
579: return \"addb2 %2,%0\";
580: }
581: if (rtx_equal_p (operands[0], operands[2]))
582: return \"addb2 %1,%0\";
583: if (GET_CODE (operands[2]) == CONST_INT
584: && (unsigned) (- INTVAL (operands[2])) < 64)
585: return \"subb3 $%n2,%1,%0\";
586: return \"addb3 %1,%2,%0\";
587: }")
588:
589: ;;- All kinds of subtract instructions.
590:
591: (define_insn "subdf3"
592: [(set (match_operand:DF 0 "general_operand" "=g")
593: (minus:DF (match_operand:DF 1 "general_operand" "gF")
594: (match_operand:DF 2 "general_operand" "gF")))]
595: ""
596: "*
597: {
598: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 599: return \"sub%#2 %2,%0\";
600: return \"sub%#3 %2,%1,%0\";
1.1 root 601: }")
602:
603: (define_insn "subsf3"
604: [(set (match_operand:SF 0 "general_operand" "=g")
605: (minus:SF (match_operand:SF 1 "general_operand" "gF")
606: (match_operand:SF 2 "general_operand" "gF")))]
607: ""
608: "*
609: {
610: if (rtx_equal_p (operands[0], operands[1]))
611: return \"subf2 %2,%0\";
612: return \"subf3 %2,%1,%0\";
613: }")
614:
615: (define_insn "subsi3"
616: [(set (match_operand:SI 0 "general_operand" "=g")
617: (minus:SI (match_operand:SI 1 "general_operand" "g")
618: (match_operand:SI 2 "general_operand" "g")))]
619: ""
620: "*
621: {
622: if (rtx_equal_p (operands[0], operands[1]))
623: {
624: if (operands[2] == const1_rtx)
625: return \"decl %0\";
626: return \"subl2 %2,%0\";
627: }
628: return \"subl3 %2,%1,%0\";
629: }")
630:
631: (define_insn "subhi3"
632: [(set (match_operand:HI 0 "general_operand" "=g")
633: (minus:HI (match_operand:HI 1 "general_operand" "g")
634: (match_operand:HI 2 "general_operand" "g")))]
635: ""
636: "*
637: {
638: if (rtx_equal_p (operands[0], operands[1]))
639: {
640: if (operands[2] == const1_rtx)
641: return \"decw %0\";
642: return \"subw2 %2,%0\";
643: }
644: return \"subw3 %2,%1,%0\";
645: }")
646:
647: (define_insn "subqi3"
648: [(set (match_operand:QI 0 "general_operand" "=g")
649: (minus:QI (match_operand:QI 1 "general_operand" "g")
650: (match_operand:QI 2 "general_operand" "g")))]
651: ""
652: "*
653: {
654: if (rtx_equal_p (operands[0], operands[1]))
655: {
656: if (operands[2] == const1_rtx)
657: return \"decb %0\";
658: return \"subb2 %2,%0\";
659: }
660: return \"subb3 %2,%1,%0\";
661: }")
662:
663: ;;- Multiply instructions.
664:
665: (define_insn "muldf3"
666: [(set (match_operand:DF 0 "general_operand" "=g")
667: (mult:DF (match_operand:DF 1 "general_operand" "gF")
668: (match_operand:DF 2 "general_operand" "gF")))]
669: ""
670: "*
671: {
672: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 673: return \"mul%#2 %2,%0\";
1.1 root 674: if (rtx_equal_p (operands[0], operands[2]))
1.1.1.3 root 675: return \"mul%#2 %1,%0\";
676: return \"mul%#3 %1,%2,%0\";
1.1 root 677: }")
678:
679: (define_insn "mulsf3"
680: [(set (match_operand:SF 0 "general_operand" "=g")
681: (mult:SF (match_operand:SF 1 "general_operand" "gF")
682: (match_operand:SF 2 "general_operand" "gF")))]
683: ""
684: "*
685: {
686: if (rtx_equal_p (operands[0], operands[1]))
687: return \"mulf2 %2,%0\";
688: if (rtx_equal_p (operands[0], operands[2]))
689: return \"mulf2 %1,%0\";
690: return \"mulf3 %1,%2,%0\";
691: }")
692:
693: (define_insn "mulsi3"
694: [(set (match_operand:SI 0 "general_operand" "=g")
695: (mult:SI (match_operand:SI 1 "general_operand" "g")
696: (match_operand:SI 2 "general_operand" "g")))]
697: ""
698: "*
699: {
700: if (rtx_equal_p (operands[0], operands[1]))
701: return \"mull2 %2,%0\";
702: if (rtx_equal_p (operands[0], operands[2]))
703: return \"mull2 %1,%0\";
704: return \"mull3 %1,%2,%0\";
705: }")
706:
707: (define_insn "mulhi3"
708: [(set (match_operand:HI 0 "general_operand" "=g")
709: (mult:HI (match_operand:HI 1 "general_operand" "g")
710: (match_operand:HI 2 "general_operand" "g")))]
711: ""
712: "*
713: {
714: if (rtx_equal_p (operands[0], operands[1]))
715: return \"mulw2 %2,%0\";
716: if (rtx_equal_p (operands[0], operands[2]))
717: return \"mulw2 %1,%0\";
718: return \"mulw3 %1,%2,%0\";
719: }")
720:
721: (define_insn "mulqi3"
722: [(set (match_operand:QI 0 "general_operand" "=g")
723: (mult:QI (match_operand:QI 1 "general_operand" "g")
724: (match_operand:QI 2 "general_operand" "g")))]
725: ""
726: "*
727: {
728: if (rtx_equal_p (operands[0], operands[1]))
729: return \"mulb2 %2,%0\";
730: if (rtx_equal_p (operands[0], operands[2]))
731: return \"mulb2 %1,%0\";
732: return \"mulb3 %1,%2,%0\";
733: }")
734:
735: ;;- Divide instructions.
736:
737: (define_insn "divdf3"
738: [(set (match_operand:DF 0 "general_operand" "=g")
739: (div:DF (match_operand:DF 1 "general_operand" "gF")
740: (match_operand:DF 2 "general_operand" "gF")))]
741: ""
742: "*
743: {
744: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 745: return \"div%#2 %2,%0\";
746: return \"div%#3 %2,%1,%0\";
1.1 root 747: }")
748:
749: (define_insn "divsf3"
750: [(set (match_operand:SF 0 "general_operand" "=g")
751: (div:SF (match_operand:SF 1 "general_operand" "gF")
752: (match_operand:SF 2 "general_operand" "gF")))]
753: ""
754: "*
755: {
756: if (rtx_equal_p (operands[0], operands[1]))
757: return \"divf2 %2,%0\";
758: return \"divf3 %2,%1,%0\";
759: }")
760:
761: (define_insn "divsi3"
762: [(set (match_operand:SI 0 "general_operand" "=g")
763: (div:SI (match_operand:SI 1 "general_operand" "g")
764: (match_operand:SI 2 "general_operand" "g")))]
765: ""
766: "*
767: {
768: if (rtx_equal_p (operands[0], operands[1]))
769: return \"divl2 %2,%0\";
770: return \"divl3 %2,%1,%0\";
771: }")
772:
773: (define_insn "divhi3"
774: [(set (match_operand:HI 0 "general_operand" "=g")
775: (div:HI (match_operand:HI 1 "general_operand" "g")
776: (match_operand:HI 2 "general_operand" "g")))]
777: ""
778: "*
779: {
780: if (rtx_equal_p (operands[0], operands[1]))
781: return \"divw2 %2,%0\";
782: return \"divw3 %2,%1,%0\";
783: }")
784:
785: (define_insn "divqi3"
786: [(set (match_operand:QI 0 "general_operand" "=g")
787: (div:QI (match_operand:QI 1 "general_operand" "g")
788: (match_operand:QI 2 "general_operand" "g")))]
789: ""
790: "*
791: {
792: if (rtx_equal_p (operands[0], operands[1]))
793: return \"divb2 %2,%0\";
794: return \"divb3 %2,%1,%0\";
795: }")
796:
797: ;This is left out because it is very slow;
798: ;we are better off programming around the "lack" of this insn.
799: ;(define_insn "divmoddisi4"
800: ; [(set (match_operand:SI 0 "general_operand" "=g")
801: ; (div:SI (match_operand:DI 1 "general_operand" "g")
802: ; (match_operand:SI 2 "general_operand" "g")))
803: ; (set (match_operand:SI 3 "general_operand" "=g")
804: ; (mod:SI (match_operand:DI 1 "general_operand" "g")
805: ; (match_operand:SI 2 "general_operand" "g")))]
806: ; ""
807: ; "ediv %2,%1,%0,%3")
808:
809: (define_insn "andcbsi3"
810: [(set (match_operand:SI 0 "general_operand" "=g")
811: (and:SI (match_operand:SI 1 "general_operand" "g")
812: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
813: ""
814: "*
815: {
816: if (rtx_equal_p (operands[0], operands[1]))
817: return \"bicl2 %2,%0\";
818: return \"bicl3 %2,%1,%0\";
819: }")
820:
821: (define_insn "andcbhi3"
822: [(set (match_operand:HI 0 "general_operand" "=g")
823: (and:HI (match_operand:HI 1 "general_operand" "g")
824: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
825: ""
826: "*
827: {
828: if (rtx_equal_p (operands[0], operands[1]))
829: return \"bicw2 %2,%0\";
830: return \"bicw3 %2,%1,%0\";
831: }")
832:
833: (define_insn "andcbqi3"
834: [(set (match_operand:QI 0 "general_operand" "=g")
835: (and:QI (match_operand:QI 1 "general_operand" "g")
836: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
837: ""
838: "*
839: {
840: if (rtx_equal_p (operands[0], operands[1]))
841: return \"bicb2 %2,%0\";
842: return \"bicb3 %2,%1,%0\";
843: }")
844:
845: ;; The following are needed because constant propagation can
846: ;; create them starting from the bic insn patterns above.
847:
848: (define_insn ""
849: [(set (match_operand:SI 0 "general_operand" "=g")
850: (and:SI (match_operand:SI 1 "general_operand" "g")
851: (match_operand:SI 2 "general_operand" "g")))]
852: "GET_CODE (operands[2]) == CONST_INT"
853: "*
854: { operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
855: if (rtx_equal_p (operands[1], operands[0]))
856: return \"bicl2 %2,%0\";
857: return \"bicl3 %2,%1,%0\";
858: }")
859:
860: (define_insn ""
861: [(set (match_operand:HI 0 "general_operand" "=g")
862: (and:HI (match_operand:HI 1 "general_operand" "g")
863: (match_operand:HI 2 "general_operand" "g")))]
864: "GET_CODE (operands[2]) == CONST_INT"
865: "*
866: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xffff & ~INTVAL (operands[2]));
867: if (rtx_equal_p (operands[1], operands[0]))
868: return \"bicw2 %2,%0\";
869: return \"bicw3 %2,%1,%0\";
870: }")
871:
872: (define_insn ""
873: [(set (match_operand:QI 0 "general_operand" "=g")
874: (and:QI (match_operand:QI 1 "general_operand" "g")
875: (match_operand:QI 2 "general_operand" "g")))]
876: "GET_CODE (operands[2]) == CONST_INT"
877: "*
878: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xff & ~INTVAL (operands[2]));
879: if (rtx_equal_p (operands[1], operands[0]))
880: return \"bicb2 %2,%0\";
881: return \"bicb3 %2,%1,%0\";
882: }")
883:
884: ;;- Bit set instructions.
885:
886: (define_insn "iorsi3"
887: [(set (match_operand:SI 0 "general_operand" "=g")
888: (ior:SI (match_operand:SI 1 "general_operand" "g")
889: (match_operand:SI 2 "general_operand" "g")))]
890: ""
891: "*
892: {
893: if (rtx_equal_p (operands[0], operands[1]))
894: return \"bisl2 %2,%0\";
895: if (rtx_equal_p (operands[0], operands[2]))
896: return \"bisl2 %1,%0\";
897: return \"bisl3 %2,%1,%0\";
898: }")
899:
900: (define_insn "iorhi3"
901: [(set (match_operand:HI 0 "general_operand" "=g")
902: (ior:HI (match_operand:HI 1 "general_operand" "g")
903: (match_operand:HI 2 "general_operand" "g")))]
904: ""
905: "*
906: {
907: if (rtx_equal_p (operands[0], operands[1]))
908: return \"bisw2 %2,%0\";
909: if (rtx_equal_p (operands[0], operands[2]))
910: return \"bisw2 %1,%0\";
911: return \"bisw3 %2,%1,%0\";
912: }")
913:
914: (define_insn "iorqi3"
915: [(set (match_operand:QI 0 "general_operand" "=g")
916: (ior:QI (match_operand:QI 1 "general_operand" "g")
917: (match_operand:QI 2 "general_operand" "g")))]
918: ""
919: "*
920: {
921: if (rtx_equal_p (operands[0], operands[1]))
922: return \"bisb2 %2,%0\";
923: if (rtx_equal_p (operands[0], operands[2]))
924: return \"bisb2 %1,%0\";
925: return \"bisb3 %2,%1,%0\";
926: }")
927:
928: ;;- xor instructions.
929:
930: (define_insn "xorsi3"
931: [(set (match_operand:SI 0 "general_operand" "=g")
932: (xor:SI (match_operand:SI 1 "general_operand" "g")
933: (match_operand:SI 2 "general_operand" "g")))]
934: ""
935: "*
936: {
937: if (rtx_equal_p (operands[0], operands[1]))
938: return \"xorl2 %2,%0\";
939: if (rtx_equal_p (operands[0], operands[2]))
940: return \"xorl2 %1,%0\";
941: return \"xorl3 %2,%1,%0\";
942: }")
943:
944: (define_insn "xorhi3"
945: [(set (match_operand:HI 0 "general_operand" "=g")
946: (xor:HI (match_operand:HI 1 "general_operand" "g")
947: (match_operand:HI 2 "general_operand" "g")))]
948: ""
949: "*
950: {
951: if (rtx_equal_p (operands[0], operands[1]))
952: return \"xorw2 %2,%0\";
953: if (rtx_equal_p (operands[0], operands[2]))
954: return \"xorw2 %1,%0\";
955: return \"xorw3 %2,%1,%0\";
956: }")
957:
958: (define_insn "xorqi3"
959: [(set (match_operand:QI 0 "general_operand" "=g")
960: (xor:QI (match_operand:QI 1 "general_operand" "g")
961: (match_operand:QI 2 "general_operand" "g")))]
962: ""
963: "*
964: {
965: if (rtx_equal_p (operands[0], operands[1]))
966: return \"xorb2 %2,%0\";
967: if (rtx_equal_p (operands[0], operands[2]))
968: return \"xorb2 %1,%0\";
969: return \"xorb3 %2,%1,%0\";
970: }")
971:
972: (define_insn "negdf2"
973: [(set (match_operand:DF 0 "general_operand" "=g")
974: (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
975: ""
1.1.1.3 root 976: "mneg%# %1,%0")
1.1 root 977:
978: (define_insn "negsf2"
979: [(set (match_operand:SF 0 "general_operand" "=g")
980: (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
981: ""
982: "mnegf %1,%0")
983:
984: (define_insn "negsi2"
985: [(set (match_operand:SI 0 "general_operand" "=g")
986: (neg:SI (match_operand:SI 1 "general_operand" "g")))]
987: ""
988: "mnegl %1,%0")
989:
990: (define_insn "neghi2"
991: [(set (match_operand:HI 0 "general_operand" "=g")
992: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
993: ""
994: "mnegw %1,%0")
995:
996: (define_insn "negqi2"
997: [(set (match_operand:QI 0 "general_operand" "=g")
998: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
999: ""
1000: "mnegb %1,%0")
1001:
1002: (define_insn "one_cmplsi2"
1003: [(set (match_operand:SI 0 "general_operand" "=g")
1004: (not:SI (match_operand:SI 1 "general_operand" "g")))]
1005: ""
1006: "mcoml %1,%0")
1007:
1008: (define_insn "one_cmplhi2"
1009: [(set (match_operand:HI 0 "general_operand" "=g")
1010: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1011: ""
1012: "mcomw %1,%0")
1013:
1014: (define_insn "one_cmplqi2"
1015: [(set (match_operand:QI 0 "general_operand" "=g")
1016: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1017: ""
1018: "mcomb %1,%0")
1019:
1020: (define_insn "ashlsi3"
1021: [(set (match_operand:SI 0 "general_operand" "=g")
1022: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1023: (match_operand:QI 2 "general_operand" "g")))]
1024: ""
1.1.1.2 root 1025: "*
1026: {
1027: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1028: return \"addl2 %0,%0\";
1029: return \"ashl %2,%1,%0\";
1030: }")
1.1 root 1031:
1032: (define_insn "ashldi3"
1033: [(set (match_operand:DI 0 "general_operand" "=g")
1034: (ashift:DI (match_operand:DI 1 "general_operand" "g")
1035: (match_operand:QI 2 "general_operand" "g")))]
1036: ""
1037: "ashq %2,%1,%0")
1038:
1039: (define_insn "rotlsi3"
1040: [(set (match_operand:SI 0 "general_operand" "=g")
1041: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1042: (match_operand:QI 2 "general_operand" "g")))]
1043: ""
1044: "rotl %2,%1,%0")
1045:
1046: (define_insn "rotldi3"
1047: [(set (match_operand:DI 0 "general_operand" "=g")
1048: (rotate:DI (match_operand:DI 1 "general_operand" "g")
1049: (match_operand:QI 2 "general_operand" "g")))]
1050: ""
1051: "rotq %2,%1,%0")
1052:
1.1.1.2 root 1053: ;This insn is probably slower than a multiply and an add.
1054: ;(define_insn ""
1055: ; [(set (match_operand:SI 0 "general_operand" "=g")
1056: ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1057: ; (match_operand:SI 2 "general_operand" "g"))
1058: ; (match_operand:SI 3 "general_operand" "g")))]
1059: ; ""
1060: ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1.1.1.4 root 1061:
1062: ;; Special cases of bit-field insns which we should
1063: ;; recognize in preference to the general case.
1064: ;; These handle aligned 8-bit and 16-bit fields,
1065: ;; which can usually be done with move instructions.
1066:
1067: (define_insn ""
1068: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro")
1069: (match_operand:SI 1 "immediate_operand" "i")
1070: (match_operand:SI 2 "immediate_operand" "i"))
1071: (match_operand:SI 3 "general_operand" "g"))]
1072: "GET_CODE (operands[1]) == CONST_INT
1073: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1074: && GET_CODE (operands[2]) == CONST_INT
1075: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1076: && (GET_CODE (operands[0]) == REG
1077: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1078: "*
1079: {
1080: if (REG_P (operands[0]))
1081: {
1082: if (INTVAL (operands[2]) != 0)
1083: return \"insv %3,%2,%1,%0\";
1084: }
1085: else
1086: operands[0]
1087: = adj_offsetable_operand (operands[0], INTVAL (operands[2]) / 8);
1088:
1089: if (INTVAL (operands[1]) == 8)
1090: return \"movb %3,%0\";
1091: return \"movw %3,%0\";
1092: }")
1093:
1094: (define_insn ""
1095: [(set (match_operand:SI 0 "general_operand" "=&g")
1096: (zero_extract:SI (match_operand:SI 1 "general_operand" "ro")
1097: (match_operand:SI 2 "immediate_operand" "i")
1098: (match_operand:SI 3 "immediate_operand" "i")))]
1099: "GET_CODE (operands[2]) == CONST_INT
1100: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1101: && GET_CODE (operands[3]) == CONST_INT
1102: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1103: && (GET_CODE (operands[1]) == REG
1104: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1105: "*
1106: {
1107: if (REG_P (operands[1]))
1108: {
1109: if (INTVAL (operands[3]) != 0)
1110: return \"extzv %3,%2,%1,%0\";
1111: }
1112: else
1113: operands[1]
1114: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8);
1115:
1116: if (INTVAL (operands[2]) == 8)
1117: return \"movzbl %1,%0\";
1118: return \"movzwl %1,%0\";
1119: }")
1120:
1121: (define_insn ""
1122: [(set (match_operand:SI 0 "general_operand" "=g")
1123: (sign_extract:SI (match_operand:SI 1 "general_operand" "ro")
1124: (match_operand:SI 2 "immediate_operand" "i")
1125: (match_operand:SI 3 "immediate_operand" "i")))]
1126: "GET_CODE (operands[2]) == CONST_INT
1127: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1128: && GET_CODE (operands[3]) == CONST_INT
1129: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1130: && (GET_CODE (operands[1]) == REG
1131: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1132: "*
1133: {
1134: if (REG_P (operands[1]))
1135: {
1136: if (INTVAL (operands[3]) != 0)
1137: return \"extv %3,%2,%1,%0\";
1138: }
1139: else
1140: operands[1]
1141: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8);
1142:
1143: if (INTVAL (operands[2]) == 8)
1144: return \"cvtbl %1,%0\";
1145: return \"cvtwl %1,%0\";
1146: }")
1147:
1148: ;; Register-only SImode cases of bit-field insns.
1.1 root 1149:
1150: (define_insn ""
1151: [(set (cc0)
1152: (minus
1.1.1.4 root 1153: (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1.1 root 1154: (match_operand:SI 1 "general_operand" "g")
1155: (match_operand:SI 2 "general_operand" "g"))
1156: (match_operand:SI 3 "general_operand" "g")))]
1157: ""
1158: "cmpv %2,%1,%0,%3")
1159:
1160: (define_insn ""
1161: [(set (cc0)
1162: (minus
1.1.1.4 root 1163: (zero_extract:SI (match_operand:SI 0 "general_operand" "r")
1.1 root 1164: (match_operand:SI 1 "general_operand" "g")
1165: (match_operand:SI 2 "general_operand" "g"))
1166: (match_operand:SI 3 "general_operand" "g")))]
1167: ""
1168: "cmpzv %2,%1,%0,%3")
1169:
1.1.1.4 root 1170: (define_insn ""
1.1 root 1171: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1172: (sign_extract:SI (match_operand:SI 1 "general_operand" "r")
1.1 root 1173: (match_operand:SI 2 "general_operand" "g")
1174: (match_operand:SI 3 "general_operand" "g")))]
1175: ""
1176: "extv %3,%2,%1,%0")
1177:
1.1.1.4 root 1178: (define_insn ""
1.1 root 1179: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1180: (zero_extract:SI (match_operand:SI 1 "general_operand" "r")
1.1 root 1181: (match_operand:SI 2 "general_operand" "g")
1182: (match_operand:SI 3 "general_operand" "g")))]
1183: ""
1184: "extzv %3,%2,%1,%0")
1185:
1.1.1.4 root 1186: ;; Non-register cases.
1187: ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1188: ;; don't match these (and therefore match the cases above instead).
1189:
1.1 root 1190: (define_insn ""
1.1.1.4 root 1191: [(set (cc0)
1192: (minus
1193: (sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1194: (match_operand:SI 1 "general_operand" "g")
1195: (match_operand:SI 2 "general_operand" "g"))
1196: (match_operand:SI 3 "general_operand" "g")))]
1197: ""
1198: "cmpv %2,%1,%0,%3")
1199:
1200: (define_insn ""
1201: [(set (cc0)
1202: (minus
1203: (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1204: (match_operand:SI 1 "general_operand" "g")
1205: (match_operand:SI 2 "general_operand" "g"))
1206: (match_operand:SI 3 "general_operand" "g")))]
1207: ""
1208: "cmpzv %2,%1,%0,%3")
1209:
1210: (define_insn "extv"
1.1 root 1211: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1212: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1.1 root 1213: (match_operand:SI 2 "general_operand" "g")
1214: (match_operand:SI 3 "general_operand" "g")))]
1215: ""
1216: "extv %3,%2,%1,%0")
1217:
1.1.1.4 root 1218: (define_insn "extzv"
1.1 root 1219: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1220: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1.1 root 1221: (match_operand:SI 2 "general_operand" "g")
1222: (match_operand:SI 3 "general_operand" "g")))]
1223: ""
1224: "extzv %3,%2,%1,%0")
1225:
1226: (define_insn "insv"
1.1.1.2 root 1227: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1.1 root 1228: (match_operand:SI 1 "general_operand" "g")
1229: (match_operand:SI 2 "general_operand" "g"))
1230: (match_operand:SI 3 "general_operand" "g"))]
1231: ""
1232: "insv %3,%2,%1,%0")
1233:
1234: (define_insn ""
1.1.1.2 root 1235: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1.1 root 1236: (match_operand:SI 1 "general_operand" "g")
1237: (match_operand:SI 2 "general_operand" "g"))
1238: (match_operand:SI 3 "general_operand" "g"))]
1239: ""
1240: "insv %3,%2,%1,%0")
1241:
1242: (define_insn "jump"
1243: [(set (pc)
1244: (label_ref (match_operand 0 "" "")))]
1245: ""
1246: "jbr %l0")
1247:
1248: (define_insn "beq"
1249: [(set (pc)
1250: (if_then_else (eq (cc0)
1251: (const_int 0))
1252: (label_ref (match_operand 0 "" ""))
1253: (pc)))]
1254: ""
1255: "jeql %l0")
1256:
1257: (define_insn "bne"
1258: [(set (pc)
1259: (if_then_else (ne (cc0)
1260: (const_int 0))
1261: (label_ref (match_operand 0 "" ""))
1262: (pc)))]
1263: ""
1264: "jneq %l0")
1265:
1266: (define_insn "bgt"
1267: [(set (pc)
1268: (if_then_else (gt (cc0)
1269: (const_int 0))
1270: (label_ref (match_operand 0 "" ""))
1271: (pc)))]
1272: ""
1273: "jgtr %l0")
1274:
1275: (define_insn "bgtu"
1276: [(set (pc)
1277: (if_then_else (gtu (cc0)
1278: (const_int 0))
1279: (label_ref (match_operand 0 "" ""))
1280: (pc)))]
1281: ""
1282: "jgtru %l0")
1283:
1284: (define_insn "blt"
1285: [(set (pc)
1286: (if_then_else (lt (cc0)
1287: (const_int 0))
1288: (label_ref (match_operand 0 "" ""))
1289: (pc)))]
1290: ""
1291: "jlss %l0")
1292:
1293: (define_insn "bltu"
1294: [(set (pc)
1295: (if_then_else (ltu (cc0)
1296: (const_int 0))
1297: (label_ref (match_operand 0 "" ""))
1298: (pc)))]
1299: ""
1300: "jlssu %l0")
1301:
1302: (define_insn "bge"
1303: [(set (pc)
1304: (if_then_else (ge (cc0)
1305: (const_int 0))
1306: (label_ref (match_operand 0 "" ""))
1307: (pc)))]
1308: ""
1309: "jgeq %l0")
1310:
1311: (define_insn "bgeu"
1312: [(set (pc)
1313: (if_then_else (geu (cc0)
1314: (const_int 0))
1315: (label_ref (match_operand 0 "" ""))
1316: (pc)))]
1317: ""
1318: "jgequ %l0")
1319:
1320: (define_insn "ble"
1321: [(set (pc)
1322: (if_then_else (le (cc0)
1323: (const_int 0))
1324: (label_ref (match_operand 0 "" ""))
1325: (pc)))]
1326: ""
1327: "jleq %l0")
1328:
1329: (define_insn "bleu"
1330: [(set (pc)
1331: (if_then_else (leu (cc0)
1332: (const_int 0))
1333: (label_ref (match_operand 0 "" ""))
1334: (pc)))]
1335: ""
1336: "jlequ %l0")
1337:
1338: (define_insn ""
1339: [(set (pc)
1340: (if_then_else (eq (cc0)
1341: (const_int 0))
1342: (pc)
1343: (label_ref (match_operand 0 "" ""))))]
1344: ""
1345: "jneq %l0")
1346:
1347: (define_insn ""
1348: [(set (pc)
1349: (if_then_else (ne (cc0)
1350: (const_int 0))
1351: (pc)
1352: (label_ref (match_operand 0 "" ""))))]
1353: ""
1354: "jeql %l0")
1355:
1356: (define_insn ""
1357: [(set (pc)
1358: (if_then_else (gt (cc0)
1359: (const_int 0))
1360: (pc)
1361: (label_ref (match_operand 0 "" ""))))]
1362: ""
1363: "jleq %l0")
1364:
1365: (define_insn ""
1366: [(set (pc)
1367: (if_then_else (gtu (cc0)
1368: (const_int 0))
1369: (pc)
1370: (label_ref (match_operand 0 "" ""))))]
1371: ""
1372: "jlequ %l0")
1373:
1374: (define_insn ""
1375: [(set (pc)
1376: (if_then_else (lt (cc0)
1377: (const_int 0))
1378: (pc)
1379: (label_ref (match_operand 0 "" ""))))]
1380: ""
1381: "jgeq %l0")
1382:
1383: (define_insn ""
1384: [(set (pc)
1385: (if_then_else (ltu (cc0)
1386: (const_int 0))
1387: (pc)
1388: (label_ref (match_operand 0 "" ""))))]
1389: ""
1390: "jgequ %l0")
1391:
1392: (define_insn ""
1393: [(set (pc)
1394: (if_then_else (ge (cc0)
1395: (const_int 0))
1396: (pc)
1397: (label_ref (match_operand 0 "" ""))))]
1398: ""
1399: "jlss %l0")
1400:
1401: (define_insn ""
1402: [(set (pc)
1403: (if_then_else (geu (cc0)
1404: (const_int 0))
1405: (pc)
1406: (label_ref (match_operand 0 "" ""))))]
1407: ""
1408: "jlssu %l0")
1409:
1410: (define_insn ""
1411: [(set (pc)
1412: (if_then_else (le (cc0)
1413: (const_int 0))
1414: (pc)
1415: (label_ref (match_operand 0 "" ""))))]
1416: ""
1417: "jgtr %l0")
1418:
1419: (define_insn ""
1420: [(set (pc)
1421: (if_then_else (leu (cc0)
1422: (const_int 0))
1423: (pc)
1424: (label_ref (match_operand 0 "" ""))))]
1425: ""
1426: "jgtru %l0")
1427:
1428: ;; Recognize jbs and jbc instructions.
1429:
1430: (define_insn ""
1431: [(set (pc)
1432: (if_then_else
1433: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1434: (const_int 1)
1435: (match_operand:SI 1 "general_operand" "g"))
1436: (const_int 0))
1437: (label_ref (match_operand 2 "" ""))
1438: (pc)))]
1439: ""
1440: "jbs %1,%0,%l2")
1441:
1442: (define_insn ""
1443: [(set (pc)
1444: (if_then_else
1445: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1446: (const_int 1)
1447: (match_operand:SI 1 "general_operand" "g"))
1448: (const_int 0))
1449: (label_ref (match_operand 2 "" ""))
1450: (pc)))]
1451: ""
1452: "jbc %1,%0,%l2")
1453:
1454: (define_insn ""
1455: [(set (pc)
1456: (if_then_else
1457: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1458: (const_int 1)
1459: (match_operand:SI 1 "general_operand" "g"))
1460: (const_int 0))
1461: (pc)
1462: (label_ref (match_operand 2 "" ""))))]
1463: ""
1464: "jbc %1,%0,%l2")
1465:
1466: (define_insn ""
1467: [(set (pc)
1468: (if_then_else
1469: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1470: (const_int 1)
1471: (match_operand:SI 1 "general_operand" "g"))
1472: (const_int 0))
1473: (pc)
1474: (label_ref (match_operand 2 "" ""))))]
1475: ""
1476: "jbs %1,%0,%l2")
1477:
1478: (define_insn ""
1479: [(set (pc)
1480: (if_then_else
1481: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1482: (const_int 1)
1483: (match_operand:SI 1 "general_operand" "g"))
1484: (const_int 0))
1485: (label_ref (match_operand 2 "" ""))
1486: (pc)))]
1.1.1.2 root 1487: "GET_CODE (operands[0]) != MEM
1488: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1489: "jbs %1,%0,%l2")
1490:
1491: (define_insn ""
1492: [(set (pc)
1493: (if_then_else
1494: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1495: (const_int 1)
1496: (match_operand:SI 1 "general_operand" "g"))
1497: (const_int 0))
1498: (label_ref (match_operand 2 "" ""))
1499: (pc)))]
1.1.1.2 root 1500: "GET_CODE (operands[0]) != MEM
1501: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1502: "jbc %1,%0,%l2")
1503:
1504: (define_insn ""
1505: [(set (pc)
1506: (if_then_else
1.1.1.2 root 1507: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1508: (match_operand:SI 1 "general_operand" "g"))
1509: (const_int 0))
1510: (pc)
1511: (label_ref (match_operand 2 "" ""))))]
1512: "GET_CODE (operands[1]) == CONST_INT
1513: && exact_log2 (INTVAL (operands[1])) >= 0
1514: && (GET_CODE (operands[0]) != MEM
1515: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1516: "*
1517: {
1518: operands[1]
1519: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1520: return \"jbs %1,%0,%l2\";
1521: }")
1522:
1523: (define_insn ""
1524: [(set (pc)
1525: (if_then_else
1526: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1527: (match_operand:SI 1 "general_operand" "g"))
1528: (const_int 0))
1529: (label_ref (match_operand 2 "" ""))
1530: (pc)))]
1531: "GET_CODE (operands[1]) == CONST_INT
1532: && exact_log2 (INTVAL (operands[1])) >= 0
1533: && (GET_CODE (operands[0]) != MEM
1534: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1535: "*
1536: {
1537: operands[1]
1538: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1539: return \"jbc %1,%0,%l2\";
1540: }")
1541:
1542: (define_insn ""
1543: [(set (pc)
1544: (if_then_else
1545: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1546: (match_operand:SI 1 "general_operand" "g"))
1547: (const_int 0))
1548: (pc)
1549: (label_ref (match_operand 2 "" ""))))]
1550: "GET_CODE (operands[1]) == CONST_INT
1551: && exact_log2 (INTVAL (operands[1])) >= 0
1552: && (GET_CODE (operands[0]) != MEM
1553: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1554: "*
1555: {
1556: operands[1]
1557: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1558: return \"jbc %1,%0,%l2\";
1559: }")
1560:
1561: (define_insn ""
1562: [(set (pc)
1563: (if_then_else
1564: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1565: (match_operand:SI 1 "general_operand" "g"))
1566: (const_int 0))
1567: (label_ref (match_operand 2 "" ""))
1568: (pc)))]
1569: "GET_CODE (operands[1]) == CONST_INT
1570: && exact_log2 (INTVAL (operands[1])) >= 0
1571: && (GET_CODE (operands[0]) != MEM
1572: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1573: "*
1574: {
1575: operands[1]
1576: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1577: return \"jbs %1,%0,%l2\";
1578: }")
1579:
1580: (define_insn ""
1581: [(set (pc)
1582: (if_then_else
1.1 root 1583: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1584: (const_int 1)
1585: (match_operand:SI 1 "general_operand" "g"))
1586: (const_int 0))
1587: (pc)
1588: (label_ref (match_operand 2 "" ""))))]
1.1.1.2 root 1589: "GET_CODE (operands[0]) != MEM
1590: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1591: "jbc %1,%0,%l2")
1592:
1593: (define_insn ""
1594: [(set (pc)
1595: (if_then_else
1596: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1597: (const_int 1)
1598: (match_operand:SI 1 "general_operand" "g"))
1599: (const_int 0))
1600: (pc)
1601: (label_ref (match_operand 2 "" ""))))]
1.1.1.2 root 1602: "GET_CODE (operands[0]) != MEM
1603: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1604: "jbs %1,%0,%l2")
1605:
1606: (define_insn ""
1607: [(set (pc)
1608: (if_then_else
1609: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1610: (const_int 1))
1611: (const_int 0))
1612: (label_ref (match_operand 1 "" ""))
1613: (pc)))]
1.1.1.2 root 1614: "GET_CODE (operands[0]) != MEM
1615: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1616: "jlbs %0,%l1")
1617:
1618: (define_insn ""
1619: [(set (pc)
1620: (if_then_else
1621: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1622: (const_int 1))
1623: (const_int 0))
1624: (label_ref (match_operand 1 "" ""))
1625: (pc)))]
1.1.1.2 root 1626: "GET_CODE (operands[0]) != MEM
1627: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1628: "jlbc %0,%l1")
1629:
1630: (define_insn ""
1631: [(set (pc)
1632: (if_then_else
1633: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1634: (const_int 1))
1635: (const_int 0))
1636: (pc)
1637: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1638: "GET_CODE (operands[0]) != MEM
1639: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1640: "jlbc %0,%l1")
1641:
1642: (define_insn ""
1643: [(set (pc)
1644: (if_then_else
1645: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1646: (const_int 1))
1647: (const_int 0))
1648: (pc)
1649: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1650: "GET_CODE (operands[0]) != MEM
1651: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1652: "jlbs %0,%l1")
1653:
1654: ;; These four entries allow a jlbc or jlbs to be made
1655: ;; by combination with a bic.
1656: (define_insn ""
1657: [(set (pc)
1658: (if_then_else
1659: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1660: (not:SI (const_int -2)))
1661: (const_int 0))
1662: (label_ref (match_operand 1 "" ""))
1663: (pc)))]
1.1.1.2 root 1664: "GET_CODE (operands[0]) != MEM
1665: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1666: "jlbs %0,%l1")
1667:
1668: (define_insn ""
1669: [(set (pc)
1670: (if_then_else
1671: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1672: (not:SI (const_int -2)))
1673: (const_int 0))
1674: (label_ref (match_operand 1 "" ""))
1675: (pc)))]
1.1.1.2 root 1676: "GET_CODE (operands[0]) != MEM
1677: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1678: "jlbc %0,%l1")
1679:
1680: (define_insn ""
1681: [(set (pc)
1682: (if_then_else
1683: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1684: (not:SI (const_int -2)))
1685: (const_int 0))
1686: (pc)
1687: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1688: "GET_CODE (operands[0]) != MEM
1689: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1690: "jlbc %0,%l1")
1691:
1692: (define_insn ""
1693: [(set (pc)
1694: (if_then_else
1695: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1696: (not:SI (const_int -2)))
1697: (const_int 0))
1698: (pc)
1699: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1700: "GET_CODE (operands[0]) != MEM
1701: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1702: "jlbs %0,%l1")
1703:
1704: ;; Subtract-and-jump and Add-and-jump insns.
1705: ;; These are not used when output is for the Unix assembler
1706: ;; because it does not know how to modify them to reach far.
1707:
1708: ;; Normal sob insns.
1709:
1710: (define_insn ""
1711: [(set (pc)
1712: (if_then_else
1713: (gt (minus:SI (match_operand:SI 0 "general_operand" "+g")
1714: (const_int 1))
1715: (const_int 0))
1716: (label_ref (match_operand 1 "" ""))
1717: (pc)))
1718: (set (match_dup 0)
1.1.1.2 root 1719: (plus:SI (match_dup 0)
1720: (const_int -1)))]
1.1 root 1721: "!TARGET_UNIX_ASM"
1722: "jsobgtr %0,%l1")
1723:
1724: (define_insn ""
1725: [(set (pc)
1726: (if_then_else
1727: (ge (minus:SI (match_operand:SI 0 "general_operand" "+g")
1728: (const_int 1))
1729: (const_int 0))
1730: (label_ref (match_operand 1 "" ""))
1731: (pc)))
1732: (set (match_dup 0)
1.1.1.2 root 1733: (plus:SI (match_dup 0)
1734: (const_int -1)))]
1.1 root 1735: "!TARGET_UNIX_ASM"
1736: "jsobgeq %0,%l1")
1737:
1738: ;; Reversed sob insns.
1739:
1740: (define_insn ""
1741: [(set (pc)
1742: (if_then_else
1743: (le (minus:SI (match_operand:SI 0 "general_operand" "+g")
1744: (const_int 1))
1745: (const_int 0))
1746: (pc)
1747: (label_ref (match_operand 1 "" ""))))
1748: (set (match_dup 0)
1.1.1.2 root 1749: (plus:SI (match_dup 0)
1750: (const_int -1)))]
1.1 root 1751: "!TARGET_UNIX_ASM"
1752: "jsobgtr %0,%l1")
1753:
1754: (define_insn ""
1755: [(set (pc)
1756: (if_then_else
1757: (lt (minus:SI (match_operand:SI 0 "general_operand" "+g")
1758: (const_int 1))
1759: (const_int 0))
1760: (pc)
1761: (label_ref (match_operand 1 "" ""))))
1762: (set (match_dup 0)
1.1.1.2 root 1763: (plus:SI (match_dup 0)
1764: (const_int -1)))]
1.1 root 1765: "!TARGET_UNIX_ASM"
1766: "jsobgeq %0,%l1")
1767:
1768: ;; Normal aob insns.
1769: (define_insn ""
1770: [(set (pc)
1771: (if_then_else
1772: (lt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1773: (const_int 1))
1774: (match_operand:SI 1 "general_operand" "g"))
1775: (const_int 0))
1776: (label_ref (match_operand 2 "" ""))
1777: (pc)))
1778: (set (match_dup 0)
1779: (plus:SI (match_dup 0)
1780: (const_int 1)))]
1781: "!TARGET_UNIX_ASM"
1782: "jaoblss %1,%0,%l2")
1783:
1784: (define_insn ""
1785: [(set (pc)
1786: (if_then_else
1787: (le (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1788: (const_int 1))
1789: (match_operand:SI 1 "general_operand" "g"))
1790: (const_int 0))
1791: (label_ref (match_operand 2 "" ""))
1792: (pc)))
1793: (set (match_dup 0)
1794: (plus:SI (match_dup 0)
1795: (const_int 1)))]
1796: "!TARGET_UNIX_ASM"
1797: "jaobleq %1,%0,%l2")
1798:
1799: ;; Reverse aob insns.
1800: (define_insn ""
1801: [(set (pc)
1802: (if_then_else
1803: (ge (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1804: (const_int 1))
1805: (match_operand:SI 1 "general_operand" "g"))
1806: (const_int 0))
1807: (pc)
1808: (label_ref (match_operand 2 "" ""))))
1809: (set (match_dup 0)
1810: (plus:SI (match_dup 0)
1811: (const_int 1)))]
1812: "!TARGET_UNIX_ASM"
1813: "jaoblss %1,%0,%l2")
1814:
1815: (define_insn ""
1816: [(set (pc)
1817: (if_then_else
1818: (gt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1819: (const_int 1))
1820: (match_operand:SI 1 "general_operand" "g"))
1821: (const_int 0))
1822: (pc)
1823: (label_ref (match_operand 2 "" ""))))
1824: (set (match_dup 0)
1825: (plus:SI (match_dup 0)
1826: (const_int 1)))]
1827: "!TARGET_UNIX_ASM"
1828: "jaobleq %1,%0,%l2")
1.1.1.5 root 1829:
1830: ;; Something like a sob insn, but compares against -1.
1831: ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1832:
1833: (define_insn ""
1834: [(set (pc)
1835: (if_then_else
1836: (ne (minus (plus:SI (match_operand:SI 0 "general_operand" "g")
1837: (const_int -1))
1838: (const_int -1))
1839: (const_int 0))
1840: (label_ref (match_operand 1 "" ""))
1841: (pc)))
1842: (set (match_dup 0)
1843: (plus:SI (match_dup 0)
1844: (const_int -1)))]
1845: ""
1846: "decl %0\;jgequ %l1")
1.1 root 1847:
1.1.1.2 root 1848: ;; Note that operand 1 is total size of args, in bytes,
1849: ;; and what the call insn wants is the number of words.
1.1 root 1850: (define_insn "call"
1851: [(call (match_operand:QI 0 "general_operand" "g")
1852: (match_operand:QI 1 "general_operand" "g"))]
1853: ""
1.1.1.2 root 1854: "*
1.1.1.5 root 1855: if (INTVAL (operands[1]) > 255 * 4)
1856: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1857: return \"calls $0,%0\;addl2 %1,sp\";
1.1.1.2 root 1858: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);
1859: return \"calls %1,%0\";
1860: ")
1861:
1862: (define_insn "call_value"
1863: [(set (match_operand 0 "" "g")
1864: (call (match_operand:QI 1 "general_operand" "g")
1865: (match_operand:QI 2 "general_operand" "g")))]
1866: ""
1867: "*
1.1.1.7 ! root 1868: if (INTVAL (operands[2]) > 255 * 4)
1.1.1.6 root 1869: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1870: return \"calls $0,%1\;addl2 %2,sp\";
1.1.1.2 root 1871: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4);
1872: return \"calls %2,%1\";
1873: ")
1.1 root 1874:
1875: (define_insn "return"
1876: [(return)]
1877: ""
1878: "ret")
1879:
1880: (define_insn "casesi"
1881: [(set (pc)
1882: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
1883: (match_operand:SI 1 "general_operand" "g"))
1884: (match_operand:SI 2 "general_operand" "g"))
1.1.1.2 root 1885: (plus:SI (sign_extend:SI
1.1 root 1886: (mem:HI (plus:SI (pc)
1887: (minus:SI (match_dup 0)
1.1.1.2 root 1888: (match_dup 1)))))
1889: (label_ref:SI (match_operand 3 "" "")))
1.1 root 1890: (pc)))]
1891: ""
1892: "casel %0,%1,%2")
1893:
1.1.1.2 root 1894: ;; This used to arise from the preceding by simplification
1895: ;; if operand 1 is zero. Perhaps it is no longer necessary.
1896: (define_insn ""
1897: [(set (pc)
1898: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1899: (match_operand:SI 1 "general_operand" "g"))
1900: (plus:SI (sign_extend:SI
1901: (mem:HI (plus:SI (pc)
1902: (minus:SI (match_dup 0)
1903: (const_int 0)))))
1904: (label_ref:SI (match_operand 3 "" "")))
1905: (pc)))]
1906: ""
1907: "casel %0,$0,%1")
1908:
1.1 root 1909: ;; This arises from the preceding by simplification if operand 1 is zero.
1910: (define_insn ""
1911: [(set (pc)
1912: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1913: (match_operand:SI 1 "general_operand" "g"))
1.1.1.2 root 1914: (plus:SI (sign_extend:SI
1.1 root 1915: (mem:HI (plus:SI (pc)
1.1.1.2 root 1916: (match_dup 0))))
1917: (label_ref:SI (match_operand 3 "" "")))
1.1 root 1918: (pc)))]
1919: ""
1920: "casel %0,$0,%1")
1921:
1.1.1.2 root 1922: ;; Optimize extzv ...,z; andl2 ...,z
1923: ;; with other operands constant.
1924: (define_peephole
1925: [(set (match_operand:SI 0 "general_operand" "g")
1926: (zero_extract:SI (match_operand:SI 1 "general_operand" "g")
1927: (match_operand:SI 2 "general_operand" "g")
1928: (match_operand:SI 3 "general_operand" "g")))
1929: (set (match_operand:SI 4 "general_operand" "g")
1930: (and:SI (match_dup 0)
1931: (match_operand:SI 5 "general_operand" "g")))]
1932: "GET_CODE (operands[2]) == CONST_INT
1933: && GET_CODE (operands[3]) == CONST_INT
1934: && (INTVAL (operands[2]) + INTVAL (operands[3])) == 32
1935: && GET_CODE (operands[5]) == CONST_INT
1936: && dead_or_set_p (insn, operands[0])"
1937: "*
1938: {
1939: unsigned long mask = INTVAL (operands[5]);
1940: operands[3] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[3]));
1941:
1942: if ((floor_log2 (mask) + 1) >= INTVAL (operands[2]))
1943: mask &= ((1 << INTVAL (operands[2])) - 1);
1944:
1945: operands[5] = gen_rtx (CONST_INT, VOIDmode, ~mask);
1946: if (push_operand (operands[4], SImode))
1947: {
1948: output_asm_insn (\"rotl %3,%1,%0\", operands);
1949: return \"bicl3 %5,%0,%4\";
1950: }
1951: else
1952: {
1953: output_asm_insn (\"rotl %3,%1,%4\", operands);
1954: return \"bicl2 %5,%4\";
1955: }
1956: }")
1957:
1958: ;; Optimize andl3 x,y,z; extzv z,....,z
1959:
1960: (define_peephole
1961: [(set (match_operand:SI 0 "general_operand" "g")
1962: (and:SI (match_operand:SI 1 "general_operand" "g")
1963: (match_operand:SI 2 "general_operand" "g")))
1964: (set (match_operand 3 "general_operand" "g")
1965: (zero_extract:SI (match_dup 0)
1966: (match_operand:SI 4 "general_operand" "g")
1967: (match_operand:SI 5 "general_operand" "g")))]
1968: "GET_CODE (operands[2]) == CONST_INT
1969: && GET_CODE (operands[4]) == CONST_INT
1970: && GET_CODE (operands[5]) == CONST_INT
1971: && (INTVAL (operands[4]) + INTVAL (operands[5])) == 32
1972: && dead_or_set_p (insn, operands[0])"
1973: "*
1974: {
1975: unsigned long mask = INTVAL (operands[2]);
1976:
1977: mask &= ~((1 << INTVAL (operands[5])) - 1);
1978: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~mask);
1979:
1980: operands[5] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[5]));
1981:
1982: if (rtx_equal_p (operands[0], operands[1]))
1983: output_asm_insn (\"bicl2 %2,%0\", operands);
1984: else
1985: output_asm_insn (\"bicl3 %2,%1,%0\", operands);
1986: return \"rotl %5,%0,%3\";
1987: }")
1988:
1.1 root 1989: ;;- Local variables:
1990: ;;- mode:emacs-lisp
1991: ;;- comment-start: ";;- "
1992: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
1993: ;;- eval: (modify-syntax-entry ?[ "(]")
1994: ;;- eval: (modify-syntax-entry ?] ")[")
1995: ;;- eval: (modify-syntax-entry ?{ "(}")
1996: ;;- eval: (modify-syntax-entry ?} "){")
1997: ;;- End:
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