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1.1.1.4 root 1:
1.1 root 2: ;;- Machine description for GNU compiler
3: ;;- Vax Version
4: ;; Copyright (C) 1987 Free Software Foundation, Inc.
5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is distributed in the hope that it will be useful,
9: ;; but WITHOUT ANY WARRANTY. No author or distributor
10: ;; accepts responsibility to anyone for the consequences of using it
11: ;; or for whether it serves any particular purpose or works at all,
12: ;; unless he says so in writing. Refer to the GNU CC General Public
13: ;; License for full details.
14:
15: ;; Everyone is granted permission to copy, modify and redistribute
16: ;; GNU CC, but only under the conditions described in the
17: ;; GNU CC General Public License. A copy of this license is
18: ;; supposed to have been given to you along with GNU CC so you
19: ;; can know your rights and responsibilities. It should be in a
20: ;; file named COPYING. Among other things, the copyright notice
21: ;; and this notice must be preserved on all copies.
22:
23:
24: ;;- Instruction patterns. When multiple patterns apply,
25: ;;- the first one in the file is chosen.
26: ;;-
27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28: ;;-
29: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
30: ;;- updates for most instructions.
31:
1.1.1.2 root 32: ; tstsi is first test insn so that it is the one to match
33: ; a constant argument.
1.1 root 34:
35: (define_insn "tstsi"
36: [(set (cc0)
37: (match_operand:SI 0 "general_operand" "g"))]
38: ""
39: "tstl %0")
40:
41: (define_insn "tsthi"
42: [(set (cc0)
43: (match_operand:HI 0 "general_operand" "g"))]
44: ""
45: "tstw %0")
46:
47: (define_insn "tstqi"
48: [(set (cc0)
49: (match_operand:QI 0 "general_operand" "g"))]
50: ""
51: "tstb %0")
52:
1.1.1.2 root 53: (define_insn "tstdf"
1.1 root 54: [(set (cc0)
1.1.1.2 root 55: (match_operand:DF 0 "general_operand" "gF"))]
1.1 root 56: ""
1.1.1.3 root 57: "tst%# %0")
1.1 root 58:
1.1.1.2 root 59: (define_insn "tstsf"
1.1 root 60: [(set (cc0)
1.1.1.2 root 61: (match_operand:SF 0 "general_operand" "gF"))]
1.1 root 62: ""
1.1.1.2 root 63: "tstf %0")
1.1 root 64:
65: (define_insn "cmpsi"
66: [(set (cc0)
67: (minus (match_operand:SI 0 "general_operand" "g")
68: (match_operand:SI 1 "general_operand" "g")))]
69: ""
70: "cmpl %0,%1")
71:
72: (define_insn "cmphi"
73: [(set (cc0)
74: (minus (match_operand:HI 0 "general_operand" "g")
75: (match_operand:HI 1 "general_operand" "g")))]
76: ""
77: "cmpw %0,%1")
78:
79: (define_insn "cmpqi"
80: [(set (cc0)
81: (minus (match_operand:QI 0 "general_operand" "g")
82: (match_operand:QI 1 "general_operand" "g")))]
83: ""
84: "cmpb %0,%1")
85:
1.1.1.2 root 86: (define_insn "cmpdf"
87: [(set (cc0)
88: (minus (match_operand:DF 0 "general_operand" "gF")
89: (match_operand:DF 1 "general_operand" "gF")))]
90: ""
1.1.1.3 root 91: "cmp%# %0,%1")
1.1.1.2 root 92:
93: (define_insn "cmpsf"
94: [(set (cc0)
95: (minus (match_operand:SF 0 "general_operand" "gF")
96: (match_operand:SF 1 "general_operand" "gF")))]
97: ""
98: "cmpf %0,%1")
99:
1.1 root 100: (define_insn ""
101: [(set (cc0)
102: (and:SI (match_operand:SI 0 "general_operand" "g")
103: (match_operand:SI 1 "general_operand" "g")))]
104: ""
105: "bitl %0,%1")
106:
107: (define_insn ""
108: [(set (cc0)
109: (and:HI (match_operand:HI 0 "general_operand" "g")
110: (match_operand:HI 1 "general_operand" "g")))]
111: ""
112: "bitw %0,%1")
113:
114: (define_insn ""
115: [(set (cc0)
116: (and:QI (match_operand:QI 0 "general_operand" "g")
117: (match_operand:QI 1 "general_operand" "g")))]
118: ""
119: "bitb %0,%1")
120:
121: (define_insn "movdf"
122: [(set (match_operand:DF 0 "general_operand" "=g")
123: (match_operand:DF 1 "general_operand" "gF"))]
124: ""
125: "*
126: {
127: if (operands[1] == dconst0_rtx)
1.1.1.3 root 128: return \"clr%# %0\";
1.1.1.8 ! root 129: if (GET_CODE (operands[1]) != CONST_DOUBLE)
! 130: return \"movq %1,%0\";
1.1.1.3 root 131: return \"mov%# %1,%0\";
1.1 root 132: }")
133:
134: (define_insn "movsf"
135: [(set (match_operand:SF 0 "general_operand" "=g")
136: (match_operand:SF 1 "general_operand" "gF"))]
137: ""
138: "*
139: {
140: if (operands[1] == fconst0_rtx)
141: return \"clrf %0\";
1.1.1.7 root 142: if (GET_CODE (operands[1]) != CONST_DOUBLE)
143: return \"movl %1,%0\";
1.1 root 144: return \"movf %1,%0\";
145: }")
146:
1.1.1.2 root 147: ;; Some vaxes don't support this instruction.
148: ;;(define_insn "movti"
149: ;; [(set (match_operand:TI 0 "general_operand" "=g")
150: ;; (match_operand:TI 1 "general_operand" "g"))]
151: ;; ""
152: ;; "movh %1,%0")
1.1 root 153:
154: (define_insn "movdi"
155: [(set (match_operand:DI 0 "general_operand" "=g")
156: (match_operand:DI 1 "general_operand" "g"))]
157: ""
1.1.1.2 root 158: "movq %1,%0")
1.1 root 159:
160: (define_insn "movsi"
161: [(set (match_operand:SI 0 "general_operand" "=g")
162: (match_operand:SI 1 "general_operand" "g"))]
163: ""
164: "*
1.1.1.8 ! root 165: {
! 166: rtx link;
! 167: if (operands[1] == const1_rtx
! 168: && (link = find_reg_note (insn, REG_WAS_0, 0))
1.1.1.2 root 169: /* Make sure the insn that stored the 0 is still present. */
1.1.1.8 ! root 170: && ! XEXP (link, 0)->volatil
! 171: && GET_CODE (XEXP (link, 0)) != NOTE
1.1.1.5 root 172: /* Make sure cross jumping didn't happen here. */
1.1.1.8 ! root 173: && no_labels_between_p (XEXP (link, 0), insn))
1.1.1.2 root 174: /* Fastest way to change a 0 to a 1. */
1.1 root 175: return \"incl %0\";
176: if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
177: {
178: if (push_operand (operands[0], SImode))
179: return \"pushab %a1\";
180: return \"movab %a1,%0\";
181: }
1.1.1.8 ! root 182: /* this is slower than a movl, except when pushing an operand */
1.1 root 183: if (operands[1] == const0_rtx)
184: return \"clrl %0\";
185: if (GET_CODE (operands[1]) == CONST_INT
186: && (unsigned) INTVAL (operands[1]) >= 64)
187: {
188: int i = INTVAL (operands[1]);
1.1.1.8 ! root 189: if ((unsigned)(~i) < 64)
1.1 root 190: {
1.1.1.8 ! root 191: operands[1] = gen_rtx (CONST_INT, VOIDmode, ~i);
! 192: return \"mcoml %1,%0\";
1.1 root 193: }
1.1.1.8 ! root 194: if ((unsigned)i < 127)
! 195: {
! 196: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
! 197: operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63);
! 198: return \"addl3 %2,%1,%0\";
! 199: }
! 200: /* trading speed for space */
1.1 root 201: if ((unsigned)i < 0x100)
202: return \"movzbl %1,%0\";
203: if (i >= -0x80 && i < 0)
204: return \"cvtbl %1,%0\";
205: if ((unsigned)i < 0x10000)
206: return \"movzwl %1,%0\";
207: if (i >= -0x8000 && i < 0)
208: return \"cvtwl %1,%0\";
209: }
210: if (push_operand (operands[0], SImode))
211: return \"pushl %1\";
212: return \"movl %1,%0\";
213: }")
214:
215: (define_insn "movhi"
216: [(set (match_operand:HI 0 "general_operand" "=g")
217: (match_operand:HI 1 "general_operand" "g"))]
218: ""
219: "*
220: {
1.1.1.8 ! root 221: rtx link;
! 222: if (operands[1] == const1_rtx
! 223: && (link = find_reg_note (insn, REG_WAS_0, 0))
! 224: /* Make sure the insn that stored the 0 is still present. */
! 225: && ! XEXP (link, 0)->volatil
! 226: && GET_CODE (XEXP (link, 0)) != NOTE
! 227: /* Make sure cross jumping didn't happen here. */
! 228: && no_labels_between_p (XEXP (link, 0), insn))
! 229: /* Fastest way to change a 0 to a 1. */
1.1 root 230: return \"incw %0\";
231: if (operands[1] == const0_rtx)
232: return \"clrw %0\";
233: if (GET_CODE (operands[1]) == CONST_INT
234: && (unsigned) INTVAL (operands[1]) >= 64)
235: {
236: int i = INTVAL (operands[1]);
1.1.1.8 ! root 237: if ((unsigned)(~i & 0xffff) < 64)
1.1 root 238: {
1.1.1.8 ! root 239: operands[1] = gen_rtx (CONST_INT, VOIDmode, ~i);
! 240: return \"mcomw %1,%0\";
1.1 root 241: }
1.1.1.8 ! root 242: if ((unsigned)(i & 0xffff) < 127)
! 243: {
! 244: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
! 245: operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63);
! 246: return \"addw3 %2,%1,%0\";
! 247: }
! 248: /* this is a lot slower, and only saves 1 measly byte! */
! 249: /* if ((unsigned)i < 0x100)
! 250: return \"movzbw %1,%0\"; */
! 251: /* if (i >= -0x80 && i < 0)
! 252: return \"cvtbw %1,%0\"; */
1.1 root 253: }
254: return \"movw %1,%0\";
255: }")
256:
257: (define_insn "movqi"
258: [(set (match_operand:QI 0 "general_operand" "=g")
259: (match_operand:QI 1 "general_operand" "g"))]
260: ""
261: "*
262: {
263: if (operands[1] == const0_rtx)
264: return \"clrb %0\";
1.1.1.8 ! root 265: if (GET_CODE (operands[1]) == CONST_INT
! 266: && (unsigned) INTVAL (operands[1]) >= 64)
! 267: {
! 268: int i = INTVAL (operands[1]);
! 269: if ((unsigned)(~i & 0xff) < 64)
! 270: {
! 271: operands[1] = gen_rtx (CONST_INT, VOIDmode, ~i);
! 272: return \"mcomb %1,%0\";
! 273: }
! 274: #if 0
! 275: /* ASCII alphabetics */
! 276: if (((unsigned) INTVAL (operands[1]) &0xff) < 127)
! 277: {
! 278: operands[1] = gen_rtx (CONST_INT, VOIDmode, 63);
! 279: operands[2] = gen_rtx (CONST_INT, VOIDmode, i-63);
! 280: return \"addb3 %2,%1,%0\";
! 281: }
! 282: #endif
! 283: }
1.1 root 284: return \"movb %1,%0\";
285: }")
286:
287: ;; The definition of this insn does not really explain what it does,
288: ;; but it should suffice
289: ;; that anything generated as this insn will be recognized as one
290: ;; and that it won't successfully combine with anything.
291: (define_insn "movstrhi"
292: [(set (match_operand:BLK 0 "general_operand" "=g")
293: (match_operand:BLK 1 "general_operand" "g"))
294: (use (match_operand:HI 2 "general_operand" "g"))
1.1.1.2 root 295: (clobber (reg:SI 0))
296: (clobber (reg:SI 1))
297: (clobber (reg:SI 2))
298: (clobber (reg:SI 3))
299: (clobber (reg:SI 4))
300: (clobber (reg:SI 5))]
1.1 root 301: ""
302: "movc3 %2,%1,%0")
303:
304: ;;- load or push effective address
305: ;; These come after the move patterns
306: ;; because we don't want pushl $1 turned into pushad 1.
307:
308: (define_insn ""
309: [(set (match_operand:SI 0 "general_operand" "=g")
310: (match_operand:QI 1 "address_operand" "p"))]
311: ""
312: "*
313: {
314: if (push_operand (operands[0], SImode))
315: return \"pushab %a1\";
316: return \"movab %a1,%0\";
317: }")
318:
319: (define_insn ""
320: [(set (match_operand:SI 0 "general_operand" "=g")
321: (match_operand:HI 1 "address_operand" "p"))]
322: ""
323: "*
324: {
325: if (push_operand (operands[0], SImode))
326: return \"pushaw %a1\";
327: return \"movaw %a1,%0\";
328: }")
329:
330: (define_insn ""
331: [(set (match_operand:SI 0 "general_operand" "=g")
332: (match_operand:SI 1 "address_operand" "p"))]
333: ""
334: "*
335: {
336: if (push_operand (operands[0], SImode))
337: return \"pushal %a1\";
338: return \"moval %a1,%0\";
339: }")
340:
341: (define_insn ""
342: [(set (match_operand:SI 0 "general_operand" "=g")
343: (match_operand:SF 1 "address_operand" "p"))]
344: ""
345: "*
346: {
347: if (push_operand (operands[0], SImode))
348: return \"pushaf %a1\";
349: return \"movaf %a1,%0\";
350: }")
351:
352: (define_insn ""
353: [(set (match_operand:SI 0 "general_operand" "=g")
354: (match_operand:DF 1 "address_operand" "p"))]
355: ""
356: "*
357: {
358: if (push_operand (operands[0], SImode))
359: return \"pushad %a1\";
360: return \"movad %a1,%0\";
361: }")
362:
1.1.1.2 root 363: ;; Extension and truncation insns.
364: ;; Those for integer source operand
365: ;; are ordered widest source type first.
1.1 root 366:
1.1.1.2 root 367: (define_insn "truncsiqi2"
368: [(set (match_operand:QI 0 "general_operand" "=g")
369: (truncate:QI (match_operand:SI 1 "general_operand" "g")))]
1.1 root 370: ""
1.1.1.2 root 371: "cvtlb %1,%0")
1.1 root 372:
1.1.1.2 root 373: (define_insn "truncsihi2"
374: [(set (match_operand:HI 0 "general_operand" "=g")
375: (truncate:HI (match_operand:SI 1 "general_operand" "g")))]
1.1 root 376: ""
1.1.1.2 root 377: "cvtlw %1,%0")
1.1 root 378:
379: (define_insn "trunchiqi2"
380: [(set (match_operand:QI 0 "general_operand" "=g")
381: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
382: ""
383: "cvtwb %1,%0")
384:
385: (define_insn "extendhisi2"
386: [(set (match_operand:SI 0 "general_operand" "=g")
387: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
388: ""
389: "cvtwl %1,%0")
390:
1.1.1.2 root 391: (define_insn "extendqihi2"
392: [(set (match_operand:HI 0 "general_operand" "=g")
393: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1.1 root 394: ""
1.1.1.2 root 395: "cvtbw %1,%0")
1.1 root 396:
1.1.1.2 root 397: (define_insn "extendqisi2"
398: [(set (match_operand:SI 0 "general_operand" "=g")
399: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
400: ""
401: "cvtbl %1,%0")
402:
403: (define_insn "extendsfdf2"
1.1 root 404: [(set (match_operand:DF 0 "general_operand" "=g")
1.1.1.2 root 405: (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
1.1 root 406: ""
1.1.1.3 root 407: "cvtf%# %1,%0")
1.1 root 408:
1.1.1.2 root 409: (define_insn "truncdfsf2"
410: [(set (match_operand:SF 0 "general_operand" "=g")
411: (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
1.1 root 412: ""
1.1.1.3 root 413: "cvt%#f %1,%0")
1.1 root 414:
1.1.1.2 root 415: (define_insn "zero_extendhisi2"
416: [(set (match_operand:SI 0 "general_operand" "=g")
417: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
418: ""
419: "movzwl %1,%0")
420:
421: (define_insn "zero_extendqihi2"
1.1 root 422: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 423: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1.1 root 424: ""
1.1.1.2 root 425: "movzbw %1,%0")
426:
427: (define_insn "zero_extendqisi2"
428: [(set (match_operand:SI 0 "general_operand" "=g")
429: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
430: ""
431: "movzbl %1,%0")
432:
433: ;; Fix-to-float conversion insns.
434: ;; Note that the ones that start with SImode come first.
435: ;; That is so that an operand that is a CONST_INT
436: ;; (and therefore lacks a specific machine mode).
437: ;; will be recognized as SImode (which is always valid)
438: ;; rather than as QImode or HImode.
1.1 root 439:
440: (define_insn "floatsisf2"
441: [(set (match_operand:SF 0 "general_operand" "=g")
442: (float:SF (match_operand:SI 1 "general_operand" "g")))]
443: ""
444: "cvtlf %1,%0")
445:
446: (define_insn "floatsidf2"
447: [(set (match_operand:DF 0 "general_operand" "=g")
448: (float:DF (match_operand:SI 1 "general_operand" "g")))]
449: ""
1.1.1.3 root 450: "cvtl%# %1,%0")
1.1 root 451:
1.1.1.2 root 452: (define_insn "floathisf2"
453: [(set (match_operand:SF 0 "general_operand" "=g")
454: (float:SF (match_operand:HI 1 "general_operand" "g")))]
1.1 root 455: ""
1.1.1.2 root 456: "cvtwf %1,%0")
1.1 root 457:
1.1.1.2 root 458: (define_insn "floathidf2"
459: [(set (match_operand:DF 0 "general_operand" "=g")
460: (float:DF (match_operand:HI 1 "general_operand" "g")))]
1.1 root 461: ""
1.1.1.3 root 462: "cvtw%# %1,%0")
1.1 root 463:
1.1.1.2 root 464: (define_insn "floatqisf2"
465: [(set (match_operand:SF 0 "general_operand" "=g")
466: (float:SF (match_operand:QI 1 "general_operand" "g")))]
1.1 root 467: ""
1.1.1.2 root 468: "cvtbf %1,%0")
1.1 root 469:
1.1.1.2 root 470: (define_insn "floatqidf2"
1.1 root 471: [(set (match_operand:DF 0 "general_operand" "=g")
1.1.1.2 root 472: (float:DF (match_operand:QI 1 "general_operand" "g")))]
1.1 root 473: ""
1.1.1.3 root 474: "cvtb%# %1,%0")
1.1.1.2 root 475:
476: ;; Float-to-fix conversion insns.
1.1 root 477:
1.1.1.2 root 478: (define_insn "fix_truncsfqi2"
1.1 root 479: [(set (match_operand:QI 0 "general_operand" "=g")
1.1.1.2 root 480: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 481: ""
1.1.1.2 root 482: "cvtfb %1,%0")
1.1 root 483:
1.1.1.2 root 484: (define_insn "fix_truncsfhi2"
1.1 root 485: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 486: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 487: ""
1.1.1.2 root 488: "cvtfw %1,%0")
1.1 root 489:
1.1.1.2 root 490: (define_insn "fix_truncsfsi2"
1.1 root 491: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 492: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
1.1 root 493: ""
1.1.1.2 root 494: "cvtfl %1,%0")
1.1 root 495:
1.1.1.2 root 496: (define_insn "fix_truncdfqi2"
497: [(set (match_operand:QI 0 "general_operand" "=g")
498: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 499: ""
1.1.1.8 ! root 500: "cvt%#b %1,%0")
1.1 root 501:
1.1.1.2 root 502: (define_insn "fix_truncdfhi2"
1.1 root 503: [(set (match_operand:HI 0 "general_operand" "=g")
1.1.1.2 root 504: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 505: ""
1.1.1.3 root 506: "cvt%#w %1,%0")
1.1 root 507:
1.1.1.2 root 508: (define_insn "fix_truncdfsi2"
1.1 root 509: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.2 root 510: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
1.1 root 511: ""
1.1.1.3 root 512: "cvt%#l %1,%0")
1.1 root 513:
514: ;;- All kinds of add instructions.
515:
516: (define_insn "adddf3"
517: [(set (match_operand:DF 0 "general_operand" "=g")
518: (plus:DF (match_operand:DF 1 "general_operand" "gF")
519: (match_operand:DF 2 "general_operand" "gF")))]
520: ""
521: "*
522: {
523: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 524: return \"add%#2 %2,%0\";
1.1 root 525: if (rtx_equal_p (operands[0], operands[2]))
1.1.1.3 root 526: return \"add%#2 %1,%0\";
527: return \"add%#3 %1,%2,%0\";
1.1 root 528: }")
529:
530: (define_insn "addsf3"
531: [(set (match_operand:SF 0 "general_operand" "=g")
532: (plus:SF (match_operand:SF 1 "general_operand" "gF")
533: (match_operand:SF 2 "general_operand" "gF")))]
534: ""
535: "*
536: {
537: if (rtx_equal_p (operands[0], operands[1]))
538: return \"addf2 %2,%0\";
539: if (rtx_equal_p (operands[0], operands[2]))
540: return \"addf2 %1,%0\";
541: return \"addf3 %1,%2,%0\";
542: }")
543:
544: (define_insn "addsi3"
545: [(set (match_operand:SI 0 "general_operand" "=g")
546: (plus:SI (match_operand:SI 1 "general_operand" "g")
547: (match_operand:SI 2 "general_operand" "g")))]
548: ""
549: "*
550: {
551: if (rtx_equal_p (operands[0], operands[1]))
552: {
553: if (operands[2] == const1_rtx)
554: return \"incl %0\";
1.1.1.2 root 555: if (GET_CODE (operands[2]) == CONST_INT
556: && INTVAL (operands[2]) == -1)
1.1 root 557: return \"decl %0\";
558: if (GET_CODE (operands[2]) == CONST_INT
559: && (unsigned) (- INTVAL (operands[2])) < 64)
560: return \"subl2 $%n2,%0\";
1.1.1.8 ! root 561: if (GET_CODE (operands[2]) == CONST_INT
! 562: && (unsigned) INTVAL (operands[2]) >= 64
! 563: && GET_CODE (operands[1]) == REG)
! 564: return \"movab %c2(%1),%0\";
1.1 root 565: return \"addl2 %2,%0\";
566: }
567: if (rtx_equal_p (operands[0], operands[2]))
568: return \"addl2 %1,%0\";
569: if (GET_CODE (operands[2]) == CONST_INT
1.1.1.8 ! root 570: && (unsigned) (- INTVAL (operands[2])) < 64)
! 571: return \"subl3 $%n2,%1,%0\";
! 572: if (GET_CODE (operands[2]) == CONST_INT
! 573: && (unsigned) INTVAL (operands[2]) >= 64
1.1 root 574: && GET_CODE (operands[1]) == REG)
575: {
576: if (push_operand (operands[0], SImode))
1.1.1.8 ! root 577: return \"pushab %c2(%1)\";
1.1 root 578: return \"movab %c2(%1),%0\";
579: }
580: return \"addl3 %1,%2,%0\";
581: }")
582:
583: (define_insn "addhi3"
584: [(set (match_operand:HI 0 "general_operand" "=g")
585: (plus:HI (match_operand:HI 1 "general_operand" "g")
586: (match_operand:HI 2 "general_operand" "g")))]
587: ""
588: "*
589: {
590: if (rtx_equal_p (operands[0], operands[1]))
591: {
592: if (operands[2] == const1_rtx)
593: return \"incw %0\";
594: if (GET_CODE (operands[1]) == CONST_INT
595: && INTVAL (operands[1]) == -1)
596: return \"decw %0\";
597: if (GET_CODE (operands[2]) == CONST_INT
598: && (unsigned) (- INTVAL (operands[2])) < 64)
599: return \"subw2 $%n2,%0\";
600: return \"addw2 %2,%0\";
601: }
602: if (rtx_equal_p (operands[0], operands[2]))
603: return \"addw2 %1,%0\";
604: if (GET_CODE (operands[2]) == CONST_INT
605: && (unsigned) (- INTVAL (operands[2])) < 64)
606: return \"subw3 $%n2,%1,%0\";
607: return \"addw3 %1,%2,%0\";
608: }")
609:
610: (define_insn "addqi3"
611: [(set (match_operand:QI 0 "general_operand" "=g")
612: (plus:QI (match_operand:QI 1 "general_operand" "g")
613: (match_operand:QI 2 "general_operand" "g")))]
614: ""
615: "*
616: {
617: if (rtx_equal_p (operands[0], operands[1]))
618: {
619: if (operands[2] == const1_rtx)
620: return \"incb %0\";
621: if (GET_CODE (operands[1]) == CONST_INT
622: && INTVAL (operands[1]) == -1)
623: return \"decb %0\";
624: if (GET_CODE (operands[2]) == CONST_INT
625: && (unsigned) (- INTVAL (operands[2])) < 64)
626: return \"subb2 $%n2,%0\";
627: return \"addb2 %2,%0\";
628: }
629: if (rtx_equal_p (operands[0], operands[2]))
630: return \"addb2 %1,%0\";
631: if (GET_CODE (operands[2]) == CONST_INT
632: && (unsigned) (- INTVAL (operands[2])) < 64)
633: return \"subb3 $%n2,%1,%0\";
634: return \"addb3 %1,%2,%0\";
635: }")
636:
637: ;;- All kinds of subtract instructions.
638:
639: (define_insn "subdf3"
640: [(set (match_operand:DF 0 "general_operand" "=g")
641: (minus:DF (match_operand:DF 1 "general_operand" "gF")
642: (match_operand:DF 2 "general_operand" "gF")))]
643: ""
644: "*
645: {
646: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 647: return \"sub%#2 %2,%0\";
648: return \"sub%#3 %2,%1,%0\";
1.1 root 649: }")
650:
651: (define_insn "subsf3"
652: [(set (match_operand:SF 0 "general_operand" "=g")
653: (minus:SF (match_operand:SF 1 "general_operand" "gF")
654: (match_operand:SF 2 "general_operand" "gF")))]
655: ""
656: "*
657: {
658: if (rtx_equal_p (operands[0], operands[1]))
659: return \"subf2 %2,%0\";
660: return \"subf3 %2,%1,%0\";
661: }")
662:
663: (define_insn "subsi3"
664: [(set (match_operand:SI 0 "general_operand" "=g")
665: (minus:SI (match_operand:SI 1 "general_operand" "g")
666: (match_operand:SI 2 "general_operand" "g")))]
667: ""
668: "*
669: {
670: if (rtx_equal_p (operands[0], operands[1]))
671: {
672: if (operands[2] == const1_rtx)
673: return \"decl %0\";
674: return \"subl2 %2,%0\";
675: }
676: return \"subl3 %2,%1,%0\";
677: }")
678:
679: (define_insn "subhi3"
680: [(set (match_operand:HI 0 "general_operand" "=g")
681: (minus:HI (match_operand:HI 1 "general_operand" "g")
682: (match_operand:HI 2 "general_operand" "g")))]
683: ""
684: "*
685: {
686: if (rtx_equal_p (operands[0], operands[1]))
687: {
688: if (operands[2] == const1_rtx)
689: return \"decw %0\";
690: return \"subw2 %2,%0\";
691: }
692: return \"subw3 %2,%1,%0\";
693: }")
694:
695: (define_insn "subqi3"
696: [(set (match_operand:QI 0 "general_operand" "=g")
697: (minus:QI (match_operand:QI 1 "general_operand" "g")
698: (match_operand:QI 2 "general_operand" "g")))]
699: ""
700: "*
701: {
702: if (rtx_equal_p (operands[0], operands[1]))
703: {
704: if (operands[2] == const1_rtx)
705: return \"decb %0\";
706: return \"subb2 %2,%0\";
707: }
708: return \"subb3 %2,%1,%0\";
709: }")
710:
711: ;;- Multiply instructions.
712:
713: (define_insn "muldf3"
714: [(set (match_operand:DF 0 "general_operand" "=g")
715: (mult:DF (match_operand:DF 1 "general_operand" "gF")
716: (match_operand:DF 2 "general_operand" "gF")))]
717: ""
718: "*
719: {
720: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 721: return \"mul%#2 %2,%0\";
1.1 root 722: if (rtx_equal_p (operands[0], operands[2]))
1.1.1.3 root 723: return \"mul%#2 %1,%0\";
724: return \"mul%#3 %1,%2,%0\";
1.1 root 725: }")
726:
727: (define_insn "mulsf3"
728: [(set (match_operand:SF 0 "general_operand" "=g")
729: (mult:SF (match_operand:SF 1 "general_operand" "gF")
730: (match_operand:SF 2 "general_operand" "gF")))]
731: ""
732: "*
733: {
734: if (rtx_equal_p (operands[0], operands[1]))
735: return \"mulf2 %2,%0\";
736: if (rtx_equal_p (operands[0], operands[2]))
737: return \"mulf2 %1,%0\";
738: return \"mulf3 %1,%2,%0\";
739: }")
740:
741: (define_insn "mulsi3"
742: [(set (match_operand:SI 0 "general_operand" "=g")
743: (mult:SI (match_operand:SI 1 "general_operand" "g")
744: (match_operand:SI 2 "general_operand" "g")))]
745: ""
746: "*
747: {
748: if (rtx_equal_p (operands[0], operands[1]))
749: return \"mull2 %2,%0\";
750: if (rtx_equal_p (operands[0], operands[2]))
751: return \"mull2 %1,%0\";
752: return \"mull3 %1,%2,%0\";
753: }")
754:
755: (define_insn "mulhi3"
756: [(set (match_operand:HI 0 "general_operand" "=g")
757: (mult:HI (match_operand:HI 1 "general_operand" "g")
758: (match_operand:HI 2 "general_operand" "g")))]
759: ""
760: "*
761: {
762: if (rtx_equal_p (operands[0], operands[1]))
763: return \"mulw2 %2,%0\";
764: if (rtx_equal_p (operands[0], operands[2]))
765: return \"mulw2 %1,%0\";
766: return \"mulw3 %1,%2,%0\";
767: }")
768:
769: (define_insn "mulqi3"
770: [(set (match_operand:QI 0 "general_operand" "=g")
771: (mult:QI (match_operand:QI 1 "general_operand" "g")
772: (match_operand:QI 2 "general_operand" "g")))]
773: ""
774: "*
775: {
776: if (rtx_equal_p (operands[0], operands[1]))
777: return \"mulb2 %2,%0\";
778: if (rtx_equal_p (operands[0], operands[2]))
779: return \"mulb2 %1,%0\";
780: return \"mulb3 %1,%2,%0\";
781: }")
782:
783: ;;- Divide instructions.
784:
785: (define_insn "divdf3"
786: [(set (match_operand:DF 0 "general_operand" "=g")
787: (div:DF (match_operand:DF 1 "general_operand" "gF")
788: (match_operand:DF 2 "general_operand" "gF")))]
789: ""
790: "*
791: {
792: if (rtx_equal_p (operands[0], operands[1]))
1.1.1.3 root 793: return \"div%#2 %2,%0\";
794: return \"div%#3 %2,%1,%0\";
1.1 root 795: }")
796:
797: (define_insn "divsf3"
798: [(set (match_operand:SF 0 "general_operand" "=g")
799: (div:SF (match_operand:SF 1 "general_operand" "gF")
800: (match_operand:SF 2 "general_operand" "gF")))]
801: ""
802: "*
803: {
804: if (rtx_equal_p (operands[0], operands[1]))
805: return \"divf2 %2,%0\";
806: return \"divf3 %2,%1,%0\";
807: }")
808:
809: (define_insn "divsi3"
810: [(set (match_operand:SI 0 "general_operand" "=g")
811: (div:SI (match_operand:SI 1 "general_operand" "g")
812: (match_operand:SI 2 "general_operand" "g")))]
813: ""
814: "*
815: {
816: if (rtx_equal_p (operands[0], operands[1]))
817: return \"divl2 %2,%0\";
818: return \"divl3 %2,%1,%0\";
819: }")
820:
821: (define_insn "divhi3"
822: [(set (match_operand:HI 0 "general_operand" "=g")
823: (div:HI (match_operand:HI 1 "general_operand" "g")
824: (match_operand:HI 2 "general_operand" "g")))]
825: ""
826: "*
827: {
828: if (rtx_equal_p (operands[0], operands[1]))
829: return \"divw2 %2,%0\";
830: return \"divw3 %2,%1,%0\";
831: }")
832:
833: (define_insn "divqi3"
834: [(set (match_operand:QI 0 "general_operand" "=g")
835: (div:QI (match_operand:QI 1 "general_operand" "g")
836: (match_operand:QI 2 "general_operand" "g")))]
837: ""
838: "*
839: {
840: if (rtx_equal_p (operands[0], operands[1]))
841: return \"divb2 %2,%0\";
842: return \"divb3 %2,%1,%0\";
843: }")
844:
845: ;This is left out because it is very slow;
846: ;we are better off programming around the "lack" of this insn.
847: ;(define_insn "divmoddisi4"
848: ; [(set (match_operand:SI 0 "general_operand" "=g")
849: ; (div:SI (match_operand:DI 1 "general_operand" "g")
850: ; (match_operand:SI 2 "general_operand" "g")))
851: ; (set (match_operand:SI 3 "general_operand" "=g")
852: ; (mod:SI (match_operand:DI 1 "general_operand" "g")
853: ; (match_operand:SI 2 "general_operand" "g")))]
854: ; ""
855: ; "ediv %2,%1,%0,%3")
856:
1.1.1.8 ! root 857: ;; Bit-and on the vax is done with a clear-bits insn.
! 858: (define_expand "andsi3"
! 859: [(set (match_operand:SI 0 "general_operand" "=g")
! 860: (and:SI (match_operand:SI 1 "general_operand" "g")
! 861: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
! 862: ""
! 863: "
! 864: {
! 865: extern rtx expand_unop ();
! 866: if (GET_CODE (operands[2]) == CONST_INT)
! 867: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
! 868: else
! 869: operands[2] = expand_unop (SImode, one_cmpl_optab, operands[2], 0, 1);
! 870: }")
! 871:
! 872: (define_expand "andhi3"
! 873: [(set (match_operand:HI 0 "general_operand" "=g")
! 874: (and:HI (match_operand:HI 1 "general_operand" "g")
! 875: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
! 876: ""
! 877: "
! 878: {
! 879: extern rtx expand_unop ();
! 880: rtx op = operands[2];
! 881: if (GET_CODE (op) == CONST_INT)
! 882: operands[2] = gen_rtx (CONST_INT, VOIDmode,
! 883: ((1 << 16) - 1) & ~INTVAL (op));
! 884: else
! 885: operands[2] = expand_unop (HImode, one_cmpl_optab, op, 0, 1);
! 886: }")
! 887:
! 888: (define_expand "andqi3"
! 889: [(set (match_operand:QI 0 "general_operand" "=g")
! 890: (and:QI (match_operand:QI 1 "general_operand" "g")
! 891: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
! 892: ""
! 893: "
! 894: {
! 895: extern rtx expand_unop ();
! 896: rtx op = operands[2];
! 897: if (GET_CODE (op) == CONST_INT)
! 898: operands[2] = gen_rtx (CONST_INT, VOIDmode,
! 899: ((1 << 8) - 1) & ~INTVAL (op));
! 900: else
! 901: operands[2] = expand_unop (QImode, one_cmpl_optab, op, 0, 1);
! 902: }")
! 903:
1.1 root 904: (define_insn "andcbsi3"
905: [(set (match_operand:SI 0 "general_operand" "=g")
906: (and:SI (match_operand:SI 1 "general_operand" "g")
907: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
908: ""
909: "*
910: {
911: if (rtx_equal_p (operands[0], operands[1]))
912: return \"bicl2 %2,%0\";
913: return \"bicl3 %2,%1,%0\";
914: }")
915:
916: (define_insn "andcbhi3"
917: [(set (match_operand:HI 0 "general_operand" "=g")
918: (and:HI (match_operand:HI 1 "general_operand" "g")
919: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
920: ""
921: "*
922: {
923: if (rtx_equal_p (operands[0], operands[1]))
924: return \"bicw2 %2,%0\";
925: return \"bicw3 %2,%1,%0\";
926: }")
927:
928: (define_insn "andcbqi3"
929: [(set (match_operand:QI 0 "general_operand" "=g")
930: (and:QI (match_operand:QI 1 "general_operand" "g")
931: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
932: ""
933: "*
934: {
935: if (rtx_equal_p (operands[0], operands[1]))
936: return \"bicb2 %2,%0\";
937: return \"bicb3 %2,%1,%0\";
938: }")
939:
940: ;; The following are needed because constant propagation can
941: ;; create them starting from the bic insn patterns above.
942:
943: (define_insn ""
944: [(set (match_operand:SI 0 "general_operand" "=g")
945: (and:SI (match_operand:SI 1 "general_operand" "g")
946: (match_operand:SI 2 "general_operand" "g")))]
947: "GET_CODE (operands[2]) == CONST_INT"
948: "*
949: { operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
950: if (rtx_equal_p (operands[1], operands[0]))
951: return \"bicl2 %2,%0\";
952: return \"bicl3 %2,%1,%0\";
953: }")
954:
955: (define_insn ""
956: [(set (match_operand:HI 0 "general_operand" "=g")
957: (and:HI (match_operand:HI 1 "general_operand" "g")
958: (match_operand:HI 2 "general_operand" "g")))]
959: "GET_CODE (operands[2]) == CONST_INT"
960: "*
961: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xffff & ~INTVAL (operands[2]));
962: if (rtx_equal_p (operands[1], operands[0]))
963: return \"bicw2 %2,%0\";
964: return \"bicw3 %2,%1,%0\";
965: }")
966:
967: (define_insn ""
968: [(set (match_operand:QI 0 "general_operand" "=g")
969: (and:QI (match_operand:QI 1 "general_operand" "g")
970: (match_operand:QI 2 "general_operand" "g")))]
971: "GET_CODE (operands[2]) == CONST_INT"
972: "*
973: { operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xff & ~INTVAL (operands[2]));
974: if (rtx_equal_p (operands[1], operands[0]))
975: return \"bicb2 %2,%0\";
976: return \"bicb3 %2,%1,%0\";
977: }")
978:
979: ;;- Bit set instructions.
980:
981: (define_insn "iorsi3"
982: [(set (match_operand:SI 0 "general_operand" "=g")
983: (ior:SI (match_operand:SI 1 "general_operand" "g")
984: (match_operand:SI 2 "general_operand" "g")))]
985: ""
986: "*
987: {
988: if (rtx_equal_p (operands[0], operands[1]))
989: return \"bisl2 %2,%0\";
990: if (rtx_equal_p (operands[0], operands[2]))
991: return \"bisl2 %1,%0\";
992: return \"bisl3 %2,%1,%0\";
993: }")
994:
995: (define_insn "iorhi3"
996: [(set (match_operand:HI 0 "general_operand" "=g")
997: (ior:HI (match_operand:HI 1 "general_operand" "g")
998: (match_operand:HI 2 "general_operand" "g")))]
999: ""
1000: "*
1001: {
1002: if (rtx_equal_p (operands[0], operands[1]))
1003: return \"bisw2 %2,%0\";
1004: if (rtx_equal_p (operands[0], operands[2]))
1005: return \"bisw2 %1,%0\";
1006: return \"bisw3 %2,%1,%0\";
1007: }")
1008:
1009: (define_insn "iorqi3"
1010: [(set (match_operand:QI 0 "general_operand" "=g")
1011: (ior:QI (match_operand:QI 1 "general_operand" "g")
1012: (match_operand:QI 2 "general_operand" "g")))]
1013: ""
1014: "*
1015: {
1016: if (rtx_equal_p (operands[0], operands[1]))
1017: return \"bisb2 %2,%0\";
1018: if (rtx_equal_p (operands[0], operands[2]))
1019: return \"bisb2 %1,%0\";
1020: return \"bisb3 %2,%1,%0\";
1021: }")
1022:
1023: ;;- xor instructions.
1024:
1025: (define_insn "xorsi3"
1026: [(set (match_operand:SI 0 "general_operand" "=g")
1027: (xor:SI (match_operand:SI 1 "general_operand" "g")
1028: (match_operand:SI 2 "general_operand" "g")))]
1029: ""
1030: "*
1031: {
1032: if (rtx_equal_p (operands[0], operands[1]))
1033: return \"xorl2 %2,%0\";
1034: if (rtx_equal_p (operands[0], operands[2]))
1035: return \"xorl2 %1,%0\";
1036: return \"xorl3 %2,%1,%0\";
1037: }")
1038:
1039: (define_insn "xorhi3"
1040: [(set (match_operand:HI 0 "general_operand" "=g")
1041: (xor:HI (match_operand:HI 1 "general_operand" "g")
1042: (match_operand:HI 2 "general_operand" "g")))]
1043: ""
1044: "*
1045: {
1046: if (rtx_equal_p (operands[0], operands[1]))
1047: return \"xorw2 %2,%0\";
1048: if (rtx_equal_p (operands[0], operands[2]))
1049: return \"xorw2 %1,%0\";
1050: return \"xorw3 %2,%1,%0\";
1051: }")
1052:
1053: (define_insn "xorqi3"
1054: [(set (match_operand:QI 0 "general_operand" "=g")
1055: (xor:QI (match_operand:QI 1 "general_operand" "g")
1056: (match_operand:QI 2 "general_operand" "g")))]
1057: ""
1058: "*
1059: {
1060: if (rtx_equal_p (operands[0], operands[1]))
1061: return \"xorb2 %2,%0\";
1062: if (rtx_equal_p (operands[0], operands[2]))
1063: return \"xorb2 %1,%0\";
1064: return \"xorb3 %2,%1,%0\";
1065: }")
1066:
1067: (define_insn "negdf2"
1068: [(set (match_operand:DF 0 "general_operand" "=g")
1069: (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
1070: ""
1.1.1.3 root 1071: "mneg%# %1,%0")
1.1 root 1072:
1073: (define_insn "negsf2"
1074: [(set (match_operand:SF 0 "general_operand" "=g")
1075: (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
1076: ""
1077: "mnegf %1,%0")
1078:
1079: (define_insn "negsi2"
1080: [(set (match_operand:SI 0 "general_operand" "=g")
1081: (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1082: ""
1083: "mnegl %1,%0")
1084:
1085: (define_insn "neghi2"
1086: [(set (match_operand:HI 0 "general_operand" "=g")
1087: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1088: ""
1089: "mnegw %1,%0")
1090:
1091: (define_insn "negqi2"
1092: [(set (match_operand:QI 0 "general_operand" "=g")
1093: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1094: ""
1095: "mnegb %1,%0")
1096:
1097: (define_insn "one_cmplsi2"
1098: [(set (match_operand:SI 0 "general_operand" "=g")
1099: (not:SI (match_operand:SI 1 "general_operand" "g")))]
1100: ""
1101: "mcoml %1,%0")
1102:
1103: (define_insn "one_cmplhi2"
1104: [(set (match_operand:HI 0 "general_operand" "=g")
1105: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1106: ""
1107: "mcomw %1,%0")
1108:
1109: (define_insn "one_cmplqi2"
1110: [(set (match_operand:QI 0 "general_operand" "=g")
1111: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1112: ""
1113: "mcomb %1,%0")
1114:
1.1.1.8 ! root 1115: ;; Arithmetic right shift on the vax works by negating the shift count.
! 1116: (define_expand "ashrsi3"
! 1117: [(set (match_operand:SI 0 "general_operand" "=g")
! 1118: (ashift:SI (match_operand:SI 1 "general_operand" "g")
! 1119: (match_operand:QI 2 "general_operand" "g")))]
! 1120: ""
! 1121: "
! 1122: {
! 1123: extern rtx negate_rtx ();
! 1124: operands[2] = negate_rtx (operands[2]);
! 1125: }")
! 1126:
1.1 root 1127: (define_insn "ashlsi3"
1128: [(set (match_operand:SI 0 "general_operand" "=g")
1129: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1130: (match_operand:QI 2 "general_operand" "g")))]
1131: ""
1.1.1.2 root 1132: "*
1133: {
1134: if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1135: return \"addl2 %0,%0\";
1.1.1.8 ! root 1136: if (GET_CODE (operands[1]) == REG
! 1137: && GET_CODE (operands[2]) == CONST_INT)
! 1138: {
! 1139: int i = INTVAL (operands[2]);
! 1140: if (i == 1)
! 1141: return \"addl3 %1,%1,%0\";
! 1142: if (i == 2)
! 1143: return \"moval 0[%1],%0\";
! 1144: if (i == 3)
! 1145: return \"movad 0[%1],%0\";
! 1146: }
1.1.1.2 root 1147: return \"ashl %2,%1,%0\";
1148: }")
1.1 root 1149:
1.1.1.8 ! root 1150: ;; Arithmetic right shift on the vax works by negating the shift count.
! 1151: (define_expand "ashrdi3"
! 1152: [(set (match_operand:DI 0 "general_operand" "=g")
! 1153: (ashift:DI (match_operand:DI 1 "general_operand" "g")
! 1154: (match_operand:QI 2 "general_operand" "g")))]
! 1155: ""
! 1156: "
! 1157: {
! 1158: extern rtx negate_rtx ();
! 1159: operands[2] = negate_rtx (operands[2]);
! 1160: }")
! 1161:
1.1 root 1162: (define_insn "ashldi3"
1163: [(set (match_operand:DI 0 "general_operand" "=g")
1164: (ashift:DI (match_operand:DI 1 "general_operand" "g")
1165: (match_operand:QI 2 "general_operand" "g")))]
1166: ""
1167: "ashq %2,%1,%0")
1168:
1.1.1.8 ! root 1169: ;; Rotate right on the vax works by negating the shift count.
! 1170: (define_expand "rotrsi3"
1.1 root 1171: [(set (match_operand:SI 0 "general_operand" "=g")
1172: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1173: (match_operand:QI 2 "general_operand" "g")))]
1174: ""
1.1.1.8 ! root 1175: "
! 1176: {
! 1177: extern rtx negate_rtx ();
! 1178: operands[2] = negate_rtx (operands[2]);
! 1179: }")
1.1 root 1180:
1.1.1.8 ! root 1181: (define_insn "rotlsi3"
! 1182: [(set (match_operand:SI 0 "general_operand" "=g")
! 1183: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1.1 root 1184: (match_operand:QI 2 "general_operand" "g")))]
1185: ""
1.1.1.8 ! root 1186: "rotl %2,%1,%0")
1.1 root 1187:
1.1.1.2 root 1188: ;This insn is probably slower than a multiply and an add.
1189: ;(define_insn ""
1190: ; [(set (match_operand:SI 0 "general_operand" "=g")
1191: ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1192: ; (match_operand:SI 2 "general_operand" "g"))
1193: ; (match_operand:SI 3 "general_operand" "g")))]
1194: ; ""
1195: ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1.1.1.4 root 1196:
1197: ;; Special cases of bit-field insns which we should
1198: ;; recognize in preference to the general case.
1199: ;; These handle aligned 8-bit and 16-bit fields,
1200: ;; which can usually be done with move instructions.
1201:
1202: (define_insn ""
1203: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro")
1204: (match_operand:SI 1 "immediate_operand" "i")
1205: (match_operand:SI 2 "immediate_operand" "i"))
1206: (match_operand:SI 3 "general_operand" "g"))]
1207: "GET_CODE (operands[1]) == CONST_INT
1208: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1209: && GET_CODE (operands[2]) == CONST_INT
1210: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1211: && (GET_CODE (operands[0]) == REG
1212: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1213: "*
1214: {
1215: if (REG_P (operands[0]))
1216: {
1217: if (INTVAL (operands[2]) != 0)
1218: return \"insv %3,%2,%1,%0\";
1219: }
1220: else
1221: operands[0]
1222: = adj_offsetable_operand (operands[0], INTVAL (operands[2]) / 8);
1223:
1224: if (INTVAL (operands[1]) == 8)
1225: return \"movb %3,%0\";
1226: return \"movw %3,%0\";
1227: }")
1228:
1229: (define_insn ""
1230: [(set (match_operand:SI 0 "general_operand" "=&g")
1231: (zero_extract:SI (match_operand:SI 1 "general_operand" "ro")
1232: (match_operand:SI 2 "immediate_operand" "i")
1233: (match_operand:SI 3 "immediate_operand" "i")))]
1234: "GET_CODE (operands[2]) == CONST_INT
1235: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1236: && GET_CODE (operands[3]) == CONST_INT
1237: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1238: && (GET_CODE (operands[1]) == REG
1239: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1240: "*
1241: {
1242: if (REG_P (operands[1]))
1243: {
1244: if (INTVAL (operands[3]) != 0)
1245: return \"extzv %3,%2,%1,%0\";
1246: }
1247: else
1248: operands[1]
1249: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8);
1250:
1251: if (INTVAL (operands[2]) == 8)
1252: return \"movzbl %1,%0\";
1253: return \"movzwl %1,%0\";
1254: }")
1255:
1256: (define_insn ""
1257: [(set (match_operand:SI 0 "general_operand" "=g")
1258: (sign_extract:SI (match_operand:SI 1 "general_operand" "ro")
1259: (match_operand:SI 2 "immediate_operand" "i")
1260: (match_operand:SI 3 "immediate_operand" "i")))]
1261: "GET_CODE (operands[2]) == CONST_INT
1262: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1263: && GET_CODE (operands[3]) == CONST_INT
1264: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1265: && (GET_CODE (operands[1]) == REG
1266: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1267: "*
1268: {
1269: if (REG_P (operands[1]))
1270: {
1271: if (INTVAL (operands[3]) != 0)
1272: return \"extv %3,%2,%1,%0\";
1273: }
1274: else
1275: operands[1]
1276: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8);
1277:
1278: if (INTVAL (operands[2]) == 8)
1279: return \"cvtbl %1,%0\";
1280: return \"cvtwl %1,%0\";
1281: }")
1282:
1283: ;; Register-only SImode cases of bit-field insns.
1.1 root 1284:
1285: (define_insn ""
1286: [(set (cc0)
1287: (minus
1.1.1.4 root 1288: (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1.1 root 1289: (match_operand:SI 1 "general_operand" "g")
1290: (match_operand:SI 2 "general_operand" "g"))
1291: (match_operand:SI 3 "general_operand" "g")))]
1292: ""
1293: "cmpv %2,%1,%0,%3")
1294:
1295: (define_insn ""
1296: [(set (cc0)
1297: (minus
1.1.1.4 root 1298: (zero_extract:SI (match_operand:SI 0 "general_operand" "r")
1.1 root 1299: (match_operand:SI 1 "general_operand" "g")
1300: (match_operand:SI 2 "general_operand" "g"))
1301: (match_operand:SI 3 "general_operand" "g")))]
1302: ""
1303: "cmpzv %2,%1,%0,%3")
1304:
1.1.1.4 root 1305: (define_insn ""
1.1 root 1306: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1307: (sign_extract:SI (match_operand:SI 1 "general_operand" "r")
1.1 root 1308: (match_operand:SI 2 "general_operand" "g")
1309: (match_operand:SI 3 "general_operand" "g")))]
1310: ""
1311: "extv %3,%2,%1,%0")
1312:
1.1.1.4 root 1313: (define_insn ""
1.1 root 1314: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1315: (zero_extract:SI (match_operand:SI 1 "general_operand" "r")
1.1 root 1316: (match_operand:SI 2 "general_operand" "g")
1317: (match_operand:SI 3 "general_operand" "g")))]
1318: ""
1319: "extzv %3,%2,%1,%0")
1320:
1.1.1.4 root 1321: ;; Non-register cases.
1322: ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1323: ;; don't match these (and therefore match the cases above instead).
1324:
1.1 root 1325: (define_insn ""
1.1.1.4 root 1326: [(set (cc0)
1327: (minus
1328: (sign_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1329: (match_operand:SI 1 "general_operand" "g")
1330: (match_operand:SI 2 "general_operand" "g"))
1331: (match_operand:SI 3 "general_operand" "g")))]
1332: ""
1333: "cmpv %2,%1,%0,%3")
1334:
1335: (define_insn ""
1336: [(set (cc0)
1337: (minus
1338: (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1339: (match_operand:SI 1 "general_operand" "g")
1340: (match_operand:SI 2 "general_operand" "g"))
1341: (match_operand:SI 3 "general_operand" "g")))]
1342: ""
1343: "cmpzv %2,%1,%0,%3")
1344:
1345: (define_insn "extv"
1.1 root 1346: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1347: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1.1 root 1348: (match_operand:SI 2 "general_operand" "g")
1349: (match_operand:SI 3 "general_operand" "g")))]
1350: ""
1351: "extv %3,%2,%1,%0")
1352:
1.1.1.4 root 1353: (define_insn "extzv"
1.1 root 1354: [(set (match_operand:SI 0 "general_operand" "=g")
1.1.1.4 root 1355: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "rm")
1.1 root 1356: (match_operand:SI 2 "general_operand" "g")
1357: (match_operand:SI 3 "general_operand" "g")))]
1358: ""
1359: "extzv %3,%2,%1,%0")
1360:
1361: (define_insn "insv"
1.1.1.2 root 1362: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1.1 root 1363: (match_operand:SI 1 "general_operand" "g")
1364: (match_operand:SI 2 "general_operand" "g"))
1365: (match_operand:SI 3 "general_operand" "g"))]
1366: ""
1367: "insv %3,%2,%1,%0")
1368:
1369: (define_insn ""
1.1.1.2 root 1370: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1.1 root 1371: (match_operand:SI 1 "general_operand" "g")
1372: (match_operand:SI 2 "general_operand" "g"))
1373: (match_operand:SI 3 "general_operand" "g"))]
1374: ""
1375: "insv %3,%2,%1,%0")
1376:
1377: (define_insn "jump"
1378: [(set (pc)
1379: (label_ref (match_operand 0 "" "")))]
1380: ""
1381: "jbr %l0")
1382:
1383: (define_insn "beq"
1384: [(set (pc)
1385: (if_then_else (eq (cc0)
1386: (const_int 0))
1387: (label_ref (match_operand 0 "" ""))
1388: (pc)))]
1389: ""
1390: "jeql %l0")
1391:
1392: (define_insn "bne"
1393: [(set (pc)
1394: (if_then_else (ne (cc0)
1395: (const_int 0))
1396: (label_ref (match_operand 0 "" ""))
1397: (pc)))]
1398: ""
1399: "jneq %l0")
1400:
1401: (define_insn "bgt"
1402: [(set (pc)
1403: (if_then_else (gt (cc0)
1404: (const_int 0))
1405: (label_ref (match_operand 0 "" ""))
1406: (pc)))]
1407: ""
1408: "jgtr %l0")
1409:
1410: (define_insn "bgtu"
1411: [(set (pc)
1412: (if_then_else (gtu (cc0)
1413: (const_int 0))
1414: (label_ref (match_operand 0 "" ""))
1415: (pc)))]
1416: ""
1417: "jgtru %l0")
1418:
1419: (define_insn "blt"
1420: [(set (pc)
1421: (if_then_else (lt (cc0)
1422: (const_int 0))
1423: (label_ref (match_operand 0 "" ""))
1424: (pc)))]
1425: ""
1426: "jlss %l0")
1427:
1428: (define_insn "bltu"
1429: [(set (pc)
1430: (if_then_else (ltu (cc0)
1431: (const_int 0))
1432: (label_ref (match_operand 0 "" ""))
1433: (pc)))]
1434: ""
1435: "jlssu %l0")
1436:
1437: (define_insn "bge"
1438: [(set (pc)
1439: (if_then_else (ge (cc0)
1440: (const_int 0))
1441: (label_ref (match_operand 0 "" ""))
1442: (pc)))]
1443: ""
1444: "jgeq %l0")
1445:
1446: (define_insn "bgeu"
1447: [(set (pc)
1448: (if_then_else (geu (cc0)
1449: (const_int 0))
1450: (label_ref (match_operand 0 "" ""))
1451: (pc)))]
1452: ""
1453: "jgequ %l0")
1454:
1455: (define_insn "ble"
1456: [(set (pc)
1457: (if_then_else (le (cc0)
1458: (const_int 0))
1459: (label_ref (match_operand 0 "" ""))
1460: (pc)))]
1461: ""
1462: "jleq %l0")
1463:
1464: (define_insn "bleu"
1465: [(set (pc)
1466: (if_then_else (leu (cc0)
1467: (const_int 0))
1468: (label_ref (match_operand 0 "" ""))
1469: (pc)))]
1470: ""
1471: "jlequ %l0")
1472:
1473: (define_insn ""
1474: [(set (pc)
1475: (if_then_else (eq (cc0)
1476: (const_int 0))
1477: (pc)
1478: (label_ref (match_operand 0 "" ""))))]
1479: ""
1480: "jneq %l0")
1481:
1482: (define_insn ""
1483: [(set (pc)
1484: (if_then_else (ne (cc0)
1485: (const_int 0))
1486: (pc)
1487: (label_ref (match_operand 0 "" ""))))]
1488: ""
1489: "jeql %l0")
1490:
1491: (define_insn ""
1492: [(set (pc)
1493: (if_then_else (gt (cc0)
1494: (const_int 0))
1495: (pc)
1496: (label_ref (match_operand 0 "" ""))))]
1497: ""
1498: "jleq %l0")
1499:
1500: (define_insn ""
1501: [(set (pc)
1502: (if_then_else (gtu (cc0)
1503: (const_int 0))
1504: (pc)
1505: (label_ref (match_operand 0 "" ""))))]
1506: ""
1507: "jlequ %l0")
1508:
1509: (define_insn ""
1510: [(set (pc)
1511: (if_then_else (lt (cc0)
1512: (const_int 0))
1513: (pc)
1514: (label_ref (match_operand 0 "" ""))))]
1515: ""
1516: "jgeq %l0")
1517:
1518: (define_insn ""
1519: [(set (pc)
1520: (if_then_else (ltu (cc0)
1521: (const_int 0))
1522: (pc)
1523: (label_ref (match_operand 0 "" ""))))]
1524: ""
1525: "jgequ %l0")
1526:
1527: (define_insn ""
1528: [(set (pc)
1529: (if_then_else (ge (cc0)
1530: (const_int 0))
1531: (pc)
1532: (label_ref (match_operand 0 "" ""))))]
1533: ""
1534: "jlss %l0")
1535:
1536: (define_insn ""
1537: [(set (pc)
1538: (if_then_else (geu (cc0)
1539: (const_int 0))
1540: (pc)
1541: (label_ref (match_operand 0 "" ""))))]
1542: ""
1543: "jlssu %l0")
1544:
1545: (define_insn ""
1546: [(set (pc)
1547: (if_then_else (le (cc0)
1548: (const_int 0))
1549: (pc)
1550: (label_ref (match_operand 0 "" ""))))]
1551: ""
1552: "jgtr %l0")
1553:
1554: (define_insn ""
1555: [(set (pc)
1556: (if_then_else (leu (cc0)
1557: (const_int 0))
1558: (pc)
1559: (label_ref (match_operand 0 "" ""))))]
1560: ""
1561: "jgtru %l0")
1562:
1563: ;; Recognize jbs and jbc instructions.
1564:
1565: (define_insn ""
1566: [(set (pc)
1567: (if_then_else
1568: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1569: (const_int 1)
1570: (match_operand:SI 1 "general_operand" "g"))
1571: (const_int 0))
1572: (label_ref (match_operand 2 "" ""))
1573: (pc)))]
1574: ""
1575: "jbs %1,%0,%l2")
1576:
1577: (define_insn ""
1578: [(set (pc)
1579: (if_then_else
1580: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1581: (const_int 1)
1582: (match_operand:SI 1 "general_operand" "g"))
1583: (const_int 0))
1584: (label_ref (match_operand 2 "" ""))
1585: (pc)))]
1586: ""
1587: "jbc %1,%0,%l2")
1588:
1589: (define_insn ""
1590: [(set (pc)
1591: (if_then_else
1592: (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1593: (const_int 1)
1594: (match_operand:SI 1 "general_operand" "g"))
1595: (const_int 0))
1596: (pc)
1597: (label_ref (match_operand 2 "" ""))))]
1598: ""
1599: "jbc %1,%0,%l2")
1600:
1601: (define_insn ""
1602: [(set (pc)
1603: (if_then_else
1604: (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")
1605: (const_int 1)
1606: (match_operand:SI 1 "general_operand" "g"))
1607: (const_int 0))
1608: (pc)
1609: (label_ref (match_operand 2 "" ""))))]
1610: ""
1611: "jbs %1,%0,%l2")
1612:
1613: (define_insn ""
1614: [(set (pc)
1615: (if_then_else
1616: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1617: (const_int 1)
1618: (match_operand:SI 1 "general_operand" "g"))
1619: (const_int 0))
1620: (label_ref (match_operand 2 "" ""))
1621: (pc)))]
1.1.1.2 root 1622: "GET_CODE (operands[0]) != MEM
1623: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1624: "jbs %1,%0,%l2")
1625:
1626: (define_insn ""
1627: [(set (pc)
1628: (if_then_else
1629: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1630: (const_int 1)
1631: (match_operand:SI 1 "general_operand" "g"))
1632: (const_int 0))
1633: (label_ref (match_operand 2 "" ""))
1634: (pc)))]
1.1.1.2 root 1635: "GET_CODE (operands[0]) != MEM
1636: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1637: "jbc %1,%0,%l2")
1638:
1639: (define_insn ""
1640: [(set (pc)
1641: (if_then_else
1.1.1.2 root 1642: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1643: (match_operand:SI 1 "general_operand" "g"))
1644: (const_int 0))
1645: (pc)
1646: (label_ref (match_operand 2 "" ""))))]
1647: "GET_CODE (operands[1]) == CONST_INT
1648: && exact_log2 (INTVAL (operands[1])) >= 0
1649: && (GET_CODE (operands[0]) != MEM
1650: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1651: "*
1652: {
1653: operands[1]
1654: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1655: return \"jbs %1,%0,%l2\";
1656: }")
1657:
1658: (define_insn ""
1659: [(set (pc)
1660: (if_then_else
1661: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1662: (match_operand:SI 1 "general_operand" "g"))
1663: (const_int 0))
1664: (label_ref (match_operand 2 "" ""))
1665: (pc)))]
1666: "GET_CODE (operands[1]) == CONST_INT
1667: && exact_log2 (INTVAL (operands[1])) >= 0
1668: && (GET_CODE (operands[0]) != MEM
1669: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1670: "*
1671: {
1672: operands[1]
1673: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1674: return \"jbc %1,%0,%l2\";
1675: }")
1676:
1677: (define_insn ""
1678: [(set (pc)
1679: (if_then_else
1680: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1681: (match_operand:SI 1 "general_operand" "g"))
1682: (const_int 0))
1683: (pc)
1684: (label_ref (match_operand 2 "" ""))))]
1685: "GET_CODE (operands[1]) == CONST_INT
1686: && exact_log2 (INTVAL (operands[1])) >= 0
1687: && (GET_CODE (operands[0]) != MEM
1688: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1689: "*
1690: {
1691: operands[1]
1692: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1693: return \"jbc %1,%0,%l2\";
1694: }")
1695:
1696: (define_insn ""
1697: [(set (pc)
1698: (if_then_else
1699: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1700: (match_operand:SI 1 "general_operand" "g"))
1701: (const_int 0))
1702: (label_ref (match_operand 2 "" ""))
1703: (pc)))]
1704: "GET_CODE (operands[1]) == CONST_INT
1705: && exact_log2 (INTVAL (operands[1])) >= 0
1706: && (GET_CODE (operands[0]) != MEM
1707: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1708: "*
1709: {
1710: operands[1]
1711: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1712: return \"jbs %1,%0,%l2\";
1713: }")
1714:
1715: (define_insn ""
1716: [(set (pc)
1717: (if_then_else
1.1 root 1718: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1719: (const_int 1)
1720: (match_operand:SI 1 "general_operand" "g"))
1721: (const_int 0))
1722: (pc)
1723: (label_ref (match_operand 2 "" ""))))]
1.1.1.2 root 1724: "GET_CODE (operands[0]) != MEM
1725: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1726: "jbc %1,%0,%l2")
1727:
1728: (define_insn ""
1729: [(set (pc)
1730: (if_then_else
1731: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
1732: (const_int 1)
1733: (match_operand:SI 1 "general_operand" "g"))
1734: (const_int 0))
1735: (pc)
1736: (label_ref (match_operand 2 "" ""))))]
1.1.1.2 root 1737: "GET_CODE (operands[0]) != MEM
1738: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1739: "jbs %1,%0,%l2")
1740:
1741: (define_insn ""
1742: [(set (pc)
1743: (if_then_else
1744: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1745: (const_int 1))
1746: (const_int 0))
1747: (label_ref (match_operand 1 "" ""))
1748: (pc)))]
1.1.1.2 root 1749: "GET_CODE (operands[0]) != MEM
1750: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1751: "jlbs %0,%l1")
1752:
1753: (define_insn ""
1754: [(set (pc)
1755: (if_then_else
1756: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1757: (const_int 1))
1758: (const_int 0))
1759: (label_ref (match_operand 1 "" ""))
1760: (pc)))]
1.1.1.2 root 1761: "GET_CODE (operands[0]) != MEM
1762: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1763: "jlbc %0,%l1")
1764:
1765: (define_insn ""
1766: [(set (pc)
1767: (if_then_else
1768: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1769: (const_int 1))
1770: (const_int 0))
1771: (pc)
1772: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1773: "GET_CODE (operands[0]) != MEM
1774: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1775: "jlbc %0,%l1")
1776:
1777: (define_insn ""
1778: [(set (pc)
1779: (if_then_else
1780: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1781: (const_int 1))
1782: (const_int 0))
1783: (pc)
1784: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1785: "GET_CODE (operands[0]) != MEM
1786: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1787: "jlbs %0,%l1")
1788:
1789: ;; These four entries allow a jlbc or jlbs to be made
1790: ;; by combination with a bic.
1791: (define_insn ""
1792: [(set (pc)
1793: (if_then_else
1794: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1795: (not:SI (const_int -2)))
1796: (const_int 0))
1797: (label_ref (match_operand 1 "" ""))
1798: (pc)))]
1.1.1.2 root 1799: "GET_CODE (operands[0]) != MEM
1800: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1801: "jlbs %0,%l1")
1802:
1803: (define_insn ""
1804: [(set (pc)
1805: (if_then_else
1806: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1807: (not:SI (const_int -2)))
1808: (const_int 0))
1809: (label_ref (match_operand 1 "" ""))
1810: (pc)))]
1.1.1.2 root 1811: "GET_CODE (operands[0]) != MEM
1812: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1813: "jlbc %0,%l1")
1814:
1815: (define_insn ""
1816: [(set (pc)
1817: (if_then_else
1818: (ne (and:SI (match_operand:SI 0 "general_operand" "g")
1819: (not:SI (const_int -2)))
1820: (const_int 0))
1821: (pc)
1822: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1823: "GET_CODE (operands[0]) != MEM
1824: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1825: "jlbc %0,%l1")
1826:
1827: (define_insn ""
1828: [(set (pc)
1829: (if_then_else
1830: (eq (and:SI (match_operand:SI 0 "general_operand" "g")
1831: (not:SI (const_int -2)))
1832: (const_int 0))
1833: (pc)
1834: (label_ref (match_operand 1 "" ""))))]
1.1.1.2 root 1835: "GET_CODE (operands[0]) != MEM
1836: || ! mode_dependent_address_p (XEXP (operands[0], 0))"
1.1 root 1837: "jlbs %0,%l1")
1838:
1839: ;; Subtract-and-jump and Add-and-jump insns.
1840: ;; These are not used when output is for the Unix assembler
1841: ;; because it does not know how to modify them to reach far.
1842:
1843: ;; Normal sob insns.
1844:
1845: (define_insn ""
1846: [(set (pc)
1847: (if_then_else
1.1.1.8 ! root 1848: (gt (plus:SI (match_operand:SI 0 "general_operand" "+g")
! 1849: (const_int -1))
1.1 root 1850: (const_int 0))
1851: (label_ref (match_operand 1 "" ""))
1852: (pc)))
1853: (set (match_dup 0)
1.1.1.2 root 1854: (plus:SI (match_dup 0)
1855: (const_int -1)))]
1.1 root 1856: "!TARGET_UNIX_ASM"
1857: "jsobgtr %0,%l1")
1858:
1859: (define_insn ""
1860: [(set (pc)
1861: (if_then_else
1.1.1.8 ! root 1862: (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")
! 1863: (const_int -1))
1.1 root 1864: (const_int 0))
1865: (label_ref (match_operand 1 "" ""))
1866: (pc)))
1867: (set (match_dup 0)
1.1.1.2 root 1868: (plus:SI (match_dup 0)
1869: (const_int -1)))]
1.1 root 1870: "!TARGET_UNIX_ASM"
1871: "jsobgeq %0,%l1")
1872:
1873: ;; Reversed sob insns.
1874:
1875: (define_insn ""
1876: [(set (pc)
1877: (if_then_else
1.1.1.8 ! root 1878: (le (plus:SI (match_operand:SI 0 "general_operand" "+g")
! 1879: (const_int -1))
1.1 root 1880: (const_int 0))
1881: (pc)
1882: (label_ref (match_operand 1 "" ""))))
1883: (set (match_dup 0)
1.1.1.2 root 1884: (plus:SI (match_dup 0)
1885: (const_int -1)))]
1.1 root 1886: "!TARGET_UNIX_ASM"
1887: "jsobgtr %0,%l1")
1888:
1889: (define_insn ""
1890: [(set (pc)
1891: (if_then_else
1.1.1.8 ! root 1892: (lt (plus:SI (match_operand:SI 0 "general_operand" "+g")
! 1893: (const_int -1))
1.1 root 1894: (const_int 0))
1895: (pc)
1896: (label_ref (match_operand 1 "" ""))))
1897: (set (match_dup 0)
1.1.1.2 root 1898: (plus:SI (match_dup 0)
1899: (const_int -1)))]
1.1 root 1900: "!TARGET_UNIX_ASM"
1901: "jsobgeq %0,%l1")
1902:
1903: ;; Normal aob insns.
1904: (define_insn ""
1905: [(set (pc)
1906: (if_then_else
1907: (lt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1908: (const_int 1))
1909: (match_operand:SI 1 "general_operand" "g"))
1910: (const_int 0))
1911: (label_ref (match_operand 2 "" ""))
1912: (pc)))
1913: (set (match_dup 0)
1914: (plus:SI (match_dup 0)
1915: (const_int 1)))]
1916: "!TARGET_UNIX_ASM"
1917: "jaoblss %1,%0,%l2")
1918:
1919: (define_insn ""
1920: [(set (pc)
1921: (if_then_else
1922: (le (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1923: (const_int 1))
1924: (match_operand:SI 1 "general_operand" "g"))
1925: (const_int 0))
1926: (label_ref (match_operand 2 "" ""))
1927: (pc)))
1928: (set (match_dup 0)
1929: (plus:SI (match_dup 0)
1930: (const_int 1)))]
1931: "!TARGET_UNIX_ASM"
1932: "jaobleq %1,%0,%l2")
1933:
1934: ;; Reverse aob insns.
1935: (define_insn ""
1936: [(set (pc)
1937: (if_then_else
1938: (ge (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1939: (const_int 1))
1940: (match_operand:SI 1 "general_operand" "g"))
1941: (const_int 0))
1942: (pc)
1943: (label_ref (match_operand 2 "" ""))))
1944: (set (match_dup 0)
1945: (plus:SI (match_dup 0)
1946: (const_int 1)))]
1947: "!TARGET_UNIX_ASM"
1948: "jaoblss %1,%0,%l2")
1949:
1950: (define_insn ""
1951: [(set (pc)
1952: (if_then_else
1953: (gt (minus (plus:SI (match_operand:SI 0 "general_operand" "+g")
1954: (const_int 1))
1955: (match_operand:SI 1 "general_operand" "g"))
1956: (const_int 0))
1957: (pc)
1958: (label_ref (match_operand 2 "" ""))))
1959: (set (match_dup 0)
1960: (plus:SI (match_dup 0)
1961: (const_int 1)))]
1962: "!TARGET_UNIX_ASM"
1963: "jaobleq %1,%0,%l2")
1.1.1.5 root 1964:
1965: ;; Something like a sob insn, but compares against -1.
1966: ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1967:
1968: (define_insn ""
1969: [(set (pc)
1970: (if_then_else
1971: (ne (minus (plus:SI (match_operand:SI 0 "general_operand" "g")
1972: (const_int -1))
1973: (const_int -1))
1974: (const_int 0))
1975: (label_ref (match_operand 1 "" ""))
1976: (pc)))
1977: (set (match_dup 0)
1978: (plus:SI (match_dup 0)
1979: (const_int -1)))]
1980: ""
1981: "decl %0\;jgequ %l1")
1.1 root 1982:
1.1.1.2 root 1983: ;; Note that operand 1 is total size of args, in bytes,
1984: ;; and what the call insn wants is the number of words.
1.1 root 1985: (define_insn "call"
1986: [(call (match_operand:QI 0 "general_operand" "g")
1987: (match_operand:QI 1 "general_operand" "g"))]
1988: ""
1.1.1.2 root 1989: "*
1.1.1.5 root 1990: if (INTVAL (operands[1]) > 255 * 4)
1991: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
1992: return \"calls $0,%0\;addl2 %1,sp\";
1.1.1.2 root 1993: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);
1994: return \"calls %1,%0\";
1995: ")
1996:
1997: (define_insn "call_value"
1998: [(set (match_operand 0 "" "g")
1999: (call (match_operand:QI 1 "general_operand" "g")
2000: (match_operand:QI 2 "general_operand" "g")))]
2001: ""
2002: "*
1.1.1.7 root 2003: if (INTVAL (operands[2]) > 255 * 4)
1.1.1.6 root 2004: /* Vax `calls' really uses only one byte of #args, so pop explicitly. */
2005: return \"calls $0,%1\;addl2 %2,sp\";
1.1.1.2 root 2006: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4);
2007: return \"calls %2,%1\";
2008: ")
1.1 root 2009:
2010: (define_insn "return"
2011: [(return)]
2012: ""
2013: "ret")
2014:
2015: (define_insn "casesi"
2016: [(set (pc)
2017: (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
2018: (match_operand:SI 1 "general_operand" "g"))
2019: (match_operand:SI 2 "general_operand" "g"))
1.1.1.2 root 2020: (plus:SI (sign_extend:SI
1.1 root 2021: (mem:HI (plus:SI (pc)
2022: (minus:SI (match_dup 0)
1.1.1.2 root 2023: (match_dup 1)))))
2024: (label_ref:SI (match_operand 3 "" "")))
1.1 root 2025: (pc)))]
2026: ""
2027: "casel %0,%1,%2")
2028:
1.1.1.2 root 2029: ;; This used to arise from the preceding by simplification
2030: ;; if operand 1 is zero. Perhaps it is no longer necessary.
2031: (define_insn ""
2032: [(set (pc)
2033: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
2034: (match_operand:SI 1 "general_operand" "g"))
2035: (plus:SI (sign_extend:SI
2036: (mem:HI (plus:SI (pc)
2037: (minus:SI (match_dup 0)
2038: (const_int 0)))))
2039: (label_ref:SI (match_operand 3 "" "")))
2040: (pc)))]
2041: ""
2042: "casel %0,$0,%1")
2043:
1.1 root 2044: ;; This arises from the preceding by simplification if operand 1 is zero.
2045: (define_insn ""
2046: [(set (pc)
2047: (if_then_else (le (match_operand:SI 0 "general_operand" "g")
2048: (match_operand:SI 1 "general_operand" "g"))
1.1.1.2 root 2049: (plus:SI (sign_extend:SI
1.1 root 2050: (mem:HI (plus:SI (pc)
1.1.1.2 root 2051: (match_dup 0))))
2052: (label_ref:SI (match_operand 3 "" "")))
1.1 root 2053: (pc)))]
2054: ""
2055: "casel %0,$0,%1")
2056:
1.1.1.2 root 2057: ;; Optimize extzv ...,z; andl2 ...,z
2058: ;; with other operands constant.
2059: (define_peephole
2060: [(set (match_operand:SI 0 "general_operand" "g")
2061: (zero_extract:SI (match_operand:SI 1 "general_operand" "g")
2062: (match_operand:SI 2 "general_operand" "g")
2063: (match_operand:SI 3 "general_operand" "g")))
2064: (set (match_operand:SI 4 "general_operand" "g")
2065: (and:SI (match_dup 0)
2066: (match_operand:SI 5 "general_operand" "g")))]
2067: "GET_CODE (operands[2]) == CONST_INT
2068: && GET_CODE (operands[3]) == CONST_INT
2069: && (INTVAL (operands[2]) + INTVAL (operands[3])) == 32
2070: && GET_CODE (operands[5]) == CONST_INT
2071: && dead_or_set_p (insn, operands[0])"
2072: "*
2073: {
2074: unsigned long mask = INTVAL (operands[5]);
2075: operands[3] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[3]));
2076:
2077: if ((floor_log2 (mask) + 1) >= INTVAL (operands[2]))
2078: mask &= ((1 << INTVAL (operands[2])) - 1);
2079:
2080: operands[5] = gen_rtx (CONST_INT, VOIDmode, ~mask);
2081: if (push_operand (operands[4], SImode))
2082: {
2083: output_asm_insn (\"rotl %3,%1,%0\", operands);
2084: return \"bicl3 %5,%0,%4\";
2085: }
2086: else
2087: {
2088: output_asm_insn (\"rotl %3,%1,%4\", operands);
2089: return \"bicl2 %5,%4\";
2090: }
2091: }")
2092:
2093: ;; Optimize andl3 x,y,z; extzv z,....,z
2094:
2095: (define_peephole
2096: [(set (match_operand:SI 0 "general_operand" "g")
2097: (and:SI (match_operand:SI 1 "general_operand" "g")
2098: (match_operand:SI 2 "general_operand" "g")))
2099: (set (match_operand 3 "general_operand" "g")
2100: (zero_extract:SI (match_dup 0)
2101: (match_operand:SI 4 "general_operand" "g")
2102: (match_operand:SI 5 "general_operand" "g")))]
2103: "GET_CODE (operands[2]) == CONST_INT
2104: && GET_CODE (operands[4]) == CONST_INT
2105: && GET_CODE (operands[5]) == CONST_INT
2106: && (INTVAL (operands[4]) + INTVAL (operands[5])) == 32
2107: && dead_or_set_p (insn, operands[0])"
2108: "*
2109: {
2110: unsigned long mask = INTVAL (operands[2]);
2111:
2112: mask &= ~((1 << INTVAL (operands[5])) - 1);
2113: operands[2] = gen_rtx (CONST_INT, VOIDmode, ~mask);
2114:
2115: operands[5] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[5]));
2116:
2117: if (rtx_equal_p (operands[0], operands[1]))
2118: output_asm_insn (\"bicl2 %2,%0\", operands);
2119: else
2120: output_asm_insn (\"bicl3 %2,%1,%0\", operands);
2121: return \"rotl %5,%0,%3\";
2122: }")
2123:
1.1 root 2124: ;;- Local variables:
2125: ;;- mode:emacs-lisp
2126: ;;- comment-start: ";;- "
2127: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2128: ;;- eval: (modify-syntax-entry ?[ "(]")
2129: ;;- eval: (modify-syntax-entry ?] ")[")
2130: ;;- eval: (modify-syntax-entry ?{ "(}")
2131: ;;- eval: (modify-syntax-entry ?} "){")
2132: ;;- End:
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