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Annotation of gcl520h/_8250.h, revision 1.1.1.1

1.1       root        1: #ifndef __8250_DOT_H
                      2: #define __8250_DOT_H
                      3: 
                      4: /*
                      5:  * _8250.H            5.20A  June 8, 1995
                      6:  *
                      7:  * This private header file has all of the 8250 UART register names
                      8:  * and bit field definitions.  This file is generally only needed to
                      9:  * rebuild the library.
                     10:  *
                     11:  *  The Greenleaf Comm Library
                     12:  *
                     13:  *  Copyright (C) 1991-1995 Greenleaf Software Inc.  All Rights Reserved.
                     14:  *
                     15:  * NOTES
                     16:  *
                     17:  * This private header file has all of the 8250 UART register names
                     18:  * and bit field definitions.  This file is generally only needed to
                     19:  * rebuild the library, not for inclusion in an end user module.  Note
                     20:  * that assembly language modules can get this stuff from _8250.EQU.
                     21:  *
                     22:  * MODIFICATIONS
                     23:  *
                     24:  *  December 12, 1992  4.00A : Initial release
                     25:  */
                     26: 
                     27: #define TRANSMIT_HOLDING_REGISTER          0
                     28: #define RECEIVE_BUFFER_REGISTER            0
                     29: #define DIVISOR_LATCH_LSB                  0
                     30: #define DIVISOR_LATCH_MSB                  1
                     31: #define INTERRUPT_ENABLE_REGISTER          1
                     32: #define   IER_RECEIVE_DATA_INTERRUPT       0x01
                     33: #define   IER_TRANSMIT_DATA_INTERRUPT      0x02
                     34: #define   IER_LINE_STATUS_INTERRUPT        0x04
                     35: #define   IER_MODEM_STATUS_INTERRUPT       0x08
                     36: #define INTERRUPT_ID_REGISTER              2
                     37: #define   IID_FIFO_ENABLED_MASK            0xc0
                     38: #define FIFO_CONTROL_REGISTER              2
                     39: #define   FCR_FIFO_ENABLE                  0x01
                     40: #define   FCR_RCVR_FIFO_RESET              0x02
                     41: #define   FCR_XMIT_FIFO_RESET              0x04
                     42: #define   FCR_DMA_MODE_SELECT              0x08
                     43: #define   FCR_RCVR_TRIGGER_LSB             0x40
                     44: #define   FCR_RCVR_TRIGGER_MSB             0x80
                     45: #define LINE_CONTROL_REGISTER              3
                     46: #define   LCR_WORD_LENGTH_SELECT_BITS      0x03
                     47: #define     LCR_WORD_LENGTH_SELECT_BIT_0   0x01
                     48: #define     LCR_WORD_LENGTH_SELECT_BIT_1   0x02
                     49: #define       LCR_WORD_LENGTH_5            0x00
                     50: #define       LCR_WORD_LENGTH_6            0x01
                     51: #define       LCR_WORD_LENGTH_7            0x02
                     52: #define       LCR_WORD_LENGTH_8            0x03
                     53: #define   LCR_NUMBER_OF_STOP_BITS          0x04
                     54: #define   LCR_PARITY_BITS                  0x38
                     55: #define     LCR_PARITY_ENABLE              0x08
                     56: #define     LCR_EVEN_PARITY_SELECT         0x10
                     57: #define     LCR_STICK_PARITY               0x20
                     58: #define       LCR_PARITY_N                 0x00
                     59: #define       LCR_PARITY_O                 0x08
                     60: #define       LCR_PARITY_E                 0x18
                     61: #define       LCR_PARITY_S                 0x38
                     62: #define       LCR_PARITY_M                 0x28
                     63: #define   LCR_SET_BREAK                    0x40
                     64: #define   LCR_DIVISOR_LATCH_ACCESS         0x80
                     65: #define MODEM_CONTROL_REGISTER             4
                     66: #define   MCR_DATA_TERMINAL_READY          0x01
                     67: #define   MCR_REQUEST_TO_SEND              0x02
                     68: #define   MCR_OUT1                         0x04
                     69: #define   MCR_OUT2                         0x08
                     70: #define   MCR_LOOPBACK                     0x10
                     71: #define LINE_STATUS_REGISTER               5
                     72: #define   LSR_DATA_READY                   0x01
                     73: #define   LSR_OVERRUN_ERROR                0x02
                     74: #define   LSR_PARITY_ERROR                 0x04
                     75: #define   LSR_FRAMING_ERROR                0x08
                     76: #define   LSR_BREAK_INTERRUPT              0x10
                     77: #define   LSR_THRE                         0x20
                     78: #define   LSR_TEMT                         0x40
                     79: #define   LSR_FIFO_ERROR                   0x80
                     80: #define MODEM_STATUS_REGISTER              6
                     81: #define   MSR_DELTA_CTS                    0x01
                     82: #define   MSR_DELTA_DSR                    0x02
                     83: #define   MSR_TRAILING_EDGE_RI             0x04
                     84: #define   MSR_DELTA_CD                     0x08
                     85: #define   MSR_CTS                          0x10
                     86: #define   MSR_DSR                          0x20
                     87: #define   MSR_RI                           0x40
                     88: #define   MSR_CD                           0x80
                     89: #define SCRATCH_REGISTER                   7
                     90: 
                     91: #endif    /* #ifndef __8250_DOT_H  */
                     92: 

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