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1.1 root 1: /* z80stb.c
2: * Zilog Z80 processor emulator in C. Modified to be API compliant with Neil
3: * Bradley's MZ80 (for ported projects)
4: * Ported to 'C' by Jeff Mitchell; original copyright follows:
5: *
6: * Abstract:
7: * Internal declarations for Zilog Z80 emulator.
8: *
9: * Revisions:
10: * 18-Apr-97 EAM Created
11: * ??-???-97 EAM Released in MageX 0.5
12: * 26-Jul-97 EAM Fixed Time Pilot slowdown bug and
13: * Gyruss hiscore bugs (opcode 0xC3)
14: *
15: * Original copyright (C) 1997 Edward Massey
16: */
17:
18: #define FALSE 0
19: #define TRUE 1
20:
21: #ifdef WORDS_BIGENDIAN
22: #define HOST_TO_LE16(y) ((((y>>8)&0x00FF)+((((y)<<8)&0xFF00)))
23: #else
24: #define HOST_TO_LE16(y) (y)
25: #endif
26:
27: #include <stdio.h>
28: #include <stdlib.h>
29: #include <assert.h>
30: #include "cmz80.h"
31: #include "z80stb.h"
32:
33: /* ***************************************************************************
34: * Edward's Internals (so to speak)
35: * ***************************************************************************
36: */
37:
38: #define _ASSERT assert
39:
40: union { /* WARN: Endianness! */
41: WORD m_regAF;
42: struct {
43: #ifdef WORDS_BIGENDIAN
44: BYTE m_regA;
45: BYTE m_regF;
46: #else
47: BYTE m_regF;
48: BYTE m_regA;
49: #endif
50: } regAFs;
51: } regAF;
52: #define m_regAF regAF.m_regAF
53: #define m_regF regAF.regAFs.m_regF
54: #define m_regA regAF.regAFs.m_regA
55:
56: union { /* WARN: Endianness! */
57: WORD m_regBC;
58: struct {
59: #ifdef WORDS_BIGENDIAN
60: BYTE m_regB;
61: BYTE m_regC;
62: #else
63: BYTE m_regC;
64: BYTE m_regB;
65: #endif
66: } regBCs;
67: } regBC;
68: #define m_regBC regBC.m_regBC
69: #define m_regB regBC.regBCs.m_regB
70: #define m_regC regBC.regBCs.m_regC
71:
72: union { /* WARN: Endianness! */
73: WORD m_regDE;
74: struct {
75: #ifdef WORDS_BIGENDIAN
76: BYTE m_regD;
77: BYTE m_regE;
78: #else
79: BYTE m_regE;
80: BYTE m_regD;
81: #endif
82: } regDEs;
83: } regDE;
84: #define m_regDE regDE.m_regDE
85: #define m_regD regDE.regDEs.m_regD
86: #define m_regE regDE.regDEs.m_regE
87:
88: union { /* WARN: Endianness! */
89: WORD m_regHL;
90: struct {
91: #ifdef WORDS_BIGENDIAN
92: BYTE m_regH;
93: BYTE m_regL;
94: #else
95: BYTE m_regL;
96: BYTE m_regH;
97: #endif
98: } regHLs;
99: } regHL;
100: #define m_regHL regHL.m_regHL
101: #define m_regH regHL.regHLs.m_regH
102: #define m_regL regHL.regHLs.m_regL
103:
104: union { /* WARN: Endianness! */
105: WORD m_regIX;
106: struct {
107: #ifdef WORDS_BIGENDIAN
108: BYTE m_regIXh;
109: BYTE m_regIXl;
110: #else
111: BYTE m_regIXl;
112: BYTE m_regIXh;
113: #endif
114: } regIXs;
115: } regIX;
116: #define m_regIX regIX.m_regIX
117: #define m_regIXl regIX.regIXs.m_regIXl
118: #define m_regIXh regIX.regIXs.m_regIXh
119:
120: union {
121: WORD m_regIY;
122: struct {
123: #ifdef WORDS_BIGENDIAN
124: BYTE m_regIYh;
125: BYTE m_regIYl;
126: #else
127: BYTE m_regIYl;
128: BYTE m_regIYh;
129: #endif
130: } regIYs;
131: } regIY;
132: #define m_regIY regIY.m_regIY
133: #define m_regIYl regIY.regIYs.m_regIYl
134: #define m_regIYh regIY.regIYs.m_regIYh
135:
136: const BYTE *m_rgbOpcode; // takes place of the PC register
137: LPBYTE m_rgbStack; // takes place of the SP register
138: LPBYTE m_rgbMemory; // direct access to memory buffer (RAM)
139: const BYTE *m_rgbOpcodeBase; // "base" pointer for m_rgbOpcode
140: LPBYTE m_rgbStackBase;
141: static int cCycles = 0;
142:
143: BYTE m_regR; // consider: should be int for performance?
144: BYTE m_regI; // consider: combine into
145:
146: // TODO: combine into a single int...
147: int m_iff1, m_iff2;
148: BOOL m_fHalt;
149: int m_nIM;
150: BOOL m_fPendingInterrupt = FALSE;
151:
152: WORD m_regAF2;
153: static WORD m_regBC2;
154: static WORD m_regDE2;
155: static WORD m_regHL2;
156: WORD z80intAddr = 0x38;
157: WORD z80nmiAddr = 0x66;
158:
159: /* ***************************************************************************
160: * Pre-calculated math tables and junk (sucked from Marat and Edward)
161: * ***************************************************************************
162: */
163: void InitTables (void);
164:
165: BYTE ZSTable[256];
166: BYTE ZSPTable[256];
167: BYTE rgfAdd[256][256];
168: BYTE rgfSub[256][256];
169: BYTE rgfAddc[256][256][2];
170: BYTE rgfSubc[256][256][2];
171: BYTE rgfInc[256];
172: BYTE rgfDec[256];
173: BYTE rgfBit[256][8];
174: static UINT32 dwElapsedTicks = 0;
175:
176: /* #include "z80daa.h" */
177: #include "z80stbd.h"
178:
179: /* ***************************************************************************
180: * Retrocade guts stuff
181: * ***************************************************************************
182: */
183: static struct MemoryReadByte *z80MemoryRead = NULL;
184: static struct MemoryWriteByte *z80MemoryWrite = NULL;
185: static struct z80PortRead *z80IoRead = NULL;
186: static struct z80PortWrite *z80IoWrite = NULL;
187: WORD z80pc = 0;
188:
189: /* ***************************************************************************
190: * Retrocade interface follows
191: * ***************************************************************************
192: */
193:
194: /* reset registers, interrupts, memory read/write memory handlers,
195: * port read and writing handlers, etc.
196: */
197: void mz80reset(void) {
198:
199: InitTables();
200:
201: m_fPendingInterrupt = FALSE;
202: m_rgbOpcodeBase = m_rgbMemory;
203: /* m_rgbMemory = */
204: m_rgbStackBase = m_rgbMemory;
205:
206: m_regAF = 0;
207: m_regBC = 0;
208: m_regDE = 0;
209: m_regHL = 0;
210: m_regAF2 = 0;
211: m_regBC2 = 0;
212: m_regDE2 = 0;
213: m_regHL2 = 0;
214: m_regR = rand();
215: m_regI = 0;
216: m_fHalt = FALSE;
217: m_nIM = 0;
218: m_regIX = 0xffff; // Yes, this intentional, and the way a Z80 comes
219: m_regIY = 0xffff; // up in power-on state!
220: m_iff1 = 0;
221: m_iff2 = 0;
222: z80intAddr = 0x38;
223: z80nmiAddr = 0x66;
224:
225: SetPC(0x0000);
226: SetSP(0x0000);
227:
228: #if 0
229: fprintf ( stderr, "Reset\n" );
230: #endif
231: }
232:
233: /* UINT32 mz80int(UINT32 a) {
234: * return ( Irq ( (BYTE) ( a & 0xFF ) ) );
235: * }
236: */
237:
238: /* UINT32 mz80nmi(void) {
239: * return ( Nmi() );
240: * }
241: */
242:
243: /* ***************************************************************************
244: * Edward Memory Handlers (guesses)
245: * ***************************************************************************
246: */
247:
248: #define ImmedByte() *m_rgbOpcode++
249:
250: /* static */ UINT16 ImmedWord ( void ) {
251: WORD w = HOST_TO_LE16(*(WORD*)m_rgbOpcode);
252: m_rgbOpcode += 2;
253: return w; // attn: little endian specific
254: }
255:
256: #define GetPC() ( (WORD)(m_rgbOpcode - m_rgbOpcodeBase) )
257:
258: void SetPC ( WORD wAddr ) {
259: m_rgbOpcode = &m_rgbOpcodeBase[wAddr];
260: }
261:
262: void AdjustPC ( signed char cb ) {
263: m_rgbOpcode += cb;
264: }
265:
266: void Push(WORD wArg) {
267: MemWriteByte(--m_rgbStack - m_rgbStackBase, HIBYTE(wArg));
268: MemWriteByte(--m_rgbStack - m_rgbStackBase, LOBYTE(wArg));
269: }
270:
271: WORD Pop() {
272: unsigned short wAddr = 0;
273:
274: wAddr = MemReadByte(m_rgbStack++ - m_rgbStackBase);
275: wAddr |= (MemReadByte(m_rgbStack++ - m_rgbStackBase) << 8);
276:
277: return(wAddr);
278: }
279:
280: WORD GetSP() {
281: return (WORD)(m_rgbStack - m_rgbStackBase);
282: }
283:
284: void SetSP(WORD wAddr) {
285: m_rgbStack = &m_rgbStackBase[wAddr];
286: }
287:
288: /* static */ UINT8 mz80GetMemory ( UINT16 addr ) {
289: struct MemoryReadByte *mr = z80MemoryRead;
290:
291: z80pc = GetPC(); /* for some of the platforms */
292:
293: while ( mr -> lowAddr != 0xffffffff ) {
294:
295: if (addr >= mr->lowAddr && addr <= mr->highAddr) {
296: z80pc = GetPC();
297: return ( mr -> memoryCall ( addr, mr ) );
298: }
299:
300: ++mr;
301:
302: }
303:
304: return ( m_rgbMemory [ addr ] );
305: }
306:
307: /* static */ void mz80PutMemory ( unsigned short int addr, unsigned char byte ) {
308: struct MemoryWriteByte *mr = z80MemoryWrite;
309:
310: while ( mr->lowAddr != 0xffffffff ) {
311: if (addr >= mr->lowAddr && addr <= mr->highAddr) {
312: z80pc = GetPC();
313: mr->memoryCall(addr, byte, mr);
314: return;
315: }
316: mr++;
317: }
318:
319: m_rgbMemory [ addr ] = byte;
320:
321: }
322:
323: BYTE In(BYTE bPort) {
324: BYTE bVal;
325: // BYTE bVal = m_rgpfnPortRead[bPort](bPort);
326:
327: struct z80PortRead *mr = z80IoRead;
328:
329: z80pc = GetPC(); /* for some of the platforms */
330:
331: while ( mr->lowIoAddr != 0xffff ) {
332: if ( bPort >= mr->lowIoAddr && bPort <= mr->highIoAddr) {
333: bVal = mr->IOCall ( bPort, mr );
334: break;
335: }
336: mr++;
337: }
338:
339: m_regF = (m_regF & C_FLAG) | ZSPTable[bVal];
340:
341: return bVal;
342: }
343:
344: BYTE InRaw (BYTE bPort) {
345: BYTE bVal;
346:
347: struct z80PortRead *mr = z80IoRead;
348:
349: z80pc = GetPC(); /* for some of the platforms */
350:
351: while ( mr->lowIoAddr != 0xffff ) {
352: if ( bPort >= mr->lowIoAddr && bPort <= mr->highIoAddr) {
353: bVal = mr->IOCall ( bPort, mr );
354: break;
355: }
356: mr++;
357: }
358:
359: // m_regF = (m_regF & C_FLAG) | ZSPTable[bVal];
360: return bVal;
361: }
362:
363: void Out(BYTE bPort, BYTE bVal) {
364: // m_rgpfnPortWrite[bPort](bPort, bVal);
365: struct z80PortWrite *mr = z80IoWrite;
366:
367: z80pc = GetPC(); /* for some of the platforms */
368:
369: while ( mr->lowIoAddr != 0xffff ) {
370: if (bPort >= mr->lowIoAddr && bPort <= mr->highIoAddr) {
371: mr->IOCall ( bPort, bVal, mr );
372: return;
373: }
374: mr++;
375: }
376:
377: }
378:
379: /* static */ void MemWriteWord ( UINT16 wAddr, UINT16 wVal ) {
380: MemWriteByte ( wAddr++, LOBYTE ( wVal ) );
381: MemWriteByte ( wAddr, HIBYTE ( wVal ) );
382: }
383:
384: /* static */ /* inline */ void MemWriteByte ( UINT16 wAddr, UINT8 bVal ) {
385: mz80PutMemory ( wAddr, bVal );
386: }
387:
388: /* static */ /* inline */ UINT8 MemReadByte ( UINT16 wAddr ) {
389: return ( mz80GetMemory ( wAddr ) );
390: }
391:
392: /* static */ /* inline */ UINT16 MemReadWord ( UINT16 wAddr ) {
393: UINT8 op1;
394: UINT8 op2;
395:
396: op1 = MemReadByte(wAddr ++);
397: op2 = MemReadByte(wAddr);
398: return ( MAKEWORD ( op1, op2 ) );
399: }
400:
401: /* ***************************************************************************
402: * Retrocade guts stuff (again) (these guys are defined after macros)
403: * ***************************************************************************
404: */
405:
406: unsigned long int mz80GetContextSize(void) {
407: return ( sizeof ( CONTEXTMZ80 ) );
408: }
409:
410: /* set memory base, etc. */
411: void mz80GetContext ( void *receiver ) {
412: CONTEXTMZ80 *c = receiver;
413: c -> z80MemRead = z80MemoryRead;
414: c -> z80MemWrite = z80MemoryWrite;
415: c -> z80Base = (UINT8 *) m_rgbOpcodeBase;
416: c -> z80IoRead = z80IoRead;
417: c -> z80IoWrite = z80IoWrite;
418: c -> z80af = m_regAF;
419: c -> z80bc = m_regBC;
420: c -> z80de = m_regDE;
421: c -> z80hl = m_regHL;
422: c -> z80afprime = m_regAF2;
423: c -> z80bcprime = m_regBC2;
424: c -> z80deprime = m_regDE2;
425: c -> z80hlprime = m_regHL2;
426: c -> z80ix = m_regIX;
427: c -> z80iy = m_regIY;
428: c -> z80sp = GetSP();
429: c -> z80pc = GetPC();
430: c -> z80i = m_regI;
431: c -> z80r = m_regR;
432: c -> z80intAddr = z80intAddr;
433: c -> z80nmiAddr = z80nmiAddr;
434: c -> z80inInterrupt = m_iff1;
435: c -> z80interruptMode = m_nIM;
436: c -> z80interruptState = m_iff2;
437: c -> z80halted = m_fHalt;
438:
439: #if 0
440: fprintf ( stderr, "GetContext\n" );
441: #endif
442: }
443:
444: void mz80SetContext( void *sender ) {
445: CONTEXTMZ80 *c = sender;
446: z80MemoryRead = c -> z80MemRead;
447: z80MemoryWrite = c -> z80MemWrite;
448: m_rgbMemory = c -> z80Base;
449: z80IoRead = c -> z80IoRead;
450: z80IoWrite = c -> z80IoWrite;
451: m_regAF = c -> z80af;
452: m_regBC = c -> z80bc;
453: m_regDE = c -> z80de;
454: m_regHL = c -> z80hl;
455: m_regAF2 = c -> z80afprime;
456: m_regBC2 = c -> z80bcprime;
457: m_regDE2 = c -> z80deprime;
458: m_regHL2 = c -> z80hlprime;
459: m_regIX = c -> z80ix;
460: m_regIY = c -> z80iy;
461: m_regI = c -> z80i;
462: m_regR = c -> z80r;
463: z80intAddr = c -> z80intAddr;
464: z80nmiAddr = c -> z80nmiAddr;
465: m_rgbOpcodeBase = m_rgbMemory;
466:
467: m_iff1 = c->z80inInterrupt;
468: m_iff2 = c->z80interruptState;
469: m_nIM = c->z80interruptMode;
470: m_fHalt = c->z80halted;
471:
472: SetPC ( c -> z80pc );
473: SetSP ( c -> z80sp );
474:
475: #if 0
476: fprintf ( stderr, "SetContext\n" );
477: #endif
478: }
479:
480: /* ***************************************************************************
481: * Z80 Please-inline-my-ass opcodes
482: * ***************************************************************************
483: */
484:
485: /* inline */ int Ret0(int f)
486: {
487: if (f)
488: {
489: SetPC(Pop());
490: return 6;
491: }
492: else
493: {
494: return 0;
495: }
496: }
497:
498: /* inline */ int Ret1(int f)
499: {
500: if (f)
501: {
502: return 0;
503: }
504: else
505: {
506: SetPC(Pop());
507: return 6;
508: }
509: }
510:
511: /* inline */ WORD Adc_2 (WORD wArg1, WORD wArg2)
512: {
513: #ifdef ARITH_TABLES
514: int q = wArg1 + wArg2 + (m_regF & C_FLAG);
515: m_regF = (((wArg1^q^wArg2)&0x1000)>>8)|((q>>16)&1)|((q&0x8000)>>8)|((q&65535)?0:Z_FLAG)|(((wArg2^wArg1^0x8000)&(wArg2^q)&0x8000)>>13);
516: return q;
517: #else
518: int q = wArg1 + wArg2 + (m_regF & C_FLAG);
519: m_regF = (((wArg1^q^wArg2)&0x1000)>>8)|((q>>16)&1)|((q&0x8000)>>8)|((q&65535)?0:Z_FLAG)|(((wArg2^wArg1^0x8000)&(wArg2^q)&0x8000)>>13);
520: return q;
521: #endif
522: }
523:
524: /* inline */ WORD Sbc_2 (WORD wArg1, WORD wArg2)
525: {
526: #ifdef ARITH_TABLES
527: int q = wArg1 - wArg2 - (m_regF & C_FLAG);
528:
529: m_regF = (((wArg1^q^wArg2)&0x1000)>>8)|((q>>16)&1)|((q&0x8000)>>8)|
530: ((q&65535)?0:Z_FLAG)|(((wArg1^wArg2)&(wArg1^q)&0x8000)>>13)|N_FLAG;
531:
532: return q;
533: #else
534: int q = wArg1 - wArg2 - (m_regF & C_FLAG);
535:
536: m_regF = (((wArg1^q^wArg2)&0x1000)>>8)|((q>>16)&1)|((q&0x8000)>>8)|
537: ((q&65535)?0:Z_FLAG)|(((wArg1^wArg2)&(wArg1^q)&0x8000)>>13)|N_FLAG;
538:
539: return q;
540: #endif
541: }
542:
543: /* inline */ WORD Add_2 (WORD wArg1, WORD wArg2)
544: {
545: #ifdef ARITH_TABLES
546: int q = wArg1 + wArg2;
547: m_regF = (m_regF&(S_FLAG|Z_FLAG|V_FLAG))|(((wArg1^q^wArg2)&0x1000)>>8)|((q>>16)&1);
548: return q;
549: #else
550: int q = wArg1 + wArg2;
551: m_regF = (m_regF&(S_FLAG|Z_FLAG|V_FLAG))|(((wArg1^q^wArg2)&0x1000)>>8)|((q>>16)&1);
552: return q;
553: #endif
554: }
555:
556: /* inline */ void Add_1 (BYTE bArg)
557: {
558: #ifdef ARITH_TABLES
559: int q = m_regA + bArg;
560: m_regF = rgfAdd[m_regA][bArg];
561: m_regA = q;
562: #else
563: int q = m_regA + bArg;
564: m_regF=ZSTable[q&255]|((q&256)>>8)| ((m_regA^q^bArg)&H_FLAG)| (((bArg^m_regA^0x80)&(bArg^q)&0x80)>>5);
565: m_regA=q;
566: #endif
567: }
568:
569: /* inline */ void Adc_1 (BYTE bArg)
570: {
571: #ifdef ARITH_TABLES
572: int q = m_regA + bArg + (m_regF & C_FLAG);
573: m_regF = rgfAddc[m_regA][bArg][m_regF & C_FLAG];
574: m_regA = q;
575: #else
576: int q = m_regA + bArg + (m_regF & C_FLAG);
577: m_regF = ZSTable[q & 255]|((q & 256)>>8)|((m_regA^q^bArg)&H_FLAG)|(((bArg^m_regA^0x80)&(bArg^q)&0x80)>>5);
578: m_regA = q;
579: #endif
580: }
581:
582: /* inline */ void Sub_1 (BYTE bArg)
583: {
584: #ifdef ARITH_TABLES
585: int q = m_regA - bArg;
586: m_regF = rgfSub[m_regA][bArg];
587: m_regA = q;
588: #else
589: int q = m_regA - bArg;
590: m_regF = ZSTable[q&255]|((q&256)>>8)|N_FLAG|((m_regA^q^bArg)&H_FLAG)|(((bArg^m_regA)&(m_regA^q)&0x80)>>5);
591: m_regA = q;
592: #endif
593: }
594:
595: /* inline */ void Sbc_1 (BYTE bArg)
596: {
597: #ifdef ARITH_TABLES
598: int q = m_regA - bArg - (m_regF & C_FLAG);
599: m_regF = rgfSubc[m_regA][bArg][m_regF & C_FLAG];
600: m_regA = q;
601: #else
602: int q = m_regA - bArg - (m_regF & C_FLAG);
603: m_regF=ZSTable[q&255]|((q&256)>>8)|N_FLAG|((m_regA^q^bArg)&H_FLAG)|(((bArg^m_regA)&(bArg^q)&0x80)>>5);
604: m_regA=q;
605: #endif
606: }
607:
608: /* inline */ void And (BYTE bArg)
609: {
610: m_regF = ZSPTable[m_regA &= bArg] | H_FLAG;
611: }
612:
613: /* inline */ void Or(BYTE bArg)
614: {
615: m_regF = ZSPTable[m_regA |= bArg];
616: }
617:
618: /* inline */ void Xor(BYTE bArg)
619: {
620: m_regF = ZSPTable[m_regA ^= bArg];
621: }
622:
623: /* inline */ void Cp(BYTE bArg)
624: {
625: #ifdef ARITH_TABLES
626: int q = m_regA - bArg;
627: m_regF = rgfSub[m_regA][bArg];
628: #else
629: int q = m_regA - bArg;
630: m_regF = ZSTable[q&255]|((q&256)>>8)|N_FLAG|((m_regA^q^bArg)&H_FLAG)|(((bArg^m_regA)&(bArg^q)&0x80)>>5);
631: #endif
632: }
633:
634: /* inline */ static BYTE Inc(BYTE bArg)
635: {
636: #ifdef ARITH_TABLES
637: bArg++;
638: m_regF = (m_regF & C_FLAG) | rgfInc[bArg];
639: return bArg;
640: #else
641: bArg++;
642: m_regF = (m_regF&C_FLAG)|ZSTable[bArg]|((bArg==0x80)?V_FLAG:0)|((bArg&0x0F)?0:H_FLAG);
643: return bArg;
644: #endif
645: }
646:
647: /* inline */ static BYTE Dec(BYTE bArg)
648: {
649: #ifdef ARITH_TABLES
650: m_regF = (m_regF & C_FLAG) | rgfDec[bArg--];
651: return bArg;
652: #else
653: m_regF=(m_regF&C_FLAG)|N_FLAG|
654: ((bArg==0x80)?V_FLAG:0)|((bArg&0x0F)?0:H_FLAG);
655:
656: m_regF|=ZSTable[--bArg];
657:
658: return bArg;
659: #endif
660: }
661:
662: // shouldn't even be members...
663:
664: /* inline */ BYTE Set(BYTE bArg, int nBit)
665: {
666: return (bArg | (1 << nBit));
667: }
668:
669: /* inline */ BYTE Res(BYTE bArg, int nBit)
670: {
671: return (bArg & ~(1 << nBit));
672: }
673:
674: /* inline */ void Bit(BYTE bArg, int nBit)
675: {
676: #ifdef ARITH_TABLES
677: m_regF = (m_regF & C_FLAG) | rgfBit[bArg][nBit];
678: #else
679: m_regF = (m_regF & C_FLAG) | H_FLAG | ((bArg&(1<< nBit))? ((nBit==7)?S_FLAG:0):Z_FLAG);
680: #endif
681: }
682:
683: /* inline */ BYTE Rlc(BYTE bArg)
684: {
685: int q = bArg >> 7;
686: bArg = (bArg << 1) | q;
687: m_regF = ZSPTable[bArg] | q;
688: return bArg;
689: }
690:
691: /* inline */ BYTE Rrc(BYTE bArg)
692: {
693: int q = bArg & 1;
694: bArg = (bArg >> 1) | (q << 7);
695: m_regF = ZSPTable[bArg]|q;
696: return bArg;
697: }
698:
699: /* inline */ BYTE Rl(BYTE bArg)
700: {
701: int q=bArg>>7;
702: bArg=(bArg<<1)|(m_regF&1);
703: m_regF=ZSPTable[bArg]|q;
704: return bArg;
705: }
706:
707: /* inline */ BYTE Rr(BYTE bArg)
708: {
709: int q = bArg&1;
710: bArg=(bArg>>1)|(m_regF<<7);
711: m_regF=ZSPTable[bArg]|q;
712: return bArg;
713: }
714:
715: /* inline */ BYTE Sll(BYTE bArg)
716: {
717: int q = bArg>>7;
718: bArg=(bArg<<1)|1;
719: m_regF=ZSPTable[bArg]|q;
720: return bArg;
721: }
722:
723: /* inline */ BYTE Srl(BYTE bArg)
724: {
725: int q = bArg&1;
726: bArg>>=1;
727: m_regF=ZSPTable[bArg]|q;
728: return bArg;
729: }
730:
731: /* inline */ BYTE Sla(BYTE bArg)
732: {
733: int q = bArg>>7;
734: bArg<<=1;
735: m_regF=ZSPTable[bArg]|q;
736: return bArg;
737: }
738:
739: /* inline */ BYTE Sra(BYTE bArg)
740: {
741: int q = bArg&1;
742: bArg = (bArg>>1)|(bArg&0x80);
743: m_regF = ZSPTable[bArg]|q;
744: return bArg;
745: }
746:
747: /* ***************************************************************************
748: * Edwards Z80 Utilities
749: * ***************************************************************************
750: */
751:
752: UINT16 swap_variable;
753: #define swap(b1,b2) swap_variable = b1; b1 = b2; b2 = swap_variable;
754: /* inline void swap ( WORD &b1, WORD &b2 ) {
755: * WORD b = b1;
756: * b1 = b2;
757: * b2 = b;
758: * }
759: */
760:
761: /* inline */ void Rlca() {
762: m_regA = (m_regA << 1) | ((m_regA & 0x80) >> 7);
763: m_regF = (m_regF & 0xEC) | (m_regA & C_FLAG);
764: }
765:
766: /* inline */ void Rrca() {
767: m_regF=(m_regF&0xEC)|(m_regA&0x01);
768: m_regA=(m_regA>>1)|(m_regA<<7);
769: }
770:
771: /* inline */ void Rla() {
772: int i = m_regF&C_FLAG;
773: m_regF = (m_regF&0xEC)|((m_regA&0x80)>>7);
774: m_regA = (m_regA<<1)|i;
775: }
776:
777: /* inline */ void Rra() {
778: int i = m_regF&C_FLAG;
779: m_regF=(m_regF&0xEC)|(m_regA&0x01);
780: m_regA=(m_regA>>1)|(i<<7);
781: }
782:
783: /* ***************************************************************************
784: * Edwards Z80 Good-bits follow
785: * ***************************************************************************
786: */
787:
788: void InitTables (void) {
789: int i;
790: DWORD dw;
791:
792: //
793: //
794: //
795:
796: for (i=0; i<256; ++i)
797: {
798: BYTE zs = 0;
799: int p=0;
800: BYTE bArg;
801: int j;
802:
803: // zs |= i ? 0 : Z_FLAG;
804: if (i==0)
805: zs|=Z_FLAG;
806:
807: // zs |= i & S_FLAG;
808: if (i&0x80)
809: zs|=S_FLAG;
810:
811: if (i&1) ++p;
812: if (i&2) ++p;
813: if (i&4) ++p;
814: if (i&8) ++p;
815: if (i&16) ++p;
816: if (i&32) ++p;
817: if (i&64) ++p;
818: if (i&128) ++p;
819:
820: // PTable[i] = (p&1) ? 0:V_FLAG;
821: ZSTable[i] = zs;
822: ZSPTable[i]= zs | ((p&1) ? 0:V_FLAG);
823:
824: rgfInc[i] = ZSTable[i] | ((i == 0x80) ? V_FLAG : 0) | ((i & 0x0F) ? 0 : H_FLAG);
825:
826: // rgfDec[i] = N_FLAG | ((i == 0x80) ? V_FLAG : 0) | ((i & 0x0F) ? 0 : H_FLAG) | ZSTable[(BYTE)i - 1];
827:
828: bArg = i;
829: rgfDec[i] = N_FLAG|((bArg==0x80)?V_FLAG:0)|((bArg&0x0F)?0:H_FLAG);
830: rgfDec[i]|=ZSTable[--bArg];
831:
832: for ( j = 0; j < 8; j++)
833: rgfBit[i][j] = H_FLAG | ((i & (1 << j))? ((j == 7) ? S_FLAG : 0) : Z_FLAG);
834: }
835:
836: //
837: // Calculate flag tables
838: //
839:
840: for ( dw = 0; dw <= 256 * 256; dw++)
841: {
842: BYTE bLo = LOBYTE(LOWORD(dw));
843: BYTE bHi = HIBYTE(LOWORD(dw));
844:
845: const BYTE regA = bLo;
846: const BYTE bArg = bHi;
847:
848: int nAcc;
849: BYTE regF;
850: int c;
851:
852: //
853: // ADD
854: //
855:
856: nAcc = regA + bArg;
857: regF = 0;
858:
859: regF |= ZSTable[nAcc&255];
860: regF |= ((nAcc&256)>>8);
861: regF |= ((regA^nAcc^bArg)&H_FLAG);
862: regF |= (((bArg^regA^0x80)&(bArg^nAcc)&0x80)>>5);
863:
864: rgfAdd[regA][bArg] = regF;
865:
866: //
867: // SUB
868: //
869:
870: nAcc = regA - bArg;
871: regF = ZSTable[nAcc&255]|((nAcc&256)>>8)|N_FLAG|((regA^nAcc^bArg)&H_FLAG)|(((bArg^regA)&(regA^nAcc)&0x80)>>5);
872:
873: rgfSub[regA][bArg] = regF;
874:
875: //
876: //
877: //
878:
879: for ( c = 0; c <= 1; c++)
880: {
881: //
882: // ADC
883: //
884:
885: nAcc = regA + bArg + c;
886: regF = 0;
887:
888: regF |= ZSTable[nAcc&255];
889: regF |= ((nAcc&256)>>8);
890: regF |= ((regA^nAcc^bArg)&H_FLAG);
891: regF |= (((bArg^regA^0x80)&(bArg^nAcc)&0x80)>>5);
892:
893: rgfAddc[regA][bArg][c] = regF;
894:
895: //
896: // SBC
897: //
898:
899: nAcc = regA - bArg - c;
900: regF = ZSTable[nAcc&255]|((nAcc&256)>>8)|N_FLAG|((regA^nAcc^bArg)&H_FLAG)|(((bArg^regA)&(bArg^nAcc)&0x80)>>5);
901:
902: rgfSubc[regA][bArg][c] = regF;
903: }
904: }
905: }
906:
907: /* ***************************************************************************
908: * Opcodes
909: * ***************************************************************************
910: */
911:
912: /*---------------------------------------------------------------------------
913:
914: Exec
915:
916: Executes the specified number of t-states. Returns the actual number of
917: t-states executed. If a halt instruction is encountered, the execution
918: loop exits. If the processor is currently in a halted state this
919: function immediately returns 0.
920:
921: ---------------------------------------------------------------------------*/
922:
923: unsigned long int mz80exec ( unsigned long int cCyclesArg ) {
924: UINT32 origElapsedTicks=dwElapsedTicks;
925: //
926: //
927: //
928:
929: // if (m_fHalt)
930: // return 0;
931:
932: //
933: // Save t-state count for return value calculation
934: //
935:
936: cCycles = cCyclesArg;
937:
938: //
939: //
940: //
941:
942:
943: #ifndef TRACE_Z80
944: while (cCycles > 0)
945: #endif
946: {
947: #ifdef _DEBUG
948: static int cins;
949:
950: if ((cins % 1000) == 0 && GetAsyncKeyState('X') < 0)
951: _ASSERT(FALSE);
952:
953: _ASSERT(cins != _instrap);
954:
955: if (cins >= _rgcins[0] && cins <= _rgcins[0] + _rgcins[1] * _rgcins[2] && ((cins - _rgcins[0]) % _rgcins[2]) == 0)
956: {
957: if (cins == _rgcins[0])
958: {
959: TRACE("instr PC AF BC DE HL IX IY SP cycl dasm \n");
960: TRACE("-------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ------------\n");
961: }
962:
963: TCHAR szBuf[128];
964:
965: Z80_Dasm(&m_rgbMemory[GetPC()], szBuf, GetPC());
966:
967: TRACE("%08X %04X %04X %04X %04X %04X %04X %04X %04X %04X %s\n",
968: cins, GetPC(), m_regAF, m_regBC, m_regDE, m_regHL, m_regIX, m_regIY, GetSP(), cCycles, szBuf);
969: }
970:
971: cins++;
972: #endif
973: const BYTE bOpcode = ImmedByte();
974:
975: #ifdef _DEBUG
976: m_rgcOpcode[0][bOpcode]++;
977: #endif
978:
979: m_regR++;
980:
981: #if 0
982: /* debug crap for RC */
983: {
984: char szBuf [ 128 ];
985: Z80_Dasm(&m_rgbMemory[GetPC()], szBuf, GetPC());
986:
987: fprintf ( stderr,
988: "%04X %04X %04X %04X %04X %04X %04X %04X %04X %s\n",
989: GetPC(), m_regAF, m_regBC, m_regDE, m_regHL,
990: m_regIX, m_regIY, GetSP(), cCycles, szBuf );
991: }
992:
993: // fprintf ( stderr, "%d\n", bOpcode );
994: #endif
995: z80pc = GetPC(); /* for some of the platforms */
996:
997: dwElapsedTicks = origElapsedTicks + (cCyclesArg - cCycles);
998:
999: switch (bOpcode)
1000: {
1001: case 0x00: // nop
1002: cCycles -= 4;
1003: break;
1004:
1005: case 0x01: // ld_bc_word
1006: cCycles -= 10;
1007: m_regBC = ImmedWord();
1008: break;
1009:
1010: case 0x02: // ld_xbc_a
1011: cCycles -= 7;
1012: MemWriteByte(m_regBC, m_regA);
1013: break;
1014:
1015: case 0x03: // inc_bc
1016: cCycles -= 6;
1017: m_regBC++;
1018: break;
1019:
1020: case 0x04: // inc_b
1021: cCycles -= 4;
1022: m_regB = Inc(m_regB);
1023: break;
1024:
1025: case 0x05: // dec_b
1026: cCycles -= 4;
1027: m_regB = Dec(m_regB);
1028: break;
1029:
1030: case 0x06: // ld_b_byte
1031: cCycles -= 7;
1032: m_regB = ImmedByte();
1033: break;
1034:
1035: case 0x07: // rlca
1036: cCycles -= 4;
1037: Rlca();
1038: break;
1039:
1040: case 0x08: // ex_af_af
1041: cCycles -= 4;
1042: swap(m_regAF, m_regAF2);
1043: break;
1044:
1045: case 0x09: // add_hl_bc
1046: cCycles -= 11;
1047: m_regHL = Add_2(m_regHL, m_regBC);
1048: break;
1049:
1050: case 0x0A: // ld_a_xbc
1051: cCycles -= 7;
1052: m_regA = MemReadByte(m_regBC);
1053: break;
1054:
1055: case 0x0B: // dec_bc
1056: cCycles -= 6;
1057: m_regBC--;
1058: break;
1059:
1060: case 0x0C: // inc_c
1061: cCycles -= 4;
1062: m_regC = Inc(m_regC);
1063: break;
1064:
1065: case 0x0D: // dec_c
1066: cCycles -= 4;
1067: m_regC = Dec(m_regC);
1068: break;
1069:
1070: case 0x0E: // ld_c_byte
1071: cCycles -= 7;
1072: m_regC = ImmedByte();
1073: break;
1074:
1075: case 0x0F: // rrca
1076: cCycles -= 4;
1077: Rrca();
1078: break;
1079:
1080: case 0x10: // djnz
1081: cCycles -= 8;
1082: cCycles -= Jr0(--m_regB);
1083: break;
1084:
1085: case 0x11: // ld_de_word
1086: cCycles -= 10;
1087: m_regDE = ImmedWord();
1088: break;
1089:
1090: case 0x12: // ld_xde_a
1091: cCycles -= 7;
1092: MemWriteByte(m_regDE, m_regA);
1093: break;
1094:
1095: case 0x13: // inc_de
1096: cCycles -= 6;
1097: m_regDE++;
1098: break;
1099:
1100: case 0x14: // inc_d
1101: cCycles -= 4;
1102: m_regD = Inc(m_regD);
1103: break;
1104:
1105: case 0x15: // dec_d
1106: cCycles -= 4;
1107: m_regD = Dec(m_regD);
1108: break;
1109:
1110: case 0x16: // ld_d_byte
1111: cCycles -= 7;
1112: m_regD = ImmedByte();
1113: break;
1114:
1115: case 0x17: // rla
1116: cCycles -= 4;
1117: Rla();
1118: break;
1119:
1120: case 0x18: // jr
1121: {
1122: #if 0
1123: cCycles -= Jr0(TRUE);
1124: #else
1125: // speedup technique adopted from Nicola's code in MAME to speedup
1126: // Galaga (the sound CPU spins with "loop: jr loop" waiting for
1127: // an interrupt). This technique is generic enough that is shouldn't
1128: // adversely effect other applications.
1129:
1130: signed char offset = (signed char)ImmedByte();
1131: cCycles -= 7;
1132: cCycles -= 5;
1133:
1134: AdjustPC(offset);
1135:
1136: if (offset == -2)
1137: {
1138: // TRACE(__FILE__ ":jr (infinite loop) at %04X\n", GetPC());
1139: goto z80ExecBottom;
1140: /* return (cCyclesArg - cCycles); */
1141: }
1142: #endif
1143: break;
1144: }
1145:
1146: case 0x19: // add_hl_de
1147: cCycles -= 11;
1148: m_regHL = Add_2(m_regHL, m_regDE);
1149: break;
1150:
1151: case 0x1A: // ld_a_xde
1152: cCycles -= 7;
1153: m_regA = MemReadByte(m_regDE);
1154: break;
1155:
1156: case 0x1B: // dec_de
1157: cCycles -= 6;
1158: m_regDE--;
1159: break;
1160:
1161: case 0x1C: // inc_e
1162: cCycles -= 4;
1163: m_regE = Inc(m_regE);
1164: break;
1165:
1166: case 0x1D: // dec_e
1167: cCycles -= 4;
1168: m_regE = Dec(m_regE);
1169: break;
1170:
1171: case 0x1E: // ld_e_byte
1172: cCycles -= 7;
1173: m_regE = ImmedByte();
1174: break;
1175:
1176: case 0x1F: // rra
1177: cCycles -= 4;
1178: Rra();
1179: break;
1180:
1181: case 0x20: // jr_nz
1182: cCycles -= 7;
1183: cCycles -= Jr1(m_regF & Z_FLAG);
1184: break;
1185:
1186: case 0x21: // ld_hl_word
1187: cCycles -= 10;
1188: m_regHL = ImmedWord();
1189: break;
1190:
1191: case 0x22: // ld_xword_hl
1192: cCycles -= 16;
1193: MemWriteWord(ImmedWord(), m_regHL);
1194: break;
1195:
1196: case 0x23: // inc_hl
1197: cCycles -= 6;
1198: m_regHL++;
1199: break;
1200:
1201: case 0x24: // inc_h
1202: cCycles -= 4;
1203: m_regH = Inc(m_regH);
1204: break;
1205:
1206: case 0x25: // dec_h
1207: cCycles -= 4;
1208: m_regH = Dec(m_regH);
1209: break;
1210:
1211: case 0x26: // ld_h_byte
1212: cCycles -= 7;
1213: m_regH = ImmedByte();
1214: break;
1215:
1216: case 0x27: // daa
1217: {
1218: int i = m_regA;
1219: cCycles -= 4;
1220: if (m_regF&C_FLAG) i|=256;
1221: if (m_regF&H_FLAG) i|=512;
1222: if (m_regF&N_FLAG) i|=1024;
1223: m_regAF = DAATable[i];
1224: break;
1225: }
1226:
1227: case 0x28: // jr_z
1228: cCycles -= 7;
1229: cCycles -= Jr0(m_regF & Z_FLAG);
1230: break;
1231:
1232: case 0x29: // add_hl_hl
1233: cCycles -= 11;
1234: m_regHL = Add_2(m_regHL, m_regHL);
1235: break;
1236:
1237: case 0x2A: // ld_hl_xword
1238: cCycles -= 16;
1239: m_regHL = MemReadWord(ImmedWord());
1240: break;
1241:
1242: case 0x2B: // dec_hl
1243: cCycles -= 6;
1244: m_regHL--;
1245: break;
1246:
1247: case 0x2C: // inc_l
1248: cCycles -= 4;
1249: m_regL = Inc(m_regL);
1250: break;
1251:
1252: case 0x2D: // dec_l
1253: cCycles -= 4;
1254: m_regL = Dec(m_regL);
1255: break;
1256:
1257: case 0x2E: // ld_l_byte
1258: cCycles -= 7;
1259: m_regL = ImmedByte();
1260: break;
1261:
1262: case 0x2F: // cpl
1263: cCycles -= 4;
1264: m_regA ^= 0xFF;
1265: m_regF |= (H_FLAG | N_FLAG);
1266: break;
1267:
1268: case 0x30: // jr_nc
1269: cCycles -= 7;
1270: cCycles -= Jr1(m_regF & C_FLAG);
1271: break;
1272:
1273: case 0x31: // ld_sp_word
1274: cCycles -= 10;
1275: SetSP(ImmedWord());
1276: break;
1277:
1278: case 0x32: // ld_xbyte_a
1279: cCycles -= 13;
1280: MemWriteByte(ImmedWord(), m_regA);
1281: break;
1282:
1283: case 0x33: // inc_sp
1284: cCycles -= 6;
1285: SetSP(GetSP() + 1);
1286: break;
1287:
1288: case 0x34: // inc_xhl
1289: cCycles -= 11;
1290: MemWriteByte(m_regHL, Inc(MemReadByte(m_regHL)));
1291: break;
1292:
1293: case 0x35: // dec_xhl
1294: cCycles -= 11;
1295: MemWriteByte(m_regHL, Dec(MemReadByte(m_regHL)));
1296: break;
1297:
1298: case 0x36: // ld_xhl_byte
1299: cCycles -= 10;
1300: MemWriteByte(m_regHL, ImmedByte());
1301: break;
1302:
1303: case 0x37: // scf
1304: cCycles -= 4;
1305: m_regF = (m_regF & 0xEC) | C_FLAG;
1306: break;
1307:
1308: case 0x38: // jr_c
1309: cCycles -= 7;
1310: cCycles -= Jr0(m_regF & C_FLAG);
1311: break;
1312:
1313: case 0x39: // add_hl_sp
1314: cCycles -= 11;
1315: m_regHL = Add_2(m_regHL, GetSP());
1316: break;
1317:
1318: case 0x3A: // ld_a_xbyte
1319: cCycles -= 13;
1320: m_regA = MemReadByte(ImmedWord());
1321: break;
1322:
1323: case 0x3B: // dec_sp
1324: cCycles -= 6;
1325: SetSP(GetSP() - 1);
1326: break;
1327:
1328: case 0x3C: // inc_a
1329: cCycles -= 4;
1330: m_regA = Inc(m_regA);
1331: break;
1332:
1333: case 0x3D: // dec_a
1334: cCycles -= 4;
1335: m_regA = Dec(m_regA);
1336: break;
1337:
1338: case 0x3E: // ld_a_byte
1339: cCycles -= 7;
1340: m_regA = ImmedByte();
1341: break;
1342:
1343: case 0x3F: // ccf
1344: cCycles -= 4;
1345: m_regF =((m_regF & 0xED)|((m_regF & 1)<<4))^1;
1346: break;
1347:
1348: case 0x40: // ld_b_b
1349: cCycles -= 4;
1350: m_regB = m_regB;
1351: break;
1352:
1353: case 0x41: // ld_b_c
1354: cCycles -= 4;
1355: m_regB = m_regC;
1356: break;
1357:
1358: case 0x42: // ld_b_d
1359: cCycles -= 4;
1360: m_regB = m_regD;
1361: break;
1362:
1363: case 0x43: // ld_b_e
1364: cCycles -= 4;
1365: m_regB = m_regE;
1366: break;
1367:
1368: case 0x44: // ld_b_h
1369: cCycles -= 4;
1370: m_regB = m_regH;
1371: break;
1372:
1373: case 0x45: // ld_b_l
1374: cCycles -= 4;
1375: m_regB = m_regL;
1376: break;
1377:
1378: case 0x46: // ld_b_xhl
1379: cCycles -= 7;
1380: m_regB = MemReadByte(m_regHL);
1381: break;
1382:
1383: case 0x47: // ld_b_a
1384: cCycles -= 4;
1385: m_regB = m_regA;
1386: break;
1387:
1388: case 0x48: // ld_c_b
1389: cCycles -= 4;
1390: m_regC = m_regB;
1391: break;
1392:
1393: case 0x49: // ld_c_c
1394: cCycles -= 4;
1395: m_regC = m_regC;
1396: break;
1397:
1398: case 0x4A: // ld_c_d
1399: cCycles -= 4;
1400: m_regC = m_regD;
1401: break;
1402:
1403: case 0x4B: // ld_c_e
1404: cCycles -= 4;
1405: m_regC = m_regE;
1406: break;
1407:
1408: case 0x4C: // ld_c_h
1409: cCycles -= 4;
1410: m_regC = m_regH;
1411: break;
1412:
1413: case 0x4D: // ld_c_l
1414: cCycles -= 4;
1415: m_regC = m_regL;
1416: break;
1417:
1418: case 0x4E: // ld_c_xhl
1419: cCycles -= 7;
1420: m_regC = MemReadByte(m_regHL);
1421: break;
1422:
1423: case 0x4F: // ld_c_a
1424: cCycles -= 4;
1425: m_regC = m_regA;
1426: break;
1427:
1428: case 0x50: // ld_d_b
1429: cCycles -= 4;
1430: m_regD = m_regB;
1431: break;
1432:
1433: case 0x51: // ld_d_c
1434: cCycles -= 4;
1435: m_regD = m_regC;
1436: break;
1437:
1438: case 0x52: // ld_d_d
1439: cCycles -= 4;
1440: m_regD = m_regD;
1441: break;
1442:
1443: case 0x53: // ld_d_e
1444: cCycles -= 4;
1445: m_regD = m_regE;
1446: break;
1447:
1448: case 0x54: // ld_d_h
1449: cCycles -= 4;
1450: m_regD = m_regH;
1451: break;
1452:
1453: case 0x55: // ld_d_l
1454: cCycles -= 4;
1455: m_regD = m_regL;
1456: break;
1457:
1458: case 0x56: // ld_d_xhl
1459: cCycles -= 7;
1460: m_regD = MemReadByte(m_regHL);
1461: break;
1462:
1463: case 0x57: // ld_d_a
1464: cCycles -= 4;
1465: m_regD = m_regA;
1466: break;
1467:
1468: case 0x58: // ld_e_b
1469: cCycles -= 4;
1470: m_regE = m_regB;
1471: break;
1472:
1473: case 0x59: // ld_e_c
1474: cCycles -= 4;
1475: m_regE = m_regC;
1476: break;
1477:
1478: case 0x5A: // ld_e_d
1479: cCycles -= 4;
1480: m_regE = m_regD;
1481: break;
1482:
1483: case 0x5B: // ld_e_e
1484: cCycles -= 4;
1485: m_regE = m_regE;
1486: break;
1487:
1488: case 0x5C: // ld_e_h
1489: cCycles -= 4;
1490: m_regE = m_regH;
1491: break;
1492:
1493: case 0x5D: // ld_e_l
1494: cCycles -= 4;
1495: m_regE = m_regL;
1496: break;
1497:
1498: case 0x5E: // ld_e_xhl
1499: cCycles -= 7;
1500: m_regE = MemReadByte(m_regHL);
1501: break;
1502:
1503: case 0x5F: // ld_e_a
1504: cCycles -= 4;
1505: m_regE = m_regA;
1506: break;
1507:
1508: case 0x60: // ld_h_b
1509: cCycles -= 4;
1510: m_regH = m_regB;
1511: break;
1512:
1513: case 0x61: // ld_h_c
1514: cCycles -= 4;
1515: m_regH = m_regC;
1516: break;
1517:
1518: case 0x62: // ld_h_d
1519: cCycles -= 4;
1520: m_regH = m_regD;
1521: break;
1522:
1523: case 0x63: // ld_h_e
1524: cCycles -= 4;
1525: m_regH = m_regE;
1526: break;
1527:
1528: case 0x64: // ld_h_h
1529: cCycles -= 4;
1530: m_regH = m_regH;
1531: break;
1532:
1533: case 0x65: // ld_h_l
1534: cCycles -= 4;
1535: m_regH = m_regL;
1536: break;
1537:
1538: case 0x66: // ld_h_xhl
1539: cCycles -= 7;
1540: m_regH = MemReadByte(m_regHL);
1541: break;
1542:
1543: case 0x67: // ld_h_a
1544: cCycles -= 4;
1545: m_regH = m_regA;
1546: break;
1547:
1548: case 0x68: // ld_l_b
1549: cCycles -= 4;
1550: m_regL = m_regB;
1551: break;
1552:
1553: case 0x69: // ld_l_c
1554: cCycles -= 4;
1555: m_regL = m_regC;
1556: break;
1557:
1558: case 0x6A: // ld_l_d
1559: cCycles -= 4;
1560: m_regL = m_regD;
1561: break;
1562:
1563: case 0x6B: // ld_l_e
1564: cCycles -= 4;
1565: m_regL = m_regE;
1566: break;
1567:
1568: case 0x6C: // ld_l_h
1569: cCycles -= 4;
1570: m_regL = m_regH;
1571: break;
1572:
1573: case 0x6D: // ld_l_l
1574: cCycles -= 4;
1575: m_regL = m_regL;
1576: break;
1577:
1578: case 0x6E: // ld_l_xhl
1579: cCycles -= 7;
1580: m_regL = MemReadByte(m_regHL);
1581: break;
1582:
1583: case 0x6F: // ld_l_a
1584: cCycles -= 4;
1585: m_regL = m_regA;
1586: break;
1587:
1588: case 0x70: // ld_xhl_b
1589: cCycles -= 7;
1590: MemWriteByte(m_regHL, m_regB);
1591: break;
1592:
1593: case 0x71: // ld_xhl_c
1594: cCycles -= 7;
1595: MemWriteByte(m_regHL, m_regC);
1596: break;
1597:
1598: case 0x72: // ld_xhl_d
1599: cCycles -= 7;
1600: MemWriteByte(m_regHL, m_regD);
1601: break;
1602:
1603: case 0x73: // ld_xhl_e
1604: cCycles -= 7;
1605: MemWriteByte(m_regHL, m_regE);
1606: break;
1607:
1608: case 0x74: // ld_xhl_h
1609: cCycles -= 7;
1610: MemWriteByte(m_regHL, m_regH);
1611: break;
1612:
1613: case 0x75: // ld_xhl_l
1614: cCycles -= 7;
1615: MemWriteByte(m_regHL, m_regL);
1616: break;
1617:
1618: case 0x76: // halt
1619: cCycles -= 4;
1620: SetPC(GetPC() - 1);
1621: m_fHalt = TRUE;
1622: goto z80ExecBottom;
1623: /* return (cCyclesArg - cCycles); */
1624:
1625: case 0x77: // ld_xhl_a
1626: cCycles -= 7;
1627: MemWriteByte(m_regHL, m_regA);
1628: break;
1629:
1630: case 0x78: // ld_a_b
1631: cCycles -= 4;
1632: m_regA = m_regB;
1633: break;
1634:
1635: case 0x79: // ld_a_c
1636: cCycles -= 4;
1637: m_regA = m_regC;
1638: break;
1639:
1640: case 0x7A: // ld_a_d
1641: cCycles -= 4;
1642: m_regA = m_regD;
1643: break;
1644:
1645: case 0x7B: // ld_a_e
1646: cCycles -= 4;
1647: m_regA = m_regE;
1648: break;
1649:
1650: case 0x7C: // ld_a_h
1651: cCycles -= 4;
1652: m_regA = m_regH;
1653: break;
1654:
1655: case 0x7D: // ld_a_l
1656: cCycles -= 4;
1657: m_regA = m_regL;
1658: break;
1659:
1660: case 0x7E: // ld_a_xhl
1661: cCycles -= 7;
1662: m_regA = MemReadByte(m_regHL);
1663: break;
1664:
1665: case 0x7F: // ld_a_a
1666: cCycles -= 4;
1667: m_regA = m_regA;
1668: break;
1669:
1670: case 0x80: // add_a_b
1671: cCycles -= 4;
1672: Add_1(m_regB);
1673: break;
1674:
1675: case 0x81: // add_a_c
1676: cCycles -= 4;
1677: Add_1(m_regC);
1678: break;
1679:
1680: case 0x82: // add_a_d
1681: cCycles -= 4;
1682: Add_1(m_regD);
1683: break;
1684:
1685: case 0x83: // add_a_e
1686: cCycles -= 4;
1687: Add_1(m_regE);
1688: break;
1689:
1690: case 0x84: // add_a_h
1691: cCycles -= 4;
1692: Add_1(m_regH);
1693: break;
1694:
1695: case 0x85: // add_a_l
1696: cCycles -= 4;
1697: Add_1(m_regL);
1698: break;
1699:
1700: case 0x86: // add_a_xhl
1701: cCycles -= 7;
1702: Add_1(MemReadByte(m_regHL));
1703: break;
1704:
1705: case 0x87: // add_a_a
1706: cCycles -= 4;
1707: Add_1(m_regA);
1708: break;
1709:
1710: case 0x88: // adc_a_b
1711: cCycles -= 4;
1712: Adc_1(m_regB);
1713: break;
1714:
1715: case 0x89: // adc_a_c
1716: cCycles -= 4;
1717: Adc_1(m_regC);
1718: break;
1719:
1720: case 0x8A: // adc_a_d
1721: cCycles -= 4;
1722: Adc_1(m_regD);
1723: break;
1724:
1725: case 0x8B: // adc_a_e
1726: cCycles -= 4;
1727: Adc_1(m_regE);
1728: break;
1729:
1730: case 0x8C: // adc_a_h
1731: cCycles -= 4;
1732: Adc_1(m_regH);
1733: break;
1734:
1735: case 0x8D: // adc_a_l
1736: cCycles -= 4;
1737: Adc_1(m_regL);
1738: break;
1739:
1740: case 0x8E: // adc_a_xhl
1741: cCycles -= 7;
1742: Adc_1(MemReadByte(m_regHL));
1743: break;
1744:
1745: case 0x8F: // adc_a_a
1746: cCycles -= 4;
1747: Adc_1(m_regA);
1748: break;
1749:
1750: case 0x90: // sub_b
1751: cCycles -= 4;
1752: Sub_1(m_regB);
1753: break;
1754:
1755: case 0x91: // sub_c
1756: cCycles -= 4;
1757: Sub_1(m_regC);
1758: break;
1759:
1760: case 0x92: // sub_d
1761: cCycles -= 4;
1762: Sub_1(m_regD);
1763: break;
1764:
1765: case 0x93: // sub_e
1766: cCycles -= 4;
1767: Sub_1(m_regE);
1768: break;
1769:
1770: case 0x94: // sub_h
1771: cCycles -= 4;
1772: Sub_1(m_regH);
1773: break;
1774:
1775: case 0x95: // sub_l
1776: cCycles -= 4;
1777: Sub_1(m_regL);
1778: break;
1779:
1780: case 0x96: // sub_xhl
1781: cCycles -= 7;
1782: Sub_1(MemReadByte(m_regHL));
1783: break;
1784:
1785: case 0x97: // sub_a
1786: cCycles -= 4;
1787: Sub_1(m_regA);
1788: break;
1789:
1790: case 0x98: // sbc_a_b
1791: cCycles -= 4;
1792: Sbc_1(m_regB);
1793: break;
1794:
1795: case 0x99: // sbc_a_c
1796: cCycles -= 4;
1797: Sbc_1(m_regC);
1798: break;
1799:
1800: case 0x9A: // sbc_a_d
1801: cCycles -= 4;
1802: Sbc_1(m_regD);
1803: break;
1804:
1805: case 0x9B: // sbc_a_e
1806: cCycles -= 4;
1807: Sbc_1(m_regE);
1808: break;
1809:
1810: case 0x9C: // sbc_a_h
1811: cCycles -= 4;
1812: Sbc_1(m_regH);
1813: break;
1814:
1815: case 0x9D: // sbc_a_l
1816: cCycles -= 4;
1817: Sbc_1(m_regL);
1818: break;
1819:
1820: case 0x9E: // sbc_a_xhl
1821: cCycles -= 7;
1822: Sbc_1(MemReadByte(m_regHL));
1823: break;
1824:
1825: case 0x9F: // sbc_a_a
1826: cCycles -= 4;
1827: Sbc_1(m_regA);
1828: break;
1829:
1830: case 0xA0: // and_b
1831: cCycles -= 4;
1832: And(m_regB);
1833: break;
1834:
1835: case 0xA1: // and_c
1836: cCycles -= 4;
1837: And(m_regC);
1838: break;
1839:
1840: case 0xA2: // and_d
1841: cCycles -= 4;
1842: And(m_regD);
1843: break;
1844:
1845: case 0xA3: // and_e
1846: cCycles -= 4;
1847: And(m_regE);
1848: break;
1849:
1850: case 0xA4: // and_h
1851: cCycles -= 4;
1852: And(m_regH);
1853: break;
1854:
1855: case 0xA5: // and_l
1856: cCycles -= 4;
1857: And(m_regL);
1858: break;
1859:
1860: case 0xA6: // and_xhl
1861: cCycles -= 7;
1862: And(MemReadByte(m_regHL));
1863: break;
1864:
1865: case 0xA7: // and_a
1866: cCycles -= 4;
1867: And(m_regA);
1868: break;
1869:
1870: case 0xA8: // xor_b
1871: cCycles -= 4;
1872: Xor(m_regB);
1873: break;
1874:
1875: case 0xA9: // xor_c
1876: cCycles -= 4;
1877: Xor(m_regC);
1878: break;
1879:
1880: case 0xAA: // xor_d
1881: cCycles -= 4;
1882: Xor(m_regD);
1883: break;
1884:
1885: case 0xAB: // xor_e
1886: cCycles -= 4;
1887: Xor(m_regE);
1888: break;
1889:
1890: case 0xAC: // xor_h
1891: cCycles -= 4;
1892: Xor(m_regH);
1893: break;
1894:
1895: case 0xAD: // xor_l
1896: cCycles -= 4;
1897: Xor(m_regL);
1898: break;
1899:
1900: case 0xAE: // xor_xhl
1901: cCycles -= 7;
1902: Xor(MemReadByte(m_regHL));
1903: break;
1904:
1905: case 0xAF: // xor_a
1906: cCycles -= 4;
1907: Xor(m_regA);
1908: break;
1909:
1910: case 0xB0: // or_b
1911: cCycles -= 4;
1912: Or(m_regB);
1913: break;
1914:
1915: case 0xB1: // or_c
1916: cCycles -= 4;
1917: Or(m_regC);
1918: break;
1919:
1920: case 0xB2: // or_d
1921: cCycles -= 4;
1922: Or(m_regD);
1923: break;
1924:
1925: case 0xB3: // or_e
1926: cCycles -= 4;
1927: Or(m_regE);
1928: break;
1929:
1930: case 0xB4: // or_h
1931: cCycles -= 4;
1932: Or(m_regH);
1933: break;
1934:
1935: case 0xB5: // or_l
1936: cCycles -= 4;
1937: Or(m_regL);
1938: break;
1939:
1940: case 0xB6: // or_xhl
1941: cCycles -= 7;
1942: Or(MemReadByte(m_regHL));
1943: break;
1944:
1945: case 0xB7: // or_a
1946: cCycles -= 4;
1947: Or(m_regA);
1948: break;
1949:
1950: case 0xB8: // cp_b
1951: cCycles -= 4;
1952: Cp(m_regB);
1953: break;
1954:
1955: case 0xB9: // cp_c
1956: cCycles -= 4;
1957: Cp(m_regC);
1958: break;
1959:
1960: case 0xBA: // cp_d
1961: cCycles -= 4;
1962: Cp(m_regD);
1963: break;
1964:
1965: case 0xBB: // cp_e
1966: cCycles -= 4;
1967: Cp(m_regE);
1968: break;
1969:
1970: case 0xBC: // cp_h
1971: cCycles -= 4;
1972: Cp(m_regH);
1973: break;
1974:
1975: case 0xBD: // cp_l
1976: cCycles -= 4;
1977: Cp(m_regL);
1978: break;
1979:
1980: case 0xBE: // cp_xhl
1981: cCycles -= 7;
1982: Cp(MemReadByte(m_regHL));
1983: break;
1984:
1985: case 0xBF: // cp_a
1986: cCycles -= 4;
1987: Cp(m_regA);
1988: break;
1989:
1990: case 0xC0: // ret_nz
1991: cCycles -= 5;
1992: cCycles -= Ret1(m_regF & Z_FLAG);
1993: break;
1994:
1995: case 0xC1: // pop_bc
1996: cCycles -= 10;
1997: m_regBC = Pop();
1998: break;
1999:
2000: case 0xC2: // jp_nz
2001: cCycles -= 10;
2002: cCycles -= Jp1(m_regF & Z_FLAG);
2003: break;
2004:
2005: case 0xC3: // jp
2006: cCycles -= 10;
2007: #if 0
2008: Jp0(TRUE);
2009: #else
2010: {
2011: // speedup hack for Galaga adopted from MAME...
2012:
2013: WORD w = ImmedWord();
2014: WORD wPc = GetPC();
2015:
2016: SetPC(w);
2017:
2018: // removed since Galaga never hit it (maybe 1942 will), and it
2019: // caused the slowdown in Time Pilot and Gyruss hiscore bug
2020: // it isn't correct anyway since "0085 jp 0088" causes is to return (Gyruss)
2021: // shouldn't it be if (w == wPC - 3)???
2022: // jul-26-97 eam
2023:
2024: /*
2025: if (w == wPc)
2026: {
2027: // TRACE(__FILE__ ":jp (infinite loop) at %04X\n", GetPC());
2028: return (cCyclesArg - cCycles);
2029: }
2030: else */
2031: if (w == wPc - 6) // attn: very Galaga specific!!!! should be done in MageX by patching ROMs with HALTs (once I figure out how to fool the ROM check at bootup)
2032: {
2033: if (*m_rgbOpcode == 0x31)
2034: {
2035: // TRACE(__FILE__ ":jp (ld sp,#xxxx) at %04X\n", GetPC());
2036: goto z80ExecBottom;
2037: /* return (cCyclesArg - cCycles); */
2038: }
2039: }
2040: }
2041: #endif
2042: break;
2043:
2044: case 0xC4: // call_nz
2045: cCycles -= 10;
2046: cCycles -= Call1(m_regF & Z_FLAG);
2047: break;
2048:
2049: case 0xC5: // push_bc
2050: cCycles -= 11;
2051: Push(m_regBC);
2052: break;
2053:
2054: case 0xC6: // add_a_byte
2055: cCycles -= 7;
2056: Add_1(ImmedByte());
2057: break;
2058:
2059: case 0xC7: // rst_00
2060: cCycles -= 11;
2061: Rst(0x00);
2062: break;
2063:
2064: case 0xC8: // ret_z
2065: cCycles -= 5;
2066: cCycles -= Ret0(m_regF & Z_FLAG);
2067: break;
2068:
2069: case 0xC9: // ret
2070: cCycles -= 4;
2071: cCycles -= Ret0(TRUE);
2072: break;
2073:
2074: case 0xCA: // jp_z
2075: cCycles -= 10;
2076: cCycles -= Jp0(m_regF & Z_FLAG);
2077: break;
2078:
2079: case 0xCB: // cb
2080: cCycles -= HandleCB();
2081: break;
2082:
2083: case 0xCC: // call_z
2084: cCycles -= 10;
2085: cCycles -= Call0(m_regF & Z_FLAG);
2086: break;
2087:
2088: case 0xCD: // call
2089: cCycles -= 10;
2090: cCycles -= Call0(TRUE);
2091: break;
2092:
2093: case 0xCE: // adc_a_byte
2094: cCycles -= 7;
2095: Adc_1(ImmedByte());
2096: break;
2097:
2098: case 0xCF: // rst_08
2099: cCycles -= 11;
2100: Rst(0x08);
2101: break;
2102:
2103: case 0xD0: // ret_nc
2104: cCycles -= 5;
2105: cCycles -= Ret1(m_regF & C_FLAG);
2106: break;
2107:
2108: case 0xD1: // pop_de
2109: cCycles -= 10;
2110: m_regDE = Pop();
2111: break;
2112:
2113: case 0xD2: // jp_nc
2114: cCycles -= 10;
2115: cCycles -= Jp1(m_regF & C_FLAG);
2116: break;
2117:
2118: case 0xD3: // out_byte_a
2119: cCycles -= 11;
2120: Out(ImmedByte(), m_regA);
2121: break;
2122:
2123: case 0xD4: // call_nc
2124: cCycles -= 10;
2125: cCycles -= Call1(m_regF & C_FLAG);
2126: break;
2127:
2128: case 0xD5: // push_de
2129: cCycles -= 11;
2130: Push(m_regDE);
2131: break;
2132:
2133: case 0xD6: // sub_byte
2134: {
2135: cCycles -= 7;
2136: Sub_1(ImmedByte());
2137: break;
2138: }
2139:
2140: case 0xD7: // rst_10
2141: cCycles -= 11;
2142: Rst(0x10);
2143: break;
2144:
2145: case 0xD8: // ret_c
2146: cCycles -= 5;
2147: cCycles -= Ret0(m_regF & C_FLAG);
2148: break;
2149:
2150: case 0xD9: // exx
2151: cCycles -= 4;
2152: Exx();
2153: break;
2154:
2155: case 0xDA: // jp_c
2156: cCycles -= 10;
2157: cCycles -= Jp0(m_regF & C_FLAG);
2158: break;
2159:
2160: case 0xDB: // in_a_byte
2161: {
2162: BYTE bPort = ImmedByte();
2163: cCycles -= 11;
2164: m_regA = InRaw ( bPort );
2165: break;
2166: }
2167:
2168: case 0xDC: // call_c
2169: cCycles -= 10;
2170: cCycles -= Call0(m_regF & C_FLAG);
2171: break;
2172:
2173: case 0xDD: // dd
2174: cCycles -= HandleDD();
2175: break;
2176:
2177: case 0xDE: // sbc_a_byte
2178: cCycles -= 7;
2179: Sbc_1(ImmedByte());
2180: break;
2181:
2182: case 0xDF: // rst_18
2183: cCycles -= 11;
2184: Rst(0x18);
2185: break;
2186:
2187: case 0xE0: // ret_po
2188: cCycles -= 5;
2189: cCycles -= Ret1(m_regF & V_FLAG);
2190: break;
2191:
2192: case 0xE1: // pop_hl
2193: cCycles -= 10;
2194: m_regHL = Pop();
2195: break;
2196:
2197: case 0xE2: // jp_po
2198: cCycles -= 10;
2199: cCycles -= Jp1(m_regF & V_FLAG);
2200: break;
2201:
2202: case 0xE3: // ex_xsp_hl
2203: cCycles -= 19;
2204: {
2205: int i = MemReadWord(GetSP());
2206: MemWriteWord(GetSP(), m_regHL);
2207: m_regHL = i;
2208: break;
2209: }
2210:
2211: case 0xE4: // call_po
2212: cCycles -= 10;
2213: cCycles -= Call1(m_regF & V_FLAG);
2214: break;
2215:
2216: case 0xE5: // push_hl
2217: cCycles -= 11;
2218: Push(m_regHL);
2219: break;
2220:
2221: case 0xE6: // and_byte
2222: cCycles -= 7;
2223: And(ImmedByte());
2224: break;
2225:
2226: case 0xE7: // rst_20
2227: cCycles -= 11;
2228: Rst(0x20);
2229: break;
2230:
2231: case 0xE8: // ret_pe
2232: cCycles -= 5;
2233: cCycles -= Ret0(m_regF & V_FLAG);
2234: break;
2235:
2236: case 0xE9: // jp_hl
2237: cCycles -= 4;
2238: SetPC(m_regHL);
2239: break;
2240:
2241: case 0xEA: // jp_pe
2242: cCycles -= 10;
2243: cCycles -= Jp0(m_regF & V_FLAG);
2244: break;
2245:
2246: case 0xEB: // ex_de_hl
2247: cCycles -= 4;
2248: swap(m_regDE, m_regHL);
2249: break;
2250:
2251: case 0xEC: // call_pe
2252: cCycles -= 10;
2253: cCycles -= Call0(m_regF & V_FLAG);
2254: break;
2255:
2256: case 0xED: // ed
2257: cCycles -= HandleED(cCycles);
2258: break;
2259:
2260: case 0xEE: // xor_byte
2261: cCycles -= 7;
2262: Xor(ImmedByte());
2263: break;
2264:
2265: case 0xEF: // rst_28
2266: cCycles -= 11;
2267: Rst(0x28);
2268: break;
2269:
2270: case 0xF0: // ret_p
2271: cCycles -= 5;
2272: cCycles -= Ret1(m_regF & S_FLAG);
2273: break;
2274:
2275: case 0xF1: // pop_af
2276: cCycles -= 10;
2277: m_regAF = Pop();
2278: break;
2279:
2280: case 0xF2: // jp_p
2281: cCycles -= 10;
2282: cCycles -= Jp1(m_regF & S_FLAG);
2283: break;
2284:
2285: case 0xF3: // di
2286: cCycles -= 4;
2287: Di();
2288: break;
2289:
2290: case 0xF4: // call_p
2291: cCycles -= 10;
2292: cCycles -= Call1(m_regF & S_FLAG);
2293: break;
2294:
2295: case 0xF5: // push_af
2296: cCycles -= 11;
2297: Push(m_regAF);
2298: break;
2299:
2300: case 0xF6: // or_byte
2301: cCycles -= 7;
2302: Or(ImmedByte());
2303: break;
2304:
2305: case 0xF7: // rst_30
2306: cCycles -= 11;
2307: Rst(0x30);
2308: break;
2309:
2310: case 0xF8: // ret_m
2311: cCycles -= 5;
2312: cCycles -= Ret0(m_regF & S_FLAG);
2313: break;
2314:
2315: case 0xF9: // ld_sp_hl
2316: cCycles -= 6;
2317: SetSP(m_regHL);
2318: break;
2319:
2320: case 0xFA: // jp_m
2321: cCycles -= 10;
2322: cCycles -= Jp0(m_regF & S_FLAG);
2323: break;
2324:
2325: case 0xFB: // ei
2326: cCycles -= 4;
2327: cCycles -= Ei();
2328: // if (m_fPendingInterrupt)
2329: {
2330: // return (cCyclesArg - cCycles);
2331: }
2332: break;
2333:
2334: case 0xFC: // call_m
2335: cCycles -= 10;
2336: cCycles -= Call0(m_regF & S_FLAG);
2337: break;
2338:
2339: case 0xFD: // fd
2340: cCycles -= HandleFD();
2341: break;
2342:
2343: case 0xFE: // cp_byte
2344: cCycles -= 7;
2345: Cp(ImmedByte());
2346: break;
2347:
2348: case 0xFF: // rst_38
2349: cCycles -= 11;
2350: Rst(0x38);
2351: break;
2352:
2353: default:
2354: assert(FALSE);
2355: break;
2356: }
2357: }
2358:
2359: z80ExecBottom:
2360: z80pc = GetPC(); /* for some of the platforms */
2361: dwElapsedTicks = origElapsedTicks + (cCyclesArg - cCycles);
2362: return ( 0x80000000 );
2363: }
2364:
2365: UINT32 mz80int ( UINT32 bVal ) {
2366: if (m_iff1 == 0) // is IRQ disabled?
2367: return 0xffffffff; // Interrupt not taken!
2368:
2369: m_fPendingInterrupt = FALSE;
2370:
2371: m_iff1 = 0;
2372:
2373: if (m_fHalt)
2374: {
2375: SetPC(GetPC() + 1);
2376: m_fHalt = FALSE;
2377: }
2378:
2379: if (0 == m_nIM || 1 == m_nIM)
2380: {
2381: Rst(z80intAddr);
2382: return(0); // We took the interrupt
2383: }
2384:
2385: Push(GetPC());
2386: SetPC(MemReadWord(MAKEWORD(bVal, m_regI)));
2387:
2388: return(0); // fix-me
2389: }
2390:
2391: UINT32 mz80nmi ( void ) {
2392: m_iff1 = 0;
2393:
2394: if (m_fHalt)
2395: {
2396: SetPC(GetPC() + 1);
2397: m_fHalt = FALSE;
2398: }
2399:
2400: Rst(z80nmiAddr);
2401:
2402: return(0);
2403: }
2404:
2405: /* ***************************************************************************
2406: * Flow of Control
2407: * ***************************************************************************
2408: */
2409:
2410: /* inline */ int Jr0(int f) {
2411: if (f)
2412: {
2413: AdjustPC((signed char)ImmedByte());
2414: return 5;
2415: }
2416: else
2417: {
2418: AdjustPC(1);
2419: return 0;
2420: }
2421: }
2422:
2423: /* inline */ int Jr1(int f) {
2424: if (f)
2425: {
2426: AdjustPC(1);
2427: return 0;
2428: }
2429: else
2430: {
2431: AdjustPC((signed char)ImmedByte());
2432: return 5;
2433: }
2434: }
2435:
2436: /* inline */ int Call0(int f) {
2437: char string[150];
2438:
2439: if (f)
2440: {
2441: WORD wAddr = ImmedWord();
2442: Push(GetPC());
2443: SetPC(wAddr);
2444: return 7;
2445: }
2446: else
2447: {
2448: AdjustPC(2);
2449: return 0;
2450: }
2451: }
2452:
2453: /* inline */ int Call1(int f) {
2454: if (f)
2455: {
2456: AdjustPC(2);
2457: return 0;
2458: }
2459: else
2460: {
2461: WORD wAddr = ImmedWord();
2462: Push(GetPC());
2463: SetPC(wAddr);
2464: return 7;
2465: }
2466: }
2467:
2468: /* inline */ int Jp0(int f) {
2469: if (f)
2470: {
2471: SetPC(ImmedWord());
2472: return 0; // ????????????????
2473: }
2474: else
2475: {
2476: AdjustPC(2);
2477: return 0;
2478: }
2479: }
2480:
2481: /* inline */ int Jp1(int f) {
2482: if (f)
2483: {
2484: AdjustPC(2);
2485: return 0;
2486: }
2487: else
2488: {
2489: SetPC(ImmedWord());
2490: return 0; // ????????????????
2491: }
2492: }
2493:
2494: /* inline */ void Rst(WORD wAddr) {
2495: Push(GetPC());
2496: SetPC(wAddr);
2497: }
2498:
2499: /* ***************************************************************************
2500: * CB prefixed instructions
2501: * ***************************************************************************
2502: */
2503:
2504: int HandleCB() {
2505: const BYTE bOpcode = ImmedByte();
2506: m_regR++;
2507:
2508: switch (bOpcode)
2509: {
2510: case 0x00: // rlc_b
2511: m_regB = Rlc(m_regB);
2512: return 8;
2513:
2514: case 0x01: // rlc_c
2515: m_regC = Rlc(m_regC);
2516: return 8;
2517:
2518: case 0x02: // rlc_d
2519: m_regD = Rlc(m_regD);
2520: return 8;
2521:
2522: case 0x03: // rlc_e
2523: m_regE = Rlc(m_regE);
2524: return 8;
2525:
2526: case 0x04: // rlc_h
2527: m_regH = Rlc(m_regH);
2528: return 8;
2529:
2530: case 0x05: // rlc_l
2531: m_regL = Rlc(m_regL);
2532: return 8;
2533:
2534: case 0x06: // rlc_xhl
2535: MemWriteByte(m_regHL, Rlc(MemReadByte(m_regHL)));
2536: return 15;
2537:
2538: case 0x07: // rlc_a
2539: m_regA = Rlc(m_regA);
2540: return 8;
2541:
2542: case 0x08: // rrc_b
2543: m_regB = Rrc(m_regB);
2544: return 8;
2545:
2546: case 0x09: // rrc_c
2547: m_regC = Rrc(m_regC);
2548: return 8;
2549:
2550: case 0x0A: // rrc_d
2551: m_regD = Rrc(m_regD);
2552: return 8;
2553:
2554: case 0x0B: // rrc_e
2555: m_regE = Rrc(m_regE);
2556: return 8;
2557:
2558: case 0x0C: // rrc_h
2559: m_regH = Rrc(m_regH);
2560: return 8;
2561:
2562: case 0x0D: // rrc_l
2563: m_regL = Rrc(m_regL);
2564: return 8;
2565:
2566: case 0x0E: // rrc_xhl
2567: MemWriteByte(m_regHL, Rrc(MemReadByte(m_regHL)));
2568: return 15;
2569:
2570: case 0x0F: // rrc_a
2571: m_regA = Rrc(m_regA);
2572: return 8;
2573:
2574: case 0x10: // rl_b
2575: m_regB = Rl(m_regB);
2576: return 8;
2577:
2578: case 0x11: // rl_c
2579: m_regC = Rl(m_regC);
2580: return 8;
2581:
2582: case 0x12: // rl_d
2583: m_regD = Rl(m_regD);
2584: return 8;
2585:
2586: case 0x13: // rl_e
2587: m_regE = Rl(m_regE);
2588: return 8;
2589:
2590: case 0x14: // rl_h
2591: m_regH = Rl(m_regH);
2592: return 8;
2593:
2594: case 0x15: // rl_l
2595: m_regL = Rl(m_regL);
2596: return 8;
2597:
2598: case 0x16: // rl_xhl
2599: MemWriteByte(m_regHL, Rl(MemReadByte(m_regHL)));
2600: return 15;
2601:
2602: case 0x17: // rl_a
2603: m_regA = Rl(m_regA);
2604: return 8;
2605:
2606: case 0x18: // rr_b
2607: m_regB = Rr(m_regB);
2608: return 8;
2609:
2610: case 0x19: // rr_c
2611: m_regC = Rr(m_regC);
2612: return 8;
2613:
2614: case 0x1A: // rr_d
2615: m_regD = Rr(m_regD);
2616: return 8;
2617:
2618: case 0x1B: // rr_e
2619: m_regE = Rr(m_regE);
2620: return 8;
2621:
2622: case 0x1C: // rr_h
2623: m_regH = Rr(m_regH);
2624: return 8;
2625:
2626: case 0x1D: // rr_l
2627: m_regL = Rr(m_regL);
2628: return 8;
2629:
2630: case 0x1E: // rr_xhl
2631: MemWriteByte(m_regHL, Rr(MemReadByte(m_regHL)));
2632: return 15;
2633:
2634: case 0x1F: // rr_a
2635: m_regA = Rr(m_regA);
2636: return 8;
2637:
2638: case 0x20: // sla_b
2639: m_regB = Sla(m_regB);
2640: return 8;
2641:
2642: case 0x21: // sla_c
2643: m_regC = Sla(m_regC);
2644: return 8;
2645:
2646: case 0x22: // sla_d
2647: m_regD = Sla(m_regD);
2648: return 8;
2649:
2650: case 0x23: // sla_e
2651: m_regE = Sla(m_regE);
2652: return 8;
2653:
2654: case 0x24: // sla_h
2655: m_regH = Sla(m_regH);
2656: return 8;
2657:
2658: case 0x25: // sla_l
2659: m_regL = Sla(m_regL);
2660: return 8;
2661:
2662: case 0x26: // sla_xhl
2663: MemWriteByte(m_regHL, Sla(MemReadByte(m_regHL)));
2664: return 15;
2665:
2666: case 0x27: // sla_a
2667: m_regA = Sla(m_regA);
2668: return 8;
2669:
2670: case 0x28: // sra_b
2671: m_regB = Sra(m_regB);
2672: return 8;
2673:
2674: case 0x29: // sra_c
2675: m_regC = Sra(m_regC);
2676: return 8;
2677:
2678: case 0x2A: // sra_d
2679: m_regD = Sra(m_regD);
2680: return 8;
2681:
2682: case 0x2B: // sra_e
2683: m_regE = Sra(m_regE);
2684: return 8;
2685:
2686: case 0x2C: // sra_h
2687: m_regH = Sra(m_regH);
2688: return 8;
2689:
2690: case 0x2D: // sra_l
2691: m_regL = Sra(m_regL);
2692: return 8;
2693:
2694: case 0x2E: // sra_xhl
2695: MemWriteByte(m_regHL, Sra(MemReadByte(m_regHL)));
2696: return 15;
2697:
2698: case 0x2F: // sra_a
2699: m_regA = Sra(m_regA);
2700: return 8;
2701:
2702: case 0x30: // sll_b
2703: m_regB = Sll(m_regB);
2704: return 8;
2705:
2706: case 0x31: // sll_c
2707: m_regC = Sll(m_regC);
2708: return 8;
2709:
2710: case 0x32: // sll_d
2711: m_regD = Sll(m_regD);
2712: return 8;
2713:
2714: case 0x33: // sll_e
2715: m_regE = Sll(m_regE);
2716: return 8;
2717:
2718: case 0x34: // sll_h
2719: m_regH = Sll(m_regH);
2720: return 8;
2721:
2722: case 0x35: // sll_l
2723: m_regL = Sll(m_regL);
2724: return 8;
2725:
2726: case 0x36: // sll_xhl
2727: MemWriteByte(m_regHL, Sll(MemReadByte(m_regHL)));
2728: return 15;
2729:
2730: case 0x37: // sll_a
2731: m_regA = Sll(m_regA);
2732: return 8;
2733:
2734: case 0x38: // srl_b
2735: m_regB = Srl(m_regB);
2736: return 8;
2737:
2738: case 0x39: // srl_c
2739: m_regC = Srl(m_regC);
2740: return 8;
2741:
2742: case 0x3A: // srl_d
2743: m_regD = Srl(m_regD);
2744: return 8;
2745:
2746: case 0x3B: // srl_e
2747: m_regE = Srl(m_regE);
2748: return 8;
2749:
2750: case 0x3C: // srl_h
2751: m_regH = Srl(m_regH);
2752: return 8;
2753:
2754: case 0x3D: // srl_l
2755: m_regL = Srl(m_regL);
2756: return 8;
2757:
2758: case 0x3E: // srl_xhl
2759: MemWriteByte(m_regHL, Srl(MemReadByte(m_regHL)));
2760: return 15;
2761:
2762: case 0x3F: // srl_a
2763: m_regA = Srl(m_regA);
2764: return 8;
2765:
2766: case 0x40: // bit_0_b
2767: Bit(m_regB, 0);
2768: return 8;
2769:
2770: case 0x41: // bit_0_c
2771: Bit(m_regC, 0);
2772: return 8;
2773:
2774: case 0x42: // bit_0_d
2775: Bit(m_regD, 0);
2776: return 8;
2777:
2778: case 0x43: // bit_0_e
2779: Bit(m_regE, 0);
2780: return 8;
2781:
2782: case 0x44: // bit_0_h
2783: Bit(m_regH, 0);
2784: return 8;
2785:
2786: case 0x45: // bit_0_l
2787: Bit(m_regL, 0);
2788: return 8;
2789:
2790: case 0x46: // bit_0_xhl
2791: Bit(MemReadByte(m_regHL), 0);
2792: return 12;
2793:
2794: case 0x47: // bit_0_a
2795: Bit(m_regA, 0);
2796: return 8;
2797:
2798: case 0x48: // bit_1_b
2799: Bit(m_regB, 1);
2800: return 8;
2801:
2802: case 0x49: // bit_1_c
2803: Bit(m_regC, 1);
2804: return 8;
2805:
2806: case 0x4A: // bit_1_d
2807: Bit(m_regD, 1);
2808: return 8;
2809:
2810: case 0x4B: // bit_1_e
2811: Bit(m_regE, 1);
2812: return 8;
2813:
2814: case 0x4C: // bit_1_h
2815: Bit(m_regH, 1);
2816: return 8;
2817:
2818: case 0x4D: // bit_1_l
2819: Bit(m_regL, 1);
2820: return 8;
2821:
2822: case 0x4E: // bit_1_xhl
2823: Bit(MemReadByte(m_regHL), 1);
2824: return 12;
2825:
2826: case 0x4F: // bit_1_a
2827: Bit(m_regA, 1);
2828: return 8;
2829:
2830: case 0x50: // bit_2_b
2831: Bit(m_regB, 2);
2832: return 8;
2833:
2834: case 0x51: // bit_2_c
2835: Bit(m_regC, 2);
2836: return 8;
2837:
2838: case 0x52: // bit_2_d
2839: Bit(m_regD, 2);
2840: return 8;
2841:
2842: case 0x53: // bit_2_e
2843: Bit(m_regE, 2);
2844: return 8;
2845:
2846: case 0x54: // bit_2_h
2847: Bit(m_regH, 2);
2848: return 8;
2849:
2850: case 0x55: // bit_2_l
2851: Bit(m_regL, 2);
2852: return 8;
2853:
2854: case 0x56: // bit_2_xhl
2855: Bit(MemReadByte(m_regHL), 2);
2856: return 12;
2857:
2858: case 0x57: // bit_2_a
2859: Bit(m_regA, 2);
2860: return 8;
2861:
2862: case 0x58: // bit_3_b
2863: Bit(m_regB, 3);
2864: return 8;
2865:
2866: case 0x59: // bit_3_c
2867: Bit(m_regC, 3);
2868: return 8;
2869:
2870: case 0x5A: // bit_3_d
2871: Bit(m_regD, 3);
2872: return 8;
2873:
2874: case 0x5B: // bit_3_e
2875: Bit(m_regE, 3);
2876: return 8;
2877:
2878: case 0x5C: // bit_3_h
2879: Bit(m_regH, 3);
2880: return 8;
2881:
2882: case 0x5D: // bit_3_l
2883: Bit(m_regL, 3);
2884: return 8;
2885:
2886: case 0x5E: // bit_3_xhl
2887: Bit(MemReadByte(m_regHL), 3);
2888: return 12;
2889:
2890: case 0x5F: // bit_3_a
2891: Bit(m_regA, 3);
2892: return 8;
2893:
2894: case 0x60: // bit_4_b
2895: Bit(m_regB, 4);
2896: return 8;
2897:
2898: case 0x61: // bit_4_c
2899: Bit(m_regC, 4);
2900: return 8;
2901:
2902: case 0x62: // bit_4_d
2903: Bit(m_regD, 4);
2904: return 8;
2905:
2906: case 0x63: // bit_4_e
2907: Bit(m_regE, 4);
2908: return 8;
2909:
2910: case 0x64: // bit_4_h
2911: Bit(m_regH, 4);
2912: return 8;
2913:
2914: case 0x65: // bit_4_l
2915: Bit(m_regL, 4);
2916: return 8;
2917:
2918: case 0x66: // bit_4_xhl
2919: Bit(MemReadByte(m_regHL), 4);
2920: return 12;
2921:
2922: case 0x67: // bit_4_a
2923: Bit(m_regA, 4);
2924: return 8;
2925:
2926: case 0x68: // bit_5_b
2927: Bit(m_regB, 5);
2928: return 8;
2929:
2930: case 0x69: // bit_5_c
2931: Bit(m_regC, 5);
2932: return 8;
2933:
2934: case 0x6A: // bit_5_d
2935: Bit(m_regD, 5);
2936: return 8;
2937:
2938: case 0x6B: // bit_5_e
2939: Bit(m_regE, 5);
2940: return 8;
2941:
2942: case 0x6C: // bit_5_h
2943: Bit(m_regH, 5);
2944: return 8;
2945:
2946: case 0x6D: // bit_5_l
2947: Bit(m_regL, 5);
2948: return 8;
2949:
2950: case 0x6E: // bit_5_xhl
2951: Bit(MemReadByte(m_regHL), 5);
2952: return 12;
2953:
2954: case 0x6F: // bit_5_a
2955: Bit(m_regA, 5);
2956: return 8;
2957:
2958: case 0x70: // bit_6_b
2959: Bit(m_regB, 6);
2960: return 8;
2961:
2962: case 0x71: // bit_6_c
2963: Bit(m_regC, 6);
2964: return 8;
2965:
2966: case 0x72: // bit_6_d
2967: Bit(m_regD, 6);
2968: return 8;
2969:
2970: case 0x73: // bit_6_e
2971: Bit(m_regE, 6);
2972: return 8;
2973:
2974: case 0x74: // bit_6_h
2975: Bit(m_regH, 6);
2976: return 8;
2977:
2978: case 0x75: // bit_6_l
2979: Bit(m_regL, 6);
2980: return 8;
2981:
2982: case 0x76: // bit_6_xhl
2983: Bit(MemReadByte(m_regHL), 6);
2984: return 12;
2985:
2986: case 0x77: // bit_6_a
2987: Bit(m_regA, 6);
2988: return 8;
2989:
2990: case 0x78: // bit_7_b
2991: Bit(m_regB, 7);
2992: return 8;
2993:
2994: case 0x79: // bit_7_c
2995: Bit(m_regC, 7);
2996: return 8;
2997:
2998: case 0x7A: // bit_7_d
2999: Bit(m_regD, 7);
3000: return 8;
3001:
3002: case 0x7B: // bit_7_e
3003: Bit(m_regE, 7);
3004: return 8;
3005:
3006: case 0x7C: // bit_7_h
3007: Bit(m_regH, 7);
3008: return 8;
3009:
3010: case 0x7D: // bit_7_l
3011: Bit(m_regL, 7);
3012: return 8;
3013:
3014: case 0x7E: // bit_7_xhl
3015: Bit(MemReadByte(m_regHL), 7);
3016: return 12;
3017:
3018: case 0x7F: // bit_7_a
3019: Bit(m_regA, 7);
3020: return 8;
3021:
3022: case 0x80: // res_0_b
3023: m_regB = Res(m_regB, 0);
3024: return 8;
3025:
3026: case 0x81: // res_0_c
3027: m_regC = Res(m_regC, 0);
3028: return 8;
3029:
3030: case 0x82: // res_0_d
3031: m_regD = Res(m_regD, 0);
3032: return 8;
3033:
3034: case 0x83: // res_0_e
3035: m_regE = Res(m_regE, 0);
3036: return 8;
3037:
3038: case 0x84: // res_0_h
3039: m_regH = Res(m_regH, 0);
3040: return 8;
3041:
3042: case 0x85: // res_0_l
3043: m_regL = Res(m_regL, 0);
3044: return 8;
3045:
3046: case 0x86: // res_0_xhl
3047: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 0));
3048: return 15;
3049:
3050: case 0x87: // res_0_a
3051: m_regA = Res(m_regA, 0);
3052: return 8;
3053:
3054: case 0x88: // res_1_b
3055: m_regB = Res(m_regB ,1);
3056: return 8;
3057:
3058: case 0x89: // res_1_c
3059: m_regC = Res(m_regC, 1);
3060: return 8;
3061:
3062: case 0x8A: // res_1_d
3063: m_regD = Res(m_regD, 1);
3064: return 8;
3065:
3066: case 0x8B: // res_1_e
3067: m_regE = Res(m_regE, 1);
3068: return 8;
3069:
3070: case 0x8C: // res_1_h
3071: m_regH = Res(m_regH, 1);
3072: return 8;
3073:
3074: case 0x8D: // res_1_l
3075: m_regL = Res(m_regL, 1);
3076: return 8;
3077:
3078: case 0x8E: // res_1_xhl
3079: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 1));
3080: return 15;
3081:
3082: case 0x8F: // res_1_a
3083: m_regA = Res(m_regA, 1);
3084: return 8;
3085:
3086: case 0x90: // res_2_b
3087: m_regB = Res(m_regB ,2);
3088: return 8;
3089:
3090: case 0x91: // res_2_c
3091: m_regC = Res(m_regC, 2);
3092: return 8;
3093:
3094: case 0x92: // res_2_d
3095: m_regD = Res(m_regD, 2);
3096: return 8;
3097:
3098: case 0x93: // res_2_e
3099: m_regE = Res(m_regE, 2);
3100: return 8;
3101:
3102: case 0x94: // res_2_h
3103: m_regH = Res(m_regH, 2);
3104: return 8;
3105:
3106: case 0x95: // res_2_l
3107: m_regL = Res(m_regL, 2);
3108: return 8;
3109:
3110: case 0x96: // res_2_xhl
3111: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 2));
3112: return 15;
3113:
3114: case 0x97: // res_2_a
3115: m_regA = Res(m_regA, 2);
3116: return 8;
3117:
3118: case 0x98: // res_3_b
3119: m_regB = Res(m_regB ,3);
3120: return 8;
3121:
3122: case 0x99: // res_3_c
3123: m_regC = Res(m_regC, 3);
3124: return 8;
3125:
3126: case 0x9A: // res_3_d
3127: m_regD = Res(m_regD, 3);
3128: return 8;
3129:
3130: case 0x9B: // res_3_e
3131: m_regE = Res(m_regE, 3);
3132: return 8;
3133:
3134: case 0x9C: // res_3_h
3135: m_regH = Res(m_regH, 3);
3136: return 8;
3137:
3138: case 0x9D: // res_3_l
3139: m_regL = Res(m_regL, 3);
3140: return 8;
3141:
3142: case 0x9E: // res_3_xhl
3143: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 3));
3144: return 15;
3145:
3146: case 0x9F: // res_3_a
3147: m_regA = Res(m_regA, 3);
3148: return 8;
3149:
3150: case 0xA0: // res_4_b
3151: m_regB = Res(m_regB ,4);
3152: return 8;
3153:
3154: case 0xA1: // res_4_c
3155: m_regC = Res(m_regC, 4);
3156: return 8;
3157:
3158: case 0xA2: // res_4_d
3159: m_regD = Res(m_regD, 4);
3160: return 8;
3161:
3162: case 0xA3: // res_4_e
3163: m_regE = Res(m_regE, 4);
3164: return 8;
3165:
3166: case 0xA4: // res_4_h
3167: m_regH = Res(m_regH, 4);
3168: return 8;
3169:
3170: case 0xA5: // res_4_l
3171: m_regL = Res(m_regL, 4);
3172: return 8;
3173:
3174: case 0xA6: // res_4_xhl
3175: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 4));
3176: return 15;
3177:
3178: case 0xA7: // res_4_a
3179: m_regA = Res(m_regA, 4);
3180: return 8;
3181:
3182: case 0xA8: // res_5_b
3183: m_regB = Res(m_regB ,5);
3184: return 8;
3185:
3186: case 0xA9: // res_5_c
3187: m_regC = Res(m_regC, 5);
3188: return 8;
3189:
3190: case 0xAA: // res_5_d
3191: m_regD = Res(m_regD, 5);
3192: return 8;
3193:
3194: case 0xAB: // res_5_e
3195: m_regE = Res(m_regE, 5);
3196: return 8;
3197:
3198: case 0xAC: // res_5_h
3199: m_regH = Res(m_regH, 5);
3200: return 8;
3201:
3202: case 0xAD: // res_5_l
3203: m_regL = Res(m_regL, 5);
3204: return 8;
3205:
3206: case 0xAE: // res_5_xhl
3207: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 5));
3208: return 15;
3209:
3210: case 0xAF: // res_5_a
3211: m_regA = Res(m_regA, 5);
3212: return 8;
3213:
3214: case 0xB0: // res_6_b
3215: m_regB = Res(m_regB ,6);
3216: return 8;
3217:
3218: case 0xB1: // res_6_c
3219: m_regC = Res(m_regC, 6);
3220: return 8;
3221:
3222: case 0xB2: // res_6_d
3223: m_regD = Res(m_regD, 6);
3224: return 8;
3225:
3226: case 0xB3: // res_6_e
3227: m_regE = Res(m_regE, 6);
3228: return 8;
3229:
3230: case 0xB4: // res_6_h
3231: m_regH = Res(m_regH, 6);
3232: return 8;
3233:
3234: case 0xB5: // res_6_l
3235: m_regL = Res(m_regL, 6);
3236: return 8;
3237:
3238: case 0xB6: // res_6_xhl
3239: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 6));
3240: return 15;
3241:
3242: case 0xB7: // res_6_a
3243: m_regA = Res(m_regA, 6);
3244: return 8;
3245:
3246: case 0xB8: // res_7_b
3247: m_regB = Res(m_regB ,7);
3248: return 8;
3249:
3250: case 0xB9: // res_7_c
3251: m_regC = Res(m_regC, 7);
3252: return 8;
3253:
3254: case 0xBA: // res_7_d
3255: m_regD = Res(m_regD, 7);
3256: return 8;
3257:
3258: case 0xBB: // res_7_e
3259: m_regE = Res(m_regE, 7);
3260: return 8;
3261:
3262: case 0xBC: // res_7_h
3263: m_regH = Res(m_regH, 7);
3264: return 8;
3265:
3266: case 0xBD: // res_7_l
3267: m_regL = Res(m_regL, 7);
3268: return 8;
3269:
3270: case 0xBE: // res_7_xhl
3271: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 7));
3272: return 15;
3273:
3274: case 0xBF: // res_7_a
3275: m_regA = Res(m_regA, 7);
3276: return 8;
3277:
3278: case 0xC0: // set_0_b
3279: m_regB = Set(m_regB ,0);
3280: return 8;
3281:
3282: case 0xC1: // set_0_c
3283: m_regC = Set(m_regC, 0);
3284: return 8;
3285:
3286: case 0xC2: // set_0_d
3287: m_regD = Set(m_regD, 0);
3288: return 8;
3289:
3290: case 0xC3: // set_0_e
3291: m_regE = Set(m_regE, 0);
3292: return 8;
3293:
3294: case 0xC4: // set_0_h
3295: m_regH = Set(m_regH, 0);
3296: return 8;
3297:
3298: case 0xC5: // set_0_l
3299: m_regL = Set(m_regL, 0);
3300: return 8;
3301:
3302: case 0xC6: // set_0_xhl
3303: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 0));
3304: return 15;
3305:
3306: case 0xC7: // set_0_a
3307: m_regA = Set(m_regA, 0);
3308: return 8;
3309:
3310: case 0xC8: // set_1_b
3311: m_regB = Set(m_regB ,1);
3312: return 8;
3313:
3314: case 0xC9: // set_1_c
3315: m_regC = Set(m_regC, 1);
3316: return 8;
3317:
3318: case 0xCA: // set_1_d
3319: m_regD = Set(m_regD, 1);
3320: return 8;
3321:
3322: case 0xCB: // set_1_e
3323: m_regE = Set(m_regE, 1);
3324: return 8;
3325:
3326: case 0xCC: // set_1_h
3327: m_regH = Set(m_regH, 1);
3328: return 8;
3329:
3330: case 0xCD: // set_1_l
3331: m_regL = Set(m_regL, 1);
3332: return 8;
3333:
3334: case 0xCE: // set_1_xhl
3335: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 1));
3336: return 15;
3337:
3338: case 0xCF: // set_1_a
3339: m_regA = Set(m_regA, 1);
3340: return 8;
3341:
3342: case 0xD0: // set_2_b
3343: m_regB = Set(m_regB ,2);
3344: return 8;
3345:
3346: case 0xD1: // set_2_c
3347: m_regC = Set(m_regC, 2);
3348: return 8;
3349:
3350: case 0xD2: // set_2_d
3351: m_regD = Set(m_regD, 2);
3352: return 8;
3353:
3354: case 0xD3: // set_2_e
3355: m_regE = Set(m_regE, 2);
3356: return 8;
3357:
3358: case 0xD4: // set_2_h
3359: m_regH = Set(m_regH, 2);
3360: return 8;
3361:
3362: case 0xD5: // set_2_l
3363: m_regL = Set(m_regL, 2);
3364: return 8;
3365:
3366: case 0xD6: // set_2_xhl
3367: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 2));
3368: return 15;
3369:
3370: case 0xD7: // set_2_a
3371: m_regA = Set(m_regA, 2);
3372: return 8;
3373:
3374: case 0xD8: // set_3_b
3375: m_regB = Set(m_regB ,3);
3376: return 8;
3377:
3378: case 0xD9: // set_3_c
3379: m_regC = Set(m_regC, 3);
3380: return 8;
3381:
3382: case 0xDA: // set_3_d
3383: m_regD = Set(m_regD, 3);
3384: return 8;
3385:
3386: case 0xDB: // set_3_e
3387: m_regE = Set(m_regE, 3);
3388: return 8;
3389:
3390: case 0xDC: // set_3_h
3391: m_regH = Set(m_regH, 3);
3392: return 8;
3393:
3394: case 0xDD: // set_3_l
3395: m_regL = Set(m_regL, 3);
3396: return 8;
3397:
3398: case 0xDE: // set_3_xhl
3399: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 3));
3400: return 15;
3401:
3402: case 0xDF: // set_3_a
3403: m_regA = Set(m_regA, 3);
3404: return 8;
3405:
3406: case 0xE0: // set_4_b
3407: m_regB = Set(m_regB ,4);
3408: return 8;
3409:
3410: case 0xE1: // set_4_c
3411: m_regC = Set(m_regC, 4);
3412: return 8;
3413:
3414: case 0xE2: // set_4_d
3415: m_regD = Set(m_regD, 4);
3416: return 8;
3417:
3418: case 0xE3: // set_4_e
3419: m_regE = Set(m_regE, 4);
3420: return 8;
3421:
3422: case 0xE4: // set_4_h
3423: m_regH = Set(m_regH, 4);
3424: return 8;
3425:
3426: case 0xE5: // set_4_l
3427: m_regL = Set(m_regL, 4);
3428: return 8;
3429:
3430: case 0xE6: // set_4_xhl
3431: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 4));
3432: return 15;
3433:
3434: case 0xE7: // set_4_a
3435: m_regA = Set(m_regA, 4);
3436: return 8;
3437:
3438: case 0xE8: // set_5_b
3439: m_regB = Set(m_regB ,5);
3440: return 8;
3441:
3442: case 0xE9: // set_5_c
3443: m_regC = Set(m_regC, 5);
3444: return 8;
3445:
3446: case 0xEA: // set_5_d
3447: m_regD = Set(m_regD, 5);
3448: return 8;
3449:
3450: case 0xEB: // set_5_e
3451: m_regE = Set(m_regE, 5);
3452: return 8;
3453:
3454: case 0xEC: // set_5_h
3455: m_regH = Set(m_regH, 5);
3456: return 8;
3457:
3458: case 0xED: // set_5_l
3459: m_regL = Set(m_regL, 5);
3460: return 8;
3461:
3462: case 0xEE: // set_5_xhl
3463: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 5));
3464: return 15;
3465:
3466: case 0xEF: // set_5_a
3467: m_regA = Set(m_regA, 5);
3468: return 8;
3469:
3470: case 0xF0: // set_6_b
3471: m_regB = Set(m_regB ,6);
3472: return 8;
3473:
3474: case 0xF1: // set_6_c
3475: m_regC = Set(m_regC, 6);
3476: return 8;
3477:
3478: case 0xF2: // set_6_d
3479: m_regD = Set(m_regD, 6);
3480: return 8;
3481:
3482: case 0xF3: // set_6_e
3483: m_regE = Set(m_regE, 6);
3484: return 8;
3485:
3486: case 0xF4: // set_6_h
3487: m_regH = Set(m_regH, 6);
3488: return 8;
3489:
3490: case 0xF5: // set_6_l
3491: m_regL = Set(m_regL, 6);
3492: return 8;
3493:
3494: case 0xF6: // set_6_xhl
3495: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 6));
3496: return 15;
3497:
3498: case 0xF7: // set_6_a
3499: m_regA = Set(m_regA, 6);
3500: return 8;
3501:
3502: case 0xF8: // set_7_b
3503: m_regB = Set(m_regB ,7);
3504: return 8;
3505:
3506: case 0xF9: // set_7_c
3507: m_regC = Set(m_regC, 7);
3508: return 8;
3509:
3510: case 0xFA: // set_7_d
3511: m_regD = Set(m_regD, 7);
3512: return 8;
3513:
3514: case 0xFB: // set_7_e
3515: m_regE = Set(m_regE, 7);
3516: return 8;
3517:
3518: case 0xFC: // set_7_h
3519: m_regH = Set(m_regH, 7);
3520: return 8;
3521:
3522: case 0xFD: // set_7_l
3523: m_regL = Set(m_regL, 7);
3524: return 8;
3525:
3526: case 0xFE: // set_7_xhl
3527: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 7));
3528: return 15;
3529:
3530: case 0xFF: // set_7_a
3531: m_regA = Set(m_regA, 7);
3532: return 8;
3533:
3534: default:
3535: _ASSERT(FALSE);
3536: return 0;
3537: }
3538: }
3539:
3540: void Exx() {
3541: swap(m_regBC, m_regBC2);
3542: swap(m_regDE, m_regDE2);
3543: swap(m_regHL, m_regHL2);
3544: }
3545:
3546: /* ***************************************************************************
3547: * DD prefixed opcodes
3548: * ***************************************************************************
3549: */
3550: /* inline */ WORD IndirectIX() {
3551: return m_regIX + (signed char)ImmedByte();
3552: }
3553:
3554: int HandleDD() {
3555: WORD wAddr;
3556: WORD wTemp;
3557:
3558: const BYTE bOpcode = ImmedByte();
3559:
3560: m_regR++;
3561:
3562: switch (bOpcode)
3563: {
3564: case 0x00: // no_op
3565: SetPC(GetPC() - 1);
3566: return 0;
3567:
3568: case 0x01: // no_op
3569: SetPC(GetPC() - 1);
3570: return 0;
3571:
3572: case 0x02: // no_op
3573: SetPC(GetPC() - 1);
3574: return 0;
3575:
3576: case 0x03: // no_op
3577: SetPC(GetPC() - 1);
3578: return 0;
3579:
3580: case 0x04: // no_op
3581: SetPC(GetPC() - 1);
3582: return 0;
3583:
3584: case 0x05: // no_op
3585: SetPC(GetPC() - 1);
3586: return 0;
3587:
3588: case 0x06: // no_op
3589: SetPC(GetPC() - 1);
3590: return 0;
3591:
3592: case 0x07: // no_op
3593: SetPC(GetPC() - 1);
3594: return 0;
3595:
3596: case 0x08: // no_op
3597: SetPC(GetPC() - 1);
3598: return 0;
3599:
3600: case 0x09: // add_ix_bc
3601: m_regIX = Add_2(m_regIX, m_regBC);
3602: return 15;
3603:
3604: case 0x0A: // no_op
3605: SetPC(GetPC() - 1);
3606: return 0;
3607:
3608: case 0x0B: // no_op
3609: SetPC(GetPC() - 1);
3610: return 0;
3611:
3612: case 0x0C: // no_op
3613: SetPC(GetPC() - 1);
3614: return 0;
3615:
3616: case 0x0D: // no_op
3617: SetPC(GetPC() - 1);
3618: return 0;
3619:
3620: case 0x0E: // no_op
3621: SetPC(GetPC() - 1);
3622: return 0;
3623:
3624: case 0x0F: // no_op
3625: SetPC(GetPC() - 1);
3626: return 0;
3627:
3628: case 0x10: // no_op
3629: SetPC(GetPC() - 1);
3630: return 0;
3631:
3632: case 0x11: // no_op
3633: SetPC(GetPC() - 1);
3634: return 0;
3635:
3636: case 0x12: // no_op
3637: SetPC(GetPC() - 1);
3638: return 0;
3639:
3640: case 0x13: // no_op
3641: SetPC(GetPC() - 1);
3642: return 0;
3643:
3644: case 0x14: // no_op
3645: SetPC(GetPC() - 1);
3646: return 0;
3647:
3648: case 0x15: // no_op
3649: SetPC(GetPC() - 1);
3650: return 0;
3651:
3652: case 0x16: // no_op
3653: SetPC(GetPC() - 1);
3654: return 0;
3655:
3656: case 0x17: // no_op
3657: SetPC(GetPC() - 1);
3658: return 0;
3659:
3660: case 0x18: // no_op
3661: SetPC(GetPC() - 1);
3662: return 0;
3663:
3664: case 0x19: // add_ix_de
3665: m_regIX = Add_2(m_regIX, m_regDE);
3666: return 15;
3667:
3668: case 0x1A: // no_op
3669: SetPC(GetPC() - 1);
3670: return 0;
3671:
3672: case 0x1B: // no_op
3673: SetPC(GetPC() - 1);
3674: return 0;
3675:
3676: case 0x1C: // no_op
3677: SetPC(GetPC() - 1);
3678: return 0;
3679:
3680: case 0x1D: // no_op
3681: SetPC(GetPC() - 1);
3682: return 0;
3683:
3684: case 0x1E: // no_op
3685: SetPC(GetPC() - 1);
3686: return 0;
3687:
3688: case 0x1F: // no_op
3689: SetPC(GetPC() - 1);
3690: return 0;
3691:
3692: case 0x20: // no_op
3693: SetPC(GetPC() - 1);
3694: return 0;
3695:
3696: case 0x21: // ld_ix_word
3697: m_regIX = ImmedWord();
3698: return 14;
3699:
3700: case 0x22: // ld_xword_ix
3701: MemWriteWord(ImmedWord(), m_regIX);
3702: return 20;
3703:
3704: case 0x23: // inc_ix
3705: m_regIX++;
3706: return 10;
3707:
3708: case 0x24: // inc_ixh
3709: m_regIXh = Inc(m_regIXh);
3710: return 9;
3711:
3712: case 0x25: // dec_ixh
3713: m_regIXh = Dec(m_regIXh);
3714: return 9;
3715:
3716: case 0x26: // ld_ixh_byte
3717: m_regIXh = ImmedByte();
3718: return 9;
3719:
3720: case 0x27: // no_op
3721: SetPC(GetPC() - 1);
3722: return 0;
3723:
3724: case 0x28: // no_op
3725: SetPC(GetPC() - 1);
3726: return 0;
3727:
3728: case 0x29: // add_ix_ix
3729: m_regIX = Add_2(m_regIX, m_regIX);
3730: return 15;
3731:
3732: case 0x2A: // ld_ix_xword
3733: m_regIX = MemReadWord(ImmedWord());
3734: return 20;
3735:
3736: case 0x2B: // dec_ix
3737: m_regIX--;
3738: return 10;
3739:
3740: case 0x2C: // inc_ixl
3741: m_regIXl = Inc(m_regIXl);
3742: return 9;
3743:
3744: case 0x2D: // dec_ixl
3745: m_regIXl = Dec(m_regIXl);
3746: return 9;
3747:
3748: case 0x2E: // ld_ixl_byte
3749: m_regIXl = ImmedByte();
3750: return 9;
3751:
3752: case 0x2F: // no_op
3753: SetPC(GetPC() - 1);
3754: return 0;
3755:
3756: case 0x30: // no_op
3757: SetPC(GetPC() - 1);
3758: return 0;
3759:
3760: case 0x31: // no_op
3761: SetPC(GetPC() - 1);
3762: return 0;
3763:
3764: case 0x32: // no_op
3765: SetPC(GetPC() - 1);
3766: return 0;
3767:
3768: case 0x33: // no_op
3769: SetPC(GetPC() - 1);
3770: return 0;
3771:
3772: case 0x34: // inc_xix
3773: wAddr = IndirectIX();
3774: MemWriteByte(wAddr, Inc(MemReadByte(wAddr)));
3775: return 23;
3776:
3777: case 0x35: // dec_xix
3778: wAddr = IndirectIX();
3779: MemWriteByte(wAddr, Dec(MemReadByte(wAddr)));
3780: return 23;
3781:
3782: case 0x36: // ld_xix_byte
3783: wAddr = IndirectIX();
3784: MemWriteByte(wAddr, ImmedByte());
3785: return 19;
3786:
3787: case 0x37: // no_op
3788: SetPC(GetPC() - 1);
3789: return 0;
3790:
3791: case 0x38: // no_op
3792: SetPC(GetPC() - 1);
3793: return 0;
3794:
3795: case 0x39: // add_ix_sp
3796: m_regIX = Add_2(m_regIX, GetSP());
3797: return 15;
3798:
3799: case 0x3A: // no_op
3800: SetPC(GetPC() - 1);
3801: return 0;
3802:
3803: case 0x3B: // no_op
3804: SetPC(GetPC() - 1);
3805: return 0;
3806:
3807: case 0x3C: // no_op
3808: SetPC(GetPC() - 1);
3809: return 0;
3810:
3811: case 0x3D: // no_op
3812: SetPC(GetPC() - 1);
3813: return 0;
3814:
3815: case 0x3E: // no_op
3816: SetPC(GetPC() - 1);
3817: return 0;
3818:
3819: case 0x3F: // no_op
3820: SetPC(GetPC() - 1);
3821: return 0;
3822:
3823: case 0x40: // no_op
3824: SetPC(GetPC() - 1);
3825: return 0;
3826:
3827: case 0x41: // no_op
3828: SetPC(GetPC() - 1);
3829: return 0;
3830:
3831: case 0x42: // no_op
3832: SetPC(GetPC() - 1);
3833: return 0;
3834:
3835: case 0x43: // no_op
3836: SetPC(GetPC() - 1);
3837: return 0;
3838:
3839: case 0x44: // ld_b_ixh
3840: m_regB = m_regIXh;
3841: return 9;
3842:
3843: case 0x45: // ld_b_ixl
3844: m_regB = m_regIXl;
3845: return 9;
3846:
3847: case 0x46: // ld_b_xix
3848: m_regB = MemReadByte(IndirectIX());
3849: return 19;
3850:
3851: case 0x47: // no_op
3852: SetPC(GetPC() - 1);
3853: return 0;
3854:
3855: case 0x48: // no_op
3856: SetPC(GetPC() - 1);
3857: return 0;
3858:
3859: case 0x49: // no_op
3860: SetPC(GetPC() - 1);
3861: return 0;
3862:
3863: case 0x4A: // no_op
3864: SetPC(GetPC() - 1);
3865: return 0;
3866:
3867: case 0x4B: // no_op
3868: SetPC(GetPC() - 1);
3869: return 0;
3870:
3871: case 0x4C: // ld_c_ixh
3872: m_regC = m_regIXh;
3873: return 9;
3874:
3875: case 0x4D: // ld_c_ixl
3876: m_regC = m_regIXl;
3877: return 9;
3878:
3879: case 0x4E: // ld_c_xix
3880: m_regC = MemReadByte(IndirectIX());
3881: return 19;
3882:
3883: case 0x4F: // no_op
3884: SetPC(GetPC() - 1);
3885: return 0;
3886:
3887: case 0x50: // no_op
3888: SetPC(GetPC() - 1);
3889: return 0;
3890:
3891: case 0x51: // no_op
3892: SetPC(GetPC() - 1);
3893: return 0;
3894:
3895: case 0x52: // no_op
3896: SetPC(GetPC() - 1);
3897: return 0;
3898:
3899: case 0x53: // no_op
3900: SetPC(GetPC() - 1);
3901: return 0;
3902:
3903: case 0x54: // ld_d_ixh
3904: m_regD = m_regIXh;
3905: return 9;
3906:
3907: case 0x55: // ld_d_ixl
3908: m_regD = m_regIXl;
3909: return 9;
3910:
3911: case 0x56: // ld_d_xix
3912: m_regD = MemReadByte(IndirectIX());
3913: return 19;
3914:
3915: case 0x57: // no_op
3916: SetPC(GetPC() - 1);
3917: return 0;
3918:
3919: case 0x58: // no_op
3920: SetPC(GetPC() - 1);
3921: return 0;
3922:
3923: case 0x59: // no_op
3924: SetPC(GetPC() - 1);
3925: return 0;
3926:
3927: case 0x5A: // no_op
3928: SetPC(GetPC() - 1);
3929: return 0;
3930:
3931: case 0x5B: // no_op
3932: SetPC(GetPC() - 1);
3933: return 0;
3934:
3935: case 0x5C: // ld_e_ixh
3936: m_regE = m_regIXh;
3937: return 9;
3938:
3939: case 0x5D: // ld_e_ixl
3940: m_regE = m_regIXl;
3941: return 9;
3942:
3943: case 0x5E: // ld_e_xix
3944: m_regE = MemReadByte(IndirectIX());
3945: return 19;
3946:
3947: case 0x5F: // no_op
3948: SetPC(GetPC() - 1);
3949: return 0;
3950:
3951: case 0x60: // ld_ixh_b
3952: m_regIXh = m_regB;
3953: return 9;
3954:
3955: case 0x61: // ld_ixh_c
3956: m_regIXh = m_regC;
3957: return 9;
3958:
3959: case 0x62: // ld_ixh_d
3960: m_regIXh = m_regD;
3961: return 9;
3962:
3963: case 0x63: // ld_ixh_e
3964: m_regIXh = m_regE;
3965: return 9;
3966:
3967: case 0x64: // ld_ixh_h
3968: m_regIXh = m_regH;
3969: return 9;
3970:
3971: case 0x65: // ld_ixh_l
3972: m_regIXh = m_regL;
3973: return 9;
3974:
3975: case 0x66: // ld_h_xix
3976: m_regH = MemReadByte(IndirectIX());
3977: return 9;
3978:
3979: case 0x67: // ld_ixh_a
3980: m_regIXh = m_regA;
3981: return 9;
3982:
3983: case 0x68: // ld_ixl_b
3984: m_regIXl = m_regB;
3985: return 9;
3986:
3987: case 0x69: // ld_ixl_c
3988: m_regIXl = m_regC;
3989: return 9;
3990:
3991: case 0x6A: // ld_ixl_d
3992: m_regIXl = m_regD;
3993: return 9;
3994:
3995: case 0x6B: // ld_ixl_e
3996: m_regIXl = m_regE;
3997: return 9;
3998:
3999: case 0x6C: // ld_ixl_h
4000: m_regIXl = m_regH;
4001: return 9;
4002:
4003: case 0x6D: // ld_ixl_l
4004: m_regIXl = m_regL;
4005: return 9;
4006:
4007: case 0x6E: // ld_l_xix
4008: m_regL = MemReadByte(IndirectIX());
4009: return 9;
4010:
4011: case 0x6F: // ld_ixl_a
4012: m_regIXl = m_regA;
4013: return 9;
4014:
4015: case 0x70: // ld_xix_b
4016: MemWriteByte(IndirectIX(), m_regB);
4017: return 19;
4018:
4019: case 0x71: // ld_xix_c
4020: MemWriteByte(IndirectIX(), m_regC);
4021: return 19;
4022:
4023: case 0x72: // ld_xix_d
4024: MemWriteByte(IndirectIX(), m_regD);
4025: return 19;
4026:
4027: case 0x73: // ld_xix_e
4028: MemWriteByte(IndirectIX(), m_regE);
4029: return 19;
4030:
4031: case 0x74: // ld_xix_h
4032: MemWriteByte(IndirectIX(), m_regH);
4033: return 19;
4034:
4035: case 0x75: // ld_xix_l
4036: MemWriteByte(IndirectIX(), m_regL);
4037: return 19;
4038:
4039: case 0x76: // no_op
4040: SetPC(GetPC() - 1);
4041: return 19;
4042:
4043: case 0x77: // ld_xix_a
4044: MemWriteByte(IndirectIX(), m_regA);
4045: return 19;
4046:
4047: case 0x78: // no_op
4048: SetPC(GetPC() - 1);
4049: return 0;
4050:
4051: case 0x79: // no_op
4052: SetPC(GetPC() - 1);
4053: return 0;
4054:
4055: case 0x7A: // no_op
4056: SetPC(GetPC() - 1);
4057: return 0;
4058:
4059: case 0x7B: // no_op
4060: SetPC(GetPC() - 1);
4061: return 0;
4062:
4063: case 0x7C: // ld_a_ixh
4064: m_regA = m_regIXh;
4065: return 9;
4066:
4067: case 0x7D: // ld_a_ixl
4068: m_regA = m_regIXl;
4069: return 9;
4070:
4071: case 0x7E: // ld_a_xix
4072: m_regA = MemReadByte(IndirectIX());
4073: return 19;
4074:
4075: case 0x7F: // no_op
4076: SetPC(GetPC() - 1);
4077: return 0;
4078:
4079: case 0x80: // no_op
4080: SetPC(GetPC() - 1);
4081: return 0;
4082:
4083: case 0x81: // no_op
4084: SetPC(GetPC() - 1);
4085: return 0;
4086:
4087: case 0x82: // no_op
4088: SetPC(GetPC() - 1);
4089: return 0;
4090:
4091: case 0x83: // no_op
4092: SetPC(GetPC() - 1);
4093: return 0;
4094:
4095: case 0x84: // add_a_ixh
4096: Add_1(m_regIXh);
4097: return 9;
4098:
4099: case 0x85: // add_a_ixl
4100: Add_1(m_regIXl);
4101: return 9;
4102:
4103: case 0x86: // add_a_xix
4104: Add_1(MemReadByte(IndirectIX()));
4105: return 19;
4106:
4107: case 0x87: // no_op
4108: SetPC(GetPC() - 1);
4109: return 0;
4110:
4111: case 0x88: // no_op
4112: SetPC(GetPC() - 1);
4113: return 0;
4114:
4115: case 0x89: // no_op
4116: SetPC(GetPC() - 1);
4117: return 0;
4118:
4119: case 0x8A: // no_op
4120: SetPC(GetPC() - 1);
4121: return 0;
4122:
4123: case 0x8B: // no_op
4124: SetPC(GetPC() - 1);
4125: return 0;
4126:
4127: case 0x8C: // adc_a_ixh
4128: Adc_1(m_regIXh);
4129: return 9;
4130:
4131: case 0x8D: // adc_a_ixl
4132: Adc_1(m_regIXl);
4133: return 9;
4134:
4135: case 0x8E: // adc_a_xix
4136: Adc_1(MemReadByte(IndirectIX()));
4137: return 19;
4138:
4139: case 0x8F: // no_op
4140: SetPC(GetPC() - 1);
4141: return 0;
4142:
4143: case 0x90: // no_op
4144: SetPC(GetPC() - 1);
4145: return 0;
4146:
4147: case 0x91: // no_op
4148: SetPC(GetPC() - 1);
4149: return 0;
4150:
4151: case 0x92: // no_op
4152: SetPC(GetPC() - 1);
4153: return 0;
4154:
4155: case 0x93: // no_op
4156: SetPC(GetPC() - 1);
4157: return 0;
4158:
4159: case 0x94: // sub_ixh
4160: Sub_1(m_regIXh);
4161: return 9;
4162:
4163: case 0x95: // sub_ixl
4164: Sub_1(m_regIXl);
4165: return 9;
4166:
4167: case 0x96: // sub_xix
4168: Sub_1(MemReadByte(IndirectIX()));
4169: return 19;
4170:
4171: case 0x97: // no_op
4172: SetPC(GetPC() - 1);
4173: return 0;
4174:
4175: case 0x98: // no_op
4176: SetPC(GetPC() - 1);
4177: return 0;
4178:
4179: case 0x99: // no_op
4180: SetPC(GetPC() - 1);
4181: return 0;
4182:
4183: case 0x9A: // no_op
4184: SetPC(GetPC() - 1);
4185: return 0;
4186:
4187: case 0x9B: // no_op
4188: SetPC(GetPC() - 1);
4189: return 0;
4190:
4191: case 0x9C: // sbc_a_ixh
4192: Sbc_1(m_regIXh);
4193: return 9;
4194:
4195: case 0x9D: // sbc_a_ixl
4196: Sbc_1(m_regIXl);
4197: return 9;
4198:
4199: case 0x9E: // sbc_a_xix
4200: Sbc_1(MemReadByte(IndirectIX()));
4201: return 19;
4202:
4203: case 0x9F: // no_op
4204: SetPC(GetPC() - 1);
4205: return 0;
4206:
4207: case 0xA0: // no_op
4208: SetPC(GetPC() - 1);
4209: return 0;
4210:
4211: case 0xA1: // no_op
4212: SetPC(GetPC() - 1);
4213: return 0;
4214:
4215: case 0xA2: // no_op
4216: SetPC(GetPC() - 1);
4217: return 0;
4218:
4219: case 0xA3: // no_op
4220: SetPC(GetPC() - 1);
4221: return 0;
4222:
4223: case 0xA4: // and_ixh
4224: And(m_regIXh);
4225: return 9;
4226:
4227: case 0xA5: // and_ixl
4228: And(m_regIXl);
4229: return 9;
4230:
4231: case 0xA6: // and_xix
4232: And(MemReadByte(IndirectIX()));
4233: return 19;
4234:
4235: case 0xA7: // no_op
4236: SetPC(GetPC() - 1);
4237: return 0;
4238:
4239: case 0xA8: // no_op
4240: SetPC(GetPC() - 1);
4241: return 0;
4242:
4243: case 0xA9: // no_op
4244: SetPC(GetPC() - 1);
4245: return 0;
4246:
4247: case 0xAA: // no_op
4248: SetPC(GetPC() - 1);
4249: return 0;
4250:
4251: case 0xAB: // no_op
4252: SetPC(GetPC() - 1);
4253: return 0;
4254:
4255: case 0xAC: // xor_ixh
4256: Xor(m_regIXh);
4257: return 9;
4258:
4259: case 0xAD: // xor_ixl
4260: Xor(m_regIXl);
4261: return 9;
4262:
4263: case 0xAE: // xor_xix
4264: Xor(MemReadByte(IndirectIX()));
4265: return 19;
4266:
4267: case 0xAF: // no_op
4268: SetPC(GetPC() - 1);
4269: return 0;
4270:
4271: case 0xB0: // no_op
4272: SetPC(GetPC() - 1);
4273: return 0;
4274:
4275: case 0xB1: // no_op
4276: SetPC(GetPC() - 1);
4277: return 0;
4278:
4279: case 0xB2: // no_op
4280: SetPC(GetPC() - 1);
4281: return 0;
4282:
4283: case 0xB3: // no_op
4284: SetPC(GetPC() - 1);
4285: return 0;
4286:
4287: case 0xB4: // or_ixh
4288: Or(m_regIXh);
4289: return 9;
4290:
4291: case 0xB5: // or_ixl
4292: Or(m_regIXl);
4293: return 9;
4294:
4295: case 0xB6: // or_xix
4296: Or(MemReadByte(IndirectIX()));
4297: return 19;
4298:
4299: case 0xB7: // no_op
4300: SetPC(GetPC() - 1);
4301: return 0;
4302:
4303: case 0xB8: // no_op
4304: SetPC(GetPC() - 1);
4305: return 0;
4306:
4307: case 0xB9: // no_op
4308: SetPC(GetPC() - 1);
4309: return 0;
4310:
4311: case 0xBA: // no_op
4312: SetPC(GetPC() - 1);
4313: return 0;
4314:
4315: case 0xBB: // no_op
4316: SetPC(GetPC() - 1);
4317: return 0;
4318:
4319: case 0xBC: // cp_ixh
4320: Cp(m_regIXh);
4321: return 9;
4322:
4323: case 0xBD: // cp_ixl
4324: Cp(m_regIXl);
4325: return 9;
4326:
4327: case 0xBE: // cp_xix
4328: Cp(MemReadByte(IndirectIX()));
4329: return 19;
4330:
4331: case 0xBF: // no_op
4332: SetPC(GetPC() - 1);
4333: return 0;
4334:
4335: case 0xC0: // no_op
4336: SetPC(GetPC() - 1);
4337: return 0;
4338:
4339: case 0xC1: // no_op
4340: SetPC(GetPC() - 1);
4341: return 0;
4342:
4343: case 0xC2: // no_op
4344: SetPC(GetPC() - 1);
4345: return 0;
4346:
4347: case 0xC3: // no_op
4348: SetPC(GetPC() - 1);
4349: return 0;
4350:
4351: case 0xC4: // no_op
4352: SetPC(GetPC() - 1);
4353: return 0;
4354:
4355: case 0xC5: // no_op
4356: SetPC(GetPC() - 1);
4357: return 0;
4358:
4359: case 0xC6: // no_op
4360: SetPC(GetPC() - 1);
4361: return 0;
4362:
4363: case 0xC7: // no_op
4364: SetPC(GetPC() - 1);
4365: return 0;
4366:
4367: case 0xC8: // no_op
4368: SetPC(GetPC() - 1);
4369: return 0;
4370:
4371: case 0xC9: // no_op
4372: SetPC(GetPC() - 1);
4373: return 0;
4374:
4375: case 0xCA: // no_op
4376: SetPC(GetPC() - 1);
4377: return 0;
4378:
4379: case 0xCB: // dd_cb
4380: return HandleDDCB();
4381: break;
4382:
4383: case 0xCC: // no_op
4384: SetPC(GetPC() - 1);
4385: return 0;
4386:
4387: case 0xCD: // no_op
4388: SetPC(GetPC() - 1);
4389: return 0;
4390:
4391: case 0xCE: // no_op
4392: SetPC(GetPC() - 1);
4393: return 0;
4394:
4395: case 0xCF: // no_op
4396: SetPC(GetPC() - 1);
4397: return 0;
4398:
4399: case 0xD0: // no_op
4400: SetPC(GetPC() - 1);
4401: return 0;
4402:
4403: case 0xD1: // no_op
4404: SetPC(GetPC() - 1);
4405: return 0;
4406:
4407: case 0xD2: // no_op
4408: SetPC(GetPC() - 1);
4409: return 0;
4410:
4411: case 0xD3: // no_op
4412: SetPC(GetPC() - 1);
4413: return 0;
4414:
4415: case 0xD4: // no_op
4416: SetPC(GetPC() - 1);
4417: return 0;
4418:
4419: case 0xD5: // no_op
4420: SetPC(GetPC() - 1);
4421: return 0;
4422:
4423: case 0xD6: // no_op
4424: SetPC(GetPC() - 1);
4425: return 0;
4426:
4427: case 0xD7: // no_op
4428: SetPC(GetPC() - 1);
4429: return 0;
4430:
4431: case 0xD8: // no_op
4432: SetPC(GetPC() - 1);
4433: return 0;
4434:
4435: case 0xD9: // no_op
4436: SetPC(GetPC() - 1);
4437: return 0;
4438:
4439: case 0xDA: // no_op
4440: SetPC(GetPC() - 1);
4441: return 0;
4442:
4443: case 0xDB: // no_op
4444: SetPC(GetPC() - 1);
4445: return 0;
4446:
4447: case 0xDC: // no_op
4448: SetPC(GetPC() - 1);
4449: return 0;
4450:
4451: case 0xDD: // no_op
4452: SetPC(GetPC() - 1);
4453: return 0;
4454:
4455: case 0xDE: // no_op
4456: SetPC(GetPC() - 1);
4457: return 0;
4458:
4459: case 0xDF: // no_op
4460: SetPC(GetPC() - 1);
4461: return 0;
4462:
4463: case 0xE0: // no_op
4464: SetPC(GetPC() - 1);
4465: return 0;
4466:
4467: case 0xE1: // pop_ix
4468: m_regIX = Pop();
4469: return 14;
4470:
4471: case 0xE2: // no_op
4472: SetPC(GetPC() - 1);
4473: return 0;
4474:
4475: case 0xE3: // ex_xsp_ix
4476: wTemp = MemReadWord(GetSP());
4477: MemWriteWord(GetSP(), m_regIX);
4478: m_regIX = wTemp;
4479: return 23;
4480:
4481: case 0xE4: // no_op
4482: SetPC(GetPC() - 1);
4483: return 0;
4484:
4485: case 0xE5: // push_ix
4486: Push(m_regIX);
4487: return 15;
4488:
4489: case 0xE6: // no_op
4490: SetPC(GetPC() - 1);
4491: return 0;
4492:
4493: case 0xE7: // no_op
4494: SetPC(GetPC() - 1);
4495: return 0;
4496:
4497: case 0xE8: // no_op
4498: SetPC(GetPC() - 1);
4499: return 0;
4500:
4501: case 0xE9: // jp_ix
4502: SetPC(m_regIX);
4503: return 8;
4504:
4505: case 0xEA: // no_op
4506: SetPC(GetPC() - 1);
4507: return 0;
4508:
4509: case 0xEB: // no_op
4510: SetPC(GetPC() - 1);
4511: return 0;
4512:
4513: case 0xEC: // no_op
4514: SetPC(GetPC() - 1);
4515: return 0;
4516:
4517: case 0xED: // no_op
4518: SetPC(GetPC() - 1);
4519: return 0;
4520:
4521: case 0xEE: // no_op
4522: SetPC(GetPC() - 1);
4523: return 0;
4524:
4525: case 0xEF: // no_op
4526: SetPC(GetPC() - 1);
4527: return 0;
4528:
4529: case 0xF0: // no_op
4530: SetPC(GetPC() - 1);
4531: return 0;
4532:
4533: case 0xF1: // no_op
4534: SetPC(GetPC() - 1);
4535: return 0;
4536:
4537: case 0xF2: // no_op
4538: SetPC(GetPC() - 1);
4539: return 0;
4540:
4541: case 0xF3: // no_op
4542: SetPC(GetPC() - 1);
4543: return 0;
4544:
4545: case 0xF4: // no_op
4546: SetPC(GetPC() - 1);
4547: return 0;
4548:
4549: case 0xF5: // no_op
4550: SetPC(GetPC() - 1);
4551: return 0;
4552:
4553: case 0xF6: // no_op
4554: SetPC(GetPC() - 1);
4555: return 0;
4556:
4557: case 0xF7: // no_op
4558: SetPC(GetPC() - 1);
4559: return 0;
4560:
4561: case 0xF8: // no_op
4562: SetPC(GetPC() - 1);
4563: return 0;
4564:
4565: case 0xF9: // ld_sp_ix
4566: SetSP(m_regIX);
4567: return 10;
4568:
4569: case 0xFA: // no_op
4570: SetPC(GetPC() - 1);
4571: return 0;
4572:
4573: case 0xFB: // no_op
4574: SetPC(GetPC() - 1);
4575: return 0;
4576:
4577: case 0xFC: // no_op
4578: SetPC(GetPC() - 1);
4579: return 0;
4580:
4581: case 0xFD: // no_op
4582: SetPC(GetPC() - 1);
4583: return 0;
4584:
4585: case 0xFE: // no_op
4586: SetPC(GetPC() - 1);
4587: return 0;
4588:
4589: case 0xFF: // no_op
4590: SetPC(GetPC() - 1);
4591: return 0;
4592:
4593: default:
4594: return 0;
4595: }
4596: }
4597:
4598: /* ***************************************************************************
4599: * ED prefixed opcodes
4600: * ***************************************************************************
4601: */
4602: int HandleED(int cCyclesArg) {
4603:
4604: const BYTE bOpcode = ImmedByte();
4605: int cCycles = cCyclesArg;
4606:
4607: m_regR++;
4608:
4609: switch (bOpcode)
4610: {
4611: case 0x00: // nop
4612: cCycles -= 0;
4613: break;
4614:
4615: case 0x01: // nop
4616: cCycles -= 0;
4617: break;
4618:
4619: case 0x02: // nop
4620: cCycles -= 0;
4621: break;
4622:
4623: case 0x03: // nop
4624: cCycles -= 0;
4625: break;
4626:
4627: case 0x04: // nop
4628: cCycles -= 0;
4629: break;
4630:
4631: case 0x05: // nop
4632: cCycles -= 0;
4633: break;
4634:
4635: case 0x06: // nop
4636: cCycles -= 0;
4637: break;
4638:
4639: case 0x07: // nop
4640: cCycles -= 0;
4641: break;
4642:
4643: case 0x08: // nop
4644: cCycles -= 0;
4645: break;
4646:
4647: case 0x09: // nop
4648: cCycles -= 0;
4649: break;
4650:
4651: case 0x0A: // nop
4652: cCycles -= 0;
4653: break;
4654:
4655: case 0x0B: // nop
4656: cCycles -= 0;
4657: break;
4658:
4659: case 0x0C: // nop
4660: cCycles -= 0;
4661: break;
4662:
4663: case 0x0D: // nop
4664: cCycles -= 0;
4665: break;
4666:
4667: case 0x0E: // nop
4668: cCycles -= 0;
4669: break;
4670:
4671: case 0x0F: // nop
4672: cCycles -= 0;
4673: break;
4674:
4675: case 0x10: // nop
4676: cCycles -= 0;
4677: break;
4678:
4679: case 0x11: // nop
4680: cCycles -= 0;
4681: break;
4682:
4683: case 0x12: // nop
4684: cCycles -= 0;
4685: break;
4686:
4687: case 0x13: // nop
4688: cCycles -= 0;
4689: break;
4690:
4691: case 0x14: // nop
4692: cCycles -= 0;
4693: break;
4694:
4695: case 0x15: // nop
4696: cCycles -= 0;
4697: break;
4698:
4699: case 0x16: // nop
4700: cCycles -= 0;
4701: break;
4702:
4703: case 0x17: // nop
4704: cCycles -= 0;
4705: break;
4706:
4707: case 0x18: // nop
4708: cCycles -= 0;
4709: break;
4710:
4711: case 0x19: // nop
4712: cCycles -= 0;
4713: break;
4714:
4715: case 0x1A: // nop
4716: cCycles -= 0;
4717: break;
4718:
4719: case 0x1B: // nop
4720: cCycles -= 0;
4721: break;
4722:
4723: case 0x1C: // nop
4724: cCycles -= 0;
4725: break;
4726:
4727: case 0x1D: // nop
4728: cCycles -= 0;
4729: break;
4730:
4731: case 0x1E: // nop
4732: cCycles -= 0;
4733: break;
4734:
4735: case 0x1F: // nop
4736: cCycles -= 0;
4737: break;
4738:
4739: case 0x20: // nop
4740: cCycles -= 0;
4741: break;
4742:
4743: case 0x21: // nop
4744: cCycles -= 0;
4745: break;
4746:
4747: case 0x22: // nop
4748: cCycles -= 0;
4749: break;
4750:
4751: case 0x23: // nop
4752: cCycles -= 0;
4753: break;
4754:
4755: case 0x24: // nop
4756: cCycles -= 0;
4757: break;
4758:
4759: case 0x25: // nop
4760: cCycles -= 0;
4761: break;
4762:
4763: case 0x26: // nop
4764: cCycles -= 0;
4765: break;
4766:
4767: case 0x27: // nop
4768: cCycles -= 0;
4769: break;
4770:
4771: case 0x28: // nop
4772: cCycles -= 0;
4773: break;
4774:
4775: case 0x29: // nop
4776: cCycles -= 0;
4777: break;
4778:
4779: case 0x2A: // nop
4780: cCycles -= 0;
4781: break;
4782:
4783: case 0x2B: // nop
4784: cCycles -= 0;
4785: break;
4786:
4787: case 0x2C: // nop
4788: cCycles -= 0;
4789: break;
4790:
4791: case 0x2D: // nop
4792: cCycles -= 0;
4793: break;
4794:
4795: case 0x2E: // nop
4796: cCycles -= 0;
4797: break;
4798:
4799: case 0x2F: // nop
4800: cCycles -= 0;
4801: break;
4802:
4803: case 0x30: // nop
4804: cCycles -= 0;
4805: break;
4806:
4807: case 0x31: // nop
4808: cCycles -= 0;
4809: break;
4810:
4811: case 0x32: // nop
4812: cCycles -= 0;
4813: break;
4814:
4815: case 0x33: // nop
4816: cCycles -= 0;
4817: break;
4818:
4819: case 0x34: // nop
4820: cCycles -= 0;
4821: break;
4822:
4823: case 0x35: // nop
4824: cCycles -= 0;
4825: break;
4826:
4827: case 0x36: // nop
4828: cCycles -= 0;
4829: break;
4830:
4831: case 0x37: // nop
4832: cCycles -= 0;
4833: break;
4834:
4835: case 0x38: // nop
4836: cCycles -= 0;
4837: break;
4838:
4839: case 0x39: // nop
4840: cCycles -= 0;
4841: break;
4842:
4843: case 0x3A: // nop
4844: cCycles -= 0;
4845: break;
4846:
4847: case 0x3B: // nop
4848: cCycles -= 0;
4849: break;
4850:
4851: case 0x3C: // nop
4852: cCycles -= 0;
4853: break;
4854:
4855: case 0x3D: // nop
4856: cCycles -= 0;
4857: break;
4858:
4859: case 0x3E: // nop
4860: cCycles -= 0;
4861: break;
4862:
4863: case 0x3F: // nop
4864: cCycles -= 0;
4865: break;
4866:
4867: case 0x40: // in_b_c
4868: cCycles -= 12;
4869: m_regB = In(m_regC);
4870: break;
4871:
4872: case 0x41: // out_c_b
4873: cCycles -= 12;
4874: Out(m_regC, m_regB);
4875: break;
4876:
4877: case 0x42: // sbc_hl_bc
4878: cCycles -= 15;
4879: m_regHL = Sbc_2(m_regHL, m_regBC);
4880: break;
4881:
4882: case 0x43: // ld_xword_bc
4883: cCycles -= 20;
4884: MemWriteWord(ImmedWord(), m_regBC);
4885: break;
4886:
4887: case 0x44: // neg
4888: cCycles -= 8;
4889: {
4890: BYTE b = m_regA;
4891: m_regA = 0;
4892: Sub_1(b);
4893: break;
4894: }
4895:
4896: case 0x45: // retn
4897: cCycles -= 8;
4898: m_iff1 = m_iff2;
4899: cCycles -= Ret0(TRUE);
4900: break;
4901:
4902: case 0x46: // im_0
4903: cCycles -= 8;
4904: m_nIM = 0;
4905: break;
4906:
4907: case 0x47: // ld_i_a
4908: cCycles -= 9;
4909: m_regI = m_regA;
4910: break;
4911:
4912: case 0x48: // in_c_c
4913: cCycles -= 12;
4914: m_regC = In(m_regC);
4915: break;
4916:
4917: case 0x49: // out_c_c
4918: cCycles -= 12;
4919: Out(m_regC, m_regC);
4920: break;
4921:
4922: case 0x4A: // adc_hl_bc
4923: cCycles -= 15;
4924: m_regHL = Adc_2(m_regHL, m_regBC);
4925: break;
4926:
4927: case 0x4B: // ld_bc_xword
4928: cCycles -= 20;
4929: m_regBC = MemReadWord(ImmedWord());
4930: break;
4931:
4932: case 0x4C: // neg
4933: cCycles -= 8;
4934: {
4935: BYTE b = m_regA;
4936: m_regA = 0;
4937: Sub_1(b);
4938: break;
4939: }
4940:
4941: case 0x4D: // reti
4942: cCycles -= 8;
4943: cCycles -= Ret0(TRUE);
4944: break;
4945:
4946: case 0x4E: // im_0
4947: cCycles -= 8;
4948: m_nIM = 0;
4949: break;
4950:
4951: case 0x4F: // ld_r_a
4952: cCycles -= 9;
4953: m_regR = m_regA;
4954: // m_regR2 = m_regA;
4955: break;
4956:
4957: case 0x50: // in_d_c
4958: cCycles -= 12;
4959: m_regD = In(m_regC);
4960: break;
4961:
4962: case 0x51: // out_c_d
4963: cCycles -= 12;
4964: Out(m_regC, m_regD);
4965: break;
4966:
4967: case 0x52: // sbc_hl_de
4968: cCycles -= 15;
4969: m_regHL = Sbc_2(m_regHL, m_regDE);
4970: break;
4971:
4972: case 0x53: // ld_xword_de
4973: cCycles -= 20;
4974: MemWriteWord(ImmedWord(), m_regDE);
4975: break;
4976:
4977: case 0x54: // neg
4978: cCycles -= 8;
4979: {
4980: BYTE b = m_regA;
4981: m_regA = 0;
4982: Sub_1(b);
4983: break;
4984: }
4985:
4986: case 0x55: // retn
4987: cCycles -= 8;
4988: m_iff1 = m_iff2;
4989: cCycles -= Ret0(TRUE);
4990: break;
4991:
4992: case 0x56: // im_1
4993: cCycles -= 8;
4994: m_nIM = 1;
4995: break;
4996:
4997: case 0x57: // ld_a_i
4998: cCycles -= 9;
4999: m_regA = m_regI;
5000: m_regF = (m_regF & C_FLAG)| ZSTable[m_regI] | (m_iff2 << 2);
5001: break;
5002:
5003: case 0x58: // in_e_c
5004: cCycles -= 12;
5005: m_regE = In(m_regC);
5006: break;
5007:
5008: case 0x59: // out_c_e
5009: cCycles -= 12;
5010: Out(m_regC, m_regE);
5011: break;
5012:
5013: case 0x5A: // adc_hl_de
5014: cCycles -= 15;
5015: m_regHL = Adc_2(m_regHL, m_regDE);
5016: break;
5017:
5018: case 0x5B: // ld_de_xword
5019: cCycles -= 20;
5020: m_regDE = MemReadWord(ImmedWord());
5021: break;
5022:
5023: case 0x5C: // neg
5024: cCycles -= 8;
5025: {
5026: BYTE b = m_regA;
5027: m_regA = 0;
5028: Sub_1(b);
5029: break;
5030: }
5031:
5032: case 0x5D: // reti
5033: cCycles -= 8;
5034: cCycles -= Ret0(TRUE);
5035: break;
5036:
5037: case 0x5E: // im_2
5038: cCycles -= 8;
5039: m_nIM = 2;
5040: break;
5041:
5042: case 0x5F: // ld_a_r
5043: cCycles -= 9;
5044: m_regA = (m_regR & 0x7F); /////////////////////////////////////// | (m_regR2 & 0x80);
5045: m_regF = (m_regF & C_FLAG) | ZSTable[m_regA] | (m_iff2 << 2);
5046: break;
5047:
5048: case 0x60: // in_h_c
5049: cCycles -= 12;
5050: m_regH = In(m_regC);
5051: break;
5052:
5053: case 0x61: // out_c_h
5054: cCycles -= 12;
5055: Out(m_regC, m_regH);
5056: break;
5057:
5058: case 0x62: // sbc_hl_hl
5059: cCycles -= 15;
5060: m_regHL = Sbc_2(m_regHL, m_regHL);
5061: break;
5062:
5063: case 0x63: // ld_xword_hl
5064: cCycles -= 20;
5065: MemWriteWord(ImmedWord(), m_regHL);
5066: break;
5067:
5068: case 0x64: // neg
5069: cCycles -= 8;
5070: {
5071: BYTE b = m_regA;
5072: m_regA = 0;
5073: Sub_1(b);
5074: break;
5075: }
5076:
5077: case 0x65: // retn
5078: cCycles -= 8;
5079: m_iff1 = m_iff2;
5080: cCycles -= Ret0(TRUE);
5081: break;
5082:
5083: case 0x66: // im_0
5084: cCycles -= 8;
5085: m_nIM = 0;
5086: break;
5087:
5088: case 0x67: // rrd
5089: cCycles -= 18;
5090: {
5091: BYTE i = MemReadByte(m_regHL);
5092: MemWriteByte(m_regHL, (i>>4) | (m_regA << 4));
5093: m_regA = (m_regA & 0xF0) | (i&0x0F);
5094: m_regF =(m_regF&C_FLAG)|ZSPTable[m_regA];
5095: break;
5096: }
5097:
5098: case 0x68: // in_l_c
5099: cCycles -= 12;
5100: m_regL = In(m_regC);
5101: break;
5102:
5103: case 0x69: // out_c_l
5104: cCycles -= 12;
5105: Out(m_regC, m_regL);
5106: break;
5107:
5108: case 0x6A: // adc_hl_hl
5109: cCycles -= 15;
5110: m_regHL = Adc_2(m_regHL, m_regHL);
5111: break;
5112:
5113: case 0x6B: // ld_hl_xword
5114: cCycles -= 20;
5115: m_regHL = MemReadWord(ImmedWord());
5116: break;
5117:
5118: case 0x6C: // neg
5119: cCycles -= 8;
5120: {
5121: BYTE b = m_regA;
5122: m_regA = 0;
5123: Sub_1(b);
5124: break;
5125: }
5126:
5127: case 0x6D: // reti
5128: cCycles -= 8;
5129: cCycles -= Ret0(TRUE);
5130: break;
5131:
5132: case 0x6E: // im_0
5133: cCycles -= 8;
5134: m_nIM = 0;
5135: break;
5136:
5137: case 0x6F: // rld
5138: cCycles -= 18;
5139: {
5140: BYTE i;
5141: i=MemReadByte(m_regHL);
5142: MemWriteByte(m_regHL,(i<<4)|(m_regA&0x0F));
5143: m_regA=(m_regA&0xF0)|(i>>4);
5144: m_regF=(m_regF&C_FLAG)|ZSPTable[m_regA];
5145: break;
5146: }
5147:
5148: case 0x70: // in_0_c
5149: cCycles -= 12;
5150: In(m_regC);
5151: break;
5152:
5153: case 0x71: // out_c_0
5154: cCycles -= 12;
5155: Out(m_regC, 0);
5156: break;
5157:
5158: case 0x72: // sbc_hl_sp
5159: cCycles -= 15;
5160: m_regHL = Sbc_2(m_regHL, GetSP());
5161: break;
5162:
5163: case 0x73: // ld_xword_sp
5164: cCycles -= 20;
5165: MemWriteWord(ImmedWord(), GetSP());
5166: break;
5167:
5168: case 0x74: // neg
5169: cCycles -= 8;
5170: {
5171: BYTE b = m_regA;
5172: m_regA = 0;
5173: Sub_1(b);
5174: break;
5175: }
5176:
5177: case 0x75: // retn
5178: cCycles -= 8;
5179: m_iff1 = m_iff2;
5180: cCycles -= Ret0(TRUE);
5181: break;
5182:
5183: case 0x76: // im_1
5184: cCycles -= 8;
5185: m_nIM = 1;
5186: break;
5187:
5188: case 0x77: // nop
5189: cCycles -= 0;
5190: break;
5191:
5192: case 0x78: // in_a_c
5193: cCycles -= 12;
5194: m_regA = In(m_regC);
5195: break;
5196:
5197: case 0x79: // out_c_a
5198: cCycles -= 12;
5199: Out(m_regC, m_regA);
5200: break;
5201:
5202: case 0x7A: // adc_hl_sp
5203: cCycles -= 15;
5204: m_regHL = Adc_2(m_regHL, GetSP());
5205: break;
5206:
5207: case 0x7B: // ld_sp_xword
5208: cCycles -= 20;
5209: SetSP(MemReadWord(ImmedWord()));
5210: break;
5211:
5212: case 0x7C: // neg
5213: cCycles -= 8;
5214: {
5215: BYTE b = m_regA;
5216: m_regA = 0;
5217: Sub_1(b);
5218: break;
5219: }
5220:
5221: case 0x7D: // reti
5222: cCycles -= 8;
5223: cCycles -= Ret0(TRUE);
5224: break;
5225:
5226: case 0x7E: // im_2
5227: cCycles -= 8;
5228: m_nIM = 2;
5229: break;
5230:
5231: case 0x7F: // nop
5232: cCycles -= 0;
5233: break;
5234:
5235: case 0x80: // nop
5236: cCycles -= 0;
5237: break;
5238:
5239: case 0x81: // nop
5240: cCycles -= 0;
5241: break;
5242:
5243: case 0x82: // nop
5244: cCycles -= 0;
5245: break;
5246:
5247: case 0x83: // nop
5248: cCycles -= 0;
5249: break;
5250:
5251: case 0x84: // nop
5252: cCycles -= 0;
5253: break;
5254:
5255: case 0x85: // nop
5256: cCycles -= 0;
5257: break;
5258:
5259: case 0x86: // nop
5260: cCycles -= 0;
5261: break;
5262:
5263: case 0x87: // nop
5264: cCycles -= 0;
5265: break;
5266:
5267: case 0x88: // nop
5268: cCycles -= 0;
5269: break;
5270:
5271: case 0x89: // nop
5272: cCycles -= 0;
5273: break;
5274:
5275: case 0x8A: // nop
5276: cCycles -= 0;
5277: break;
5278:
5279: case 0x8B: // nop
5280: cCycles -= 0;
5281: break;
5282:
5283: case 0x8C: // nop
5284: cCycles -= 0;
5285: break;
5286:
5287: case 0x8D: // nop
5288: cCycles -= 0;
5289: break;
5290:
5291: case 0x8E: // nop
5292: cCycles -= 0;
5293: break;
5294:
5295: case 0x8F: // nop
5296: cCycles -= 0;
5297: break;
5298:
5299: case 0x90: // nop
5300: cCycles -= 0;
5301: break;
5302:
5303: case 0x91: // nop
5304: cCycles -= 0;
5305: break;
5306:
5307: case 0x92: // nop
5308: cCycles -= 0;
5309: break;
5310:
5311: case 0x93: // nop
5312: cCycles -= 0;
5313: break;
5314:
5315: case 0x94: // nop
5316: cCycles -= 0;
5317: break;
5318:
5319: case 0x95: // nop
5320: cCycles -= 0;
5321: break;
5322:
5323: case 0x96: // nop
5324: cCycles -= 0;
5325: break;
5326:
5327: case 0x97: // nop
5328: cCycles -= 0;
5329: break;
5330:
5331: case 0x98: // nop
5332: cCycles -= 0;
5333: break;
5334:
5335: case 0x99: // nop
5336: cCycles -= 0;
5337: break;
5338:
5339: case 0x9A: // nop
5340: cCycles -= 0;
5341: break;
5342:
5343: case 0x9B: // nop
5344: cCycles -= 0;
5345: break;
5346:
5347: case 0x9C: // nop
5348: cCycles -= 0;
5349: break;
5350:
5351: case 0x9D: // nop
5352: cCycles -= 0;
5353: break;
5354:
5355: case 0x9E: // nop
5356: cCycles -= 0;
5357: break;
5358:
5359: case 0x9F: // nop
5360: cCycles -= 0;
5361: break;
5362:
5363: case 0xA0: // ldi
5364: cCycles -= 16;
5365: {
5366: MemWriteByte(m_regDE++, MemReadByte(m_regHL++));
5367: m_regBC--;
5368: m_regF = (m_regF & 0xE9) | (m_regBC ? V_FLAG : 0);
5369: break;
5370: }
5371:
5372: case 0xA1: // cpi
5373: cCycles -= 16;
5374: {
5375: BYTE i,j;
5376: i=MemReadByte(m_regHL);
5377: j=m_regA-i;
5378: ++m_regHL;
5379: --m_regBC;
5380: m_regF=(m_regF&C_FLAG)|ZSTable[j]|
5381: ((m_regA^i^j)&H_FLAG)|(m_regBC? V_FLAG:0)|N_FLAG;
5382: break;
5383: }
5384:
5385: case 0xA2: // ini
5386: cCycles -= 16;
5387: {
5388: MemWriteByte(m_regHL,In(m_regC));
5389: ++m_regHL;
5390: --m_regB;
5391: m_regF=(m_regB)? N_FLAG:(N_FLAG|Z_FLAG);
5392: break;
5393: }
5394:
5395: case 0xA3: // outi
5396: cCycles -= 16;
5397: {
5398: Out(m_regC, MemReadByte(m_regHL));
5399: ++m_regHL;
5400: --m_regB;
5401: m_regF=(m_regB)? N_FLAG:(Z_FLAG|N_FLAG);
5402: break;
5403: }
5404:
5405: case 0xA4: // nop
5406: cCycles -= 0;
5407: break;
5408:
5409: case 0xA5: // nop
5410: cCycles -= 0;
5411: break;
5412:
5413: case 0xA6: // nop
5414: cCycles -= 0;
5415: break;
5416:
5417: case 0xA7: // nop
5418: cCycles -= 0;
5419: break;
5420:
5421: case 0xA8: // ldd
5422: cCycles -= 16;
5423: {
5424: MemWriteByte(m_regDE,MemReadByte(m_regHL));
5425: --m_regDE;
5426: --m_regHL;
5427: --m_regBC;
5428: m_regF=(m_regF&0xE9)|(m_regBC? V_FLAG:0);
5429: break;
5430: }
5431:
5432: case 0xA9: // cpd
5433: cCycles -= 16;
5434: {
5435: BYTE i,j;
5436: i=MemReadByte(m_regHL);
5437: j=m_regA-i;
5438: --m_regHL;
5439: --m_regBC;
5440: m_regF=(m_regF&C_FLAG)|ZSTable[j]|
5441: ((m_regA^i^j)&H_FLAG)|(m_regBC? V_FLAG:0)|N_FLAG;
5442: break;
5443: }
5444:
5445: case 0xAA: // ind
5446: cCycles -= 16;
5447: {
5448: MemWriteByte(m_regHL,In(m_regC));
5449: --m_regHL;
5450: --m_regB;
5451: m_regF=(m_regB)? N_FLAG:(N_FLAG|Z_FLAG);
5452: break;
5453: }
5454:
5455: case 0xAB: // outd
5456: cCycles -= 16;
5457: {
5458: Out (m_regC,MemReadByte(m_regHL));
5459: --m_regHL;
5460: --m_regB;
5461: m_regF=(m_regB)? N_FLAG:(Z_FLAG|N_FLAG);
5462: break;
5463: }
5464:
5465: case 0xAC: // nop
5466: cCycles -= 0;
5467: break;
5468:
5469: case 0xAD: // nop
5470: cCycles -= 0;
5471: break;
5472:
5473: case 0xAE: // nop
5474: cCycles -= 0;
5475: break;
5476:
5477: case 0xAF: // nop
5478: cCycles -= 0;
5479: break;
5480:
5481: case 0xB0: // ldir
5482: cCycles -= 0;
5483: {
5484: m_regR -= 2;
5485:
5486: /*
5487: if (m_rgfMemDesc[m_regHL] & MF_READ_DIRECT &&
5488: m_rgfMemDesc[m_regDE] & MF_WRITE_DIRECT)
5489: {
5490: do
5491: {
5492: m_regR += 2;
5493: m_rgbMemory[m_regDE++] = m_rgbMemory[m_regHL++];
5494: cCycles -= 21;
5495: }
5496: while (--m_regBC); // && cCycles>0);
5497:
5498: m_regF=(m_regF&0xE9)|(m_regBC? V_FLAG:0);
5499:
5500: if (m_regBC)
5501: // m_regPC -= 2;
5502: AdjustPC(-2);
5503: else
5504: cCycles += 5;
5505: }
5506: else
5507: */
5508: {
5509: do
5510: {
5511: m_regR += 2;
5512: MemWriteByte(m_regDE++, MemReadByte(m_regHL++));
5513: cCycles -= 21;
5514: }
5515: while (--m_regBC); // && cCycles>0);
5516:
5517: m_regF=(m_regF&0xE9)|(m_regBC? V_FLAG:0);
5518:
5519: if (m_regBC)
5520: // m_regPC -= 2;
5521: AdjustPC(-2);
5522: else
5523: cCycles += 5;
5524: }
5525:
5526: break;
5527: }
5528:
5529: case 0xB1: // cpir
5530: cCycles -= 0;
5531: {
5532: BYTE i,j;
5533: m_regR-=2;
5534: do
5535: {
5536: m_regR+=2;
5537: i=MemReadByte(m_regHL);
5538: j=m_regA-i;
5539: ++m_regHL;
5540: --m_regBC;
5541: cCycles-=21;
5542: }
5543: while (m_regBC && j && cCycles>0);
5544: m_regF=(m_regF&C_FLAG)|ZSTable[j]|
5545: ((m_regA^i^j)&H_FLAG)|(m_regBC? V_FLAG:0)|N_FLAG;
5546: if (m_regBC && j) AdjustPC(-2); // m_regPC-=2;
5547: else cCycles+=5;
5548: break;
5549: }
5550:
5551: case 0xB2: // inir
5552: cCycles -= 0;
5553: {
5554: m_regR-=2;
5555: do
5556: {
5557: m_regR+=2;
5558: MemWriteByte(m_regHL,In(m_regC));
5559: ++m_regHL;
5560: --m_regB;
5561: cCycles-=21;
5562: }
5563: while (m_regB && cCycles>0);
5564: m_regF=(m_regB)? N_FLAG:(N_FLAG|Z_FLAG);
5565: if (m_regB) AdjustPC(-2); // m_regPC-=2;
5566: else cCycles+=5;
5567: break;
5568: }
5569:
5570: case 0xB3: // otir
5571: cCycles -= 0;
5572: {
5573: m_regR-=2;
5574: do
5575: {
5576: m_regR+=2;
5577: Out (m_regC,MemReadByte(m_regHL));
5578: ++m_regHL;
5579: --m_regB;
5580: cCycles-=21;
5581: }
5582: while (m_regB && cCycles>0);
5583: m_regF=(m_regB)? N_FLAG:(Z_FLAG|N_FLAG);
5584: if (m_regB) AdjustPC(-2); // m_regPC-=2;
5585: else cCycles+=5;
5586: }
5587: break;
5588:
5589: case 0xB4: // nop
5590: cCycles -= 0;
5591: break;
5592:
5593: case 0xB5: // nop
5594: cCycles -= 0;
5595: break;
5596:
5597: case 0xB6: // nop
5598: cCycles -= 0;
5599: break;
5600:
5601: case 0xB7: // nop
5602: cCycles -= 0;
5603: break;
5604:
5605: case 0xB8: // lddr
5606: cCycles -= 0;
5607: {
5608: m_regR-=2;
5609: do
5610: {
5611: m_regR+=2;
5612: MemWriteByte(m_regDE,MemReadByte(m_regHL));
5613: --m_regDE;
5614: --m_regHL;
5615: --m_regBC;
5616: cCycles-=21;
5617: }
5618: while (m_regBC);
5619: m_regF=(m_regF&0xE9)|(m_regBC? V_FLAG:0);
5620: if (m_regBC) AdjustPC(-2); // m_regPC-=2;
5621: else
5622: cCycles+=5;
5623: break;
5624: }
5625:
5626: case 0xB9: // cpdr
5627: cCycles -= 0;
5628: {
5629: BYTE i,j;
5630: m_regR-=2;
5631: do
5632: {
5633: m_regR+=2;
5634: i=MemReadByte(m_regHL);
5635: j=m_regA-i;
5636: --m_regHL;
5637: --m_regBC;
5638: cCycles-=21;
5639: }
5640: while (m_regBC && j && cCycles>0);
5641: m_regF=(m_regF&C_FLAG)|ZSTable[j]|
5642: ((m_regA^i^j)&H_FLAG)|(m_regBC? V_FLAG:0)|N_FLAG;
5643: if (m_regBC && j) AdjustPC(-2); // m_regPC-=2;
5644: else cCycles+=5;
5645: break;
5646: }
5647:
5648: case 0xBA: // indr
5649: cCycles -= 0;
5650: {
5651: m_regR-=2;
5652: do
5653: {
5654: m_regR+=2;
5655: MemWriteByte(m_regHL,In(m_regC));
5656: --m_regHL;
5657: --m_regB;
5658: cCycles-=21;
5659: }
5660: while (m_regB && cCycles>0);
5661: m_regF=(m_regB)? N_FLAG:(N_FLAG|Z_FLAG);
5662: if (m_regB) AdjustPC(-2); // m_regPC-=2;
5663: else cCycles+=5;
5664: break;
5665: }
5666:
5667: case 0xBB: // otdr
5668: cCycles -= 0;
5669: {
5670: m_regR-=2;
5671: do
5672: {
5673: m_regR+=2;
5674: Out (m_regC,MemReadByte(m_regHL));
5675: --m_regHL;
5676: --m_regB;
5677: cCycles-=21;
5678: }
5679: while (m_regB && cCycles>0);
5680: m_regF=(m_regB)? N_FLAG:(Z_FLAG|N_FLAG);
5681: if (m_regB) AdjustPC(-2); // m_regPC-=2;
5682: else cCycles+=5;
5683: break;
5684: }
5685:
5686: case 0xBC: // nop
5687: cCycles -= 0;
5688: break;
5689:
5690: case 0xBD: // nop
5691: cCycles -= 0;
5692: break;
5693:
5694: case 0xBE: // nop
5695: cCycles -= 0;
5696: break;
5697:
5698: case 0xBF: // nop
5699: cCycles -= 0;
5700: break;
5701:
5702: case 0xC0: // nop
5703: cCycles -= 0;
5704: break;
5705:
5706: case 0xC1: // nop
5707: cCycles -= 0;
5708: break;
5709:
5710: case 0xC2: // nop
5711: cCycles -= 0;
5712: break;
5713:
5714: case 0xC3: // nop
5715: cCycles -= 0;
5716: break;
5717:
5718: case 0xC4: // nop
5719: cCycles -= 0;
5720: break;
5721:
5722: case 0xC5: // nop
5723: cCycles -= 0;
5724: break;
5725:
5726: case 0xC6: // nop
5727: cCycles -= 0;
5728: break;
5729:
5730: case 0xC7: // nop
5731: cCycles -= 0;
5732: break;
5733:
5734: case 0xC8: // nop
5735: cCycles -= 0;
5736: break;
5737:
5738: case 0xC9: // nop
5739: cCycles -= 0;
5740: break;
5741:
5742: case 0xCA: // nop
5743: cCycles -= 0;
5744: break;
5745:
5746: case 0xCB: // nop
5747: cCycles -= 0;
5748: break;
5749:
5750: case 0xCC: // nop
5751: cCycles -= 0;
5752: break;
5753:
5754: case 0xCD: // nop
5755: cCycles -= 0;
5756: break;
5757:
5758: case 0xCE: // nop
5759: cCycles -= 0;
5760: break;
5761:
5762: case 0xCF: // nop
5763: cCycles -= 0;
5764: break;
5765:
5766: case 0xD0: // nop
5767: cCycles -= 0;
5768: break;
5769:
5770: case 0xD1: // nop
5771: cCycles -= 0;
5772: break;
5773:
5774: case 0xD2: // nop
5775: cCycles -= 0;
5776: break;
5777:
5778: case 0xD3: // nop
5779: cCycles -= 0;
5780: break;
5781:
5782: case 0xD4: // nop
5783: cCycles -= 0;
5784: break;
5785:
5786: case 0xD5: // nop
5787: cCycles -= 0;
5788: break;
5789:
5790: case 0xD6: // nop
5791: cCycles -= 0;
5792: break;
5793:
5794: case 0xD7: // nop
5795: cCycles -= 0;
5796: break;
5797:
5798: case 0xD8: // nop
5799: cCycles -= 0;
5800: break;
5801:
5802: case 0xD9: // nop
5803: cCycles -= 0;
5804: break;
5805:
5806: case 0xDA: // nop
5807: cCycles -= 0;
5808: break;
5809:
5810: case 0xDB: // nop
5811: cCycles -= 0;
5812: break;
5813:
5814: case 0xDC: // nop
5815: cCycles -= 0;
5816: break;
5817:
5818: case 0xDD: // nop
5819: cCycles -= 0;
5820: break;
5821:
5822: case 0xDE: // nop
5823: cCycles -= 0;
5824: break;
5825:
5826: case 0xDF: // nop
5827: cCycles -= 0;
5828: break;
5829:
5830: case 0xE0: // nop
5831: cCycles -= 0;
5832: break;
5833:
5834: case 0xE1: // nop
5835: cCycles -= 0;
5836: break;
5837:
5838: case 0xE2: // nop
5839: cCycles -= 0;
5840: break;
5841:
5842: case 0xE3: // nop
5843: cCycles -= 0;
5844: break;
5845:
5846: case 0xE4: // nop
5847: cCycles -= 0;
5848: break;
5849:
5850: case 0xE5: // nop
5851: cCycles -= 0;
5852: break;
5853:
5854: case 0xE6: // nop
5855: cCycles -= 0;
5856: break;
5857:
5858: case 0xE7: // nop
5859: cCycles -= 0;
5860: break;
5861:
5862: case 0xE8: // nop
5863: cCycles -= 0;
5864: break;
5865:
5866: case 0xE9: // nop
5867: cCycles -= 0;
5868: break;
5869:
5870: case 0xEA: // nop
5871: cCycles -= 0;
5872: break;
5873:
5874: case 0xEB: // nop
5875: cCycles -= 0;
5876: break;
5877:
5878: case 0xEC: // nop
5879: cCycles -= 0;
5880: break;
5881:
5882: case 0xED: // nop
5883: cCycles -= 0;
5884: break;
5885:
5886: case 0xEE: // nop
5887: cCycles -= 0;
5888: break;
5889:
5890: case 0xEF: // nop
5891: cCycles -= 0;
5892: break;
5893:
5894: case 0xF0: // nop
5895: cCycles -= 0;
5896: break;
5897:
5898: case 0xF1: // nop
5899: cCycles -= 0;
5900: break;
5901:
5902: case 0xF2: // nop
5903: cCycles -= 0;
5904: break;
5905:
5906: case 0xF3: // nop
5907: cCycles -= 0;
5908: break;
5909:
5910: case 0xF4: // nop
5911: cCycles -= 0;
5912: break;
5913:
5914: case 0xF5: // nop
5915: cCycles -= 0;
5916: break;
5917:
5918: case 0xF6: // nop
5919: cCycles -= 0;
5920: break;
5921:
5922: case 0xF7: // nop
5923: cCycles -= 0;
5924: break;
5925:
5926: case 0xF8: // nop
5927: cCycles -= 0;
5928: break;
5929:
5930: case 0xF9: // nop
5931: cCycles -= 0;
5932: break;
5933:
5934: case 0xFA: // nop
5935: cCycles -= 0;
5936: break;
5937:
5938: case 0xFB: // nop
5939: cCycles -= 0;
5940: break;
5941:
5942: case 0xFC: // nop
5943: cCycles -= 0;
5944: break;
5945:
5946: case 0xFD: // nop
5947: cCycles -= 0;
5948: break;
5949:
5950: case 0xFE: // patch
5951: cCycles -= 0;
5952: break;
5953:
5954: case 0xFF: // nop
5955: cCycles -= 0;
5956: break;
5957:
5958: default:
5959: _ASSERT(FALSE);
5960: break;
5961: }
5962:
5963: return (cCyclesArg - cCycles);
5964: }
5965:
5966: int Ei() {
5967: /* fprintf ( stderr, "Enable Interrupt\n" ); */
5968: m_iff2 = 1;
5969:
5970: if (m_iff1 != 0)
5971: return 0;
5972:
5973: m_iff1 = 1;
5974:
5975: return(0);
5976: }
5977:
5978: void Di() {
5979: /* fprintf ( stderr, "Disable Interrupt\n" ); */
5980: m_iff1 = 0;
5981: m_iff2 = 0;
5982: }
5983:
5984: /* ***************************************************************************
5985: * FD prefixed opcodes
5986: * ***************************************************************************
5987: */
5988: /* inline */ WORD IndirectIY() {
5989: return m_regIY + (signed char)ImmedByte();
5990: }
5991:
5992: int HandleFD() {
5993:
5994: WORD wAddr;
5995: WORD wTemp;
5996: const BYTE bOpcode = ImmedByte();
5997:
5998: m_regR++;
5999:
6000: switch (bOpcode)
6001: {
6002: case 0x00: // no_op
6003: SetPC(GetPC() - 1);
6004: return 0;
6005:
6006: case 0x01: // no_op
6007: SetPC(GetPC() - 1);
6008: return 0;
6009:
6010: case 0x02: // no_op
6011: SetPC(GetPC() - 1);
6012: return 0;
6013:
6014: case 0x03: // no_op
6015: SetPC(GetPC() - 1);
6016: return 0;
6017:
6018: case 0x04: // no_op
6019: SetPC(GetPC() - 1);
6020: return 0;
6021:
6022: case 0x05: // no_op
6023: SetPC(GetPC() - 1);
6024: return 0;
6025:
6026: case 0x06: // no_op
6027: SetPC(GetPC() - 1);
6028: return 0;
6029:
6030: case 0x07: // no_op
6031: SetPC(GetPC() - 1);
6032: return 0;
6033:
6034: case 0x08: // no_op
6035: SetPC(GetPC() - 1);
6036: return 0;
6037:
6038: case 0x09: // add_iy_bc
6039: m_regIY = Add_2(m_regIY, m_regBC);
6040: return 15;
6041:
6042: case 0x0A: // no_op
6043: SetPC(GetPC() - 1);
6044: return 0;
6045:
6046: case 0x0B: // no_op
6047: SetPC(GetPC() - 1);
6048: return 0;
6049:
6050: case 0x0C: // no_op
6051: SetPC(GetPC() - 1);
6052: return 0;
6053:
6054: case 0x0D: // no_op
6055: SetPC(GetPC() - 1);
6056: return 0;
6057:
6058: case 0x0E: // no_op
6059: SetPC(GetPC() - 1);
6060: return 0;
6061:
6062: case 0x0F: // no_op
6063: SetPC(GetPC() - 1);
6064: return 0;
6065:
6066: case 0x10: // no_op
6067: SetPC(GetPC() - 1);
6068: return 0;
6069:
6070: case 0x11: // no_op
6071: SetPC(GetPC() - 1);
6072: return 0;
6073:
6074: case 0x12: // no_op
6075: SetPC(GetPC() - 1);
6076: return 0;
6077:
6078: case 0x13: // no_op
6079: SetPC(GetPC() - 1);
6080: return 0;
6081:
6082: case 0x14: // no_op
6083: SetPC(GetPC() - 1);
6084: return 0;
6085:
6086: case 0x15: // no_op
6087: SetPC(GetPC() - 1);
6088: return 0;
6089:
6090: case 0x16: // no_op
6091: SetPC(GetPC() - 1);
6092: return 0;
6093:
6094: case 0x17: // no_op
6095: SetPC(GetPC() - 1);
6096: return 0;
6097:
6098: case 0x18: // no_op
6099: SetPC(GetPC() - 1);
6100: return 0;
6101:
6102: case 0x19: // add_iy_de
6103: m_regIY = Add_2(m_regIY, m_regDE);
6104: return 15;
6105:
6106: case 0x1A: // no_op
6107: SetPC(GetPC() - 1);
6108: return 0;
6109:
6110: case 0x1B: // no_op
6111: SetPC(GetPC() - 1);
6112: return 0;
6113:
6114: case 0x1C: // no_op
6115: SetPC(GetPC() - 1);
6116: return 0;
6117:
6118: case 0x1D: // no_op
6119: SetPC(GetPC() - 1);
6120: return 0;
6121:
6122: case 0x1E: // no_op
6123: SetPC(GetPC() - 1);
6124: return 0;
6125:
6126: case 0x1F: // no_op
6127: SetPC(GetPC() - 1);
6128: return 0;
6129:
6130: case 0x20: // no_op
6131: SetPC(GetPC() - 1);
6132: return 0;
6133:
6134: case 0x21: // ld_iy_word
6135: m_regIY = ImmedWord();
6136: return 14;
6137:
6138: case 0x22: // ld_xword_iy
6139: MemWriteWord(ImmedWord(), m_regIY);
6140: return 20;
6141:
6142: case 0x23: // inc_iy
6143: m_regIY++;
6144: return 10;
6145:
6146: case 0x24: // inc_iyh
6147: m_regIYh = Inc(m_regIYh);
6148: return 9;
6149:
6150: case 0x25: // dec_iyh
6151: m_regIYh = Dec(m_regIYh);
6152: return 9;
6153:
6154: case 0x26: // ld_iyh_byte
6155: m_regIYh = ImmedByte();
6156: return 9;
6157:
6158: case 0x27: // no_op
6159: SetPC(GetPC() - 1);
6160: return 0;
6161:
6162: case 0x28: // no_op
6163: SetPC(GetPC() - 1);
6164: return 0;
6165:
6166: case 0x29: // add_iy_iy
6167: m_regIY = Add_2(m_regIY, m_regIY);
6168: return 15;
6169:
6170: case 0x2A: // ld_iy_xword
6171: m_regIY = MemReadWord(ImmedWord());
6172: return 20;
6173:
6174: case 0x2B: // dec_iy
6175: m_regIY--;
6176: return 10;
6177:
6178: case 0x2C: // inc_iyl
6179: m_regIYl = Inc(m_regIYl);
6180: return 9;
6181:
6182: case 0x2D: // dec_iyl
6183: m_regIYl = Dec(m_regIYl);
6184: return 9;
6185:
6186: case 0x2E: // ld_iyl_byte
6187: m_regIYl = ImmedByte();
6188: return 9;
6189:
6190: case 0x2F: // no_op
6191: SetPC(GetPC() - 1);
6192: return 0;
6193:
6194: case 0x30: // no_op
6195: SetPC(GetPC() - 1);
6196: return 0;
6197:
6198: case 0x31: // no_op
6199: SetPC(GetPC() - 1);
6200: return 0;
6201:
6202: case 0x32: // no_op
6203: SetPC(GetPC() - 1);
6204: return 0;
6205:
6206: case 0x33: // no_op
6207: SetPC(GetPC() - 1);
6208: return 0;
6209:
6210: case 0x34: // inc_xiy
6211: wAddr = IndirectIY();
6212: MemWriteByte(wAddr, Inc(MemReadByte(wAddr)));
6213: return 23;
6214:
6215: case 0x35: // dec_xiy
6216: wAddr = IndirectIY();
6217: MemWriteByte(wAddr, Dec(MemReadByte(wAddr)));
6218: return 23;
6219:
6220: case 0x36: // ld_xiy_byte
6221: wAddr = IndirectIY();
6222: MemWriteByte(wAddr, ImmedByte());
6223: return 19;
6224:
6225: case 0x37: // no_op
6226: SetPC(GetPC() - 1);
6227: return 0;
6228:
6229: case 0x38: // no_op
6230: SetPC(GetPC() - 1);
6231: return 0;
6232:
6233: case 0x39: // add_iy_sp
6234: m_regIY = Add_2(m_regIY, GetSP());
6235: return 15;
6236:
6237: case 0x3A: // no_op
6238: SetPC(GetPC() - 1);
6239: return 0;
6240:
6241: case 0x3B: // no_op
6242: SetPC(GetPC() - 1);
6243: return 0;
6244:
6245: case 0x3C: // no_op
6246: SetPC(GetPC() - 1);
6247: return 0;
6248:
6249: case 0x3D: // no_op
6250: SetPC(GetPC() - 1);
6251: return 0;
6252:
6253: case 0x3E: // no_op
6254: SetPC(GetPC() - 1);
6255: return 0;
6256:
6257: case 0x3F: // no_op
6258: SetPC(GetPC() - 1);
6259: return 0;
6260:
6261: case 0x40: // no_op
6262: SetPC(GetPC() - 1);
6263: return 0;
6264:
6265: case 0x41: // no_op
6266: SetPC(GetPC() - 1);
6267: return 0;
6268:
6269: case 0x42: // no_op
6270: SetPC(GetPC() - 1);
6271: return 0;
6272:
6273: case 0x43: // no_op
6274: SetPC(GetPC() - 1);
6275: return 0;
6276:
6277: case 0x44: // ld_b_iyh
6278: m_regB = m_regIYh;
6279: return 9;
6280:
6281: case 0x45: // ld_b_iyl
6282: m_regB = m_regIYl;
6283: return 9;
6284:
6285: case 0x46: // ld_b_xiy
6286: m_regB = MemReadByte(IndirectIY());
6287: return 19;
6288:
6289: case 0x47: // no_op
6290: SetPC(GetPC() - 1);
6291: return 0;
6292:
6293: case 0x48: // no_op
6294: SetPC(GetPC() - 1);
6295: return 0;
6296:
6297: case 0x49: // no_op
6298: SetPC(GetPC() - 1);
6299: return 0;
6300:
6301: case 0x4A: // no_op
6302: SetPC(GetPC() - 1);
6303: return 0;
6304:
6305: case 0x4B: // no_op
6306: SetPC(GetPC() - 1);
6307: return 0;
6308:
6309: case 0x4C: // ld_c_iyh
6310: m_regC = m_regIYh;
6311: return 9;
6312:
6313: case 0x4D: // ld_c_iyl
6314: m_regC = m_regIYl;
6315: return 9;
6316:
6317: case 0x4E: // ld_c_xiy
6318: m_regC = MemReadByte(IndirectIY());
6319: return 19;
6320:
6321: case 0x4F: // no_op
6322: SetPC(GetPC() - 1);
6323: return 0;
6324:
6325: case 0x50: // no_op
6326: SetPC(GetPC() - 1);
6327: return 0;
6328:
6329: case 0x51: // no_op
6330: SetPC(GetPC() - 1);
6331: return 0;
6332:
6333: case 0x52: // no_op
6334: SetPC(GetPC() - 1);
6335: return 0;
6336:
6337: case 0x53: // no_op
6338: SetPC(GetPC() - 1);
6339: return 0;
6340:
6341: case 0x54: // ld_d_iyh
6342: m_regD = m_regIYh;
6343: return 9;
6344:
6345: case 0x55: // ld_d_iyl
6346: m_regD = m_regIYl;
6347: return 9;
6348:
6349: case 0x56: // ld_d_xiy
6350: m_regD = MemReadByte(IndirectIY());
6351: return 19;
6352:
6353: case 0x57: // no_op
6354: SetPC(GetPC() - 1);
6355: return 0;
6356:
6357: case 0x58: // no_op
6358: SetPC(GetPC() - 1);
6359: return 0;
6360:
6361: case 0x59: // no_op
6362: SetPC(GetPC() - 1);
6363: return 0;
6364:
6365: case 0x5A: // no_op
6366: SetPC(GetPC() - 1);
6367: return 0;
6368:
6369: case 0x5B: // no_op
6370: SetPC(GetPC() - 1);
6371: return 0;
6372:
6373: case 0x5C: // ld_e_iyh
6374: m_regE = m_regIYh;
6375: return 9;
6376:
6377: case 0x5D: // ld_e_iyl
6378: m_regE = m_regIYl;
6379: return 9;
6380:
6381: case 0x5E: // ld_e_xiy
6382: m_regE = MemReadByte(IndirectIY());
6383: return 19;
6384:
6385: case 0x5F: // no_op
6386: SetPC(GetPC() - 1);
6387: return 0;
6388:
6389: case 0x60: // ld_iyh_b
6390: m_regIYh = m_regB;
6391: return 9;
6392:
6393: case 0x61: // ld_iyh_c
6394: m_regIYh = m_regC;
6395: return 9;
6396:
6397: case 0x62: // ld_iyh_d
6398: m_regIYh = m_regD;
6399: return 9;
6400:
6401: case 0x63: // ld_iyh_e
6402: m_regIYh = m_regE;
6403: return 9;
6404:
6405: case 0x64: // ld_iyh_h
6406: m_regIYh = m_regH;
6407: return 9;
6408:
6409: case 0x65: // ld_iyh_l
6410: m_regIYh = m_regL;
6411: return 9;
6412:
6413: case 0x66: // ld_h_xiy
6414: m_regH = MemReadByte(IndirectIY());
6415: return 9;
6416:
6417: case 0x67: // ld_iyh_a
6418: m_regIYh = m_regA;
6419: return 9;
6420:
6421: case 0x68: // ld_iyl_b
6422: m_regIYl = m_regB;
6423: return 9;
6424:
6425: case 0x69: // ld_iyl_c
6426: m_regIYl = m_regC;
6427: return 9;
6428:
6429: case 0x6A: // ld_iyl_d
6430: m_regIYl = m_regD;
6431: return 9;
6432:
6433: case 0x6B: // ld_iyl_e
6434: m_regIYl = m_regE;
6435: return 9;
6436:
6437: case 0x6C: // ld_iyl_h
6438: m_regIYl = m_regH;
6439: return 9;
6440:
6441: case 0x6D: // ld_iyl_l
6442: m_regIYl = m_regL;
6443: return 9;
6444:
6445: case 0x6E: // ld_l_xiy
6446: m_regL = MemReadByte(IndirectIY());
6447: return 9;
6448:
6449: case 0x6F: // ld_iyl_a
6450: m_regIYl = m_regA;
6451: return 9;
6452:
6453: case 0x70: // ld_xiy_b
6454: MemWriteByte(IndirectIY(), m_regB);
6455: return 19;
6456:
6457: case 0x71: // ld_xiy_c
6458: MemWriteByte(IndirectIY(), m_regC);
6459: return 19;
6460:
6461: case 0x72: // ld_xiy_d
6462: MemWriteByte(IndirectIY(), m_regD);
6463: return 19;
6464:
6465: case 0x73: // ld_xiy_e
6466: MemWriteByte(IndirectIY(), m_regE);
6467: return 19;
6468:
6469: case 0x74: // ld_xiy_h
6470: MemWriteByte(IndirectIY(), m_regH);
6471: return 19;
6472:
6473: case 0x75: // ld_xiy_l
6474: MemWriteByte(IndirectIY(), m_regL);
6475: return 19;
6476:
6477: case 0x76: // no_op
6478: SetPC(GetPC() - 1);
6479: return 19;
6480:
6481: case 0x77: // ld_xiy_a
6482: MemWriteByte(IndirectIY(), m_regA);
6483: return 19;
6484:
6485: case 0x78: // no_op
6486: SetPC(GetPC() - 1);
6487: return 0;
6488:
6489: case 0x79: // no_op
6490: SetPC(GetPC() - 1);
6491: return 0;
6492:
6493: case 0x7A: // no_op
6494: SetPC(GetPC() - 1);
6495: return 0;
6496:
6497: case 0x7B: // no_op
6498: SetPC(GetPC() - 1);
6499: return 0;
6500:
6501: case 0x7C: // ld_a_iyh
6502: m_regA = m_regIYh;
6503: return 9;
6504:
6505: case 0x7D: // ld_a_iyl
6506: m_regA = m_regIYl;
6507: return 9;
6508:
6509: case 0x7E: // ld_a_xiy
6510: m_regA = MemReadByte(IndirectIY());
6511: return 19;
6512:
6513: case 0x7F: // no_op
6514: SetPC(GetPC() - 1);
6515: return 0;
6516:
6517: case 0x80: // no_op
6518: SetPC(GetPC() - 1);
6519: return 0;
6520:
6521: case 0x81: // no_op
6522: SetPC(GetPC() - 1);
6523: return 0;
6524:
6525: case 0x82: // no_op
6526: SetPC(GetPC() - 1);
6527: return 0;
6528:
6529: case 0x83: // no_op
6530: SetPC(GetPC() - 1);
6531: return 0;
6532:
6533: case 0x84: // add_a_iyh
6534: Add_1(m_regIYh);
6535: return 9;
6536:
6537: case 0x85: // add_a_iyl
6538: Add_1(m_regIYl);
6539: return 9;
6540:
6541: case 0x86: // add_a_xiy
6542: Add_1(MemReadByte(IndirectIY()));
6543: return 19;
6544:
6545: case 0x87: // no_op
6546: SetPC(GetPC() - 1);
6547: return 0;
6548:
6549: case 0x88: // no_op
6550: SetPC(GetPC() - 1);
6551: return 0;
6552:
6553: case 0x89: // no_op
6554: SetPC(GetPC() - 1);
6555: return 0;
6556:
6557: case 0x8A: // no_op
6558: SetPC(GetPC() - 1);
6559: return 0;
6560:
6561: case 0x8B: // no_op
6562: SetPC(GetPC() - 1);
6563: return 0;
6564:
6565: case 0x8C: // adc_a_iyh
6566: Adc_1(m_regIYh);
6567: return 9;
6568:
6569: case 0x8D: // adc_a_iyl
6570: Adc_1(m_regIYl);
6571: return 9;
6572:
6573: case 0x8E: // adc_a_xiy
6574: Adc_1(MemReadByte(IndirectIY()));
6575: return 19;
6576:
6577: case 0x8F: // no_op
6578: SetPC(GetPC() - 1);
6579: return 0;
6580:
6581: case 0x90: // no_op
6582: SetPC(GetPC() - 1);
6583: return 0;
6584:
6585: case 0x91: // no_op
6586: SetPC(GetPC() - 1);
6587: return 0;
6588:
6589: case 0x92: // no_op
6590: SetPC(GetPC() - 1);
6591: return 0;
6592:
6593: case 0x93: // no_op
6594: SetPC(GetPC() - 1);
6595: return 0;
6596:
6597: case 0x94: // sub_iyh
6598: Sub_1(m_regIYh);
6599: return 9;
6600:
6601: case 0x95: // sub_iyl
6602: Sub_1(m_regIYl);
6603: return 9;
6604:
6605: case 0x96: // sub_xiy
6606: Sub_1(MemReadByte(IndirectIY()));
6607: return 19;
6608:
6609: case 0x97: // no_op
6610: SetPC(GetPC() - 1);
6611: return 0;
6612:
6613: case 0x98: // no_op
6614: SetPC(GetPC() - 1);
6615: return 0;
6616:
6617: case 0x99: // no_op
6618: SetPC(GetPC() - 1);
6619: return 0;
6620:
6621: case 0x9A: // no_op
6622: SetPC(GetPC() - 1);
6623: return 0;
6624:
6625: case 0x9B: // no_op
6626: SetPC(GetPC() - 1);
6627: return 0;
6628:
6629: case 0x9C: // sbc_a_iyh
6630: Sbc_1(m_regIYh);
6631: return 9;
6632:
6633: case 0x9D: // sbc_a_iyl
6634: Sbc_1(m_regIYl);
6635: return 9;
6636:
6637: case 0x9E: // sbc_a_xiy
6638: Sbc_1(MemReadByte(IndirectIY()));
6639: return 19;
6640:
6641: case 0x9F: // no_op
6642: SetPC(GetPC() - 1);
6643: return 0;
6644:
6645: case 0xA0: // no_op
6646: SetPC(GetPC() - 1);
6647: return 0;
6648:
6649: case 0xA1: // no_op
6650: SetPC(GetPC() - 1);
6651: return 0;
6652:
6653: case 0xA2: // no_op
6654: SetPC(GetPC() - 1);
6655: return 0;
6656:
6657: case 0xA3: // no_op
6658: SetPC(GetPC() - 1);
6659: return 0;
6660:
6661: case 0xA4: // and_iyh
6662: And(m_regIYh);
6663: return 9;
6664:
6665: case 0xA5: // and_iyl
6666: And(m_regIYl);
6667: return 9;
6668:
6669: case 0xA6: // and_xiy
6670: And(MemReadByte(IndirectIY()));
6671: return 19;
6672:
6673: case 0xA7: // no_op
6674: SetPC(GetPC() - 1);
6675: return 0;
6676:
6677: case 0xA8: // no_op
6678: SetPC(GetPC() - 1);
6679: return 0;
6680:
6681: case 0xA9: // no_op
6682: SetPC(GetPC() - 1);
6683: return 0;
6684:
6685: case 0xAA: // no_op
6686: SetPC(GetPC() - 1);
6687: return 0;
6688:
6689: case 0xAB: // no_op
6690: SetPC(GetPC() - 1);
6691: return 0;
6692:
6693: case 0xAC: // xor_iyh
6694: Xor(m_regIYh);
6695: return 9;
6696:
6697: case 0xAD: // xor_iyl
6698: Xor(m_regIYl);
6699: return 9;
6700:
6701: case 0xAE: // xor_xiy
6702: Xor(MemReadByte(IndirectIY()));
6703: return 19;
6704:
6705: case 0xAF: // no_op
6706: SetPC(GetPC() - 1);
6707: return 0;
6708:
6709: case 0xB0: // no_op
6710: SetPC(GetPC() - 1);
6711: return 0;
6712:
6713: case 0xB1: // no_op
6714: SetPC(GetPC() - 1);
6715: return 0;
6716:
6717: case 0xB2: // no_op
6718: SetPC(GetPC() - 1);
6719: return 0;
6720:
6721: case 0xB3: // no_op
6722: SetPC(GetPC() - 1);
6723: return 0;
6724:
6725: case 0xB4: // or_iyh
6726: Or(m_regIYh);
6727: return 9;
6728:
6729: case 0xB5: // or_iyl
6730: Or(m_regIYl);
6731: return 9;
6732:
6733: case 0xB6: // or_xiy
6734: Or(MemReadByte(IndirectIY()));
6735: return 19;
6736:
6737: case 0xB7: // no_op
6738: SetPC(GetPC() - 1);
6739: return 0;
6740:
6741: case 0xB8: // no_op
6742: SetPC(GetPC() - 1);
6743: return 0;
6744:
6745: case 0xB9: // no_op
6746: SetPC(GetPC() - 1);
6747: return 0;
6748:
6749: case 0xBA: // no_op
6750: SetPC(GetPC() - 1);
6751: return 0;
6752:
6753: case 0xBB: // no_op
6754: SetPC(GetPC() - 1);
6755: return 0;
6756:
6757: case 0xBC: // cp_iyh
6758: Cp(m_regIYh);
6759: return 9;
6760:
6761: case 0xBD: // cp_iyl
6762: Cp(m_regIYl);
6763: return 9;
6764:
6765: case 0xBE: // cp_xiy
6766: Cp(MemReadByte(IndirectIY()));
6767: return 19;
6768:
6769: case 0xBF: // no_op
6770: SetPC(GetPC() - 1);
6771: return 0;
6772:
6773: case 0xC0: // no_op
6774: SetPC(GetPC() - 1);
6775: return 0;
6776:
6777: case 0xC1: // no_op
6778: SetPC(GetPC() - 1);
6779: return 0;
6780:
6781: case 0xC2: // no_op
6782: SetPC(GetPC() - 1);
6783: return 0;
6784:
6785: case 0xC3: // no_op
6786: SetPC(GetPC() - 1);
6787: return 0;
6788:
6789: case 0xC4: // no_op
6790: SetPC(GetPC() - 1);
6791: return 0;
6792:
6793: case 0xC5: // no_op
6794: SetPC(GetPC() - 1);
6795: return 0;
6796:
6797: case 0xC6: // no_op
6798: SetPC(GetPC() - 1);
6799: return 0;
6800:
6801: case 0xC7: // no_op
6802: SetPC(GetPC() - 1);
6803: return 0;
6804:
6805: case 0xC8: // no_op
6806: SetPC(GetPC() - 1);
6807: return 0;
6808:
6809: case 0xC9: // no_op
6810: SetPC(GetPC() - 1);
6811: return 0;
6812:
6813: case 0xCA: // no_op
6814: SetPC(GetPC() - 1);
6815: return 0;
6816:
6817: case 0xCB: // fd_cb
6818: return HandleFDCB();
6819:
6820: case 0xCC: // no_op
6821: SetPC(GetPC() - 1);
6822: return 0;
6823:
6824: case 0xCD: // no_op
6825: SetPC(GetPC() - 1);
6826: return 0;
6827:
6828: case 0xCE: // no_op
6829: SetPC(GetPC() - 1);
6830: return 0;
6831:
6832: case 0xCF: // no_op
6833: SetPC(GetPC() - 1);
6834: return 0;
6835:
6836: case 0xD0: // no_op
6837: SetPC(GetPC() - 1);
6838: return 0;
6839:
6840: case 0xD1: // no_op
6841: SetPC(GetPC() - 1);
6842: return 0;
6843:
6844: case 0xD2: // no_op
6845: SetPC(GetPC() - 1);
6846: return 0;
6847:
6848: case 0xD3: // no_op
6849: SetPC(GetPC() - 1);
6850: return 0;
6851:
6852: case 0xD4: // no_op
6853: SetPC(GetPC() - 1);
6854: return 0;
6855:
6856: case 0xD5: // no_op
6857: SetPC(GetPC() - 1);
6858: return 0;
6859:
6860: case 0xD6: // no_op
6861: SetPC(GetPC() - 1);
6862: return 0;
6863:
6864: case 0xD7: // no_op
6865: SetPC(GetPC() - 1);
6866: return 0;
6867:
6868: case 0xD8: // no_op
6869: SetPC(GetPC() - 1);
6870: return 0;
6871:
6872: case 0xD9: // no_op
6873: SetPC(GetPC() - 1);
6874: return 0;
6875:
6876: case 0xDA: // no_op
6877: SetPC(GetPC() - 1);
6878: return 0;
6879:
6880: case 0xDB: // no_op
6881: SetPC(GetPC() - 1);
6882: return 0;
6883:
6884: case 0xDC: // no_op
6885: SetPC(GetPC() - 1);
6886: return 0;
6887:
6888: case 0xDD: // no_op
6889: SetPC(GetPC() - 1);
6890: return 0;
6891:
6892: case 0xDE: // no_op
6893: SetPC(GetPC() - 1);
6894: return 0;
6895:
6896: case 0xDF: // no_op
6897: SetPC(GetPC() - 1);
6898: return 0;
6899:
6900: case 0xE0: // no_op
6901: SetPC(GetPC() - 1);
6902: return 0;
6903:
6904: case 0xE1: // pop_iy
6905: m_regIY = Pop();
6906: return 14;
6907:
6908: case 0xE2: // no_op
6909: SetPC(GetPC() - 1);
6910: return 0;
6911:
6912: case 0xE3: // ex_xsp_iy
6913: wTemp = MemReadWord(GetSP());
6914: MemWriteWord(GetSP(), m_regIY);
6915: m_regIY = wTemp;
6916: return 23;
6917:
6918: case 0xE4: // no_op
6919: SetPC(GetPC() - 1);
6920: return 0;
6921:
6922: case 0xE5: // push_iy
6923: Push(m_regIY);
6924: return 15;
6925:
6926: case 0xE6: // no_op
6927: SetPC(GetPC() - 1);
6928: return 0;
6929:
6930: case 0xE7: // no_op
6931: SetPC(GetPC() - 1);
6932: return 0;
6933:
6934: case 0xE8: // no_op
6935: SetPC(GetPC() - 1);
6936: return 0;
6937:
6938: case 0xE9: // jp_iy
6939: SetPC(m_regIY);
6940: return 8;
6941:
6942: case 0xEA: // no_op
6943: SetPC(GetPC() - 1);
6944: return 0;
6945:
6946: case 0xEB: // no_op
6947: SetPC(GetPC() - 1);
6948: return 0;
6949:
6950: case 0xEC: // no_op
6951: SetPC(GetPC() - 1);
6952: return 0;
6953:
6954: case 0xED: // no_op
6955: SetPC(GetPC() - 1);
6956: return 0;
6957:
6958: case 0xEE: // no_op
6959: SetPC(GetPC() - 1);
6960: return 0;
6961:
6962: case 0xEF: // no_op
6963: SetPC(GetPC() - 1);
6964: return 0;
6965:
6966: case 0xF0: // no_op
6967: SetPC(GetPC() - 1);
6968: return 0;
6969:
6970: case 0xF1: // no_op
6971: SetPC(GetPC() - 1);
6972: return 0;
6973:
6974: case 0xF2: // no_op
6975: SetPC(GetPC() - 1);
6976: return 0;
6977:
6978: case 0xF3: // no_op
6979: SetPC(GetPC() - 1);
6980: return 0;
6981:
6982: case 0xF4: // no_op
6983: SetPC(GetPC() - 1);
6984: return 0;
6985:
6986: case 0xF5: // no_op
6987: SetPC(GetPC() - 1);
6988: return 0;
6989:
6990: case 0xF6: // no_op
6991: SetPC(GetPC() - 1);
6992: return 0;
6993:
6994: case 0xF7: // no_op
6995: SetPC(GetPC() - 1);
6996: return 0;
6997:
6998: case 0xF8: // no_op
6999: SetPC(GetPC() - 1);
7000: return 0;
7001:
7002: case 0xF9: // ld_sp_iy
7003: SetSP(m_regIY);
7004: return 10;
7005:
7006: case 0xFA: // no_op
7007: SetPC(GetPC() - 1);
7008: return 0;
7009:
7010: case 0xFB: // no_op
7011: SetPC(GetPC() - 1);
7012: return 0;
7013:
7014: case 0xFC: // no_op
7015: SetPC(GetPC() - 1);
7016: return 0;
7017:
7018: case 0xFD: // no_op
7019: SetPC(GetPC() - 1);
7020: return 0;
7021:
7022: case 0xFE: // no_op
7023: SetPC(GetPC() - 1);
7024: return 0;
7025:
7026: case 0xFF: // no_op
7027: SetPC(GetPC() - 1);
7028: return 0;
7029:
7030: default:
7031: _ASSERT(FALSE);
7032: return 0;
7033: }
7034: }
7035:
7036: /* ***************************************************************************
7037: * FDCD prefixed opcodes
7038: * ***************************************************************************
7039: */
7040:
7041: int HandleFDCB() {
7042: const WORD wAddr = m_regIY + (signed char)ImmedByte();
7043: const BYTE bOpcode = ImmedByte();
7044:
7045: switch (bOpcode)
7046: {
7047: case 0x00: // no_op_xx
7048: return 0;
7049:
7050: case 0x01: // no_op_xx
7051: return 0;
7052:
7053: case 0x02: // no_op_xx
7054: return 0;
7055:
7056: case 0x03: // no_op_xx
7057: return 0;
7058:
7059: case 0x04: // no_op_xx
7060: return 0;
7061:
7062: case 0x05: // no_op_xx
7063: return 0;
7064:
7065: case 0x06: // rlc_xiy
7066: MemWriteByte(wAddr, Rlc(MemReadByte(wAddr)));
7067: return 23;
7068:
7069: case 0x07: // no_op_xx
7070: return 0;
7071:
7072: case 0x08: // no_op_xx
7073: return 0;
7074:
7075: case 0x09: // no_op_xx
7076: return 0;
7077:
7078: case 0x0A: // no_op_xx
7079: return 0;
7080:
7081: case 0x0B: // no_op_xx
7082: return 0;
7083:
7084: case 0x0C: // no_op_xx
7085: return 0;
7086:
7087: case 0x0D: // no_op_xx
7088: return 0;
7089:
7090: case 0x0E: // rrc_xiy
7091: MemWriteByte(wAddr, Rrc(MemReadByte(wAddr)));
7092: return 23;
7093:
7094: case 0x0F: // no_op_xx
7095: return 0;
7096:
7097: case 0x10: // no_op_xx
7098: return 0;
7099:
7100: case 0x11: // no_op_xx
7101: return 0;
7102:
7103: case 0x12: // no_op_xx
7104: return 0;
7105:
7106: case 0x13: // no_op_xx
7107: return 0;
7108:
7109: case 0x14: // no_op_xx
7110: return 0;
7111:
7112: case 0x15: // no_op_xx
7113: return 0;
7114:
7115: case 0x16: // rl_xiy
7116: MemWriteByte(wAddr, Rl(MemReadByte(wAddr)));
7117: return 23;
7118:
7119: case 0x17: // no_op_xx
7120: return 0;
7121:
7122: case 0x18: // no_op_xx
7123: return 0;
7124:
7125: case 0x19: // no_op_xx
7126: return 0;
7127:
7128: case 0x1A: // no_op_xx
7129: return 0;
7130:
7131: case 0x1B: // no_op_xx
7132: return 0;
7133:
7134: case 0x1C: // no_op_xx
7135: return 0;
7136:
7137: case 0x1D: // no_op_xx
7138: return 0;
7139:
7140: case 0x1E: // rr_xiy
7141: MemWriteByte(wAddr, Rr(MemReadByte(wAddr)));
7142: return 23;
7143:
7144: case 0x1F: // no_op_xx
7145: return 0;
7146:
7147: case 0x20: // no_op_xx
7148: return 0;
7149:
7150: case 0x21: // no_op_xx
7151: return 0;
7152:
7153: case 0x22: // no_op_xx
7154: return 0;
7155:
7156: case 0x23: // no_op_xx
7157: return 0;
7158:
7159: case 0x24: // no_op_xx
7160: return 0;
7161:
7162: case 0x25: // no_op_xx
7163: return 0;
7164:
7165: case 0x26: // sla_xiy
7166: MemWriteByte(wAddr, Sla(MemReadByte(wAddr)));
7167: return 23;
7168:
7169: case 0x27: // no_op_xx
7170: return 0;
7171:
7172: case 0x28: // no_op_xx
7173: return 0;
7174:
7175: case 0x29: // no_op_xx
7176: return 0;
7177:
7178: case 0x2A: // no_op_xx
7179: return 0;
7180:
7181: case 0x2B: // no_op_xx
7182: return 0;
7183:
7184: case 0x2C: // no_op_xx
7185: return 0;
7186:
7187: case 0x2D: // no_op_xx
7188: return 0;
7189:
7190: case 0x2E: // sra_xiy
7191: MemWriteByte(wAddr, Sra(MemReadByte(wAddr)));
7192: return 23;
7193:
7194: case 0x2F: // no_op_xx
7195: return 0;
7196:
7197: case 0x30: // no_op_xx
7198: return 0;
7199:
7200: case 0x31: // no_op_xx
7201: return 0;
7202:
7203: case 0x32: // no_op_xx
7204: return 0;
7205:
7206: case 0x33: // no_op_xx
7207: return 0;
7208:
7209: case 0x34: // no_op_xx
7210: return 0;
7211:
7212: case 0x35: // no_op_xx
7213: return 0;
7214:
7215: case 0x36: // sll_xiy
7216: MemWriteByte(wAddr, Sll(MemReadByte(wAddr)));
7217: return 23;
7218:
7219: case 0x37: // no_op_xx
7220: return 0;
7221:
7222: case 0x38: // no_op_xx
7223: return 0;
7224:
7225: case 0x39: // no_op_xx
7226: return 0;
7227:
7228: case 0x3A: // no_op_xx
7229: return 0;
7230:
7231: case 0x3B: // no_op_xx
7232: return 0;
7233:
7234: case 0x3C: // no_op_xx
7235: return 0;
7236:
7237: case 0x3D: // no_op_xx
7238: return 0;
7239:
7240: case 0x3E: // srl_xiy
7241: MemWriteByte(wAddr, Srl(MemReadByte(wAddr)));
7242: return 23;
7243:
7244: case 0x3F: // no_op_xx
7245: return 0;
7246:
7247: case 0x40: // bit_0_xiy
7248: case 0x41: // bit_0_xiy
7249: case 0x42: // bit_0_xiy
7250: case 0x43: // bit_0_xiy
7251: case 0x44: // bit_0_xiy
7252: case 0x45: // bit_0_xiy
7253: case 0x46: // bit_0_xiy
7254: case 0x47: // bit_0_xiy
7255: Bit(MemReadByte(wAddr), 0);
7256: return 20;
7257:
7258: case 0x48: // bit_1_xiy
7259: case 0x49: // bit_1_xiy
7260: case 0x4A: // bit_1_xiy
7261: case 0x4B: // bit_1_xiy
7262: case 0x4C: // bit_1_xiy
7263: case 0x4D: // bit_1_xiy
7264: case 0x4E: // bit_1_xiy
7265: case 0x4F: // bit_1_xiy
7266: Bit(MemReadByte(wAddr), 1);
7267: return 20;
7268:
7269: case 0x50: // bit_2_xiy
7270: case 0x51: // bit_2_xiy
7271: case 0x52: // bit_2_xiy
7272: case 0x53: // bit_2_xiy
7273: case 0x54: // bit_2_xiy
7274: case 0x55: // bit_2_xiy
7275: case 0x56: // bit_2_xiy
7276: case 0x57: // bit_2_xiy
7277: Bit(MemReadByte(wAddr), 2);
7278: return 20;
7279:
7280: case 0x58: // bit_3_xiy
7281: case 0x59: // bit_3_xiy
7282: case 0x5A: // bit_3_xiy
7283: case 0x5B: // bit_3_xiy
7284: case 0x5C: // bit_3_xiy
7285: case 0x5D: // bit_3_xiy
7286: case 0x5E: // bit_3_xiy
7287: case 0x5F: // bit_3_xiy
7288: Bit(MemReadByte(wAddr), 3);
7289: return 20;
7290:
7291: case 0x60: // bit_4_xiy
7292: case 0x61: // bit_4_xiy
7293: case 0x62: // bit_4_xiy
7294: case 0x63: // bit_4_xiy
7295: case 0x64: // bit_4_xiy
7296: case 0x65: // bit_4_xiy
7297: case 0x66: // bit_4_xiy
7298: case 0x67: // bit_4_xiy
7299: Bit(MemReadByte(wAddr), 4);
7300: return 20;
7301:
7302: case 0x68: // bit_5_xiy
7303: case 0x69: // bit_5_xiy
7304: case 0x6A: // bit_5_xiy
7305: case 0x6B: // bit_5_xiy
7306: case 0x6C: // bit_5_xiy
7307: case 0x6D: // bit_5_xiy
7308: case 0x6E: // bit_5_xiy
7309: case 0x6F: // bit_5_xiy
7310: Bit(MemReadByte(wAddr), 5);
7311: return 20;
7312:
7313: case 0x70: // bit_6_xiy
7314: case 0x71: // bit_6_xiy
7315: case 0x72: // bit_6_xiy
7316: case 0x73: // bit_6_xiy
7317: case 0x74: // bit_6_xiy
7318: case 0x75: // bit_6_xiy
7319: case 0x76: // bit_6_xiy
7320: case 0x77: // bit_6_xiy
7321: Bit(MemReadByte(wAddr), 6);
7322: return 20;
7323:
7324: case 0x78: // bit_7_xiy
7325: case 0x79: // bit_7_xiy
7326: case 0x7A: // bit_7_xiy
7327: case 0x7B: // bit_7_xiy
7328: case 0x7C: // bit_7_xiy
7329: case 0x7D: // bit_7_xiy
7330: case 0x7E: // bit_7_xiy
7331: case 0x7F: // bit_7_xiy
7332: Bit(MemReadByte(wAddr), 7);
7333: return 20;
7334:
7335: case 0x80: // no_op_xx
7336: return 0;
7337:
7338: case 0x81: // no_op_xx
7339: return 0;
7340:
7341: case 0x82: // no_op_xx
7342: return 0;
7343:
7344: case 0x83: // no_op_xx
7345: return 0;
7346:
7347: case 0x84: // no_op_xx
7348: return 0;
7349:
7350: case 0x85: // no_op_xx
7351: return 0;
7352:
7353: case 0x86: // res_0_xiy
7354: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 0));
7355: return 23;
7356:
7357: case 0x87: // no_op_xx
7358: return 0;
7359:
7360: case 0x88: // no_op_xx
7361: return 0;
7362:
7363: case 0x89: // no_op_xx
7364: return 0;
7365:
7366: case 0x8A: // no_op_xx
7367: return 0;
7368:
7369: case 0x8B: // no_op_xx
7370: return 0;
7371:
7372: case 0x8C: // no_op_xx
7373: return 0;
7374:
7375: case 0x8D: // no_op_xx
7376: return 0;
7377:
7378: case 0x8E: // res_1_xiy
7379: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 1));
7380: return 23;
7381:
7382: case 0x8F: // no_op_xx
7383: return 0;
7384:
7385: case 0x90: // no_op_xx
7386: return 0;
7387:
7388: case 0x91: // no_op_xx
7389: return 0;
7390:
7391: case 0x92: // no_op_xx
7392: return 0;
7393:
7394: case 0x93: // no_op_xx
7395: return 0;
7396:
7397: case 0x94: // no_op_xx
7398: return 0;
7399:
7400: case 0x95: // no_op_xx
7401: return 0;
7402:
7403: case 0x96: // res_2_xiy
7404: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 2));
7405: return 23;
7406:
7407: case 0x97: // no_op_xx
7408: return 0;
7409:
7410: case 0x98: // no_op_xx
7411: return 0;
7412:
7413: case 0x99: // no_op_xx
7414: return 0;
7415:
7416: case 0x9A: // no_op_xx
7417: return 0;
7418:
7419: case 0x9B: // no_op_xx
7420: return 0;
7421:
7422: case 0x9C: // no_op_xx
7423: return 0;
7424:
7425: case 0x9D: // no_op_xx
7426: return 0;
7427:
7428: case 0x9E: // res_3_xiy
7429: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 3));
7430: return 23;
7431:
7432: case 0x9F: // no_op_xx
7433: return 0;
7434:
7435: case 0xA0: // no_op_xx
7436: return 0;
7437:
7438: case 0xA1: // no_op_xx
7439: return 0;
7440:
7441: case 0xA2: // no_op_xx
7442: return 0;
7443:
7444: case 0xA3: // no_op_xx
7445: return 0;
7446:
7447: case 0xA4: // no_op_xx
7448: return 0;
7449:
7450: case 0xA5: // no_op_xx
7451: return 0;
7452:
7453: case 0xA6: // res_4_xiy
7454: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 4));
7455: return 23;
7456:
7457: case 0xA7: // no_op_xx
7458: return 0;
7459:
7460: case 0xA8: // no_op_xx
7461: return 0;
7462:
7463: case 0xA9: // no_op_xx
7464: return 0;
7465:
7466: case 0xAA: // no_op_xx
7467: return 0;
7468:
7469: case 0xAB: // no_op_xx
7470: return 0;
7471:
7472: case 0xAC: // no_op_xx
7473: return 0;
7474:
7475: case 0xAD: // no_op_xx
7476: return 0;
7477:
7478: case 0xAE: // res_5_xiy
7479: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 5));
7480: return 23;
7481:
7482: case 0xAF: // no_op_xx
7483: return 0;
7484:
7485: case 0xB0: // no_op_xx
7486: return 0;
7487:
7488: case 0xB1: // no_op_xx
7489: return 0;
7490:
7491: case 0xB2: // no_op_xx
7492: return 0;
7493:
7494: case 0xB3: // no_op_xx
7495: return 0;
7496:
7497: case 0xB4: // no_op_xx
7498: return 0;
7499:
7500: case 0xB5: // no_op_xx
7501: return 0;
7502:
7503: case 0xB6: // res_6_xiy
7504: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 6));
7505: return 23;
7506:
7507: case 0xB7: // no_op_xx
7508: return 0;
7509:
7510: case 0xB8: // no_op_xx
7511: return 0;
7512:
7513: case 0xB9: // no_op_xx
7514: return 0;
7515:
7516: case 0xBA: // no_op_xx
7517: return 0;
7518:
7519: case 0xBB: // no_op_xx
7520: return 0;
7521:
7522: case 0xBC: // no_op_xx
7523: return 0;
7524:
7525: case 0xBD: // no_op_xx
7526: return 0;
7527:
7528: case 0xBE: // res_7_xiy
7529: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 7));
7530: return 23;
7531:
7532: case 0xBF: // no_op_xx
7533: return 0;
7534:
7535: case 0xC0: // no_op_xx
7536: return 0;
7537:
7538: case 0xC1: // no_op_xx
7539: return 0;
7540:
7541: case 0xC2: // no_op_xx
7542: return 0;
7543:
7544: case 0xC3: // no_op_xx
7545: return 0;
7546:
7547: case 0xC4: // no_op_xx
7548: return 0;
7549:
7550: case 0xC5: // no_op_xx
7551: return 0;
7552:
7553: case 0xC6: // set_0_xiy
7554: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 0));
7555: return 23;
7556:
7557: case 0xC7: // no_op_xx
7558: return 0;
7559:
7560: case 0xC8: // no_op_xx
7561: return 0;
7562:
7563: case 0xC9: // no_op_xx
7564: return 0;
7565:
7566: case 0xCA: // no_op_xx
7567: return 0;
7568:
7569: case 0xCB: // no_op_xx
7570: return 0;
7571:
7572: case 0xCC: // no_op_xx
7573: return 0;
7574:
7575: case 0xCD: // no_op_xx
7576: return 0;
7577:
7578: case 0xCE: // set_1_xiy
7579: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 1));
7580: return 23;
7581:
7582: case 0xCF: // no_op_xx
7583: return 0;
7584:
7585: case 0xD0: // no_op_xx
7586: return 0;
7587:
7588: case 0xD1: // no_op_xx
7589: return 0;
7590:
7591: case 0xD2: // no_op_xx
7592: return 0;
7593:
7594: case 0xD3: // no_op_xx
7595: return 0;
7596:
7597: case 0xD4: // no_op_xx
7598: return 0;
7599:
7600: case 0xD5: // no_op_xx
7601: return 0;
7602:
7603: case 0xD6: // set_2_xiy
7604: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 2));
7605: return 23;
7606:
7607: case 0xD7: // no_op_xx
7608: return 0;
7609:
7610: case 0xD8: // no_op_xx
7611: return 0;
7612:
7613: case 0xD9: // no_op_xx
7614: return 0;
7615:
7616: case 0xDA: // no_op_xx
7617: return 0;
7618:
7619: case 0xDB: // no_op_xx
7620: return 0;
7621:
7622: case 0xDC: // no_op_xx
7623: return 0;
7624:
7625: case 0xDD: // no_op_xx
7626: return 0;
7627:
7628: case 0xDE: // set_3_xiy
7629: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 3));
7630: return 23;
7631:
7632: case 0xDF: // no_op_xx
7633: return 0;
7634:
7635: case 0xE0: // no_op_xx
7636: return 0;
7637:
7638: case 0xE1: // no_op_xx
7639: return 0;
7640:
7641: case 0xE2: // no_op_xx
7642: return 0;
7643:
7644: case 0xE3: // no_op_xx
7645: return 0;
7646:
7647: case 0xE4: // no_op_xx
7648: return 0;
7649:
7650: case 0xE5: // no_op_xx
7651: return 0;
7652:
7653: case 0xE6: // set_4_xiy
7654: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 4));
7655: return 23;
7656:
7657: case 0xE7: // no_op_xx
7658: return 0;
7659:
7660: case 0xE8: // no_op_xx
7661: return 0;
7662:
7663: case 0xE9: // no_op_xx
7664: return 0;
7665:
7666: case 0xEA: // no_op_xx
7667: return 0;
7668:
7669: case 0xEB: // no_op_xx
7670: return 0;
7671:
7672: case 0xEC: // no_op_xx
7673: return 0;
7674:
7675: case 0xED: // no_op_xx
7676: return 0;
7677:
7678: case 0xEE: // set_5_xiy
7679: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 5));
7680: return 23;
7681:
7682: case 0xEF: // no_op_xx
7683: return 0;
7684:
7685: case 0xF0: // no_op_xx
7686: return 0;
7687:
7688: case 0xF1: // no_op_xx
7689: return 0;
7690:
7691: case 0xF2: // no_op_xx
7692: return 0;
7693:
7694: case 0xF3: // no_op_xx
7695: return 0;
7696:
7697: case 0xF4: // no_op_xx
7698: return 0;
7699:
7700: case 0xF5: // no_op_xx
7701: return 0;
7702:
7703: case 0xF6: // set_6_xiy
7704: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 6));
7705: return 23;
7706:
7707: case 0xF7: // no_op_xx
7708: return 0;
7709:
7710: case 0xF8: // no_op_xx
7711: return 0;
7712:
7713: case 0xF9: // no_op_xx
7714: return 0;
7715:
7716: case 0xFA: // no_op_xx
7717: return 0;
7718:
7719: case 0xFB: // no_op_xx
7720: return 0;
7721:
7722: case 0xFC: // no_op_xx
7723: return 0;
7724:
7725: case 0xFD: // no_op_xx
7726: return 0;
7727:
7728: case 0xFE: // set_7_xiy
7729: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 7));
7730: return 23;
7731:
7732: case 0xFF: // no_op_x
7733: return 0;
7734:
7735: default:
7736: _ASSERT(FALSE);
7737: return 0;
7738: }
7739: }
7740:
7741: /* ***************************************************************************
7742: * DDCB prefixed opcodes
7743: * ***************************************************************************
7744: */
7745:
7746: int HandleDDCB() {
7747: const WORD wAddr = m_regIX + (signed char)ImmedByte();
7748: const BYTE bOpcode = ImmedByte();
7749:
7750: switch (bOpcode)
7751: {
7752: case 0x00: // no_op_xx
7753: return 0;
7754:
7755: case 0x01: // no_op_xx
7756: return 0;
7757:
7758: case 0x02: // no_op_xx
7759: return 0;
7760:
7761: case 0x03: // no_op_xx
7762: return 0;
7763:
7764: case 0x04: // no_op_xx
7765: return 0;
7766:
7767: case 0x05: // no_op_xx
7768: return 0;
7769:
7770: case 0x06: // rlc_xix
7771: MemWriteByte(wAddr, Rlc(MemReadByte(wAddr)));
7772: return 23;
7773:
7774: case 0x07: // no_op_xx
7775: return 0;
7776:
7777: case 0x08: // no_op_xx
7778: return 0;
7779:
7780: case 0x09: // no_op_xx
7781: return 0;
7782:
7783: case 0x0A: // no_op_xx
7784: return 0;
7785:
7786: case 0x0B: // no_op_xx
7787: return 0;
7788:
7789: case 0x0C: // no_op_xx
7790: return 0;
7791:
7792: case 0x0D: // no_op_xx
7793: return 0;
7794:
7795: case 0x0E: // rrc_xix
7796: MemWriteByte(wAddr, Rrc(MemReadByte(wAddr)));
7797: return 23;
7798:
7799: case 0x0F: // no_op_xx
7800: return 0;
7801:
7802: case 0x10: // no_op_xx
7803: return 0;
7804:
7805: case 0x11: // no_op_xx
7806: return 0;
7807:
7808: case 0x12: // no_op_xx
7809: return 0;
7810:
7811: case 0x13: // no_op_xx
7812: return 0;
7813:
7814: case 0x14: // no_op_xx
7815: return 0;
7816:
7817: case 0x15: // no_op_xx
7818: return 0;
7819:
7820: case 0x16: // rl_xix
7821: MemWriteByte(wAddr, Rl(MemReadByte(wAddr)));
7822: return 23;
7823:
7824: case 0x17: // no_op_xx
7825: return 0;
7826:
7827: case 0x18: // no_op_xx
7828: return 0;
7829:
7830: case 0x19: // no_op_xx
7831: return 0;
7832:
7833: case 0x1A: // no_op_xx
7834: return 0;
7835:
7836: case 0x1B: // no_op_xx
7837: return 0;
7838:
7839: case 0x1C: // no_op_xx
7840: return 0;
7841:
7842: case 0x1D: // no_op_xx
7843: return 0;
7844:
7845: case 0x1E: // rr_xix
7846: MemWriteByte(wAddr, Rr(MemReadByte(wAddr)));
7847: return 23;
7848:
7849: case 0x1F: // no_op_xx
7850: return 0;
7851:
7852: case 0x20: // no_op_xx
7853: return 0;
7854:
7855: case 0x21: // no_op_xx
7856: return 0;
7857:
7858: case 0x22: // no_op_xx
7859: return 0;
7860:
7861: case 0x23: // no_op_xx
7862: return 0;
7863:
7864: case 0x24: // no_op_xx
7865: return 0;
7866:
7867: case 0x25: // no_op_xx
7868: return 0;
7869:
7870: case 0x26: // sla_xix
7871: MemWriteByte(wAddr, Sla(MemReadByte(wAddr)));
7872: return 23;
7873:
7874: case 0x27: // no_op_xx
7875: return 0;
7876:
7877: case 0x28: // no_op_xx
7878: return 0;
7879:
7880: case 0x29: // no_op_xx
7881: return 0;
7882:
7883: case 0x2A: // no_op_xx
7884: return 0;
7885:
7886: case 0x2B: // no_op_xx
7887: return 0;
7888:
7889: case 0x2C: // no_op_xx
7890: return 0;
7891:
7892: case 0x2D: // no_op_xx
7893: return 0;
7894:
7895: case 0x2E: // sra_xix
7896: MemWriteByte(wAddr, Sra(MemReadByte(wAddr)));
7897: return 23;
7898:
7899: case 0x2F: // no_op_xx
7900: return 0;
7901:
7902: case 0x30: // no_op_xx
7903: return 0;
7904:
7905: case 0x31: // no_op_xx
7906: return 0;
7907:
7908: case 0x32: // no_op_xx
7909: return 0;
7910:
7911: case 0x33: // no_op_xx
7912: return 0;
7913:
7914: case 0x34: // no_op_xx
7915: return 0;
7916:
7917: case 0x35: // no_op_xx
7918: return 0;
7919:
7920: case 0x36: // sll_xix
7921: MemWriteByte(wAddr, Sll(MemReadByte(wAddr)));
7922: return 23;
7923:
7924: case 0x37: // no_op_xx
7925: return 0;
7926:
7927: case 0x38: // no_op_xx
7928: return 0;
7929:
7930: case 0x39: // no_op_xx
7931: return 0;
7932:
7933: case 0x3A: // no_op_xx
7934: return 0;
7935:
7936: case 0x3B: // no_op_xx
7937: return 0;
7938:
7939: case 0x3C: // no_op_xx
7940: return 0;
7941:
7942: case 0x3D: // no_op_xx
7943: return 0;
7944:
7945: case 0x3E: // srl_xix
7946: MemWriteByte(wAddr, Srl(MemReadByte(wAddr)));
7947: return 23;
7948:
7949: case 0x3F: // no_op_xx
7950: return 0;
7951:
7952: case 0x40: // bit_0_xix
7953: case 0x41: // bit_0_xix
7954: case 0x42: // bit_0_xix
7955: case 0x43: // bit_0_xix
7956: case 0x44: // bit_0_xix
7957: case 0x45: // bit_0_xix
7958: case 0x46: // bit_0_xix
7959: case 0x47: // bit_0_xix
7960: Bit(MemReadByte(wAddr), 0);
7961: return 20;
7962:
7963: case 0x48: // bit_1_xix
7964: case 0x49: // bit_1_xix
7965: case 0x4A: // bit_1_xix
7966: case 0x4B: // bit_1_xix
7967: case 0x4C: // bit_1_xix
7968: case 0x4D: // bit_1_xix
7969: case 0x4E: // bit_1_xix
7970: case 0x4F: // bit_1_xix
7971: Bit(MemReadByte(wAddr), 1);
7972: return 20;
7973:
7974: case 0x50: // bit_2_xix
7975: case 0x51: // bit_2_xix
7976: case 0x52: // bit_2_xix
7977: case 0x53: // bit_2_xix
7978: case 0x54: // bit_2_xix
7979: case 0x55: // bit_2_xix
7980: case 0x56: // bit_2_xix
7981: case 0x57: // bit_2_xix
7982: Bit(MemReadByte(wAddr), 2);
7983: return 20;
7984:
7985: case 0x58: // bit_3_xix
7986: case 0x59: // bit_3_xix
7987: case 0x5A: // bit_3_xix
7988: case 0x5B: // bit_3_xix
7989: case 0x5C: // bit_3_xix
7990: case 0x5D: // bit_3_xix
7991: case 0x5E: // bit_3_xix
7992: case 0x5F: // bit_3_xix
7993: Bit(MemReadByte(wAddr), 3);
7994: return 20;
7995:
7996: case 0x60: // bit_4_xix
7997: case 0x61: // bit_4_xix
7998: case 0x62: // bit_4_xix
7999: case 0x63: // bit_4_xix
8000: case 0x64: // bit_4_xix
8001: case 0x65: // bit_4_xix
8002: case 0x66: // bit_4_xix
8003: case 0x67: // bit_4_xix
8004: Bit(MemReadByte(wAddr), 4);
8005: return 20;
8006:
8007: case 0x68: // bit_5_xix
8008: case 0x69: // bit_5_xix
8009: case 0x6A: // bit_5_xix
8010: case 0x6B: // bit_5_xix
8011: case 0x6C: // bit_5_xix
8012: case 0x6D: // bit_5_xix
8013: case 0x6E: // bit_5_xix
8014: case 0x6F: // bit_5_xix
8015: Bit(MemReadByte(wAddr), 5);
8016: return 20;
8017:
8018: case 0x70: // bit_6_xix
8019: case 0x71: // bit_6_xix
8020: case 0x72: // bit_6_xix
8021: case 0x73: // bit_6_xix
8022: case 0x74: // bit_6_xix
8023: case 0x75: // bit_6_xix
8024: case 0x76: // bit_6_xix
8025: case 0x77: // bit_6_xix
8026: Bit(MemReadByte(wAddr), 6);
8027: return 20;
8028:
8029: case 0x78: // bit_7_xix
8030: case 0x79: // bit_7_xix
8031: case 0x7A: // bit_7_xix
8032: case 0x7B: // bit_7_xix
8033: case 0x7C: // bit_7_xix
8034: case 0x7D: // bit_7_xix
8035: case 0x7E: // bit_7_xix
8036: case 0x7F: // bit_7_xix
8037: Bit(MemReadByte(wAddr), 7);
8038: return 20;
8039:
8040: case 0x80: // no_op_xx
8041: return 0;
8042:
8043: case 0x81: // no_op_xx
8044: return 0;
8045:
8046: case 0x82: // no_op_xx
8047: return 0;
8048:
8049: case 0x83: // no_op_xx
8050: return 0;
8051:
8052: case 0x84: // no_op_xx
8053: return 0;
8054:
8055: case 0x85: // no_op_xx
8056: return 0;
8057:
8058: case 0x86: // res_0_xix
8059: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 0));
8060: return 23;
8061:
8062: case 0x87: // no_op_xx
8063: return 0;
8064:
8065: case 0x88: // no_op_xx
8066: return 0;
8067:
8068: case 0x89: // no_op_xx
8069: return 0;
8070:
8071: case 0x8A: // no_op_xx
8072: return 0;
8073:
8074: case 0x8B: // no_op_xx
8075: return 0;
8076:
8077: case 0x8C: // no_op_xx
8078: return 0;
8079:
8080: case 0x8D: // no_op_xx
8081: return 0;
8082:
8083: case 0x8E: // res_1_xix
8084: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 1));
8085: return 23;
8086:
8087: case 0x8F: // no_op_xx
8088: return 0;
8089:
8090: case 0x90: // no_op_xx
8091: return 0;
8092:
8093: case 0x91: // no_op_xx
8094: return 0;
8095:
8096: case 0x92: // no_op_xx
8097: return 0;
8098:
8099: case 0x93: // no_op_xx
8100: return 0;
8101:
8102: case 0x94: // no_op_xx
8103: return 0;
8104:
8105: case 0x95: // no_op_xx
8106: return 0;
8107:
8108: case 0x96: // res_2_xix
8109: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 2));
8110: return 23;
8111:
8112: case 0x97: // no_op_xx
8113: return 0;
8114:
8115: case 0x98: // no_op_xx
8116: return 0;
8117:
8118: case 0x99: // no_op_xx
8119: return 0;
8120:
8121: case 0x9A: // no_op_xx
8122: return 0;
8123:
8124: case 0x9B: // no_op_xx
8125: return 0;
8126:
8127: case 0x9C: // no_op_xx
8128: return 0;
8129:
8130: case 0x9D: // no_op_xx
8131: return 0;
8132:
8133: case 0x9E: // res_3_xix
8134: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 3));
8135: return 23;
8136:
8137: case 0x9F: // no_op_xx
8138: return 0;
8139:
8140: case 0xA0: // no_op_xx
8141: return 0;
8142:
8143: case 0xA1: // no_op_xx
8144: return 0;
8145:
8146: case 0xA2: // no_op_xx
8147: return 0;
8148:
8149: case 0xA3: // no_op_xx
8150: return 0;
8151:
8152: case 0xA4: // no_op_xx
8153: return 0;
8154:
8155: case 0xA5: // no_op_xx
8156: return 0;
8157:
8158: case 0xA6: // res_4_xix
8159: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 4));
8160: return 23;
8161:
8162: case 0xA7: // no_op_xx
8163: return 0;
8164:
8165: case 0xA8: // no_op_xx
8166: return 0;
8167:
8168: case 0xA9: // no_op_xx
8169: return 0;
8170:
8171: case 0xAA: // no_op_xx
8172: return 0;
8173:
8174: case 0xAB: // no_op_xx
8175: return 0;
8176:
8177: case 0xAC: // no_op_xx
8178: return 0;
8179:
8180: case 0xAD: // no_op_xx
8181: return 0;
8182:
8183: case 0xAE: // res_5_xix
8184: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 5));
8185: return 23;
8186:
8187: case 0xAF: // no_op_xx
8188: return 0;
8189:
8190: case 0xB0: // no_op_xx
8191: return 0;
8192:
8193: case 0xB1: // no_op_xx
8194: return 0;
8195:
8196: case 0xB2: // no_op_xx
8197: return 0;
8198:
8199: case 0xB3: // no_op_xx
8200: return 0;
8201:
8202: case 0xB4: // no_op_xx
8203: return 0;
8204:
8205: case 0xB5: // no_op_xx
8206: return 0;
8207:
8208: case 0xB6: // res_6_xix
8209: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 6));
8210: return 23;
8211:
8212: case 0xB7: // no_op_xx
8213: return 0;
8214:
8215: case 0xB8: // no_op_xx
8216: return 0;
8217:
8218: case 0xB9: // no_op_xx
8219: return 0;
8220:
8221: case 0xBA: // no_op_xx
8222: return 0;
8223:
8224: case 0xBB: // no_op_xx
8225: return 0;
8226:
8227: case 0xBC: // no_op_xx
8228: return 0;
8229:
8230: case 0xBD: // no_op_xx
8231: return 0;
8232:
8233: case 0xBE: // res_7_xix
8234: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 7));
8235: return 23;
8236:
8237: case 0xBF: // no_op_xx
8238: return 0;
8239:
8240: case 0xC0: // no_op_xx
8241: return 0;
8242:
8243: case 0xC1: // no_op_xx
8244: return 0;
8245:
8246: case 0xC2: // no_op_xx
8247: return 0;
8248:
8249: case 0xC3: // no_op_xx
8250: return 0;
8251:
8252: case 0xC4: // no_op_xx
8253: return 0;
8254:
8255: case 0xC5: // no_op_xx
8256: return 0;
8257:
8258: case 0xC6: // set_0_xix
8259: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 0));
8260: return 23;
8261:
8262: case 0xC7: // no_op_xx
8263: return 0;
8264:
8265: case 0xC8: // no_op_xx
8266: return 0;
8267:
8268: case 0xC9: // no_op_xx
8269: return 0;
8270:
8271: case 0xCA: // no_op_xx
8272: return 0;
8273:
8274: case 0xCB: // no_op_xx
8275: return 0;
8276:
8277: case 0xCC: // no_op_xx
8278: return 0;
8279:
8280: case 0xCD: // no_op_xx
8281: return 0;
8282:
8283: case 0xCE: // set_1_xix
8284: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 1));
8285: return 23;
8286:
8287: case 0xCF: // no_op_xx
8288: return 0;
8289:
8290: case 0xD0: // no_op_xx
8291: return 0;
8292:
8293: case 0xD1: // no_op_xx
8294: return 0;
8295:
8296: case 0xD2: // no_op_xx
8297: return 0;
8298:
8299: case 0xD3: // no_op_xx
8300: return 0;
8301:
8302: case 0xD4: // no_op_xx
8303: return 0;
8304:
8305: case 0xD5: // no_op_xx
8306: return 0;
8307:
8308: case 0xD6: // set_2_xix
8309: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 2));
8310: return 23;
8311:
8312: case 0xD7: // no_op_xx
8313: return 0;
8314:
8315: case 0xD8: // no_op_xx
8316: return 0;
8317:
8318: case 0xD9: // no_op_xx
8319: return 0;
8320:
8321: case 0xDA: // no_op_xx
8322: return 0;
8323:
8324: case 0xDB: // no_op_xx
8325: return 0;
8326:
8327: case 0xDC: // no_op_xx
8328: return 0;
8329:
8330: case 0xDD: // no_op_xx
8331: return 0;
8332:
8333: case 0xDE: // set_3_xix
8334: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 3));
8335: return 23;
8336:
8337: case 0xDF: // no_op_xx
8338: return 0;
8339:
8340: case 0xE0: // no_op_xx
8341: return 0;
8342:
8343: case 0xE1: // no_op_xx
8344: return 0;
8345:
8346: case 0xE2: // no_op_xx
8347: return 0;
8348:
8349: case 0xE3: // no_op_xx
8350: return 0;
8351:
8352: case 0xE4: // no_op_xx
8353: return 0;
8354:
8355: case 0xE5: // no_op_xx
8356: return 0;
8357:
8358: case 0xE6: // set_4_xix
8359: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 4));
8360: return 23;
8361:
8362: case 0xE7: // no_op_xx
8363: return 0;
8364:
8365: case 0xE8: // no_op_xx
8366: return 0;
8367:
8368: case 0xE9: // no_op_xx
8369: return 0;
8370:
8371: case 0xEA: // no_op_xx
8372: return 0;
8373:
8374: case 0xEB: // no_op_xx
8375: return 0;
8376:
8377: case 0xEC: // no_op_xx
8378: return 0;
8379:
8380: case 0xED: // no_op_xx
8381: return 0;
8382:
8383: case 0xEE: // set_5_xix
8384: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 5));
8385: return 23;
8386:
8387: case 0xEF: // no_op_xx
8388: return 0;
8389:
8390: case 0xF0: // no_op_xx
8391: return 0;
8392:
8393: case 0xF1: // no_op_xx
8394: return 0;
8395:
8396: case 0xF2: // no_op_xx
8397: return 0;
8398:
8399: case 0xF3: // no_op_xx
8400: return 0;
8401:
8402: case 0xF4: // no_op_xx
8403: return 0;
8404:
8405: case 0xF5: // no_op_xx
8406: return 0;
8407:
8408: case 0xF6: // set_6_xix
8409: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 6));
8410: return 23;
8411:
8412: case 0xF7: // no_op_xx
8413: return 0;
8414:
8415: case 0xF8: // no_op_xx
8416: return 0;
8417:
8418: case 0xF9: // no_op_xx
8419: return 0;
8420:
8421: case 0xFA: // no_op_xx
8422: return 0;
8423:
8424: case 0xFB: // no_op_xx
8425: return 0;
8426:
8427: case 0xFC: // no_op_xx
8428: return 0;
8429:
8430: case 0xFD: // no_op_xx
8431: return 0;
8432:
8433: case 0xFE: // set_7_xix
8434: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 7));
8435: return 23;
8436:
8437: case 0xFF: // no_op_x
8438: return 0;
8439:
8440: default:
8441: _ASSERT(FALSE);
8442: return 0;
8443: }
8444: }
8445:
8446: /* ***************************************************************************
8447: * Debugger shit
8448: * ***************************************************************************
8449: */
8450:
8451: /*** Z80Em: Portable Z80 emulator *******************************************/
8452: /*** ***/
8453: /*** Z80Dasm.h ***/
8454: /*** ***/
8455: /*** This file contains a routine to disassemble a buffer containing Z80 ***/
8456: /*** opcodes. It is included from Z80Debug.c and z80dasm.c ***/
8457: /*** ***/
8458: /*** Copyright (C) Marcel de Kogel 1996,1997 ***/
8459: /*** You are not allowed to distribute this software commercially ***/
8460: /*** Please, notify me, if you make any changes to this file ***/
8461: /****************************************************************************/
8462:
8463: #include <stdio.h>
8464: #include <string.h>
8465:
8466: static char *mnemonic_xx_cb[256]=
8467: {
8468: "#","#","#","#","#","#","rlc Y" ,"#",
8469: "#","#","#","#","#","#","rrc Y" ,"#",
8470: "#","#","#","#","#","#","rl Y" ,"#",
8471: "#","#","#","#","#","#","rr Y" ,"#",
8472: "#","#","#","#","#","#","sla Y" ,"#",
8473: "#","#","#","#","#","#","sra Y" ,"#",
8474: "#","#","#","#","#","#","sll Y" ,"#",
8475: "#","#","#","#","#","#","srl Y" ,"#",
8476: "#","#","#","#","#","#","bit 0,Y","#",
8477: "#","#","#","#","#","#","bit 1,Y","#",
8478: "#","#","#","#","#","#","bit 2,Y","#",
8479: "#","#","#","#","#","#","bit 3,Y","#",
8480: "#","#","#","#","#","#","bit 4,Y","#",
8481: "#","#","#","#","#","#","bit 5,Y","#",
8482: "#","#","#","#","#","#","bit 6,Y","#",
8483: "#","#","#","#","#","#","bit 7,Y","#",
8484: "#","#","#","#","#","#","res 0,Y","#",
8485: "#","#","#","#","#","#","res 1,Y","#",
8486: "#","#","#","#","#","#","res 2,Y","#",
8487: "#","#","#","#","#","#","res 3,Y","#",
8488: "#","#","#","#","#","#","res 4,Y","#",
8489: "#","#","#","#","#","#","res 5,Y","#",
8490: "#","#","#","#","#","#","res 6,Y","#",
8491: "#","#","#","#","#","#","res 7,Y","#",
8492: "#","#","#","#","#","#","set 0,Y","#",
8493: "#","#","#","#","#","#","set 1,Y","#",
8494: "#","#","#","#","#","#","set 2,Y","#",
8495: "#","#","#","#","#","#","set 3,Y","#",
8496: "#","#","#","#","#","#","set 4,Y","#",
8497: "#","#","#","#","#","#","set 5,Y","#",
8498: "#","#","#","#","#","#","set 6,Y","#",
8499: "#","#","#","#","#","#","set 7,Y","#"
8500: };
8501:
8502: static char *mnemonic_cb[256]=
8503: {
8504: "rlc b" ,"rlc c" ,"rlc d" ,"rlc e" ,"rlc h" ,"rlc l" ,"rlc (hl)" ,"rlc a" ,
8505: "rrc b" ,"rrc c" ,"rrc d" ,"rrc e" ,"rrc h" ,"rrc l" ,"rrc (hl)" ,"rrc a" ,
8506: "rl b" ,"rl c" ,"rl d" ,"rl e" ,"rl h" ,"rl l" ,"rl (hl)" ,"rl a" ,
8507: "rr b" ,"rr c" ,"rr d" ,"rr e" ,"rr h" ,"rr l" ,"rr (hl)" ,"rr a" ,
8508: "sla b" ,"sla c" ,"sla d" ,"sla e" ,"sla h" ,"sla l" ,"sla (hl)" ,"sla a" ,
8509: "sra b" ,"sra c" ,"sra d" ,"sra e" ,"sra h" ,"sra l" ,"sra (hl)" ,"sra a" ,
8510: "sll b" ,"sll c" ,"sll d" ,"sll e" ,"sll h" ,"sll l" ,"sll (hl)" ,"sll a" ,
8511: "srl b" ,"srl c" ,"srl d" ,"srl e" ,"srl h" ,"srl l" ,"srl (hl)" ,"srl a" ,
8512: "bit 0,b","bit 0,c","bit 0,d","bit 0,e","bit 0,h","bit 0,l","bit 0,(hl)","bit 0,a",
8513: "bit 1,b","bit 1,c","bit 1,d","bit 1,e","bit 1,h","bit 1,l","bit 1,(hl)","bit 1,a",
8514: "bit 2,b","bit 2,c","bit 2,d","bit 2,e","bit 2,h","bit 2,l","bit 2,(hl)","bit 2,a",
8515: "bit 3,b","bit 3,c","bit 3,d","bit 3,e","bit 3,h","bit 3,l","bit 3,(hl)","bit 3,a",
8516: "bit 4,b","bit 4,c","bit 4,d","bit 4,e","bit 4,h","bit 4,l","bit 4,(hl)","bit 4,a",
8517: "bit 5,b","bit 5,c","bit 5,d","bit 5,e","bit 5,h","bit 5,l","bit 5,(hl)","bit 5,a",
8518: "bit 6,b","bit 6,c","bit 6,d","bit 6,e","bit 6,h","bit 6,l","bit 6,(hl)","bit 6,a",
8519: "bit 7,b","bit 7,c","bit 7,d","bit 7,e","bit 7,h","bit 7,l","bit 7,(hl)","bit 7,a",
8520: "res 0,b","res 0,c","res 0,d","res 0,e","res 0,h","res 0,l","res 0,(hl)","res 0,a",
8521: "res 1,b","res 1,c","res 1,d","res 1,e","res 1,h","res 1,l","res 1,(hl)","res 1,a",
8522: "res 2,b","res 2,c","res 2,d","res 2,e","res 2,h","res 2,l","res 2,(hl)","res 2,a",
8523: "res 3,b","res 3,c","res 3,d","res 3,e","res 3,h","res 3,l","res 3,(hl)","res 3,a",
8524: "res 4,b","res 4,c","res 4,d","res 4,e","res 4,h","res 4,l","res 4,(hl)","res 4,a",
8525: "res 5,b","res 5,c","res 5,d","res 5,e","res 5,h","res 5,l","res 5,(hl)","res 5,a",
8526: "res 6,b","res 6,c","res 6,d","res 6,e","res 6,h","res 6,l","res 6,(hl)","res 6,a",
8527: "res 7,b","res 7,c","res 7,d","res 7,e","res 7,h","res 7,l","res 7,(hl)","res 7,a",
8528: "set 0,b","set 0,c","set 0,d","set 0,e","set 0,h","set 0,l","set 0,(hl)","set 0,a",
8529: "set 1,b","set 1,c","set 1,d","set 1,e","set 1,h","set 1,l","set 1,(hl)","set 1,a",
8530: "set 2,b","set 2,c","set 2,d","set 2,e","set 2,h","set 2,l","set 2,(hl)","set 2,a",
8531: "set 3,b","set 3,c","set 3,d","set 3,e","set 3,h","set 3,l","set 3,(hl)","set 3,a",
8532: "set 4,b","set 4,c","set 4,d","set 4,e","set 4,h","set 4,l","set 4,(hl)","set 4,a",
8533: "set 5,b","set 5,c","set 5,d","set 5,e","set 5,h","set 5,l","set 5,(hl)","set 5,a",
8534: "set 6,b","set 6,c","set 6,d","set 6,e","set 6,h","set 6,l","set 6,(hl)","set 6,a",
8535: "set 7,b","set 7,c","set 7,d","set 7,e","set 7,h","set 7,l","set 7,(hl)","set 7,a"
8536: };
8537:
8538: static char *mnemonic_ed[256]=
8539: {
8540: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8541: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8542: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8543: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8544: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8545: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8546: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8547: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8548: "in b,(c)","out (c),b","sbc hl,bc","ld (W),bc","neg","retn","im 0","ld i,a",
8549: "in c,(c)","out (c),c","adc hl,bc","ld bc,(W)","!" ,"reti","!" ,"ld r,a",
8550: "in d,(c)","out (c),d","sbc hl,de","ld (W),de","!" ,"!" ,"im 1","ld a,i",
8551: "in e,(c)","out (c),e","adc hl,de","ld de,(W)","!" ,"!" ,"im 2","ld a,r",
8552: "in h,(c)","out (c),h","sbc hl,hl","ld (W),hl","!" ,"!" ,"!" ,"rrd" ,
8553: "in l,(c)","out (c),l","adc hl,hl","ld hl,(W)","!" ,"!" ,"!" ,"rld" ,
8554: "in 0,(c)","out (c),0","sbc hl,sp","ld (W),sp","!" ,"!" ,"!" ,"!" ,
8555: "in a,(c)","out (c),a","adc hl,sp","ld sp,(W)","!" ,"!" ,"!" ,"!" ,
8556: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8557: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8558: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8559: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8560: "ldi" ,"cpi" ,"ini" ,"outi" ,"!" ,"!" ,"!" ,"!" ,
8561: "ldd" ,"cpd" ,"ind" ,"outd" ,"!" ,"!" ,"!" ,"!" ,
8562: "ldir" ,"cpir" ,"inir" ,"otir" ,"!" ,"!" ,"!" ,"!" ,
8563: "lddr" ,"cpdr" ,"indr" ,"otdr" ,"!" ,"!" ,"!" ,"!" ,
8564: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8565: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8566: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8567: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8568: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8569: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8570: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8571: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!"
8572: };
8573:
8574: static char *mnemonic_xx[256]=
8575: {
8576: "@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8577: "@" ,"add I,bc","@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8578: "@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8579: "@" ,"add I,de","@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8580: "@" ,"ld I,W" ,"ld (W),I","inc I" ,"inc Ih" ,"dec Ih" ,"ld Ih,B","@" ,
8581: "@" ,"add I,I" ,"ld I,(W)","dec I" ,"inc Il" ,"dec Il" ,"ld Il,B","@" ,
8582: "@" ,"@" ,"@" ,"@" ,"inc X" ,"dec X" ,"ld X,B" ,"@" ,
8583: "@" ,"add I,sp","@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8584: "@" ,"@" ,"@" ,"@" ,"ld b,Ih" ,"ld b,Il" ,"ld b,X" ,"@" ,
8585: "@" ,"@" ,"@" ,"@" ,"ld c,Ih" ,"ld c,Il" ,"ld c,X" ,"@" ,
8586: "@" ,"@" ,"@" ,"@" ,"ld d,Ih" ,"ld d,Il" ,"ld d,X" ,"@" ,
8587: "@" ,"@" ,"@" ,"@" ,"ld e,Ih" ,"ld e,Il" ,"ld e,X" ,"@" ,
8588: "ld Ih,b","ld Ih,c" ,"ld Ih,d" ,"ld Ih,e" ,"ld Ih,h" ,"ld Ih,l" ,"ld h,X" ,"ld Ih,a",
8589: "ld Il,b","ld Il,c" ,"ld Il,d" ,"ld Il,e" ,"ld Il,h" ,"ld Il,l" ,"ld l,X" ,"ld Il,a",
8590: "ld X,b" ,"ld X,c" ,"ld X,d" ,"ld X,e" ,"ld X,h" ,"ld X,l" ,"@" ,"ld X,a" ,
8591: "@" ,"@" ,"@" ,"@" ,"ld a,Ih" ,"ld a,Il" ,"ld a,X" ,"@" ,
8592: "@" ,"@" ,"@" ,"@" ,"add a,Ih","add a,Il","add a,X","@" ,
8593: "@" ,"@" ,"@" ,"@" ,"adc a,Ih","adc a,Il","adc a,X","@" ,
8594: "@" ,"@" ,"@" ,"@" ,"sub Ih" ,"sub Il" ,"sub X" ,"@" ,
8595: "@" ,"@" ,"@" ,"@" ,"sbc a,Ih","sbc a,Il","sbc a,X","@" ,
8596: "@" ,"@" ,"@" ,"@" ,"and Ih" ,"and Il" ,"and X" ,"@" ,
8597: "@" ,"@" ,"@" ,"@" ,"xor Ih" ,"xor Il" ,"xor X" ,"@" ,
8598: "@" ,"@" ,"@" ,"@" ,"or Ih" ,"or Il" ,"or X" ,"@" ,
8599: "@" ,"@" ,"@" ,"@" ,"cp Ih" ,"cp Il" ,"cp X" ,"@" ,
8600: "@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8601: "@" ,"@" ,"@" ,"fd cb" ,"@" ,"@" ,"@" ,"@" ,
8602: "@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8603: "@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8604: "@" ,"pop I" ,"@" ,"ex (sp),I","@" ,"push I" ,"@" ,"@" ,
8605: "@" ,"jp (I)" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8606: "@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8607: "@" ,"ld sp,I" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@"
8608: };
8609:
8610: static char *mnemonic_main[256]=
8611: {
8612: "nop" ,"ld bc,W" ,"ld (bc),a","inc bc" ,"inc b" ,"dec b" ,"ld b,B" ,"rlca" ,
8613: "ex af,af'","add hl,bc","ld a,(bc)","dec bc" ,"inc c" ,"dec c" ,"ld c,B" ,"rrca" ,
8614: "djnz R" ,"ld de,W" ,"ld (de),a","inc de" ,"inc d" ,"dec d" ,"ld d,B" ,"rla" ,
8615: "jr R" ,"add hl,de","ld a,(de)","dec de" ,"inc e" ,"dec e" ,"ld e,B" ,"rra" ,
8616: "jr nz,R" ,"ld hl,W" ,"ld (W),hl","inc hl" ,"inc h" ,"dec h" ,"ld h,B" ,"daa" ,
8617: "jr z,R" ,"add hl,hl","ld hl,(W)","dec hl" ,"inc l" ,"dec l" ,"ld l,B" ,"cpl" ,
8618: "jr nc,R" ,"ld sp,W" ,"ld (W),a" ,"inc sp" ,"inc (hl)" ,"dec (hl)" ,"ld (hl),B" ,"scf" ,
8619: "jr c,R" ,"add hl,sp","ld a,(W)" ,"dec sp" ,"inc a" ,"dec a" ,"ld a,B" ,"ccf" ,
8620: "ld b,b" ,"ld b,c" ,"ld b,d" ,"ld b,e" ,"ld b,h" ,"ld b,l" ,"ld b,(hl)" ,"ld b,a" ,
8621: "ld c,b" ,"ld c,c" ,"ld c,d" ,"ld c,e" ,"ld c,h" ,"ld c,l" ,"ld c,(hl)" ,"ld c,a" ,
8622: "ld d,b" ,"ld d,c" ,"ld d,d" ,"ld d,e" ,"ld d,h" ,"ld d,l" ,"ld d,(hl)" ,"ld d,a" ,
8623: "ld e,b" ,"ld e,c" ,"ld e,d" ,"ld e,e" ,"ld e,h" ,"ld e,l" ,"ld e,(hl)" ,"ld e,a" ,
8624: "ld h,b" ,"ld h,c" ,"ld h,d" ,"ld h,e" ,"ld h,h" ,"ld h,l" ,"ld h,(hl)" ,"ld h,a" ,
8625: "ld l,b" ,"ld l,c" ,"ld l,d" ,"ld l,e" ,"ld l,h" ,"ld l,l" ,"ld l,(hl)" ,"ld l,a" ,
8626: "ld (hl),b","ld (hl),c","ld (hl),d","ld (hl),e" ,"ld (hl),h","ld (hl),l","halt" ,"ld (hl),a",
8627: "ld a,b" ,"ld a,c" ,"ld a,d" ,"ld a,e" ,"ld a,h" ,"ld a,l" ,"ld a,(hl)" ,"ld a,a" ,
8628: "add a,b" ,"add a,c" ,"add a,d" ,"add a,e" ,"add a,h" ,"add a,l" ,"add a,(hl)","add a,a" ,
8629: "adc a,b" ,"adc a,c" ,"adc a,d" ,"adc a,e" ,"adc a,h" ,"adc a,l" ,"adc a,(hl)","adc a,a" ,
8630: "sub b" ,"sub c" ,"sub d" ,"sub e" ,"sub h" ,"sub l" ,"sub (hl)" ,"sub a" ,
8631: "sbc a,b" ,"sbc a,c" ,"sbc a,d" ,"sbc a,e" ,"sbc a,h" ,"sbc a,l" ,"sbc a,(hl)","sbc a,a" ,
8632: "and b" ,"and c" ,"and d" ,"and e" ,"and h" ,"and l" ,"and (hl)" ,"and a" ,
8633: "xor b" ,"xor c" ,"xor d" ,"xor e" ,"xor h" ,"xor l" ,"xor (hl)" ,"xor a" ,
8634: "or b" ,"or c" ,"or d" ,"or e" ,"or h" ,"or l" ,"or (hl)" ,"or a" ,
8635: "cp b" ,"cp c" ,"cp d" ,"cp e" ,"cp h" ,"cp l" ,"cp (hl)" ,"cp a" ,
8636: "ret nz" ,"pop bc" ,"jp nz,W" ,"jp W" ,"call nz,W","push bc" ,"add a,B" ,"rst 00h" ,
8637: "ret z" ,"ret" ,"jp z,W" ,"cb" ,"call z,W" ,"call W" ,"adc a,B" ,"rst 08h" ,
8638: "ret nc" ,"pop de" ,"jp nc,W" ,"out (B),a" ,"call nc,W","push de" ,"sub B" ,"rst 10h" ,
8639: "ret c" ,"exx" ,"jp c,W" ,"in a,(B)" ,"call c,W" ,"dd" ,"sbc a,B" ,"rst 18h" ,
8640: "ret po" ,"pop hl" ,"jp po,W" ,"ex (sp),hl","call po,W","push hl" ,"and B" ,"rst 20h" ,
8641: "ret pe" ,"jp (hl)" ,"jp pe,W" ,"ex de,hl" ,"call pe,W","ed" ,"xor B" ,"rst 28h" ,
8642: "ret p" ,"pop af" ,"jp p,W" ,"di" ,"call p,W" ,"push af" ,"or B" ,"rst 30h" ,
8643: "ret m" ,"ld sp,hl" ,"jp m,W" ,"ei" ,"call m,W" ,"fd" ,"cp B" ,"rst 38h"
8644: };
8645:
8646: static char Sign (unsigned char a)
8647: {
8648: return (a&128)? '-':'+';
8649: }
8650:
8651: static int Abs (unsigned char a)
8652: {
8653: if (a&128) return 256-a;
8654: else return a;
8655: }
8656:
8657: /****************************************************************************/
8658: /* Disassemble first opcode in buffer and return number of bytes it takes */
8659: /****************************************************************************/
8660: int Z80_Dasm (unsigned char *buffer,char *dest,unsigned PC) {
8661: char *S;
8662: char *r;
8663: int i,j,k;
8664: unsigned char buf[10];
8665: char Offset;
8666: i=Offset=0;
8667: r="INTERNAL PROGRAM ERROR";
8668: dest[0]='\0';
8669: switch (buffer[i])
8670: {
8671: case 0xCB:
8672: i++;
8673: S=mnemonic_cb[buffer[i++]];
8674: break;
8675: case 0xED:
8676: i++;
8677: S=mnemonic_ed[buffer[i++]];
8678: break;
8679: case 0xDD:
8680: i++;
8681: r="ix";
8682: switch (buffer[i])
8683: {
8684: case 0xcb:
8685: i++;
8686: Offset=buffer[i++];
8687: S=mnemonic_xx_cb[buffer[i++]];
8688: break;
8689: default:
8690: S=mnemonic_xx[buffer[i++]];
8691: break;
8692: }
8693: break;
8694: case 0xFD:
8695: i++;
8696: r="iy";
8697: switch (buffer[i])
8698: {
8699: case 0xcb:
8700: i++;
8701: Offset=buffer[i++];
8702: S=mnemonic_xx_cb[buffer[i++]];
8703: break;
8704: default:
8705: S=mnemonic_xx[buffer[i++]];
8706: break;
8707: }
8708: break;
8709: default:
8710: S=mnemonic_main[buffer[i++]];
8711: break;
8712: }
8713: for (j=0;S[j];++j)
8714: {
8715: switch (S[j])
8716: {
8717: case 'B':
8718: sprintf (buf,"$%02x",buffer[i++]);
8719: strcat (dest,buf);
8720: break;
8721: case 'R':
8722: sprintf (buf,"$%04x",(PC+2+(signed char)buffer[i])&0xFFFF);
8723: i++;
8724: strcat (dest,buf);
8725: break;
8726: case 'W':
8727: sprintf (buf,"$%04x",buffer[i]+buffer[i+1]*256);
8728: i+=2;
8729: strcat (dest,buf);
8730: break;
8731: case 'X':
8732: sprintf (buf,"(%s%c$%02x)",r,Sign(buffer[i]),Abs(buffer[i]));
8733: i++;
8734: strcat (dest,buf);
8735: break;
8736: case 'Y':
8737: sprintf (buf,"(%s%c$%02x)",r,Sign(Offset),Abs(Offset));
8738: strcat (dest,buf);
8739: break;
8740: case 'I':
8741: strcat (dest,r);
8742: break;
8743: case '!':
8744: sprintf (dest,"db $ed,$%02x",buffer[1]);
8745: return 2;
8746: case '@':
8747: sprintf (dest,"db $%02x",buffer[0]);
8748: return 1;
8749: case '#':
8750: sprintf (dest,"db $%02x,$cb,$%02x",buffer[0],buffer[2]);
8751: return 2;
8752: case ' ':
8753: k=strlen(dest);
8754: if (k<6) k=7-k;
8755: else k=1;
8756: memset (buf,' ',k);
8757: buf[k]='\0';
8758: strcat (dest,buf);
8759: break;
8760: default:
8761: buf[0]=S[j];
8762: buf[1]='\0';
8763: strcat (dest,buf);
8764: break;
8765: }
8766: }
8767: return i;
8768: }
8769:
8770: UINT32 mz80GetElapsedTicks(UINT32 dwClearIt)
8771: {
8772: UINT32 dwTempVar = 0;
8773: char string[150];
8774:
8775: dwTempVar = dwElapsedTicks;
8776: if (dwClearIt)
8777: dwElapsedTicks = 0;
8778: return(dwTempVar);
8779: }
8780:
8781: void mz80ReleaseTimeslice()
8782: {
8783: cCycles = 0;
8784: }
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