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1.1 root 1: /* z80stb.c
2: * Zilog Z80 processor emulator in C. Modified to be API compliant with Neil
3: * Bradley's MZ80 (for ported projects)
4: * Ported to 'C' by Jeff Mitchell; original copyright follows:
5: *
6: * Abstract:
7: * Internal declarations for Zilog Z80 emulator.
8: *
9: * Revisions:
10: * 18-Apr-97 EAM Created
11: * ??-???-97 EAM Released in MageX 0.5
12: * 26-Jul-97 EAM Fixed Time Pilot slowdown bug and
13: * Gyruss hiscore bugs (opcode 0xC3)
14: *
15: * Original copyright (C) 1997 Edward Massey
16: */
17:
1.1.1.2 ! root 18: #include <generator.h>
! 19:
1.1 root 20: #define FALSE 0
21: #define TRUE 1
22:
23: #ifdef WORDS_BIGENDIAN
1.1.1.2 ! root 24: #define HOST_TO_LE16(y) ( (((y)>>8)&0x00FF) + (((y)<<8)&0xFF00) )
1.1 root 25: #else
26: #define HOST_TO_LE16(y) (y)
27: #endif
28:
29: #include <stdio.h>
30: #include <stdlib.h>
31: #include <assert.h>
32: #include "cmz80.h"
33: #include "z80stb.h"
34:
35: /* ***************************************************************************
36: * Edward's Internals (so to speak)
37: * ***************************************************************************
38: */
39:
40: #define _ASSERT assert
41:
42: union { /* WARN: Endianness! */
43: WORD m_regAF;
44: struct {
45: #ifdef WORDS_BIGENDIAN
46: BYTE m_regA;
47: BYTE m_regF;
48: #else
49: BYTE m_regF;
50: BYTE m_regA;
51: #endif
52: } regAFs;
53: } regAF;
54: #define m_regAF regAF.m_regAF
55: #define m_regF regAF.regAFs.m_regF
56: #define m_regA regAF.regAFs.m_regA
57:
58: union { /* WARN: Endianness! */
59: WORD m_regBC;
60: struct {
61: #ifdef WORDS_BIGENDIAN
62: BYTE m_regB;
63: BYTE m_regC;
64: #else
65: BYTE m_regC;
66: BYTE m_regB;
67: #endif
68: } regBCs;
69: } regBC;
70: #define m_regBC regBC.m_regBC
71: #define m_regB regBC.regBCs.m_regB
72: #define m_regC regBC.regBCs.m_regC
73:
74: union { /* WARN: Endianness! */
75: WORD m_regDE;
76: struct {
77: #ifdef WORDS_BIGENDIAN
78: BYTE m_regD;
79: BYTE m_regE;
80: #else
81: BYTE m_regE;
82: BYTE m_regD;
83: #endif
84: } regDEs;
85: } regDE;
86: #define m_regDE regDE.m_regDE
87: #define m_regD regDE.regDEs.m_regD
88: #define m_regE regDE.regDEs.m_regE
89:
90: union { /* WARN: Endianness! */
91: WORD m_regHL;
92: struct {
93: #ifdef WORDS_BIGENDIAN
94: BYTE m_regH;
95: BYTE m_regL;
96: #else
97: BYTE m_regL;
98: BYTE m_regH;
99: #endif
100: } regHLs;
101: } regHL;
102: #define m_regHL regHL.m_regHL
103: #define m_regH regHL.regHLs.m_regH
104: #define m_regL regHL.regHLs.m_regL
105:
106: union { /* WARN: Endianness! */
107: WORD m_regIX;
108: struct {
109: #ifdef WORDS_BIGENDIAN
110: BYTE m_regIXh;
111: BYTE m_regIXl;
112: #else
113: BYTE m_regIXl;
114: BYTE m_regIXh;
115: #endif
116: } regIXs;
117: } regIX;
118: #define m_regIX regIX.m_regIX
119: #define m_regIXl regIX.regIXs.m_regIXl
120: #define m_regIXh regIX.regIXs.m_regIXh
121:
122: union {
123: WORD m_regIY;
124: struct {
125: #ifdef WORDS_BIGENDIAN
126: BYTE m_regIYh;
127: BYTE m_regIYl;
128: #else
129: BYTE m_regIYl;
130: BYTE m_regIYh;
131: #endif
132: } regIYs;
133: } regIY;
134: #define m_regIY regIY.m_regIY
135: #define m_regIYl regIY.regIYs.m_regIYl
136: #define m_regIYh regIY.regIYs.m_regIYh
137:
138: const BYTE *m_rgbOpcode; // takes place of the PC register
139: LPBYTE m_rgbStack; // takes place of the SP register
140: LPBYTE m_rgbMemory; // direct access to memory buffer (RAM)
141: const BYTE *m_rgbOpcodeBase; // "base" pointer for m_rgbOpcode
142: LPBYTE m_rgbStackBase;
143: static int cCycles = 0;
144:
145: BYTE m_regR; // consider: should be int for performance?
146: BYTE m_regI; // consider: combine into
147:
148: // TODO: combine into a single int...
149: int m_iff1, m_iff2;
150: BOOL m_fHalt;
151: int m_nIM;
152: BOOL m_fPendingInterrupt = FALSE;
153:
154: WORD m_regAF2;
155: static WORD m_regBC2;
156: static WORD m_regDE2;
157: static WORD m_regHL2;
158: WORD z80intAddr = 0x38;
159: WORD z80nmiAddr = 0x66;
160:
161: /* ***************************************************************************
162: * Pre-calculated math tables and junk (sucked from Marat and Edward)
163: * ***************************************************************************
164: */
165: void InitTables (void);
166:
167: BYTE ZSTable[256];
168: BYTE ZSPTable[256];
169: BYTE rgfAdd[256][256];
170: BYTE rgfSub[256][256];
171: BYTE rgfAddc[256][256][2];
172: BYTE rgfSubc[256][256][2];
173: BYTE rgfInc[256];
174: BYTE rgfDec[256];
175: BYTE rgfBit[256][8];
176: static UINT32 dwElapsedTicks = 0;
177:
178: /* #include "z80daa.h" */
179: #include "z80stbd.h"
180:
181: /* ***************************************************************************
182: * Retrocade guts stuff
183: * ***************************************************************************
184: */
185: static struct MemoryReadByte *z80MemoryRead = NULL;
186: static struct MemoryWriteByte *z80MemoryWrite = NULL;
187: static struct z80PortRead *z80IoRead = NULL;
188: static struct z80PortWrite *z80IoWrite = NULL;
189: WORD z80pc = 0;
190:
191: /* ***************************************************************************
192: * Retrocade interface follows
193: * ***************************************************************************
194: */
195:
196: /* reset registers, interrupts, memory read/write memory handlers,
197: * port read and writing handlers, etc.
198: */
199: void mz80reset(void) {
200:
201: InitTables();
202:
203: m_fPendingInterrupt = FALSE;
204: m_rgbOpcodeBase = m_rgbMemory;
205: /* m_rgbMemory = */
206: m_rgbStackBase = m_rgbMemory;
207:
208: m_regAF = 0;
209: m_regBC = 0;
210: m_regDE = 0;
211: m_regHL = 0;
212: m_regAF2 = 0;
213: m_regBC2 = 0;
214: m_regDE2 = 0;
215: m_regHL2 = 0;
216: m_regR = rand();
217: m_regI = 0;
218: m_fHalt = FALSE;
219: m_nIM = 0;
220: m_regIX = 0xffff; // Yes, this intentional, and the way a Z80 comes
221: m_regIY = 0xffff; // up in power-on state!
222: m_iff1 = 0;
223: m_iff2 = 0;
224: z80intAddr = 0x38;
225: z80nmiAddr = 0x66;
226:
227: SetPC(0x0000);
228: SetSP(0x0000);
229:
230: #if 0
231: fprintf ( stderr, "Reset\n" );
232: #endif
233: }
234:
235: /* UINT32 mz80int(UINT32 a) {
236: * return ( Irq ( (BYTE) ( a & 0xFF ) ) );
237: * }
238: */
239:
240: /* UINT32 mz80nmi(void) {
241: * return ( Nmi() );
242: * }
243: */
244:
245: /* ***************************************************************************
246: * Edward Memory Handlers (guesses)
247: * ***************************************************************************
248: */
249:
250: #define ImmedByte() *m_rgbOpcode++
251:
252: /* static */ UINT16 ImmedWord ( void ) {
253: WORD w = HOST_TO_LE16(*(WORD*)m_rgbOpcode);
254: m_rgbOpcode += 2;
255: return w; // attn: little endian specific
256: }
257:
258: #define GetPC() ( (WORD)(m_rgbOpcode - m_rgbOpcodeBase) )
259:
260: void SetPC ( WORD wAddr ) {
261: m_rgbOpcode = &m_rgbOpcodeBase[wAddr];
262: }
263:
264: void AdjustPC ( signed char cb ) {
265: m_rgbOpcode += cb;
266: }
267:
268: void Push(WORD wArg) {
269: MemWriteByte(--m_rgbStack - m_rgbStackBase, HIBYTE(wArg));
270: MemWriteByte(--m_rgbStack - m_rgbStackBase, LOBYTE(wArg));
271: }
272:
273: WORD Pop() {
274: unsigned short wAddr = 0;
275:
276: wAddr = MemReadByte(m_rgbStack++ - m_rgbStackBase);
277: wAddr |= (MemReadByte(m_rgbStack++ - m_rgbStackBase) << 8);
278:
279: return(wAddr);
280: }
281:
282: WORD GetSP() {
283: return (WORD)(m_rgbStack - m_rgbStackBase);
284: }
285:
286: void SetSP(WORD wAddr) {
287: m_rgbStack = &m_rgbStackBase[wAddr];
288: }
289:
290: /* static */ UINT8 mz80GetMemory ( UINT16 addr ) {
291: struct MemoryReadByte *mr = z80MemoryRead;
292:
293: z80pc = GetPC(); /* for some of the platforms */
294:
295: while ( mr -> lowAddr != 0xffffffff ) {
296:
297: if (addr >= mr->lowAddr && addr <= mr->highAddr) {
298: z80pc = GetPC();
299: return ( mr -> memoryCall ( addr, mr ) );
300: }
301:
302: ++mr;
303:
304: }
305:
306: return ( m_rgbMemory [ addr ] );
307: }
308:
309: /* static */ void mz80PutMemory ( unsigned short int addr, unsigned char byte ) {
310: struct MemoryWriteByte *mr = z80MemoryWrite;
311:
312: while ( mr->lowAddr != 0xffffffff ) {
313: if (addr >= mr->lowAddr && addr <= mr->highAddr) {
314: z80pc = GetPC();
315: mr->memoryCall(addr, byte, mr);
316: return;
317: }
318: mr++;
319: }
320:
321: m_rgbMemory [ addr ] = byte;
322:
323: }
324:
325: BYTE In(BYTE bPort) {
326: BYTE bVal;
327: // BYTE bVal = m_rgpfnPortRead[bPort](bPort);
328:
329: struct z80PortRead *mr = z80IoRead;
330:
331: z80pc = GetPC(); /* for some of the platforms */
332:
333: while ( mr->lowIoAddr != 0xffff ) {
334: if ( bPort >= mr->lowIoAddr && bPort <= mr->highIoAddr) {
335: bVal = mr->IOCall ( bPort, mr );
336: break;
337: }
338: mr++;
339: }
340:
341: m_regF = (m_regF & C_FLAG) | ZSPTable[bVal];
342:
343: return bVal;
344: }
345:
346: BYTE InRaw (BYTE bPort) {
347: BYTE bVal;
348:
349: struct z80PortRead *mr = z80IoRead;
350:
351: z80pc = GetPC(); /* for some of the platforms */
352:
353: while ( mr->lowIoAddr != 0xffff ) {
354: if ( bPort >= mr->lowIoAddr && bPort <= mr->highIoAddr) {
355: bVal = mr->IOCall ( bPort, mr );
356: break;
357: }
358: mr++;
359: }
360:
361: // m_regF = (m_regF & C_FLAG) | ZSPTable[bVal];
362: return bVal;
363: }
364:
365: void Out(BYTE bPort, BYTE bVal) {
366: // m_rgpfnPortWrite[bPort](bPort, bVal);
367: struct z80PortWrite *mr = z80IoWrite;
368:
369: z80pc = GetPC(); /* for some of the platforms */
370:
371: while ( mr->lowIoAddr != 0xffff ) {
372: if (bPort >= mr->lowIoAddr && bPort <= mr->highIoAddr) {
373: mr->IOCall ( bPort, bVal, mr );
374: return;
375: }
376: mr++;
377: }
378:
379: }
380:
381: /* static */ void MemWriteWord ( UINT16 wAddr, UINT16 wVal ) {
382: MemWriteByte ( wAddr++, LOBYTE ( wVal ) );
383: MemWriteByte ( wAddr, HIBYTE ( wVal ) );
384: }
385:
386: /* static */ /* inline */ void MemWriteByte ( UINT16 wAddr, UINT8 bVal ) {
387: mz80PutMemory ( wAddr, bVal );
388: }
389:
390: /* static */ /* inline */ UINT8 MemReadByte ( UINT16 wAddr ) {
391: return ( mz80GetMemory ( wAddr ) );
392: }
393:
394: /* static */ /* inline */ UINT16 MemReadWord ( UINT16 wAddr ) {
395: UINT8 op1;
396: UINT8 op2;
397:
398: op1 = MemReadByte(wAddr ++);
399: op2 = MemReadByte(wAddr);
400: return ( MAKEWORD ( op1, op2 ) );
401: }
402:
403: /* ***************************************************************************
404: * Retrocade guts stuff (again) (these guys are defined after macros)
405: * ***************************************************************************
406: */
407:
408: unsigned long int mz80GetContextSize(void) {
409: return ( sizeof ( CONTEXTMZ80 ) );
410: }
411:
412: /* set memory base, etc. */
413: void mz80GetContext ( void *receiver ) {
414: CONTEXTMZ80 *c = receiver;
415: c -> z80MemRead = z80MemoryRead;
416: c -> z80MemWrite = z80MemoryWrite;
417: c -> z80Base = (UINT8 *) m_rgbOpcodeBase;
418: c -> z80IoRead = z80IoRead;
419: c -> z80IoWrite = z80IoWrite;
420: c -> z80af = m_regAF;
421: c -> z80bc = m_regBC;
422: c -> z80de = m_regDE;
423: c -> z80hl = m_regHL;
424: c -> z80afprime = m_regAF2;
425: c -> z80bcprime = m_regBC2;
426: c -> z80deprime = m_regDE2;
427: c -> z80hlprime = m_regHL2;
428: c -> z80ix = m_regIX;
429: c -> z80iy = m_regIY;
430: c -> z80sp = GetSP();
431: c -> z80pc = GetPC();
432: c -> z80i = m_regI;
433: c -> z80r = m_regR;
434: c -> z80intAddr = z80intAddr;
435: c -> z80nmiAddr = z80nmiAddr;
436: c -> z80inInterrupt = m_iff1;
437: c -> z80interruptMode = m_nIM;
438: c -> z80interruptState = m_iff2;
439: c -> z80halted = m_fHalt;
440:
441: #if 0
442: fprintf ( stderr, "GetContext\n" );
443: #endif
444: }
445:
446: void mz80SetContext( void *sender ) {
447: CONTEXTMZ80 *c = sender;
448: z80MemoryRead = c -> z80MemRead;
449: z80MemoryWrite = c -> z80MemWrite;
450: m_rgbMemory = c -> z80Base;
451: z80IoRead = c -> z80IoRead;
452: z80IoWrite = c -> z80IoWrite;
453: m_regAF = c -> z80af;
454: m_regBC = c -> z80bc;
455: m_regDE = c -> z80de;
456: m_regHL = c -> z80hl;
457: m_regAF2 = c -> z80afprime;
458: m_regBC2 = c -> z80bcprime;
459: m_regDE2 = c -> z80deprime;
460: m_regHL2 = c -> z80hlprime;
461: m_regIX = c -> z80ix;
462: m_regIY = c -> z80iy;
463: m_regI = c -> z80i;
464: m_regR = c -> z80r;
465: z80intAddr = c -> z80intAddr;
466: z80nmiAddr = c -> z80nmiAddr;
467: m_rgbOpcodeBase = m_rgbMemory;
468:
469: m_iff1 = c->z80inInterrupt;
470: m_iff2 = c->z80interruptState;
471: m_nIM = c->z80interruptMode;
472: m_fHalt = c->z80halted;
473:
474: SetPC ( c -> z80pc );
475: SetSP ( c -> z80sp );
476:
477: #if 0
478: fprintf ( stderr, "SetContext\n" );
479: #endif
480: }
481:
482: /* ***************************************************************************
483: * Z80 Please-inline-my-ass opcodes
484: * ***************************************************************************
485: */
486:
487: /* inline */ int Ret0(int f)
488: {
489: if (f)
490: {
491: SetPC(Pop());
492: return 6;
493: }
494: else
495: {
496: return 0;
497: }
498: }
499:
500: /* inline */ int Ret1(int f)
501: {
502: if (f)
503: {
504: return 0;
505: }
506: else
507: {
508: SetPC(Pop());
509: return 6;
510: }
511: }
512:
513: /* inline */ WORD Adc_2 (WORD wArg1, WORD wArg2)
514: {
515: #ifdef ARITH_TABLES
516: int q = wArg1 + wArg2 + (m_regF & C_FLAG);
517: m_regF = (((wArg1^q^wArg2)&0x1000)>>8)|((q>>16)&1)|((q&0x8000)>>8)|((q&65535)?0:Z_FLAG)|(((wArg2^wArg1^0x8000)&(wArg2^q)&0x8000)>>13);
518: return q;
519: #else
520: int q = wArg1 + wArg2 + (m_regF & C_FLAG);
521: m_regF = (((wArg1^q^wArg2)&0x1000)>>8)|((q>>16)&1)|((q&0x8000)>>8)|((q&65535)?0:Z_FLAG)|(((wArg2^wArg1^0x8000)&(wArg2^q)&0x8000)>>13);
522: return q;
523: #endif
524: }
525:
526: /* inline */ WORD Sbc_2 (WORD wArg1, WORD wArg2)
527: {
528: #ifdef ARITH_TABLES
529: int q = wArg1 - wArg2 - (m_regF & C_FLAG);
530:
531: m_regF = (((wArg1^q^wArg2)&0x1000)>>8)|((q>>16)&1)|((q&0x8000)>>8)|
532: ((q&65535)?0:Z_FLAG)|(((wArg1^wArg2)&(wArg1^q)&0x8000)>>13)|N_FLAG;
533:
534: return q;
535: #else
536: int q = wArg1 - wArg2 - (m_regF & C_FLAG);
537:
538: m_regF = (((wArg1^q^wArg2)&0x1000)>>8)|((q>>16)&1)|((q&0x8000)>>8)|
539: ((q&65535)?0:Z_FLAG)|(((wArg1^wArg2)&(wArg1^q)&0x8000)>>13)|N_FLAG;
540:
541: return q;
542: #endif
543: }
544:
545: /* inline */ WORD Add_2 (WORD wArg1, WORD wArg2)
546: {
547: #ifdef ARITH_TABLES
548: int q = wArg1 + wArg2;
549: m_regF = (m_regF&(S_FLAG|Z_FLAG|V_FLAG))|(((wArg1^q^wArg2)&0x1000)>>8)|((q>>16)&1);
550: return q;
551: #else
552: int q = wArg1 + wArg2;
553: m_regF = (m_regF&(S_FLAG|Z_FLAG|V_FLAG))|(((wArg1^q^wArg2)&0x1000)>>8)|((q>>16)&1);
554: return q;
555: #endif
556: }
557:
558: /* inline */ void Add_1 (BYTE bArg)
559: {
560: #ifdef ARITH_TABLES
561: int q = m_regA + bArg;
562: m_regF = rgfAdd[m_regA][bArg];
563: m_regA = q;
564: #else
565: int q = m_regA + bArg;
566: m_regF=ZSTable[q&255]|((q&256)>>8)| ((m_regA^q^bArg)&H_FLAG)| (((bArg^m_regA^0x80)&(bArg^q)&0x80)>>5);
567: m_regA=q;
568: #endif
569: }
570:
571: /* inline */ void Adc_1 (BYTE bArg)
572: {
573: #ifdef ARITH_TABLES
574: int q = m_regA + bArg + (m_regF & C_FLAG);
575: m_regF = rgfAddc[m_regA][bArg][m_regF & C_FLAG];
576: m_regA = q;
577: #else
578: int q = m_regA + bArg + (m_regF & C_FLAG);
579: m_regF = ZSTable[q & 255]|((q & 256)>>8)|((m_regA^q^bArg)&H_FLAG)|(((bArg^m_regA^0x80)&(bArg^q)&0x80)>>5);
580: m_regA = q;
581: #endif
582: }
583:
584: /* inline */ void Sub_1 (BYTE bArg)
585: {
586: #ifdef ARITH_TABLES
587: int q = m_regA - bArg;
588: m_regF = rgfSub[m_regA][bArg];
589: m_regA = q;
590: #else
591: int q = m_regA - bArg;
592: m_regF = ZSTable[q&255]|((q&256)>>8)|N_FLAG|((m_regA^q^bArg)&H_FLAG)|(((bArg^m_regA)&(m_regA^q)&0x80)>>5);
593: m_regA = q;
594: #endif
595: }
596:
597: /* inline */ void Sbc_1 (BYTE bArg)
598: {
599: #ifdef ARITH_TABLES
600: int q = m_regA - bArg - (m_regF & C_FLAG);
601: m_regF = rgfSubc[m_regA][bArg][m_regF & C_FLAG];
602: m_regA = q;
603: #else
604: int q = m_regA - bArg - (m_regF & C_FLAG);
605: m_regF=ZSTable[q&255]|((q&256)>>8)|N_FLAG|((m_regA^q^bArg)&H_FLAG)|(((bArg^m_regA)&(bArg^q)&0x80)>>5);
606: m_regA=q;
607: #endif
608: }
609:
610: /* inline */ void And (BYTE bArg)
611: {
612: m_regF = ZSPTable[m_regA &= bArg] | H_FLAG;
613: }
614:
615: /* inline */ void Or(BYTE bArg)
616: {
617: m_regF = ZSPTable[m_regA |= bArg];
618: }
619:
620: /* inline */ void Xor(BYTE bArg)
621: {
622: m_regF = ZSPTable[m_regA ^= bArg];
623: }
624:
625: /* inline */ void Cp(BYTE bArg)
626: {
627: #ifdef ARITH_TABLES
628: int q = m_regA - bArg;
629: m_regF = rgfSub[m_regA][bArg];
630: #else
631: int q = m_regA - bArg;
632: m_regF = ZSTable[q&255]|((q&256)>>8)|N_FLAG|((m_regA^q^bArg)&H_FLAG)|(((bArg^m_regA)&(bArg^q)&0x80)>>5);
633: #endif
634: }
635:
636: /* inline */ static BYTE Inc(BYTE bArg)
637: {
638: #ifdef ARITH_TABLES
639: bArg++;
640: m_regF = (m_regF & C_FLAG) | rgfInc[bArg];
641: return bArg;
642: #else
643: bArg++;
644: m_regF = (m_regF&C_FLAG)|ZSTable[bArg]|((bArg==0x80)?V_FLAG:0)|((bArg&0x0F)?0:H_FLAG);
645: return bArg;
646: #endif
647: }
648:
649: /* inline */ static BYTE Dec(BYTE bArg)
650: {
651: #ifdef ARITH_TABLES
652: m_regF = (m_regF & C_FLAG) | rgfDec[bArg--];
653: return bArg;
654: #else
655: m_regF=(m_regF&C_FLAG)|N_FLAG|
656: ((bArg==0x80)?V_FLAG:0)|((bArg&0x0F)?0:H_FLAG);
657:
658: m_regF|=ZSTable[--bArg];
659:
660: return bArg;
661: #endif
662: }
663:
664: // shouldn't even be members...
665:
666: /* inline */ BYTE Set(BYTE bArg, int nBit)
667: {
668: return (bArg | (1 << nBit));
669: }
670:
671: /* inline */ BYTE Res(BYTE bArg, int nBit)
672: {
673: return (bArg & ~(1 << nBit));
674: }
675:
676: /* inline */ void Bit(BYTE bArg, int nBit)
677: {
678: #ifdef ARITH_TABLES
679: m_regF = (m_regF & C_FLAG) | rgfBit[bArg][nBit];
680: #else
681: m_regF = (m_regF & C_FLAG) | H_FLAG | ((bArg&(1<< nBit))? ((nBit==7)?S_FLAG:0):Z_FLAG);
682: #endif
683: }
684:
685: /* inline */ BYTE Rlc(BYTE bArg)
686: {
687: int q = bArg >> 7;
688: bArg = (bArg << 1) | q;
689: m_regF = ZSPTable[bArg] | q;
690: return bArg;
691: }
692:
693: /* inline */ BYTE Rrc(BYTE bArg)
694: {
695: int q = bArg & 1;
696: bArg = (bArg >> 1) | (q << 7);
697: m_regF = ZSPTable[bArg]|q;
698: return bArg;
699: }
700:
701: /* inline */ BYTE Rl(BYTE bArg)
702: {
703: int q=bArg>>7;
704: bArg=(bArg<<1)|(m_regF&1);
705: m_regF=ZSPTable[bArg]|q;
706: return bArg;
707: }
708:
709: /* inline */ BYTE Rr(BYTE bArg)
710: {
711: int q = bArg&1;
712: bArg=(bArg>>1)|(m_regF<<7);
713: m_regF=ZSPTable[bArg]|q;
714: return bArg;
715: }
716:
717: /* inline */ BYTE Sll(BYTE bArg)
718: {
719: int q = bArg>>7;
720: bArg=(bArg<<1)|1;
721: m_regF=ZSPTable[bArg]|q;
722: return bArg;
723: }
724:
725: /* inline */ BYTE Srl(BYTE bArg)
726: {
727: int q = bArg&1;
728: bArg>>=1;
729: m_regF=ZSPTable[bArg]|q;
730: return bArg;
731: }
732:
733: /* inline */ BYTE Sla(BYTE bArg)
734: {
735: int q = bArg>>7;
736: bArg<<=1;
737: m_regF=ZSPTable[bArg]|q;
738: return bArg;
739: }
740:
741: /* inline */ BYTE Sra(BYTE bArg)
742: {
743: int q = bArg&1;
744: bArg = (bArg>>1)|(bArg&0x80);
745: m_regF = ZSPTable[bArg]|q;
746: return bArg;
747: }
748:
749: /* ***************************************************************************
750: * Edwards Z80 Utilities
751: * ***************************************************************************
752: */
753:
754: UINT16 swap_variable;
755: #define swap(b1,b2) swap_variable = b1; b1 = b2; b2 = swap_variable;
756: /* inline void swap ( WORD &b1, WORD &b2 ) {
757: * WORD b = b1;
758: * b1 = b2;
759: * b2 = b;
760: * }
761: */
762:
763: /* inline */ void Rlca() {
764: m_regA = (m_regA << 1) | ((m_regA & 0x80) >> 7);
765: m_regF = (m_regF & 0xEC) | (m_regA & C_FLAG);
766: }
767:
768: /* inline */ void Rrca() {
769: m_regF=(m_regF&0xEC)|(m_regA&0x01);
770: m_regA=(m_regA>>1)|(m_regA<<7);
771: }
772:
773: /* inline */ void Rla() {
774: int i = m_regF&C_FLAG;
775: m_regF = (m_regF&0xEC)|((m_regA&0x80)>>7);
776: m_regA = (m_regA<<1)|i;
777: }
778:
779: /* inline */ void Rra() {
780: int i = m_regF&C_FLAG;
781: m_regF=(m_regF&0xEC)|(m_regA&0x01);
782: m_regA=(m_regA>>1)|(i<<7);
783: }
784:
785: /* ***************************************************************************
786: * Edwards Z80 Good-bits follow
787: * ***************************************************************************
788: */
789:
790: void InitTables (void) {
791: int i;
792: DWORD dw;
793:
794: //
795: //
796: //
797:
798: for (i=0; i<256; ++i)
799: {
800: BYTE zs = 0;
801: int p=0;
802: BYTE bArg;
803: int j;
804:
805: // zs |= i ? 0 : Z_FLAG;
806: if (i==0)
807: zs|=Z_FLAG;
808:
809: // zs |= i & S_FLAG;
810: if (i&0x80)
811: zs|=S_FLAG;
812:
813: if (i&1) ++p;
814: if (i&2) ++p;
815: if (i&4) ++p;
816: if (i&8) ++p;
817: if (i&16) ++p;
818: if (i&32) ++p;
819: if (i&64) ++p;
820: if (i&128) ++p;
821:
822: // PTable[i] = (p&1) ? 0:V_FLAG;
823: ZSTable[i] = zs;
824: ZSPTable[i]= zs | ((p&1) ? 0:V_FLAG);
825:
826: rgfInc[i] = ZSTable[i] | ((i == 0x80) ? V_FLAG : 0) | ((i & 0x0F) ? 0 : H_FLAG);
827:
828: // rgfDec[i] = N_FLAG | ((i == 0x80) ? V_FLAG : 0) | ((i & 0x0F) ? 0 : H_FLAG) | ZSTable[(BYTE)i - 1];
829:
830: bArg = i;
831: rgfDec[i] = N_FLAG|((bArg==0x80)?V_FLAG:0)|((bArg&0x0F)?0:H_FLAG);
832: rgfDec[i]|=ZSTable[--bArg];
833:
834: for ( j = 0; j < 8; j++)
835: rgfBit[i][j] = H_FLAG | ((i & (1 << j))? ((j == 7) ? S_FLAG : 0) : Z_FLAG);
836: }
837:
838: //
839: // Calculate flag tables
840: //
841:
842: for ( dw = 0; dw <= 256 * 256; dw++)
843: {
844: BYTE bLo = LOBYTE(LOWORD(dw));
845: BYTE bHi = HIBYTE(LOWORD(dw));
846:
847: const BYTE regA = bLo;
848: const BYTE bArg = bHi;
849:
850: int nAcc;
851: BYTE regF;
852: int c;
853:
854: //
855: // ADD
856: //
857:
858: nAcc = regA + bArg;
859: regF = 0;
860:
861: regF |= ZSTable[nAcc&255];
862: regF |= ((nAcc&256)>>8);
863: regF |= ((regA^nAcc^bArg)&H_FLAG);
864: regF |= (((bArg^regA^0x80)&(bArg^nAcc)&0x80)>>5);
865:
866: rgfAdd[regA][bArg] = regF;
867:
868: //
869: // SUB
870: //
871:
872: nAcc = regA - bArg;
873: regF = ZSTable[nAcc&255]|((nAcc&256)>>8)|N_FLAG|((regA^nAcc^bArg)&H_FLAG)|(((bArg^regA)&(regA^nAcc)&0x80)>>5);
874:
875: rgfSub[regA][bArg] = regF;
876:
877: //
878: //
879: //
880:
881: for ( c = 0; c <= 1; c++)
882: {
883: //
884: // ADC
885: //
886:
887: nAcc = regA + bArg + c;
888: regF = 0;
889:
890: regF |= ZSTable[nAcc&255];
891: regF |= ((nAcc&256)>>8);
892: regF |= ((regA^nAcc^bArg)&H_FLAG);
893: regF |= (((bArg^regA^0x80)&(bArg^nAcc)&0x80)>>5);
894:
895: rgfAddc[regA][bArg][c] = regF;
896:
897: //
898: // SBC
899: //
900:
901: nAcc = regA - bArg - c;
902: regF = ZSTable[nAcc&255]|((nAcc&256)>>8)|N_FLAG|((regA^nAcc^bArg)&H_FLAG)|(((bArg^regA)&(bArg^nAcc)&0x80)>>5);
903:
904: rgfSubc[regA][bArg][c] = regF;
905: }
906: }
907: }
908:
909: /* ***************************************************************************
910: * Opcodes
911: * ***************************************************************************
912: */
913:
914: /*---------------------------------------------------------------------------
915:
916: Exec
917:
918: Executes the specified number of t-states. Returns the actual number of
919: t-states executed. If a halt instruction is encountered, the execution
920: loop exits. If the processor is currently in a halted state this
921: function immediately returns 0.
922:
923: ---------------------------------------------------------------------------*/
924:
925: unsigned long int mz80exec ( unsigned long int cCyclesArg ) {
926: UINT32 origElapsedTicks=dwElapsedTicks;
927: //
928: //
929: //
930:
931: // if (m_fHalt)
932: // return 0;
933:
934: //
935: // Save t-state count for return value calculation
936: //
937:
938: cCycles = cCyclesArg;
939:
940: //
941: //
942: //
943:
944:
945: #ifndef TRACE_Z80
946: while (cCycles > 0)
947: #endif
948: {
949: #ifdef _DEBUG
950: static int cins;
951:
952: if ((cins % 1000) == 0 && GetAsyncKeyState('X') < 0)
953: _ASSERT(FALSE);
954:
955: _ASSERT(cins != _instrap);
956:
957: if (cins >= _rgcins[0] && cins <= _rgcins[0] + _rgcins[1] * _rgcins[2] && ((cins - _rgcins[0]) % _rgcins[2]) == 0)
958: {
959: if (cins == _rgcins[0])
960: {
961: TRACE("instr PC AF BC DE HL IX IY SP cycl dasm \n");
962: TRACE("-------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ------------\n");
963: }
964:
965: TCHAR szBuf[128];
966:
967: Z80_Dasm(&m_rgbMemory[GetPC()], szBuf, GetPC());
968:
969: TRACE("%08X %04X %04X %04X %04X %04X %04X %04X %04X %04X %s\n",
970: cins, GetPC(), m_regAF, m_regBC, m_regDE, m_regHL, m_regIX, m_regIY, GetSP(), cCycles, szBuf);
971: }
972:
973: cins++;
974: #endif
975: const BYTE bOpcode = ImmedByte();
976:
977: #ifdef _DEBUG
978: m_rgcOpcode[0][bOpcode]++;
979: #endif
980:
981: m_regR++;
982:
983: #if 0
984: /* debug crap for RC */
985: {
986: char szBuf [ 128 ];
987: Z80_Dasm(&m_rgbMemory[GetPC()], szBuf, GetPC());
988:
989: fprintf ( stderr,
990: "%04X %04X %04X %04X %04X %04X %04X %04X %04X %s\n",
991: GetPC(), m_regAF, m_regBC, m_regDE, m_regHL,
992: m_regIX, m_regIY, GetSP(), cCycles, szBuf );
993: }
994:
995: // fprintf ( stderr, "%d\n", bOpcode );
996: #endif
997: z80pc = GetPC(); /* for some of the platforms */
998:
999: dwElapsedTicks = origElapsedTicks + (cCyclesArg - cCycles);
1000:
1001: switch (bOpcode)
1002: {
1003: case 0x00: // nop
1004: cCycles -= 4;
1005: break;
1006:
1007: case 0x01: // ld_bc_word
1008: cCycles -= 10;
1009: m_regBC = ImmedWord();
1010: break;
1011:
1012: case 0x02: // ld_xbc_a
1013: cCycles -= 7;
1014: MemWriteByte(m_regBC, m_regA);
1015: break;
1016:
1017: case 0x03: // inc_bc
1018: cCycles -= 6;
1019: m_regBC++;
1020: break;
1021:
1022: case 0x04: // inc_b
1023: cCycles -= 4;
1024: m_regB = Inc(m_regB);
1025: break;
1026:
1027: case 0x05: // dec_b
1028: cCycles -= 4;
1029: m_regB = Dec(m_regB);
1030: break;
1031:
1032: case 0x06: // ld_b_byte
1033: cCycles -= 7;
1034: m_regB = ImmedByte();
1035: break;
1036:
1037: case 0x07: // rlca
1038: cCycles -= 4;
1039: Rlca();
1040: break;
1041:
1042: case 0x08: // ex_af_af
1043: cCycles -= 4;
1044: swap(m_regAF, m_regAF2);
1045: break;
1046:
1047: case 0x09: // add_hl_bc
1048: cCycles -= 11;
1049: m_regHL = Add_2(m_regHL, m_regBC);
1050: break;
1051:
1052: case 0x0A: // ld_a_xbc
1053: cCycles -= 7;
1054: m_regA = MemReadByte(m_regBC);
1055: break;
1056:
1057: case 0x0B: // dec_bc
1058: cCycles -= 6;
1059: m_regBC--;
1060: break;
1061:
1062: case 0x0C: // inc_c
1063: cCycles -= 4;
1064: m_regC = Inc(m_regC);
1065: break;
1066:
1067: case 0x0D: // dec_c
1068: cCycles -= 4;
1069: m_regC = Dec(m_regC);
1070: break;
1071:
1072: case 0x0E: // ld_c_byte
1073: cCycles -= 7;
1074: m_regC = ImmedByte();
1075: break;
1076:
1077: case 0x0F: // rrca
1078: cCycles -= 4;
1079: Rrca();
1080: break;
1081:
1082: case 0x10: // djnz
1083: cCycles -= 8;
1084: cCycles -= Jr0(--m_regB);
1085: break;
1086:
1087: case 0x11: // ld_de_word
1088: cCycles -= 10;
1089: m_regDE = ImmedWord();
1090: break;
1091:
1092: case 0x12: // ld_xde_a
1093: cCycles -= 7;
1094: MemWriteByte(m_regDE, m_regA);
1095: break;
1096:
1097: case 0x13: // inc_de
1098: cCycles -= 6;
1099: m_regDE++;
1100: break;
1101:
1102: case 0x14: // inc_d
1103: cCycles -= 4;
1104: m_regD = Inc(m_regD);
1105: break;
1106:
1107: case 0x15: // dec_d
1108: cCycles -= 4;
1109: m_regD = Dec(m_regD);
1110: break;
1111:
1112: case 0x16: // ld_d_byte
1113: cCycles -= 7;
1114: m_regD = ImmedByte();
1115: break;
1116:
1117: case 0x17: // rla
1118: cCycles -= 4;
1119: Rla();
1120: break;
1121:
1122: case 0x18: // jr
1123: {
1124: #if 0
1125: cCycles -= Jr0(TRUE);
1126: #else
1127: // speedup technique adopted from Nicola's code in MAME to speedup
1128: // Galaga (the sound CPU spins with "loop: jr loop" waiting for
1129: // an interrupt). This technique is generic enough that is shouldn't
1130: // adversely effect other applications.
1131:
1132: signed char offset = (signed char)ImmedByte();
1133: cCycles -= 7;
1134: cCycles -= 5;
1135:
1136: AdjustPC(offset);
1137:
1138: if (offset == -2)
1139: {
1140: // TRACE(__FILE__ ":jr (infinite loop) at %04X\n", GetPC());
1141: goto z80ExecBottom;
1142: /* return (cCyclesArg - cCycles); */
1143: }
1144: #endif
1145: break;
1146: }
1147:
1148: case 0x19: // add_hl_de
1149: cCycles -= 11;
1150: m_regHL = Add_2(m_regHL, m_regDE);
1151: break;
1152:
1153: case 0x1A: // ld_a_xde
1154: cCycles -= 7;
1155: m_regA = MemReadByte(m_regDE);
1156: break;
1157:
1158: case 0x1B: // dec_de
1159: cCycles -= 6;
1160: m_regDE--;
1161: break;
1162:
1163: case 0x1C: // inc_e
1164: cCycles -= 4;
1165: m_regE = Inc(m_regE);
1166: break;
1167:
1168: case 0x1D: // dec_e
1169: cCycles -= 4;
1170: m_regE = Dec(m_regE);
1171: break;
1172:
1173: case 0x1E: // ld_e_byte
1174: cCycles -= 7;
1175: m_regE = ImmedByte();
1176: break;
1177:
1178: case 0x1F: // rra
1179: cCycles -= 4;
1180: Rra();
1181: break;
1182:
1183: case 0x20: // jr_nz
1184: cCycles -= 7;
1185: cCycles -= Jr1(m_regF & Z_FLAG);
1186: break;
1187:
1188: case 0x21: // ld_hl_word
1189: cCycles -= 10;
1190: m_regHL = ImmedWord();
1191: break;
1192:
1193: case 0x22: // ld_xword_hl
1194: cCycles -= 16;
1195: MemWriteWord(ImmedWord(), m_regHL);
1196: break;
1197:
1198: case 0x23: // inc_hl
1199: cCycles -= 6;
1200: m_regHL++;
1201: break;
1202:
1203: case 0x24: // inc_h
1204: cCycles -= 4;
1205: m_regH = Inc(m_regH);
1206: break;
1207:
1208: case 0x25: // dec_h
1209: cCycles -= 4;
1210: m_regH = Dec(m_regH);
1211: break;
1212:
1213: case 0x26: // ld_h_byte
1214: cCycles -= 7;
1215: m_regH = ImmedByte();
1216: break;
1217:
1218: case 0x27: // daa
1219: {
1220: int i = m_regA;
1221: cCycles -= 4;
1222: if (m_regF&C_FLAG) i|=256;
1223: if (m_regF&H_FLAG) i|=512;
1224: if (m_regF&N_FLAG) i|=1024;
1225: m_regAF = DAATable[i];
1226: break;
1227: }
1228:
1229: case 0x28: // jr_z
1230: cCycles -= 7;
1231: cCycles -= Jr0(m_regF & Z_FLAG);
1232: break;
1233:
1234: case 0x29: // add_hl_hl
1235: cCycles -= 11;
1236: m_regHL = Add_2(m_regHL, m_regHL);
1237: break;
1238:
1239: case 0x2A: // ld_hl_xword
1240: cCycles -= 16;
1241: m_regHL = MemReadWord(ImmedWord());
1242: break;
1243:
1244: case 0x2B: // dec_hl
1245: cCycles -= 6;
1246: m_regHL--;
1247: break;
1248:
1249: case 0x2C: // inc_l
1250: cCycles -= 4;
1251: m_regL = Inc(m_regL);
1252: break;
1253:
1254: case 0x2D: // dec_l
1255: cCycles -= 4;
1256: m_regL = Dec(m_regL);
1257: break;
1258:
1259: case 0x2E: // ld_l_byte
1260: cCycles -= 7;
1261: m_regL = ImmedByte();
1262: break;
1263:
1264: case 0x2F: // cpl
1265: cCycles -= 4;
1266: m_regA ^= 0xFF;
1267: m_regF |= (H_FLAG | N_FLAG);
1268: break;
1269:
1270: case 0x30: // jr_nc
1271: cCycles -= 7;
1272: cCycles -= Jr1(m_regF & C_FLAG);
1273: break;
1274:
1275: case 0x31: // ld_sp_word
1276: cCycles -= 10;
1277: SetSP(ImmedWord());
1278: break;
1279:
1280: case 0x32: // ld_xbyte_a
1281: cCycles -= 13;
1282: MemWriteByte(ImmedWord(), m_regA);
1283: break;
1284:
1285: case 0x33: // inc_sp
1286: cCycles -= 6;
1287: SetSP(GetSP() + 1);
1288: break;
1289:
1290: case 0x34: // inc_xhl
1291: cCycles -= 11;
1292: MemWriteByte(m_regHL, Inc(MemReadByte(m_regHL)));
1293: break;
1294:
1295: case 0x35: // dec_xhl
1296: cCycles -= 11;
1297: MemWriteByte(m_regHL, Dec(MemReadByte(m_regHL)));
1298: break;
1299:
1300: case 0x36: // ld_xhl_byte
1301: cCycles -= 10;
1302: MemWriteByte(m_regHL, ImmedByte());
1303: break;
1304:
1305: case 0x37: // scf
1306: cCycles -= 4;
1307: m_regF = (m_regF & 0xEC) | C_FLAG;
1308: break;
1309:
1310: case 0x38: // jr_c
1311: cCycles -= 7;
1312: cCycles -= Jr0(m_regF & C_FLAG);
1313: break;
1314:
1315: case 0x39: // add_hl_sp
1316: cCycles -= 11;
1317: m_regHL = Add_2(m_regHL, GetSP());
1318: break;
1319:
1320: case 0x3A: // ld_a_xbyte
1321: cCycles -= 13;
1322: m_regA = MemReadByte(ImmedWord());
1323: break;
1324:
1325: case 0x3B: // dec_sp
1326: cCycles -= 6;
1327: SetSP(GetSP() - 1);
1328: break;
1329:
1330: case 0x3C: // inc_a
1331: cCycles -= 4;
1332: m_regA = Inc(m_regA);
1333: break;
1334:
1335: case 0x3D: // dec_a
1336: cCycles -= 4;
1337: m_regA = Dec(m_regA);
1338: break;
1339:
1340: case 0x3E: // ld_a_byte
1341: cCycles -= 7;
1342: m_regA = ImmedByte();
1343: break;
1344:
1345: case 0x3F: // ccf
1346: cCycles -= 4;
1347: m_regF =((m_regF & 0xED)|((m_regF & 1)<<4))^1;
1348: break;
1349:
1350: case 0x40: // ld_b_b
1351: cCycles -= 4;
1352: m_regB = m_regB;
1353: break;
1354:
1355: case 0x41: // ld_b_c
1356: cCycles -= 4;
1357: m_regB = m_regC;
1358: break;
1359:
1360: case 0x42: // ld_b_d
1361: cCycles -= 4;
1362: m_regB = m_regD;
1363: break;
1364:
1365: case 0x43: // ld_b_e
1366: cCycles -= 4;
1367: m_regB = m_regE;
1368: break;
1369:
1370: case 0x44: // ld_b_h
1371: cCycles -= 4;
1372: m_regB = m_regH;
1373: break;
1374:
1375: case 0x45: // ld_b_l
1376: cCycles -= 4;
1377: m_regB = m_regL;
1378: break;
1379:
1380: case 0x46: // ld_b_xhl
1381: cCycles -= 7;
1382: m_regB = MemReadByte(m_regHL);
1383: break;
1384:
1385: case 0x47: // ld_b_a
1386: cCycles -= 4;
1387: m_regB = m_regA;
1388: break;
1389:
1390: case 0x48: // ld_c_b
1391: cCycles -= 4;
1392: m_regC = m_regB;
1393: break;
1394:
1395: case 0x49: // ld_c_c
1396: cCycles -= 4;
1397: m_regC = m_regC;
1398: break;
1399:
1400: case 0x4A: // ld_c_d
1401: cCycles -= 4;
1402: m_regC = m_regD;
1403: break;
1404:
1405: case 0x4B: // ld_c_e
1406: cCycles -= 4;
1407: m_regC = m_regE;
1408: break;
1409:
1410: case 0x4C: // ld_c_h
1411: cCycles -= 4;
1412: m_regC = m_regH;
1413: break;
1414:
1415: case 0x4D: // ld_c_l
1416: cCycles -= 4;
1417: m_regC = m_regL;
1418: break;
1419:
1420: case 0x4E: // ld_c_xhl
1421: cCycles -= 7;
1422: m_regC = MemReadByte(m_regHL);
1423: break;
1424:
1425: case 0x4F: // ld_c_a
1426: cCycles -= 4;
1427: m_regC = m_regA;
1428: break;
1429:
1430: case 0x50: // ld_d_b
1431: cCycles -= 4;
1432: m_regD = m_regB;
1433: break;
1434:
1435: case 0x51: // ld_d_c
1436: cCycles -= 4;
1437: m_regD = m_regC;
1438: break;
1439:
1440: case 0x52: // ld_d_d
1441: cCycles -= 4;
1442: m_regD = m_regD;
1443: break;
1444:
1445: case 0x53: // ld_d_e
1446: cCycles -= 4;
1447: m_regD = m_regE;
1448: break;
1449:
1450: case 0x54: // ld_d_h
1451: cCycles -= 4;
1452: m_regD = m_regH;
1453: break;
1454:
1455: case 0x55: // ld_d_l
1456: cCycles -= 4;
1457: m_regD = m_regL;
1458: break;
1459:
1460: case 0x56: // ld_d_xhl
1461: cCycles -= 7;
1462: m_regD = MemReadByte(m_regHL);
1463: break;
1464:
1465: case 0x57: // ld_d_a
1466: cCycles -= 4;
1467: m_regD = m_regA;
1468: break;
1469:
1470: case 0x58: // ld_e_b
1471: cCycles -= 4;
1472: m_regE = m_regB;
1473: break;
1474:
1475: case 0x59: // ld_e_c
1476: cCycles -= 4;
1477: m_regE = m_regC;
1478: break;
1479:
1480: case 0x5A: // ld_e_d
1481: cCycles -= 4;
1482: m_regE = m_regD;
1483: break;
1484:
1485: case 0x5B: // ld_e_e
1486: cCycles -= 4;
1487: m_regE = m_regE;
1488: break;
1489:
1490: case 0x5C: // ld_e_h
1491: cCycles -= 4;
1492: m_regE = m_regH;
1493: break;
1494:
1495: case 0x5D: // ld_e_l
1496: cCycles -= 4;
1497: m_regE = m_regL;
1498: break;
1499:
1500: case 0x5E: // ld_e_xhl
1501: cCycles -= 7;
1502: m_regE = MemReadByte(m_regHL);
1503: break;
1504:
1505: case 0x5F: // ld_e_a
1506: cCycles -= 4;
1507: m_regE = m_regA;
1508: break;
1509:
1510: case 0x60: // ld_h_b
1511: cCycles -= 4;
1512: m_regH = m_regB;
1513: break;
1514:
1515: case 0x61: // ld_h_c
1516: cCycles -= 4;
1517: m_regH = m_regC;
1518: break;
1519:
1520: case 0x62: // ld_h_d
1521: cCycles -= 4;
1522: m_regH = m_regD;
1523: break;
1524:
1525: case 0x63: // ld_h_e
1526: cCycles -= 4;
1527: m_regH = m_regE;
1528: break;
1529:
1530: case 0x64: // ld_h_h
1531: cCycles -= 4;
1532: m_regH = m_regH;
1533: break;
1534:
1535: case 0x65: // ld_h_l
1536: cCycles -= 4;
1537: m_regH = m_regL;
1538: break;
1539:
1540: case 0x66: // ld_h_xhl
1541: cCycles -= 7;
1542: m_regH = MemReadByte(m_regHL);
1543: break;
1544:
1545: case 0x67: // ld_h_a
1546: cCycles -= 4;
1547: m_regH = m_regA;
1548: break;
1549:
1550: case 0x68: // ld_l_b
1551: cCycles -= 4;
1552: m_regL = m_regB;
1553: break;
1554:
1555: case 0x69: // ld_l_c
1556: cCycles -= 4;
1557: m_regL = m_regC;
1558: break;
1559:
1560: case 0x6A: // ld_l_d
1561: cCycles -= 4;
1562: m_regL = m_regD;
1563: break;
1564:
1565: case 0x6B: // ld_l_e
1566: cCycles -= 4;
1567: m_regL = m_regE;
1568: break;
1569:
1570: case 0x6C: // ld_l_h
1571: cCycles -= 4;
1572: m_regL = m_regH;
1573: break;
1574:
1575: case 0x6D: // ld_l_l
1576: cCycles -= 4;
1577: m_regL = m_regL;
1578: break;
1579:
1580: case 0x6E: // ld_l_xhl
1581: cCycles -= 7;
1582: m_regL = MemReadByte(m_regHL);
1583: break;
1584:
1585: case 0x6F: // ld_l_a
1586: cCycles -= 4;
1587: m_regL = m_regA;
1588: break;
1589:
1590: case 0x70: // ld_xhl_b
1591: cCycles -= 7;
1592: MemWriteByte(m_regHL, m_regB);
1593: break;
1594:
1595: case 0x71: // ld_xhl_c
1596: cCycles -= 7;
1597: MemWriteByte(m_regHL, m_regC);
1598: break;
1599:
1600: case 0x72: // ld_xhl_d
1601: cCycles -= 7;
1602: MemWriteByte(m_regHL, m_regD);
1603: break;
1604:
1605: case 0x73: // ld_xhl_e
1606: cCycles -= 7;
1607: MemWriteByte(m_regHL, m_regE);
1608: break;
1609:
1610: case 0x74: // ld_xhl_h
1611: cCycles -= 7;
1612: MemWriteByte(m_regHL, m_regH);
1613: break;
1614:
1615: case 0x75: // ld_xhl_l
1616: cCycles -= 7;
1617: MemWriteByte(m_regHL, m_regL);
1618: break;
1619:
1620: case 0x76: // halt
1621: cCycles -= 4;
1622: SetPC(GetPC() - 1);
1623: m_fHalt = TRUE;
1624: goto z80ExecBottom;
1625: /* return (cCyclesArg - cCycles); */
1626:
1627: case 0x77: // ld_xhl_a
1628: cCycles -= 7;
1629: MemWriteByte(m_regHL, m_regA);
1630: break;
1631:
1632: case 0x78: // ld_a_b
1633: cCycles -= 4;
1634: m_regA = m_regB;
1635: break;
1636:
1637: case 0x79: // ld_a_c
1638: cCycles -= 4;
1639: m_regA = m_regC;
1640: break;
1641:
1642: case 0x7A: // ld_a_d
1643: cCycles -= 4;
1644: m_regA = m_regD;
1645: break;
1646:
1647: case 0x7B: // ld_a_e
1648: cCycles -= 4;
1649: m_regA = m_regE;
1650: break;
1651:
1652: case 0x7C: // ld_a_h
1653: cCycles -= 4;
1654: m_regA = m_regH;
1655: break;
1656:
1657: case 0x7D: // ld_a_l
1658: cCycles -= 4;
1659: m_regA = m_regL;
1660: break;
1661:
1662: case 0x7E: // ld_a_xhl
1663: cCycles -= 7;
1664: m_regA = MemReadByte(m_regHL);
1665: break;
1666:
1667: case 0x7F: // ld_a_a
1668: cCycles -= 4;
1669: m_regA = m_regA;
1670: break;
1671:
1672: case 0x80: // add_a_b
1673: cCycles -= 4;
1674: Add_1(m_regB);
1675: break;
1676:
1677: case 0x81: // add_a_c
1678: cCycles -= 4;
1679: Add_1(m_regC);
1680: break;
1681:
1682: case 0x82: // add_a_d
1683: cCycles -= 4;
1684: Add_1(m_regD);
1685: break;
1686:
1687: case 0x83: // add_a_e
1688: cCycles -= 4;
1689: Add_1(m_regE);
1690: break;
1691:
1692: case 0x84: // add_a_h
1693: cCycles -= 4;
1694: Add_1(m_regH);
1695: break;
1696:
1697: case 0x85: // add_a_l
1698: cCycles -= 4;
1699: Add_1(m_regL);
1700: break;
1701:
1702: case 0x86: // add_a_xhl
1703: cCycles -= 7;
1704: Add_1(MemReadByte(m_regHL));
1705: break;
1706:
1707: case 0x87: // add_a_a
1708: cCycles -= 4;
1709: Add_1(m_regA);
1710: break;
1711:
1712: case 0x88: // adc_a_b
1713: cCycles -= 4;
1714: Adc_1(m_regB);
1715: break;
1716:
1717: case 0x89: // adc_a_c
1718: cCycles -= 4;
1719: Adc_1(m_regC);
1720: break;
1721:
1722: case 0x8A: // adc_a_d
1723: cCycles -= 4;
1724: Adc_1(m_regD);
1725: break;
1726:
1727: case 0x8B: // adc_a_e
1728: cCycles -= 4;
1729: Adc_1(m_regE);
1730: break;
1731:
1732: case 0x8C: // adc_a_h
1733: cCycles -= 4;
1734: Adc_1(m_regH);
1735: break;
1736:
1737: case 0x8D: // adc_a_l
1738: cCycles -= 4;
1739: Adc_1(m_regL);
1740: break;
1741:
1742: case 0x8E: // adc_a_xhl
1743: cCycles -= 7;
1744: Adc_1(MemReadByte(m_regHL));
1745: break;
1746:
1747: case 0x8F: // adc_a_a
1748: cCycles -= 4;
1749: Adc_1(m_regA);
1750: break;
1751:
1752: case 0x90: // sub_b
1753: cCycles -= 4;
1754: Sub_1(m_regB);
1755: break;
1756:
1757: case 0x91: // sub_c
1758: cCycles -= 4;
1759: Sub_1(m_regC);
1760: break;
1761:
1762: case 0x92: // sub_d
1763: cCycles -= 4;
1764: Sub_1(m_regD);
1765: break;
1766:
1767: case 0x93: // sub_e
1768: cCycles -= 4;
1769: Sub_1(m_regE);
1770: break;
1771:
1772: case 0x94: // sub_h
1773: cCycles -= 4;
1774: Sub_1(m_regH);
1775: break;
1776:
1777: case 0x95: // sub_l
1778: cCycles -= 4;
1779: Sub_1(m_regL);
1780: break;
1781:
1782: case 0x96: // sub_xhl
1783: cCycles -= 7;
1784: Sub_1(MemReadByte(m_regHL));
1785: break;
1786:
1787: case 0x97: // sub_a
1788: cCycles -= 4;
1789: Sub_1(m_regA);
1790: break;
1791:
1792: case 0x98: // sbc_a_b
1793: cCycles -= 4;
1794: Sbc_1(m_regB);
1795: break;
1796:
1797: case 0x99: // sbc_a_c
1798: cCycles -= 4;
1799: Sbc_1(m_regC);
1800: break;
1801:
1802: case 0x9A: // sbc_a_d
1803: cCycles -= 4;
1804: Sbc_1(m_regD);
1805: break;
1806:
1807: case 0x9B: // sbc_a_e
1808: cCycles -= 4;
1809: Sbc_1(m_regE);
1810: break;
1811:
1812: case 0x9C: // sbc_a_h
1813: cCycles -= 4;
1814: Sbc_1(m_regH);
1815: break;
1816:
1817: case 0x9D: // sbc_a_l
1818: cCycles -= 4;
1819: Sbc_1(m_regL);
1820: break;
1821:
1822: case 0x9E: // sbc_a_xhl
1823: cCycles -= 7;
1824: Sbc_1(MemReadByte(m_regHL));
1825: break;
1826:
1827: case 0x9F: // sbc_a_a
1828: cCycles -= 4;
1829: Sbc_1(m_regA);
1830: break;
1831:
1832: case 0xA0: // and_b
1833: cCycles -= 4;
1834: And(m_regB);
1835: break;
1836:
1837: case 0xA1: // and_c
1838: cCycles -= 4;
1839: And(m_regC);
1840: break;
1841:
1842: case 0xA2: // and_d
1843: cCycles -= 4;
1844: And(m_regD);
1845: break;
1846:
1847: case 0xA3: // and_e
1848: cCycles -= 4;
1849: And(m_regE);
1850: break;
1851:
1852: case 0xA4: // and_h
1853: cCycles -= 4;
1854: And(m_regH);
1855: break;
1856:
1857: case 0xA5: // and_l
1858: cCycles -= 4;
1859: And(m_regL);
1860: break;
1861:
1862: case 0xA6: // and_xhl
1863: cCycles -= 7;
1864: And(MemReadByte(m_regHL));
1865: break;
1866:
1867: case 0xA7: // and_a
1868: cCycles -= 4;
1869: And(m_regA);
1870: break;
1871:
1872: case 0xA8: // xor_b
1873: cCycles -= 4;
1874: Xor(m_regB);
1875: break;
1876:
1877: case 0xA9: // xor_c
1878: cCycles -= 4;
1879: Xor(m_regC);
1880: break;
1881:
1882: case 0xAA: // xor_d
1883: cCycles -= 4;
1884: Xor(m_regD);
1885: break;
1886:
1887: case 0xAB: // xor_e
1888: cCycles -= 4;
1889: Xor(m_regE);
1890: break;
1891:
1892: case 0xAC: // xor_h
1893: cCycles -= 4;
1894: Xor(m_regH);
1895: break;
1896:
1897: case 0xAD: // xor_l
1898: cCycles -= 4;
1899: Xor(m_regL);
1900: break;
1901:
1902: case 0xAE: // xor_xhl
1903: cCycles -= 7;
1904: Xor(MemReadByte(m_regHL));
1905: break;
1906:
1907: case 0xAF: // xor_a
1908: cCycles -= 4;
1909: Xor(m_regA);
1910: break;
1911:
1912: case 0xB0: // or_b
1913: cCycles -= 4;
1914: Or(m_regB);
1915: break;
1916:
1917: case 0xB1: // or_c
1918: cCycles -= 4;
1919: Or(m_regC);
1920: break;
1921:
1922: case 0xB2: // or_d
1923: cCycles -= 4;
1924: Or(m_regD);
1925: break;
1926:
1927: case 0xB3: // or_e
1928: cCycles -= 4;
1929: Or(m_regE);
1930: break;
1931:
1932: case 0xB4: // or_h
1933: cCycles -= 4;
1934: Or(m_regH);
1935: break;
1936:
1937: case 0xB5: // or_l
1938: cCycles -= 4;
1939: Or(m_regL);
1940: break;
1941:
1942: case 0xB6: // or_xhl
1943: cCycles -= 7;
1944: Or(MemReadByte(m_regHL));
1945: break;
1946:
1947: case 0xB7: // or_a
1948: cCycles -= 4;
1949: Or(m_regA);
1950: break;
1951:
1952: case 0xB8: // cp_b
1953: cCycles -= 4;
1954: Cp(m_regB);
1955: break;
1956:
1957: case 0xB9: // cp_c
1958: cCycles -= 4;
1959: Cp(m_regC);
1960: break;
1961:
1962: case 0xBA: // cp_d
1963: cCycles -= 4;
1964: Cp(m_regD);
1965: break;
1966:
1967: case 0xBB: // cp_e
1968: cCycles -= 4;
1969: Cp(m_regE);
1970: break;
1971:
1972: case 0xBC: // cp_h
1973: cCycles -= 4;
1974: Cp(m_regH);
1975: break;
1976:
1977: case 0xBD: // cp_l
1978: cCycles -= 4;
1979: Cp(m_regL);
1980: break;
1981:
1982: case 0xBE: // cp_xhl
1983: cCycles -= 7;
1984: Cp(MemReadByte(m_regHL));
1985: break;
1986:
1987: case 0xBF: // cp_a
1988: cCycles -= 4;
1989: Cp(m_regA);
1990: break;
1991:
1992: case 0xC0: // ret_nz
1993: cCycles -= 5;
1994: cCycles -= Ret1(m_regF & Z_FLAG);
1995: break;
1996:
1997: case 0xC1: // pop_bc
1998: cCycles -= 10;
1999: m_regBC = Pop();
2000: break;
2001:
2002: case 0xC2: // jp_nz
2003: cCycles -= 10;
2004: cCycles -= Jp1(m_regF & Z_FLAG);
2005: break;
2006:
2007: case 0xC3: // jp
2008: cCycles -= 10;
2009: #if 0
2010: Jp0(TRUE);
2011: #else
2012: {
2013: // speedup hack for Galaga adopted from MAME...
2014:
2015: WORD w = ImmedWord();
2016: WORD wPc = GetPC();
2017:
2018: SetPC(w);
2019:
2020: // removed since Galaga never hit it (maybe 1942 will), and it
2021: // caused the slowdown in Time Pilot and Gyruss hiscore bug
2022: // it isn't correct anyway since "0085 jp 0088" causes is to return (Gyruss)
2023: // shouldn't it be if (w == wPC - 3)???
2024: // jul-26-97 eam
2025:
2026: /*
2027: if (w == wPc)
2028: {
2029: // TRACE(__FILE__ ":jp (infinite loop) at %04X\n", GetPC());
2030: return (cCyclesArg - cCycles);
2031: }
2032: else */
2033: if (w == wPc - 6) // attn: very Galaga specific!!!! should be done in MageX by patching ROMs with HALTs (once I figure out how to fool the ROM check at bootup)
2034: {
2035: if (*m_rgbOpcode == 0x31)
2036: {
2037: // TRACE(__FILE__ ":jp (ld sp,#xxxx) at %04X\n", GetPC());
2038: goto z80ExecBottom;
2039: /* return (cCyclesArg - cCycles); */
2040: }
2041: }
2042: }
2043: #endif
2044: break;
2045:
2046: case 0xC4: // call_nz
2047: cCycles -= 10;
2048: cCycles -= Call1(m_regF & Z_FLAG);
2049: break;
2050:
2051: case 0xC5: // push_bc
2052: cCycles -= 11;
2053: Push(m_regBC);
2054: break;
2055:
2056: case 0xC6: // add_a_byte
2057: cCycles -= 7;
2058: Add_1(ImmedByte());
2059: break;
2060:
2061: case 0xC7: // rst_00
2062: cCycles -= 11;
2063: Rst(0x00);
2064: break;
2065:
2066: case 0xC8: // ret_z
2067: cCycles -= 5;
2068: cCycles -= Ret0(m_regF & Z_FLAG);
2069: break;
2070:
2071: case 0xC9: // ret
2072: cCycles -= 4;
2073: cCycles -= Ret0(TRUE);
2074: break;
2075:
2076: case 0xCA: // jp_z
2077: cCycles -= 10;
2078: cCycles -= Jp0(m_regF & Z_FLAG);
2079: break;
2080:
2081: case 0xCB: // cb
2082: cCycles -= HandleCB();
2083: break;
2084:
2085: case 0xCC: // call_z
2086: cCycles -= 10;
2087: cCycles -= Call0(m_regF & Z_FLAG);
2088: break;
2089:
2090: case 0xCD: // call
2091: cCycles -= 10;
2092: cCycles -= Call0(TRUE);
2093: break;
2094:
2095: case 0xCE: // adc_a_byte
2096: cCycles -= 7;
2097: Adc_1(ImmedByte());
2098: break;
2099:
2100: case 0xCF: // rst_08
2101: cCycles -= 11;
2102: Rst(0x08);
2103: break;
2104:
2105: case 0xD0: // ret_nc
2106: cCycles -= 5;
2107: cCycles -= Ret1(m_regF & C_FLAG);
2108: break;
2109:
2110: case 0xD1: // pop_de
2111: cCycles -= 10;
2112: m_regDE = Pop();
2113: break;
2114:
2115: case 0xD2: // jp_nc
2116: cCycles -= 10;
2117: cCycles -= Jp1(m_regF & C_FLAG);
2118: break;
2119:
2120: case 0xD3: // out_byte_a
2121: cCycles -= 11;
2122: Out(ImmedByte(), m_regA);
2123: break;
2124:
2125: case 0xD4: // call_nc
2126: cCycles -= 10;
2127: cCycles -= Call1(m_regF & C_FLAG);
2128: break;
2129:
2130: case 0xD5: // push_de
2131: cCycles -= 11;
2132: Push(m_regDE);
2133: break;
2134:
2135: case 0xD6: // sub_byte
2136: {
2137: cCycles -= 7;
2138: Sub_1(ImmedByte());
2139: break;
2140: }
2141:
2142: case 0xD7: // rst_10
2143: cCycles -= 11;
2144: Rst(0x10);
2145: break;
2146:
2147: case 0xD8: // ret_c
2148: cCycles -= 5;
2149: cCycles -= Ret0(m_regF & C_FLAG);
2150: break;
2151:
2152: case 0xD9: // exx
2153: cCycles -= 4;
2154: Exx();
2155: break;
2156:
2157: case 0xDA: // jp_c
2158: cCycles -= 10;
2159: cCycles -= Jp0(m_regF & C_FLAG);
2160: break;
2161:
2162: case 0xDB: // in_a_byte
2163: {
2164: BYTE bPort = ImmedByte();
2165: cCycles -= 11;
2166: m_regA = InRaw ( bPort );
2167: break;
2168: }
2169:
2170: case 0xDC: // call_c
2171: cCycles -= 10;
2172: cCycles -= Call0(m_regF & C_FLAG);
2173: break;
2174:
2175: case 0xDD: // dd
2176: cCycles -= HandleDD();
2177: break;
2178:
2179: case 0xDE: // sbc_a_byte
2180: cCycles -= 7;
2181: Sbc_1(ImmedByte());
2182: break;
2183:
2184: case 0xDF: // rst_18
2185: cCycles -= 11;
2186: Rst(0x18);
2187: break;
2188:
2189: case 0xE0: // ret_po
2190: cCycles -= 5;
2191: cCycles -= Ret1(m_regF & V_FLAG);
2192: break;
2193:
2194: case 0xE1: // pop_hl
2195: cCycles -= 10;
2196: m_regHL = Pop();
2197: break;
2198:
2199: case 0xE2: // jp_po
2200: cCycles -= 10;
2201: cCycles -= Jp1(m_regF & V_FLAG);
2202: break;
2203:
2204: case 0xE3: // ex_xsp_hl
2205: cCycles -= 19;
2206: {
2207: int i = MemReadWord(GetSP());
2208: MemWriteWord(GetSP(), m_regHL);
2209: m_regHL = i;
2210: break;
2211: }
2212:
2213: case 0xE4: // call_po
2214: cCycles -= 10;
2215: cCycles -= Call1(m_regF & V_FLAG);
2216: break;
2217:
2218: case 0xE5: // push_hl
2219: cCycles -= 11;
2220: Push(m_regHL);
2221: break;
2222:
2223: case 0xE6: // and_byte
2224: cCycles -= 7;
2225: And(ImmedByte());
2226: break;
2227:
2228: case 0xE7: // rst_20
2229: cCycles -= 11;
2230: Rst(0x20);
2231: break;
2232:
2233: case 0xE8: // ret_pe
2234: cCycles -= 5;
2235: cCycles -= Ret0(m_regF & V_FLAG);
2236: break;
2237:
2238: case 0xE9: // jp_hl
2239: cCycles -= 4;
2240: SetPC(m_regHL);
2241: break;
2242:
2243: case 0xEA: // jp_pe
2244: cCycles -= 10;
2245: cCycles -= Jp0(m_regF & V_FLAG);
2246: break;
2247:
2248: case 0xEB: // ex_de_hl
2249: cCycles -= 4;
2250: swap(m_regDE, m_regHL);
2251: break;
2252:
2253: case 0xEC: // call_pe
2254: cCycles -= 10;
2255: cCycles -= Call0(m_regF & V_FLAG);
2256: break;
2257:
2258: case 0xED: // ed
2259: cCycles -= HandleED(cCycles);
2260: break;
2261:
2262: case 0xEE: // xor_byte
2263: cCycles -= 7;
2264: Xor(ImmedByte());
2265: break;
2266:
2267: case 0xEF: // rst_28
2268: cCycles -= 11;
2269: Rst(0x28);
2270: break;
2271:
2272: case 0xF0: // ret_p
2273: cCycles -= 5;
2274: cCycles -= Ret1(m_regF & S_FLAG);
2275: break;
2276:
2277: case 0xF1: // pop_af
2278: cCycles -= 10;
2279: m_regAF = Pop();
2280: break;
2281:
2282: case 0xF2: // jp_p
2283: cCycles -= 10;
2284: cCycles -= Jp1(m_regF & S_FLAG);
2285: break;
2286:
2287: case 0xF3: // di
2288: cCycles -= 4;
2289: Di();
2290: break;
2291:
2292: case 0xF4: // call_p
2293: cCycles -= 10;
2294: cCycles -= Call1(m_regF & S_FLAG);
2295: break;
2296:
2297: case 0xF5: // push_af
2298: cCycles -= 11;
2299: Push(m_regAF);
2300: break;
2301:
2302: case 0xF6: // or_byte
2303: cCycles -= 7;
2304: Or(ImmedByte());
2305: break;
2306:
2307: case 0xF7: // rst_30
2308: cCycles -= 11;
2309: Rst(0x30);
2310: break;
2311:
2312: case 0xF8: // ret_m
2313: cCycles -= 5;
2314: cCycles -= Ret0(m_regF & S_FLAG);
2315: break;
2316:
2317: case 0xF9: // ld_sp_hl
2318: cCycles -= 6;
2319: SetSP(m_regHL);
2320: break;
2321:
2322: case 0xFA: // jp_m
2323: cCycles -= 10;
2324: cCycles -= Jp0(m_regF & S_FLAG);
2325: break;
2326:
2327: case 0xFB: // ei
2328: cCycles -= 4;
2329: cCycles -= Ei();
2330: // if (m_fPendingInterrupt)
2331: {
2332: // return (cCyclesArg - cCycles);
2333: }
2334: break;
2335:
2336: case 0xFC: // call_m
2337: cCycles -= 10;
2338: cCycles -= Call0(m_regF & S_FLAG);
2339: break;
2340:
2341: case 0xFD: // fd
2342: cCycles -= HandleFD();
2343: break;
2344:
2345: case 0xFE: // cp_byte
2346: cCycles -= 7;
2347: Cp(ImmedByte());
2348: break;
2349:
2350: case 0xFF: // rst_38
2351: cCycles -= 11;
2352: Rst(0x38);
2353: break;
2354:
2355: default:
2356: assert(FALSE);
2357: break;
2358: }
2359: }
2360:
2361: z80ExecBottom:
2362: z80pc = GetPC(); /* for some of the platforms */
2363: dwElapsedTicks = origElapsedTicks + (cCyclesArg - cCycles);
2364: return ( 0x80000000 );
2365: }
2366:
2367: UINT32 mz80int ( UINT32 bVal ) {
2368: if (m_iff1 == 0) // is IRQ disabled?
2369: return 0xffffffff; // Interrupt not taken!
2370:
2371: m_fPendingInterrupt = FALSE;
2372:
2373: m_iff1 = 0;
2374:
2375: if (m_fHalt)
2376: {
2377: SetPC(GetPC() + 1);
2378: m_fHalt = FALSE;
2379: }
2380:
2381: if (0 == m_nIM || 1 == m_nIM)
2382: {
2383: Rst(z80intAddr);
2384: return(0); // We took the interrupt
2385: }
2386:
2387: Push(GetPC());
2388: SetPC(MemReadWord(MAKEWORD(bVal, m_regI)));
2389:
2390: return(0); // fix-me
2391: }
2392:
2393: UINT32 mz80nmi ( void ) {
2394: m_iff1 = 0;
2395:
2396: if (m_fHalt)
2397: {
2398: SetPC(GetPC() + 1);
2399: m_fHalt = FALSE;
2400: }
2401:
2402: Rst(z80nmiAddr);
2403:
2404: return(0);
2405: }
2406:
2407: /* ***************************************************************************
2408: * Flow of Control
2409: * ***************************************************************************
2410: */
2411:
2412: /* inline */ int Jr0(int f) {
2413: if (f)
2414: {
2415: AdjustPC((signed char)ImmedByte());
2416: return 5;
2417: }
2418: else
2419: {
2420: AdjustPC(1);
2421: return 0;
2422: }
2423: }
2424:
2425: /* inline */ int Jr1(int f) {
2426: if (f)
2427: {
2428: AdjustPC(1);
2429: return 0;
2430: }
2431: else
2432: {
2433: AdjustPC((signed char)ImmedByte());
2434: return 5;
2435: }
2436: }
2437:
2438: /* inline */ int Call0(int f) {
2439: char string[150];
2440:
2441: if (f)
2442: {
2443: WORD wAddr = ImmedWord();
2444: Push(GetPC());
2445: SetPC(wAddr);
2446: return 7;
2447: }
2448: else
2449: {
2450: AdjustPC(2);
2451: return 0;
2452: }
2453: }
2454:
2455: /* inline */ int Call1(int f) {
2456: if (f)
2457: {
2458: AdjustPC(2);
2459: return 0;
2460: }
2461: else
2462: {
2463: WORD wAddr = ImmedWord();
2464: Push(GetPC());
2465: SetPC(wAddr);
2466: return 7;
2467: }
2468: }
2469:
2470: /* inline */ int Jp0(int f) {
2471: if (f)
2472: {
2473: SetPC(ImmedWord());
2474: return 0; // ????????????????
2475: }
2476: else
2477: {
2478: AdjustPC(2);
2479: return 0;
2480: }
2481: }
2482:
2483: /* inline */ int Jp1(int f) {
2484: if (f)
2485: {
2486: AdjustPC(2);
2487: return 0;
2488: }
2489: else
2490: {
2491: SetPC(ImmedWord());
2492: return 0; // ????????????????
2493: }
2494: }
2495:
2496: /* inline */ void Rst(WORD wAddr) {
2497: Push(GetPC());
2498: SetPC(wAddr);
2499: }
2500:
2501: /* ***************************************************************************
2502: * CB prefixed instructions
2503: * ***************************************************************************
2504: */
2505:
2506: int HandleCB() {
2507: const BYTE bOpcode = ImmedByte();
2508: m_regR++;
2509:
2510: switch (bOpcode)
2511: {
2512: case 0x00: // rlc_b
2513: m_regB = Rlc(m_regB);
2514: return 8;
2515:
2516: case 0x01: // rlc_c
2517: m_regC = Rlc(m_regC);
2518: return 8;
2519:
2520: case 0x02: // rlc_d
2521: m_regD = Rlc(m_regD);
2522: return 8;
2523:
2524: case 0x03: // rlc_e
2525: m_regE = Rlc(m_regE);
2526: return 8;
2527:
2528: case 0x04: // rlc_h
2529: m_regH = Rlc(m_regH);
2530: return 8;
2531:
2532: case 0x05: // rlc_l
2533: m_regL = Rlc(m_regL);
2534: return 8;
2535:
2536: case 0x06: // rlc_xhl
2537: MemWriteByte(m_regHL, Rlc(MemReadByte(m_regHL)));
2538: return 15;
2539:
2540: case 0x07: // rlc_a
2541: m_regA = Rlc(m_regA);
2542: return 8;
2543:
2544: case 0x08: // rrc_b
2545: m_regB = Rrc(m_regB);
2546: return 8;
2547:
2548: case 0x09: // rrc_c
2549: m_regC = Rrc(m_regC);
2550: return 8;
2551:
2552: case 0x0A: // rrc_d
2553: m_regD = Rrc(m_regD);
2554: return 8;
2555:
2556: case 0x0B: // rrc_e
2557: m_regE = Rrc(m_regE);
2558: return 8;
2559:
2560: case 0x0C: // rrc_h
2561: m_regH = Rrc(m_regH);
2562: return 8;
2563:
2564: case 0x0D: // rrc_l
2565: m_regL = Rrc(m_regL);
2566: return 8;
2567:
2568: case 0x0E: // rrc_xhl
2569: MemWriteByte(m_regHL, Rrc(MemReadByte(m_regHL)));
2570: return 15;
2571:
2572: case 0x0F: // rrc_a
2573: m_regA = Rrc(m_regA);
2574: return 8;
2575:
2576: case 0x10: // rl_b
2577: m_regB = Rl(m_regB);
2578: return 8;
2579:
2580: case 0x11: // rl_c
2581: m_regC = Rl(m_regC);
2582: return 8;
2583:
2584: case 0x12: // rl_d
2585: m_regD = Rl(m_regD);
2586: return 8;
2587:
2588: case 0x13: // rl_e
2589: m_regE = Rl(m_regE);
2590: return 8;
2591:
2592: case 0x14: // rl_h
2593: m_regH = Rl(m_regH);
2594: return 8;
2595:
2596: case 0x15: // rl_l
2597: m_regL = Rl(m_regL);
2598: return 8;
2599:
2600: case 0x16: // rl_xhl
2601: MemWriteByte(m_regHL, Rl(MemReadByte(m_regHL)));
2602: return 15;
2603:
2604: case 0x17: // rl_a
2605: m_regA = Rl(m_regA);
2606: return 8;
2607:
2608: case 0x18: // rr_b
2609: m_regB = Rr(m_regB);
2610: return 8;
2611:
2612: case 0x19: // rr_c
2613: m_regC = Rr(m_regC);
2614: return 8;
2615:
2616: case 0x1A: // rr_d
2617: m_regD = Rr(m_regD);
2618: return 8;
2619:
2620: case 0x1B: // rr_e
2621: m_regE = Rr(m_regE);
2622: return 8;
2623:
2624: case 0x1C: // rr_h
2625: m_regH = Rr(m_regH);
2626: return 8;
2627:
2628: case 0x1D: // rr_l
2629: m_regL = Rr(m_regL);
2630: return 8;
2631:
2632: case 0x1E: // rr_xhl
2633: MemWriteByte(m_regHL, Rr(MemReadByte(m_regHL)));
2634: return 15;
2635:
2636: case 0x1F: // rr_a
2637: m_regA = Rr(m_regA);
2638: return 8;
2639:
2640: case 0x20: // sla_b
2641: m_regB = Sla(m_regB);
2642: return 8;
2643:
2644: case 0x21: // sla_c
2645: m_regC = Sla(m_regC);
2646: return 8;
2647:
2648: case 0x22: // sla_d
2649: m_regD = Sla(m_regD);
2650: return 8;
2651:
2652: case 0x23: // sla_e
2653: m_regE = Sla(m_regE);
2654: return 8;
2655:
2656: case 0x24: // sla_h
2657: m_regH = Sla(m_regH);
2658: return 8;
2659:
2660: case 0x25: // sla_l
2661: m_regL = Sla(m_regL);
2662: return 8;
2663:
2664: case 0x26: // sla_xhl
2665: MemWriteByte(m_regHL, Sla(MemReadByte(m_regHL)));
2666: return 15;
2667:
2668: case 0x27: // sla_a
2669: m_regA = Sla(m_regA);
2670: return 8;
2671:
2672: case 0x28: // sra_b
2673: m_regB = Sra(m_regB);
2674: return 8;
2675:
2676: case 0x29: // sra_c
2677: m_regC = Sra(m_regC);
2678: return 8;
2679:
2680: case 0x2A: // sra_d
2681: m_regD = Sra(m_regD);
2682: return 8;
2683:
2684: case 0x2B: // sra_e
2685: m_regE = Sra(m_regE);
2686: return 8;
2687:
2688: case 0x2C: // sra_h
2689: m_regH = Sra(m_regH);
2690: return 8;
2691:
2692: case 0x2D: // sra_l
2693: m_regL = Sra(m_regL);
2694: return 8;
2695:
2696: case 0x2E: // sra_xhl
2697: MemWriteByte(m_regHL, Sra(MemReadByte(m_regHL)));
2698: return 15;
2699:
2700: case 0x2F: // sra_a
2701: m_regA = Sra(m_regA);
2702: return 8;
2703:
2704: case 0x30: // sll_b
2705: m_regB = Sll(m_regB);
2706: return 8;
2707:
2708: case 0x31: // sll_c
2709: m_regC = Sll(m_regC);
2710: return 8;
2711:
2712: case 0x32: // sll_d
2713: m_regD = Sll(m_regD);
2714: return 8;
2715:
2716: case 0x33: // sll_e
2717: m_regE = Sll(m_regE);
2718: return 8;
2719:
2720: case 0x34: // sll_h
2721: m_regH = Sll(m_regH);
2722: return 8;
2723:
2724: case 0x35: // sll_l
2725: m_regL = Sll(m_regL);
2726: return 8;
2727:
2728: case 0x36: // sll_xhl
2729: MemWriteByte(m_regHL, Sll(MemReadByte(m_regHL)));
2730: return 15;
2731:
2732: case 0x37: // sll_a
2733: m_regA = Sll(m_regA);
2734: return 8;
2735:
2736: case 0x38: // srl_b
2737: m_regB = Srl(m_regB);
2738: return 8;
2739:
2740: case 0x39: // srl_c
2741: m_regC = Srl(m_regC);
2742: return 8;
2743:
2744: case 0x3A: // srl_d
2745: m_regD = Srl(m_regD);
2746: return 8;
2747:
2748: case 0x3B: // srl_e
2749: m_regE = Srl(m_regE);
2750: return 8;
2751:
2752: case 0x3C: // srl_h
2753: m_regH = Srl(m_regH);
2754: return 8;
2755:
2756: case 0x3D: // srl_l
2757: m_regL = Srl(m_regL);
2758: return 8;
2759:
2760: case 0x3E: // srl_xhl
2761: MemWriteByte(m_regHL, Srl(MemReadByte(m_regHL)));
2762: return 15;
2763:
2764: case 0x3F: // srl_a
2765: m_regA = Srl(m_regA);
2766: return 8;
2767:
2768: case 0x40: // bit_0_b
2769: Bit(m_regB, 0);
2770: return 8;
2771:
2772: case 0x41: // bit_0_c
2773: Bit(m_regC, 0);
2774: return 8;
2775:
2776: case 0x42: // bit_0_d
2777: Bit(m_regD, 0);
2778: return 8;
2779:
2780: case 0x43: // bit_0_e
2781: Bit(m_regE, 0);
2782: return 8;
2783:
2784: case 0x44: // bit_0_h
2785: Bit(m_regH, 0);
2786: return 8;
2787:
2788: case 0x45: // bit_0_l
2789: Bit(m_regL, 0);
2790: return 8;
2791:
2792: case 0x46: // bit_0_xhl
2793: Bit(MemReadByte(m_regHL), 0);
2794: return 12;
2795:
2796: case 0x47: // bit_0_a
2797: Bit(m_regA, 0);
2798: return 8;
2799:
2800: case 0x48: // bit_1_b
2801: Bit(m_regB, 1);
2802: return 8;
2803:
2804: case 0x49: // bit_1_c
2805: Bit(m_regC, 1);
2806: return 8;
2807:
2808: case 0x4A: // bit_1_d
2809: Bit(m_regD, 1);
2810: return 8;
2811:
2812: case 0x4B: // bit_1_e
2813: Bit(m_regE, 1);
2814: return 8;
2815:
2816: case 0x4C: // bit_1_h
2817: Bit(m_regH, 1);
2818: return 8;
2819:
2820: case 0x4D: // bit_1_l
2821: Bit(m_regL, 1);
2822: return 8;
2823:
2824: case 0x4E: // bit_1_xhl
2825: Bit(MemReadByte(m_regHL), 1);
2826: return 12;
2827:
2828: case 0x4F: // bit_1_a
2829: Bit(m_regA, 1);
2830: return 8;
2831:
2832: case 0x50: // bit_2_b
2833: Bit(m_regB, 2);
2834: return 8;
2835:
2836: case 0x51: // bit_2_c
2837: Bit(m_regC, 2);
2838: return 8;
2839:
2840: case 0x52: // bit_2_d
2841: Bit(m_regD, 2);
2842: return 8;
2843:
2844: case 0x53: // bit_2_e
2845: Bit(m_regE, 2);
2846: return 8;
2847:
2848: case 0x54: // bit_2_h
2849: Bit(m_regH, 2);
2850: return 8;
2851:
2852: case 0x55: // bit_2_l
2853: Bit(m_regL, 2);
2854: return 8;
2855:
2856: case 0x56: // bit_2_xhl
2857: Bit(MemReadByte(m_regHL), 2);
2858: return 12;
2859:
2860: case 0x57: // bit_2_a
2861: Bit(m_regA, 2);
2862: return 8;
2863:
2864: case 0x58: // bit_3_b
2865: Bit(m_regB, 3);
2866: return 8;
2867:
2868: case 0x59: // bit_3_c
2869: Bit(m_regC, 3);
2870: return 8;
2871:
2872: case 0x5A: // bit_3_d
2873: Bit(m_regD, 3);
2874: return 8;
2875:
2876: case 0x5B: // bit_3_e
2877: Bit(m_regE, 3);
2878: return 8;
2879:
2880: case 0x5C: // bit_3_h
2881: Bit(m_regH, 3);
2882: return 8;
2883:
2884: case 0x5D: // bit_3_l
2885: Bit(m_regL, 3);
2886: return 8;
2887:
2888: case 0x5E: // bit_3_xhl
2889: Bit(MemReadByte(m_regHL), 3);
2890: return 12;
2891:
2892: case 0x5F: // bit_3_a
2893: Bit(m_regA, 3);
2894: return 8;
2895:
2896: case 0x60: // bit_4_b
2897: Bit(m_regB, 4);
2898: return 8;
2899:
2900: case 0x61: // bit_4_c
2901: Bit(m_regC, 4);
2902: return 8;
2903:
2904: case 0x62: // bit_4_d
2905: Bit(m_regD, 4);
2906: return 8;
2907:
2908: case 0x63: // bit_4_e
2909: Bit(m_regE, 4);
2910: return 8;
2911:
2912: case 0x64: // bit_4_h
2913: Bit(m_regH, 4);
2914: return 8;
2915:
2916: case 0x65: // bit_4_l
2917: Bit(m_regL, 4);
2918: return 8;
2919:
2920: case 0x66: // bit_4_xhl
2921: Bit(MemReadByte(m_regHL), 4);
2922: return 12;
2923:
2924: case 0x67: // bit_4_a
2925: Bit(m_regA, 4);
2926: return 8;
2927:
2928: case 0x68: // bit_5_b
2929: Bit(m_regB, 5);
2930: return 8;
2931:
2932: case 0x69: // bit_5_c
2933: Bit(m_regC, 5);
2934: return 8;
2935:
2936: case 0x6A: // bit_5_d
2937: Bit(m_regD, 5);
2938: return 8;
2939:
2940: case 0x6B: // bit_5_e
2941: Bit(m_regE, 5);
2942: return 8;
2943:
2944: case 0x6C: // bit_5_h
2945: Bit(m_regH, 5);
2946: return 8;
2947:
2948: case 0x6D: // bit_5_l
2949: Bit(m_regL, 5);
2950: return 8;
2951:
2952: case 0x6E: // bit_5_xhl
2953: Bit(MemReadByte(m_regHL), 5);
2954: return 12;
2955:
2956: case 0x6F: // bit_5_a
2957: Bit(m_regA, 5);
2958: return 8;
2959:
2960: case 0x70: // bit_6_b
2961: Bit(m_regB, 6);
2962: return 8;
2963:
2964: case 0x71: // bit_6_c
2965: Bit(m_regC, 6);
2966: return 8;
2967:
2968: case 0x72: // bit_6_d
2969: Bit(m_regD, 6);
2970: return 8;
2971:
2972: case 0x73: // bit_6_e
2973: Bit(m_regE, 6);
2974: return 8;
2975:
2976: case 0x74: // bit_6_h
2977: Bit(m_regH, 6);
2978: return 8;
2979:
2980: case 0x75: // bit_6_l
2981: Bit(m_regL, 6);
2982: return 8;
2983:
2984: case 0x76: // bit_6_xhl
2985: Bit(MemReadByte(m_regHL), 6);
2986: return 12;
2987:
2988: case 0x77: // bit_6_a
2989: Bit(m_regA, 6);
2990: return 8;
2991:
2992: case 0x78: // bit_7_b
2993: Bit(m_regB, 7);
2994: return 8;
2995:
2996: case 0x79: // bit_7_c
2997: Bit(m_regC, 7);
2998: return 8;
2999:
3000: case 0x7A: // bit_7_d
3001: Bit(m_regD, 7);
3002: return 8;
3003:
3004: case 0x7B: // bit_7_e
3005: Bit(m_regE, 7);
3006: return 8;
3007:
3008: case 0x7C: // bit_7_h
3009: Bit(m_regH, 7);
3010: return 8;
3011:
3012: case 0x7D: // bit_7_l
3013: Bit(m_regL, 7);
3014: return 8;
3015:
3016: case 0x7E: // bit_7_xhl
3017: Bit(MemReadByte(m_regHL), 7);
3018: return 12;
3019:
3020: case 0x7F: // bit_7_a
3021: Bit(m_regA, 7);
3022: return 8;
3023:
3024: case 0x80: // res_0_b
3025: m_regB = Res(m_regB, 0);
3026: return 8;
3027:
3028: case 0x81: // res_0_c
3029: m_regC = Res(m_regC, 0);
3030: return 8;
3031:
3032: case 0x82: // res_0_d
3033: m_regD = Res(m_regD, 0);
3034: return 8;
3035:
3036: case 0x83: // res_0_e
3037: m_regE = Res(m_regE, 0);
3038: return 8;
3039:
3040: case 0x84: // res_0_h
3041: m_regH = Res(m_regH, 0);
3042: return 8;
3043:
3044: case 0x85: // res_0_l
3045: m_regL = Res(m_regL, 0);
3046: return 8;
3047:
3048: case 0x86: // res_0_xhl
3049: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 0));
3050: return 15;
3051:
3052: case 0x87: // res_0_a
3053: m_regA = Res(m_regA, 0);
3054: return 8;
3055:
3056: case 0x88: // res_1_b
3057: m_regB = Res(m_regB ,1);
3058: return 8;
3059:
3060: case 0x89: // res_1_c
3061: m_regC = Res(m_regC, 1);
3062: return 8;
3063:
3064: case 0x8A: // res_1_d
3065: m_regD = Res(m_regD, 1);
3066: return 8;
3067:
3068: case 0x8B: // res_1_e
3069: m_regE = Res(m_regE, 1);
3070: return 8;
3071:
3072: case 0x8C: // res_1_h
3073: m_regH = Res(m_regH, 1);
3074: return 8;
3075:
3076: case 0x8D: // res_1_l
3077: m_regL = Res(m_regL, 1);
3078: return 8;
3079:
3080: case 0x8E: // res_1_xhl
3081: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 1));
3082: return 15;
3083:
3084: case 0x8F: // res_1_a
3085: m_regA = Res(m_regA, 1);
3086: return 8;
3087:
3088: case 0x90: // res_2_b
3089: m_regB = Res(m_regB ,2);
3090: return 8;
3091:
3092: case 0x91: // res_2_c
3093: m_regC = Res(m_regC, 2);
3094: return 8;
3095:
3096: case 0x92: // res_2_d
3097: m_regD = Res(m_regD, 2);
3098: return 8;
3099:
3100: case 0x93: // res_2_e
3101: m_regE = Res(m_regE, 2);
3102: return 8;
3103:
3104: case 0x94: // res_2_h
3105: m_regH = Res(m_regH, 2);
3106: return 8;
3107:
3108: case 0x95: // res_2_l
3109: m_regL = Res(m_regL, 2);
3110: return 8;
3111:
3112: case 0x96: // res_2_xhl
3113: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 2));
3114: return 15;
3115:
3116: case 0x97: // res_2_a
3117: m_regA = Res(m_regA, 2);
3118: return 8;
3119:
3120: case 0x98: // res_3_b
3121: m_regB = Res(m_regB ,3);
3122: return 8;
3123:
3124: case 0x99: // res_3_c
3125: m_regC = Res(m_regC, 3);
3126: return 8;
3127:
3128: case 0x9A: // res_3_d
3129: m_regD = Res(m_regD, 3);
3130: return 8;
3131:
3132: case 0x9B: // res_3_e
3133: m_regE = Res(m_regE, 3);
3134: return 8;
3135:
3136: case 0x9C: // res_3_h
3137: m_regH = Res(m_regH, 3);
3138: return 8;
3139:
3140: case 0x9D: // res_3_l
3141: m_regL = Res(m_regL, 3);
3142: return 8;
3143:
3144: case 0x9E: // res_3_xhl
3145: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 3));
3146: return 15;
3147:
3148: case 0x9F: // res_3_a
3149: m_regA = Res(m_regA, 3);
3150: return 8;
3151:
3152: case 0xA0: // res_4_b
3153: m_regB = Res(m_regB ,4);
3154: return 8;
3155:
3156: case 0xA1: // res_4_c
3157: m_regC = Res(m_regC, 4);
3158: return 8;
3159:
3160: case 0xA2: // res_4_d
3161: m_regD = Res(m_regD, 4);
3162: return 8;
3163:
3164: case 0xA3: // res_4_e
3165: m_regE = Res(m_regE, 4);
3166: return 8;
3167:
3168: case 0xA4: // res_4_h
3169: m_regH = Res(m_regH, 4);
3170: return 8;
3171:
3172: case 0xA5: // res_4_l
3173: m_regL = Res(m_regL, 4);
3174: return 8;
3175:
3176: case 0xA6: // res_4_xhl
3177: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 4));
3178: return 15;
3179:
3180: case 0xA7: // res_4_a
3181: m_regA = Res(m_regA, 4);
3182: return 8;
3183:
3184: case 0xA8: // res_5_b
3185: m_regB = Res(m_regB ,5);
3186: return 8;
3187:
3188: case 0xA9: // res_5_c
3189: m_regC = Res(m_regC, 5);
3190: return 8;
3191:
3192: case 0xAA: // res_5_d
3193: m_regD = Res(m_regD, 5);
3194: return 8;
3195:
3196: case 0xAB: // res_5_e
3197: m_regE = Res(m_regE, 5);
3198: return 8;
3199:
3200: case 0xAC: // res_5_h
3201: m_regH = Res(m_regH, 5);
3202: return 8;
3203:
3204: case 0xAD: // res_5_l
3205: m_regL = Res(m_regL, 5);
3206: return 8;
3207:
3208: case 0xAE: // res_5_xhl
3209: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 5));
3210: return 15;
3211:
3212: case 0xAF: // res_5_a
3213: m_regA = Res(m_regA, 5);
3214: return 8;
3215:
3216: case 0xB0: // res_6_b
3217: m_regB = Res(m_regB ,6);
3218: return 8;
3219:
3220: case 0xB1: // res_6_c
3221: m_regC = Res(m_regC, 6);
3222: return 8;
3223:
3224: case 0xB2: // res_6_d
3225: m_regD = Res(m_regD, 6);
3226: return 8;
3227:
3228: case 0xB3: // res_6_e
3229: m_regE = Res(m_regE, 6);
3230: return 8;
3231:
3232: case 0xB4: // res_6_h
3233: m_regH = Res(m_regH, 6);
3234: return 8;
3235:
3236: case 0xB5: // res_6_l
3237: m_regL = Res(m_regL, 6);
3238: return 8;
3239:
3240: case 0xB6: // res_6_xhl
3241: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 6));
3242: return 15;
3243:
3244: case 0xB7: // res_6_a
3245: m_regA = Res(m_regA, 6);
3246: return 8;
3247:
3248: case 0xB8: // res_7_b
3249: m_regB = Res(m_regB ,7);
3250: return 8;
3251:
3252: case 0xB9: // res_7_c
3253: m_regC = Res(m_regC, 7);
3254: return 8;
3255:
3256: case 0xBA: // res_7_d
3257: m_regD = Res(m_regD, 7);
3258: return 8;
3259:
3260: case 0xBB: // res_7_e
3261: m_regE = Res(m_regE, 7);
3262: return 8;
3263:
3264: case 0xBC: // res_7_h
3265: m_regH = Res(m_regH, 7);
3266: return 8;
3267:
3268: case 0xBD: // res_7_l
3269: m_regL = Res(m_regL, 7);
3270: return 8;
3271:
3272: case 0xBE: // res_7_xhl
3273: MemWriteByte(m_regHL, Res(MemReadByte(m_regHL), 7));
3274: return 15;
3275:
3276: case 0xBF: // res_7_a
3277: m_regA = Res(m_regA, 7);
3278: return 8;
3279:
3280: case 0xC0: // set_0_b
3281: m_regB = Set(m_regB ,0);
3282: return 8;
3283:
3284: case 0xC1: // set_0_c
3285: m_regC = Set(m_regC, 0);
3286: return 8;
3287:
3288: case 0xC2: // set_0_d
3289: m_regD = Set(m_regD, 0);
3290: return 8;
3291:
3292: case 0xC3: // set_0_e
3293: m_regE = Set(m_regE, 0);
3294: return 8;
3295:
3296: case 0xC4: // set_0_h
3297: m_regH = Set(m_regH, 0);
3298: return 8;
3299:
3300: case 0xC5: // set_0_l
3301: m_regL = Set(m_regL, 0);
3302: return 8;
3303:
3304: case 0xC6: // set_0_xhl
3305: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 0));
3306: return 15;
3307:
3308: case 0xC7: // set_0_a
3309: m_regA = Set(m_regA, 0);
3310: return 8;
3311:
3312: case 0xC8: // set_1_b
3313: m_regB = Set(m_regB ,1);
3314: return 8;
3315:
3316: case 0xC9: // set_1_c
3317: m_regC = Set(m_regC, 1);
3318: return 8;
3319:
3320: case 0xCA: // set_1_d
3321: m_regD = Set(m_regD, 1);
3322: return 8;
3323:
3324: case 0xCB: // set_1_e
3325: m_regE = Set(m_regE, 1);
3326: return 8;
3327:
3328: case 0xCC: // set_1_h
3329: m_regH = Set(m_regH, 1);
3330: return 8;
3331:
3332: case 0xCD: // set_1_l
3333: m_regL = Set(m_regL, 1);
3334: return 8;
3335:
3336: case 0xCE: // set_1_xhl
3337: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 1));
3338: return 15;
3339:
3340: case 0xCF: // set_1_a
3341: m_regA = Set(m_regA, 1);
3342: return 8;
3343:
3344: case 0xD0: // set_2_b
3345: m_regB = Set(m_regB ,2);
3346: return 8;
3347:
3348: case 0xD1: // set_2_c
3349: m_regC = Set(m_regC, 2);
3350: return 8;
3351:
3352: case 0xD2: // set_2_d
3353: m_regD = Set(m_regD, 2);
3354: return 8;
3355:
3356: case 0xD3: // set_2_e
3357: m_regE = Set(m_regE, 2);
3358: return 8;
3359:
3360: case 0xD4: // set_2_h
3361: m_regH = Set(m_regH, 2);
3362: return 8;
3363:
3364: case 0xD5: // set_2_l
3365: m_regL = Set(m_regL, 2);
3366: return 8;
3367:
3368: case 0xD6: // set_2_xhl
3369: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 2));
3370: return 15;
3371:
3372: case 0xD7: // set_2_a
3373: m_regA = Set(m_regA, 2);
3374: return 8;
3375:
3376: case 0xD8: // set_3_b
3377: m_regB = Set(m_regB ,3);
3378: return 8;
3379:
3380: case 0xD9: // set_3_c
3381: m_regC = Set(m_regC, 3);
3382: return 8;
3383:
3384: case 0xDA: // set_3_d
3385: m_regD = Set(m_regD, 3);
3386: return 8;
3387:
3388: case 0xDB: // set_3_e
3389: m_regE = Set(m_regE, 3);
3390: return 8;
3391:
3392: case 0xDC: // set_3_h
3393: m_regH = Set(m_regH, 3);
3394: return 8;
3395:
3396: case 0xDD: // set_3_l
3397: m_regL = Set(m_regL, 3);
3398: return 8;
3399:
3400: case 0xDE: // set_3_xhl
3401: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 3));
3402: return 15;
3403:
3404: case 0xDF: // set_3_a
3405: m_regA = Set(m_regA, 3);
3406: return 8;
3407:
3408: case 0xE0: // set_4_b
3409: m_regB = Set(m_regB ,4);
3410: return 8;
3411:
3412: case 0xE1: // set_4_c
3413: m_regC = Set(m_regC, 4);
3414: return 8;
3415:
3416: case 0xE2: // set_4_d
3417: m_regD = Set(m_regD, 4);
3418: return 8;
3419:
3420: case 0xE3: // set_4_e
3421: m_regE = Set(m_regE, 4);
3422: return 8;
3423:
3424: case 0xE4: // set_4_h
3425: m_regH = Set(m_regH, 4);
3426: return 8;
3427:
3428: case 0xE5: // set_4_l
3429: m_regL = Set(m_regL, 4);
3430: return 8;
3431:
3432: case 0xE6: // set_4_xhl
3433: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 4));
3434: return 15;
3435:
3436: case 0xE7: // set_4_a
3437: m_regA = Set(m_regA, 4);
3438: return 8;
3439:
3440: case 0xE8: // set_5_b
3441: m_regB = Set(m_regB ,5);
3442: return 8;
3443:
3444: case 0xE9: // set_5_c
3445: m_regC = Set(m_regC, 5);
3446: return 8;
3447:
3448: case 0xEA: // set_5_d
3449: m_regD = Set(m_regD, 5);
3450: return 8;
3451:
3452: case 0xEB: // set_5_e
3453: m_regE = Set(m_regE, 5);
3454: return 8;
3455:
3456: case 0xEC: // set_5_h
3457: m_regH = Set(m_regH, 5);
3458: return 8;
3459:
3460: case 0xED: // set_5_l
3461: m_regL = Set(m_regL, 5);
3462: return 8;
3463:
3464: case 0xEE: // set_5_xhl
3465: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 5));
3466: return 15;
3467:
3468: case 0xEF: // set_5_a
3469: m_regA = Set(m_regA, 5);
3470: return 8;
3471:
3472: case 0xF0: // set_6_b
3473: m_regB = Set(m_regB ,6);
3474: return 8;
3475:
3476: case 0xF1: // set_6_c
3477: m_regC = Set(m_regC, 6);
3478: return 8;
3479:
3480: case 0xF2: // set_6_d
3481: m_regD = Set(m_regD, 6);
3482: return 8;
3483:
3484: case 0xF3: // set_6_e
3485: m_regE = Set(m_regE, 6);
3486: return 8;
3487:
3488: case 0xF4: // set_6_h
3489: m_regH = Set(m_regH, 6);
3490: return 8;
3491:
3492: case 0xF5: // set_6_l
3493: m_regL = Set(m_regL, 6);
3494: return 8;
3495:
3496: case 0xF6: // set_6_xhl
3497: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 6));
3498: return 15;
3499:
3500: case 0xF7: // set_6_a
3501: m_regA = Set(m_regA, 6);
3502: return 8;
3503:
3504: case 0xF8: // set_7_b
3505: m_regB = Set(m_regB ,7);
3506: return 8;
3507:
3508: case 0xF9: // set_7_c
3509: m_regC = Set(m_regC, 7);
3510: return 8;
3511:
3512: case 0xFA: // set_7_d
3513: m_regD = Set(m_regD, 7);
3514: return 8;
3515:
3516: case 0xFB: // set_7_e
3517: m_regE = Set(m_regE, 7);
3518: return 8;
3519:
3520: case 0xFC: // set_7_h
3521: m_regH = Set(m_regH, 7);
3522: return 8;
3523:
3524: case 0xFD: // set_7_l
3525: m_regL = Set(m_regL, 7);
3526: return 8;
3527:
3528: case 0xFE: // set_7_xhl
3529: MemWriteByte(m_regHL, Set(MemReadByte(m_regHL), 7));
3530: return 15;
3531:
3532: case 0xFF: // set_7_a
3533: m_regA = Set(m_regA, 7);
3534: return 8;
3535:
3536: default:
3537: _ASSERT(FALSE);
3538: return 0;
3539: }
3540: }
3541:
3542: void Exx() {
3543: swap(m_regBC, m_regBC2);
3544: swap(m_regDE, m_regDE2);
3545: swap(m_regHL, m_regHL2);
3546: }
3547:
3548: /* ***************************************************************************
3549: * DD prefixed opcodes
3550: * ***************************************************************************
3551: */
3552: /* inline */ WORD IndirectIX() {
3553: return m_regIX + (signed char)ImmedByte();
3554: }
3555:
3556: int HandleDD() {
3557: WORD wAddr;
3558: WORD wTemp;
3559:
3560: const BYTE bOpcode = ImmedByte();
3561:
3562: m_regR++;
3563:
3564: switch (bOpcode)
3565: {
3566: case 0x00: // no_op
3567: SetPC(GetPC() - 1);
3568: return 0;
3569:
3570: case 0x01: // no_op
3571: SetPC(GetPC() - 1);
3572: return 0;
3573:
3574: case 0x02: // no_op
3575: SetPC(GetPC() - 1);
3576: return 0;
3577:
3578: case 0x03: // no_op
3579: SetPC(GetPC() - 1);
3580: return 0;
3581:
3582: case 0x04: // no_op
3583: SetPC(GetPC() - 1);
3584: return 0;
3585:
3586: case 0x05: // no_op
3587: SetPC(GetPC() - 1);
3588: return 0;
3589:
3590: case 0x06: // no_op
3591: SetPC(GetPC() - 1);
3592: return 0;
3593:
3594: case 0x07: // no_op
3595: SetPC(GetPC() - 1);
3596: return 0;
3597:
3598: case 0x08: // no_op
3599: SetPC(GetPC() - 1);
3600: return 0;
3601:
3602: case 0x09: // add_ix_bc
3603: m_regIX = Add_2(m_regIX, m_regBC);
3604: return 15;
3605:
3606: case 0x0A: // no_op
3607: SetPC(GetPC() - 1);
3608: return 0;
3609:
3610: case 0x0B: // no_op
3611: SetPC(GetPC() - 1);
3612: return 0;
3613:
3614: case 0x0C: // no_op
3615: SetPC(GetPC() - 1);
3616: return 0;
3617:
3618: case 0x0D: // no_op
3619: SetPC(GetPC() - 1);
3620: return 0;
3621:
3622: case 0x0E: // no_op
3623: SetPC(GetPC() - 1);
3624: return 0;
3625:
3626: case 0x0F: // no_op
3627: SetPC(GetPC() - 1);
3628: return 0;
3629:
3630: case 0x10: // no_op
3631: SetPC(GetPC() - 1);
3632: return 0;
3633:
3634: case 0x11: // no_op
3635: SetPC(GetPC() - 1);
3636: return 0;
3637:
3638: case 0x12: // no_op
3639: SetPC(GetPC() - 1);
3640: return 0;
3641:
3642: case 0x13: // no_op
3643: SetPC(GetPC() - 1);
3644: return 0;
3645:
3646: case 0x14: // no_op
3647: SetPC(GetPC() - 1);
3648: return 0;
3649:
3650: case 0x15: // no_op
3651: SetPC(GetPC() - 1);
3652: return 0;
3653:
3654: case 0x16: // no_op
3655: SetPC(GetPC() - 1);
3656: return 0;
3657:
3658: case 0x17: // no_op
3659: SetPC(GetPC() - 1);
3660: return 0;
3661:
3662: case 0x18: // no_op
3663: SetPC(GetPC() - 1);
3664: return 0;
3665:
3666: case 0x19: // add_ix_de
3667: m_regIX = Add_2(m_regIX, m_regDE);
3668: return 15;
3669:
3670: case 0x1A: // no_op
3671: SetPC(GetPC() - 1);
3672: return 0;
3673:
3674: case 0x1B: // no_op
3675: SetPC(GetPC() - 1);
3676: return 0;
3677:
3678: case 0x1C: // no_op
3679: SetPC(GetPC() - 1);
3680: return 0;
3681:
3682: case 0x1D: // no_op
3683: SetPC(GetPC() - 1);
3684: return 0;
3685:
3686: case 0x1E: // no_op
3687: SetPC(GetPC() - 1);
3688: return 0;
3689:
3690: case 0x1F: // no_op
3691: SetPC(GetPC() - 1);
3692: return 0;
3693:
3694: case 0x20: // no_op
3695: SetPC(GetPC() - 1);
3696: return 0;
3697:
3698: case 0x21: // ld_ix_word
3699: m_regIX = ImmedWord();
3700: return 14;
3701:
3702: case 0x22: // ld_xword_ix
3703: MemWriteWord(ImmedWord(), m_regIX);
3704: return 20;
3705:
3706: case 0x23: // inc_ix
3707: m_regIX++;
3708: return 10;
3709:
3710: case 0x24: // inc_ixh
3711: m_regIXh = Inc(m_regIXh);
3712: return 9;
3713:
3714: case 0x25: // dec_ixh
3715: m_regIXh = Dec(m_regIXh);
3716: return 9;
3717:
3718: case 0x26: // ld_ixh_byte
3719: m_regIXh = ImmedByte();
3720: return 9;
3721:
3722: case 0x27: // no_op
3723: SetPC(GetPC() - 1);
3724: return 0;
3725:
3726: case 0x28: // no_op
3727: SetPC(GetPC() - 1);
3728: return 0;
3729:
3730: case 0x29: // add_ix_ix
3731: m_regIX = Add_2(m_regIX, m_regIX);
3732: return 15;
3733:
3734: case 0x2A: // ld_ix_xword
3735: m_regIX = MemReadWord(ImmedWord());
3736: return 20;
3737:
3738: case 0x2B: // dec_ix
3739: m_regIX--;
3740: return 10;
3741:
3742: case 0x2C: // inc_ixl
3743: m_regIXl = Inc(m_regIXl);
3744: return 9;
3745:
3746: case 0x2D: // dec_ixl
3747: m_regIXl = Dec(m_regIXl);
3748: return 9;
3749:
3750: case 0x2E: // ld_ixl_byte
3751: m_regIXl = ImmedByte();
3752: return 9;
3753:
3754: case 0x2F: // no_op
3755: SetPC(GetPC() - 1);
3756: return 0;
3757:
3758: case 0x30: // no_op
3759: SetPC(GetPC() - 1);
3760: return 0;
3761:
3762: case 0x31: // no_op
3763: SetPC(GetPC() - 1);
3764: return 0;
3765:
3766: case 0x32: // no_op
3767: SetPC(GetPC() - 1);
3768: return 0;
3769:
3770: case 0x33: // no_op
3771: SetPC(GetPC() - 1);
3772: return 0;
3773:
3774: case 0x34: // inc_xix
3775: wAddr = IndirectIX();
3776: MemWriteByte(wAddr, Inc(MemReadByte(wAddr)));
3777: return 23;
3778:
3779: case 0x35: // dec_xix
3780: wAddr = IndirectIX();
3781: MemWriteByte(wAddr, Dec(MemReadByte(wAddr)));
3782: return 23;
3783:
3784: case 0x36: // ld_xix_byte
3785: wAddr = IndirectIX();
3786: MemWriteByte(wAddr, ImmedByte());
3787: return 19;
3788:
3789: case 0x37: // no_op
3790: SetPC(GetPC() - 1);
3791: return 0;
3792:
3793: case 0x38: // no_op
3794: SetPC(GetPC() - 1);
3795: return 0;
3796:
3797: case 0x39: // add_ix_sp
3798: m_regIX = Add_2(m_regIX, GetSP());
3799: return 15;
3800:
3801: case 0x3A: // no_op
3802: SetPC(GetPC() - 1);
3803: return 0;
3804:
3805: case 0x3B: // no_op
3806: SetPC(GetPC() - 1);
3807: return 0;
3808:
3809: case 0x3C: // no_op
3810: SetPC(GetPC() - 1);
3811: return 0;
3812:
3813: case 0x3D: // no_op
3814: SetPC(GetPC() - 1);
3815: return 0;
3816:
3817: case 0x3E: // no_op
3818: SetPC(GetPC() - 1);
3819: return 0;
3820:
3821: case 0x3F: // no_op
3822: SetPC(GetPC() - 1);
3823: return 0;
3824:
3825: case 0x40: // no_op
3826: SetPC(GetPC() - 1);
3827: return 0;
3828:
3829: case 0x41: // no_op
3830: SetPC(GetPC() - 1);
3831: return 0;
3832:
3833: case 0x42: // no_op
3834: SetPC(GetPC() - 1);
3835: return 0;
3836:
3837: case 0x43: // no_op
3838: SetPC(GetPC() - 1);
3839: return 0;
3840:
3841: case 0x44: // ld_b_ixh
3842: m_regB = m_regIXh;
3843: return 9;
3844:
3845: case 0x45: // ld_b_ixl
3846: m_regB = m_regIXl;
3847: return 9;
3848:
3849: case 0x46: // ld_b_xix
3850: m_regB = MemReadByte(IndirectIX());
3851: return 19;
3852:
3853: case 0x47: // no_op
3854: SetPC(GetPC() - 1);
3855: return 0;
3856:
3857: case 0x48: // no_op
3858: SetPC(GetPC() - 1);
3859: return 0;
3860:
3861: case 0x49: // no_op
3862: SetPC(GetPC() - 1);
3863: return 0;
3864:
3865: case 0x4A: // no_op
3866: SetPC(GetPC() - 1);
3867: return 0;
3868:
3869: case 0x4B: // no_op
3870: SetPC(GetPC() - 1);
3871: return 0;
3872:
3873: case 0x4C: // ld_c_ixh
3874: m_regC = m_regIXh;
3875: return 9;
3876:
3877: case 0x4D: // ld_c_ixl
3878: m_regC = m_regIXl;
3879: return 9;
3880:
3881: case 0x4E: // ld_c_xix
3882: m_regC = MemReadByte(IndirectIX());
3883: return 19;
3884:
3885: case 0x4F: // no_op
3886: SetPC(GetPC() - 1);
3887: return 0;
3888:
3889: case 0x50: // no_op
3890: SetPC(GetPC() - 1);
3891: return 0;
3892:
3893: case 0x51: // no_op
3894: SetPC(GetPC() - 1);
3895: return 0;
3896:
3897: case 0x52: // no_op
3898: SetPC(GetPC() - 1);
3899: return 0;
3900:
3901: case 0x53: // no_op
3902: SetPC(GetPC() - 1);
3903: return 0;
3904:
3905: case 0x54: // ld_d_ixh
3906: m_regD = m_regIXh;
3907: return 9;
3908:
3909: case 0x55: // ld_d_ixl
3910: m_regD = m_regIXl;
3911: return 9;
3912:
3913: case 0x56: // ld_d_xix
3914: m_regD = MemReadByte(IndirectIX());
3915: return 19;
3916:
3917: case 0x57: // no_op
3918: SetPC(GetPC() - 1);
3919: return 0;
3920:
3921: case 0x58: // no_op
3922: SetPC(GetPC() - 1);
3923: return 0;
3924:
3925: case 0x59: // no_op
3926: SetPC(GetPC() - 1);
3927: return 0;
3928:
3929: case 0x5A: // no_op
3930: SetPC(GetPC() - 1);
3931: return 0;
3932:
3933: case 0x5B: // no_op
3934: SetPC(GetPC() - 1);
3935: return 0;
3936:
3937: case 0x5C: // ld_e_ixh
3938: m_regE = m_regIXh;
3939: return 9;
3940:
3941: case 0x5D: // ld_e_ixl
3942: m_regE = m_regIXl;
3943: return 9;
3944:
3945: case 0x5E: // ld_e_xix
3946: m_regE = MemReadByte(IndirectIX());
3947: return 19;
3948:
3949: case 0x5F: // no_op
3950: SetPC(GetPC() - 1);
3951: return 0;
3952:
3953: case 0x60: // ld_ixh_b
3954: m_regIXh = m_regB;
3955: return 9;
3956:
3957: case 0x61: // ld_ixh_c
3958: m_regIXh = m_regC;
3959: return 9;
3960:
3961: case 0x62: // ld_ixh_d
3962: m_regIXh = m_regD;
3963: return 9;
3964:
3965: case 0x63: // ld_ixh_e
3966: m_regIXh = m_regE;
3967: return 9;
3968:
3969: case 0x64: // ld_ixh_h
3970: m_regIXh = m_regH;
3971: return 9;
3972:
3973: case 0x65: // ld_ixh_l
3974: m_regIXh = m_regL;
3975: return 9;
3976:
3977: case 0x66: // ld_h_xix
3978: m_regH = MemReadByte(IndirectIX());
3979: return 9;
3980:
3981: case 0x67: // ld_ixh_a
3982: m_regIXh = m_regA;
3983: return 9;
3984:
3985: case 0x68: // ld_ixl_b
3986: m_regIXl = m_regB;
3987: return 9;
3988:
3989: case 0x69: // ld_ixl_c
3990: m_regIXl = m_regC;
3991: return 9;
3992:
3993: case 0x6A: // ld_ixl_d
3994: m_regIXl = m_regD;
3995: return 9;
3996:
3997: case 0x6B: // ld_ixl_e
3998: m_regIXl = m_regE;
3999: return 9;
4000:
4001: case 0x6C: // ld_ixl_h
4002: m_regIXl = m_regH;
4003: return 9;
4004:
4005: case 0x6D: // ld_ixl_l
4006: m_regIXl = m_regL;
4007: return 9;
4008:
4009: case 0x6E: // ld_l_xix
4010: m_regL = MemReadByte(IndirectIX());
4011: return 9;
4012:
4013: case 0x6F: // ld_ixl_a
4014: m_regIXl = m_regA;
4015: return 9;
4016:
4017: case 0x70: // ld_xix_b
4018: MemWriteByte(IndirectIX(), m_regB);
4019: return 19;
4020:
4021: case 0x71: // ld_xix_c
4022: MemWriteByte(IndirectIX(), m_regC);
4023: return 19;
4024:
4025: case 0x72: // ld_xix_d
4026: MemWriteByte(IndirectIX(), m_regD);
4027: return 19;
4028:
4029: case 0x73: // ld_xix_e
4030: MemWriteByte(IndirectIX(), m_regE);
4031: return 19;
4032:
4033: case 0x74: // ld_xix_h
4034: MemWriteByte(IndirectIX(), m_regH);
4035: return 19;
4036:
4037: case 0x75: // ld_xix_l
4038: MemWriteByte(IndirectIX(), m_regL);
4039: return 19;
4040:
4041: case 0x76: // no_op
4042: SetPC(GetPC() - 1);
4043: return 19;
4044:
4045: case 0x77: // ld_xix_a
4046: MemWriteByte(IndirectIX(), m_regA);
4047: return 19;
4048:
4049: case 0x78: // no_op
4050: SetPC(GetPC() - 1);
4051: return 0;
4052:
4053: case 0x79: // no_op
4054: SetPC(GetPC() - 1);
4055: return 0;
4056:
4057: case 0x7A: // no_op
4058: SetPC(GetPC() - 1);
4059: return 0;
4060:
4061: case 0x7B: // no_op
4062: SetPC(GetPC() - 1);
4063: return 0;
4064:
4065: case 0x7C: // ld_a_ixh
4066: m_regA = m_regIXh;
4067: return 9;
4068:
4069: case 0x7D: // ld_a_ixl
4070: m_regA = m_regIXl;
4071: return 9;
4072:
4073: case 0x7E: // ld_a_xix
4074: m_regA = MemReadByte(IndirectIX());
4075: return 19;
4076:
4077: case 0x7F: // no_op
4078: SetPC(GetPC() - 1);
4079: return 0;
4080:
4081: case 0x80: // no_op
4082: SetPC(GetPC() - 1);
4083: return 0;
4084:
4085: case 0x81: // no_op
4086: SetPC(GetPC() - 1);
4087: return 0;
4088:
4089: case 0x82: // no_op
4090: SetPC(GetPC() - 1);
4091: return 0;
4092:
4093: case 0x83: // no_op
4094: SetPC(GetPC() - 1);
4095: return 0;
4096:
4097: case 0x84: // add_a_ixh
4098: Add_1(m_regIXh);
4099: return 9;
4100:
4101: case 0x85: // add_a_ixl
4102: Add_1(m_regIXl);
4103: return 9;
4104:
4105: case 0x86: // add_a_xix
4106: Add_1(MemReadByte(IndirectIX()));
4107: return 19;
4108:
4109: case 0x87: // no_op
4110: SetPC(GetPC() - 1);
4111: return 0;
4112:
4113: case 0x88: // no_op
4114: SetPC(GetPC() - 1);
4115: return 0;
4116:
4117: case 0x89: // no_op
4118: SetPC(GetPC() - 1);
4119: return 0;
4120:
4121: case 0x8A: // no_op
4122: SetPC(GetPC() - 1);
4123: return 0;
4124:
4125: case 0x8B: // no_op
4126: SetPC(GetPC() - 1);
4127: return 0;
4128:
4129: case 0x8C: // adc_a_ixh
4130: Adc_1(m_regIXh);
4131: return 9;
4132:
4133: case 0x8D: // adc_a_ixl
4134: Adc_1(m_regIXl);
4135: return 9;
4136:
4137: case 0x8E: // adc_a_xix
4138: Adc_1(MemReadByte(IndirectIX()));
4139: return 19;
4140:
4141: case 0x8F: // no_op
4142: SetPC(GetPC() - 1);
4143: return 0;
4144:
4145: case 0x90: // no_op
4146: SetPC(GetPC() - 1);
4147: return 0;
4148:
4149: case 0x91: // no_op
4150: SetPC(GetPC() - 1);
4151: return 0;
4152:
4153: case 0x92: // no_op
4154: SetPC(GetPC() - 1);
4155: return 0;
4156:
4157: case 0x93: // no_op
4158: SetPC(GetPC() - 1);
4159: return 0;
4160:
4161: case 0x94: // sub_ixh
4162: Sub_1(m_regIXh);
4163: return 9;
4164:
4165: case 0x95: // sub_ixl
4166: Sub_1(m_regIXl);
4167: return 9;
4168:
4169: case 0x96: // sub_xix
4170: Sub_1(MemReadByte(IndirectIX()));
4171: return 19;
4172:
4173: case 0x97: // no_op
4174: SetPC(GetPC() - 1);
4175: return 0;
4176:
4177: case 0x98: // no_op
4178: SetPC(GetPC() - 1);
4179: return 0;
4180:
4181: case 0x99: // no_op
4182: SetPC(GetPC() - 1);
4183: return 0;
4184:
4185: case 0x9A: // no_op
4186: SetPC(GetPC() - 1);
4187: return 0;
4188:
4189: case 0x9B: // no_op
4190: SetPC(GetPC() - 1);
4191: return 0;
4192:
4193: case 0x9C: // sbc_a_ixh
4194: Sbc_1(m_regIXh);
4195: return 9;
4196:
4197: case 0x9D: // sbc_a_ixl
4198: Sbc_1(m_regIXl);
4199: return 9;
4200:
4201: case 0x9E: // sbc_a_xix
4202: Sbc_1(MemReadByte(IndirectIX()));
4203: return 19;
4204:
4205: case 0x9F: // no_op
4206: SetPC(GetPC() - 1);
4207: return 0;
4208:
4209: case 0xA0: // no_op
4210: SetPC(GetPC() - 1);
4211: return 0;
4212:
4213: case 0xA1: // no_op
4214: SetPC(GetPC() - 1);
4215: return 0;
4216:
4217: case 0xA2: // no_op
4218: SetPC(GetPC() - 1);
4219: return 0;
4220:
4221: case 0xA3: // no_op
4222: SetPC(GetPC() - 1);
4223: return 0;
4224:
4225: case 0xA4: // and_ixh
4226: And(m_regIXh);
4227: return 9;
4228:
4229: case 0xA5: // and_ixl
4230: And(m_regIXl);
4231: return 9;
4232:
4233: case 0xA6: // and_xix
4234: And(MemReadByte(IndirectIX()));
4235: return 19;
4236:
4237: case 0xA7: // no_op
4238: SetPC(GetPC() - 1);
4239: return 0;
4240:
4241: case 0xA8: // no_op
4242: SetPC(GetPC() - 1);
4243: return 0;
4244:
4245: case 0xA9: // no_op
4246: SetPC(GetPC() - 1);
4247: return 0;
4248:
4249: case 0xAA: // no_op
4250: SetPC(GetPC() - 1);
4251: return 0;
4252:
4253: case 0xAB: // no_op
4254: SetPC(GetPC() - 1);
4255: return 0;
4256:
4257: case 0xAC: // xor_ixh
4258: Xor(m_regIXh);
4259: return 9;
4260:
4261: case 0xAD: // xor_ixl
4262: Xor(m_regIXl);
4263: return 9;
4264:
4265: case 0xAE: // xor_xix
4266: Xor(MemReadByte(IndirectIX()));
4267: return 19;
4268:
4269: case 0xAF: // no_op
4270: SetPC(GetPC() - 1);
4271: return 0;
4272:
4273: case 0xB0: // no_op
4274: SetPC(GetPC() - 1);
4275: return 0;
4276:
4277: case 0xB1: // no_op
4278: SetPC(GetPC() - 1);
4279: return 0;
4280:
4281: case 0xB2: // no_op
4282: SetPC(GetPC() - 1);
4283: return 0;
4284:
4285: case 0xB3: // no_op
4286: SetPC(GetPC() - 1);
4287: return 0;
4288:
4289: case 0xB4: // or_ixh
4290: Or(m_regIXh);
4291: return 9;
4292:
4293: case 0xB5: // or_ixl
4294: Or(m_regIXl);
4295: return 9;
4296:
4297: case 0xB6: // or_xix
4298: Or(MemReadByte(IndirectIX()));
4299: return 19;
4300:
4301: case 0xB7: // no_op
4302: SetPC(GetPC() - 1);
4303: return 0;
4304:
4305: case 0xB8: // no_op
4306: SetPC(GetPC() - 1);
4307: return 0;
4308:
4309: case 0xB9: // no_op
4310: SetPC(GetPC() - 1);
4311: return 0;
4312:
4313: case 0xBA: // no_op
4314: SetPC(GetPC() - 1);
4315: return 0;
4316:
4317: case 0xBB: // no_op
4318: SetPC(GetPC() - 1);
4319: return 0;
4320:
4321: case 0xBC: // cp_ixh
4322: Cp(m_regIXh);
4323: return 9;
4324:
4325: case 0xBD: // cp_ixl
4326: Cp(m_regIXl);
4327: return 9;
4328:
4329: case 0xBE: // cp_xix
4330: Cp(MemReadByte(IndirectIX()));
4331: return 19;
4332:
4333: case 0xBF: // no_op
4334: SetPC(GetPC() - 1);
4335: return 0;
4336:
4337: case 0xC0: // no_op
4338: SetPC(GetPC() - 1);
4339: return 0;
4340:
4341: case 0xC1: // no_op
4342: SetPC(GetPC() - 1);
4343: return 0;
4344:
4345: case 0xC2: // no_op
4346: SetPC(GetPC() - 1);
4347: return 0;
4348:
4349: case 0xC3: // no_op
4350: SetPC(GetPC() - 1);
4351: return 0;
4352:
4353: case 0xC4: // no_op
4354: SetPC(GetPC() - 1);
4355: return 0;
4356:
4357: case 0xC5: // no_op
4358: SetPC(GetPC() - 1);
4359: return 0;
4360:
4361: case 0xC6: // no_op
4362: SetPC(GetPC() - 1);
4363: return 0;
4364:
4365: case 0xC7: // no_op
4366: SetPC(GetPC() - 1);
4367: return 0;
4368:
4369: case 0xC8: // no_op
4370: SetPC(GetPC() - 1);
4371: return 0;
4372:
4373: case 0xC9: // no_op
4374: SetPC(GetPC() - 1);
4375: return 0;
4376:
4377: case 0xCA: // no_op
4378: SetPC(GetPC() - 1);
4379: return 0;
4380:
4381: case 0xCB: // dd_cb
4382: return HandleDDCB();
4383: break;
4384:
4385: case 0xCC: // no_op
4386: SetPC(GetPC() - 1);
4387: return 0;
4388:
4389: case 0xCD: // no_op
4390: SetPC(GetPC() - 1);
4391: return 0;
4392:
4393: case 0xCE: // no_op
4394: SetPC(GetPC() - 1);
4395: return 0;
4396:
4397: case 0xCF: // no_op
4398: SetPC(GetPC() - 1);
4399: return 0;
4400:
4401: case 0xD0: // no_op
4402: SetPC(GetPC() - 1);
4403: return 0;
4404:
4405: case 0xD1: // no_op
4406: SetPC(GetPC() - 1);
4407: return 0;
4408:
4409: case 0xD2: // no_op
4410: SetPC(GetPC() - 1);
4411: return 0;
4412:
4413: case 0xD3: // no_op
4414: SetPC(GetPC() - 1);
4415: return 0;
4416:
4417: case 0xD4: // no_op
4418: SetPC(GetPC() - 1);
4419: return 0;
4420:
4421: case 0xD5: // no_op
4422: SetPC(GetPC() - 1);
4423: return 0;
4424:
4425: case 0xD6: // no_op
4426: SetPC(GetPC() - 1);
4427: return 0;
4428:
4429: case 0xD7: // no_op
4430: SetPC(GetPC() - 1);
4431: return 0;
4432:
4433: case 0xD8: // no_op
4434: SetPC(GetPC() - 1);
4435: return 0;
4436:
4437: case 0xD9: // no_op
4438: SetPC(GetPC() - 1);
4439: return 0;
4440:
4441: case 0xDA: // no_op
4442: SetPC(GetPC() - 1);
4443: return 0;
4444:
4445: case 0xDB: // no_op
4446: SetPC(GetPC() - 1);
4447: return 0;
4448:
4449: case 0xDC: // no_op
4450: SetPC(GetPC() - 1);
4451: return 0;
4452:
4453: case 0xDD: // no_op
4454: SetPC(GetPC() - 1);
4455: return 0;
4456:
4457: case 0xDE: // no_op
4458: SetPC(GetPC() - 1);
4459: return 0;
4460:
4461: case 0xDF: // no_op
4462: SetPC(GetPC() - 1);
4463: return 0;
4464:
4465: case 0xE0: // no_op
4466: SetPC(GetPC() - 1);
4467: return 0;
4468:
4469: case 0xE1: // pop_ix
4470: m_regIX = Pop();
4471: return 14;
4472:
4473: case 0xE2: // no_op
4474: SetPC(GetPC() - 1);
4475: return 0;
4476:
4477: case 0xE3: // ex_xsp_ix
4478: wTemp = MemReadWord(GetSP());
4479: MemWriteWord(GetSP(), m_regIX);
4480: m_regIX = wTemp;
4481: return 23;
4482:
4483: case 0xE4: // no_op
4484: SetPC(GetPC() - 1);
4485: return 0;
4486:
4487: case 0xE5: // push_ix
4488: Push(m_regIX);
4489: return 15;
4490:
4491: case 0xE6: // no_op
4492: SetPC(GetPC() - 1);
4493: return 0;
4494:
4495: case 0xE7: // no_op
4496: SetPC(GetPC() - 1);
4497: return 0;
4498:
4499: case 0xE8: // no_op
4500: SetPC(GetPC() - 1);
4501: return 0;
4502:
4503: case 0xE9: // jp_ix
4504: SetPC(m_regIX);
4505: return 8;
4506:
4507: case 0xEA: // no_op
4508: SetPC(GetPC() - 1);
4509: return 0;
4510:
4511: case 0xEB: // no_op
4512: SetPC(GetPC() - 1);
4513: return 0;
4514:
4515: case 0xEC: // no_op
4516: SetPC(GetPC() - 1);
4517: return 0;
4518:
4519: case 0xED: // no_op
4520: SetPC(GetPC() - 1);
4521: return 0;
4522:
4523: case 0xEE: // no_op
4524: SetPC(GetPC() - 1);
4525: return 0;
4526:
4527: case 0xEF: // no_op
4528: SetPC(GetPC() - 1);
4529: return 0;
4530:
4531: case 0xF0: // no_op
4532: SetPC(GetPC() - 1);
4533: return 0;
4534:
4535: case 0xF1: // no_op
4536: SetPC(GetPC() - 1);
4537: return 0;
4538:
4539: case 0xF2: // no_op
4540: SetPC(GetPC() - 1);
4541: return 0;
4542:
4543: case 0xF3: // no_op
4544: SetPC(GetPC() - 1);
4545: return 0;
4546:
4547: case 0xF4: // no_op
4548: SetPC(GetPC() - 1);
4549: return 0;
4550:
4551: case 0xF5: // no_op
4552: SetPC(GetPC() - 1);
4553: return 0;
4554:
4555: case 0xF6: // no_op
4556: SetPC(GetPC() - 1);
4557: return 0;
4558:
4559: case 0xF7: // no_op
4560: SetPC(GetPC() - 1);
4561: return 0;
4562:
4563: case 0xF8: // no_op
4564: SetPC(GetPC() - 1);
4565: return 0;
4566:
4567: case 0xF9: // ld_sp_ix
4568: SetSP(m_regIX);
4569: return 10;
4570:
4571: case 0xFA: // no_op
4572: SetPC(GetPC() - 1);
4573: return 0;
4574:
4575: case 0xFB: // no_op
4576: SetPC(GetPC() - 1);
4577: return 0;
4578:
4579: case 0xFC: // no_op
4580: SetPC(GetPC() - 1);
4581: return 0;
4582:
4583: case 0xFD: // no_op
4584: SetPC(GetPC() - 1);
4585: return 0;
4586:
4587: case 0xFE: // no_op
4588: SetPC(GetPC() - 1);
4589: return 0;
4590:
4591: case 0xFF: // no_op
4592: SetPC(GetPC() - 1);
4593: return 0;
4594:
4595: default:
4596: return 0;
4597: }
4598: }
4599:
4600: /* ***************************************************************************
4601: * ED prefixed opcodes
4602: * ***************************************************************************
4603: */
4604: int HandleED(int cCyclesArg) {
4605:
4606: const BYTE bOpcode = ImmedByte();
4607: int cCycles = cCyclesArg;
4608:
4609: m_regR++;
4610:
4611: switch (bOpcode)
4612: {
4613: case 0x00: // nop
4614: cCycles -= 0;
4615: break;
4616:
4617: case 0x01: // nop
4618: cCycles -= 0;
4619: break;
4620:
4621: case 0x02: // nop
4622: cCycles -= 0;
4623: break;
4624:
4625: case 0x03: // nop
4626: cCycles -= 0;
4627: break;
4628:
4629: case 0x04: // nop
4630: cCycles -= 0;
4631: break;
4632:
4633: case 0x05: // nop
4634: cCycles -= 0;
4635: break;
4636:
4637: case 0x06: // nop
4638: cCycles -= 0;
4639: break;
4640:
4641: case 0x07: // nop
4642: cCycles -= 0;
4643: break;
4644:
4645: case 0x08: // nop
4646: cCycles -= 0;
4647: break;
4648:
4649: case 0x09: // nop
4650: cCycles -= 0;
4651: break;
4652:
4653: case 0x0A: // nop
4654: cCycles -= 0;
4655: break;
4656:
4657: case 0x0B: // nop
4658: cCycles -= 0;
4659: break;
4660:
4661: case 0x0C: // nop
4662: cCycles -= 0;
4663: break;
4664:
4665: case 0x0D: // nop
4666: cCycles -= 0;
4667: break;
4668:
4669: case 0x0E: // nop
4670: cCycles -= 0;
4671: break;
4672:
4673: case 0x0F: // nop
4674: cCycles -= 0;
4675: break;
4676:
4677: case 0x10: // nop
4678: cCycles -= 0;
4679: break;
4680:
4681: case 0x11: // nop
4682: cCycles -= 0;
4683: break;
4684:
4685: case 0x12: // nop
4686: cCycles -= 0;
4687: break;
4688:
4689: case 0x13: // nop
4690: cCycles -= 0;
4691: break;
4692:
4693: case 0x14: // nop
4694: cCycles -= 0;
4695: break;
4696:
4697: case 0x15: // nop
4698: cCycles -= 0;
4699: break;
4700:
4701: case 0x16: // nop
4702: cCycles -= 0;
4703: break;
4704:
4705: case 0x17: // nop
4706: cCycles -= 0;
4707: break;
4708:
4709: case 0x18: // nop
4710: cCycles -= 0;
4711: break;
4712:
4713: case 0x19: // nop
4714: cCycles -= 0;
4715: break;
4716:
4717: case 0x1A: // nop
4718: cCycles -= 0;
4719: break;
4720:
4721: case 0x1B: // nop
4722: cCycles -= 0;
4723: break;
4724:
4725: case 0x1C: // nop
4726: cCycles -= 0;
4727: break;
4728:
4729: case 0x1D: // nop
4730: cCycles -= 0;
4731: break;
4732:
4733: case 0x1E: // nop
4734: cCycles -= 0;
4735: break;
4736:
4737: case 0x1F: // nop
4738: cCycles -= 0;
4739: break;
4740:
4741: case 0x20: // nop
4742: cCycles -= 0;
4743: break;
4744:
4745: case 0x21: // nop
4746: cCycles -= 0;
4747: break;
4748:
4749: case 0x22: // nop
4750: cCycles -= 0;
4751: break;
4752:
4753: case 0x23: // nop
4754: cCycles -= 0;
4755: break;
4756:
4757: case 0x24: // nop
4758: cCycles -= 0;
4759: break;
4760:
4761: case 0x25: // nop
4762: cCycles -= 0;
4763: break;
4764:
4765: case 0x26: // nop
4766: cCycles -= 0;
4767: break;
4768:
4769: case 0x27: // nop
4770: cCycles -= 0;
4771: break;
4772:
4773: case 0x28: // nop
4774: cCycles -= 0;
4775: break;
4776:
4777: case 0x29: // nop
4778: cCycles -= 0;
4779: break;
4780:
4781: case 0x2A: // nop
4782: cCycles -= 0;
4783: break;
4784:
4785: case 0x2B: // nop
4786: cCycles -= 0;
4787: break;
4788:
4789: case 0x2C: // nop
4790: cCycles -= 0;
4791: break;
4792:
4793: case 0x2D: // nop
4794: cCycles -= 0;
4795: break;
4796:
4797: case 0x2E: // nop
4798: cCycles -= 0;
4799: break;
4800:
4801: case 0x2F: // nop
4802: cCycles -= 0;
4803: break;
4804:
4805: case 0x30: // nop
4806: cCycles -= 0;
4807: break;
4808:
4809: case 0x31: // nop
4810: cCycles -= 0;
4811: break;
4812:
4813: case 0x32: // nop
4814: cCycles -= 0;
4815: break;
4816:
4817: case 0x33: // nop
4818: cCycles -= 0;
4819: break;
4820:
4821: case 0x34: // nop
4822: cCycles -= 0;
4823: break;
4824:
4825: case 0x35: // nop
4826: cCycles -= 0;
4827: break;
4828:
4829: case 0x36: // nop
4830: cCycles -= 0;
4831: break;
4832:
4833: case 0x37: // nop
4834: cCycles -= 0;
4835: break;
4836:
4837: case 0x38: // nop
4838: cCycles -= 0;
4839: break;
4840:
4841: case 0x39: // nop
4842: cCycles -= 0;
4843: break;
4844:
4845: case 0x3A: // nop
4846: cCycles -= 0;
4847: break;
4848:
4849: case 0x3B: // nop
4850: cCycles -= 0;
4851: break;
4852:
4853: case 0x3C: // nop
4854: cCycles -= 0;
4855: break;
4856:
4857: case 0x3D: // nop
4858: cCycles -= 0;
4859: break;
4860:
4861: case 0x3E: // nop
4862: cCycles -= 0;
4863: break;
4864:
4865: case 0x3F: // nop
4866: cCycles -= 0;
4867: break;
4868:
4869: case 0x40: // in_b_c
4870: cCycles -= 12;
4871: m_regB = In(m_regC);
4872: break;
4873:
4874: case 0x41: // out_c_b
4875: cCycles -= 12;
4876: Out(m_regC, m_regB);
4877: break;
4878:
4879: case 0x42: // sbc_hl_bc
4880: cCycles -= 15;
4881: m_regHL = Sbc_2(m_regHL, m_regBC);
4882: break;
4883:
4884: case 0x43: // ld_xword_bc
4885: cCycles -= 20;
4886: MemWriteWord(ImmedWord(), m_regBC);
4887: break;
4888:
4889: case 0x44: // neg
4890: cCycles -= 8;
4891: {
4892: BYTE b = m_regA;
4893: m_regA = 0;
4894: Sub_1(b);
4895: break;
4896: }
4897:
4898: case 0x45: // retn
4899: cCycles -= 8;
4900: m_iff1 = m_iff2;
4901: cCycles -= Ret0(TRUE);
4902: break;
4903:
4904: case 0x46: // im_0
4905: cCycles -= 8;
4906: m_nIM = 0;
4907: break;
4908:
4909: case 0x47: // ld_i_a
4910: cCycles -= 9;
4911: m_regI = m_regA;
4912: break;
4913:
4914: case 0x48: // in_c_c
4915: cCycles -= 12;
4916: m_regC = In(m_regC);
4917: break;
4918:
4919: case 0x49: // out_c_c
4920: cCycles -= 12;
4921: Out(m_regC, m_regC);
4922: break;
4923:
4924: case 0x4A: // adc_hl_bc
4925: cCycles -= 15;
4926: m_regHL = Adc_2(m_regHL, m_regBC);
4927: break;
4928:
4929: case 0x4B: // ld_bc_xword
4930: cCycles -= 20;
4931: m_regBC = MemReadWord(ImmedWord());
4932: break;
4933:
4934: case 0x4C: // neg
4935: cCycles -= 8;
4936: {
4937: BYTE b = m_regA;
4938: m_regA = 0;
4939: Sub_1(b);
4940: break;
4941: }
4942:
4943: case 0x4D: // reti
4944: cCycles -= 8;
4945: cCycles -= Ret0(TRUE);
4946: break;
4947:
4948: case 0x4E: // im_0
4949: cCycles -= 8;
4950: m_nIM = 0;
4951: break;
4952:
4953: case 0x4F: // ld_r_a
4954: cCycles -= 9;
4955: m_regR = m_regA;
4956: // m_regR2 = m_regA;
4957: break;
4958:
4959: case 0x50: // in_d_c
4960: cCycles -= 12;
4961: m_regD = In(m_regC);
4962: break;
4963:
4964: case 0x51: // out_c_d
4965: cCycles -= 12;
4966: Out(m_regC, m_regD);
4967: break;
4968:
4969: case 0x52: // sbc_hl_de
4970: cCycles -= 15;
4971: m_regHL = Sbc_2(m_regHL, m_regDE);
4972: break;
4973:
4974: case 0x53: // ld_xword_de
4975: cCycles -= 20;
4976: MemWriteWord(ImmedWord(), m_regDE);
4977: break;
4978:
4979: case 0x54: // neg
4980: cCycles -= 8;
4981: {
4982: BYTE b = m_regA;
4983: m_regA = 0;
4984: Sub_1(b);
4985: break;
4986: }
4987:
4988: case 0x55: // retn
4989: cCycles -= 8;
4990: m_iff1 = m_iff2;
4991: cCycles -= Ret0(TRUE);
4992: break;
4993:
4994: case 0x56: // im_1
4995: cCycles -= 8;
4996: m_nIM = 1;
4997: break;
4998:
4999: case 0x57: // ld_a_i
5000: cCycles -= 9;
5001: m_regA = m_regI;
5002: m_regF = (m_regF & C_FLAG)| ZSTable[m_regI] | (m_iff2 << 2);
5003: break;
5004:
5005: case 0x58: // in_e_c
5006: cCycles -= 12;
5007: m_regE = In(m_regC);
5008: break;
5009:
5010: case 0x59: // out_c_e
5011: cCycles -= 12;
5012: Out(m_regC, m_regE);
5013: break;
5014:
5015: case 0x5A: // adc_hl_de
5016: cCycles -= 15;
5017: m_regHL = Adc_2(m_regHL, m_regDE);
5018: break;
5019:
5020: case 0x5B: // ld_de_xword
5021: cCycles -= 20;
5022: m_regDE = MemReadWord(ImmedWord());
5023: break;
5024:
5025: case 0x5C: // neg
5026: cCycles -= 8;
5027: {
5028: BYTE b = m_regA;
5029: m_regA = 0;
5030: Sub_1(b);
5031: break;
5032: }
5033:
5034: case 0x5D: // reti
5035: cCycles -= 8;
5036: cCycles -= Ret0(TRUE);
5037: break;
5038:
5039: case 0x5E: // im_2
5040: cCycles -= 8;
5041: m_nIM = 2;
5042: break;
5043:
5044: case 0x5F: // ld_a_r
5045: cCycles -= 9;
5046: m_regA = (m_regR & 0x7F); /////////////////////////////////////// | (m_regR2 & 0x80);
5047: m_regF = (m_regF & C_FLAG) | ZSTable[m_regA] | (m_iff2 << 2);
5048: break;
5049:
5050: case 0x60: // in_h_c
5051: cCycles -= 12;
5052: m_regH = In(m_regC);
5053: break;
5054:
5055: case 0x61: // out_c_h
5056: cCycles -= 12;
5057: Out(m_regC, m_regH);
5058: break;
5059:
5060: case 0x62: // sbc_hl_hl
5061: cCycles -= 15;
5062: m_regHL = Sbc_2(m_regHL, m_regHL);
5063: break;
5064:
5065: case 0x63: // ld_xword_hl
5066: cCycles -= 20;
5067: MemWriteWord(ImmedWord(), m_regHL);
5068: break;
5069:
5070: case 0x64: // neg
5071: cCycles -= 8;
5072: {
5073: BYTE b = m_regA;
5074: m_regA = 0;
5075: Sub_1(b);
5076: break;
5077: }
5078:
5079: case 0x65: // retn
5080: cCycles -= 8;
5081: m_iff1 = m_iff2;
5082: cCycles -= Ret0(TRUE);
5083: break;
5084:
5085: case 0x66: // im_0
5086: cCycles -= 8;
5087: m_nIM = 0;
5088: break;
5089:
5090: case 0x67: // rrd
5091: cCycles -= 18;
5092: {
5093: BYTE i = MemReadByte(m_regHL);
5094: MemWriteByte(m_regHL, (i>>4) | (m_regA << 4));
5095: m_regA = (m_regA & 0xF0) | (i&0x0F);
5096: m_regF =(m_regF&C_FLAG)|ZSPTable[m_regA];
5097: break;
5098: }
5099:
5100: case 0x68: // in_l_c
5101: cCycles -= 12;
5102: m_regL = In(m_regC);
5103: break;
5104:
5105: case 0x69: // out_c_l
5106: cCycles -= 12;
5107: Out(m_regC, m_regL);
5108: break;
5109:
5110: case 0x6A: // adc_hl_hl
5111: cCycles -= 15;
5112: m_regHL = Adc_2(m_regHL, m_regHL);
5113: break;
5114:
5115: case 0x6B: // ld_hl_xword
5116: cCycles -= 20;
5117: m_regHL = MemReadWord(ImmedWord());
5118: break;
5119:
5120: case 0x6C: // neg
5121: cCycles -= 8;
5122: {
5123: BYTE b = m_regA;
5124: m_regA = 0;
5125: Sub_1(b);
5126: break;
5127: }
5128:
5129: case 0x6D: // reti
5130: cCycles -= 8;
5131: cCycles -= Ret0(TRUE);
5132: break;
5133:
5134: case 0x6E: // im_0
5135: cCycles -= 8;
5136: m_nIM = 0;
5137: break;
5138:
5139: case 0x6F: // rld
5140: cCycles -= 18;
5141: {
5142: BYTE i;
5143: i=MemReadByte(m_regHL);
5144: MemWriteByte(m_regHL,(i<<4)|(m_regA&0x0F));
5145: m_regA=(m_regA&0xF0)|(i>>4);
5146: m_regF=(m_regF&C_FLAG)|ZSPTable[m_regA];
5147: break;
5148: }
5149:
5150: case 0x70: // in_0_c
5151: cCycles -= 12;
5152: In(m_regC);
5153: break;
5154:
5155: case 0x71: // out_c_0
5156: cCycles -= 12;
5157: Out(m_regC, 0);
5158: break;
5159:
5160: case 0x72: // sbc_hl_sp
5161: cCycles -= 15;
5162: m_regHL = Sbc_2(m_regHL, GetSP());
5163: break;
5164:
5165: case 0x73: // ld_xword_sp
5166: cCycles -= 20;
5167: MemWriteWord(ImmedWord(), GetSP());
5168: break;
5169:
5170: case 0x74: // neg
5171: cCycles -= 8;
5172: {
5173: BYTE b = m_regA;
5174: m_regA = 0;
5175: Sub_1(b);
5176: break;
5177: }
5178:
5179: case 0x75: // retn
5180: cCycles -= 8;
5181: m_iff1 = m_iff2;
5182: cCycles -= Ret0(TRUE);
5183: break;
5184:
5185: case 0x76: // im_1
5186: cCycles -= 8;
5187: m_nIM = 1;
5188: break;
5189:
5190: case 0x77: // nop
5191: cCycles -= 0;
5192: break;
5193:
5194: case 0x78: // in_a_c
5195: cCycles -= 12;
5196: m_regA = In(m_regC);
5197: break;
5198:
5199: case 0x79: // out_c_a
5200: cCycles -= 12;
5201: Out(m_regC, m_regA);
5202: break;
5203:
5204: case 0x7A: // adc_hl_sp
5205: cCycles -= 15;
5206: m_regHL = Adc_2(m_regHL, GetSP());
5207: break;
5208:
5209: case 0x7B: // ld_sp_xword
5210: cCycles -= 20;
5211: SetSP(MemReadWord(ImmedWord()));
5212: break;
5213:
5214: case 0x7C: // neg
5215: cCycles -= 8;
5216: {
5217: BYTE b = m_regA;
5218: m_regA = 0;
5219: Sub_1(b);
5220: break;
5221: }
5222:
5223: case 0x7D: // reti
5224: cCycles -= 8;
5225: cCycles -= Ret0(TRUE);
5226: break;
5227:
5228: case 0x7E: // im_2
5229: cCycles -= 8;
5230: m_nIM = 2;
5231: break;
5232:
5233: case 0x7F: // nop
5234: cCycles -= 0;
5235: break;
5236:
5237: case 0x80: // nop
5238: cCycles -= 0;
5239: break;
5240:
5241: case 0x81: // nop
5242: cCycles -= 0;
5243: break;
5244:
5245: case 0x82: // nop
5246: cCycles -= 0;
5247: break;
5248:
5249: case 0x83: // nop
5250: cCycles -= 0;
5251: break;
5252:
5253: case 0x84: // nop
5254: cCycles -= 0;
5255: break;
5256:
5257: case 0x85: // nop
5258: cCycles -= 0;
5259: break;
5260:
5261: case 0x86: // nop
5262: cCycles -= 0;
5263: break;
5264:
5265: case 0x87: // nop
5266: cCycles -= 0;
5267: break;
5268:
5269: case 0x88: // nop
5270: cCycles -= 0;
5271: break;
5272:
5273: case 0x89: // nop
5274: cCycles -= 0;
5275: break;
5276:
5277: case 0x8A: // nop
5278: cCycles -= 0;
5279: break;
5280:
5281: case 0x8B: // nop
5282: cCycles -= 0;
5283: break;
5284:
5285: case 0x8C: // nop
5286: cCycles -= 0;
5287: break;
5288:
5289: case 0x8D: // nop
5290: cCycles -= 0;
5291: break;
5292:
5293: case 0x8E: // nop
5294: cCycles -= 0;
5295: break;
5296:
5297: case 0x8F: // nop
5298: cCycles -= 0;
5299: break;
5300:
5301: case 0x90: // nop
5302: cCycles -= 0;
5303: break;
5304:
5305: case 0x91: // nop
5306: cCycles -= 0;
5307: break;
5308:
5309: case 0x92: // nop
5310: cCycles -= 0;
5311: break;
5312:
5313: case 0x93: // nop
5314: cCycles -= 0;
5315: break;
5316:
5317: case 0x94: // nop
5318: cCycles -= 0;
5319: break;
5320:
5321: case 0x95: // nop
5322: cCycles -= 0;
5323: break;
5324:
5325: case 0x96: // nop
5326: cCycles -= 0;
5327: break;
5328:
5329: case 0x97: // nop
5330: cCycles -= 0;
5331: break;
5332:
5333: case 0x98: // nop
5334: cCycles -= 0;
5335: break;
5336:
5337: case 0x99: // nop
5338: cCycles -= 0;
5339: break;
5340:
5341: case 0x9A: // nop
5342: cCycles -= 0;
5343: break;
5344:
5345: case 0x9B: // nop
5346: cCycles -= 0;
5347: break;
5348:
5349: case 0x9C: // nop
5350: cCycles -= 0;
5351: break;
5352:
5353: case 0x9D: // nop
5354: cCycles -= 0;
5355: break;
5356:
5357: case 0x9E: // nop
5358: cCycles -= 0;
5359: break;
5360:
5361: case 0x9F: // nop
5362: cCycles -= 0;
5363: break;
5364:
5365: case 0xA0: // ldi
5366: cCycles -= 16;
5367: {
5368: MemWriteByte(m_regDE++, MemReadByte(m_regHL++));
5369: m_regBC--;
5370: m_regF = (m_regF & 0xE9) | (m_regBC ? V_FLAG : 0);
5371: break;
5372: }
5373:
5374: case 0xA1: // cpi
5375: cCycles -= 16;
5376: {
5377: BYTE i,j;
5378: i=MemReadByte(m_regHL);
5379: j=m_regA-i;
5380: ++m_regHL;
5381: --m_regBC;
5382: m_regF=(m_regF&C_FLAG)|ZSTable[j]|
5383: ((m_regA^i^j)&H_FLAG)|(m_regBC? V_FLAG:0)|N_FLAG;
5384: break;
5385: }
5386:
5387: case 0xA2: // ini
5388: cCycles -= 16;
5389: {
5390: MemWriteByte(m_regHL,In(m_regC));
5391: ++m_regHL;
5392: --m_regB;
5393: m_regF=(m_regB)? N_FLAG:(N_FLAG|Z_FLAG);
5394: break;
5395: }
5396:
5397: case 0xA3: // outi
5398: cCycles -= 16;
5399: {
5400: Out(m_regC, MemReadByte(m_regHL));
5401: ++m_regHL;
5402: --m_regB;
5403: m_regF=(m_regB)? N_FLAG:(Z_FLAG|N_FLAG);
5404: break;
5405: }
5406:
5407: case 0xA4: // nop
5408: cCycles -= 0;
5409: break;
5410:
5411: case 0xA5: // nop
5412: cCycles -= 0;
5413: break;
5414:
5415: case 0xA6: // nop
5416: cCycles -= 0;
5417: break;
5418:
5419: case 0xA7: // nop
5420: cCycles -= 0;
5421: break;
5422:
5423: case 0xA8: // ldd
5424: cCycles -= 16;
5425: {
5426: MemWriteByte(m_regDE,MemReadByte(m_regHL));
5427: --m_regDE;
5428: --m_regHL;
5429: --m_regBC;
5430: m_regF=(m_regF&0xE9)|(m_regBC? V_FLAG:0);
5431: break;
5432: }
5433:
5434: case 0xA9: // cpd
5435: cCycles -= 16;
5436: {
5437: BYTE i,j;
5438: i=MemReadByte(m_regHL);
5439: j=m_regA-i;
5440: --m_regHL;
5441: --m_regBC;
5442: m_regF=(m_regF&C_FLAG)|ZSTable[j]|
5443: ((m_regA^i^j)&H_FLAG)|(m_regBC? V_FLAG:0)|N_FLAG;
5444: break;
5445: }
5446:
5447: case 0xAA: // ind
5448: cCycles -= 16;
5449: {
5450: MemWriteByte(m_regHL,In(m_regC));
5451: --m_regHL;
5452: --m_regB;
5453: m_regF=(m_regB)? N_FLAG:(N_FLAG|Z_FLAG);
5454: break;
5455: }
5456:
5457: case 0xAB: // outd
5458: cCycles -= 16;
5459: {
5460: Out (m_regC,MemReadByte(m_regHL));
5461: --m_regHL;
5462: --m_regB;
5463: m_regF=(m_regB)? N_FLAG:(Z_FLAG|N_FLAG);
5464: break;
5465: }
5466:
5467: case 0xAC: // nop
5468: cCycles -= 0;
5469: break;
5470:
5471: case 0xAD: // nop
5472: cCycles -= 0;
5473: break;
5474:
5475: case 0xAE: // nop
5476: cCycles -= 0;
5477: break;
5478:
5479: case 0xAF: // nop
5480: cCycles -= 0;
5481: break;
5482:
5483: case 0xB0: // ldir
5484: cCycles -= 0;
5485: {
5486: m_regR -= 2;
5487:
5488: /*
5489: if (m_rgfMemDesc[m_regHL] & MF_READ_DIRECT &&
5490: m_rgfMemDesc[m_regDE] & MF_WRITE_DIRECT)
5491: {
5492: do
5493: {
5494: m_regR += 2;
5495: m_rgbMemory[m_regDE++] = m_rgbMemory[m_regHL++];
5496: cCycles -= 21;
5497: }
5498: while (--m_regBC); // && cCycles>0);
5499:
5500: m_regF=(m_regF&0xE9)|(m_regBC? V_FLAG:0);
5501:
5502: if (m_regBC)
5503: // m_regPC -= 2;
5504: AdjustPC(-2);
5505: else
5506: cCycles += 5;
5507: }
5508: else
5509: */
5510: {
5511: do
5512: {
5513: m_regR += 2;
5514: MemWriteByte(m_regDE++, MemReadByte(m_regHL++));
5515: cCycles -= 21;
5516: }
5517: while (--m_regBC); // && cCycles>0);
5518:
5519: m_regF=(m_regF&0xE9)|(m_regBC? V_FLAG:0);
5520:
5521: if (m_regBC)
5522: // m_regPC -= 2;
5523: AdjustPC(-2);
5524: else
5525: cCycles += 5;
5526: }
5527:
5528: break;
5529: }
5530:
5531: case 0xB1: // cpir
5532: cCycles -= 0;
5533: {
5534: BYTE i,j;
5535: m_regR-=2;
5536: do
5537: {
5538: m_regR+=2;
5539: i=MemReadByte(m_regHL);
5540: j=m_regA-i;
5541: ++m_regHL;
5542: --m_regBC;
5543: cCycles-=21;
5544: }
5545: while (m_regBC && j && cCycles>0);
5546: m_regF=(m_regF&C_FLAG)|ZSTable[j]|
5547: ((m_regA^i^j)&H_FLAG)|(m_regBC? V_FLAG:0)|N_FLAG;
5548: if (m_regBC && j) AdjustPC(-2); // m_regPC-=2;
5549: else cCycles+=5;
5550: break;
5551: }
5552:
5553: case 0xB2: // inir
5554: cCycles -= 0;
5555: {
5556: m_regR-=2;
5557: do
5558: {
5559: m_regR+=2;
5560: MemWriteByte(m_regHL,In(m_regC));
5561: ++m_regHL;
5562: --m_regB;
5563: cCycles-=21;
5564: }
5565: while (m_regB && cCycles>0);
5566: m_regF=(m_regB)? N_FLAG:(N_FLAG|Z_FLAG);
5567: if (m_regB) AdjustPC(-2); // m_regPC-=2;
5568: else cCycles+=5;
5569: break;
5570: }
5571:
5572: case 0xB3: // otir
5573: cCycles -= 0;
5574: {
5575: m_regR-=2;
5576: do
5577: {
5578: m_regR+=2;
5579: Out (m_regC,MemReadByte(m_regHL));
5580: ++m_regHL;
5581: --m_regB;
5582: cCycles-=21;
5583: }
5584: while (m_regB && cCycles>0);
5585: m_regF=(m_regB)? N_FLAG:(Z_FLAG|N_FLAG);
5586: if (m_regB) AdjustPC(-2); // m_regPC-=2;
5587: else cCycles+=5;
5588: }
5589: break;
5590:
5591: case 0xB4: // nop
5592: cCycles -= 0;
5593: break;
5594:
5595: case 0xB5: // nop
5596: cCycles -= 0;
5597: break;
5598:
5599: case 0xB6: // nop
5600: cCycles -= 0;
5601: break;
5602:
5603: case 0xB7: // nop
5604: cCycles -= 0;
5605: break;
5606:
5607: case 0xB8: // lddr
5608: cCycles -= 0;
5609: {
5610: m_regR-=2;
5611: do
5612: {
5613: m_regR+=2;
5614: MemWriteByte(m_regDE,MemReadByte(m_regHL));
5615: --m_regDE;
5616: --m_regHL;
5617: --m_regBC;
5618: cCycles-=21;
5619: }
5620: while (m_regBC);
5621: m_regF=(m_regF&0xE9)|(m_regBC? V_FLAG:0);
5622: if (m_regBC) AdjustPC(-2); // m_regPC-=2;
5623: else
5624: cCycles+=5;
5625: break;
5626: }
5627:
5628: case 0xB9: // cpdr
5629: cCycles -= 0;
5630: {
5631: BYTE i,j;
5632: m_regR-=2;
5633: do
5634: {
5635: m_regR+=2;
5636: i=MemReadByte(m_regHL);
5637: j=m_regA-i;
5638: --m_regHL;
5639: --m_regBC;
5640: cCycles-=21;
5641: }
5642: while (m_regBC && j && cCycles>0);
5643: m_regF=(m_regF&C_FLAG)|ZSTable[j]|
5644: ((m_regA^i^j)&H_FLAG)|(m_regBC? V_FLAG:0)|N_FLAG;
5645: if (m_regBC && j) AdjustPC(-2); // m_regPC-=2;
5646: else cCycles+=5;
5647: break;
5648: }
5649:
5650: case 0xBA: // indr
5651: cCycles -= 0;
5652: {
5653: m_regR-=2;
5654: do
5655: {
5656: m_regR+=2;
5657: MemWriteByte(m_regHL,In(m_regC));
5658: --m_regHL;
5659: --m_regB;
5660: cCycles-=21;
5661: }
5662: while (m_regB && cCycles>0);
5663: m_regF=(m_regB)? N_FLAG:(N_FLAG|Z_FLAG);
5664: if (m_regB) AdjustPC(-2); // m_regPC-=2;
5665: else cCycles+=5;
5666: break;
5667: }
5668:
5669: case 0xBB: // otdr
5670: cCycles -= 0;
5671: {
5672: m_regR-=2;
5673: do
5674: {
5675: m_regR+=2;
5676: Out (m_regC,MemReadByte(m_regHL));
5677: --m_regHL;
5678: --m_regB;
5679: cCycles-=21;
5680: }
5681: while (m_regB && cCycles>0);
5682: m_regF=(m_regB)? N_FLAG:(Z_FLAG|N_FLAG);
5683: if (m_regB) AdjustPC(-2); // m_regPC-=2;
5684: else cCycles+=5;
5685: break;
5686: }
5687:
5688: case 0xBC: // nop
5689: cCycles -= 0;
5690: break;
5691:
5692: case 0xBD: // nop
5693: cCycles -= 0;
5694: break;
5695:
5696: case 0xBE: // nop
5697: cCycles -= 0;
5698: break;
5699:
5700: case 0xBF: // nop
5701: cCycles -= 0;
5702: break;
5703:
5704: case 0xC0: // nop
5705: cCycles -= 0;
5706: break;
5707:
5708: case 0xC1: // nop
5709: cCycles -= 0;
5710: break;
5711:
5712: case 0xC2: // nop
5713: cCycles -= 0;
5714: break;
5715:
5716: case 0xC3: // nop
5717: cCycles -= 0;
5718: break;
5719:
5720: case 0xC4: // nop
5721: cCycles -= 0;
5722: break;
5723:
5724: case 0xC5: // nop
5725: cCycles -= 0;
5726: break;
5727:
5728: case 0xC6: // nop
5729: cCycles -= 0;
5730: break;
5731:
5732: case 0xC7: // nop
5733: cCycles -= 0;
5734: break;
5735:
5736: case 0xC8: // nop
5737: cCycles -= 0;
5738: break;
5739:
5740: case 0xC9: // nop
5741: cCycles -= 0;
5742: break;
5743:
5744: case 0xCA: // nop
5745: cCycles -= 0;
5746: break;
5747:
5748: case 0xCB: // nop
5749: cCycles -= 0;
5750: break;
5751:
5752: case 0xCC: // nop
5753: cCycles -= 0;
5754: break;
5755:
5756: case 0xCD: // nop
5757: cCycles -= 0;
5758: break;
5759:
5760: case 0xCE: // nop
5761: cCycles -= 0;
5762: break;
5763:
5764: case 0xCF: // nop
5765: cCycles -= 0;
5766: break;
5767:
5768: case 0xD0: // nop
5769: cCycles -= 0;
5770: break;
5771:
5772: case 0xD1: // nop
5773: cCycles -= 0;
5774: break;
5775:
5776: case 0xD2: // nop
5777: cCycles -= 0;
5778: break;
5779:
5780: case 0xD3: // nop
5781: cCycles -= 0;
5782: break;
5783:
5784: case 0xD4: // nop
5785: cCycles -= 0;
5786: break;
5787:
5788: case 0xD5: // nop
5789: cCycles -= 0;
5790: break;
5791:
5792: case 0xD6: // nop
5793: cCycles -= 0;
5794: break;
5795:
5796: case 0xD7: // nop
5797: cCycles -= 0;
5798: break;
5799:
5800: case 0xD8: // nop
5801: cCycles -= 0;
5802: break;
5803:
5804: case 0xD9: // nop
5805: cCycles -= 0;
5806: break;
5807:
5808: case 0xDA: // nop
5809: cCycles -= 0;
5810: break;
5811:
5812: case 0xDB: // nop
5813: cCycles -= 0;
5814: break;
5815:
5816: case 0xDC: // nop
5817: cCycles -= 0;
5818: break;
5819:
5820: case 0xDD: // nop
5821: cCycles -= 0;
5822: break;
5823:
5824: case 0xDE: // nop
5825: cCycles -= 0;
5826: break;
5827:
5828: case 0xDF: // nop
5829: cCycles -= 0;
5830: break;
5831:
5832: case 0xE0: // nop
5833: cCycles -= 0;
5834: break;
5835:
5836: case 0xE1: // nop
5837: cCycles -= 0;
5838: break;
5839:
5840: case 0xE2: // nop
5841: cCycles -= 0;
5842: break;
5843:
5844: case 0xE3: // nop
5845: cCycles -= 0;
5846: break;
5847:
5848: case 0xE4: // nop
5849: cCycles -= 0;
5850: break;
5851:
5852: case 0xE5: // nop
5853: cCycles -= 0;
5854: break;
5855:
5856: case 0xE6: // nop
5857: cCycles -= 0;
5858: break;
5859:
5860: case 0xE7: // nop
5861: cCycles -= 0;
5862: break;
5863:
5864: case 0xE8: // nop
5865: cCycles -= 0;
5866: break;
5867:
5868: case 0xE9: // nop
5869: cCycles -= 0;
5870: break;
5871:
5872: case 0xEA: // nop
5873: cCycles -= 0;
5874: break;
5875:
5876: case 0xEB: // nop
5877: cCycles -= 0;
5878: break;
5879:
5880: case 0xEC: // nop
5881: cCycles -= 0;
5882: break;
5883:
5884: case 0xED: // nop
5885: cCycles -= 0;
5886: break;
5887:
5888: case 0xEE: // nop
5889: cCycles -= 0;
5890: break;
5891:
5892: case 0xEF: // nop
5893: cCycles -= 0;
5894: break;
5895:
5896: case 0xF0: // nop
5897: cCycles -= 0;
5898: break;
5899:
5900: case 0xF1: // nop
5901: cCycles -= 0;
5902: break;
5903:
5904: case 0xF2: // nop
5905: cCycles -= 0;
5906: break;
5907:
5908: case 0xF3: // nop
5909: cCycles -= 0;
5910: break;
5911:
5912: case 0xF4: // nop
5913: cCycles -= 0;
5914: break;
5915:
5916: case 0xF5: // nop
5917: cCycles -= 0;
5918: break;
5919:
5920: case 0xF6: // nop
5921: cCycles -= 0;
5922: break;
5923:
5924: case 0xF7: // nop
5925: cCycles -= 0;
5926: break;
5927:
5928: case 0xF8: // nop
5929: cCycles -= 0;
5930: break;
5931:
5932: case 0xF9: // nop
5933: cCycles -= 0;
5934: break;
5935:
5936: case 0xFA: // nop
5937: cCycles -= 0;
5938: break;
5939:
5940: case 0xFB: // nop
5941: cCycles -= 0;
5942: break;
5943:
5944: case 0xFC: // nop
5945: cCycles -= 0;
5946: break;
5947:
5948: case 0xFD: // nop
5949: cCycles -= 0;
5950: break;
5951:
5952: case 0xFE: // patch
5953: cCycles -= 0;
5954: break;
5955:
5956: case 0xFF: // nop
5957: cCycles -= 0;
5958: break;
5959:
5960: default:
5961: _ASSERT(FALSE);
5962: break;
5963: }
5964:
5965: return (cCyclesArg - cCycles);
5966: }
5967:
5968: int Ei() {
5969: /* fprintf ( stderr, "Enable Interrupt\n" ); */
5970: m_iff2 = 1;
5971:
5972: if (m_iff1 != 0)
5973: return 0;
5974:
5975: m_iff1 = 1;
5976:
5977: return(0);
5978: }
5979:
5980: void Di() {
5981: /* fprintf ( stderr, "Disable Interrupt\n" ); */
5982: m_iff1 = 0;
5983: m_iff2 = 0;
5984: }
5985:
5986: /* ***************************************************************************
5987: * FD prefixed opcodes
5988: * ***************************************************************************
5989: */
5990: /* inline */ WORD IndirectIY() {
5991: return m_regIY + (signed char)ImmedByte();
5992: }
5993:
5994: int HandleFD() {
5995:
5996: WORD wAddr;
5997: WORD wTemp;
5998: const BYTE bOpcode = ImmedByte();
5999:
6000: m_regR++;
6001:
6002: switch (bOpcode)
6003: {
6004: case 0x00: // no_op
6005: SetPC(GetPC() - 1);
6006: return 0;
6007:
6008: case 0x01: // no_op
6009: SetPC(GetPC() - 1);
6010: return 0;
6011:
6012: case 0x02: // no_op
6013: SetPC(GetPC() - 1);
6014: return 0;
6015:
6016: case 0x03: // no_op
6017: SetPC(GetPC() - 1);
6018: return 0;
6019:
6020: case 0x04: // no_op
6021: SetPC(GetPC() - 1);
6022: return 0;
6023:
6024: case 0x05: // no_op
6025: SetPC(GetPC() - 1);
6026: return 0;
6027:
6028: case 0x06: // no_op
6029: SetPC(GetPC() - 1);
6030: return 0;
6031:
6032: case 0x07: // no_op
6033: SetPC(GetPC() - 1);
6034: return 0;
6035:
6036: case 0x08: // no_op
6037: SetPC(GetPC() - 1);
6038: return 0;
6039:
6040: case 0x09: // add_iy_bc
6041: m_regIY = Add_2(m_regIY, m_regBC);
6042: return 15;
6043:
6044: case 0x0A: // no_op
6045: SetPC(GetPC() - 1);
6046: return 0;
6047:
6048: case 0x0B: // no_op
6049: SetPC(GetPC() - 1);
6050: return 0;
6051:
6052: case 0x0C: // no_op
6053: SetPC(GetPC() - 1);
6054: return 0;
6055:
6056: case 0x0D: // no_op
6057: SetPC(GetPC() - 1);
6058: return 0;
6059:
6060: case 0x0E: // no_op
6061: SetPC(GetPC() - 1);
6062: return 0;
6063:
6064: case 0x0F: // no_op
6065: SetPC(GetPC() - 1);
6066: return 0;
6067:
6068: case 0x10: // no_op
6069: SetPC(GetPC() - 1);
6070: return 0;
6071:
6072: case 0x11: // no_op
6073: SetPC(GetPC() - 1);
6074: return 0;
6075:
6076: case 0x12: // no_op
6077: SetPC(GetPC() - 1);
6078: return 0;
6079:
6080: case 0x13: // no_op
6081: SetPC(GetPC() - 1);
6082: return 0;
6083:
6084: case 0x14: // no_op
6085: SetPC(GetPC() - 1);
6086: return 0;
6087:
6088: case 0x15: // no_op
6089: SetPC(GetPC() - 1);
6090: return 0;
6091:
6092: case 0x16: // no_op
6093: SetPC(GetPC() - 1);
6094: return 0;
6095:
6096: case 0x17: // no_op
6097: SetPC(GetPC() - 1);
6098: return 0;
6099:
6100: case 0x18: // no_op
6101: SetPC(GetPC() - 1);
6102: return 0;
6103:
6104: case 0x19: // add_iy_de
6105: m_regIY = Add_2(m_regIY, m_regDE);
6106: return 15;
6107:
6108: case 0x1A: // no_op
6109: SetPC(GetPC() - 1);
6110: return 0;
6111:
6112: case 0x1B: // no_op
6113: SetPC(GetPC() - 1);
6114: return 0;
6115:
6116: case 0x1C: // no_op
6117: SetPC(GetPC() - 1);
6118: return 0;
6119:
6120: case 0x1D: // no_op
6121: SetPC(GetPC() - 1);
6122: return 0;
6123:
6124: case 0x1E: // no_op
6125: SetPC(GetPC() - 1);
6126: return 0;
6127:
6128: case 0x1F: // no_op
6129: SetPC(GetPC() - 1);
6130: return 0;
6131:
6132: case 0x20: // no_op
6133: SetPC(GetPC() - 1);
6134: return 0;
6135:
6136: case 0x21: // ld_iy_word
6137: m_regIY = ImmedWord();
6138: return 14;
6139:
6140: case 0x22: // ld_xword_iy
6141: MemWriteWord(ImmedWord(), m_regIY);
6142: return 20;
6143:
6144: case 0x23: // inc_iy
6145: m_regIY++;
6146: return 10;
6147:
6148: case 0x24: // inc_iyh
6149: m_regIYh = Inc(m_regIYh);
6150: return 9;
6151:
6152: case 0x25: // dec_iyh
6153: m_regIYh = Dec(m_regIYh);
6154: return 9;
6155:
6156: case 0x26: // ld_iyh_byte
6157: m_regIYh = ImmedByte();
6158: return 9;
6159:
6160: case 0x27: // no_op
6161: SetPC(GetPC() - 1);
6162: return 0;
6163:
6164: case 0x28: // no_op
6165: SetPC(GetPC() - 1);
6166: return 0;
6167:
6168: case 0x29: // add_iy_iy
6169: m_regIY = Add_2(m_regIY, m_regIY);
6170: return 15;
6171:
6172: case 0x2A: // ld_iy_xword
6173: m_regIY = MemReadWord(ImmedWord());
6174: return 20;
6175:
6176: case 0x2B: // dec_iy
6177: m_regIY--;
6178: return 10;
6179:
6180: case 0x2C: // inc_iyl
6181: m_regIYl = Inc(m_regIYl);
6182: return 9;
6183:
6184: case 0x2D: // dec_iyl
6185: m_regIYl = Dec(m_regIYl);
6186: return 9;
6187:
6188: case 0x2E: // ld_iyl_byte
6189: m_regIYl = ImmedByte();
6190: return 9;
6191:
6192: case 0x2F: // no_op
6193: SetPC(GetPC() - 1);
6194: return 0;
6195:
6196: case 0x30: // no_op
6197: SetPC(GetPC() - 1);
6198: return 0;
6199:
6200: case 0x31: // no_op
6201: SetPC(GetPC() - 1);
6202: return 0;
6203:
6204: case 0x32: // no_op
6205: SetPC(GetPC() - 1);
6206: return 0;
6207:
6208: case 0x33: // no_op
6209: SetPC(GetPC() - 1);
6210: return 0;
6211:
6212: case 0x34: // inc_xiy
6213: wAddr = IndirectIY();
6214: MemWriteByte(wAddr, Inc(MemReadByte(wAddr)));
6215: return 23;
6216:
6217: case 0x35: // dec_xiy
6218: wAddr = IndirectIY();
6219: MemWriteByte(wAddr, Dec(MemReadByte(wAddr)));
6220: return 23;
6221:
6222: case 0x36: // ld_xiy_byte
6223: wAddr = IndirectIY();
6224: MemWriteByte(wAddr, ImmedByte());
6225: return 19;
6226:
6227: case 0x37: // no_op
6228: SetPC(GetPC() - 1);
6229: return 0;
6230:
6231: case 0x38: // no_op
6232: SetPC(GetPC() - 1);
6233: return 0;
6234:
6235: case 0x39: // add_iy_sp
6236: m_regIY = Add_2(m_regIY, GetSP());
6237: return 15;
6238:
6239: case 0x3A: // no_op
6240: SetPC(GetPC() - 1);
6241: return 0;
6242:
6243: case 0x3B: // no_op
6244: SetPC(GetPC() - 1);
6245: return 0;
6246:
6247: case 0x3C: // no_op
6248: SetPC(GetPC() - 1);
6249: return 0;
6250:
6251: case 0x3D: // no_op
6252: SetPC(GetPC() - 1);
6253: return 0;
6254:
6255: case 0x3E: // no_op
6256: SetPC(GetPC() - 1);
6257: return 0;
6258:
6259: case 0x3F: // no_op
6260: SetPC(GetPC() - 1);
6261: return 0;
6262:
6263: case 0x40: // no_op
6264: SetPC(GetPC() - 1);
6265: return 0;
6266:
6267: case 0x41: // no_op
6268: SetPC(GetPC() - 1);
6269: return 0;
6270:
6271: case 0x42: // no_op
6272: SetPC(GetPC() - 1);
6273: return 0;
6274:
6275: case 0x43: // no_op
6276: SetPC(GetPC() - 1);
6277: return 0;
6278:
6279: case 0x44: // ld_b_iyh
6280: m_regB = m_regIYh;
6281: return 9;
6282:
6283: case 0x45: // ld_b_iyl
6284: m_regB = m_regIYl;
6285: return 9;
6286:
6287: case 0x46: // ld_b_xiy
6288: m_regB = MemReadByte(IndirectIY());
6289: return 19;
6290:
6291: case 0x47: // no_op
6292: SetPC(GetPC() - 1);
6293: return 0;
6294:
6295: case 0x48: // no_op
6296: SetPC(GetPC() - 1);
6297: return 0;
6298:
6299: case 0x49: // no_op
6300: SetPC(GetPC() - 1);
6301: return 0;
6302:
6303: case 0x4A: // no_op
6304: SetPC(GetPC() - 1);
6305: return 0;
6306:
6307: case 0x4B: // no_op
6308: SetPC(GetPC() - 1);
6309: return 0;
6310:
6311: case 0x4C: // ld_c_iyh
6312: m_regC = m_regIYh;
6313: return 9;
6314:
6315: case 0x4D: // ld_c_iyl
6316: m_regC = m_regIYl;
6317: return 9;
6318:
6319: case 0x4E: // ld_c_xiy
6320: m_regC = MemReadByte(IndirectIY());
6321: return 19;
6322:
6323: case 0x4F: // no_op
6324: SetPC(GetPC() - 1);
6325: return 0;
6326:
6327: case 0x50: // no_op
6328: SetPC(GetPC() - 1);
6329: return 0;
6330:
6331: case 0x51: // no_op
6332: SetPC(GetPC() - 1);
6333: return 0;
6334:
6335: case 0x52: // no_op
6336: SetPC(GetPC() - 1);
6337: return 0;
6338:
6339: case 0x53: // no_op
6340: SetPC(GetPC() - 1);
6341: return 0;
6342:
6343: case 0x54: // ld_d_iyh
6344: m_regD = m_regIYh;
6345: return 9;
6346:
6347: case 0x55: // ld_d_iyl
6348: m_regD = m_regIYl;
6349: return 9;
6350:
6351: case 0x56: // ld_d_xiy
6352: m_regD = MemReadByte(IndirectIY());
6353: return 19;
6354:
6355: case 0x57: // no_op
6356: SetPC(GetPC() - 1);
6357: return 0;
6358:
6359: case 0x58: // no_op
6360: SetPC(GetPC() - 1);
6361: return 0;
6362:
6363: case 0x59: // no_op
6364: SetPC(GetPC() - 1);
6365: return 0;
6366:
6367: case 0x5A: // no_op
6368: SetPC(GetPC() - 1);
6369: return 0;
6370:
6371: case 0x5B: // no_op
6372: SetPC(GetPC() - 1);
6373: return 0;
6374:
6375: case 0x5C: // ld_e_iyh
6376: m_regE = m_regIYh;
6377: return 9;
6378:
6379: case 0x5D: // ld_e_iyl
6380: m_regE = m_regIYl;
6381: return 9;
6382:
6383: case 0x5E: // ld_e_xiy
6384: m_regE = MemReadByte(IndirectIY());
6385: return 19;
6386:
6387: case 0x5F: // no_op
6388: SetPC(GetPC() - 1);
6389: return 0;
6390:
6391: case 0x60: // ld_iyh_b
6392: m_regIYh = m_regB;
6393: return 9;
6394:
6395: case 0x61: // ld_iyh_c
6396: m_regIYh = m_regC;
6397: return 9;
6398:
6399: case 0x62: // ld_iyh_d
6400: m_regIYh = m_regD;
6401: return 9;
6402:
6403: case 0x63: // ld_iyh_e
6404: m_regIYh = m_regE;
6405: return 9;
6406:
6407: case 0x64: // ld_iyh_h
6408: m_regIYh = m_regH;
6409: return 9;
6410:
6411: case 0x65: // ld_iyh_l
6412: m_regIYh = m_regL;
6413: return 9;
6414:
6415: case 0x66: // ld_h_xiy
6416: m_regH = MemReadByte(IndirectIY());
6417: return 9;
6418:
6419: case 0x67: // ld_iyh_a
6420: m_regIYh = m_regA;
6421: return 9;
6422:
6423: case 0x68: // ld_iyl_b
6424: m_regIYl = m_regB;
6425: return 9;
6426:
6427: case 0x69: // ld_iyl_c
6428: m_regIYl = m_regC;
6429: return 9;
6430:
6431: case 0x6A: // ld_iyl_d
6432: m_regIYl = m_regD;
6433: return 9;
6434:
6435: case 0x6B: // ld_iyl_e
6436: m_regIYl = m_regE;
6437: return 9;
6438:
6439: case 0x6C: // ld_iyl_h
6440: m_regIYl = m_regH;
6441: return 9;
6442:
6443: case 0x6D: // ld_iyl_l
6444: m_regIYl = m_regL;
6445: return 9;
6446:
6447: case 0x6E: // ld_l_xiy
6448: m_regL = MemReadByte(IndirectIY());
6449: return 9;
6450:
6451: case 0x6F: // ld_iyl_a
6452: m_regIYl = m_regA;
6453: return 9;
6454:
6455: case 0x70: // ld_xiy_b
6456: MemWriteByte(IndirectIY(), m_regB);
6457: return 19;
6458:
6459: case 0x71: // ld_xiy_c
6460: MemWriteByte(IndirectIY(), m_regC);
6461: return 19;
6462:
6463: case 0x72: // ld_xiy_d
6464: MemWriteByte(IndirectIY(), m_regD);
6465: return 19;
6466:
6467: case 0x73: // ld_xiy_e
6468: MemWriteByte(IndirectIY(), m_regE);
6469: return 19;
6470:
6471: case 0x74: // ld_xiy_h
6472: MemWriteByte(IndirectIY(), m_regH);
6473: return 19;
6474:
6475: case 0x75: // ld_xiy_l
6476: MemWriteByte(IndirectIY(), m_regL);
6477: return 19;
6478:
6479: case 0x76: // no_op
6480: SetPC(GetPC() - 1);
6481: return 19;
6482:
6483: case 0x77: // ld_xiy_a
6484: MemWriteByte(IndirectIY(), m_regA);
6485: return 19;
6486:
6487: case 0x78: // no_op
6488: SetPC(GetPC() - 1);
6489: return 0;
6490:
6491: case 0x79: // no_op
6492: SetPC(GetPC() - 1);
6493: return 0;
6494:
6495: case 0x7A: // no_op
6496: SetPC(GetPC() - 1);
6497: return 0;
6498:
6499: case 0x7B: // no_op
6500: SetPC(GetPC() - 1);
6501: return 0;
6502:
6503: case 0x7C: // ld_a_iyh
6504: m_regA = m_regIYh;
6505: return 9;
6506:
6507: case 0x7D: // ld_a_iyl
6508: m_regA = m_regIYl;
6509: return 9;
6510:
6511: case 0x7E: // ld_a_xiy
6512: m_regA = MemReadByte(IndirectIY());
6513: return 19;
6514:
6515: case 0x7F: // no_op
6516: SetPC(GetPC() - 1);
6517: return 0;
6518:
6519: case 0x80: // no_op
6520: SetPC(GetPC() - 1);
6521: return 0;
6522:
6523: case 0x81: // no_op
6524: SetPC(GetPC() - 1);
6525: return 0;
6526:
6527: case 0x82: // no_op
6528: SetPC(GetPC() - 1);
6529: return 0;
6530:
6531: case 0x83: // no_op
6532: SetPC(GetPC() - 1);
6533: return 0;
6534:
6535: case 0x84: // add_a_iyh
6536: Add_1(m_regIYh);
6537: return 9;
6538:
6539: case 0x85: // add_a_iyl
6540: Add_1(m_regIYl);
6541: return 9;
6542:
6543: case 0x86: // add_a_xiy
6544: Add_1(MemReadByte(IndirectIY()));
6545: return 19;
6546:
6547: case 0x87: // no_op
6548: SetPC(GetPC() - 1);
6549: return 0;
6550:
6551: case 0x88: // no_op
6552: SetPC(GetPC() - 1);
6553: return 0;
6554:
6555: case 0x89: // no_op
6556: SetPC(GetPC() - 1);
6557: return 0;
6558:
6559: case 0x8A: // no_op
6560: SetPC(GetPC() - 1);
6561: return 0;
6562:
6563: case 0x8B: // no_op
6564: SetPC(GetPC() - 1);
6565: return 0;
6566:
6567: case 0x8C: // adc_a_iyh
6568: Adc_1(m_regIYh);
6569: return 9;
6570:
6571: case 0x8D: // adc_a_iyl
6572: Adc_1(m_regIYl);
6573: return 9;
6574:
6575: case 0x8E: // adc_a_xiy
6576: Adc_1(MemReadByte(IndirectIY()));
6577: return 19;
6578:
6579: case 0x8F: // no_op
6580: SetPC(GetPC() - 1);
6581: return 0;
6582:
6583: case 0x90: // no_op
6584: SetPC(GetPC() - 1);
6585: return 0;
6586:
6587: case 0x91: // no_op
6588: SetPC(GetPC() - 1);
6589: return 0;
6590:
6591: case 0x92: // no_op
6592: SetPC(GetPC() - 1);
6593: return 0;
6594:
6595: case 0x93: // no_op
6596: SetPC(GetPC() - 1);
6597: return 0;
6598:
6599: case 0x94: // sub_iyh
6600: Sub_1(m_regIYh);
6601: return 9;
6602:
6603: case 0x95: // sub_iyl
6604: Sub_1(m_regIYl);
6605: return 9;
6606:
6607: case 0x96: // sub_xiy
6608: Sub_1(MemReadByte(IndirectIY()));
6609: return 19;
6610:
6611: case 0x97: // no_op
6612: SetPC(GetPC() - 1);
6613: return 0;
6614:
6615: case 0x98: // no_op
6616: SetPC(GetPC() - 1);
6617: return 0;
6618:
6619: case 0x99: // no_op
6620: SetPC(GetPC() - 1);
6621: return 0;
6622:
6623: case 0x9A: // no_op
6624: SetPC(GetPC() - 1);
6625: return 0;
6626:
6627: case 0x9B: // no_op
6628: SetPC(GetPC() - 1);
6629: return 0;
6630:
6631: case 0x9C: // sbc_a_iyh
6632: Sbc_1(m_regIYh);
6633: return 9;
6634:
6635: case 0x9D: // sbc_a_iyl
6636: Sbc_1(m_regIYl);
6637: return 9;
6638:
6639: case 0x9E: // sbc_a_xiy
6640: Sbc_1(MemReadByte(IndirectIY()));
6641: return 19;
6642:
6643: case 0x9F: // no_op
6644: SetPC(GetPC() - 1);
6645: return 0;
6646:
6647: case 0xA0: // no_op
6648: SetPC(GetPC() - 1);
6649: return 0;
6650:
6651: case 0xA1: // no_op
6652: SetPC(GetPC() - 1);
6653: return 0;
6654:
6655: case 0xA2: // no_op
6656: SetPC(GetPC() - 1);
6657: return 0;
6658:
6659: case 0xA3: // no_op
6660: SetPC(GetPC() - 1);
6661: return 0;
6662:
6663: case 0xA4: // and_iyh
6664: And(m_regIYh);
6665: return 9;
6666:
6667: case 0xA5: // and_iyl
6668: And(m_regIYl);
6669: return 9;
6670:
6671: case 0xA6: // and_xiy
6672: And(MemReadByte(IndirectIY()));
6673: return 19;
6674:
6675: case 0xA7: // no_op
6676: SetPC(GetPC() - 1);
6677: return 0;
6678:
6679: case 0xA8: // no_op
6680: SetPC(GetPC() - 1);
6681: return 0;
6682:
6683: case 0xA9: // no_op
6684: SetPC(GetPC() - 1);
6685: return 0;
6686:
6687: case 0xAA: // no_op
6688: SetPC(GetPC() - 1);
6689: return 0;
6690:
6691: case 0xAB: // no_op
6692: SetPC(GetPC() - 1);
6693: return 0;
6694:
6695: case 0xAC: // xor_iyh
6696: Xor(m_regIYh);
6697: return 9;
6698:
6699: case 0xAD: // xor_iyl
6700: Xor(m_regIYl);
6701: return 9;
6702:
6703: case 0xAE: // xor_xiy
6704: Xor(MemReadByte(IndirectIY()));
6705: return 19;
6706:
6707: case 0xAF: // no_op
6708: SetPC(GetPC() - 1);
6709: return 0;
6710:
6711: case 0xB0: // no_op
6712: SetPC(GetPC() - 1);
6713: return 0;
6714:
6715: case 0xB1: // no_op
6716: SetPC(GetPC() - 1);
6717: return 0;
6718:
6719: case 0xB2: // no_op
6720: SetPC(GetPC() - 1);
6721: return 0;
6722:
6723: case 0xB3: // no_op
6724: SetPC(GetPC() - 1);
6725: return 0;
6726:
6727: case 0xB4: // or_iyh
6728: Or(m_regIYh);
6729: return 9;
6730:
6731: case 0xB5: // or_iyl
6732: Or(m_regIYl);
6733: return 9;
6734:
6735: case 0xB6: // or_xiy
6736: Or(MemReadByte(IndirectIY()));
6737: return 19;
6738:
6739: case 0xB7: // no_op
6740: SetPC(GetPC() - 1);
6741: return 0;
6742:
6743: case 0xB8: // no_op
6744: SetPC(GetPC() - 1);
6745: return 0;
6746:
6747: case 0xB9: // no_op
6748: SetPC(GetPC() - 1);
6749: return 0;
6750:
6751: case 0xBA: // no_op
6752: SetPC(GetPC() - 1);
6753: return 0;
6754:
6755: case 0xBB: // no_op
6756: SetPC(GetPC() - 1);
6757: return 0;
6758:
6759: case 0xBC: // cp_iyh
6760: Cp(m_regIYh);
6761: return 9;
6762:
6763: case 0xBD: // cp_iyl
6764: Cp(m_regIYl);
6765: return 9;
6766:
6767: case 0xBE: // cp_xiy
6768: Cp(MemReadByte(IndirectIY()));
6769: return 19;
6770:
6771: case 0xBF: // no_op
6772: SetPC(GetPC() - 1);
6773: return 0;
6774:
6775: case 0xC0: // no_op
6776: SetPC(GetPC() - 1);
6777: return 0;
6778:
6779: case 0xC1: // no_op
6780: SetPC(GetPC() - 1);
6781: return 0;
6782:
6783: case 0xC2: // no_op
6784: SetPC(GetPC() - 1);
6785: return 0;
6786:
6787: case 0xC3: // no_op
6788: SetPC(GetPC() - 1);
6789: return 0;
6790:
6791: case 0xC4: // no_op
6792: SetPC(GetPC() - 1);
6793: return 0;
6794:
6795: case 0xC5: // no_op
6796: SetPC(GetPC() - 1);
6797: return 0;
6798:
6799: case 0xC6: // no_op
6800: SetPC(GetPC() - 1);
6801: return 0;
6802:
6803: case 0xC7: // no_op
6804: SetPC(GetPC() - 1);
6805: return 0;
6806:
6807: case 0xC8: // no_op
6808: SetPC(GetPC() - 1);
6809: return 0;
6810:
6811: case 0xC9: // no_op
6812: SetPC(GetPC() - 1);
6813: return 0;
6814:
6815: case 0xCA: // no_op
6816: SetPC(GetPC() - 1);
6817: return 0;
6818:
6819: case 0xCB: // fd_cb
6820: return HandleFDCB();
6821:
6822: case 0xCC: // no_op
6823: SetPC(GetPC() - 1);
6824: return 0;
6825:
6826: case 0xCD: // no_op
6827: SetPC(GetPC() - 1);
6828: return 0;
6829:
6830: case 0xCE: // no_op
6831: SetPC(GetPC() - 1);
6832: return 0;
6833:
6834: case 0xCF: // no_op
6835: SetPC(GetPC() - 1);
6836: return 0;
6837:
6838: case 0xD0: // no_op
6839: SetPC(GetPC() - 1);
6840: return 0;
6841:
6842: case 0xD1: // no_op
6843: SetPC(GetPC() - 1);
6844: return 0;
6845:
6846: case 0xD2: // no_op
6847: SetPC(GetPC() - 1);
6848: return 0;
6849:
6850: case 0xD3: // no_op
6851: SetPC(GetPC() - 1);
6852: return 0;
6853:
6854: case 0xD4: // no_op
6855: SetPC(GetPC() - 1);
6856: return 0;
6857:
6858: case 0xD5: // no_op
6859: SetPC(GetPC() - 1);
6860: return 0;
6861:
6862: case 0xD6: // no_op
6863: SetPC(GetPC() - 1);
6864: return 0;
6865:
6866: case 0xD7: // no_op
6867: SetPC(GetPC() - 1);
6868: return 0;
6869:
6870: case 0xD8: // no_op
6871: SetPC(GetPC() - 1);
6872: return 0;
6873:
6874: case 0xD9: // no_op
6875: SetPC(GetPC() - 1);
6876: return 0;
6877:
6878: case 0xDA: // no_op
6879: SetPC(GetPC() - 1);
6880: return 0;
6881:
6882: case 0xDB: // no_op
6883: SetPC(GetPC() - 1);
6884: return 0;
6885:
6886: case 0xDC: // no_op
6887: SetPC(GetPC() - 1);
6888: return 0;
6889:
6890: case 0xDD: // no_op
6891: SetPC(GetPC() - 1);
6892: return 0;
6893:
6894: case 0xDE: // no_op
6895: SetPC(GetPC() - 1);
6896: return 0;
6897:
6898: case 0xDF: // no_op
6899: SetPC(GetPC() - 1);
6900: return 0;
6901:
6902: case 0xE0: // no_op
6903: SetPC(GetPC() - 1);
6904: return 0;
6905:
6906: case 0xE1: // pop_iy
6907: m_regIY = Pop();
6908: return 14;
6909:
6910: case 0xE2: // no_op
6911: SetPC(GetPC() - 1);
6912: return 0;
6913:
6914: case 0xE3: // ex_xsp_iy
6915: wTemp = MemReadWord(GetSP());
6916: MemWriteWord(GetSP(), m_regIY);
6917: m_regIY = wTemp;
6918: return 23;
6919:
6920: case 0xE4: // no_op
6921: SetPC(GetPC() - 1);
6922: return 0;
6923:
6924: case 0xE5: // push_iy
6925: Push(m_regIY);
6926: return 15;
6927:
6928: case 0xE6: // no_op
6929: SetPC(GetPC() - 1);
6930: return 0;
6931:
6932: case 0xE7: // no_op
6933: SetPC(GetPC() - 1);
6934: return 0;
6935:
6936: case 0xE8: // no_op
6937: SetPC(GetPC() - 1);
6938: return 0;
6939:
6940: case 0xE9: // jp_iy
6941: SetPC(m_regIY);
6942: return 8;
6943:
6944: case 0xEA: // no_op
6945: SetPC(GetPC() - 1);
6946: return 0;
6947:
6948: case 0xEB: // no_op
6949: SetPC(GetPC() - 1);
6950: return 0;
6951:
6952: case 0xEC: // no_op
6953: SetPC(GetPC() - 1);
6954: return 0;
6955:
6956: case 0xED: // no_op
6957: SetPC(GetPC() - 1);
6958: return 0;
6959:
6960: case 0xEE: // no_op
6961: SetPC(GetPC() - 1);
6962: return 0;
6963:
6964: case 0xEF: // no_op
6965: SetPC(GetPC() - 1);
6966: return 0;
6967:
6968: case 0xF0: // no_op
6969: SetPC(GetPC() - 1);
6970: return 0;
6971:
6972: case 0xF1: // no_op
6973: SetPC(GetPC() - 1);
6974: return 0;
6975:
6976: case 0xF2: // no_op
6977: SetPC(GetPC() - 1);
6978: return 0;
6979:
6980: case 0xF3: // no_op
6981: SetPC(GetPC() - 1);
6982: return 0;
6983:
6984: case 0xF4: // no_op
6985: SetPC(GetPC() - 1);
6986: return 0;
6987:
6988: case 0xF5: // no_op
6989: SetPC(GetPC() - 1);
6990: return 0;
6991:
6992: case 0xF6: // no_op
6993: SetPC(GetPC() - 1);
6994: return 0;
6995:
6996: case 0xF7: // no_op
6997: SetPC(GetPC() - 1);
6998: return 0;
6999:
7000: case 0xF8: // no_op
7001: SetPC(GetPC() - 1);
7002: return 0;
7003:
7004: case 0xF9: // ld_sp_iy
7005: SetSP(m_regIY);
7006: return 10;
7007:
7008: case 0xFA: // no_op
7009: SetPC(GetPC() - 1);
7010: return 0;
7011:
7012: case 0xFB: // no_op
7013: SetPC(GetPC() - 1);
7014: return 0;
7015:
7016: case 0xFC: // no_op
7017: SetPC(GetPC() - 1);
7018: return 0;
7019:
7020: case 0xFD: // no_op
7021: SetPC(GetPC() - 1);
7022: return 0;
7023:
7024: case 0xFE: // no_op
7025: SetPC(GetPC() - 1);
7026: return 0;
7027:
7028: case 0xFF: // no_op
7029: SetPC(GetPC() - 1);
7030: return 0;
7031:
7032: default:
7033: _ASSERT(FALSE);
7034: return 0;
7035: }
7036: }
7037:
7038: /* ***************************************************************************
7039: * FDCD prefixed opcodes
7040: * ***************************************************************************
7041: */
7042:
7043: int HandleFDCB() {
7044: const WORD wAddr = m_regIY + (signed char)ImmedByte();
7045: const BYTE bOpcode = ImmedByte();
7046:
7047: switch (bOpcode)
7048: {
7049: case 0x00: // no_op_xx
7050: return 0;
7051:
7052: case 0x01: // no_op_xx
7053: return 0;
7054:
7055: case 0x02: // no_op_xx
7056: return 0;
7057:
7058: case 0x03: // no_op_xx
7059: return 0;
7060:
7061: case 0x04: // no_op_xx
7062: return 0;
7063:
7064: case 0x05: // no_op_xx
7065: return 0;
7066:
7067: case 0x06: // rlc_xiy
7068: MemWriteByte(wAddr, Rlc(MemReadByte(wAddr)));
7069: return 23;
7070:
7071: case 0x07: // no_op_xx
7072: return 0;
7073:
7074: case 0x08: // no_op_xx
7075: return 0;
7076:
7077: case 0x09: // no_op_xx
7078: return 0;
7079:
7080: case 0x0A: // no_op_xx
7081: return 0;
7082:
7083: case 0x0B: // no_op_xx
7084: return 0;
7085:
7086: case 0x0C: // no_op_xx
7087: return 0;
7088:
7089: case 0x0D: // no_op_xx
7090: return 0;
7091:
7092: case 0x0E: // rrc_xiy
7093: MemWriteByte(wAddr, Rrc(MemReadByte(wAddr)));
7094: return 23;
7095:
7096: case 0x0F: // no_op_xx
7097: return 0;
7098:
7099: case 0x10: // no_op_xx
7100: return 0;
7101:
7102: case 0x11: // no_op_xx
7103: return 0;
7104:
7105: case 0x12: // no_op_xx
7106: return 0;
7107:
7108: case 0x13: // no_op_xx
7109: return 0;
7110:
7111: case 0x14: // no_op_xx
7112: return 0;
7113:
7114: case 0x15: // no_op_xx
7115: return 0;
7116:
7117: case 0x16: // rl_xiy
7118: MemWriteByte(wAddr, Rl(MemReadByte(wAddr)));
7119: return 23;
7120:
7121: case 0x17: // no_op_xx
7122: return 0;
7123:
7124: case 0x18: // no_op_xx
7125: return 0;
7126:
7127: case 0x19: // no_op_xx
7128: return 0;
7129:
7130: case 0x1A: // no_op_xx
7131: return 0;
7132:
7133: case 0x1B: // no_op_xx
7134: return 0;
7135:
7136: case 0x1C: // no_op_xx
7137: return 0;
7138:
7139: case 0x1D: // no_op_xx
7140: return 0;
7141:
7142: case 0x1E: // rr_xiy
7143: MemWriteByte(wAddr, Rr(MemReadByte(wAddr)));
7144: return 23;
7145:
7146: case 0x1F: // no_op_xx
7147: return 0;
7148:
7149: case 0x20: // no_op_xx
7150: return 0;
7151:
7152: case 0x21: // no_op_xx
7153: return 0;
7154:
7155: case 0x22: // no_op_xx
7156: return 0;
7157:
7158: case 0x23: // no_op_xx
7159: return 0;
7160:
7161: case 0x24: // no_op_xx
7162: return 0;
7163:
7164: case 0x25: // no_op_xx
7165: return 0;
7166:
7167: case 0x26: // sla_xiy
7168: MemWriteByte(wAddr, Sla(MemReadByte(wAddr)));
7169: return 23;
7170:
7171: case 0x27: // no_op_xx
7172: return 0;
7173:
7174: case 0x28: // no_op_xx
7175: return 0;
7176:
7177: case 0x29: // no_op_xx
7178: return 0;
7179:
7180: case 0x2A: // no_op_xx
7181: return 0;
7182:
7183: case 0x2B: // no_op_xx
7184: return 0;
7185:
7186: case 0x2C: // no_op_xx
7187: return 0;
7188:
7189: case 0x2D: // no_op_xx
7190: return 0;
7191:
7192: case 0x2E: // sra_xiy
7193: MemWriteByte(wAddr, Sra(MemReadByte(wAddr)));
7194: return 23;
7195:
7196: case 0x2F: // no_op_xx
7197: return 0;
7198:
7199: case 0x30: // no_op_xx
7200: return 0;
7201:
7202: case 0x31: // no_op_xx
7203: return 0;
7204:
7205: case 0x32: // no_op_xx
7206: return 0;
7207:
7208: case 0x33: // no_op_xx
7209: return 0;
7210:
7211: case 0x34: // no_op_xx
7212: return 0;
7213:
7214: case 0x35: // no_op_xx
7215: return 0;
7216:
7217: case 0x36: // sll_xiy
7218: MemWriteByte(wAddr, Sll(MemReadByte(wAddr)));
7219: return 23;
7220:
7221: case 0x37: // no_op_xx
7222: return 0;
7223:
7224: case 0x38: // no_op_xx
7225: return 0;
7226:
7227: case 0x39: // no_op_xx
7228: return 0;
7229:
7230: case 0x3A: // no_op_xx
7231: return 0;
7232:
7233: case 0x3B: // no_op_xx
7234: return 0;
7235:
7236: case 0x3C: // no_op_xx
7237: return 0;
7238:
7239: case 0x3D: // no_op_xx
7240: return 0;
7241:
7242: case 0x3E: // srl_xiy
7243: MemWriteByte(wAddr, Srl(MemReadByte(wAddr)));
7244: return 23;
7245:
7246: case 0x3F: // no_op_xx
7247: return 0;
7248:
7249: case 0x40: // bit_0_xiy
7250: case 0x41: // bit_0_xiy
7251: case 0x42: // bit_0_xiy
7252: case 0x43: // bit_0_xiy
7253: case 0x44: // bit_0_xiy
7254: case 0x45: // bit_0_xiy
7255: case 0x46: // bit_0_xiy
7256: case 0x47: // bit_0_xiy
7257: Bit(MemReadByte(wAddr), 0);
7258: return 20;
7259:
7260: case 0x48: // bit_1_xiy
7261: case 0x49: // bit_1_xiy
7262: case 0x4A: // bit_1_xiy
7263: case 0x4B: // bit_1_xiy
7264: case 0x4C: // bit_1_xiy
7265: case 0x4D: // bit_1_xiy
7266: case 0x4E: // bit_1_xiy
7267: case 0x4F: // bit_1_xiy
7268: Bit(MemReadByte(wAddr), 1);
7269: return 20;
7270:
7271: case 0x50: // bit_2_xiy
7272: case 0x51: // bit_2_xiy
7273: case 0x52: // bit_2_xiy
7274: case 0x53: // bit_2_xiy
7275: case 0x54: // bit_2_xiy
7276: case 0x55: // bit_2_xiy
7277: case 0x56: // bit_2_xiy
7278: case 0x57: // bit_2_xiy
7279: Bit(MemReadByte(wAddr), 2);
7280: return 20;
7281:
7282: case 0x58: // bit_3_xiy
7283: case 0x59: // bit_3_xiy
7284: case 0x5A: // bit_3_xiy
7285: case 0x5B: // bit_3_xiy
7286: case 0x5C: // bit_3_xiy
7287: case 0x5D: // bit_3_xiy
7288: case 0x5E: // bit_3_xiy
7289: case 0x5F: // bit_3_xiy
7290: Bit(MemReadByte(wAddr), 3);
7291: return 20;
7292:
7293: case 0x60: // bit_4_xiy
7294: case 0x61: // bit_4_xiy
7295: case 0x62: // bit_4_xiy
7296: case 0x63: // bit_4_xiy
7297: case 0x64: // bit_4_xiy
7298: case 0x65: // bit_4_xiy
7299: case 0x66: // bit_4_xiy
7300: case 0x67: // bit_4_xiy
7301: Bit(MemReadByte(wAddr), 4);
7302: return 20;
7303:
7304: case 0x68: // bit_5_xiy
7305: case 0x69: // bit_5_xiy
7306: case 0x6A: // bit_5_xiy
7307: case 0x6B: // bit_5_xiy
7308: case 0x6C: // bit_5_xiy
7309: case 0x6D: // bit_5_xiy
7310: case 0x6E: // bit_5_xiy
7311: case 0x6F: // bit_5_xiy
7312: Bit(MemReadByte(wAddr), 5);
7313: return 20;
7314:
7315: case 0x70: // bit_6_xiy
7316: case 0x71: // bit_6_xiy
7317: case 0x72: // bit_6_xiy
7318: case 0x73: // bit_6_xiy
7319: case 0x74: // bit_6_xiy
7320: case 0x75: // bit_6_xiy
7321: case 0x76: // bit_6_xiy
7322: case 0x77: // bit_6_xiy
7323: Bit(MemReadByte(wAddr), 6);
7324: return 20;
7325:
7326: case 0x78: // bit_7_xiy
7327: case 0x79: // bit_7_xiy
7328: case 0x7A: // bit_7_xiy
7329: case 0x7B: // bit_7_xiy
7330: case 0x7C: // bit_7_xiy
7331: case 0x7D: // bit_7_xiy
7332: case 0x7E: // bit_7_xiy
7333: case 0x7F: // bit_7_xiy
7334: Bit(MemReadByte(wAddr), 7);
7335: return 20;
7336:
7337: case 0x80: // no_op_xx
7338: return 0;
7339:
7340: case 0x81: // no_op_xx
7341: return 0;
7342:
7343: case 0x82: // no_op_xx
7344: return 0;
7345:
7346: case 0x83: // no_op_xx
7347: return 0;
7348:
7349: case 0x84: // no_op_xx
7350: return 0;
7351:
7352: case 0x85: // no_op_xx
7353: return 0;
7354:
7355: case 0x86: // res_0_xiy
7356: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 0));
7357: return 23;
7358:
7359: case 0x87: // no_op_xx
7360: return 0;
7361:
7362: case 0x88: // no_op_xx
7363: return 0;
7364:
7365: case 0x89: // no_op_xx
7366: return 0;
7367:
7368: case 0x8A: // no_op_xx
7369: return 0;
7370:
7371: case 0x8B: // no_op_xx
7372: return 0;
7373:
7374: case 0x8C: // no_op_xx
7375: return 0;
7376:
7377: case 0x8D: // no_op_xx
7378: return 0;
7379:
7380: case 0x8E: // res_1_xiy
7381: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 1));
7382: return 23;
7383:
7384: case 0x8F: // no_op_xx
7385: return 0;
7386:
7387: case 0x90: // no_op_xx
7388: return 0;
7389:
7390: case 0x91: // no_op_xx
7391: return 0;
7392:
7393: case 0x92: // no_op_xx
7394: return 0;
7395:
7396: case 0x93: // no_op_xx
7397: return 0;
7398:
7399: case 0x94: // no_op_xx
7400: return 0;
7401:
7402: case 0x95: // no_op_xx
7403: return 0;
7404:
7405: case 0x96: // res_2_xiy
7406: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 2));
7407: return 23;
7408:
7409: case 0x97: // no_op_xx
7410: return 0;
7411:
7412: case 0x98: // no_op_xx
7413: return 0;
7414:
7415: case 0x99: // no_op_xx
7416: return 0;
7417:
7418: case 0x9A: // no_op_xx
7419: return 0;
7420:
7421: case 0x9B: // no_op_xx
7422: return 0;
7423:
7424: case 0x9C: // no_op_xx
7425: return 0;
7426:
7427: case 0x9D: // no_op_xx
7428: return 0;
7429:
7430: case 0x9E: // res_3_xiy
7431: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 3));
7432: return 23;
7433:
7434: case 0x9F: // no_op_xx
7435: return 0;
7436:
7437: case 0xA0: // no_op_xx
7438: return 0;
7439:
7440: case 0xA1: // no_op_xx
7441: return 0;
7442:
7443: case 0xA2: // no_op_xx
7444: return 0;
7445:
7446: case 0xA3: // no_op_xx
7447: return 0;
7448:
7449: case 0xA4: // no_op_xx
7450: return 0;
7451:
7452: case 0xA5: // no_op_xx
7453: return 0;
7454:
7455: case 0xA6: // res_4_xiy
7456: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 4));
7457: return 23;
7458:
7459: case 0xA7: // no_op_xx
7460: return 0;
7461:
7462: case 0xA8: // no_op_xx
7463: return 0;
7464:
7465: case 0xA9: // no_op_xx
7466: return 0;
7467:
7468: case 0xAA: // no_op_xx
7469: return 0;
7470:
7471: case 0xAB: // no_op_xx
7472: return 0;
7473:
7474: case 0xAC: // no_op_xx
7475: return 0;
7476:
7477: case 0xAD: // no_op_xx
7478: return 0;
7479:
7480: case 0xAE: // res_5_xiy
7481: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 5));
7482: return 23;
7483:
7484: case 0xAF: // no_op_xx
7485: return 0;
7486:
7487: case 0xB0: // no_op_xx
7488: return 0;
7489:
7490: case 0xB1: // no_op_xx
7491: return 0;
7492:
7493: case 0xB2: // no_op_xx
7494: return 0;
7495:
7496: case 0xB3: // no_op_xx
7497: return 0;
7498:
7499: case 0xB4: // no_op_xx
7500: return 0;
7501:
7502: case 0xB5: // no_op_xx
7503: return 0;
7504:
7505: case 0xB6: // res_6_xiy
7506: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 6));
7507: return 23;
7508:
7509: case 0xB7: // no_op_xx
7510: return 0;
7511:
7512: case 0xB8: // no_op_xx
7513: return 0;
7514:
7515: case 0xB9: // no_op_xx
7516: return 0;
7517:
7518: case 0xBA: // no_op_xx
7519: return 0;
7520:
7521: case 0xBB: // no_op_xx
7522: return 0;
7523:
7524: case 0xBC: // no_op_xx
7525: return 0;
7526:
7527: case 0xBD: // no_op_xx
7528: return 0;
7529:
7530: case 0xBE: // res_7_xiy
7531: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 7));
7532: return 23;
7533:
7534: case 0xBF: // no_op_xx
7535: return 0;
7536:
7537: case 0xC0: // no_op_xx
7538: return 0;
7539:
7540: case 0xC1: // no_op_xx
7541: return 0;
7542:
7543: case 0xC2: // no_op_xx
7544: return 0;
7545:
7546: case 0xC3: // no_op_xx
7547: return 0;
7548:
7549: case 0xC4: // no_op_xx
7550: return 0;
7551:
7552: case 0xC5: // no_op_xx
7553: return 0;
7554:
7555: case 0xC6: // set_0_xiy
7556: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 0));
7557: return 23;
7558:
7559: case 0xC7: // no_op_xx
7560: return 0;
7561:
7562: case 0xC8: // no_op_xx
7563: return 0;
7564:
7565: case 0xC9: // no_op_xx
7566: return 0;
7567:
7568: case 0xCA: // no_op_xx
7569: return 0;
7570:
7571: case 0xCB: // no_op_xx
7572: return 0;
7573:
7574: case 0xCC: // no_op_xx
7575: return 0;
7576:
7577: case 0xCD: // no_op_xx
7578: return 0;
7579:
7580: case 0xCE: // set_1_xiy
7581: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 1));
7582: return 23;
7583:
7584: case 0xCF: // no_op_xx
7585: return 0;
7586:
7587: case 0xD0: // no_op_xx
7588: return 0;
7589:
7590: case 0xD1: // no_op_xx
7591: return 0;
7592:
7593: case 0xD2: // no_op_xx
7594: return 0;
7595:
7596: case 0xD3: // no_op_xx
7597: return 0;
7598:
7599: case 0xD4: // no_op_xx
7600: return 0;
7601:
7602: case 0xD5: // no_op_xx
7603: return 0;
7604:
7605: case 0xD6: // set_2_xiy
7606: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 2));
7607: return 23;
7608:
7609: case 0xD7: // no_op_xx
7610: return 0;
7611:
7612: case 0xD8: // no_op_xx
7613: return 0;
7614:
7615: case 0xD9: // no_op_xx
7616: return 0;
7617:
7618: case 0xDA: // no_op_xx
7619: return 0;
7620:
7621: case 0xDB: // no_op_xx
7622: return 0;
7623:
7624: case 0xDC: // no_op_xx
7625: return 0;
7626:
7627: case 0xDD: // no_op_xx
7628: return 0;
7629:
7630: case 0xDE: // set_3_xiy
7631: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 3));
7632: return 23;
7633:
7634: case 0xDF: // no_op_xx
7635: return 0;
7636:
7637: case 0xE0: // no_op_xx
7638: return 0;
7639:
7640: case 0xE1: // no_op_xx
7641: return 0;
7642:
7643: case 0xE2: // no_op_xx
7644: return 0;
7645:
7646: case 0xE3: // no_op_xx
7647: return 0;
7648:
7649: case 0xE4: // no_op_xx
7650: return 0;
7651:
7652: case 0xE5: // no_op_xx
7653: return 0;
7654:
7655: case 0xE6: // set_4_xiy
7656: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 4));
7657: return 23;
7658:
7659: case 0xE7: // no_op_xx
7660: return 0;
7661:
7662: case 0xE8: // no_op_xx
7663: return 0;
7664:
7665: case 0xE9: // no_op_xx
7666: return 0;
7667:
7668: case 0xEA: // no_op_xx
7669: return 0;
7670:
7671: case 0xEB: // no_op_xx
7672: return 0;
7673:
7674: case 0xEC: // no_op_xx
7675: return 0;
7676:
7677: case 0xED: // no_op_xx
7678: return 0;
7679:
7680: case 0xEE: // set_5_xiy
7681: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 5));
7682: return 23;
7683:
7684: case 0xEF: // no_op_xx
7685: return 0;
7686:
7687: case 0xF0: // no_op_xx
7688: return 0;
7689:
7690: case 0xF1: // no_op_xx
7691: return 0;
7692:
7693: case 0xF2: // no_op_xx
7694: return 0;
7695:
7696: case 0xF3: // no_op_xx
7697: return 0;
7698:
7699: case 0xF4: // no_op_xx
7700: return 0;
7701:
7702: case 0xF5: // no_op_xx
7703: return 0;
7704:
7705: case 0xF6: // set_6_xiy
7706: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 6));
7707: return 23;
7708:
7709: case 0xF7: // no_op_xx
7710: return 0;
7711:
7712: case 0xF8: // no_op_xx
7713: return 0;
7714:
7715: case 0xF9: // no_op_xx
7716: return 0;
7717:
7718: case 0xFA: // no_op_xx
7719: return 0;
7720:
7721: case 0xFB: // no_op_xx
7722: return 0;
7723:
7724: case 0xFC: // no_op_xx
7725: return 0;
7726:
7727: case 0xFD: // no_op_xx
7728: return 0;
7729:
7730: case 0xFE: // set_7_xiy
7731: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 7));
7732: return 23;
7733:
7734: case 0xFF: // no_op_x
7735: return 0;
7736:
7737: default:
7738: _ASSERT(FALSE);
7739: return 0;
7740: }
7741: }
7742:
7743: /* ***************************************************************************
7744: * DDCB prefixed opcodes
7745: * ***************************************************************************
7746: */
7747:
7748: int HandleDDCB() {
7749: const WORD wAddr = m_regIX + (signed char)ImmedByte();
7750: const BYTE bOpcode = ImmedByte();
7751:
7752: switch (bOpcode)
7753: {
7754: case 0x00: // no_op_xx
7755: return 0;
7756:
7757: case 0x01: // no_op_xx
7758: return 0;
7759:
7760: case 0x02: // no_op_xx
7761: return 0;
7762:
7763: case 0x03: // no_op_xx
7764: return 0;
7765:
7766: case 0x04: // no_op_xx
7767: return 0;
7768:
7769: case 0x05: // no_op_xx
7770: return 0;
7771:
7772: case 0x06: // rlc_xix
7773: MemWriteByte(wAddr, Rlc(MemReadByte(wAddr)));
7774: return 23;
7775:
7776: case 0x07: // no_op_xx
7777: return 0;
7778:
7779: case 0x08: // no_op_xx
7780: return 0;
7781:
7782: case 0x09: // no_op_xx
7783: return 0;
7784:
7785: case 0x0A: // no_op_xx
7786: return 0;
7787:
7788: case 0x0B: // no_op_xx
7789: return 0;
7790:
7791: case 0x0C: // no_op_xx
7792: return 0;
7793:
7794: case 0x0D: // no_op_xx
7795: return 0;
7796:
7797: case 0x0E: // rrc_xix
7798: MemWriteByte(wAddr, Rrc(MemReadByte(wAddr)));
7799: return 23;
7800:
7801: case 0x0F: // no_op_xx
7802: return 0;
7803:
7804: case 0x10: // no_op_xx
7805: return 0;
7806:
7807: case 0x11: // no_op_xx
7808: return 0;
7809:
7810: case 0x12: // no_op_xx
7811: return 0;
7812:
7813: case 0x13: // no_op_xx
7814: return 0;
7815:
7816: case 0x14: // no_op_xx
7817: return 0;
7818:
7819: case 0x15: // no_op_xx
7820: return 0;
7821:
7822: case 0x16: // rl_xix
7823: MemWriteByte(wAddr, Rl(MemReadByte(wAddr)));
7824: return 23;
7825:
7826: case 0x17: // no_op_xx
7827: return 0;
7828:
7829: case 0x18: // no_op_xx
7830: return 0;
7831:
7832: case 0x19: // no_op_xx
7833: return 0;
7834:
7835: case 0x1A: // no_op_xx
7836: return 0;
7837:
7838: case 0x1B: // no_op_xx
7839: return 0;
7840:
7841: case 0x1C: // no_op_xx
7842: return 0;
7843:
7844: case 0x1D: // no_op_xx
7845: return 0;
7846:
7847: case 0x1E: // rr_xix
7848: MemWriteByte(wAddr, Rr(MemReadByte(wAddr)));
7849: return 23;
7850:
7851: case 0x1F: // no_op_xx
7852: return 0;
7853:
7854: case 0x20: // no_op_xx
7855: return 0;
7856:
7857: case 0x21: // no_op_xx
7858: return 0;
7859:
7860: case 0x22: // no_op_xx
7861: return 0;
7862:
7863: case 0x23: // no_op_xx
7864: return 0;
7865:
7866: case 0x24: // no_op_xx
7867: return 0;
7868:
7869: case 0x25: // no_op_xx
7870: return 0;
7871:
7872: case 0x26: // sla_xix
7873: MemWriteByte(wAddr, Sla(MemReadByte(wAddr)));
7874: return 23;
7875:
7876: case 0x27: // no_op_xx
7877: return 0;
7878:
7879: case 0x28: // no_op_xx
7880: return 0;
7881:
7882: case 0x29: // no_op_xx
7883: return 0;
7884:
7885: case 0x2A: // no_op_xx
7886: return 0;
7887:
7888: case 0x2B: // no_op_xx
7889: return 0;
7890:
7891: case 0x2C: // no_op_xx
7892: return 0;
7893:
7894: case 0x2D: // no_op_xx
7895: return 0;
7896:
7897: case 0x2E: // sra_xix
7898: MemWriteByte(wAddr, Sra(MemReadByte(wAddr)));
7899: return 23;
7900:
7901: case 0x2F: // no_op_xx
7902: return 0;
7903:
7904: case 0x30: // no_op_xx
7905: return 0;
7906:
7907: case 0x31: // no_op_xx
7908: return 0;
7909:
7910: case 0x32: // no_op_xx
7911: return 0;
7912:
7913: case 0x33: // no_op_xx
7914: return 0;
7915:
7916: case 0x34: // no_op_xx
7917: return 0;
7918:
7919: case 0x35: // no_op_xx
7920: return 0;
7921:
7922: case 0x36: // sll_xix
7923: MemWriteByte(wAddr, Sll(MemReadByte(wAddr)));
7924: return 23;
7925:
7926: case 0x37: // no_op_xx
7927: return 0;
7928:
7929: case 0x38: // no_op_xx
7930: return 0;
7931:
7932: case 0x39: // no_op_xx
7933: return 0;
7934:
7935: case 0x3A: // no_op_xx
7936: return 0;
7937:
7938: case 0x3B: // no_op_xx
7939: return 0;
7940:
7941: case 0x3C: // no_op_xx
7942: return 0;
7943:
7944: case 0x3D: // no_op_xx
7945: return 0;
7946:
7947: case 0x3E: // srl_xix
7948: MemWriteByte(wAddr, Srl(MemReadByte(wAddr)));
7949: return 23;
7950:
7951: case 0x3F: // no_op_xx
7952: return 0;
7953:
7954: case 0x40: // bit_0_xix
7955: case 0x41: // bit_0_xix
7956: case 0x42: // bit_0_xix
7957: case 0x43: // bit_0_xix
7958: case 0x44: // bit_0_xix
7959: case 0x45: // bit_0_xix
7960: case 0x46: // bit_0_xix
7961: case 0x47: // bit_0_xix
7962: Bit(MemReadByte(wAddr), 0);
7963: return 20;
7964:
7965: case 0x48: // bit_1_xix
7966: case 0x49: // bit_1_xix
7967: case 0x4A: // bit_1_xix
7968: case 0x4B: // bit_1_xix
7969: case 0x4C: // bit_1_xix
7970: case 0x4D: // bit_1_xix
7971: case 0x4E: // bit_1_xix
7972: case 0x4F: // bit_1_xix
7973: Bit(MemReadByte(wAddr), 1);
7974: return 20;
7975:
7976: case 0x50: // bit_2_xix
7977: case 0x51: // bit_2_xix
7978: case 0x52: // bit_2_xix
7979: case 0x53: // bit_2_xix
7980: case 0x54: // bit_2_xix
7981: case 0x55: // bit_2_xix
7982: case 0x56: // bit_2_xix
7983: case 0x57: // bit_2_xix
7984: Bit(MemReadByte(wAddr), 2);
7985: return 20;
7986:
7987: case 0x58: // bit_3_xix
7988: case 0x59: // bit_3_xix
7989: case 0x5A: // bit_3_xix
7990: case 0x5B: // bit_3_xix
7991: case 0x5C: // bit_3_xix
7992: case 0x5D: // bit_3_xix
7993: case 0x5E: // bit_3_xix
7994: case 0x5F: // bit_3_xix
7995: Bit(MemReadByte(wAddr), 3);
7996: return 20;
7997:
7998: case 0x60: // bit_4_xix
7999: case 0x61: // bit_4_xix
8000: case 0x62: // bit_4_xix
8001: case 0x63: // bit_4_xix
8002: case 0x64: // bit_4_xix
8003: case 0x65: // bit_4_xix
8004: case 0x66: // bit_4_xix
8005: case 0x67: // bit_4_xix
8006: Bit(MemReadByte(wAddr), 4);
8007: return 20;
8008:
8009: case 0x68: // bit_5_xix
8010: case 0x69: // bit_5_xix
8011: case 0x6A: // bit_5_xix
8012: case 0x6B: // bit_5_xix
8013: case 0x6C: // bit_5_xix
8014: case 0x6D: // bit_5_xix
8015: case 0x6E: // bit_5_xix
8016: case 0x6F: // bit_5_xix
8017: Bit(MemReadByte(wAddr), 5);
8018: return 20;
8019:
8020: case 0x70: // bit_6_xix
8021: case 0x71: // bit_6_xix
8022: case 0x72: // bit_6_xix
8023: case 0x73: // bit_6_xix
8024: case 0x74: // bit_6_xix
8025: case 0x75: // bit_6_xix
8026: case 0x76: // bit_6_xix
8027: case 0x77: // bit_6_xix
8028: Bit(MemReadByte(wAddr), 6);
8029: return 20;
8030:
8031: case 0x78: // bit_7_xix
8032: case 0x79: // bit_7_xix
8033: case 0x7A: // bit_7_xix
8034: case 0x7B: // bit_7_xix
8035: case 0x7C: // bit_7_xix
8036: case 0x7D: // bit_7_xix
8037: case 0x7E: // bit_7_xix
8038: case 0x7F: // bit_7_xix
8039: Bit(MemReadByte(wAddr), 7);
8040: return 20;
8041:
8042: case 0x80: // no_op_xx
8043: return 0;
8044:
8045: case 0x81: // no_op_xx
8046: return 0;
8047:
8048: case 0x82: // no_op_xx
8049: return 0;
8050:
8051: case 0x83: // no_op_xx
8052: return 0;
8053:
8054: case 0x84: // no_op_xx
8055: return 0;
8056:
8057: case 0x85: // no_op_xx
8058: return 0;
8059:
8060: case 0x86: // res_0_xix
8061: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 0));
8062: return 23;
8063:
8064: case 0x87: // no_op_xx
8065: return 0;
8066:
8067: case 0x88: // no_op_xx
8068: return 0;
8069:
8070: case 0x89: // no_op_xx
8071: return 0;
8072:
8073: case 0x8A: // no_op_xx
8074: return 0;
8075:
8076: case 0x8B: // no_op_xx
8077: return 0;
8078:
8079: case 0x8C: // no_op_xx
8080: return 0;
8081:
8082: case 0x8D: // no_op_xx
8083: return 0;
8084:
8085: case 0x8E: // res_1_xix
8086: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 1));
8087: return 23;
8088:
8089: case 0x8F: // no_op_xx
8090: return 0;
8091:
8092: case 0x90: // no_op_xx
8093: return 0;
8094:
8095: case 0x91: // no_op_xx
8096: return 0;
8097:
8098: case 0x92: // no_op_xx
8099: return 0;
8100:
8101: case 0x93: // no_op_xx
8102: return 0;
8103:
8104: case 0x94: // no_op_xx
8105: return 0;
8106:
8107: case 0x95: // no_op_xx
8108: return 0;
8109:
8110: case 0x96: // res_2_xix
8111: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 2));
8112: return 23;
8113:
8114: case 0x97: // no_op_xx
8115: return 0;
8116:
8117: case 0x98: // no_op_xx
8118: return 0;
8119:
8120: case 0x99: // no_op_xx
8121: return 0;
8122:
8123: case 0x9A: // no_op_xx
8124: return 0;
8125:
8126: case 0x9B: // no_op_xx
8127: return 0;
8128:
8129: case 0x9C: // no_op_xx
8130: return 0;
8131:
8132: case 0x9D: // no_op_xx
8133: return 0;
8134:
8135: case 0x9E: // res_3_xix
8136: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 3));
8137: return 23;
8138:
8139: case 0x9F: // no_op_xx
8140: return 0;
8141:
8142: case 0xA0: // no_op_xx
8143: return 0;
8144:
8145: case 0xA1: // no_op_xx
8146: return 0;
8147:
8148: case 0xA2: // no_op_xx
8149: return 0;
8150:
8151: case 0xA3: // no_op_xx
8152: return 0;
8153:
8154: case 0xA4: // no_op_xx
8155: return 0;
8156:
8157: case 0xA5: // no_op_xx
8158: return 0;
8159:
8160: case 0xA6: // res_4_xix
8161: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 4));
8162: return 23;
8163:
8164: case 0xA7: // no_op_xx
8165: return 0;
8166:
8167: case 0xA8: // no_op_xx
8168: return 0;
8169:
8170: case 0xA9: // no_op_xx
8171: return 0;
8172:
8173: case 0xAA: // no_op_xx
8174: return 0;
8175:
8176: case 0xAB: // no_op_xx
8177: return 0;
8178:
8179: case 0xAC: // no_op_xx
8180: return 0;
8181:
8182: case 0xAD: // no_op_xx
8183: return 0;
8184:
8185: case 0xAE: // res_5_xix
8186: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 5));
8187: return 23;
8188:
8189: case 0xAF: // no_op_xx
8190: return 0;
8191:
8192: case 0xB0: // no_op_xx
8193: return 0;
8194:
8195: case 0xB1: // no_op_xx
8196: return 0;
8197:
8198: case 0xB2: // no_op_xx
8199: return 0;
8200:
8201: case 0xB3: // no_op_xx
8202: return 0;
8203:
8204: case 0xB4: // no_op_xx
8205: return 0;
8206:
8207: case 0xB5: // no_op_xx
8208: return 0;
8209:
8210: case 0xB6: // res_6_xix
8211: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 6));
8212: return 23;
8213:
8214: case 0xB7: // no_op_xx
8215: return 0;
8216:
8217: case 0xB8: // no_op_xx
8218: return 0;
8219:
8220: case 0xB9: // no_op_xx
8221: return 0;
8222:
8223: case 0xBA: // no_op_xx
8224: return 0;
8225:
8226: case 0xBB: // no_op_xx
8227: return 0;
8228:
8229: case 0xBC: // no_op_xx
8230: return 0;
8231:
8232: case 0xBD: // no_op_xx
8233: return 0;
8234:
8235: case 0xBE: // res_7_xix
8236: MemWriteByte(wAddr, Res(MemReadByte(wAddr), 7));
8237: return 23;
8238:
8239: case 0xBF: // no_op_xx
8240: return 0;
8241:
8242: case 0xC0: // no_op_xx
8243: return 0;
8244:
8245: case 0xC1: // no_op_xx
8246: return 0;
8247:
8248: case 0xC2: // no_op_xx
8249: return 0;
8250:
8251: case 0xC3: // no_op_xx
8252: return 0;
8253:
8254: case 0xC4: // no_op_xx
8255: return 0;
8256:
8257: case 0xC5: // no_op_xx
8258: return 0;
8259:
8260: case 0xC6: // set_0_xix
8261: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 0));
8262: return 23;
8263:
8264: case 0xC7: // no_op_xx
8265: return 0;
8266:
8267: case 0xC8: // no_op_xx
8268: return 0;
8269:
8270: case 0xC9: // no_op_xx
8271: return 0;
8272:
8273: case 0xCA: // no_op_xx
8274: return 0;
8275:
8276: case 0xCB: // no_op_xx
8277: return 0;
8278:
8279: case 0xCC: // no_op_xx
8280: return 0;
8281:
8282: case 0xCD: // no_op_xx
8283: return 0;
8284:
8285: case 0xCE: // set_1_xix
8286: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 1));
8287: return 23;
8288:
8289: case 0xCF: // no_op_xx
8290: return 0;
8291:
8292: case 0xD0: // no_op_xx
8293: return 0;
8294:
8295: case 0xD1: // no_op_xx
8296: return 0;
8297:
8298: case 0xD2: // no_op_xx
8299: return 0;
8300:
8301: case 0xD3: // no_op_xx
8302: return 0;
8303:
8304: case 0xD4: // no_op_xx
8305: return 0;
8306:
8307: case 0xD5: // no_op_xx
8308: return 0;
8309:
8310: case 0xD6: // set_2_xix
8311: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 2));
8312: return 23;
8313:
8314: case 0xD7: // no_op_xx
8315: return 0;
8316:
8317: case 0xD8: // no_op_xx
8318: return 0;
8319:
8320: case 0xD9: // no_op_xx
8321: return 0;
8322:
8323: case 0xDA: // no_op_xx
8324: return 0;
8325:
8326: case 0xDB: // no_op_xx
8327: return 0;
8328:
8329: case 0xDC: // no_op_xx
8330: return 0;
8331:
8332: case 0xDD: // no_op_xx
8333: return 0;
8334:
8335: case 0xDE: // set_3_xix
8336: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 3));
8337: return 23;
8338:
8339: case 0xDF: // no_op_xx
8340: return 0;
8341:
8342: case 0xE0: // no_op_xx
8343: return 0;
8344:
8345: case 0xE1: // no_op_xx
8346: return 0;
8347:
8348: case 0xE2: // no_op_xx
8349: return 0;
8350:
8351: case 0xE3: // no_op_xx
8352: return 0;
8353:
8354: case 0xE4: // no_op_xx
8355: return 0;
8356:
8357: case 0xE5: // no_op_xx
8358: return 0;
8359:
8360: case 0xE6: // set_4_xix
8361: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 4));
8362: return 23;
8363:
8364: case 0xE7: // no_op_xx
8365: return 0;
8366:
8367: case 0xE8: // no_op_xx
8368: return 0;
8369:
8370: case 0xE9: // no_op_xx
8371: return 0;
8372:
8373: case 0xEA: // no_op_xx
8374: return 0;
8375:
8376: case 0xEB: // no_op_xx
8377: return 0;
8378:
8379: case 0xEC: // no_op_xx
8380: return 0;
8381:
8382: case 0xED: // no_op_xx
8383: return 0;
8384:
8385: case 0xEE: // set_5_xix
8386: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 5));
8387: return 23;
8388:
8389: case 0xEF: // no_op_xx
8390: return 0;
8391:
8392: case 0xF0: // no_op_xx
8393: return 0;
8394:
8395: case 0xF1: // no_op_xx
8396: return 0;
8397:
8398: case 0xF2: // no_op_xx
8399: return 0;
8400:
8401: case 0xF3: // no_op_xx
8402: return 0;
8403:
8404: case 0xF4: // no_op_xx
8405: return 0;
8406:
8407: case 0xF5: // no_op_xx
8408: return 0;
8409:
8410: case 0xF6: // set_6_xix
8411: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 6));
8412: return 23;
8413:
8414: case 0xF7: // no_op_xx
8415: return 0;
8416:
8417: case 0xF8: // no_op_xx
8418: return 0;
8419:
8420: case 0xF9: // no_op_xx
8421: return 0;
8422:
8423: case 0xFA: // no_op_xx
8424: return 0;
8425:
8426: case 0xFB: // no_op_xx
8427: return 0;
8428:
8429: case 0xFC: // no_op_xx
8430: return 0;
8431:
8432: case 0xFD: // no_op_xx
8433: return 0;
8434:
8435: case 0xFE: // set_7_xix
8436: MemWriteByte(wAddr, Set(MemReadByte(wAddr), 7));
8437: return 23;
8438:
8439: case 0xFF: // no_op_x
8440: return 0;
8441:
8442: default:
8443: _ASSERT(FALSE);
8444: return 0;
8445: }
8446: }
8447:
8448: /* ***************************************************************************
8449: * Debugger shit
8450: * ***************************************************************************
8451: */
8452:
8453: /*** Z80Em: Portable Z80 emulator *******************************************/
8454: /*** ***/
8455: /*** Z80Dasm.h ***/
8456: /*** ***/
8457: /*** This file contains a routine to disassemble a buffer containing Z80 ***/
8458: /*** opcodes. It is included from Z80Debug.c and z80dasm.c ***/
8459: /*** ***/
8460: /*** Copyright (C) Marcel de Kogel 1996,1997 ***/
8461: /*** You are not allowed to distribute this software commercially ***/
8462: /*** Please, notify me, if you make any changes to this file ***/
8463: /****************************************************************************/
8464:
8465: #include <stdio.h>
8466: #include <string.h>
8467:
8468: static char *mnemonic_xx_cb[256]=
8469: {
8470: "#","#","#","#","#","#","rlc Y" ,"#",
8471: "#","#","#","#","#","#","rrc Y" ,"#",
8472: "#","#","#","#","#","#","rl Y" ,"#",
8473: "#","#","#","#","#","#","rr Y" ,"#",
8474: "#","#","#","#","#","#","sla Y" ,"#",
8475: "#","#","#","#","#","#","sra Y" ,"#",
8476: "#","#","#","#","#","#","sll Y" ,"#",
8477: "#","#","#","#","#","#","srl Y" ,"#",
8478: "#","#","#","#","#","#","bit 0,Y","#",
8479: "#","#","#","#","#","#","bit 1,Y","#",
8480: "#","#","#","#","#","#","bit 2,Y","#",
8481: "#","#","#","#","#","#","bit 3,Y","#",
8482: "#","#","#","#","#","#","bit 4,Y","#",
8483: "#","#","#","#","#","#","bit 5,Y","#",
8484: "#","#","#","#","#","#","bit 6,Y","#",
8485: "#","#","#","#","#","#","bit 7,Y","#",
8486: "#","#","#","#","#","#","res 0,Y","#",
8487: "#","#","#","#","#","#","res 1,Y","#",
8488: "#","#","#","#","#","#","res 2,Y","#",
8489: "#","#","#","#","#","#","res 3,Y","#",
8490: "#","#","#","#","#","#","res 4,Y","#",
8491: "#","#","#","#","#","#","res 5,Y","#",
8492: "#","#","#","#","#","#","res 6,Y","#",
8493: "#","#","#","#","#","#","res 7,Y","#",
8494: "#","#","#","#","#","#","set 0,Y","#",
8495: "#","#","#","#","#","#","set 1,Y","#",
8496: "#","#","#","#","#","#","set 2,Y","#",
8497: "#","#","#","#","#","#","set 3,Y","#",
8498: "#","#","#","#","#","#","set 4,Y","#",
8499: "#","#","#","#","#","#","set 5,Y","#",
8500: "#","#","#","#","#","#","set 6,Y","#",
8501: "#","#","#","#","#","#","set 7,Y","#"
8502: };
8503:
8504: static char *mnemonic_cb[256]=
8505: {
8506: "rlc b" ,"rlc c" ,"rlc d" ,"rlc e" ,"rlc h" ,"rlc l" ,"rlc (hl)" ,"rlc a" ,
8507: "rrc b" ,"rrc c" ,"rrc d" ,"rrc e" ,"rrc h" ,"rrc l" ,"rrc (hl)" ,"rrc a" ,
8508: "rl b" ,"rl c" ,"rl d" ,"rl e" ,"rl h" ,"rl l" ,"rl (hl)" ,"rl a" ,
8509: "rr b" ,"rr c" ,"rr d" ,"rr e" ,"rr h" ,"rr l" ,"rr (hl)" ,"rr a" ,
8510: "sla b" ,"sla c" ,"sla d" ,"sla e" ,"sla h" ,"sla l" ,"sla (hl)" ,"sla a" ,
8511: "sra b" ,"sra c" ,"sra d" ,"sra e" ,"sra h" ,"sra l" ,"sra (hl)" ,"sra a" ,
8512: "sll b" ,"sll c" ,"sll d" ,"sll e" ,"sll h" ,"sll l" ,"sll (hl)" ,"sll a" ,
8513: "srl b" ,"srl c" ,"srl d" ,"srl e" ,"srl h" ,"srl l" ,"srl (hl)" ,"srl a" ,
8514: "bit 0,b","bit 0,c","bit 0,d","bit 0,e","bit 0,h","bit 0,l","bit 0,(hl)","bit 0,a",
8515: "bit 1,b","bit 1,c","bit 1,d","bit 1,e","bit 1,h","bit 1,l","bit 1,(hl)","bit 1,a",
8516: "bit 2,b","bit 2,c","bit 2,d","bit 2,e","bit 2,h","bit 2,l","bit 2,(hl)","bit 2,a",
8517: "bit 3,b","bit 3,c","bit 3,d","bit 3,e","bit 3,h","bit 3,l","bit 3,(hl)","bit 3,a",
8518: "bit 4,b","bit 4,c","bit 4,d","bit 4,e","bit 4,h","bit 4,l","bit 4,(hl)","bit 4,a",
8519: "bit 5,b","bit 5,c","bit 5,d","bit 5,e","bit 5,h","bit 5,l","bit 5,(hl)","bit 5,a",
8520: "bit 6,b","bit 6,c","bit 6,d","bit 6,e","bit 6,h","bit 6,l","bit 6,(hl)","bit 6,a",
8521: "bit 7,b","bit 7,c","bit 7,d","bit 7,e","bit 7,h","bit 7,l","bit 7,(hl)","bit 7,a",
8522: "res 0,b","res 0,c","res 0,d","res 0,e","res 0,h","res 0,l","res 0,(hl)","res 0,a",
8523: "res 1,b","res 1,c","res 1,d","res 1,e","res 1,h","res 1,l","res 1,(hl)","res 1,a",
8524: "res 2,b","res 2,c","res 2,d","res 2,e","res 2,h","res 2,l","res 2,(hl)","res 2,a",
8525: "res 3,b","res 3,c","res 3,d","res 3,e","res 3,h","res 3,l","res 3,(hl)","res 3,a",
8526: "res 4,b","res 4,c","res 4,d","res 4,e","res 4,h","res 4,l","res 4,(hl)","res 4,a",
8527: "res 5,b","res 5,c","res 5,d","res 5,e","res 5,h","res 5,l","res 5,(hl)","res 5,a",
8528: "res 6,b","res 6,c","res 6,d","res 6,e","res 6,h","res 6,l","res 6,(hl)","res 6,a",
8529: "res 7,b","res 7,c","res 7,d","res 7,e","res 7,h","res 7,l","res 7,(hl)","res 7,a",
8530: "set 0,b","set 0,c","set 0,d","set 0,e","set 0,h","set 0,l","set 0,(hl)","set 0,a",
8531: "set 1,b","set 1,c","set 1,d","set 1,e","set 1,h","set 1,l","set 1,(hl)","set 1,a",
8532: "set 2,b","set 2,c","set 2,d","set 2,e","set 2,h","set 2,l","set 2,(hl)","set 2,a",
8533: "set 3,b","set 3,c","set 3,d","set 3,e","set 3,h","set 3,l","set 3,(hl)","set 3,a",
8534: "set 4,b","set 4,c","set 4,d","set 4,e","set 4,h","set 4,l","set 4,(hl)","set 4,a",
8535: "set 5,b","set 5,c","set 5,d","set 5,e","set 5,h","set 5,l","set 5,(hl)","set 5,a",
8536: "set 6,b","set 6,c","set 6,d","set 6,e","set 6,h","set 6,l","set 6,(hl)","set 6,a",
8537: "set 7,b","set 7,c","set 7,d","set 7,e","set 7,h","set 7,l","set 7,(hl)","set 7,a"
8538: };
8539:
8540: static char *mnemonic_ed[256]=
8541: {
8542: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8543: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8544: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8545: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8546: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8547: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8548: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8549: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8550: "in b,(c)","out (c),b","sbc hl,bc","ld (W),bc","neg","retn","im 0","ld i,a",
8551: "in c,(c)","out (c),c","adc hl,bc","ld bc,(W)","!" ,"reti","!" ,"ld r,a",
8552: "in d,(c)","out (c),d","sbc hl,de","ld (W),de","!" ,"!" ,"im 1","ld a,i",
8553: "in e,(c)","out (c),e","adc hl,de","ld de,(W)","!" ,"!" ,"im 2","ld a,r",
8554: "in h,(c)","out (c),h","sbc hl,hl","ld (W),hl","!" ,"!" ,"!" ,"rrd" ,
8555: "in l,(c)","out (c),l","adc hl,hl","ld hl,(W)","!" ,"!" ,"!" ,"rld" ,
8556: "in 0,(c)","out (c),0","sbc hl,sp","ld (W),sp","!" ,"!" ,"!" ,"!" ,
8557: "in a,(c)","out (c),a","adc hl,sp","ld sp,(W)","!" ,"!" ,"!" ,"!" ,
8558: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8559: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8560: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8561: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8562: "ldi" ,"cpi" ,"ini" ,"outi" ,"!" ,"!" ,"!" ,"!" ,
8563: "ldd" ,"cpd" ,"ind" ,"outd" ,"!" ,"!" ,"!" ,"!" ,
8564: "ldir" ,"cpir" ,"inir" ,"otir" ,"!" ,"!" ,"!" ,"!" ,
8565: "lddr" ,"cpdr" ,"indr" ,"otdr" ,"!" ,"!" ,"!" ,"!" ,
8566: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8567: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8568: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8569: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8570: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8571: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8572: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,
8573: "!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!" ,"!"
8574: };
8575:
8576: static char *mnemonic_xx[256]=
8577: {
8578: "@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8579: "@" ,"add I,bc","@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8580: "@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8581: "@" ,"add I,de","@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8582: "@" ,"ld I,W" ,"ld (W),I","inc I" ,"inc Ih" ,"dec Ih" ,"ld Ih,B","@" ,
8583: "@" ,"add I,I" ,"ld I,(W)","dec I" ,"inc Il" ,"dec Il" ,"ld Il,B","@" ,
8584: "@" ,"@" ,"@" ,"@" ,"inc X" ,"dec X" ,"ld X,B" ,"@" ,
8585: "@" ,"add I,sp","@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8586: "@" ,"@" ,"@" ,"@" ,"ld b,Ih" ,"ld b,Il" ,"ld b,X" ,"@" ,
8587: "@" ,"@" ,"@" ,"@" ,"ld c,Ih" ,"ld c,Il" ,"ld c,X" ,"@" ,
8588: "@" ,"@" ,"@" ,"@" ,"ld d,Ih" ,"ld d,Il" ,"ld d,X" ,"@" ,
8589: "@" ,"@" ,"@" ,"@" ,"ld e,Ih" ,"ld e,Il" ,"ld e,X" ,"@" ,
8590: "ld Ih,b","ld Ih,c" ,"ld Ih,d" ,"ld Ih,e" ,"ld Ih,h" ,"ld Ih,l" ,"ld h,X" ,"ld Ih,a",
8591: "ld Il,b","ld Il,c" ,"ld Il,d" ,"ld Il,e" ,"ld Il,h" ,"ld Il,l" ,"ld l,X" ,"ld Il,a",
8592: "ld X,b" ,"ld X,c" ,"ld X,d" ,"ld X,e" ,"ld X,h" ,"ld X,l" ,"@" ,"ld X,a" ,
8593: "@" ,"@" ,"@" ,"@" ,"ld a,Ih" ,"ld a,Il" ,"ld a,X" ,"@" ,
8594: "@" ,"@" ,"@" ,"@" ,"add a,Ih","add a,Il","add a,X","@" ,
8595: "@" ,"@" ,"@" ,"@" ,"adc a,Ih","adc a,Il","adc a,X","@" ,
8596: "@" ,"@" ,"@" ,"@" ,"sub Ih" ,"sub Il" ,"sub X" ,"@" ,
8597: "@" ,"@" ,"@" ,"@" ,"sbc a,Ih","sbc a,Il","sbc a,X","@" ,
8598: "@" ,"@" ,"@" ,"@" ,"and Ih" ,"and Il" ,"and X" ,"@" ,
8599: "@" ,"@" ,"@" ,"@" ,"xor Ih" ,"xor Il" ,"xor X" ,"@" ,
8600: "@" ,"@" ,"@" ,"@" ,"or Ih" ,"or Il" ,"or X" ,"@" ,
8601: "@" ,"@" ,"@" ,"@" ,"cp Ih" ,"cp Il" ,"cp X" ,"@" ,
8602: "@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8603: "@" ,"@" ,"@" ,"fd cb" ,"@" ,"@" ,"@" ,"@" ,
8604: "@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8605: "@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8606: "@" ,"pop I" ,"@" ,"ex (sp),I","@" ,"push I" ,"@" ,"@" ,
8607: "@" ,"jp (I)" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8608: "@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@" ,
8609: "@" ,"ld sp,I" ,"@" ,"@" ,"@" ,"@" ,"@" ,"@"
8610: };
8611:
8612: static char *mnemonic_main[256]=
8613: {
8614: "nop" ,"ld bc,W" ,"ld (bc),a","inc bc" ,"inc b" ,"dec b" ,"ld b,B" ,"rlca" ,
8615: "ex af,af'","add hl,bc","ld a,(bc)","dec bc" ,"inc c" ,"dec c" ,"ld c,B" ,"rrca" ,
8616: "djnz R" ,"ld de,W" ,"ld (de),a","inc de" ,"inc d" ,"dec d" ,"ld d,B" ,"rla" ,
8617: "jr R" ,"add hl,de","ld a,(de)","dec de" ,"inc e" ,"dec e" ,"ld e,B" ,"rra" ,
8618: "jr nz,R" ,"ld hl,W" ,"ld (W),hl","inc hl" ,"inc h" ,"dec h" ,"ld h,B" ,"daa" ,
8619: "jr z,R" ,"add hl,hl","ld hl,(W)","dec hl" ,"inc l" ,"dec l" ,"ld l,B" ,"cpl" ,
8620: "jr nc,R" ,"ld sp,W" ,"ld (W),a" ,"inc sp" ,"inc (hl)" ,"dec (hl)" ,"ld (hl),B" ,"scf" ,
8621: "jr c,R" ,"add hl,sp","ld a,(W)" ,"dec sp" ,"inc a" ,"dec a" ,"ld a,B" ,"ccf" ,
8622: "ld b,b" ,"ld b,c" ,"ld b,d" ,"ld b,e" ,"ld b,h" ,"ld b,l" ,"ld b,(hl)" ,"ld b,a" ,
8623: "ld c,b" ,"ld c,c" ,"ld c,d" ,"ld c,e" ,"ld c,h" ,"ld c,l" ,"ld c,(hl)" ,"ld c,a" ,
8624: "ld d,b" ,"ld d,c" ,"ld d,d" ,"ld d,e" ,"ld d,h" ,"ld d,l" ,"ld d,(hl)" ,"ld d,a" ,
8625: "ld e,b" ,"ld e,c" ,"ld e,d" ,"ld e,e" ,"ld e,h" ,"ld e,l" ,"ld e,(hl)" ,"ld e,a" ,
8626: "ld h,b" ,"ld h,c" ,"ld h,d" ,"ld h,e" ,"ld h,h" ,"ld h,l" ,"ld h,(hl)" ,"ld h,a" ,
8627: "ld l,b" ,"ld l,c" ,"ld l,d" ,"ld l,e" ,"ld l,h" ,"ld l,l" ,"ld l,(hl)" ,"ld l,a" ,
8628: "ld (hl),b","ld (hl),c","ld (hl),d","ld (hl),e" ,"ld (hl),h","ld (hl),l","halt" ,"ld (hl),a",
8629: "ld a,b" ,"ld a,c" ,"ld a,d" ,"ld a,e" ,"ld a,h" ,"ld a,l" ,"ld a,(hl)" ,"ld a,a" ,
8630: "add a,b" ,"add a,c" ,"add a,d" ,"add a,e" ,"add a,h" ,"add a,l" ,"add a,(hl)","add a,a" ,
8631: "adc a,b" ,"adc a,c" ,"adc a,d" ,"adc a,e" ,"adc a,h" ,"adc a,l" ,"adc a,(hl)","adc a,a" ,
8632: "sub b" ,"sub c" ,"sub d" ,"sub e" ,"sub h" ,"sub l" ,"sub (hl)" ,"sub a" ,
8633: "sbc a,b" ,"sbc a,c" ,"sbc a,d" ,"sbc a,e" ,"sbc a,h" ,"sbc a,l" ,"sbc a,(hl)","sbc a,a" ,
8634: "and b" ,"and c" ,"and d" ,"and e" ,"and h" ,"and l" ,"and (hl)" ,"and a" ,
8635: "xor b" ,"xor c" ,"xor d" ,"xor e" ,"xor h" ,"xor l" ,"xor (hl)" ,"xor a" ,
8636: "or b" ,"or c" ,"or d" ,"or e" ,"or h" ,"or l" ,"or (hl)" ,"or a" ,
8637: "cp b" ,"cp c" ,"cp d" ,"cp e" ,"cp h" ,"cp l" ,"cp (hl)" ,"cp a" ,
8638: "ret nz" ,"pop bc" ,"jp nz,W" ,"jp W" ,"call nz,W","push bc" ,"add a,B" ,"rst 00h" ,
8639: "ret z" ,"ret" ,"jp z,W" ,"cb" ,"call z,W" ,"call W" ,"adc a,B" ,"rst 08h" ,
8640: "ret nc" ,"pop de" ,"jp nc,W" ,"out (B),a" ,"call nc,W","push de" ,"sub B" ,"rst 10h" ,
8641: "ret c" ,"exx" ,"jp c,W" ,"in a,(B)" ,"call c,W" ,"dd" ,"sbc a,B" ,"rst 18h" ,
8642: "ret po" ,"pop hl" ,"jp po,W" ,"ex (sp),hl","call po,W","push hl" ,"and B" ,"rst 20h" ,
8643: "ret pe" ,"jp (hl)" ,"jp pe,W" ,"ex de,hl" ,"call pe,W","ed" ,"xor B" ,"rst 28h" ,
8644: "ret p" ,"pop af" ,"jp p,W" ,"di" ,"call p,W" ,"push af" ,"or B" ,"rst 30h" ,
8645: "ret m" ,"ld sp,hl" ,"jp m,W" ,"ei" ,"call m,W" ,"fd" ,"cp B" ,"rst 38h"
8646: };
8647:
8648: static char Sign (unsigned char a)
8649: {
8650: return (a&128)? '-':'+';
8651: }
8652:
8653: static int Abs (unsigned char a)
8654: {
8655: if (a&128) return 256-a;
8656: else return a;
8657: }
8658:
8659: /****************************************************************************/
8660: /* Disassemble first opcode in buffer and return number of bytes it takes */
8661: /****************************************************************************/
8662: int Z80_Dasm (unsigned char *buffer,char *dest,unsigned PC) {
8663: char *S;
8664: char *r;
8665: int i,j,k;
8666: unsigned char buf[10];
8667: char Offset;
8668: i=Offset=0;
8669: r="INTERNAL PROGRAM ERROR";
8670: dest[0]='\0';
8671: switch (buffer[i])
8672: {
8673: case 0xCB:
8674: i++;
8675: S=mnemonic_cb[buffer[i++]];
8676: break;
8677: case 0xED:
8678: i++;
8679: S=mnemonic_ed[buffer[i++]];
8680: break;
8681: case 0xDD:
8682: i++;
8683: r="ix";
8684: switch (buffer[i])
8685: {
8686: case 0xcb:
8687: i++;
8688: Offset=buffer[i++];
8689: S=mnemonic_xx_cb[buffer[i++]];
8690: break;
8691: default:
8692: S=mnemonic_xx[buffer[i++]];
8693: break;
8694: }
8695: break;
8696: case 0xFD:
8697: i++;
8698: r="iy";
8699: switch (buffer[i])
8700: {
8701: case 0xcb:
8702: i++;
8703: Offset=buffer[i++];
8704: S=mnemonic_xx_cb[buffer[i++]];
8705: break;
8706: default:
8707: S=mnemonic_xx[buffer[i++]];
8708: break;
8709: }
8710: break;
8711: default:
8712: S=mnemonic_main[buffer[i++]];
8713: break;
8714: }
8715: for (j=0;S[j];++j)
8716: {
8717: switch (S[j])
8718: {
8719: case 'B':
8720: sprintf (buf,"$%02x",buffer[i++]);
8721: strcat (dest,buf);
8722: break;
8723: case 'R':
8724: sprintf (buf,"$%04x",(PC+2+(signed char)buffer[i])&0xFFFF);
8725: i++;
8726: strcat (dest,buf);
8727: break;
8728: case 'W':
8729: sprintf (buf,"$%04x",buffer[i]+buffer[i+1]*256);
8730: i+=2;
8731: strcat (dest,buf);
8732: break;
8733: case 'X':
8734: sprintf (buf,"(%s%c$%02x)",r,Sign(buffer[i]),Abs(buffer[i]));
8735: i++;
8736: strcat (dest,buf);
8737: break;
8738: case 'Y':
8739: sprintf (buf,"(%s%c$%02x)",r,Sign(Offset),Abs(Offset));
8740: strcat (dest,buf);
8741: break;
8742: case 'I':
8743: strcat (dest,r);
8744: break;
8745: case '!':
8746: sprintf (dest,"db $ed,$%02x",buffer[1]);
8747: return 2;
8748: case '@':
8749: sprintf (dest,"db $%02x",buffer[0]);
8750: return 1;
8751: case '#':
8752: sprintf (dest,"db $%02x,$cb,$%02x",buffer[0],buffer[2]);
8753: return 2;
8754: case ' ':
8755: k=strlen(dest);
8756: if (k<6) k=7-k;
8757: else k=1;
8758: memset (buf,' ',k);
8759: buf[k]='\0';
8760: strcat (dest,buf);
8761: break;
8762: default:
8763: buf[0]=S[j];
8764: buf[1]='\0';
8765: strcat (dest,buf);
8766: break;
8767: }
8768: }
8769: return i;
8770: }
8771:
8772: UINT32 mz80GetElapsedTicks(UINT32 dwClearIt)
8773: {
8774: UINT32 dwTempVar = 0;
8775: char string[150];
8776:
8777: dwTempVar = dwElapsedTicks;
8778: if (dwClearIt)
8779: dwElapsedTicks = 0;
8780: return(dwTempVar);
8781: }
8782:
8783: void mz80ReleaseTimeslice()
8784: {
8785: cCycles = 0;
8786: }
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