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1.1 root 1: ; instruction
2: ; -----------
3: ; 0 - bit 0
4: ; 1 - bit 1
5: ; i - immediate data
6: ; n - register
7: ; N - register II
8: ; e - EA mode
9: ; E - EA reg
10: ; f - EA mode II
11: ; F - EA reg II
12: ; z - size
13: ; x - not important
14:
15: ; flags
16: ; -----
17: ; two flags, the first is whether the instruction is a
18: ; privileged one:
19: ; 0 - normal
20: ; 1 - only when in supervisor mode
21: ; the second is whether the instruction ends a block:
22: ; 0 - does not affect PC
23: ; 1 - affects PC
24:
25: ; used/set flags
26: ; --------------
27: ; used flags - flags which the instruction may look at
28: ; set flags - flags which the instruction may set
29: ; 0 - clear
30: ; 1 - set
31: ; all else means that flag is used or set
32:
33: ; assembler syntax
34: ; ----------------
35: ;
36: ; name.size source, destination
37: ;
38: ; source and destination can be one of:
39: ; #z - immediate data of size specified in instruction
40: ; #B,#W/#L - immediate data byte/word/long
41: ; #i - immedaite data within instruction
42: ; #I - immediate data within instruction, excluding 0.
43: ; #s - immediate data within instruction sign extended
44: ; e(...)/f(...) - effective address (see keywords below)
45: ; or one of below:
46:
47: ; for dddDDD/sssSSS modes the following define what modes can be used:
48: ; Dreg - Data register direct (000/register)
49: ; Areg - Address register direct (001/register)
50: ; Aind - Address register indirect (010/register)
51: ; Ainc - Address register indirect postincrement (011/register)
52: ; Adec - Address register indirect predecrement (100/register)
53: ; Adis - Address regsiter indirect with displacement (101/register)
54: ; Aidx - Address register indirect with index (110/register)
55: ; AbsW - Absolute word (111/000)
56: ; AbsL - Absolute long (111/001)
57: ; Pdis - PC with displacement (111/010)
58: ; Pidx - PC with index (111/011)
59: ; Imm - Immediate data (111/100)
60:
61: ; * is an alias for all possible modes (default if no qualifier)
62: ; PC is an alias for either Pdis or Pidx.
63: ; Regs is an alias for either Dreg or Areg.
64: ; Amod is an alias for either Ainc or Adec.
65:
66: ; instruction flags used set name[.size][ src[,dst]]
67:
68: 0000 0000 zz eee EEE 0 0 ----- -NZ00 OR.z #z,e(*,-Areg,-Imm,-PC)
69: 0000 0000 00 111 100 0 0 XNZVC ----- ORSR.B #B
70: 0000 0000 01 111 100 1 0 XNZVC ----- ORSR.W #W
71:
72: 0000 0010 zz eee EEE 0 0 ----- -NZ00 AND.z #z,e(*,-Areg,-Imm,-PC)
73: 0000 0010 00 111 100 0 0 XNZVC ----- ANDSR.B #B
74: 0000 0010 01 111 100 1 0 XNZVC ----- ANDSR.W #W
75:
76: 0000 0100 zz eee EEE 0 0 ----- XNZVC SUB.z #z,e(*,-Areg,-Imm,-PC)
77: 0000 0110 zz eee EEE 0 0 ----- XNZVC ADD.z #z,e(*,-Areg,-Imm,-PC)
78:
79: 0000 1000 00 eee EEE 0 0 ----- --Z-- BTST.B #B,e(*,-Regs,-Imm)
80: 0000 1000 01 eee EEE 0 0 ----- --Z-- BCHG.B #B,e(*,-Regs,-Imm,-PC)
81: 0000 1000 10 eee EEE 0 0 ----- --Z-- BCLR.B #B,e(*,-Regs,-Imm,-PC)
82: 0000 1000 11 eee EEE 0 0 ----- --Z-- BSET.B #B,e(*,-Regs,-Imm,-PC)
83: 0000 1000 00 eee EEE 0 0 ----- --Z-- BTST.L #B,e(Dreg)
84: 0000 1000 01 eee EEE 0 0 ----- --Z-- BCHG.L #B,e(Dreg)
85: 0000 1000 10 eee EEE 0 0 ----- --Z-- BCLR.L #B,e(Dreg)
86: 0000 1000 11 eee EEE 0 0 ----- --Z-- BSET.L #B,e(Dreg)
87:
88: 0000 1010 00 111 100 0 0 XNZVC ----- EORSR.B #B
89: 0000 1010 01 111 100 1 0 XNZVC ----- EORSR.W #W
90: 0000 1010 zz eee EEE 0 0 ----- -NZ00 EOR.z #z,e(*,-Areg,-Imm,-PC)
91: 0000 1100 zz eee EEE 0 0 ----- -NZVC CMP.z #z,e(*,-Areg,-Imm,-PC)
92:
93: 0000 nnn1 00 001 NNN 0 0 ----- ----- MOVEPMR.W N(Adis),n(Dreg)
94: 0000 nnn1 01 001 NNN 0 0 ----- ----- MOVEPMR.L N(Adis),n(Dreg)
95: 0000 nnn1 10 001 NNN 0 0 ----- ----- MOVEPRM.W n(Dreg),N(Adis)
96: 0000 nnn1 11 001 NNN 0 0 ----- ----- MOVEPRM.L n(Dreg),N(Adis)
1.1.1.2 ! root 97: ; you can do BTST Dx, #nnnn (bit-pos in reg) - weirdo instruction
! 98: 0000 nnn1 00 eee EEE 0 0 ----- --Z-- BTST.B n(Dreg),e(*,-Regs)
1.1 root 99: 0000 nnn1 01 eee EEE 0 0 ----- --Z-- BCHG.B n(Dreg),e(*,-Regs,-Imm,-PC)
100: 0000 nnn1 10 eee EEE 0 0 ----- --Z-- BCLR.B n(Dreg),e(*,-Regs,-Imm,-PC)
101: 0000 nnn1 11 eee EEE 0 0 ----- --Z-- BSET.B n(Dreg),e(*,-Regs,-Imm,-PC)
102: 0000 nnn1 00 eee EEE 0 0 ----- --Z-- BTST.L n(Dreg),e(Dreg)
103: 0000 nnn1 01 eee EEE 0 0 ----- --Z-- BCHG.L n(Dreg),e(Dreg)
104: 0000 nnn1 10 eee EEE 0 0 ----- --Z-- BCLR.L n(Dreg),e(Dreg)
105: 0000 nnn1 11 eee EEE 0 0 ----- --Z-- BSET.L n(Dreg),e(Dreg)
106:
107: 0001 FFF fff eee EEE 0 0 ----- -NZ00 MOVE.B e(*),f(*,-Areg,-Imm,-PC)
108: 0010 FFF fff eee EEE 0 0 ----- -NZ00 MOVE.L e(*),f(*,-Areg,-Imm,-PC)
109: 0010 FFF fff eee EEE 0 0 ----- ----- MOVE.L e(*),f(Areg)
110: 0011 FFF fff eee EEE 0 0 ----- -NZ00 MOVE.W e(*),f(*,-Areg,-Imm,-PC)
111: 0011 FFF fff eee EEE 0 0 ----- ----- MOVEA.W e(*),f(Areg)
112:
113: 0100 0000 zz eee EEE 0 0 ----- XNZVC NEGX.z e(*,-Areg,-Imm,-PC)
114: 0100 0010 zz eee EEE 0 0 -0100 XNZVC CLR.z e(*,-Areg,-Imm,-PC)
115: 0100 0100 zz eee EEE 0 0 ----- XNZVC NEG.z e(*,-Areg,-Imm,-PC)
116: 0100 0110 zz eee EEE 0 0 ----- -NZ00 NOT.z e(*,-Areg,-Imm,-PC)
117: 0100 0000 11 eee EEE 0 0 XNZVC ----- MOVEFSR.W e(*,-Areg,-Imm,-PC)
118: 0100 0100 11 eee EEE 0 0 ----- XNZVC MOVETSR.B e(*,-Areg)
119: 0100 0110 11 eee EEE 1 0 ----- XNZVC MOVETSR.W e(*,-Areg)
120:
1.1.1.2 ! root 121: 0100 1000 00 eee EEE 0 0 X---- XNZVC NBCD.B e(*,-Areg,-Imm,-PC)
1.1 root 122: 0100 1000 01 eee EEE 0 0 ----- -NZ00 SWAP.L e(Dreg)
123: 0100 1000 01 eee EEE 0 0 ----- ----- PEA.L e(*,-Regs,-Imm,-Amod)
124: 0100 1000 10 eee EEE 0 0 ----- -NZ00 EXT.W e(Dreg)
125: 0100 1000 10 eee EEE 0 0 ----- ----- MOVEMRM.W #W,e(*,-Regs,-Ainc,-Imm,-PC)
126: 0100 1000 11 eee EEE 0 0 ----- -NZ00 EXT.L e(Dreg)
127: 0100 1000 11 eee EEE 0 0 ----- ----- MOVEMRM.L #W,e(*,-Regs,-Ainc,-Imm,-PC)
128: 0100 1010 zz eee EEE 0 0 ----- -NZ00 TST.z e(*,-Areg,-Imm,-PC)
129: 0100 1010 11 eee EEE 0 0 ----- -NZ00 TAS.B e(*,-Areg,-Imm,-PC)
130: 0100 1010 11 111 100 0 1 ----- ----- ILLEGAL
131:
132: 0100 1100 10 eee EEE 0 0 ----- ----- MOVEMMR.W #W,e(*,-Regs,-Adec,-Imm)
133: 0100 1100 11 eee EEE 0 0 ----- ----- MOVEMMR.L #W,e(*,-Regs,-Adec,-Imm)
134:
135: 0100 1110 01 00 iiii 0 1 XNZVC ----- TRAP #i
136: 0100 1110 01 01 0nnn 0 0 ----- ----- LINK.L #W,n(Areg)
137: 0100 1110 01 01 1nnn 0 0 ----- ----- UNLK.L n(Areg)
138: 0100 1110 01 10 0nnn 0 0 ----- ----- MOVETUSP.L n(Areg)
139: 0100 1110 01 10 1nnn 0 0 ----- ----- MOVEFUSP.L n(Areg)
140:
141: 0100 1110 01 11 0000 1 1 ----- ----- RESET
142: 0100 1110 01 11 0001 0 0 ----- ----- NOP
143: 0100 1110 01 11 0010 1 1 ----- XNZVC STOP #W
144: 0100 1110 01 11 0011 1 1 ----- XNZVC RTE
145: 0100 1110 01 11 0101 0 1 ----- ----- RTS
146: 0100 1110 01 11 0110 0 1 ---V- ----- TRAPV
147: 0100 1110 01 11 0111 0 1 ----- XNZVC RTR
148: 0100 1110 10 eee EEE 0 1 ----- ----- JSR.L e(*,-Regs,-Amod,-Imm)
149: 0100 1110 11 eee EEE 0 1 ----- ----- JMP.L e(*,-Regs,-Amod,-Imm)
150: 0100 nnn1 10 eee EEE 0 0 ----- -Nxxx CHK.W e(*,-Areg),n(Dreg)
151: 0100 nnn1 11 eee EEE 0 0 ----- ----- LEA.L e(*,-Regs,-Amod,-Imm),n(Areg)
152:
153: 0101 iii0 zz eee EEE 0 0 ----- XNZVC ADD.z #I,e(*,-Areg,-PC,-Imm)
154: 0101 iii0 01 eee EEE 0 0 ----- ----- ADDA.W #I,e(Areg)
155: 0101 iii0 10 eee EEE 0 0 ----- ----- ADDA.L #I,e(Areg)
156: 0101 iii1 zz eee EEE 0 0 ----- XNZVC SUB.z #I,e(*,-Areg,-PC,-Imm)
157: 0101 iii1 01 eee EEE 0 0 ----- ----- SUBA.L #I,e(Areg)
158: 0101 iii1 10 eee EEE 0 0 ----- ----- SUBA.L #I,e(Areg)
159:
160: 0101 0000 zz eee EEE 0 0 ----- XNZVC ADD.z #8,e(*,-Areg,-PC,-Imm)
161: 0101 0000 01 eee EEE 0 0 ----- ----- ADDA.W #8,e(Areg)
162: 0101 0000 10 eee EEE 0 0 ----- ----- ADDA.L #8,e(Areg)
163: 0101 0001 zz eee EEE 0 0 ----- XNZVC SUB.z #8,e(*,-Areg,-PC,-Imm)
164: 0101 0001 01 eee EEE 0 0 ----- ----- SUBA.L #8,e(Areg)
165: 0101 0001 10 eee EEE 0 0 ----- ----- SUBA.L #8,e(Areg)
166:
167: 0101 cccc 11 eee EEE 0 0 XNZVC ----- Scc.B e(*,-Areg,-PC,-Imm)
168: 0101 0001 11 eee EEE 0 0 XNZVC ----- SF.B e(*,-Areg,-PC,-Imm)
169: 0101 cccc 11 001 nnn 0 1 XNZVC ----- DBcc.W #W,n(Dreg)
170: 0101 0001 11 001 nnn 0 1 XNZVC ----- DBRA.W #W,n(Dreg)
171:
172: 0110 cccc 0000 0000 0 1 XNZVC ----- Bcc.W #W
173: 0110 0001 0000 0000 0 1 XNZVC ----- BSR.W #W
174: 0110 cccc iiii iiii 0 1 XNZVC ----- Bcc.B #I
175: 0110 0001 iiii iiii 0 1 XNZVC ----- BSR.B #I
176:
177: 0111 nnn0 iiii iiii 0 0 ----- -NZ00 MOVE.L #s,n(Dreg)
178:
179: 1000 nnn0 zz eee EEE 0 0 ----- -NZ00 OR.z e(*,-Areg),n(Dreg)
180: 1000 nnn1 zz eee EEE 0 0 ----- -NZ00 OR.z n(Dreg),e(*,-Regs,-PC,-Imm)
181: 1000 nnn0 11 eee EEE 0 0 ----- -NZ0C DIVU.W e(*,-Areg),n(Dreg)
182: 1000 nnn1 11 eee EEE 0 0 ----- -NZ0C DIVS.W e(*,-Areg),n(Dreg)
1.1.1.2 ! root 183: 1000 nnn1 00 000 NNN 0 0 X-Z-- XNZVC SBCD.B N(Dreg),n(Dreg)
! 184: 1000 nnn1 00 001 NNN 0 0 X-Z-- XNZVC SBCD.B N(Adec),n(Adec)
1.1 root 185:
186: 1001 nnn0 zz eee EEE 0 0 ----- XNZVC SUB.z e(*),n(Dreg)
187: 1001 nnn1 zz eee EEE 0 0 ----- XNZVC SUB.z n(Dreg),e(*,-Regs,-PC,-Imm)
188: 1001 nnn0 11 eee EEE 0 0 ----- ----- SUBA.W e(*),n(Areg)
189: 1001 nnn1 11 eee EEE 0 0 ----- ----- SUBA.L e(*),n(Areg)
190: 1001 nnn1 zz 000 NNN 0 0 X-Z-- XNZVC SUBX.z N(Dreg),n(Dreg)
191: 1001 nnn1 zz 001 NNN 0 0 X-Z-- XNZVC SUBX.z N(Adec),n(Adec)
192:
193: 1011 nnn0 zz eee EEE 0 0 ----- -NZVC CMP.z e(*),n(Dreg)
194: 1011 nnn0 11 eee EEE 0 0 ----- -NZVC CMPA.W e(*),n(Areg)
195: 1011 nnn1 zz eee EEE 0 0 ----- -NZ00 EOR.z n(Dreg),e(*,-Areg,-PC,-Imm)
196: 1011 nnn1 zz 001 NNN 0 0 ----- -NZVC CMP.z N(Ainc),n(Ainc)
197: 1011 nnn1 11 eee EEE 0 0 ----- -NZVC CMP.L e(*),n(Areg)
198:
199: 1100 nnn0 zz eee EEE 0 0 ----- -NZ00 AND.z e(*,-Areg),n(Dreg)
200: 1100 nnn1 zz eee EEE 0 0 ----- -NZ00 AND.z n(Dreg),e(*,-Regs,-PC,-Imm)
201: 1100 nnn0 11 eee EEE 0 0 ----- -NZ00 MULU.W e(*,-Areg),n(Dreg)
202: 1100 nnn1 11 eee EEE 0 0 ----- -NZ00 MULS.W e(*,-Areg),n(Dreg)
1.1.1.2 ! root 203: 1100 nnn1 00 000 NNN 0 0 X-Z-- XNZVC ABCD.B N(Dreg),n(Dreg)
! 204: 1100 nnn1 00 001 NNN 0 0 X-Z-- XNZVC ABCD.B N(Adec),n(Adec)
1.1 root 205: 1100 nnn1 01 000 NNN 0 0 ----- ----- EXG.L N(Dreg),n(Dreg)
206: 1100 nnn1 01 001 NNN 0 0 ----- ----- EXG.L N(Areg),n(Areg)
207: 1100 nnn1 10 001 NNN 0 0 ----- ----- EXG.L n(Dreg),N(Areg)
208:
209: 1101 nnn0 zz eee EEE 0 0 ----- XNZVC ADD.z e(*),n(Dreg)
210: 1101 nnn1 zz eee EEE 0 0 ----- XNZVC ADD.z n(Dreg),e(*,-Regs,-PC,-Imm)
211: 1101 nnn0 11 eee EEE 0 0 ----- ----- ADDA.W e(*),n(Areg)
212: 1101 nnn1 11 eee EEE 0 0 ----- ----- ADDA.L e(*),n(Areg)
213: 1101 nnn1 zz 000 NNN 0 0 X-Z-- XNZVC ADDX.z N(Dreg),n(Dreg)
214: 1101 nnn1 zz 001 NNN 0 0 X-Z-- XNZVC ADDX.z N(Adec),n(Adec)
215:
216: 1110 iii0 zz 0 00 nnn 0 0 ----- XNZ0C ASR.z #I,n(Dreg)
217: 1110 iii0 zz 0 01 nnn 0 0 ----- XNZ0C LSR.z #I,n(Dreg)
218: 1110 iii0 zz 0 10 nnn 0 0 X---- XNZ0C ROXR.z #I,n(Dreg)
219: 1110 iii0 zz 0 11 nnn 0 0 ----- -NZ0C ROR.z #I,n(Dreg)
220: 1110 0000 zz 0 00 nnn 0 0 ----- XNZ0C ASR.z #8,n(Dreg)
221: 1110 0000 zz 0 01 nnn 0 0 ----- XNZ0C LSR.z #8,n(Dreg)
222: 1110 0000 zz 0 10 nnn 0 0 X---- XNZ0C ROXR.z #8,n(Dreg)
223: 1110 0000 zz 0 11 nnn 0 0 ----- -NZ0C ROR.z #8,n(Dreg)
224: 1110 NNN0 zz 1 00 nnn 0 0 ----- XNZVC ASR.z N(Dreg),n(Dreg)
225: 1110 NNN0 zz 1 01 nnn 0 0 ----- XNZ0C LSR.z N(Dreg),n(Dreg)
226: 1110 NNN0 zz 1 10 nnn 0 0 X---- XNZ0C ROXR.z N(Dreg),n(Dreg)
227: 1110 NNN0 zz 1 11 nnn 0 0 ----- -NZ0C ROR.z N(Dreg),n(Dreg)
228:
229: 1110 iii1 zz 0 00 nnn 0 0 ----- XNZ0C ASL.z #I,n(Dreg)
230: 1110 iii1 zz 0 01 nnn 0 0 ----- XNZ0C LSL.z #I,n(Dreg)
231: 1110 iii1 zz 0 10 nnn 0 0 X---- XNZ0C ROXL.z #I,n(Dreg)
232: 1110 iii1 zz 0 11 nnn 0 0 ----- -NZ0C ROL.z #I,n(Dreg)
233: 1110 0001 zz 0 00 nnn 0 0 ----- XNZ0C ASL.z #8,n(Dreg)
234: 1110 0001 zz 0 01 nnn 0 0 ----- XNZ0C LSL.z #8,n(Dreg)
235: 1110 0001 zz 0 10 nnn 0 0 X---- XNZ0C ROXL.z #8,n(Dreg)
236: 1110 0001 zz 0 11 nnn 0 0 ----- -NZ0C ROL.z #8,n(Dreg)
237: 1110 NNN1 zz 1 00 nnn 0 0 ----- XNZVC ASL.z N(Dreg),n(Dreg)
238: 1110 NNN1 zz 1 01 nnn 0 0 ----- XNZ0C LSL.z N(Dreg),n(Dreg)
239: 1110 NNN1 zz 1 10 nnn 0 0 X---- XNZ0C ROXL.z N(Dreg),n(Dreg)
240: 1110 NNN1 zz 1 11 nnn 0 0 ----- -NZ0C ROL.z N(Dreg),n(Dreg)
241:
242: 1110 0000 11 eee EEE 0 0 ----- XNZVC ASR.W #1,e(*,-Regs,-PC,-Imm)
243: 1110 0010 11 eee EEE 0 0 ----- XNZ0C LSR.W #1,e(*,-Regs,-PC,-Imm)
244: 1110 0100 11 eee EEE 0 0 X---- XNZ0C ROXR.W #1,e(*,-Regs,-PC,-Imm)
245: 1110 0110 11 eee EEE 0 0 ----- -NZ0C ROR.W #1,e(*,-Regs,-PC,-Imm)
246:
247: 1110 0001 11 eee EEE 0 0 ----- XNZVC ASL.W #1,e(*,-Regs,-PC,-Imm)
248: 1110 0011 11 eee EEE 0 0 ----- XNZ0C LSL.W #1,e(*,-Regs,-PC,-Imm)
249: 1110 0101 11 eee EEE 0 0 X---- XNZ0C ROXL.W #1,e(*,-Regs,-PC,-Imm)
250: 1110 0111 11 eee EEE 0 0 ----- -NZ0C ROL.W #1,e(*,-Regs,-PC,-Imm)
251:
252: 1010 VVVV VVVV VVVV 0 1 XNZVC ----- LINE10 #V
253: 1111 VVVV VVVV VVVV 0 1 XNZVC ----- LINE15 #V
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