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1.1 root 1: /* Generator is (c) James Ponder, 1997-2001 http://www.squish.net/generator/ */
2:
3: #include <stdio.h>
4:
5: #include "generator.h"
6: #include "cpu68k.h"
7: #include "mem68k.h"
8: #include "vdp.h"
9: #include "cpuz80.h"
10: #include "gensound.h"
11: #include "ui.h"
12:
13: #undef DEBUG_VDP
14: #undef DEBUG_BUS
15: #undef DEBUG_SRAM
16: #undef DEBUG_RAM
17: #undef DEBUG_BANK
18:
19: /*** forward references ***/
20:
21: uint8 *mem68k_memptr_bad(uint32 addr);
22: uint8 *mem68k_memptr_rom(uint32 addr);
23: uint8 *mem68k_memptr_ram(uint32 addr);
24:
1.1.1.2 root 25: uint8 mem68k_fetch_bad_byte(uint32 addr);
1.1 root 26: uint16 mem68k_fetch_bad_word(uint32 addr);
27: uint32 mem68k_fetch_bad_long(uint32 addr);
1.1.1.2 root 28: uint8 mem68k_fetch_rom_byte(uint32 addr);
1.1 root 29: uint16 mem68k_fetch_rom_word(uint32 addr);
30: uint32 mem68k_fetch_rom_long(uint32 addr);
1.1.1.2 root 31: uint8 mem68k_fetch_sram_byte(uint32 addr);
1.1 root 32: uint16 mem68k_fetch_sram_word(uint32 addr);
33: uint32 mem68k_fetch_sram_long(uint32 addr);
1.1.1.2 root 34: uint8 mem68k_fetch_yam_byte(uint32 addr);
1.1 root 35: uint16 mem68k_fetch_yam_word(uint32 addr);
36: uint32 mem68k_fetch_yam_long(uint32 addr);
1.1.1.2 root 37: uint8 mem68k_fetch_bank_byte(uint32 addr);
1.1 root 38: uint16 mem68k_fetch_bank_word(uint32 addr);
39: uint32 mem68k_fetch_bank_long(uint32 addr);
1.1.1.2 root 40: uint8 mem68k_fetch_io_byte(uint32 addr);
1.1 root 41: uint16 mem68k_fetch_io_word(uint32 addr);
42: uint32 mem68k_fetch_io_long(uint32 addr);
1.1.1.2 root 43: uint8 mem68k_fetch_ctrl_byte(uint32 addr);
1.1 root 44: uint16 mem68k_fetch_ctrl_word(uint32 addr);
45: uint32 mem68k_fetch_ctrl_long(uint32 addr);
1.1.1.2 root 46: uint8 mem68k_fetch_vdp_byte(uint32 addr);
1.1 root 47: uint16 mem68k_fetch_vdp_word(uint32 addr);
48: uint32 mem68k_fetch_vdp_long(uint32 addr);
1.1.1.2 root 49: uint8 mem68k_fetch_ram_byte(uint32 addr);
1.1 root 50: uint16 mem68k_fetch_ram_word(uint32 addr);
51: uint32 mem68k_fetch_ram_long(uint32 addr);
52:
1.1.1.2 root 53: void mem68k_store_bad_byte(uint32 addr, uint8 data);
54: void mem68k_store_bad_word(uint32 addr, uint16 data);
55: void mem68k_store_bad_long(uint32 addr, uint32 data);
56: void mem68k_store_rom_byte(uint32 addr, uint8 data);
57: void mem68k_store_rom_word(uint32 addr, uint16 data);
58: void mem68k_store_rom_long(uint32 addr, uint32 data);
59: void mem68k_store_sram_byte(uint32 addr, uint8 data);
1.1 root 60: void mem68k_store_sram_word(uint32 addr, uint16 data);
61: void mem68k_store_sram_long(uint32 addr, uint32 data);
1.1.1.2 root 62: void mem68k_store_yam_byte(uint32 addr, uint8 data);
63: void mem68k_store_yam_word(uint32 addr, uint16 data);
64: void mem68k_store_yam_long(uint32 addr, uint32 data);
65: void mem68k_store_bank_byte(uint32 addr, uint8 data);
1.1 root 66: void mem68k_store_bank_word(uint32 addr, uint16 data);
67: void mem68k_store_bank_long(uint32 addr, uint32 data);
1.1.1.2 root 68: void mem68k_store_io_byte(uint32 addr, uint8 data);
69: void mem68k_store_io_word(uint32 addr, uint16 data);
70: void mem68k_store_io_long(uint32 addr, uint32 data);
71: void mem68k_store_ctrl_byte(uint32 addr, uint8 data);
1.1 root 72: void mem68k_store_ctrl_word(uint32 addr, uint16 data);
73: void mem68k_store_ctrl_long(uint32 addr, uint32 data);
1.1.1.2 root 74: void mem68k_store_vdp_byte(uint32 addr, uint8 data);
75: void mem68k_store_vdp_word(uint32 addr, uint16 data);
76: void mem68k_store_vdp_long(uint32 addr, uint32 data);
77: void mem68k_store_ram_byte(uint32 addr, uint8 data);
78: void mem68k_store_ram_word(uint32 addr, uint16 data);
79: void mem68k_store_ram_long(uint32 addr, uint32 data);
80:
81: t_keys mem68k_cont[2];
1.1 root 82:
83: static uint8 mem68k_cont1ctrl;
84: static uint8 mem68k_cont2ctrl;
85: static uint8 mem68k_contEctrl;
86: static uint8 mem68k_cont1output;
87: static uint8 mem68k_cont2output;
88: static uint8 mem68k_contEoutput;
89:
90: /*** memory map ***/
91:
92: t_mem68k_def mem68k_def[] = {
93:
1.1.1.2 root 94: {0x000, 0x400, mem68k_memptr_rom,
95: mem68k_fetch_rom_byte, mem68k_fetch_rom_word, mem68k_fetch_rom_long,
96: mem68k_store_rom_byte, mem68k_store_rom_word, mem68k_store_rom_long},
97:
98: {0x400, 0x1000, mem68k_memptr_bad,
99: mem68k_fetch_bad_byte, mem68k_fetch_bad_word, mem68k_fetch_bad_long,
100: mem68k_store_bad_byte, mem68k_store_bad_word, mem68k_store_bad_long},
101:
102: {0xA00, 0xA10, mem68k_memptr_bad, /* note overlaps blocks below */
103: mem68k_fetch_sram_byte, mem68k_fetch_sram_word, mem68k_fetch_sram_long,
104: mem68k_store_sram_byte, mem68k_store_sram_word, mem68k_store_sram_long},
105:
106: {0xA04, 0xA05, mem68k_memptr_bad,
107: mem68k_fetch_yam_byte, mem68k_fetch_yam_word, mem68k_fetch_yam_long,
108: mem68k_store_yam_byte, mem68k_store_yam_word, mem68k_store_yam_long},
109:
110: {0xA06, 0xA07, mem68k_memptr_bad,
111: mem68k_fetch_bank_byte, mem68k_fetch_bank_word, mem68k_fetch_bank_long,
112: mem68k_store_bank_byte, mem68k_store_bank_word, mem68k_store_bank_long},
113:
114: {0xA0C, 0xA10, mem68k_memptr_bad, /* this is probably more yam/bank stuff */
115: mem68k_fetch_bad_byte, mem68k_fetch_bad_word, mem68k_fetch_bad_long,
116: mem68k_store_bad_byte, mem68k_store_bad_word, mem68k_store_bad_long},
117:
118: {0xA10, 0xA11, mem68k_memptr_bad,
119: mem68k_fetch_io_byte, mem68k_fetch_io_word, mem68k_fetch_io_long,
120: mem68k_store_io_byte, mem68k_store_io_word, mem68k_store_io_long},
121:
122: {0xA11, 0xA12, mem68k_memptr_bad,
123: mem68k_fetch_ctrl_byte, mem68k_fetch_ctrl_word, mem68k_fetch_ctrl_long,
124: mem68k_store_ctrl_byte, mem68k_store_ctrl_word, mem68k_store_ctrl_long},
125:
126: {0xC00, 0xC01, mem68k_memptr_bad,
127: mem68k_fetch_vdp_byte, mem68k_fetch_vdp_word, mem68k_fetch_vdp_long,
128: mem68k_store_vdp_byte, mem68k_store_vdp_word, mem68k_store_vdp_long},
129:
130: {0xE00, 0x1000, mem68k_memptr_ram,
131: mem68k_fetch_ram_byte, mem68k_fetch_ram_word, mem68k_fetch_ram_long,
132: mem68k_store_ram_byte, mem68k_store_ram_word, mem68k_store_ram_long},
1.1 root 133:
1.1.1.2 root 134: {0, 0, NULL, NULL, NULL, NULL, NULL, NULL, NULL}
1.1 root 135:
136: };
137:
1.1.1.2 root 138: uint8 *(*mem68k_memptr[0x1000]) (uint32 addr);
139: uint8 (*mem68k_fetch_byte[0x1000]) (uint32 addr);
140: uint16 (*mem68k_fetch_word[0x1000]) (uint32 addr);
141: uint32 (*mem68k_fetch_long[0x1000]) (uint32 addr);
142: void (*mem68k_store_byte[0x1000]) (uint32 addr, uint8 data);
143: void (*mem68k_store_word[0x1000]) (uint32 addr, uint16 data);
144: void (*mem68k_store_long[0x1000]) (uint32 addr, uint32 data);
1.1 root 145:
146: /*** initialise memory tables ***/
147:
148: int mem68k_init(void)
149: {
150: int i = 0;
151: int j;
152:
153: do {
154: for (j = mem68k_def[i].start; j < mem68k_def[i].end; j++) {
155: mem68k_memptr[j] = mem68k_def[i].memptr;
156: mem68k_fetch_byte[j] = mem68k_def[i].fetch_byte;
157: mem68k_fetch_word[j] = mem68k_def[i].fetch_word;
158: mem68k_fetch_long[j] = mem68k_def[i].fetch_long;
159: mem68k_store_byte[j] = mem68k_def[i].store_byte;
160: mem68k_store_word[j] = mem68k_def[i].store_word;
161: mem68k_store_long[j] = mem68k_def[i].store_long;
162: }
163: i++;
1.1.1.2 root 164: }
165: while ((mem68k_def[i].start != 0) || (mem68k_def[i].end != 0));
1.1 root 166: mem68k_cont1ctrl = 0;
167: mem68k_cont2ctrl = 0;
168: mem68k_contEctrl = 0;
169: mem68k_cont1output = 0;
170: mem68k_cont2output = 0;
171: mem68k_contEoutput = 0;
1.1.1.2 root 172: memset(&mem68k_cont, 0, sizeof(mem68k_cont));
1.1 root 173: return 0;
174: }
175:
176: /*** memptr routines - called for IPC generation so speed is not vital ***/
177:
178: uint8 *mem68k_memptr_bad(uint32 addr)
179: {
180: LOG_CRITICAL(("%08X [MEM] Invalid memory access 0x%X", regs.pc, addr));
181: return cpu68k_rom;
182: }
183:
184: uint8 *mem68k_memptr_rom(uint32 addr)
185: {
186: if (addr < cpu68k_romlen) {
1.1.1.2 root 187: return (cpu68k_rom + addr);
1.1 root 188: }
189: LOG_CRITICAL(("%08X [MEM] Invalid memory access to ROM 0x%X", regs.pc,
1.1.1.2 root 190: addr));
1.1 root 191: return cpu68k_rom;
192: }
193:
194: uint8 *mem68k_memptr_ram(uint32 addr)
195: {
196: /* LOG_USER(("%08X [MEM] Executing code from RAM 0x%X", regs.pc, addr)); */
1.1.1.2 root 197: addr &= 0xffff;
198: return (cpu68k_ram + addr);
1.1 root 199: }
200:
201:
202: /*** BAD fetch/store ***/
203:
204: uint8 mem68k_fetch_bad_byte(uint32 addr)
205: {
1.1.1.2 root 206: LOG_CRITICAL(("%08X [MEM] Invalid memory fetch (byte) 0x%X", regs.pc,
207: addr));
1.1 root 208: return 0;
209: }
210:
211: uint16 mem68k_fetch_bad_word(uint32 addr)
212: {
1.1.1.2 root 213: LOG_CRITICAL(("%08X [MEM] Invalid memory fetch (word) 0x%X", regs.pc,
214: addr));
1.1 root 215: return 0;
216: }
217:
218: uint32 mem68k_fetch_bad_long(uint32 addr)
219: {
1.1.1.2 root 220: LOG_CRITICAL(("%08X [MEM] Invalid memory fetch (long) 0x%X", regs.pc,
221: addr));
1.1 root 222: return 0;
223: }
224:
225: void mem68k_store_bad_byte(uint32 addr, uint8 data)
226: {
1.1.1.3 ! root 227: LOG_CRITICAL(("%08X [MEM] Invalid memory store (byte) 0x%X = %X", regs.pc,
! 228: addr, data));
1.1 root 229: }
230:
231: void mem68k_store_bad_word(uint32 addr, uint16 data)
232: {
1.1.1.3 ! root 233: LOG_CRITICAL(("%08X [MEM] Invalid memory store (word) 0x%X = %X", regs.pc,
! 234: addr, data));
1.1 root 235: }
236:
237: void mem68k_store_bad_long(uint32 addr, uint32 data)
238: {
1.1.1.3 ! root 239: LOG_CRITICAL(("%08X [MEM] Invalid memory store (long) 0x%X = %X", regs.pc,
! 240: addr, data));
1.1 root 241: }
242:
243:
244: /*** ROM fetch/store ***/
245:
246: uint8 mem68k_fetch_rom_byte(uint32 addr)
247: {
248: if (addr < cpu68k_romlen) {
1.1.1.2 root 249: return (*(uint8 *)(cpu68k_rom + addr));
1.1 root 250: }
1.1.1.2 root 251: LOG_CRITICAL(("%08X [ROM] Invalid memory fetch (byte) 0x%X", regs.pc,
252: addr));
1.1 root 253: return 0;
254: }
255:
256: uint16 mem68k_fetch_rom_word(uint32 addr)
257: {
258: #ifdef DEBUG_BUS
259: if (addr & 1) {
260: LOG_CRITICAL(("%08X [ROM] Bus error 0x%X", regs.pc, addr));
261: return 0;
262: }
263: #endif
264: if (addr < cpu68k_romlen) {
1.1.1.2 root 265: return LOCENDIAN16(*(uint16 *)(cpu68k_rom + addr));
1.1 root 266: }
1.1.1.2 root 267: LOG_CRITICAL(("%08X [ROM] Invalid memory fetch (word) 0x%X", regs.pc,
268: addr));
1.1 root 269: return 0;
270: }
271:
272: uint32 mem68k_fetch_rom_long(uint32 addr)
273: {
274: #ifdef DEBUG_BUS
275: if (addr & 1) {
276: LOG_CRITICAL(("%08X [ROM] Bus error 0x%X", regs.pc, addr));
277: return 0;
278: }
279: #endif
280: if (addr < cpu68k_romlen) {
281: #ifdef ALIGNLONGS
1.1.1.2 root 282: return (LOCENDIAN16(*(uint16 *)(cpu68k_rom + addr)) << 16) |
283: LOCENDIAN16(*(uint16 *)(cpu68k_rom + addr + 2));
1.1 root 284: #else
1.1.1.2 root 285: return LOCENDIAN32(*(uint32 *)(cpu68k_rom + addr));
1.1 root 286: #endif
287: }
1.1.1.2 root 288: LOG_CRITICAL(("%08X [ROM] Invalid memory fetch (long) 0x%X", regs.pc,
289: addr));
1.1 root 290: return 0;
291: }
292:
293: void mem68k_store_rom_byte(uint32 addr, uint8 data)
294: {
1.1.1.3 ! root 295: LOG_CRITICAL(("%08X [ROM] Invalid memory store (byte) 0x%X = %X", regs.pc,
! 296: addr, data));
1.1 root 297: }
298:
299: void mem68k_store_rom_word(uint32 addr, uint16 data)
300: {
1.1.1.3 ! root 301: LOG_CRITICAL(("%08X [ROM] Invalid memory store (word) 0x%X = %X", regs.pc,
! 302: addr, data));
1.1 root 303: }
304:
305: void mem68k_store_rom_long(uint32 addr, uint32 data)
306: {
1.1.1.3 ! root 307: LOG_CRITICAL(("%08X [ROM] Invalid memory store (long) 0x%X = %X", regs.pc,
! 308: addr, data));
1.1 root 309: }
310:
311:
312: /*** SRAM fetch/store ***/
313:
314: uint8 mem68k_fetch_sram_byte(uint32 addr)
315: {
316: #ifdef DEBUG_SRAM
317: LOG_VERBOSE(("%08X [SRAM] Fetch byte from %X", regs.pc, addr));
318: #endif
1.1.1.2 root 319: addr &= 0x1fff;
320: return (*(uint8 *)(cpuz80_ram + addr));
1.1 root 321: }
322:
323: uint16 mem68k_fetch_sram_word(uint32 addr)
324: {
325: uint8 data;
326: #ifdef DEBUG_BUS
327: if (addr & 1) {
328: LOG_CRITICAL(("%08X [SRAM] Bus error 0x%X", regs.pc, addr));
329: return 0;
330: }
331: #endif
332: #ifdef DEBUG_SRAM
333: LOG_VERBOSE(("%08X [SRAM] Fetch word from %X", regs.pc, addr));
334: #endif
1.1.1.2 root 335: addr &= 0x1fff;
1.1 root 336: /* sram word fetches are fetched with duplicated low byte data */
1.1.1.2 root 337: data = *(uint8 *)(cpuz80_ram + addr);
338: return data | (data << 8);
1.1 root 339: }
340:
341: uint32 mem68k_fetch_sram_long(uint32 addr)
342: {
343: #ifdef DEBUG_BUS
344: if (addr & 1) {
345: LOG_CRITICAL(("%08X [SRAM] Bus error 0x%X", regs.pc, addr));
346: return 0;
347: }
348: #endif
349: #ifdef DEBUG_SRAM
350: LOG_VERBOSE(("%08X [SRAM] Fetch long from %X", regs.pc, addr));
351: #endif
1.1.1.2 root 352: addr &= 0x1fff;
1.1 root 353: #ifdef ALIGNLONGS
1.1.1.2 root 354: return (LOCENDIAN16(*(uint16 *)(cpuz80_ram + addr)) << 16) |
355: LOCENDIAN16(*(uint16 *)(cpuz80_ram + addr + 2));
1.1 root 356: #else
1.1.1.2 root 357: return LOCENDIAN32(*(uint32 *)(cpuz80_ram + addr));
1.1 root 358: #endif
359: }
360:
361: void mem68k_store_sram_byte(uint32 addr, uint8 data)
362: {
363: #ifdef DEBUG_SRAM
364: LOG_VERBOSE(("%08X [SRAM] Store byte to %X", regs.pc, addr));
365: #endif
1.1.1.2 root 366: addr &= 0x1fff;
367: *(uint8 *)(cpuz80_ram + addr) = data;
1.1 root 368: return;
369: }
370:
371: void mem68k_store_sram_word(uint32 addr, uint16 data)
372: {
373: #ifdef DEBUG_BUS
374: if (addr & 1) {
375: LOG_CRITICAL(("%08X [SRAM] Bus error 0x%X", regs.pc, addr));
376: return;
377: }
378: #endif
379: #ifdef DEBUG_SRAM
380: LOG_VERBOSE(("%08X [SRAM] Store word to %X", regs.pc, addr));
381: #endif
1.1.1.2 root 382: addr &= 0x1fff;
1.1 root 383: /* word writes are stored with low byte cleared */
1.1.1.2 root 384: *(uint8 *)(cpuz80_ram + addr) = data >> 8;
1.1 root 385: return;
386: }
387:
388: void mem68k_store_sram_long(uint32 addr, uint32 data)
389: {
390: #ifdef DEBUG_BUS
391: if (addr & 1) {
392: LOG_CRITICAL(("%08X [SRAM] Bus error 0x%X", regs.pc, addr));
393: return;
394: }
395: #endif
396: #ifdef DEBUG_SRAM
397: LOG_VERBOSE(("%08X [SRAM] Store byte to %X", regs.pc, addr));
398: #endif
1.1.1.2 root 399: addr &= 0x1fff;
1.1 root 400: #ifdef ALIGNLONGS
1.1.1.2 root 401: *(uint16 *)(cpuz80_ram + addr) = LOCENDIAN16((uint16)(data >> 16));
402: *(uint16 *)(cpuz80_ram + addr + 2) = LOCENDIAN16((uint16)(data));
1.1 root 403: #else
1.1.1.2 root 404: *(uint32 *)(cpuz80_ram + addr) = LOCENDIAN32(data);
1.1 root 405: #endif
406: return;
407: }
408:
409:
410: /*** YAM fetch/store ***/
411:
412: uint8 mem68k_fetch_yam_byte(uint32 addr)
413: {
1.1.1.2 root 414: addr -= 0xA04000;
1.1 root 415: /* LOG_USER(("%08X [YAM] fetch (byte) 0x%X", regs.pc, addr)); */
416: if (addr < 4) {
1.1.1.2 root 417: return sound_ym2612fetch(addr);
1.1 root 418: } else {
419: LOG_CRITICAL(("%08X [YAM] Invalid YAM fetch (byte) 0x%X", regs.pc, addr));
420: return 0;
421: }
422: }
423:
424: uint16 mem68k_fetch_yam_word(uint32 addr)
425: {
426: #ifdef DEBUG_BUS
427: if (addr & 1) {
428: LOG_CRITICAL(("%08X [YAM] Bus error 0x%X", regs.pc, addr));
429: return 0;
430: }
431: #endif
1.1.1.2 root 432: addr -= 0xA04000;
433: LOG_CRITICAL(("%08X [YAM] Invalid memory fetch (word) 0x%X", regs.pc,
434: addr));
1.1 root 435: return 0;
436: }
437:
438: uint32 mem68k_fetch_yam_long(uint32 addr)
439: {
440: #ifdef DEBUG_BUS
441: if (addr & 1) {
442: LOG_CRITICAL(("%08X [YAM] Bus error 0x%X", regs.pc, addr));
443: return 0;
444: }
445: #endif
1.1.1.2 root 446: addr -= 0xA04000;
1.1 root 447: /* no longs please */
1.1.1.2 root 448: LOG_CRITICAL(("%08X [YAM] Invalid memory fetch (long) 0x%X", regs.pc,
449: addr));
1.1 root 450: return 0;
451: }
452:
453: void mem68k_store_yam_byte(uint32 addr, uint8 data)
454: {
1.1.1.2 root 455: addr -= 0xA04000;
1.1 root 456: /* LOG_USER(("%08X [YAM] (68k) store (byte) 0x%X (%d)", regs.pc, addr,
457: data)); */
458: if (addr < 4)
1.1.1.2 root 459: sound_ym2612store(addr, data);
1.1 root 460: else
461: LOG_CRITICAL(("%08X [YAM] Invalid YAM store (byte) 0x%X", regs.pc, addr));
462: }
463:
464: void mem68k_store_yam_word(uint32 addr, uint16 data)
465: {
466: #ifdef DEBUG_BUS
467: if (addr & 1) {
468: LOG_CRITICAL(("%08X [YAM] Bus error 0x%X", regs.pc, addr));
469: return;
470: }
471: #endif
1.1.1.2 root 472: addr -= 0xA04000;
1.1.1.3 ! root 473: LOG_CRITICAL(("%08X [YAM] Invalid memory store (word) 0x%X = %X", regs.pc,
! 474: addr, data));
1.1 root 475: }
476:
477: void mem68k_store_yam_long(uint32 addr, uint32 data)
478: {
479: #ifdef DEBUG_BUS
480: if (addr & 1) {
481: LOG_CRITICAL(("%08X [YAM] Bus error 0x%X", regs.pc, addr));
482: return;
483: }
484: #endif
1.1.1.2 root 485: addr -= 0xA04000;
1.1 root 486: /* no longs please */
1.1.1.3 ! root 487: LOG_CRITICAL(("%08X [YAM] Invalid memory store (long) 0x%X = %X", regs.pc,
! 488: addr, data));
1.1 root 489: }
490:
491:
492: /*** BANK fetch/store ***/
493:
494: uint8 mem68k_fetch_bank_byte(uint32 addr)
495: {
496: /* write only */
497: LOG_CRITICAL(("%08X [BANK] Invalid memory fetch (byte) 0x%X", regs.pc,
1.1.1.2 root 498: addr));
1.1 root 499: return 0;
500: }
501:
502: uint16 mem68k_fetch_bank_word(uint32 addr)
503: {
504: /* write only */
505: LOG_CRITICAL(("%08X [BANK] Invalid memory fetch (word) 0x%X", regs.pc,
1.1.1.2 root 506: addr));
1.1 root 507: return 0;
508: }
509:
510: uint32 mem68k_fetch_bank_long(uint32 addr)
511: {
512: /* write only */
513: LOG_CRITICAL(("%08X [BANK] Invalid memory fetch (long) 0x%X", regs.pc,
1.1.1.2 root 514: addr));
1.1 root 515: return 0;
516: }
517:
518: void mem68k_store_bank_byte(uint32 addr, uint8 data)
519: {
1.1.1.2 root 520: addr -= 0xA06000;
1.1 root 521: if (addr == 0x000) {
522: #ifdef DEBUG_SRAM
523: LOG_VERBOSE(("%08X [BANK] Store byte to %X", regs.pc, addr));
524: #endif
525: cpuz80_bankwrite(data);
526: } else {
527: LOG_CRITICAL(("%08X [BANK] Invalid memory store (byte) 0x%X", regs.pc,
1.1.1.2 root 528: addr));
1.1 root 529: }
530: }
531:
532: void mem68k_store_bank_word(uint32 addr, uint16 data)
533: {
1.1.1.2 root 534: addr -= 0xA06000;
1.1 root 535: if (addr == 0x000) {
536: #ifdef DEBUG_SRAM
537: LOG_VERBOSE(("%08X [BANK] Store word to %X", regs.pc, addr));
538: #endif
1.1.1.2 root 539: cpuz80_bankwrite(data >> 8);
1.1 root 540: } else {
541: LOG_CRITICAL(("%08X [BANK] Invalid memory store (word) 0x%X", regs.pc,
1.1.1.2 root 542: addr));
1.1 root 543: }
544: }
545:
546: void mem68k_store_bank_long(uint32 addr, uint32 data)
547: {
1.1.1.2 root 548: addr -= 0xA06000;
1.1 root 549: /* no longs please */
1.1.1.3 ! root 550: LOG_CRITICAL(("%08X [BANK] Invalid memory store (long) 0x%X = %X", regs.pc,
! 551: addr, data));
1.1 root 552: }
553:
554:
555: /*** I/O fetch/store ***/
556:
557: uint8 mem68k_fetch_io_byte(uint32 addr)
558: {
559: uint8 in;
560:
1.1.1.2 root 561: addr -= 0xA10000;
1.1 root 562: if ((addr & 1) == 0) {
563: LOG_CRITICAL(("%08X [IO] Invalid memory fetch (byte) 0x%X",
1.1.1.2 root 564: regs.pc, addr));
1.1 root 565: return 0;
566: }
1.1.1.2 root 567: switch (addr >> 1) {
568: case 0: /* 0x1 */
1.1 root 569: /* version */
1.1.1.2 root 570: return (1 << 5 | vdp_pal << 6 | vdp_overseas << 7);
571: case 1: /* 0x3 */
1.1 root 572: /* get input state */
1.1.1.2 root 573: in = ((mem68k_cont1output & 1 << 6)
574: ? ((1 - mem68k_cont[0].up) | (1 - mem68k_cont[0].down) << 1 |
575: (1 - mem68k_cont[0].left) << 2 | (1 - mem68k_cont[0].right) << 3 |
576: (1 - mem68k_cont[0].b) << 4 | (1 - mem68k_cont[0].c) << 5)
577: : ((1 - mem68k_cont[0].up) | (1 - mem68k_cont[0].down) << 1 |
578: (1 - mem68k_cont[0].a) << 4 | (1 - mem68k_cont[0].start) << 5));
1.1 root 579: return (in & ~mem68k_cont1ctrl) | (mem68k_cont1output & mem68k_cont1ctrl);
1.1.1.2 root 580: case 2: /* 0x5 */
1.1 root 581: /* get input state */
1.1.1.2 root 582: in = ((mem68k_cont2output & 1 << 6)
583: ? ((1 - mem68k_cont[1].up) | (1 - mem68k_cont[1].down) << 1 |
584: (1 - mem68k_cont[1].left) << 2 | (1 - mem68k_cont[1].right) << 3 |
585: (1 - mem68k_cont[1].b) << 4 | (1 - mem68k_cont[1].c) << 5)
586: : ((1 - mem68k_cont[1].up) | (1 - mem68k_cont[1].down) << 1 |
587: (1 - mem68k_cont[1].a) << 4 | (1 - mem68k_cont[1].start) << 5));
1.1 root 588: return (in & ~mem68k_cont2ctrl) | (mem68k_cont2output & mem68k_cont2ctrl);
1.1.1.2 root 589: case 3: /* 0x7 */
1.1 root 590: LOG_NORMAL(("%08X [IO] EXT port read", regs.pc));
591: /* get input state */
1.1.1.2 root 592: in = 0; /* BUG: unsupported */
1.1 root 593: return (in & ~mem68k_cont1ctrl) | (mem68k_cont1output & mem68k_cont1ctrl);
1.1.1.2 root 594: case 4: /* 0x9 */
1.1 root 595: return mem68k_cont1ctrl;
1.1.1.2 root 596: case 5: /* 0xB */
1.1 root 597: return mem68k_cont2ctrl;
1.1.1.2 root 598: case 6: /* 0xD */
1.1 root 599: return mem68k_contEctrl;
600: default:
601: LOG_CRITICAL(("%08X [IO] Invalid memory fetch (byte) 0x%X",
1.1.1.2 root 602: regs.pc, addr));
1.1 root 603: return 0;
604: }
605: }
606:
607: uint16 mem68k_fetch_io_word(uint32 addr)
608: {
1.1.1.2 root 609: return mem68k_fetch_io_byte(addr + 1);
1.1 root 610: }
611:
612: uint32 mem68k_fetch_io_long(uint32 addr)
613: {
1.1.1.2 root 614: return (mem68k_fetch_io_word(addr) << 16) | mem68k_fetch_io_word(addr + 2);
1.1 root 615: }
616:
617: void mem68k_store_io_byte(uint32 addr, uint8 data)
618: {
1.1.1.2 root 619: addr -= 0xA10000;
1.1 root 620: switch (addr) {
621: case 0x3:
622: mem68k_cont1output = data;
623: return;
624: case 0x5:
625: mem68k_cont2output = data;
626: return;
627: case 0x7:
628: mem68k_contEoutput = data;
629: LOG_NORMAL(("%08X [IO] EXT port output set to %X", regs.pc, data));
630: return;
631: case 0x9:
632: mem68k_cont1ctrl = data;
633: if (data != 0x40) {
1.1.1.2 root 634: LOG_CRITICAL(("%08X [IO] Unknown controller 1 setting (0x%X)",
635: regs.pc, data));
1.1 root 636: }
637: return;
638: case 0xB:
639: mem68k_cont2ctrl = data;
640: if (data != 0x40) {
641: LOG_CRITICAL(("%08X [IO] Unknown controller 2 setting (0x%X)",
1.1.1.2 root 642: regs.pc, data));
1.1 root 643: }
644: return;
645: case 0xD:
646: mem68k_contEctrl = data;
647: LOG_NORMAL(("%08X [IO] EXT port ctrl set to %X", regs.pc, data));
648: return;
649: case 0xF:
650: case 0x11:
651: case 0x13:
652: case 0x15:
653: case 0x17:
654: case 0x19:
655: case 0x1B:
656: case 0x1D:
657: case 0x1F:
658: /* return; */
659: default:
660: LOG_CRITICAL(("%08X [IO] Invalid memory store (byte) 0x%X",
1.1.1.2 root 661: regs.pc, addr));
1.1 root 662: return;
663: }
664: }
665:
666: void mem68k_store_io_word(uint32 addr, uint16 data)
667: {
668: if (data >> 8)
669: LOG_CRITICAL(("%08X [IO] Word store to %X of %X", addr, data));
1.1.1.2 root 670: mem68k_store_io_byte(addr + 1, data & 0xff);
1.1 root 671: }
672:
673: void mem68k_store_io_long(uint32 addr, uint32 data)
674: {
1.1.1.2 root 675: mem68k_store_io_word(addr, (uint16)(data >> 16));
676: mem68k_store_io_word(addr + 2, (uint16)data);
1.1 root 677: return;
678: }
679:
680:
681: /*** CTRL fetch/store ***/
682:
683: uint8 mem68k_fetch_ctrl_byte(uint32 addr)
684: {
1.1.1.2 root 685: addr -= 0xA11000;
1.1 root 686: /* 0x000 mode (write only), 0x100 z80 busreq, 0x200 z80 reset (write only) */
687: if (addr == 0x100) {
688: return cpuz80_active ? 1 : 0;
689: }
690: LOG_CRITICAL(("%08X [CTRL] Invalid memory fetch (byte) 0x%X",
1.1.1.2 root 691: regs.pc, addr));
1.1 root 692: return 0;
693: }
694:
695: uint16 mem68k_fetch_ctrl_word(uint32 addr)
696: {
1.1.1.2 root 697: addr -= 0xA11000;
1.1 root 698: /* 0x000 mode (write only), 0x100 z80 busreq, 0x200 z80 reset (write only) */
699: if (addr == 0x100) {
700: return cpuz80_active ? 0x100 : 0;
701: }
702: LOG_CRITICAL(("%08X [CTRL] Invalid memory fetch (word) 0x%X",
1.1.1.2 root 703: regs.pc, addr));
1.1 root 704: return 0;
705: }
706:
707: uint32 mem68k_fetch_ctrl_long(uint32 addr)
708: {
1.1.1.2 root 709: addr -= 0xA11000;
1.1 root 710: /* no long access allowed */
711: LOG_CRITICAL(("%08X [CTRL] Invalid memory fetch (long) 0x%X",
1.1.1.2 root 712: regs.pc, addr));
1.1 root 713: return 0;
714: }
715:
716: void mem68k_store_ctrl_byte(uint32 addr, uint8 data)
717: {
1.1.1.2 root 718: addr -= 0xA11000;
1.1 root 719: if (addr == 0x000 || addr == 0x001) {
720: /* z80 memory mode - not applicable for production carts */
721: return;
722: } else if (addr == 0x100) {
723: /* bus request */
724: if (data & 1) {
725: cpuz80_stop();
726: LOG_DEBUG1(("%08X Z80 stopped", regs.pc));
727: } else {
728: cpuz80_start();
729: LOG_DEBUG1(("%08X Z80 started", regs.pc));
730: }
731: } else if (addr == 0x101) {
1.1.1.2 root 732: return; /* ignore low byte */
1.1 root 733: } else if (addr == 0x200) {
734: /* z80 reset request */
735: if (!(data & 1)) {
736: /* cpuz80_stop(); */
737: cpuz80_resetcpu();
738: sound_genreset();
739: LOG_DEBUG1(("%08X Z80 reset", regs.pc));
740: } else {
741: cpuz80_unresetcpu();
742: LOG_DEBUG1(("%08X Z80 un-reset", regs.pc));
743: }
744: } else if (addr == 0x201) {
1.1.1.2 root 745: return; /* ignore low byte */
1.1 root 746: } else {
747: LOG_CRITICAL(("%08X [CTRL] Invalid memory store (byte) 0x%X",
1.1.1.2 root 748: regs.pc, addr));
1.1 root 749: }
750: }
751:
752: void mem68k_store_ctrl_word(uint32 addr, uint16 data)
753: {
1.1.1.2 root 754: addr -= 0xA11000;
1.1 root 755: if (addr == 0x000) {
756: /* z80 memory mode - not applicable for production carts */
757: return;
758: } else if (addr == 0x100) {
759: /* bus request */
760: if (data == 0x100) {
761: cpuz80_stop();
762: LOG_DEBUG1(("%08X Z80 stopped", regs.pc));
763: } else {
764: cpuz80_start();
765: LOG_DEBUG1(("%08X Z80 started", regs.pc));
766: }
767: } else if (addr == 0x200) {
768: /* z80 reset request */
769: if (!(data & 0x100)) {
770: /* cpuz80_stop(); */
771: cpuz80_resetcpu();
772: sound_genreset();
773: LOG_DEBUG1(("%08X Z80 reset", regs.pc));
774: } else {
775: cpuz80_unresetcpu();
776: LOG_DEBUG1(("%08X Z80 un-reset", regs.pc));
777: }
778: } else {
779: LOG_CRITICAL(("%08X [CTRL] Invalid memory store (word) 0x%X",
1.1.1.2 root 780: regs.pc, addr));
1.1 root 781: }
782: }
783:
784: void mem68k_store_ctrl_long(uint32 addr, uint32 data)
785: {
1.1.1.2 root 786: addr -= 0xA11000;
1.1 root 787: /* no long access allowed */
1.1.1.3 ! root 788: LOG_CRITICAL(("%08X [CTRL] Invalid memory store (long) 0x%X = %X",
! 789: regs.pc, addr, data));
1.1 root 790: }
791:
792:
793: /*** VDP fetch/store ***/
794:
795: uint8 mem68k_fetch_vdp_byte(uint32 addr)
796: {
1.1.1.2 root 797: uint16 data = mem68k_fetch_vdp_word(addr & ~1);
798: return ((addr & 1) ? (data & 0xff) : ((data >> 8) & 0xff));
1.1 root 799: }
800:
801: uint16 mem68k_fetch_vdp_word(uint32 addr)
802: {
803: #ifdef DEBUG_BUS
804: if (addr & 1) {
805: LOG_CRITICAL(("%08X [VDP] Bus error 0x%X", regs.pc, addr));
806: return 0;
807: }
808: #endif
1.1.1.2 root 809: addr -= 0xC00000;
810: switch (addr >> 1) {
1.1 root 811: case 0:
812: case 1:
813: /* data port */
814: #ifdef DEBUG_VDP
1.1.1.2 root 815: LOG_VERBOSE(("%08X [VDP] Word fetch from data port 0x%X", regs.pc, addr));
1.1 root 816: #endif
817: return vdp_fetchdata();
818: case 2:
819: case 3:
820: /* control port */
821: #ifdef DEBUG_VDP
822: LOG_VERBOSE(("%08X [VDP] Word fetch from control port "
1.1.1.2 root 823: "(status) 0x%X", regs.pc, addr));
1.1 root 824: #endif
825: return vdp_status();
826: case 4:
827: /* hv counter */
828: {
829: uint8 line8;
830: uint16 hvcount;
831:
832: /* line counter advances at H-int */
833: line8 = (vdp_line - vdp_visstartline + (vdp_event > 2 ? 1 : 0)) & 0xff;
834:
835: #ifdef DEBUG_VDP
836: LOG_VERBOSE(("%08X [VDP] Word fetch from hv counter 0x%X",
1.1.1.2 root 837: regs.pc, addr));
1.1 root 838: #endif
839: if ((vdp_reg[12] >> 1) & 3) {
840: /* interlace mode - replace lowest bit with highest bit */
1.1.1.2 root 841: hvcount = ((line8 & ~1) << 8) | (line8 & 0x100) | vdp_gethpos();
1.1 root 842: LOG_DEBUG1(("Interlace mode HV read - check this: %04X", hvcount));
843: return hvcount;
844: } else {
845: /* non-interlace mode */
846: hvcount = (line8 << 8) | vdp_gethpos();
847: LOG_DEBUG1(("%08X H/V counter read = %04X", regs.pc, hvcount));
848: return hvcount;
849: }
850: }
851: case 8:
852: LOG_CRITICAL(("%08X [VDP] PSG/prohibited word fetch.", regs.pc));
853: return 0;
854: default:
855: LOG_CRITICAL(("%08X [VDP] Invalid memory fetch (word) 0x%X",
1.1.1.2 root 856: regs.pc, addr));
1.1 root 857: return 0;
858: }
859: }
860:
861: uint32 mem68k_fetch_vdp_long(uint32 addr)
862: {
863: #ifdef DEBUG_BUS
864: if (addr & 1) {
865: LOG_CRITICAL(("%08X [VDP] Bus error 0x%X", regs.pc, addr));
866: return 0;
867: }
868: #endif
1.1.1.2 root 869: addr -= 0xC00000;
870: switch (addr >> 1) {
1.1 root 871: case 0:
872: /* data port */
873: #ifdef DEBUG_VDP
1.1.1.2 root 874: LOG_VERBOSE(("%08X [VDP] Long fetch from data port 0x%X", regs.pc, addr));
1.1 root 875: #endif
1.1.1.2 root 876: return (vdp_fetchdata() << 16) | vdp_fetchdata();
1.1 root 877: case 2:
878: /* control port */
879: #ifdef DEBUG_VDP
880: LOG_VERBOSE(("%08X [VDP] Long fetch from control port 0x%X",
1.1.1.2 root 881: regs.pc, addr));
1.1 root 882: LOG_CRITICAL(("%08X [VDP] Long fetch from control port 0x%X",
1.1.1.2 root 883: regs.pc, addr));
1.1 root 884: #endif
885: return 0;
886: case 4:
887: /* hv counter ish */
888: LOG_CRITICAL(("%08X [VDP] Long fetch from hv/prohibited 0x%X",
1.1.1.2 root 889: regs.pc, addr));
1.1 root 890: return 0;
891: default:
892: LOG_CRITICAL(("%08X [VDP] Invalid memory fetch (word) 0x%X",
1.1.1.2 root 893: regs.pc, addr));
1.1 root 894: return 0;
895: }
896: }
897:
898: void mem68k_store_vdp_byte(uint32 addr, uint8 data)
899: {
1.1.1.2 root 900: addr -= 0xC00000;
901: switch (addr) {
1.1 root 902: case 0:
903: case 1:
904: case 2:
905: case 3:
906: /* data port */
907: #ifdef DEBUG_VDP
908: LOG_VERBOSE(("%08X [VDP] Byte store to DATA of %X [%d][%X]", regs.pc,
1.1.1.2 root 909: data, vdp_reg[23] >> 6, vdp_reg[1]));
1.1 root 910: #endif
911: vdp_storedata(data | (data << 8));
912: return;
913: case 4:
914: case 5:
915: case 6:
916: case 7:
917:
918: #ifdef DEBUG_VDP
1.1.1.2 root 919: LOG_VERBOSE(("%08X [VDP] Byte store to CONTROL of %X [%d][%X]",
920: regs.pc, data, vdp_reg[23] >> 6, vdp_reg[1]));
1.1 root 921: #endif
922: /* control port */
923: vdp_storectrl(data | (data << 8));
924: return;
925: case 8:
926: case 9:
927: /* hv counter */
928: LOG_CRITICAL(("%08X [VDP] Byte store to hv counter 0x%X", regs.pc, addr));
929: return;
930: case 17:
1.1.1.2 root 931: sound_sn76496store(data);
1.1 root 932: return;
933: default:
934: LOG_CRITICAL(("%08X [VDP] Invalid memory store (byte) 0x%X",
1.1.1.2 root 935: regs.pc, addr));
1.1 root 936: return;
937: }
938: }
939:
940: void mem68k_store_vdp_word(uint32 addr, uint16 data)
941: {
942: #ifdef DEBUG_BUS
943: if (addr & 1) {
944: LOG_CRITICAL(("%08X [VDP] Bus error 0x%X", regs.pc, addr));
945: return;
946: }
947: #endif
1.1.1.2 root 948: addr -= 0xC00000;
949: switch (addr >> 1) {
1.1 root 950: case 0:
951: case 1:
952: /* data port */
953: #ifdef DEBUG_VDP
954: LOG_CRITICAL(("%08X [VDP] Word store to DATA of %X [%d][%X]", regs.pc,
1.1.1.2 root 955: data, vdp_reg[23] >> 6, vdp_reg[1]));
1.1 root 956: #endif
957: vdp_storedata(data);
958: return;
959: case 2:
960: case 3:
961: #ifdef DEBUG_VDP
1.1.1.2 root 962: LOG_VERBOSE(("%08X [VDP] Word store to CONTROL of %X [%d][%X]",
963: regs.pc, data, vdp_reg[23] >> 6, vdp_reg[1]));
1.1 root 964: #endif
965: /* control port */
966: vdp_storectrl(data);
967: return;
968: case 4:
969: /* hv counter */
970: LOG_CRITICAL(("%08X [VDP] Word store to hv counter 0x%X", regs.pc, addr));
971: return;
972: case 8:
973: LOG_CRITICAL(("%08X [VDP] PSG/prohibited word store.", regs.pc));
974: return;
975: default:
976: LOG_CRITICAL(("%08X [VDP] Invalid memory store (word) 0x%X", regs.pc,
1.1.1.2 root 977: addr));
1.1 root 978: return;
979: }
980: }
981:
982: void mem68k_store_vdp_long(uint32 addr, uint32 data)
983: {
984: #ifdef DEBUG_BUS
985: if (addr & 1) {
986: LOG_CRITICAL(("%08X [VDP] Bus error 0x%X", regs.pc, addr));
987: return;
988: }
989: #endif
1.1.1.2 root 990: addr -= 0xC00000;
991: switch (addr >> 1) {
1.1 root 992: case 0:
993: /* data port */
994: #ifdef DEBUG_VDP
995: LOG_VERBOSE(("%08X [VDP] Long store to DATA of %X [%d][%X]", regs.pc,
1.1.1.2 root 996: data, vdp_reg[23] >> 6, vdp_reg[1]));
1.1 root 997: #endif
1.1.1.2 root 998: vdp_storedata((uint16)(data >> 16));
1.1 root 999: vdp_storedata((uint16)(data));
1000: return;
1001: case 2:
1002: /* control port */
1003: #ifdef DEBUG_VDP
1.1.1.2 root 1004: LOG_VERBOSE(("%08X [VDP] Long store to CONTROL of %X [%d][%X]",
1005: regs.pc, data, vdp_reg[23] >> 6, vdp_reg[1]));
1.1 root 1006: #endif
1.1.1.2 root 1007: vdp_storectrl((uint16)(data >> 16));
1.1 root 1008: vdp_storectrl((uint16)(data));
1009: return;
1010: case 4:
1011: /* hv counter */
1012: LOG_CRITICAL(("%08X [VDP] Long store to hv/prohibited 0x%X", regs.pc,
1.1.1.2 root 1013: addr));
1.1 root 1014: return;
1015: default:
1016: LOG_CRITICAL(("%08X [VDP] Invalid memory store (long) 0x%X", regs.pc,
1.1.1.2 root 1017: addr));
1.1 root 1018: return;
1019: }
1020: }
1021:
1022: /*** RAM fetch/store ***/
1023:
1024: uint8 mem68k_fetch_ram_byte(uint32 addr)
1025: {
1.1.1.2 root 1026: addr &= 0xffff;
1027: return (*(uint8 *)(cpu68k_ram + addr));
1.1 root 1028: }
1029:
1030: uint16 mem68k_fetch_ram_word(uint32 addr)
1031: {
1.1.1.2 root 1032: addr &= 0xffff;
1033: return LOCENDIAN16(*(uint16 *)(cpu68k_ram + addr));
1.1 root 1034: }
1035:
1036: uint32 mem68k_fetch_ram_long(uint32 addr)
1037: {
1.1.1.2 root 1038: addr &= 0xffff;
1.1 root 1039: #ifdef ALIGNLONGS
1.1.1.2 root 1040: return (LOCENDIAN16(*(uint16 *)(cpu68k_ram + addr)) << 16) |
1041: LOCENDIAN16(*(uint16 *)(cpu68k_ram + addr + 2));
1.1 root 1042: #else
1.1.1.2 root 1043: return LOCENDIAN32(*(uint32 *)(cpu68k_ram + addr));
1.1 root 1044: #endif
1045: }
1046:
1047: void mem68k_store_ram_byte(uint32 addr, uint8 data)
1048: {
1.1.1.2 root 1049: addr &= 0xffff;
1050: *(uint8 *)(cpu68k_ram + addr) = data;
1.1 root 1051: return;
1052: }
1053:
1054: void mem68k_store_ram_word(uint32 addr, uint16 data)
1055: {
1.1.1.2 root 1056: addr &= 0xffff;
1057: *(uint16 *)(cpu68k_ram + addr) = LOCENDIAN16(data);
1.1 root 1058: return;
1059: }
1060:
1061: void mem68k_store_ram_long(uint32 addr, uint32 data)
1062: {
1.1.1.2 root 1063: addr &= 0xffff;
1.1 root 1064: #ifdef ALIGNLONGS
1.1.1.2 root 1065: *(uint16 *)(cpu68k_ram + addr) = LOCENDIAN16((uint16)(data >> 16));
1066: *(uint16 *)(cpu68k_ram + addr + 2) = LOCENDIAN16((uint16)(data));
1.1 root 1067: #else
1.1.1.2 root 1068: *(uint32 *)(cpu68k_ram + addr) = LOCENDIAN32(data);
1.1 root 1069: #endif
1070: return;
1071: }
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