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1.1 root 1: ;----------------------------------------------------------------------------;
2: ; RAZE-x86 Z80 emulator.
3: ; version 1.06
4: ;
5: ; Copyright (c) 1999 Richard Mitton
6: ;
7: ; This may only be distributed as part of the complete RAZE package.
8: ; See RAZE.TXT for license information.
9: ;----------------------------------------------------------------------------;
10:
11: %macro cglobal 1
12: global @UNDERSCORE@%1
13: %define %1 @UNDERSCORE@%1
14: %endmacro
15:
16: ; You are not expected to understand this.
17:
18:
19: ;----------------------------------------------------------------------------;
20: ; Comment these in/out for faster speed (less accurate):
21: %define EMULATE_UNDOC_FLAGS ; a couple of undocumented flags
22: %define EMULATE_BITS_3_5 ; bits 3/5 of the flags (undocumented)
23: %define EMULATE_WEIRD_STUFF ; misc *very obscure* undocumented behaviour
24: %define EMULATE_R_REGISTER ; precise R register (not usually needed)
25: ;;;;%define USE_FETCH_CALLBACK ; call a callback for every fetch (slow!)
26: ;----------------------------------------------------------------------------;
27:
28: ; Registers:
29: ; AF = ax (flags in AH)
30: ; HL = bx
31: ; BC = cx
32: ; PC = si
33: ; R = ebp
34: ;
35: ; GCC wants EBX, ESI, EDI, ESP, and EBP to be preserved at all times
36: ; DH should always be clear between macros
37: ; The high 16-bits of all registers should be clear at all times (except EBP)
38: ; This assumes LAHF will set bit 1 of AH. (supposed to be undefined...)
39:
40: BITS 32
41: SECTION .bss USE32
42:
43: ; Maximum number of memory handlers
44: %define MAX_MEM_HANDLERS 64
45:
46: ; The current context
47: align 16
48: context_start:
49: z80_AF resd 1
50: z80_BC resd 1
51: z80_DE resd 1
52: z80_HL resd 1
53: z80_IX resd 1
54: z80_IY resd 1
55: z80_PC resd 1
56: z80_SP resd 1
57: z80_AF2 resd 1
58: z80_BC2 resd 1
59: z80_DE2 resd 1
60: z80_HL2 resd 1
61: z80_IFF1 resb 1
62: z80_IFF2 resb 1
63: z80_R resd 1
64: z80_R2 resd 1
65: z80_I resb 1
66: z80_flag35 resb 1
67: z80_IM resb 1
68: z80_IRQVector resb 1
69: z80_IRQLine resb 1
70: z80_halted resb 1
71: z80_Extra_Cycles resd 1
72: registers_end:
73:
74: z80_Fetch resd 256
75: z80_Read resd (256*2)
76: z80_Write resd (256*2)
77: z80_In resd 1
78: z80_Out resd 1
79: z80_RetI resd 1
80: z80_Fetch_Callback resd 1
81: _read_handlers resd 4*MAX_MEM_HANDLERS
82: _write_handlers resd 4*MAX_MEM_HANDLERS
83: context_end:
84: resd 1 ; safety gap, so z80_reset can use 32-bit transfers
85:
86: ; Variables
87: z80_ICount resd 1
88: z80_Initial_ICount resd 1
89: z80_TempICount resd 1
90: z80_afterEI resb 1
91:
92: SECTION .text USE32
93: ;----------------------------------------------------------------------------;
94: ; Prepare to call a GCC function
95: %macro CALLGCC_START 0
96: mov [z80_AF], ezAF ; eax
97: mov [z80_BC], ezBC ; ecx
98: mov [z80_PC], ezPC ; esi
99: mov [z80_R], zR ; ebp
100: %endmacro
101:
102: ; Return from a GCC function
103: %macro CALLGCC_END 0
104: mov ezAF, [z80_AF] ; eax
105: mov ezBC, [z80_BC] ; ecx
106: mov ezPC, [z80_PC] ; esi
107: mov zR, [z80_R] ; ebp
108: %endmacro
109:
110: ; Read a byte from the PC, into DL
111: ; GETBYTE
112: %macro GETBYTE 0
113: %ifdef USE_FETCH_CALLBACK
114: CALLGCC_START
115: push ezPC
116: call [z80_Fetch_Callback]
117: add esp, 4
118: CALLGCC_END
119: %endif
120: mov edx, ezPC
121: shr edx, 8
122: mov edi, [z80_Fetch+edx*4]
123:
124: mov dl, [edi+ezPC]
125: inc zPC
126: xor edi, edi
127: %endmacro
128:
129: ; Read a byte from the PC, sign-extended into DI
130: ; GETDISP
131: %macro GETDISP 0
132: %ifdef USE_FETCH_CALLBACK
133: CALLGCC_START
134: push ezPC
135: call [z80_Fetch_Callback]
136: add esp, 4
137: CALLGCC_END
138: %endif
139: mov edx, ezPC
140: shr edx, 8
141: mov edx, [z80_Fetch+edx*4]
142:
143: movsx di, [edx+ezPC]
144: inc zPC
145: xor edx, edx
146: %endmacro
147:
148: ; Read a word from the PC, into DI
149: ; GETWORD
150: %macro GETWORD 0
151: %ifdef USE_FETCH_CALLBACK
152: CALLGCC_START
153: push ezPC
154: call [z80_Fetch_Callback]
155: add esp, 4
156: CALLGCC_END
157: %endif
158: mov [z80_BC], ezBC
159: mov edx, ezPC ; low byte
160: shr edx, 8
161: mov edi, [z80_Fetch+edx*4]
162:
163: mov dl, [edi+ezPC]
164: inc zPC
165:
166: %ifdef USE_FETCH_CALLBACK
167: push edx
168: CALLGCC_START
169: push ezPC
170: call [z80_Fetch_Callback]
171: add esp, 4
172: CALLGCC_END
173: pop edx
174: %endif
175: mov ecx, ezPC ; high byte
176: shr ecx, 8
177: mov edi, [z80_Fetch+ecx*4]
178:
179: mov dh, [edi+ezPC]
180: inc zPC
181: mov edi, edx
182: mov ezBC, [z80_BC]
183: xor edx, edx
184: %endmacro
185:
186: ; Read a byte from memory (DI) into DL
187: ; MEMREAD
188: %macro MEMREAD 0
189: CALLGCC_START
190: mov edx, edi
191: shr edx, 8
192: mov ecx, [z80_Read+edx*8]
193:
194: test ecx, ecx ; if handler exists, call it
195: jnz %%handler
196: ; no handler, so go direct
197: mov ecx, [z80_Read+edx*8+4]
198: mov dl, [ecx+edi]
199: jmp %%finish
200:
201: %%handler:
202: push edi
203: call ecx
204: xor edx, edx
205: add esp, 4
206: mov dl, al
207: %%finish:
208: CALLGCC_END
209: %endmacro
210:
211: ; Write a byte in DL to memory (DI)
212: %macro MEMWRITE 0
213: CALLGCC_START
214: xor eax, eax
215: mov al, dl
216:
217: mov edx, edi
218: shr edx, 8
219: mov ecx, [z80_Write+edx*8]
220:
221: test ecx, ecx ; if handler exists, call it
222: jnz %%handler
223: ; no handler, so go direct
224: mov ecx, [z80_Write+edx*8+4]
225: mov [ecx+edi], al
226: jmp %%finish
227:
228: %%handler:
229: push eax
230: push edi
231: call ecx
232: add esp, 8
233: %%finish:
234: CALLGCC_END
235: xor edx, edx
236: %endmacro
237:
238: ; Read a byte from port (DI) into DL
239: ; IOREAD
240: %macro IOREAD 0
241: push edi
242: CALLGCC_START
243: call [z80_In]
244: xor edx, edx
245: add esp, 4
246: mov dl, al
247: CALLGCC_END
248: %endmacro
249:
250: ; Write a byte in DL to port (DI)
251: %macro IOWRITE 0
252: CALLGCC_START
253: xor dh, dh
254: push edx
255: push edi
256: call [z80_Out]
257: add esp, 8
258: CALLGCC_END
259: xor edx, edx
260: %endmacro
261:
262: ; Align code to the default boundary
263: %macro ALIGN 0
264: align 4
265: %endmacro
266:
267: ; Define an instruction
268: ; DEF prefix, opcode, std_cycles, extra_cycles
269: %macro DEF 4
270: ALIGN
271: %define std_cycles %3
272: %define extra_cycles %4
273: %{1}_%2:
274: %endmacro
275:
276: ; Subtract the clock cycles for this instruction from the ICount
277: %macro DO_CYCLES 0
278: sub dword [z80_ICount], std_cycles
279: jbe near z80_finish
280: %endmacro
281:
282: ; Subtract the extra clock cycles for this instruction from the ICount
283: %macro DO_EXTRA_CYCLES 0
284: sub dword [z80_ICount], extra_cycles
285: jbe near z80_finish
286: %endmacro
287:
288: ; Finish straight away
289: %macro EXIT 0
290: jmp z80_finish
291: %endmacro
292:
293: ; Jump to the next instruction
294: %macro NEXT 0
295: %ifdef EMULATE_R_REGISTER
296: inc zR
297: %endif
298: GETBYTE
299: jmp [OpTable+edx*4]
300: %endmacro
301:
302: ; Check the IRQ line, cause an interrupt if needed
303: %macro CHECK_IRQ 0
304: cmp [z80_IRQLine], byte 0 ; check the IRQ line
305: je near %%finish
306: cmp [z80_IFF1], byte 0 ; check ints are enabled
307: je near %%finish
308:
309: ; disable interrupts
310: mov [z80_IFF1], byte 0
311: mov [z80_IFF2], byte 0
312: %ifdef EMULATE_R_REGISTER
313: inc zR
314: %endif
315:
316: mov [z80_halted], byte 0 ; Un-HALT the Z80
317:
318: mov edx, ezPC ; write the PC
319: dec zSP
320:
321: xchg dl, dh
322: mov edi, ezSP
323: MEMWRITE
324: dec zSP
325: mov edx, ezPC
326: mov edi, ezSP
327: MEMWRITE
328:
329: cmp [z80_IM], byte 0
330: jne %%not_im0
331: ; IM 0, 13 T-states
332: add [z80_Extra_Cycles], dword 13
333: mov dl, [z80_IRQVector]
334: sub dl, 0c7h
335: movzx ezPC, dl
336: jmp %%finish
337:
338: %%not_im0:
339: cmp [z80_IM], byte 1
340: jne %%not_im1
341: ; IM 1, 13 T-states
342: add [z80_Extra_Cycles], dword 13
343: mov ezPC, 38h
344: jmp %%finish
345:
346: %%not_im1:
347: ; IM 2, 19 T-states
348: add [z80_Extra_Cycles], dword 19
349: mov dl, [z80_IRQVector]
350: mov dh, zI
351: mov edi, edx
352: MEMREAD
353: inc di
354: mov ezPC, edx
355: MEMREAD
356: xchg dl, dh
357: or ezPC, edx
358: xor dh, dh
359: %%finish:
360: %endmacro
361:
362: ;----------------------------------------------------------------------------;
363: ; Helper functions
364:
365: ; Add A, %1
366: %macro DO_ADD 1
367: add zA, %1
368: %ifdef EMULATE_BITS_3_5
369: mov [z80_flag35], zA
370: %endif
371: lahf
372: jo %%set_overflow
373:
374: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C
375: jmp %%finish
376:
377: %%set_overflow:
378: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C
379: or zF, FLAG_P
380: %%finish:
381: %endmacro
382:
383: ; Sub A, %1
384: %macro DO_SUB 1
385: sub zA, %1
386: %ifdef EMULATE_BITS_3_5
387: mov [z80_flag35], zA
388: %endif
389: lahf
390: jo %%set_overflow
391:
392: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C|FLAG_N
393: jmp %%finish
394:
395: %%set_overflow:
396: or zF, FLAG_P
397: %%finish:
398: %endmacro
399:
400: ; Adc A, %1
401: %macro DO_ADC 1
402: ror zF, 1
403: adc zA, %1
404: %ifdef EMULATE_BITS_3_5
405: mov [z80_flag35], zA
406: %endif
407: lahf
408: jo %%set_overflow
409:
410: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C
411: jmp %%finish
412:
413: %%set_overflow:
414: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C
415: or zF, FLAG_P
416: %%finish:
417: %endmacro
418:
419: ; Sbc A, %1
420: %macro DO_SBC 1
421: ror zF, 1
422: sbb zA, %1
423: %ifdef EMULATE_BITS_3_5
424: mov [z80_flag35], zA
425: %endif
426: lahf
427: jo %%set_overflow
428:
429: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C|FLAG_N
430: jmp %%finish
431:
432: %%set_overflow:
433: or zF, FLAG_P
434: %%finish:
435: %endmacro
436:
437: ; And A, %1
438: %macro DO_AND 1
439: and zA, %1
440: %ifdef EMULATE_BITS_3_5
441: mov [z80_flag35], zA
442: %endif
443: lahf
444: and zF, ~(FLAG_N|FLAG_C) ; clear N and carry
445: or zF, FLAG_H ; set half-carry
446: %endmacro
447:
448: ; Or A, %1
449: %macro DO_OR 1
450: or zA, %1
451: %ifdef EMULATE_BITS_3_5
452: mov [z80_flag35], zA
453: %endif
454: lahf
455: and zF, ~(FLAG_N|FLAG_C|FLAG_H) ; clear N, carry and half-carry
456: %endmacro
457:
458: ; Xor A, %1
459: %macro DO_XOR 1
460: xor zA, %1
461: %ifdef EMULATE_BITS_3_5
462: mov [z80_flag35], zA
463: %endif
464: lahf
465: and zF, ~(FLAG_N|FLAG_C|FLAG_H) ; clear N, carry and half-carry
466: %endmacro
467:
468: ; Cp A, %1
469: %macro DO_CP 1
470: %ifdef EMULATE_BITS_3_5
471: mov ah, %1
472: mov [z80_flag35], ah
473: %endif
474: cmp zA, %1
475: lahf
476: jo %%overflow
477:
478: and zF, ~FLAG_P ; clear the overflow
479: or zF, FLAG_N ; set the N flag
480: jmp %%finish
481:
482: %%overflow:
483: or zF, FLAG_P|FLAG_N ; set the overflow and N flag
484: %%finish:
485: %endmacro
486:
487: ; Inc %1
488: %macro DO_INC 1
489: and zF, FLAG_C ; leave carry alone
490: %ifnidn %1, dl
491: mov dl, %1
492: %endif
493: or zF, [INC_Table+edx]
494: inc %1
495: %ifdef EMULATE_BITS_3_5
496: %ifnidn %1, dl
497: inc dl
498: %endif
499: mov [z80_flag35], dl
500: %endif
501: %endmacro
502:
503: ; Dec %1
504: %macro DO_DEC 1
505: and zF, FLAG_C ; leave carry alone
506: %ifnidn %1, dl
507: mov dl, %1
508: %endif
509: or zF, [DEC_Table+edx]
510: dec %1
511: %ifdef EMULATE_BITS_3_5
512: %ifnidn %1, dl
513: dec dl
514: %endif
515: mov [z80_flag35], dl
516: %endif
517: %endmacro
518:
519: ; Add16 %1, %2
520: %macro DO_ADD16 2
521: %ifidn %2, dx
522: %error "DX used as parameter for DO_ADD16!"
523: %endif
524: mov edi, e%2
525: %ifdef EMULATE_UNDOC_FLAGS
526: mov edx, e%1
527: %endif
528: and zF, FLAG_S|FLAG_Z|FLAG_P
529:
530: add %1, di ; do it
531: adc zF, 0 ; merge the new carry in
532:
533: %ifdef EMULATE_UNDOC_FLAGS
534: xor edx, e%1 ; work out our new half-carry
535: xor edx, edi
536: and dh, FLAG_H
537: or zF, dh
538: %endif
539:
540: %ifdef EMULATE_BITS_3_5
541: mov dl, h%1
542: mov [z80_flag35], dl
543: %endif
544: %ifdef EMULATE_UNDOC_FLAGS
545: xor dh, dh
546: %endif
547: %endmacro
548:
549: ; Adc16 %1, %2
550: %macro DO_ADC16 2
551: %ifidn %2, dx
552: %error "DX used as parameter for DO_ADC16!"
553: %endif
554: mov edi, e%2
555: %ifdef EMULATE_UNDOC_FLAGS
556: mov edx, e%1
557: %endif
558: ror zF, 1 ; load the carry
559: adc %1, %2
560: lahf
561: jo %%overflow
562:
563: and zF, ~(FLAG_N|FLAG_H|FLAG_P) ; clear N,H and overflow
564: jmp %%finish
565:
566: %%overflow:
567: and zF, ~(FLAG_N|FLAG_H) ; clear N and H
568: or zF, FLAG_P ; set overflow
569: %%finish:
570:
571: %ifdef EMULATE_UNDOC_FLAGS
572: xor edx, e%1 ; work out our new half-carry
573: xor edx, edi
574: and dh, FLAG_H
575: or zF, dh
576: %endif
577:
578: %ifdef EMULATE_BITS_3_5
579: mov dl, h%1
580: mov [z80_flag35], dl
581: %endif
582: %ifdef EMULATE_UNDOC_FLAGS
583: xor dh, dh
584: %endif
585: %endmacro
586:
587: ; Sbc16 %1, %2
588: %macro DO_SBC16 2
589: %ifidn %2, dx
590: %error "DX used as parameter for DO_SBC16!"
591: %endif
592: %ifdef EMULATE_UNDOC_FLAGS
593: mov edi, e%2
594: %endif
595: mov edx, e%1
596: ror zF, 1 ; load the carry
597: sbb %1, %2
598: lahf
599: jo %%overflow
600:
601: and zF, ~(FLAG_P|FLAG_H) ; clear H and overflow
602: or zF, FLAG_N ; set N
603: jmp %%finish
604:
605: %%overflow:
606: or zF, FLAG_N|FLAG_P ; set overflow and N
607: and zF, ~FLAG_H ; clear H
608: %%finish:
609:
610: %ifdef EMULATE_UNDOC_FLAGS
611: xor edx, e%1 ; work out our new half-carry
612: xor edx, edi
613: and dh, FLAG_H
614: or zF, dh
615: %endif
616:
617: %ifdef EMULATE_BITS_3_5
618: mov dl, h%1
619: mov [z80_flag35], dl
620: %endif
621: %ifdef EMULATE_UNDOC_FLAGS
622: xor dh, dh
623: %endif
624: %endmacro
625:
626: ; Rotate method, reg8
627: %macro DO_ROT 2
628: %ifidn %1, RLA
629: mov dl, zF
630: and dl, FLAG_S|FLAG_Z|FLAG_P
631: sahf
632: rcl zA, 1
633: adc dl, 0
634: %ifdef EMULATE_BITS_3_5
635: mov [z80_flag35], zA
636: %endif
637: mov zF, dl
638: %elifidn %1, RRA
639: mov dl, zF
640: and dl, FLAG_S|FLAG_Z|FLAG_P
641: sahf
642: rcr zA, 1
643: adc dl, 0
644: %ifdef EMULATE_BITS_3_5
645: mov [z80_flag35], zA
646: %endif
647: mov zF, dl
648: %elifidn %1, RLCA
649: and zF, FLAG_S|FLAG_Z|FLAG_P
650: rol zA, 1
651: adc zF, 0
652: %ifdef EMULATE_BITS_3_5
653: mov [z80_flag35], zA
654: %endif
655: %elifidn %1, RRCA
656: and zF, FLAG_S|FLAG_Z|FLAG_P
657: ror zA, 1
658: adc zF, 0
659: %ifdef EMULATE_BITS_3_5
660: mov [z80_flag35], zA
661: %endif
662: %else
663: %ifnidn %2, dl
664: mov dl, %2
665: %endif
666:
667: %ifidn %1, RLC
668: rol dl, 1
669: %elifidn %1, RRC
670: ror dl, 1
671: %elifidn %1, RL
672: sahf
673: rcl dl, 1
674: %elifidn %1, RR
675: sahf
676: rcr dl, 1
677: %endif
678:
679: adc dh, dh
680: test dl, dl
681: lahf
682: and zF, FLAG_S|FLAG_Z|FLAG_P
683: or zF, dh
684: %ifdef EMULATE_BITS_3_5
685: mov [z80_flag35], dl
686: %endif
687: %ifnidn %2, dl
688: mov %2, dl
689: %endif
690: xor dh, dh
691: %endif
692: %endmacro
693:
694: ; Shift method, reg8
695: %macro DO_SHF 2
696: %ifnidn %2, dl
697: mov dl, %2
698: %endif
699:
700: %ifidn %1, SLA
701: add dl, dl
702: adc dh, dh
703: %elifidn %1, SLL
704: add dl, dl
705: adc dh, dh
706: inc dl
707: %elifidn %1, SRA
708: sar dl, 1
709: adc dh, dh
710: %elifidn %1, SRL
711: shr dl, 1
712: adc dh, dh
713: %endif
714:
715: test dl, dl
716: lahf
717: and zF, FLAG_S|FLAG_Z|FLAG_P
718: or zF, dh
719: %ifdef EMULATE_BITS_3_5
720: mov [z80_flag35], dl
721: %endif
722: %ifnidn %2, dl
723: mov %2, dl
724: %endif
725: xor dh, dh
726: %endmacro
727:
728: ; BIT r,n n = bit (0-7)
729: ; r = 8-bit register
730: %macro DO_BIT 2
731: and zF, FLAG_C
732: test %1, (1 << %2)
733: %ifdef EMULATE_BITS_3_5
734: ; bit 3 and 5 are set from the register
735: ; (actually they are bizarrely set, but
736: ; there's no point emulating that, it's just
737: ; plain silly...)
738: %ifnidn %1, dl
739: mov dl, %1 ; put in DL if not there already
740: %endif
741: mov [z80_flag35], dl
742: %endif
743:
744: jz %%bit_is_clear
745: %ifidn %2, 7
746: or zF, FLAG_H|FLAG_S ; set sign bit, if testing bit 7
747: %else
748: or zF, FLAG_H ; set half-carry, and parity
749: %endif
750: jmp %%finish
751:
752: %%bit_is_clear:
753: or zF, FLAG_H|FLAG_Z|FLAG_P ; set half-carry, parity, and zero
754: %%finish:
755: %endmacro
756:
757: ; SET r,n n = bit (0-7)
758: ; r = 8-bit register
759: %macro DO_SET 2
760: or %1, (1 << %2)
761: %endmacro
762:
763: ; RES r,n n = bit (0-7)
764: ; r = 8-bit register
765: %macro DO_RES 2
766: and %1, ~(1 << %2)
767: %endmacro
768:
769: ;----------------------------------------------------------------------------;
770: ; Here are the interface functions:
771:
772: ; Move a register to another
773: ; LD_R_R d8, s8 s8 = src reg, d8 = dest reg
774: %macro LD_R_R 2
775: %ifnidn %1, %2
776: %ifidn %2, D
777: mov dl, zD
778: mov z%1, dl
779: %elifidn %2, E
780: mov dl, zE
781: mov z%1, dl
782: %else
783: mov z%1, z%2
784: %endif
785: %endif
786: DO_CYCLES
787: NEXT
788: %endmacro
789:
790: ; Move a register to another (IXh/IXl)
791: ; LD_XYr_XYr d8, s8 s8 = src reg, d8 = dest reg
792: %macro LD_XYr_XYr 2
793: %ifnidn %1, %2
794: mov dl, z%2
795: mov z%1, dl
796: %endif
797: DO_CYCLES
798: NEXT
799: %endmacro
800:
801: ; Move an immediate byte into a register
802: ; LD_R_N d8 d8 = dest reg
803: %macro LD_R_N 1
804: GETBYTE
805: mov z%1, dl
806: DO_CYCLES
807: NEXT
808: %endmacro
809:
810: ; Move from (RR) into a register
811: ; LD_R_mRR d8, s16 d8 = dest reg, s16 = src reg
812: %macro LD_R_mRR 2
813: mov edi, ez%2
814: MEMREAD
815: mov z%1, dl
816: DO_CYCLES
817: NEXT
818: %endmacro
819:
820: ; Move from (XY+dd) into a register
821: ; LD_R_mXY d8, s16 d8 = dest reg, s16 = src reg
822: %macro LD_R_mXY 2
823: GETDISP
824: add di, z%2
825: MEMREAD
826: mov z%1, dl
827: DO_CYCLES
828: NEXT
829: %endmacro
830:
831: ; Move from a register into (RR)
832: ; LD_mRR_R d16, s8 d16 = destreg, s8 = src reg
833: %macro LD_mRR_R 2
834: mov edi, ez%1
835: mov dl, z%2
836: MEMWRITE
837: DO_CYCLES
838: NEXT
839: %endmacro
840:
841: ; Move from a register into (XY+dd)
842: ; LD_mXY_R d16, s8 d16 = dest reg, s8 = src reg
843: %macro LD_mXY_R 2
844: GETDISP
845: add di, z%1
846: mov dl, z%2
847: MEMWRITE
848: DO_CYCLES
849: NEXT
850: %endmacro
851:
852: ; Move an immediate into (RR)
853: ; LD_mRR_N d16 d16 = dest reg
854: %macro LD_mRR_N 1
855: GETBYTE
856: mov edi, ez%1
857: MEMWRITE
858: DO_CYCLES
859: NEXT
860: %endmacro
861:
862: ; Move an immediate into (XY+dd)
863: ; LD_mXY_N d16 d16 = dest reg
864: %macro LD_mXY_N 1
865: GETDISP
866: add di, z%1
867: push edi
868: GETBYTE
869: pop edi
870: MEMWRITE
871: DO_CYCLES
872: NEXT
873: %endmacro
874:
875: ; Move from (NN) into a register
876: ; LD_R_mNN d8 d8 = dest reg
877: %macro LD_R_mNN 1
878: GETWORD
879: MEMREAD
880: mov z%1, dl
881: DO_CYCLES
882: NEXT
883: %endmacro
884:
885: ; Move from a register into (NN)
886: ; LD_mNN_R s8 s8 = src reg
887: %macro LD_mNN_R 1
888: GETWORD
889: mov dl, z%1
890: MEMWRITE
891: DO_CYCLES
892: NEXT
893: %endmacro
894:
895: ; Move the Interrupt register into a register
896: ; LD_R_I d8 d8 = dest reg
897: %macro LD_R_I 1
898: mov z%1, zI
899: and zF, FLAG_C ; keep old carry
900: mov dl, zF
901:
902: test z%1, z%1
903: lahf
904: and zF, FLAG_S|FLAG_Z ; set S/Z from the I register
905: or zF, dl
906: or zF, [z80_IFF2]
907: %ifdef EMULATE_BITS_3_5
908: mov [z80_flag35], z%1
909: %endif
910: DO_CYCLES
911: NEXT
912: %endmacro
913:
914: ; Move a register into the Interrupt register
915: ; LD_I_R s8 s8 = src reg
916: %macro LD_I_R 1
917: mov zI, z%1
918: DO_CYCLES
919: NEXT
920: %endmacro
921:
922: ; Move the Refresh register into a register
923: ; LD_R_Rf d8 d8 = dest reg
924: %macro LD_R_Rf 1
925: mov edx, [z80_R2]
926: and edx, 80h ; take bits 0-6 from R, bit 7 from R2
927:
928: %ifndef EMULATE_R_REGISTER
929: ; attempt to fake the R-register
930: ; take the ICount, invert it, divide by 4
931: ; this produces an increasing counter, roughly proportional to
932: ; the number of instructions done
933: mov zR, [z80_ICount]
934: not zR
935: shr zR, 2
936: %endif
937:
938: and zR, 7fh
939: or edx, zR
940: mov z%1, dl
941:
942: mov dl, zF
943: and dl, FLAG_C ; keep the old carry
944:
945: test z%1, z%1
946: lahf
947: and zF, FLAG_S|FLAG_Z
948: or zF, dl
949: or zF, [z80_IFF2]
950: %ifdef EMULATE_BITS_3_5
951: mov [z80_flag35], z%1
952: %endif
953: DO_CYCLES
954: NEXT
955: %endmacro
956:
957: ; Move a register into the Refresh register
958: ; LD_Rf_R s8 s8 = src reg
959: %macro LD_Rf_R 1
960: mov dl, z%1
961: mov zR, edx
962: mov [z80_R2], edx
963: DO_CYCLES
964: NEXT
965: %endmacro
966:
967: ; Move a 16-bit immediate into a register
968: ; LD_RR_NN d16 d16 = dest reg
969: %macro LD_RR_NN 1
970: GETWORD
971: mov ez%1, edi
972: DO_CYCLES
973: NEXT
974: %endmacro
975:
976: ; Move from (NN) into a 16-bit register
977: ; LD_RR_mNN d16 d16 = dest reg
978: %macro LD_RR_mNN 1
979: GETWORD
980: MEMREAD
981: mov lz%1, dl
982: inc di
983: MEMREAD
984: mov hz%1, dl
985: DO_CYCLES
986: NEXT
987: %endmacro
988:
989: ; Move from a 16-bit register into (NN)
990: ; LD_mNN_RR s16 s16 = src reg
991: %macro LD_mNN_RR 1
992: GETWORD
993: mov dl, lz%1
994: MEMWRITE
995: inc di
996: mov dl, hz%1
997: MEMWRITE
998: DO_CYCLES
999: NEXT
1000: %endmacro
1001:
1002: ; Move from a 16-bit register into another
1003: ; LD_RR_RR d16, s16 s16 = src reg, d16 = dest reg
1004: %macro LD_RR_RR 2
1005: mov ez%1, ez%2
1006: DO_CYCLES
1007: NEXT
1008: %endmacro
1009:
1010: ; Move from a 16-bit register into another
1011: ; LD_RR_XY d16, s16 s16 = src reg, d16 = dest reg
1012: %macro LD_RR_XY 2
1013: mov edi, ez%2
1014: mov ez%1, edi
1015: DO_CYCLES
1016: NEXT
1017: %endmacro
1018:
1019: ; Push a word on the stack
1020: ; PUSH_RR s16 s16 = src reg
1021: %macro PUSH_RR 1
1022: mov dl, hz%1
1023: dec zSP
1024: mov edi, ezSP
1025: MEMWRITE
1026: dec zSP
1027: mov edi, ezSP
1028: %ifidn %1, AF
1029: ; merge bits 3 and 5 in
1030: and zF, ~(FLAG_3|FLAG_5)
1031: mov dl, [z80_flag35]
1032: and dl, FLAG_3|FLAG_5
1033: or zF, dl
1034: %endif
1035: mov dl, lz%1
1036: MEMWRITE
1037: DO_CYCLES
1038: NEXT
1039: %endmacro
1040:
1041: ; Pop a word from the stack
1042: ; POP_RR s16 s16 = src reg
1043: %macro POP_RR 1
1044: mov edi, ezSP
1045: MEMREAD
1046: %ifidn %1, AF
1047: mov [z80_flag35], dl ; take out bits 3/5
1048: %endif
1049: mov lz%1, dl
1050: inc zSP
1051: mov edi, ezSP
1052: MEMREAD
1053: mov hz%1, dl
1054: inc zSP
1055: DO_CYCLES
1056: NEXT
1057: %endmacro
1058:
1059: ; Exchange 2 16-bit registers
1060: ; EX_RR_RR s16, d16 s16 = src reg, d16 = dest reg
1061: %macro EX_RR_RR 2
1062: xchg ez%1, ez%2
1063: DO_CYCLES
1064: NEXT
1065: %endmacro
1066:
1067: ; Exchange AF with AF'
1068: ; EX_AF_AF2
1069: %macro EX_AF_AF2 0
1070: ; Merge bits 3+5 of the flags in first
1071: and zF, ~(FLAG_3|FLAG_5)
1072: mov dl, [z80_flag35]
1073: and dl, FLAG_3|FLAG_5
1074: or zF, dl
1075: xchg ezAF, ezAF2
1076:
1077: ; Un-merge the flags again
1078: mov [z80_flag35], zF
1079: DO_CYCLES
1080: NEXT
1081: %endmacro
1082:
1083: ; Exchange the 16-bit registers with their primes
1084: ; EXX
1085: %macro EXX 0
1086: mov edi, ezDE
1087: xchg ezBC, ezBC2
1088: xchg ezHL, ezHL2
1089: xchg edi, ezDE2
1090: mov ezDE, edi
1091: DO_CYCLES
1092: NEXT
1093: %endmacro
1094:
1095: ; Exchange a 16-bit register with (RR)
1096: ; EX_RR_mRR d16, m16 d16 = dest reg, m16 = memory reg
1097: %macro EX_RR_mRR 2
1098: mov edi, ez%2 ; swap low byte
1099: MEMREAD
1100: xchg dl, lz%1
1101: MEMWRITE
1102:
1103: inc di ; swap high byte
1104: MEMREAD
1105: xchg dl, hz%1
1106: MEMWRITE
1107:
1108: DO_CYCLES
1109: NEXT
1110: %endmacro
1111:
1112: ; Move from (HL) to (DE), post-increment
1113: ; LDI
1114: %macro LDI 0
1115: mov edi, ezHL
1116: MEMREAD
1117: %ifdef EMULATE_BITS_3_5
1118: push edx
1119: %endif
1120: mov edi, ezDE
1121: MEMWRITE
1122:
1123: %ifdef EMULATE_BITS_3_5
1124: pop edx
1125: add dl, zA
1126: mov dh, dl
1127: shl dl, 4
1128: and edx, FLAG_5 | (FLAG_3 << 8)
1129: or dl, dh
1130: mov [z80_flag35], dl
1131: xor dh, dh
1132: %endif
1133:
1134: and zF, FLAG_S|FLAG_Z|FLAG_C
1135: inc zHL
1136: inc zDE
1137: dec zBC
1138: jz %%ldi_zero
1139: or zF, FLAG_P
1140: %%ldi_zero:
1141: DO_CYCLES
1142: NEXT
1143: %endmacro
1144:
1145: ; Move from (HL) to (DE), post-decrement
1146: ; LDD
1147: %macro LDD 0
1148: mov edi, ezHL
1149: MEMREAD
1150: %ifdef EMULATE_BITS_3_5
1151: push edx
1152: %endif
1153: mov edi, ezDE
1154: MEMWRITE
1155:
1156: %ifdef EMULATE_BITS_3_5
1157: pop edx
1158: add dl, zA
1159: mov dh, dl
1160: shl dl, 4
1161: and edx, FLAG_5 | (FLAG_3 << 8)
1162: or dl, dh
1163: mov [z80_flag35], dl
1164: xor dh, dh
1165: %endif
1166:
1167: and zF, FLAG_S|FLAG_Z|FLAG_C
1168: dec zHL
1169: dec zDE
1170: dec zBC
1171: jz %%ldd_zero
1172: or zF, FLAG_P
1173: %%ldd_zero:
1174: DO_CYCLES
1175: NEXT
1176: %endmacro
1177:
1178: ; Move from (HL) to (DE), post-increment, repeat
1179: ; LDIR
1180: %macro LDIR 0
1181: %ifdef EMULATE_WEIRD_STUFF
1182: ; Code marked with CG is from Charles Gallagher, to fix the
1183: ; Spectrum game 'Quazatron'
1184: push ezPC ; CG
1185: sub zPC, 2 ; CG
1186: mov edi, ezPC ; CG
1187: shr edi, 8 ; CG
1188: add ezPC, [z80_Fetch+edi*4] ; CG
1189: %endif
1190:
1191: %%ldir_loop:
1192: %ifdef EMULATE_WEIRD_STUFF
1193: cmp [ezPC], word 0b0edh ; CG - check for self modifiying code!
1194: jne near %%ldir_modified
1195: %endif
1196:
1197: mov edi, ezHL
1198: MEMREAD
1199: %ifdef EMULATE_BITS_3_5
1200: push edx
1201: %endif
1202: mov edi, ezDE
1203: MEMWRITE
1204: %ifdef EMULATE_BITS_3_5
1205: pop edx
1206: %endif
1207:
1208: inc zHL
1209: inc zDE
1210: dec zBC
1211: jz %%ldir_zero
1212:
1213: %ifdef EMULATE_R_REGISTER
1214: inc zR
1215: %endif
1216: sub [z80_ICount], dword extra_cycles
1217: ja near %%ldir_loop
1218:
1219: %ifdef EMULATE_WEIRD_STUFF
1220: pop ezPC ; CG
1221: %endif
1222:
1223: and zF, FLAG_S|FLAG_Z|FLAG_C
1224: %ifdef EMULATE_BITS_3_5
1225: add dl, zA
1226: mov dh, dl
1227: shl dl, 4
1228: and edx, FLAG_5 | (FLAG_3 << 8)
1229: or dl, dh
1230: mov [z80_flag35], dl
1231: xor dh, dh
1232: %endif
1233: or zF, FLAG_P
1234: sub zPC, 2 ; rewind to instruction start
1235: EXIT
1236:
1237: %ifdef EMULATE_WEIRD_STUFF
1238: %%ldir_modified:
1239: sub [esp], word 2 ; CG
1240: %endif
1241:
1242: %%ldir_zero:
1243: %ifdef EMULATE_WEIRD_STUFF
1244: pop ezPC ; CG
1245: %endif
1246: and zF, FLAG_S|FLAG_Z|FLAG_C
1247: %ifdef EMULATE_BITS_3_5
1248: add dl, zA
1249: mov dh, dl
1250: shl dl, 4
1251: and edx, FLAG_5 | (FLAG_3 << 8)
1252: or dl, dh
1253: mov [z80_flag35], dl
1254: xor dh, dh
1255: %endif
1256: DO_CYCLES
1257: NEXT
1258: %endmacro
1259:
1260: ; Move from (HL) to (DE), post-decrement, repeat
1261: ; LDDR
1262: %macro LDDR 0
1263: %%lddr_loop:
1264: mov edi, ezHL
1265: MEMREAD
1266: %ifdef EMULATE_BITS_3_5
1267: push edx
1268: %endif
1269: mov edi, ezDE
1270: MEMWRITE
1271: %ifdef EMULATE_BITS_3_5
1272: pop edx
1273: %endif
1274:
1275: dec zHL
1276: dec zDE
1277: dec zBC
1278: jz %%lddr_zero
1279:
1280: %ifdef EMULATE_R_REGISTER
1281: inc zR
1282: %endif
1283: sub [z80_ICount], dword extra_cycles
1284: ja near %%lddr_loop
1285:
1286: and zF, FLAG_S|FLAG_Z|FLAG_C
1287: %ifdef EMULATE_BITS_3_5
1288: add dl, zA
1289: mov dh, dl
1290: shl dl, 4
1291: and edx, FLAG_5 | (FLAG_3 << 8)
1292: or dl, dh
1293: mov [z80_flag35], dl
1294: xor dh, dh
1295: %endif
1296: or zF, FLAG_P
1297: sub zPC, 2 ; rewind to instruction start
1298: EXIT
1299:
1300: %%lddr_zero:
1301: and zF, FLAG_S|FLAG_Z|FLAG_C
1302: %ifdef EMULATE_BITS_3_5
1303: add dl, zA
1304: mov dh, dl
1305: shl dl, 4
1306: and edx, FLAG_5 | (FLAG_3 << 8)
1307: or dl, dh
1308: mov [z80_flag35], dl
1309: xor dh, dh
1310: %endif
1311: DO_CYCLES
1312: NEXT
1313: %endmacro
1314:
1315: ; Compare A against (HL), post-increment
1316: ; CPI
1317: %macro CPI 0
1318: mov edi, ezHL
1319: MEMREAD
1320:
1321: and zF, FLAG_C ; keep the old carry
1322: mov dh, zF
1323: cmp zA, dl
1324: lahf
1325: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1326: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1327:
1328: inc zHL
1329: dec zBC
1330: jz %%cpi_zero
1331: or zF, FLAG_P ; set P if BC != 0
1332: %%cpi_zero:
1333:
1334: %ifdef EMULATE_BITS_3_5
1335: mov dh, zA
1336: sub dh, dl
1337: test zF, FLAG_H
1338: jz %%cpi_hzero
1339: dec dh
1340: %%cpi_hzero:
1341:
1342: mov dl, dh
1343: shl dl, 4
1344: and edx, FLAG_5 | (FLAG_3 << 8)
1345: or dl, dh
1346: mov [z80_flag35], dl
1347: %endif
1348: xor dh, dh
1349:
1350: DO_CYCLES
1351: NEXT
1352: %endmacro
1353:
1354: ; Compare A against (HL), post-decrement
1355: ; CPD
1356: %macro CPD 0
1357: mov edi, ezHL
1358: MEMREAD
1359:
1360: and zF, FLAG_C ; keep the old carry
1361: mov dh, zF
1362: cmp zA, dl
1363: lahf
1364: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1365: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1366:
1367: dec zHL
1368: dec zBC
1369: jz %%cpd_zero
1370: or zF, FLAG_P ; set P if BC != 0
1371: %%cpd_zero:
1372:
1373: %ifdef EMULATE_BITS_3_5
1374: mov dh, zA
1375: sub dh, dl
1376: test zF, FLAG_H
1377: jz %%cpd_hzero
1378: dec dh
1379: %%cpd_hzero:
1380:
1381: mov dl, dh
1382: shl dl, 4
1383: and edx, FLAG_5 | (FLAG_3 << 8)
1384: or dl, dh
1385: mov [z80_flag35], dl
1386: %endif
1387: xor dh, dh
1388:
1389: DO_CYCLES
1390: NEXT
1391: %endmacro
1392:
1393: ; Compare A against (HL), post-increment, repeat
1394: ; CPIR
1395: %macro CPIR 0
1396: and zF, FLAG_C ; keep the old carry
1397: %%cpir_loop:
1398: mov edi, ezHL
1399: MEMREAD
1400:
1401: inc zHL
1402: dec zBC
1403: jz %%cpir_end_bc ; end due to BC=0
1404:
1405: %ifdef EMULATE_R_REGISTER
1406: inc zR
1407: %endif
1408: cmp zA, dl
1409: je %%cpir_end_equal ; end due to A=(HL)
1410:
1411: sub [z80_ICount], dword extra_cycles
1412: ja %%cpir_loop
1413:
1414: ; out of cycles, but not finished
1415: mov dh, zF
1416: cmp zA, dl
1417: lahf
1418: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1419: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1420:
1421: %ifdef EMULATE_BITS_3_5
1422: mov dh, zA
1423: sub dh, dl
1424: test zF, FLAG_H
1425: jz %%cpir_hzero
1426: dec dh
1427: %%cpir_hzero:
1428:
1429: mov dl, dh
1430: shl dl, 4
1431: and edx, FLAG_5 | (FLAG_3 << 8)
1432: or dl, dh
1433: mov [z80_flag35], dl
1434: %endif
1435: or zF, FLAG_P ; set P to indicate not finished
1436: sub zPC, 2 ; rewind to instruction start
1437: xor dh, dh
1438: EXIT
1439:
1440: %%cpir_end_equal:
1441: or zF, FLAG_P ; set P to indicate not finished
1442: %%cpir_end_bc:
1443: mov dh, zF
1444: cmp zA, dl
1445: lahf
1446: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1447: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1448:
1449: %ifdef EMULATE_BITS_3_5
1450: mov dh, zA
1451: sub dh, dl
1452: test zF, FLAG_H
1453: jz %%cpir_hzero2
1454: dec dh
1455: %%cpir_hzero2:
1456:
1457: mov dl, dh
1458: shl dl, 4
1459: and edx, FLAG_5 | (FLAG_3 << 8)
1460: or dl, dh
1461: mov [z80_flag35], dl
1462: %endif
1463: xor dh, dh
1464: DO_CYCLES
1465: NEXT
1466: %endmacro
1467:
1468: ; Compare A against (HL), post-decrement, repeat
1469: ; CPDR
1470: %macro CPDR 0
1471: and zF, FLAG_C ; keep the old carry
1472: %%cpdr_loop:
1473: mov edi, ezHL
1474: MEMREAD
1475:
1476: dec zHL
1477: dec zBC
1478: jz %%cpdr_end_bc ; end due to BC=0
1479:
1480: %ifdef EMULATE_R_REGISTER
1481: inc zR
1482: %endif
1483: cmp zA, dl
1484: je %%cpdr_end_equal ; end due to A=(HL)
1485:
1486: sub [z80_ICount], dword extra_cycles
1487: ja %%cpdr_loop
1488:
1489: ; out of cycles, but not finished
1490: mov dh, zF
1491: cmp zA, dl
1492: lahf
1493: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1494: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1495:
1496: %ifdef EMULATE_BITS_3_5
1497: mov dh, zA
1498: sub dh, dl
1499: test zF, FLAG_H
1500: jz %%cpdr_hzero
1501: dec dh
1502: %%cpdr_hzero:
1503:
1504: mov dl, dh
1505: shl dl, 4
1506: and edx, FLAG_5 | (FLAG_3 << 8)
1507: or dl, dh
1508: mov [z80_flag35], dl
1509: %endif
1510: or zF, FLAG_P ; set P to indicate not finished
1511: sub zPC, 2 ; rewind to instruction start
1512: xor dh, dh
1513: EXIT
1514:
1515: %%cpdr_end_equal:
1516: or zF, FLAG_P ; set P to indicate not finished
1517: %%cpdr_end_bc:
1518: mov dh, zF
1519: cmp zA, dl
1520: lahf
1521: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1522: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1523:
1524: %ifdef EMULATE_BITS_3_5
1525: mov dh, zA
1526: sub dh, dl
1527: test zF, FLAG_H
1528: jz %%cpdr_hzero2
1529: dec dh
1530: %%cpdr_hzero2:
1531:
1532: mov dl, dh
1533: shl dl, 4
1534: and edx, FLAG_5 | (FLAG_3 << 8)
1535: or dl, dh
1536: mov [z80_flag35], dl
1537: %endif
1538: xor dh, dh
1539: DO_CYCLES
1540: NEXT
1541: %endmacro
1542:
1543: ; Perform arithmetic on the A register
1544: ; ART_R method, src8
1545: %macro ART_R 2
1546: %ifidn %1, ADD
1547: DO_ADD z%2
1548: %elifidn %1, ADC
1549: DO_ADC z%2
1550: %elifidn %1, SUB
1551: DO_SUB z%2
1552: %elifidn %1, SBC
1553: DO_SBC z%2
1554: %endif
1555:
1556: DO_CYCLES
1557: NEXT
1558: %endmacro
1559:
1560: ; Perform arithmetic on the A register (using an immediate)
1561: ; ART_N method
1562: %macro ART_N 1
1563: GETBYTE
1564: %ifidn %1, ADD
1565: DO_ADD dl
1566: %elifidn %1, ADC
1567: DO_ADC dl
1568: %elifidn %1, SUB
1569: DO_SUB dl
1570: %elifidn %1, SBC
1571: DO_SBC dl
1572: %endif
1573:
1574: DO_CYCLES
1575: NEXT
1576: %endmacro
1577:
1578: ; Perform arithmetic on the A register, using (XY)
1579: ; ART_mXY method, src16
1580: %macro ART_mXY 2
1581: GETDISP
1582: add di, z%2
1583: MEMREAD
1584: %ifidn %1, ADD
1585: DO_ADD dl
1586: %elifidn %1, ADC
1587: DO_ADC dl
1588: %elifidn %1, SUB
1589: DO_SUB dl
1590: %elifidn %1, SBC
1591: DO_SBC dl
1592: %endif
1593:
1594: DO_CYCLES
1595: NEXT
1596: %endmacro
1597:
1598: ; Perform arithmetic on the A register using (RR)
1599: ; ART_mRR method, src16
1600: %macro ART_mRR 2
1601: mov edi, ez%2
1602: MEMREAD
1603: %ifidn %1, ADD
1604: DO_ADD dl
1605: %elifidn %1, ADC
1606: DO_ADC dl
1607: %elifidn %1, SUB
1608: DO_SUB dl
1609: %elifidn %1, SBC
1610: DO_SBC dl
1611: %endif
1612:
1613: DO_CYCLES
1614: NEXT
1615: %endmacro
1616:
1617: ; Perform logic on the A register
1618: ; LOG_R method, src8
1619: %macro LOG_R 2
1620: %ifidn %1, AND
1621: DO_AND z%2
1622: %elifidn %1, OR
1623: DO_OR z%2
1624: %elifidn %1, XOR
1625: DO_XOR z%2
1626: %endif
1627:
1628: DO_CYCLES
1629: NEXT
1630: %endmacro
1631:
1632: ; Perform logic on the A register (using an immediate)
1633: ; LOG_N method
1634: %macro LOG_N 1
1635: GETBYTE
1636: %ifidn %1, AND
1637: DO_AND dl
1638: %elifidn %1, OR
1639: DO_OR dl
1640: %elifidn %1, XOR
1641: DO_XOR dl
1642: %endif
1643:
1644: DO_CYCLES
1645: NEXT
1646: %endmacro
1647:
1648: ; Perform logic on the A register, using (RR)
1649: ; LOG_mRR method, src16
1650: %macro LOG_mRR 2
1651: mov edi, ez%2
1652: MEMREAD
1653: %ifidn %1, AND
1654: DO_AND dl
1655: %elifidn %1, OR
1656: DO_OR dl
1657: %elifidn %1, XOR
1658: DO_XOR dl
1659: %endif
1660:
1661: DO_CYCLES
1662: NEXT
1663: %endmacro
1664:
1665: ; Perform logic on the A register, using (XY+dd)
1666: ; LOG_mXY method, src16
1667: %macro LOG_mXY 2
1668: GETDISP
1669: add di, z%2
1670: MEMREAD
1671: %ifidn %1, AND
1672: DO_AND dl
1673: %elifidn %1, OR
1674: DO_OR dl
1675: %elifidn %1, XOR
1676: DO_XOR dl
1677: %endif
1678:
1679: DO_CYCLES
1680: NEXT
1681: %endmacro
1682:
1683: ; Compare against the A register
1684: ; CP_R src8
1685: %macro CP_R 1
1686: DO_CP z%1
1687:
1688: DO_CYCLES
1689: NEXT
1690: %endmacro
1691:
1692: ; Compare against the A register, using an immediate
1693: ; CP_N
1694: %macro CP_N 0
1695: GETBYTE
1696: DO_CP dl
1697:
1698: DO_CYCLES
1699: NEXT
1700: %endmacro
1701:
1702: ; Compare against the A register, using (RR)
1703: ; CP_mRR src16
1704: %macro CP_mRR 1
1705: mov edi, ez%1
1706: MEMREAD
1707: DO_CP dl
1708:
1709: DO_CYCLES
1710: NEXT
1711: %endmacro
1712:
1713: ; Compare against the A register, using (XY+dd)
1714: ; CP_mXY src16
1715: %macro CP_mXY 1
1716: GETDISP
1717: add di, z%1
1718: MEMREAD
1719: DO_CP dl
1720:
1721: DO_CYCLES
1722: NEXT
1723: %endmacro
1724:
1725: ; Inc/dec a register
1726: ; DECINC_R method, reg8
1727: %macro DECINC_R 2
1728: %ifidn %1, INC
1729: DO_INC z%2
1730: %elifidn %1, DEC
1731: DO_DEC z%2
1732: %endif
1733:
1734: DO_CYCLES
1735: NEXT
1736: %endmacro
1737:
1738: ; Inc/dec (RR)
1739: ; DECINC_mRR method
1740: %macro DECINC_mRR 2
1741: mov edi, ez%2
1742: MEMREAD
1743: %ifidn %1, INC
1744: DO_INC dl
1745: %elifidn %1, DEC
1746: DO_DEC dl
1747: %endif
1748: MEMWRITE
1749:
1750: DO_CYCLES
1751: NEXT
1752: %endmacro
1753:
1754: ; Inc/dec (XY+dd)
1755: ; DECINC_mXY method
1756: %macro DECINC_mXY 2
1757: GETDISP
1758: add di, z%2
1759: MEMREAD
1760: %ifidn %1, INC
1761: DO_INC dl
1762: %elifidn %1, DEC
1763: DO_DEC dl
1764: %endif
1765: MEMWRITE
1766:
1767: DO_CYCLES
1768: NEXT
1769: %endmacro
1770:
1771: ; Add two 16-bit registers
1772: ; ADD_RR_RR dest16, src16
1773: %macro ADD_RR_RR 2
1774: DO_ADD16 z%1, z%2
1775:
1776: DO_CYCLES
1777: NEXT
1778: %endmacro
1779:
1780: ; Add two 16-bit registers, with carry
1781: ; ADC_RR_RR dest16, src16
1782: %macro ADC_RR_RR 2
1783: DO_ADC16 z%1, z%2
1784:
1785: DO_CYCLES
1786: NEXT
1787: %endmacro
1788:
1789: ; Subtract two 16-bit registers, with carry
1790: ; SBC_RR_RR dest16, src16
1791: %macro SBC_RR_RR 2
1792: DO_SBC16 z%1, z%2
1793:
1794: DO_CYCLES
1795: NEXT
1796: %endmacro
1797:
1798: ; Inc/dec a 16-bit register
1799: ; DECINC_RR method, reg16
1800: %macro DECINC_RR 2
1801: %ifidn %1, INC
1802: inc z%2
1803: %elifidn %1, DEC
1804: dec z%2
1805: %endif
1806:
1807: DO_CYCLES
1808: NEXT
1809: %endmacro
1810:
1811: ; Rotate a register
1812: ; ROT_R method, reg8
1813: %macro ROT_R 2
1814: DO_ROT %1, z%2
1815:
1816: DO_CYCLES
1817: NEXT
1818: %endmacro
1819:
1820: ; Rotate (RR)
1821: ; ROT_mRR method, src16
1822: %macro ROT_mRR 2
1823: mov edi, ez%2
1824: MEMREAD
1825: DO_ROT %1, dl
1826: MEMWRITE
1827:
1828: DO_CYCLES
1829: NEXT
1830: %endmacro
1831:
1832: ; Rotate (XY+dd)
1833: ; ROT_mXY method
1834: %macro ROT_mXY 1
1835: MEMREAD
1836: DO_ROT %1, dl
1837: MEMWRITE
1838:
1839: DO_CYCLES
1840: NEXT
1841: %endmacro
1842:
1843: ; Rotate (XY+dd), and store into a register
1844: ; ROT_mXY_R method, dest8
1845: %macro ROT_mXY_R 2
1846: MEMREAD
1847: DO_ROT %1, dl
1848: mov z%2, dl
1849: MEMWRITE
1850:
1851: DO_CYCLES
1852: NEXT
1853: %endmacro
1854:
1855: ; Shift a register
1856: ; SHF_R method, reg8
1857: %macro SHF_R 2
1858: DO_SHF %1, z%2
1859:
1860: DO_CYCLES
1861: NEXT
1862: %endmacro
1863:
1864: ; Shift (RR)
1865: ; SHF_mRR method, src16
1866: %macro SHF_mRR 2
1867: mov edi, ez%2
1868: MEMREAD
1869: DO_SHF %1, dl
1870: MEMWRITE
1871:
1872: DO_CYCLES
1873: NEXT
1874: %endmacro
1875:
1876: ; Shift (XY+dd)
1877: ; SHF_mXY method
1878: %macro SHF_mXY 1
1879: MEMREAD
1880: DO_SHF %1, dl
1881: MEMWRITE
1882:
1883: DO_CYCLES
1884: NEXT
1885: %endmacro
1886:
1887: ; Shift (XY+dd), and store into a register
1888: ; SHF_mXY_R method, dest8
1889: %macro SHF_mXY_R 2
1890: MEMREAD
1891: DO_SHF %1, dl
1892: mov z%2, dl
1893: MEMWRITE
1894:
1895: DO_CYCLES
1896: NEXT
1897: %endmacro
1898:
1899: ; Rotate A/(HL) left, via nibbles
1900: ; RLD
1901: %macro RLD 0
1902: mov edi, ezHL
1903: MEMREAD
1904: mov dh, zA
1905: and zF, FLAG_C
1906: shl dh, 4
1907: rol dx, 4
1908: and zA, 0f0h
1909: or zA, dh
1910: mov dh, zF
1911: lahf
1912: and zF, FLAG_S|FLAG_Z|FLAG_P
1913: or zF, dh
1914: %ifdef EMULATE_BITS_3_5
1915: mov [z80_flag35], zA
1916: %endif
1917: MEMWRITE
1918:
1919: DO_CYCLES
1920: NEXT
1921: %endmacro
1922:
1923: ; Rotate A/(HL) right, via nibbles
1924: ; RRD
1925: %macro RRD 0
1926: mov edi, ezHL
1927: MEMREAD
1928: mov dh, zA
1929: and zF, FLAG_C
1930: ror dx, 4
1931: shr dh, 4
1932: and zA, 0f0h
1933: or zA, dh
1934: mov dh, zF
1935: lahf
1936: and zF, FLAG_S|FLAG_Z|FLAG_P
1937: or zF, dh
1938: %ifdef EMULATE_BITS_3_5
1939: mov [z80_flag35], zA
1940: %endif
1941: MEMWRITE
1942:
1943: DO_CYCLES
1944: NEXT
1945: %endmacro
1946:
1947: ; Bit-test a register
1948: ; BIT_R src8, bit
1949: %macro BIT_R_b 2
1950: DO_BIT z%1, %2
1951:
1952: DO_CYCLES
1953: NEXT
1954: %endmacro
1955:
1956: ; Bit-test (RR)
1957: ; BIT_mRR_b src16, bit
1958: %macro BIT_mRR_b 2
1959: and zF, FLAG_C
1960: mov edi, ez%1
1961: MEMREAD
1962:
1963: test dl, (1 << %2)
1964:
1965: ; bit 3 and 5 are always cleared
1966: ; (actually they are bizarrely set, but
1967: ; there's no point emulating that, it's just
1968: ; plain silly...)
1969:
1970: jz %%bit_is_clear
1971: %ifidn %2, 7
1972: or zF, FLAG_H|FLAG_S ; set sign bit, if testing bit 7
1973: %else
1974: or zF, FLAG_H ; set half-carry, and parity
1975: %endif
1976: jmp %%finish
1977:
1978: %%bit_is_clear:
1979: or zF, FLAG_H|FLAG_Z|FLAG_P ; set half-carry, parity, and zero
1980: %%finish:
1981:
1982: DO_CYCLES
1983: NEXT
1984: %endmacro
1985:
1986: ; Bit-test (XY+dd)
1987: ; BIT_mXY_b bit
1988: %macro BIT_mXY_b 1
1989: %ifdef EMULATE_BITS_3_5
1990: mov edx, edi
1991: mov [z80_flag35], dh
1992: %endif
1993:
1994: MEMREAD
1995: and zF, FLAG_C
1996: test dl, (1 << %1)
1997:
1998: jz %%bit_is_clear
1999: %ifidn %1, 7
2000: or zF, FLAG_H|FLAG_S ; set sign bit, if testing bit 7
2001: %else
2002: or zF, FLAG_H ; set half-carry, and parity
2003: %endif
2004: jmp %%finish
2005:
2006: %%bit_is_clear:
2007: or zF, FLAG_H|FLAG_Z|FLAG_P ; set half-carry, parity, and zero
2008: %%finish:
2009:
2010: DO_CYCLES
2011: NEXT
2012: %endmacro
2013:
2014: ; Bit-clear a register
2015: ; RES_R_b src8, bit
2016: %macro RES_R_b 2
2017: DO_RES z%1, %2
2018:
2019: DO_CYCLES
2020: NEXT
2021: %endmacro
2022:
2023: ; Bit-clear (RR)
2024: ; RES_mRR_b src16, bit
2025: %macro RES_mRR_b 2
2026: mov edi, ez%1
2027: MEMREAD
2028: DO_RES dl, %2
2029: MEMWRITE
2030:
2031: DO_CYCLES
2032: NEXT
2033: %endmacro
2034:
2035: ; Bit-clear (XY+dd)
2036: ; RES_mXY_b bit
2037: %macro RES_mXY_b 1
2038: MEMREAD
2039: DO_RES dl, %1
2040: MEMWRITE
2041:
2042: DO_CYCLES
2043: NEXT
2044: %endmacro
2045:
2046: ; Bit-clear (XY+dd), with extra store
2047: ; RES_mXY_b_R bit, dest8
2048: %macro RES_mXY_b_R 2
2049: MEMREAD
2050: DO_RES dl, %1
2051: mov z%2, dl
2052: MEMWRITE
2053:
2054: DO_CYCLES
2055: NEXT
2056: %endmacro
2057:
2058: ; Bit-set a register
2059: ; SET_R_b src8, bit
2060: %macro SET_R_b 2
2061: DO_SET z%1, %2
2062:
2063: DO_CYCLES
2064: NEXT
2065: %endmacro
2066:
2067: ; Bit-set (RR)
2068: ; SET_mRR_b src16, bit
2069: %macro SET_mRR_b 2
2070: mov edi, ez%1
2071: MEMREAD
2072: DO_SET dl, %2
2073: MEMWRITE
2074:
2075: DO_CYCLES
2076: NEXT
2077: %endmacro
2078:
2079: ; Bit-set (XY+dd)
2080: ; SET_mXY_b bit
2081: %macro SET_mXY_b 1
2082: MEMREAD
2083: DO_SET dl, %1
2084: MEMWRITE
2085:
2086: DO_CYCLES
2087: NEXT
2088: %endmacro
2089:
2090: ; Bit-set (XY+dd), with extra store
2091: ; SET_mXY_b_R bit, dest8
2092: %macro SET_mXY_b_R 2
2093: MEMREAD
2094: DO_SET dl, %1
2095: mov z%2, dl
2096: MEMWRITE
2097:
2098: DO_CYCLES
2099: NEXT
2100: %endmacro
2101:
2102: ; Jump to an absolute address
2103: ; JP_NN
2104: %macro JP_NN 0
2105: GETWORD
2106: mov ezPC, edi
2107: DO_CYCLES
2108: NEXT
2109: %endmacro
2110:
2111: ; Jump to an absolute address, conditionally
2112: ; JP_cc_NN nz,cc
2113: %macro JP_cc_NN 2
2114: test zF, FLAG_%2
2115: j%1 near %%dont_take_jump
2116: GETWORD
2117: mov ezPC, edi
2118: DO_CYCLES
2119: NEXT
2120:
2121: ALIGN
2122: %%dont_take_jump:
2123: add zPC, 2 ; skip address
2124: DO_CYCLES
2125: NEXT
2126: %endmacro
2127:
2128: ; Jump to an relative address
2129: ; JR_N
2130: %macro JR_N 0
2131: GETDISP
2132: add zPC, di
2133: DO_CYCLES
2134: NEXT
2135: %endmacro
2136:
2137: ; Jump to an relative address, conditionally
2138: ; JR_cc_N nz,cc
2139: %macro JR_cc_N 2
2140: test zF, FLAG_%2
2141: j%1 near %%dont_take_jump
2142: GETDISP
2143: add zPC, di
2144: DO_EXTRA_CYCLES
2145: NEXT
2146:
2147: ALIGN
2148: %%dont_take_jump:
2149: inc zPC ; skip over the displacement
2150: DO_CYCLES
2151: NEXT
2152: %endmacro
2153:
2154: ; Jump to an absolute address (in a register)
2155: ; JP_RR addr16
2156: %macro JP_RR 1
2157: mov ezPC, ez%1
2158: DO_CYCLES
2159: NEXT
2160: %endmacro
2161:
2162: ; Decrease B, if non-zero, jump to a relative address
2163: ; DJNZ_N
2164: %macro DJNZ_N 0
2165: dec zB
2166: jz near %%dont_take_jump
2167: GETDISP
2168: add zPC, di
2169: DO_EXTRA_CYCLES
2170: NEXT
2171:
2172: ALIGN
2173: %%dont_take_jump:
2174: inc zPC ; skip over the displacement
2175: DO_CYCLES
2176: NEXT
2177: %endmacro
2178:
2179: ; Call an absolute address
2180: ; CALL_NN
2181: %macro CALL_NN 0
2182: GETWORD
2183: mov edx, ezPC ; write the PC
2184: dec zSP
2185: push edi
2186:
2187: xchg dl, dh
2188: mov edi, ezSP
2189: MEMWRITE
2190: dec zSP
2191: mov edx, ezPC
2192: mov edi, ezSP
2193: MEMWRITE
2194:
2195: pop ezPC ; get the new PC
2196: DO_CYCLES
2197: NEXT
2198: %endmacro
2199:
2200: ; Call an absolute address, conditionally
2201: ; CALL_cc_NN
2202: %macro CALL_cc_NN 2
2203: test zF, FLAG_%2
2204: j%1 near %%dont_take_jump
2205: GETWORD
2206: mov edx, ezPC ; write the PC
2207: push edi
2208:
2209: dec zSP
2210: xchg dl, dh
2211: mov edi, ezSP
2212: MEMWRITE
2213: dec zSP
2214: mov edx, ezPC
2215: mov edi, ezSP
2216: MEMWRITE
2217:
2218: pop ezPC ; get the new PC
2219: DO_CYCLES
2220: NEXT
2221:
2222: ALIGN
2223: %%dont_take_jump:
2224: add zPC, 2 ; skip address
2225: DO_CYCLES
2226: NEXT
2227: %endmacro
2228:
2229: ; Pop the PC
2230: ; RET
2231: %macro RET 0
2232: mov edi, ezSP
2233: MEMREAD
2234: inc zSP
2235: mov ezPC, edx
2236: mov edi, ezSP
2237: MEMREAD
2238: xchg dl, dh
2239: or ezPC, edx
2240: inc zSP
2241:
2242: xor dh, dh
2243: DO_CYCLES
2244: NEXT
2245: %endmacro
2246:
2247: ; Pop the PC, conditionally
2248: ; RET_cc
2249: %macro RET_cc 2
2250: test zF, FLAG_%2
2251: j%1 near %%dont_take_jump
2252: mov edi, ezSP
2253: MEMREAD
2254: inc zSP
2255: mov ezPC, edx
2256: mov edi, ezSP
2257: MEMREAD
2258: xchg dl, dh
2259: or ezPC, edx
2260: inc zSP
2261:
2262: xor dh, dh
2263: DO_CYCLES
2264: NEXT
2265:
2266: ALIGN
2267: %%dont_take_jump:
2268: DO_CYCLES
2269: NEXT
2270: %endmacro
2271:
2272: ; Pop the PC, restore IFF1, signal the BUS
2273: ; RETI
2274: %macro RETI 0
2275: mov edi, ezSP
2276: MEMREAD
2277: mov ezPC, edx
2278: inc zSP
2279: mov edi, ezSP
2280: MEMREAD
2281: xchg dl, dh
2282: or ezPC, edx
2283: inc zSP
2284:
2285: mov dl, [z80_IFF2]
2286: mov [z80_IFF1], dl
2287: call [z80_RetI] ; signal the user handler
2288:
2289: DO_CYCLES
2290: NEXT
2291: %endmacro
2292:
2293: ; Pop the PC, restore IFF1
2294: ; RETN
2295: %macro RETN 0
2296: mov edi, ezSP
2297: MEMREAD
2298: mov ezPC, edx
2299: inc zSP
2300: mov edi, ezSP
2301: MEMREAD
2302: xchg dl, dh
2303: or ezPC, edx
2304: inc zSP
2305:
2306: mov dl, [z80_IFF2]
2307: mov [z80_IFF1], dl
2308: DO_CYCLES
2309: NEXT
2310: %endmacro
2311:
2312: ; Call an absolute address
2313: ; RST addr8
2314: %macro RST 1
2315: dec zSP
2316: mov edx, ezPC ; write the PC
2317: xchg dl, dh
2318: mov edi, ezSP
2319: MEMWRITE
2320: dec zSP
2321: mov edx, ezPC
2322: mov edi, ezSP
2323: MEMWRITE
2324:
2325: mov ezPC, %1 ; get the new PC
2326: DO_CYCLES
2327: NEXT
2328: %endmacro
2329:
2330: ; Out R to R*256+N
2331: ; OUT_N_R src8
2332: %macro OUT_N_R 1
2333: GETBYTE
2334: mov dh, z%1
2335: mov edi, edx
2336: mov dl, z%1
2337: IOWRITE
2338: DO_CYCLES
2339: NEXT
2340: %endmacro
2341:
2342: ; In from R*256+N, into R
2343: ; IN_R_N dest8
2344: %macro IN_R_N 1
2345: GETBYTE
2346: mov dh, z%1
2347: mov edi, edx
2348: IOREAD
2349: mov z%1, dl
2350: DO_CYCLES
2351: NEXT
2352: %endmacro
2353:
2354: ; In from BC
2355: ; IN_R dest8
2356: %macro IN_R 1
2357: mov edi, ezBC
2358: IOREAD
2359: mov dh, zF
2360: and dh, FLAG_C ; keep the old carry
2361: mov z%1, dl
2362: test dl, dl ; other flags come from the result
2363: lahf
2364: and zF, FLAG_S|FLAG_Z|FLAG_P
2365: or zF, dh
2366: %ifdef EMULATE_BITS_3_5
2367: mov [z80_flag35], dl
2368: %endif
2369: xor dh, dh
2370:
2371: DO_CYCLES
2372: NEXT
2373: %endmacro
2374:
2375: ; In from BC, ignore result
2376: ; IN_F
2377: %macro IN_F 0
2378: mov edi, ezBC
2379: IOREAD
2380: mov dh, zF
2381: and dh, FLAG_C ; keep the old carry
2382: test dl, dl ; other flags come from the result
2383: lahf
2384: and zF, FLAG_S|FLAG_Z|FLAG_P
2385: or zF, dh
2386: %ifdef EMULATE_BITS_3_5
2387: mov [z80_flag35], dl
2388: %endif
2389: xor dh, dh
2390:
2391: DO_CYCLES
2392: NEXT
2393: %endmacro
2394:
2395: ; Out to BC
2396: ; OUT_R src8
2397: %macro OUT_R 1
2398: mov edi, ezBC
2399: mov dl, z%1
2400: IOWRITE
2401: DO_CYCLES
2402: NEXT
2403: %endmacro
2404:
2405: ; Out zero to BC
2406: ; OUT_0
2407: %macro OUT_0 0
2408: mov edi, ezBC
2409: xor dl, dl
2410: IOWRITE
2411: DO_CYCLES
2412: NEXT
2413: %endmacro
2414:
2415: ; In from BC into (HL), increase HL, decrease B
2416: %macro INI 0
2417: ; FIXME - Parity flag is not emulated
2418: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2419:
2420: IOREAD ; read from the port
2421: mov edi, ezHL
2422: %ifdef EMULATE_WEIRD_STUFF
2423: push edx ; preserve the value
2424: %endif
2425: MEMWRITE ; write to (HL)
2426: %ifdef EMULATE_WEIRD_STUFF
2427: pop edx
2428: %endif
2429:
2430: inc zHL ; increase HL
2431: dec zB ; decrease B
2432: %ifdef EMULATE_BITS_3_5
2433: mov [z80_flag35], zB
2434: %endif
2435:
2436: lahf
2437: and zF, FLAG_S|FLAG_Z|FLAG_P
2438:
2439: ; This is a prime example of the weirdness of the Z80...
2440: %ifdef EMULATE_WEIRD_STUFF
2441: mov dh, zC
2442: inc dh
2443: add dh, dl
2444: jnc %%no_carry
2445: or zF, FLAG_H|FLAG_C
2446: %%no_carry:
2447: shr dl, 6
2448: and edx, FLAG_N
2449: or zF, dl
2450: %endif
2451: DO_CYCLES
2452: NEXT
2453: %endmacro
2454:
2455: ; In from BC into (HL), decrease HL, decrease B
2456: %macro IND 0
2457: ; FIXME - Parity flag is not emulated
2458: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2459:
2460: IOREAD ; read from the port
2461: mov edi, ezHL
2462: %ifdef EMULATE_WEIRD_STUFF
2463: push edx ; preserve the value
2464: %endif
2465: MEMWRITE ; write to (HL)
2466: %ifdef EMULATE_WEIRD_STUFF
2467: pop edx
2468: %endif
2469:
2470: dec zHL ; increase HL
2471: dec zB ; decrease B
2472: %ifdef EMULATE_BITS_3_5
2473: mov [z80_flag35], zB
2474: %endif
2475:
2476: lahf
2477: and zF, FLAG_S|FLAG_Z|FLAG_P
2478:
2479: ; This is a prime example of the weirdness of the Z80...
2480: %ifdef EMULATE_WEIRD_STUFF
2481: mov dh, zC
2482: dec dh
2483: add dh, dl
2484: jnc %%no_carry
2485: or zF, FLAG_H|FLAG_C
2486: %%no_carry:
2487: shr dl, 6
2488: and edx, FLAG_N
2489: or zF, dl
2490: %endif
2491: DO_CYCLES
2492: NEXT
2493: %endmacro
2494:
2495: ; In from BC into (HL), increase HL, decrease B, repeat
2496: %macro INIR 0
2497: ; FIXME - Parity flag is not emulated
2498: %%inir_loop:
2499: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2500:
2501: IOREAD ; read from the port
2502: mov edi, ezHL
2503: %ifdef EMULATE_WEIRD_STUFF
2504: push edx ; preserve the value
2505: %endif
2506: MEMWRITE ; write to (HL)
2507: %ifdef EMULATE_WEIRD_STUFF
2508: pop edx
2509: %endif
2510:
2511: inc zHL ; increase HL
2512: dec zB ; decrease B
2513: jz %%inir_zero
2514:
2515: sub [z80_ICount], dword extra_cycles
2516: ja near %%inir_loop ; repeat while cycles left and B>0
2517:
2518: ; out of cycles, but operation not finished
2519: %ifdef EMULATE_BITS_3_5
2520: mov [z80_flag35], zB
2521: %endif
2522:
2523: mov zF, zB
2524: and zF, FLAG_S
2525:
2526: ; This is a prime example of the weirdness of the Z80...
2527: %ifdef EMULATE_WEIRD_STUFF
2528: mov dh, zC
2529: inc dh
2530: add dh, dl
2531: jnc %%no_carry
2532: or zF, FLAG_H|FLAG_C
2533: %%no_carry:
2534: shr dl, 6
2535: and edx, FLAG_N
2536: or zF, dl
2537: %endif
2538: sub zPC, 2 ; rewind to instruction start
2539: EXIT
2540:
2541: ; B=0
2542: %%inir_zero:
2543: mov zF, FLAG_Z|FLAG_P
2544: %ifdef EMULATE_BITS_3_5
2545: mov [z80_flag35], zF
2546: %endif
2547:
2548: ; This is a prime example of the weirdness of the Z80...
2549: %ifdef EMULATE_WEIRD_STUFF
2550: mov dh, zC
2551: inc dh
2552: add dh, dl
2553: jnc %%no_carry2
2554: or zF, FLAG_H|FLAG_C
2555: %%no_carry2:
2556: shr dl, 6
2557: and edx, FLAG_N
2558: or zF, dl
2559: %endif
2560: DO_CYCLES
2561: NEXT
2562: %endmacro
2563:
2564: ; In from BC into (HL), decrease HL, decrease B, repeat
2565: %macro INDR 0
2566: ; FIXME - Parity flag is not emulated
2567: %%indr_loop:
2568: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2569:
2570: IOREAD ; read from the port
2571: mov edi, ezHL
2572: %ifdef EMULATE_WEIRD_STUFF
2573: push edx ; preserve the value
2574: %endif
2575: MEMWRITE ; write to (HL)
2576: %ifdef EMULATE_WEIRD_STUFF
2577: pop edx
2578: %endif
2579:
2580: dec zHL ; decrease HL
2581: dec zB ; decrease B
2582: jz %%indr_zero
2583:
2584: sub [z80_ICount], dword extra_cycles
2585: ja near %%indr_loop ; repeat while cycles left and B>0
2586:
2587: ; out of cycles, but operation not finished
2588: %ifdef EMULATE_BITS_3_5
2589: mov [z80_flag35], zB
2590: %endif
2591:
2592: mov zF, zB
2593: and zF, FLAG_S
2594:
2595: ; This is a prime example of the weirdness of the Z80...
2596: %ifdef EMULATE_WEIRD_STUFF
2597: mov dh, zC
2598: inc dh
2599: add dh, dl
2600: jnc %%no_carry
2601: or zF, FLAG_H|FLAG_C
2602: %%no_carry:
2603: shr dl, 6
2604: and edx, FLAG_N
2605: or zF, dl
2606: %endif
2607: sub zPC, 2 ; rewind to instruction start
2608: EXIT
2609:
2610: ; B=0
2611: %%indr_zero:
2612: mov zF, FLAG_Z|FLAG_P
2613: %ifdef EMULATE_BITS_3_5
2614: mov [z80_flag35], zF
2615: %endif
2616:
2617: ; This is a prime example of the weirdness of the Z80...
2618: %ifdef EMULATE_WEIRD_STUFF
2619: mov dh, zC
2620: inc dh
2621: add dh, dl
2622: jnc %%no_carry2
2623: or zF, FLAG_H|FLAG_C
2624: %%no_carry2:
2625: shr dl, 6
2626: and edx, FLAG_N
2627: or zF, dl
2628: %endif
2629: DO_CYCLES
2630: NEXT
2631: %endmacro
2632:
2633: ; Out from (HL) into BC, increase HL, decrease B
2634: %macro OUTI 0
2635: ; FIXME - Parity flag is not emulated
2636: mov edi, ezHL
2637:
2638: MEMREAD ; read from (HL)
2639: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2640: %ifdef EMULATE_WEIRD_STUFF
2641: push edx ; preserve the value
2642: %endif
2643: IOWRITE ; write to the port
2644: %ifdef EMULATE_WEIRD_STUFF
2645: pop edx
2646: %endif
2647:
2648: inc zHL ; increase HL
2649: dec zB ; decrease B
2650: %ifdef EMULATE_BITS_3_5
2651: mov [z80_flag35], zB
2652: %endif
2653:
2654: lahf
2655: and zF, FLAG_S|FLAG_Z|FLAG_P
2656:
2657: ; This is a prime example of the weirdness of the Z80...
2658: %ifdef EMULATE_WEIRD_STUFF
2659: mov dh, zC
2660: inc dh
2661: add dh, dl
2662: jnc %%no_carry
2663: or zF, FLAG_H|FLAG_C
2664: %%no_carry:
2665: shr dl, 6
2666: and edx, FLAG_N
2667: or zF, dl
2668: %endif
2669: DO_CYCLES
2670: NEXT
2671: %endmacro
2672:
2673: ; Out from (HL) into BC, decrease HL, decrease B
2674: %macro OUTD 0
2675: ; FIXME - Parity flag is not emulated
2676: mov edi, ezHL
2677:
2678: MEMREAD ; read from (HL)
2679: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2680: %ifdef EMULATE_WEIRD_STUFF
2681: push edx ; preserve the value
2682: %endif
2683: IOWRITE ; write to the port
2684: %ifdef EMULATE_WEIRD_STUFF
2685: pop edx
2686: %endif
2687:
2688: dec zHL ; decrease HL
2689: dec zB ; decrease B
2690: %ifdef EMULATE_BITS_3_5
2691: mov [z80_flag35], zB
2692: %endif
2693:
2694: lahf
2695: and zF, FLAG_S|FLAG_Z|FLAG_P
2696:
2697: ; This is a prime example of the weirdness of the Z80...
2698: %ifdef EMULATE_WEIRD_STUFF
2699: mov dh, zC
2700: inc dh
2701: add dh, dl
2702: jnc %%no_carry
2703: or zF, FLAG_H|FLAG_C
2704: %%no_carry:
2705: shr dl, 6
2706: and edx, FLAG_N
2707: or zF, dl
2708: %endif
2709: DO_CYCLES
2710: NEXT
2711: %endmacro
2712:
2713: ; Out from (HL) into BC, increase HL, decrease B, repeat
2714: %macro OTIR 0
2715: %%otir_loop:
2716: mov edi, ezHL
2717: MEMREAD
2718: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2719: %ifdef EMULATE_WEIRD_STUFF
2720: push edx ; preserve the value
2721: %endif
2722: IOWRITE
2723: %ifdef EMULATE_WEIRD_STUFF
2724: pop edx
2725: %endif
2726:
2727: inc zHL
2728: dec zB
2729: jz %%otir_zero
2730:
2731: %ifdef EMULATE_R_REGISTER
2732: inc zR
2733: %endif
2734: sub [z80_ICount], dword extra_cycles
2735: ja near %%otir_loop
2736:
2737: ; out of cycles, but not finished
2738: %ifdef EMULATE_BITS_3_5
2739: mov [z80_flag35], zB
2740: %endif
2741:
2742: mov zF, zB
2743: and zF, FLAG_S
2744:
2745: %ifdef EMULATE_WEIRD_STUFF
2746: mov dh, zC
2747: inc dh
2748: add dh, dl
2749: jnc %%otir_nocarry
2750: or zF, FLAG_H|FLAG_C
2751: %%otir_nocarry:
2752: shr dl, 6
2753: and edx, FLAG_N
2754: or zF, dl
2755: %endif
2756: sub zPC, 2 ; rewind to instruction start
2757: EXIT
2758:
2759: %%otir_zero:
2760: mov zF, FLAG_Z|FLAG_P
2761: %ifdef EMULATE_BITS_3_5
2762: mov [z80_flag35], zF
2763: %endif
2764: %ifdef EMULATE_WEIRD_STUFF
2765: mov dh, zC
2766: inc dh
2767: add dh, dl
2768: jnc %%otir_nocarry2
2769: or zF, FLAG_H|FLAG_C
2770: %%otir_nocarry2:
2771: shr dl, 6
2772: and edx, FLAG_N
2773: or zF, dl
2774: %endif
2775: DO_CYCLES
2776: NEXT
2777: %endmacro
2778:
2779: ; Out from (HL) into BC, decrease HL, decrease B, repeat
2780: %macro OTDR 0
2781: %%otdr_loop:
2782: mov edi, ezHL
2783: MEMREAD
2784: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2785: %ifdef EMULATE_WEIRD_STUFF
2786: push edx ; preserve the value
2787: %endif
2788: IOWRITE
2789: %ifdef EMULATE_WEIRD_STUFF
2790: pop edx
2791: %endif
2792:
2793: dec zHL
2794: dec zB
2795: jz %%otdr_zero
2796:
2797: %ifdef EMULATE_R_REGISTER
2798: inc zR
2799: %endif
2800: sub [z80_ICount], dword extra_cycles
2801: ja near %%otdr_loop
2802:
2803: ; out of cycles, but not finished
2804: %ifdef EMULATE_BITS_3_5
2805: mov [z80_flag35], zB
2806: %endif
2807:
2808: mov zF, zB
2809: and zF, FLAG_S
2810:
2811: %ifdef EMULATE_WEIRD_STUFF
2812: mov dh, zC
2813: inc dh
2814: add dh, dl
2815: jnc %%otdr_nocarry
2816: or zF, FLAG_H|FLAG_C
2817: %%otdr_nocarry:
2818: shr dl, 6
2819: and edx, FLAG_N
2820: or zF, dl
2821: %endif
2822: sub zPC, 2 ; rewind to instruction start
2823: EXIT
2824:
2825: %%otdr_zero:
2826: mov zF, FLAG_Z|FLAG_P
2827: %ifdef EMULATE_BITS_3_5
2828: mov [z80_flag35], zF
2829: %endif
2830: %ifdef EMULATE_WEIRD_STUFF
2831: mov dh, zC
2832: inc dh
2833: add dh, dl
2834: jnc %%otdr_nocarry2
2835: or zF, FLAG_H|FLAG_C
2836: %%otdr_nocarry2:
2837: shr dl, 6
2838: and edx, FLAG_N
2839: or zF, dl
2840: %endif
2841: DO_CYCLES
2842: NEXT
2843: %endmacro
2844:
2845: ; BCD adjust
2846: %macro DAA 0
2847: test zF, FLAG_H
2848: jnz %%daa_h_set
2849: and eax, 03ffh
2850: mov ax, [DAA_Table + eax*2]
2851: %ifdef EMULATE_BITS_3_5
2852: mov [z80_flag35], zF
2853: %endif
2854: DO_CYCLES
2855: NEXT
2856:
2857: %%daa_h_set:
2858: and eax, 03ffh
2859: mov ax, [DAA_Table + eax*2 + 4*512]
2860: %ifdef EMULATE_BITS_3_5
2861: mov [z80_flag35], zF
2862: %endif
2863: DO_CYCLES
2864: NEXT
2865: %endmacro
2866:
2867: ; Complement A
2868: %macro CPL 0
2869: not zA
2870: or zF, FLAG_H|FLAG_N
2871: %ifdef EMULATE_BITS_3_5
2872: mov [z80_flag35], zA
2873: %endif
2874: DO_CYCLES
2875: NEXT
2876: %endmacro
2877:
2878: ; Negate A
2879: %macro NEG 0
2880: neg zA
2881: lahf
2882: %ifdef EMULATE_BITS_3_5
2883: mov [z80_flag35], zA
2884: %endif
2885: jo %%neg_overflow
2886: and zF, ~FLAG_P
2887: DO_CYCLES
2888: NEXT
2889:
2890: %%neg_overflow:
2891: or zF, FLAG_P
2892: DO_CYCLES
2893: NEXT
2894: %endmacro
2895:
2896: ; Set carry flag
2897: %macro SCF 0
2898: and zF, FLAG_S|FLAG_Z|FLAG_P
2899: or zF, FLAG_C
2900: %ifdef EMULATE_BITS_3_5
2901: mov [z80_flag35], zA
2902: %endif
2903: DO_CYCLES
2904: NEXT
2905: %endmacro
2906:
2907: ; Complement carry flag
2908: %macro CCF 0
2909: test zF, FLAG_C
2910: jz %%set_carry
2911: and zF, FLAG_S|FLAG_Z|FLAG_P
2912: or zF, FLAG_H
2913: %ifdef EMULATE_BITS_3_5
2914: mov [z80_flag35], zA
2915: %endif
2916: DO_CYCLES
2917: NEXT
2918:
2919: %%set_carry:
2920: SCF
2921: %endmacro
2922:
2923: ; No operation
2924: %macro NOP 0
2925: DO_CYCLES
2926: NEXT
2927: %endmacro
2928:
2929: ; Halt the processor
2930: %macro HALT 0
2931: and [z80_ICount], dword 3
2932: sub [z80_ICount], dword 4
2933: mov [z80_halted], byte 1
2934: EXIT
2935: %endmacro
2936:
2937: ; Enable interrupts
2938: %macro EI 0
2939: mov dl, FLAG_P ; set the P/V bit, for use in "LD I,A" etc
2940: mov [z80_IFF1], dl
2941: mov [z80_IFF2], dl
2942:
2943: ; force the next instruction to be executed, regardless of ICount
2944: ; then force an IRQ check after it.
2945: mov [z80_afterEI], byte 1
2946: push eax
2947: mov eax, [z80_ICount] ; set ICount to zero, so it will terminate
2948: mov [z80_TempICount], eax ; after the next instruction.
2949: mov [z80_ICount], dword 1 ; we can then pick it up again and carry on.
2950: pop eax
2951: NEXT
2952: %endmacro
2953:
2954: ; Disable interrupts
2955: %macro DI 0
2956: xor edx, edx
2957: mov [z80_IFF1], dl
2958: mov [z80_IFF2], dl
2959: DO_CYCLES
2960: NEXT
2961: %endmacro
2962:
2963: ; Set interrupt mode
2964: %macro IM 1
2965: mov [z80_IM], byte %1
2966: DO_CYCLES
2967: NEXT
2968: %endmacro
2969:
2970: ;----------------------------------------------------------------------------;
2971: ; Bring in the opcodes...
2972: %include 'raze.inc'
2973: ;----------------------------------------------------------------------------;
2974:
2975: ;----------------------------------------------------------------------------;
2976: ; Support functions:
2977:
2978: DEF op, cb, 0, 0
2979: %ifdef EMULATE_R_REGISTER
2980: inc zR
2981: %endif
2982: GETBYTE
2983: jmp [CBTable+edx*4]
2984:
2985: DEF op, ed, 0, 0
2986: %ifdef EMULATE_R_REGISTER
2987: inc zR
2988: %endif
2989: GETBYTE
2990: jmp [EDTable+edx*4]
2991:
2992: DEF op, dd, 0, 0
2993: %ifdef EMULATE_R_REGISTER
2994: inc zR
2995: %endif
2996: GETBYTE
2997: jmp [DDTable+edx*4]
2998:
2999: DEF op, fd, 0, 0
3000: %ifdef EMULATE_R_REGISTER
3001: inc zR
3002: %endif
3003: GETBYTE
3004: jmp [FDTable+edx*4]
3005:
3006: DEF dd, cb, 0, 0
3007: %ifdef EMULATE_R_REGISTER
3008: inc zR
3009: %endif
3010: GETDISP
3011: add di, zIX
3012: push edi
3013: GETBYTE
3014: pop edi
3015: jmp [DDCBTable+edx*4]
3016:
3017: DEF fd, cb, 0, 0
3018: %ifdef EMULATE_R_REGISTER
3019: inc zR
3020: %endif
3021: GETDISP
3022: add di, zIY
3023: push edi
3024: GETBYTE
3025: pop edi
3026: jmp [DDCBTable+edx*4]
3027:
3028: DEF ed, xx, 8, 0
3029: %ifdef EMULATE_R_REGISTER
3030: inc zR
3031: %endif
3032: DO_CYCLES
3033: NEXT
3034:
3035: DEF dd, xx, 4, 0
3036: dec zPC
3037: DO_CYCLES
3038: NEXT
3039:
3040: DEF fd, xx, 0, 0
3041: dec zPC
3042: DO_CYCLES
3043: NEXT
3044:
3045: ; called when out-of-cycles
3046: z80_finish:
3047: cmp [z80_afterEI], byte 1 ; test for the post-EI behaviour
3048: jne near really_finish
3049: push eax
3050: mov eax, [z80_TempICount]
3051: mov [z80_ICount], eax
3052: mov [z80_afterEI], byte 0
3053: pop eax
3054: CHECK_IRQ
3055: sub dword [z80_ICount], 4 ; subtract EI's cycles
3056: jbe near z80_finish
3057: NEXT
3058:
3059: really_finish:
3060: ; merge bits 3 and 5 of the flags into the regs
3061: and zF, ~(FLAG_3|FLAG_5)
3062: mov dl, [z80_flag35]
3063: and dl, FLAG_3|FLAG_5
3064: or zF, dl
3065:
3066: mov [z80_AF], ezAF
3067: mov [z80_HL], ezHL
3068: mov [z80_BC], ezBC
3069: mov [z80_PC], ezPC
3070: mov [z80_R], zR
3071: pop ebp
3072: pop edi
3073: pop esi
3074: pop ebx
3075: mov eax, [z80_Initial_ICount]
3076: sub eax, [z80_ICount]
3077: ret
3078:
3079: z80_default_in:
3080: z80_default_read:
3081: mov eax, 0ffh
3082: ret
3083:
3084: z80_default_out:
3085: z80_default_write:
3086: z80_default_reti:
3087: z80_default_fetch_callback:
3088: ret
3089:
3090: ; called to look up a read handler
3091: ; address is on the stack
3092: read_dispatcher:
3093: mov eax, [esp+4]
3094: mov edx, _read_handlers
3095: rd_find:
3096: add edx, 16
3097: cmp [edx-16], eax
3098: ja rd_find
3099: cmp [edx-12], eax
3100: jb rd_find
3101:
3102: cmp [edx-8], dword 1
3103: je rd_handler
3104:
3105: add eax, [edx-4]
3106: movzx eax, byte [eax]
3107: ret
3108:
3109: rd_handler:
3110: jmp [edx-4] ; call the GCC function
3111:
3112: ; called to look up a write handler
3113: ; address+value are on the stack
3114: write_dispatcher:
3115: mov eax, [esp+4]
3116: mov edx, _write_handlers
3117: wd_find:
3118: add edx, 16
3119: cmp [edx-16], eax
3120: ja wd_find
3121: cmp [edx-12], eax
3122: jb wd_find
3123:
3124: cmp [edx-8], dword 1
3125: je wd_handler
3126:
3127: add eax, [edx-4]
3128: mov ecx, [esp+8]
3129: mov [eax], cl
3130: ret
3131:
3132: wd_handler:
3133: jmp [edx-4] ; call the GCC function
3134:
3135: ; int z80_emulate(int cycles)
3136: ; Emulate for 'cycles' T-states,
3137: ; Returns the number of cycles actually emulated.
3138: cglobal z80_emulate
3139: z80_emulate:
3140: mov eax, [esp+4]
3141: push ebx
3142: push esi
3143: push edi
3144: push ebp
3145:
3146: add eax, [z80_Extra_Cycles]
3147: mov [z80_ICount], eax
3148: mov [z80_Initial_ICount], eax
3149: xor edx, edx
3150: xor edi, edi
3151: mov [z80_Extra_Cycles], edx
3152: mov [z80_afterEI], dl
3153: mov ezAF, [z80_AF]
3154: mov ezHL, [z80_HL]
3155: mov ezBC, [z80_BC]
3156: mov ezPC, [z80_PC]
3157: mov zR, [z80_R]
3158: mov [z80_flag35], zF ; take out bits 3/5
3159: cmp [z80_halted], byte 0
3160: je not_halted
3161: and [z80_ICount], dword 3 ; If we're halted, just skip it all.
3162: sub [z80_ICount], dword 4
3163: EXIT
3164: not_halted:
3165: NEXT
3166:
3167: ; void z80_reset(void)
3168: ; Resets the Z80.
3169: cglobal z80_reset
3170: z80_reset:
3171: push edi
3172: xor eax, eax ; just zero it all
3173: mov edi, context_start
3174: mov ecx, (registers_end - context_start)
3175: rep stosb
3176: pop edi
3177: mov [z80_IX], word 0ffffh
3178: mov [z80_IY], word 0ffffh
3179: mov [z80_AF], word 04000h
3180: ret
3181:
3182: ; void z80_raise_IRQ(UBYTE vector)
3183: ; Causes an interrupt with the given vector.
3184: ; In IM 0, the vector has to be an RST opcode.
3185: ; If interrupts are disabled, the interrupt will still happen as long as
3186: ; the IRQ line stays raised.
3187: cglobal z80_raise_IRQ
3188: z80_raise_IRQ:
3189: mov [z80_IRQLine], byte 1
3190: mov eax, [esp+4]
3191: mov [z80_IRQVector], al
3192:
3193: xor edx, edx
3194: push ebx
3195: push esi
3196: push edi
3197: push ebp
3198: CALLGCC_END ; grab our Z80 regs
3199:
3200: CHECK_IRQ
3201:
3202: CALLGCC_START
3203: pop ebp
3204: pop edi
3205: pop esi
3206: pop ebx
3207: ret
3208:
3209: ; void z80_lower_IRQ(void)
3210: ; Lowers the IRQ line.
3211: cglobal z80_lower_IRQ
3212: z80_lower_IRQ:
3213: mov [z80_IRQLine], byte 0
3214: ret
3215:
3216: ; void z80_cause_NMI(void)
3217: ; Causes a non-maskable interrupt.
3218: ; This will always be accepted.
3219: ; There is no raise/lower functions, as the NMI is edge-triggered.
3220: cglobal z80_cause_NMI
3221: z80_cause_NMI:
3222: xor edx, edx
3223: push ebx
3224: push esi
3225: push edi
3226: push ebp
3227: CALLGCC_END ; grab our Z80 regs
3228:
3229: ; disable interrupts
3230: mov [z80_IFF1], byte 0
3231:
3232: ; take up 11 T-states
3233: add [z80_Extra_Cycles], dword 11
3234: %ifdef EMULATE_R_REGISTER
3235: inc zR
3236: %endif
3237:
3238: mov [z80_halted], byte 0 ; Un-HALT us.
3239:
3240: mov edx, ezPC ; write the PC
3241: dec zSP
3242:
3243: xchg dl, dh
3244: mov edi, ezSP
3245: MEMWRITE
3246: dec zSP
3247: mov edx, ezPC
3248: mov edi, ezSP
3249: MEMWRITE
3250:
3251: mov ezPC, 66h ; set the new PC
3252:
3253: CALLGCC_START
3254: pop ebp
3255: pop edi
3256: pop esi
3257: pop ebx
3258: ret
3259:
3260: ; int z80_get_context_size(void)
3261: ; Returns the size of the context, in bytes
3262: cglobal z80_get_context_size
3263: z80_get_context_size:
3264: mov eax, (context_end - context_start) + 4 ; +4 for a safety buffer
3265: ret
3266:
3267:
3268: ; void z80_set_context(void *context)
3269: ; Copy the given context to the current Z80.
3270: cglobal z80_set_context
3271: z80_set_context:
3272: push esi
3273: push edi
3274: mov ecx, (context_end - context_start) / 4
3275: mov esi, [esp+12]
3276: mov edi, context_start
3277: rep movsd
3278: pop edi
3279: pop esi
3280: ret
3281:
3282: ; void z80_get_context(void *context)
3283: ; Copy the current Z80 to the given context.
3284: cglobal z80_get_context
3285: z80_get_context:
3286: push esi
3287: push edi
3288: mov ecx, (context_end - context_start) / 4
3289: mov edi, [esp+12]
3290: mov esi, context_start
3291: rep movsd
3292: pop edi
3293: pop esi
3294: ret
3295:
3296: ; int z80_get_cycles_elapsed(void)
3297: ; Returns the number of cycles emulated since z80_emulate was called.
3298: cglobal z80_get_cycles_elapsed
3299: z80_get_cycles_elapsed:
3300: mov eax, [z80_Initial_ICount]
3301: sub eax, [z80_ICount]
3302: cmp [z80_afterEI], byte 0
3303: je z80_gcd_fin
3304: sub eax, [z80_TempICount]
3305: z80_gcd_fin:
3306: ret
3307:
3308: ; void z80_stop_emulating(void)
3309: ; Stops the emulation dead. (waits for the current instruction to finish
3310: ; first though).
3311: ; The return value from z80_execute will obviously be lower than expected.
3312: cglobal z80_stop_emulating
3313: z80_stop_emulating:
3314: mov eax, [z80_ICount]
3315: sub [z80_Initial_ICount], eax
3316: cmp [z80_afterEI], byte 0
3317: je z80_se_fin
3318: mov ecx, [z80_TempICount]
3319: sub [z80_Initial_ICount], ecx
3320: z80_se_fin:
3321: mov [z80_ICount], dword 0
3322: mov [z80_TempICount], dword 0
3323: ret
3324:
3325: ; void z80_skip_idle(void)
3326: ; Stops the emulation dead. (waits for the current instruction to finish
3327: ; first though).
3328: ; The return value from z80_execute will appear as though it had executed
3329: ; all the instructions like normal.
3330: cglobal z80_skip_idle
3331: z80_skip_idle:
3332: mov [z80_ICount], dword 0
3333: mov [z80_TempICount], dword 0
3334: ret
3335:
3336: ; void z80_do_wait_states(int n)
3337: ; Halts the CPU temporarily, to execute 'n' memory wait states.
3338: cglobal z80_do_wait_states
3339: z80_do_wait_states:
3340: add [z80_Initial_ICount], eax
3341: ret
3342:
3343: ; UWORD z80_get_reg(z80_register reg)
3344: ; Return the value of the specified register.
3345: cglobal z80_get_reg
3346: z80_get_reg:
3347: mov ecx, [esp+4]
3348: cmp ecx, Z80_REG_HL2
3349: mov eax, [context_start + ecx*4]
3350: jbe getreg_simple
3351:
3352: cmp ecx, Z80_REG_IFF1
3353: mov al, [z80_IFF1]
3354: je getreg_boolean
3355:
3356: cmp ecx, Z80_REG_IFF2
3357: mov al, [z80_IFF2]
3358: je getreg_boolean
3359:
3360: cmp ecx, Z80_REG_IRQLine
3361: mov al, [z80_IRQLine]
3362: je getreg_boolean
3363:
3364: cmp ecx, Z80_REG_Halted
3365: mov al, [z80_halted]
3366: je getreg_boolean
3367:
3368: cmp ecx, Z80_REG_IM
3369: movzx eax, byte [z80_IM]
3370: je getreg_finish
3371:
3372: cmp ecx, Z80_REG_IRQVector
3373: movzx eax, byte [z80_IRQVector]
3374: je getreg_finish
3375:
3376: ; construct IR
3377: mov eax, [z80_R]
3378: and eax, 7fh
3379: mov edx, [z80_R2]
3380: and edx, 80h
3381: or eax, edx
3382: mov ah, byte [z80_I]
3383: ret
3384:
3385: getreg_simple:
3386: cmp ecx, Z80_REG_AF
3387: je getreg_swap
3388: cmp ecx, Z80_REG_AF2
3389: je getreg_swap
3390: getreg_finish:
3391: ret
3392: getreg_swap:
3393: xchg al, ah ; swap A and F
3394: ret
3395:
3396: getreg_boolean:
3397: and eax, 0ffh
3398: jz getreg_finish
3399: mov al, 1
3400: ret
3401:
3402: ; void z80_set_reg(z80_register reg, UWORD value)
3403: ; Set the specified register to a new value.
3404: cglobal z80_set_reg
3405: z80_set_reg:
3406: mov ecx, [esp+4]
3407: mov eax, [esp+8]
3408: and eax, 0ffffh
3409: cmp ecx, Z80_REG_HL2
3410: jbe setreg_simple
3411:
3412: cmp ecx, Z80_REG_IFF1
3413: lea edx, [z80_IFF1]
3414: jbe setreg_boolean
3415:
3416: cmp ecx, Z80_REG_IFF2
3417: lea edx, [z80_IFF2]
3418: jbe setreg_boolean
3419:
3420: cmp ecx, Z80_REG_IRQLine
3421: lea edx, [z80_IRQLine]
3422: je setreg_boolean
3423:
3424: cmp ecx, Z80_REG_Halted
3425: lea edx, [z80_halted]
3426: je setreg_boolean
3427:
3428: cmp ecx, Z80_REG_IM
3429: lea edx, [z80_IM]
3430: je setreg_value
3431:
3432: cmp ecx, Z80_REG_IRQVector
3433: lea edx, [z80_IRQVector]
3434: je setreg_value
3435:
3436: ; deconstruct IR
3437: mov [z80_I], ah
3438: mov [z80_R2], eax
3439: mov [z80_R], eax
3440: ret
3441:
3442: setreg_simple:
3443: cmp ecx, Z80_REG_AF
3444: je setreg_swap
3445: cmp ecx, Z80_REG_AF2
3446: je setreg_swap
3447: setreg_finish:
3448: mov [context_start + ecx*4], eax
3449: ret
3450: setreg_swap:
3451: xchg al, ah ; swap A and F
3452: mov [context_start + ecx*4], eax
3453: ret
3454:
3455: setreg_boolean:
3456: test eax, eax
3457: jz setreg_value
3458: mov al, FLAG_P
3459:
3460: setreg_value:
3461: mov [edx], al
3462: ret
3463:
3464: ; void z80_init_memmap(void)
3465: ; Reset the current memory map
3466: cglobal z80_init_memmap
3467: z80_init_memmap:
3468: mov [z80_In], dword z80_default_in
3469: mov [z80_Out], dword z80_default_out
3470: mov [z80_RetI], dword z80_default_reti
3471: mov [z80_Fetch_Callback], dword z80_default_fetch_callback
3472:
3473: push edi ; clear the memory handlers
3474: mov eax, -1
3475: mov ecx, MAX_MEM_HANDLERS*4
3476: mov edi, _read_handlers
3477: rep stosd
3478: mov ecx, MAX_MEM_HANDLERS*4
3479: mov edi, _write_handlers
3480: rep stosd
3481:
3482: ; reset the read table
3483: mov edi, z80_Read
3484: mov ecx, 100h
3485: clear_read:
3486: mov [edi], dword z80_default_read
3487: add edi, 8
3488: loop clear_read
3489:
3490: ; reset the write table
3491: mov edi, z80_Write
3492: mov ecx, 100h
3493: clear_write:
3494: mov [edi], dword z80_default_write
3495: add edi, 8
3496: loop clear_write
3497:
3498: pop edi
3499: ret
3500:
3501: ; void z80_end_memmap(void)
3502: ; Finishes the current memory map
3503: cglobal z80_end_memmap
3504: z80_end_memmap:
3505: ; put the entry at the end of the read table
3506: mov edx, _read_handlers
3507: er_find:
3508: add edx, 16
3509: cmp [edx-16], dword (-1)
3510: jne er_find
3511: sub edx, 16
3512:
3513: ; put it in there
3514: mov [edx], dword 0
3515: mov [edx+4], dword 0ffffh
3516: mov [edx+8], dword 0
3517: mov [edx+12], dword z80_default_read
3518:
3519: ; put the entry at the end of the write table
3520: mov edx, _write_handlers
3521: ew_find:
3522: add edx, 16
3523: cmp [edx-16], dword (-1)
3524: jne ew_find
3525: sub edx, 16
3526:
3527: ; put it in there
3528: mov [edx], dword 0
3529: mov [edx+4], dword 0ffffh
3530: mov [edx+8], dword 0
3531: mov [edx+12], dword z80_default_write
3532: ret
3533:
3534: ; void z80_map_fetch(UWORD start, UWORD end, UBYTE *memory)
3535: ; Set the given area for op-code fetching
3536: ; start/end = the area it covers
3537: ; memory = the ROM/RAM to read from
3538: cglobal z80_map_fetch
3539: z80_map_fetch:
3540: push ebx
3541: mov eax, [esp+8]
3542: mov ebx, [esp+12]
3543: mov ecx, [esp+16]
3544: and eax, 0ffffh
3545: and ebx, 0ffffh
3546: sub ecx, eax
3547:
3548: mf_loop:
3549: ; if there's no area left inbetween, stop now.
3550: mov edx, eax
3551: shr edx, 8
3552:
3553: cmp eax, ebx
3554: ja mf_finish
3555:
3556: mov [z80_Fetch+edx*4], ecx
3557: add eax, 0100h
3558: jmp mf_loop
3559:
3560: mf_finish:
3561: pop ebx
3562: ret
3563:
3564: ; void z80_map_read(UWORD start, UWORD end, UBYTE *memory)
3565: ; Moves a Z80_MAP_MAPPED area to use a different region of memory
3566: ; start/end = the area it covers (must be page-aligned)
3567: ; memory = the ROM/RAM to read from
3568: cglobal z80_map_read
3569: z80_map_read:
3570: push ebx
3571: mov eax, [esp+8]
3572: mov ebx, [esp+12]
3573: mov ecx, [esp+16]
3574: and eax, 0ffffh
3575: and ebx, 0ffffh
3576: sub ecx, eax
3577:
3578: mr_loop:
3579: ; if there's no area left inbetween, stop now.
3580: mov edx, eax
3581: shr edx, 8
3582:
3583: cmp eax, ebx
3584: ja mr_finish
3585:
3586: mov [z80_Read+edx*8], dword 0
3587: mov [z80_Read+edx*8+4], ecx
3588: add eax, 0100h
3589: jmp mr_loop
3590:
3591: mr_finish:
3592: pop ebx
3593: ret
3594:
3595: ; void z80_map_write(UWORD start, UWORD end, UBYTE *memory)
3596: ; Moves a Z80_MAP_MAPPED area to use a different region of memory
3597: ; start/end = the area it covers (must be page-aligned)
3598: ; memory = the ROM/RAM to read from
3599: cglobal z80_map_write
3600: z80_map_write:
3601: push ebx
3602: mov eax, [esp+8]
3603: mov ebx, [esp+12]
3604: mov ecx, [esp+16]
3605: and eax, 0ffffh
3606: and ebx, 0ffffh
3607: sub ecx, eax
3608:
3609: mw_loop:
3610: ; if there's no area left inbetween, stop now.
3611: mov edx, eax
3612: shr edx, 8
3613:
3614: cmp eax, ebx
3615: ja mw_finish
3616:
3617: mov [z80_Write+edx*8], dword 0
3618: mov [z80_Write+edx*8+4], ecx
3619: add eax, 0100h
3620: jmp mw_loop
3621:
3622: mw_finish:
3623: pop ebx
3624: ret
3625:
3626: ; void z80_add_read(UWORD start, UWORD end, int method, void *data)
3627: ; Add a READ memory handler to the memory map
3628: ; start/end = the area it covers
3629: ; method = 0 for direct, 1 for handled
3630: ; data = RAM for direct, handler for handled
3631: cglobal z80_add_read
3632: z80_add_read:
3633: push ebx
3634: mov eax, [esp+8]
3635: mov ebx, [esp+12]
3636: mov ecx, [esp+20]
3637: and eax, 0ffffh
3638: and ebx, 0ffffh
3639:
3640: ; put the entry in the read table first
3641: mov edx, _read_handlers
3642: ar_find:
3643: add edx, 16
3644: cmp [edx-16], dword (-1)
3645: jne ar_find
3646: sub edx, 16
3647:
3648: ; put it in there
3649: mov [edx], eax
3650: mov [edx+4], ebx
3651: mov eax, [esp+16]
3652: mov [edx+8], eax
3653:
3654: mov eax, ecx ; if direct, subtract the start from the memory area
3655: push ebx
3656: mov ebx, [esp+12]
3657: and ebx, 0ffffh
3658: cmp [esp+20], dword 1
3659: je ar_dont_adjust
3660: sub eax, ebx
3661: ar_dont_adjust:
3662: mov [edx+12], eax
3663:
3664: mov eax, ebx
3665: pop ebx
3666:
3667: ; process the start, so it's page aligned
3668: test al, al
3669: jz ar_start_done
3670:
3671: ; put the start handler to go to the dispatcher
3672: mov edx, eax
3673: shr edx, 8
3674: mov [z80_Read+edx*8], dword read_dispatcher
3675: xor al, al
3676: add eax, 0100h
3677:
3678: ar_start_done:
3679: ; process the end, so it's page aligned
3680: cmp bl, 0ffh
3681: je ar_end_done
3682:
3683: ; put the end handler to go to the dispatcher
3684: mov edx, ebx
3685: shr edx, 8
3686: mov [z80_Read+edx*8], dword read_dispatcher
3687: mov bl, 0ffh
3688: sub ebx, 0100h
3689:
3690: ar_end_done:
3691:
3692: sub ecx, eax
3693: ar_loop:
3694: ; if there's no area left inbetween, stop now.
3695: mov edx, eax
3696: shr edx, 8
3697:
3698: cmp eax, ebx
3699: jg ar_finish
3700:
3701: cmp [esp+16], dword 0
3702: je ar_put_direct
3703:
3704: push ecx
3705: mov ecx, [esp+24]
3706: mov [z80_Read+edx*8], ecx
3707: pop ecx
3708: add eax, 0100h
3709: jmp ar_loop
3710:
3711: ar_put_direct:
3712: mov [z80_Read+edx*8], dword 0
3713: mov [z80_Read+edx*8+4], ecx
3714: add eax, 0100h
3715: jmp ar_loop
3716:
3717: ar_finish:
3718: pop ebx
3719: ret
3720:
3721: ; void z80_add_write(UWORD start, UWORD end, int method, void *data)
3722: ; Add a WRITE memory handler to the memory map
3723: ; start/end = the area it covers
3724: ; method = 0 for direct, 1 for handled
3725: ; data = RAM for direct, handler for handled
3726: cglobal z80_add_write
3727: z80_add_write:
3728: push ebx
3729: mov eax, [esp+8]
3730: mov ebx, [esp+12]
3731: mov ecx, [esp+20]
3732: and eax, 0ffffh
3733: and ebx, 0ffffh
3734:
3735: ; put the entry in the read table first
3736: mov edx, _write_handlers
3737: aw_find:
3738: add edx, 16
3739: cmp [edx-16], dword (-1)
3740: jne aw_find
3741: sub edx, 16
3742:
3743: ; put it in there
3744: mov [edx], eax
3745: mov [edx+4], ebx
3746: mov eax, [esp+16]
3747: mov [edx+8], eax
3748:
3749: mov eax, ecx ; if direct, subtract the start from the memory area
3750: push ebx
3751: mov ebx, [esp+12]
3752: and ebx, 0ffffh
3753: cmp [esp+20], dword 1
3754: je aw_dont_adjust
3755: sub eax, ebx
3756: aw_dont_adjust:
3757: mov [edx+12], eax
3758:
3759: mov eax, ebx
3760: pop ebx
3761:
3762: ; process the start, so it's page aligned
3763: test al, al
3764: jz aw_start_done
3765:
3766: ; put the start handler to go to the dispatcher
3767: mov edx, eax
3768: shr edx, 8
3769: mov [z80_Write+edx*8], dword write_dispatcher
3770: xor al, al
3771: add eax, 0100h
3772:
3773: aw_start_done:
3774: ; process the end, so it's page aligned
3775: cmp bl, 0ffh
3776: je aw_end_done
3777:
3778: ; put the end handler to go to the dispatcher
3779: mov edx, ebx
3780: shr edx, 8
3781: mov [z80_Write+edx*8], dword write_dispatcher
3782: mov bl, 0ffh
3783: sub ebx, 0100h
3784:
3785: aw_end_done:
3786:
3787: sub ecx, eax
3788: aw_loop:
3789: ; if there's no area left inbetween, stop now.
3790: mov edx, eax
3791: shr edx, 8
3792:
3793: cmp eax, ebx
3794: jg aw_finish
3795:
3796: cmp [esp+16], dword 0
3797: je aw_put_direct
3798:
3799: push ecx
3800: mov ecx, [esp+24]
3801: mov [z80_Write+edx*8], ecx
3802: pop ecx
3803: add eax, 0100h
3804: jmp aw_loop
3805:
3806: aw_put_direct:
3807: mov [z80_Write+edx*8], dword 0
3808: mov [z80_Write+edx*8+4], ecx
3809: add eax, 0100h
3810: jmp aw_loop
3811:
3812: aw_finish:
3813: pop ebx
3814: ret
3815:
3816: ; void z80_set_in(UBYTE (*handler)(UWORD port))
3817: ; Set the IN port handler to the given function
3818: cglobal z80_set_in
3819: z80_set_in:
3820: mov eax, [esp+4]
3821: mov [z80_In], eax
3822: ret
3823:
3824: ; void z80_set_out(void (*handler)(UWORD port, UBYTE value))
3825: ; Set the OUT port handler to the given function
3826: cglobal z80_set_out
3827: z80_set_out:
3828: mov eax, [esp+4]
3829: mov [z80_Out], eax
3830: ret
3831:
3832: ; void z80_set_reti(void (*handler)(void))
3833: ; Set the RETI handler to the given function
3834: cglobal z80_set_reti
3835: z80_set_reti:
3836: mov eax, [esp+4]
3837: mov [z80_RetI], eax
3838: ret
3839:
3840: ; void z80_set_fetch_callback(void (*handler)(UWORD pc))
3841: ; Set the fetch callback to the given function
3842: cglobal z80_set_fetch_callback
3843: z80_set_fetch_callback:
3844: mov eax, [esp+4]
3845: mov [z80_Fetch_Callback], eax
3846: ret
3847:
3848: ;----------------------------------------------------------------------------;
3849: ; the jump tables
3850: OpTable:
3851: dd op_00, op_01, op_02, op_03, op_04, op_05, op_06, op_07
3852: dd op_08, op_09, op_0a, op_0b, op_0c, op_0d, op_0e, op_0f
3853: dd op_10, op_11, op_12, op_13, op_14, op_15, op_16, op_17
3854: dd op_18, op_19, op_1a, op_1b, op_1c, op_1d, op_1e, op_1f
3855: dd op_20, op_21, op_22, op_23, op_24, op_25, op_26, op_27
3856: dd op_28, op_29, op_2a, op_2b, op_2c, op_2d, op_2e, op_2f
3857: dd op_30, op_31, op_32, op_33, op_34, op_35, op_36, op_37
3858: dd op_38, op_39, op_3a, op_3b, op_3c, op_3d, op_3e, op_3f
3859: dd op_40, op_41, op_42, op_43, op_44, op_45, op_46, op_47
3860: dd op_48, op_49, op_4a, op_4b, op_4c, op_4d, op_4e, op_4f
3861: dd op_50, op_51, op_52, op_53, op_54, op_55, op_56, op_57
3862: dd op_58, op_59, op_5a, op_5b, op_5c, op_5d, op_5e, op_5f
3863: dd op_60, op_61, op_62, op_63, op_64, op_65, op_66, op_67
3864: dd op_68, op_69, op_6a, op_6b, op_6c, op_6d, op_6e, op_6f
3865: dd op_70, op_71, op_72, op_73, op_74, op_75, op_76, op_77
3866: dd op_78, op_79, op_7a, op_7b, op_7c, op_7d, op_7e, op_7f
3867: dd op_80, op_81, op_82, op_83, op_84, op_85, op_86, op_87
3868: dd op_88, op_89, op_8a, op_8b, op_8c, op_8d, op_8e, op_8f
3869: dd op_90, op_91, op_92, op_93, op_94, op_95, op_96, op_97
3870: dd op_98, op_99, op_9a, op_9b, op_9c, op_9d, op_9e, op_9f
3871: dd op_a0, op_a1, op_a2, op_a3, op_a4, op_a5, op_a6, op_a7
3872: dd op_a8, op_a9, op_aa, op_ab, op_ac, op_ad, op_ae, op_af
3873: dd op_b0, op_b1, op_b2, op_b3, op_b4, op_b5, op_b6, op_b7
3874: dd op_b8, op_b9, op_ba, op_bb, op_bc, op_bd, op_be, op_bf
3875: dd op_c0, op_c1, op_c2, op_c3, op_c4, op_c5, op_c6, op_c7
3876: dd op_c8, op_c9, op_ca, op_cb, op_cc, op_cd, op_ce, op_cf
3877: dd op_d0, op_d1, op_d2, op_d3, op_d4, op_d5, op_d6, op_d7
3878: dd op_d8, op_d9, op_da, op_db, op_dc, op_dd, op_de, op_df
3879: dd op_e0, op_e1, op_e2, op_e3, op_e4, op_e5, op_e6, op_e7
3880: dd op_e8, op_e9, op_ea, op_eb, op_ec, op_ed, op_ee, op_ef
3881: dd op_f0, op_f1, op_f2, op_f3, op_f4, op_f5, op_f6, op_f7
3882: dd op_f8, op_f9, op_fa, op_fb, op_fc, op_fd, op_fe, op_ff
3883:
3884: CBTable:
3885: dd cb_00, cb_01, cb_02, cb_03, cb_04, cb_05, cb_06, cb_07
3886: dd cb_08, cb_09, cb_0a, cb_0b, cb_0c, cb_0d, cb_0e, cb_0f
3887: dd cb_10, cb_11, cb_12, cb_13, cb_14, cb_15, cb_16, cb_17
3888: dd cb_18, cb_19, cb_1a, cb_1b, cb_1c, cb_1d, cb_1e, cb_1f
3889: dd cb_20, cb_21, cb_22, cb_23, cb_24, cb_25, cb_26, cb_27
3890: dd cb_28, cb_29, cb_2a, cb_2b, cb_2c, cb_2d, cb_2e, cb_2f
3891: dd cb_30, cb_31, cb_32, cb_33, cb_34, cb_35, cb_36, cb_37
3892: dd cb_38, cb_39, cb_3a, cb_3b, cb_3c, cb_3d, cb_3e, cb_3f
3893: dd cb_40, cb_41, cb_42, cb_43, cb_44, cb_45, cb_46, cb_47
3894: dd cb_48, cb_49, cb_4a, cb_4b, cb_4c, cb_4d, cb_4e, cb_4f
3895: dd cb_50, cb_51, cb_52, cb_53, cb_54, cb_55, cb_56, cb_57
3896: dd cb_58, cb_59, cb_5a, cb_5b, cb_5c, cb_5d, cb_5e, cb_5f
3897: dd cb_60, cb_61, cb_62, cb_63, cb_64, cb_65, cb_66, cb_67
3898: dd cb_68, cb_69, cb_6a, cb_6b, cb_6c, cb_6d, cb_6e, cb_6f
3899: dd cb_70, cb_71, cb_72, cb_73, cb_74, cb_75, cb_76, cb_77
3900: dd cb_78, cb_79, cb_7a, cb_7b, cb_7c, cb_7d, cb_7e, cb_7f
3901: dd cb_80, cb_81, cb_82, cb_83, cb_84, cb_85, cb_86, cb_87
3902: dd cb_88, cb_89, cb_8a, cb_8b, cb_8c, cb_8d, cb_8e, cb_8f
3903: dd cb_90, cb_91, cb_92, cb_93, cb_94, cb_95, cb_96, cb_97
3904: dd cb_98, cb_99, cb_9a, cb_9b, cb_9c, cb_9d, cb_9e, cb_9f
3905: dd cb_a0, cb_a1, cb_a2, cb_a3, cb_a4, cb_a5, cb_a6, cb_a7
3906: dd cb_a8, cb_a9, cb_aa, cb_ab, cb_ac, cb_ad, cb_ae, cb_af
3907: dd cb_b0, cb_b1, cb_b2, cb_b3, cb_b4, cb_b5, cb_b6, cb_b7
3908: dd cb_b8, cb_b9, cb_ba, cb_bb, cb_bc, cb_bd, cb_be, cb_bf
3909: dd cb_c0, cb_c1, cb_c2, cb_c3, cb_c4, cb_c5, cb_c6, cb_c7
3910: dd cb_c8, cb_c9, cb_ca, cb_cb, cb_cc, cb_cd, cb_ce, cb_cf
3911: dd cb_d0, cb_d1, cb_d2, cb_d3, cb_d4, cb_d5, cb_d6, cb_d7
3912: dd cb_d8, cb_d9, cb_da, cb_db, cb_dc, cb_dd, cb_de, cb_df
3913: dd cb_e0, cb_e1, cb_e2, cb_e3, cb_e4, cb_e5, cb_e6, cb_e7
3914: dd cb_e8, cb_e9, cb_ea, cb_eb, cb_ec, cb_ed, cb_ee, cb_ef
3915: dd cb_f0, cb_f1, cb_f2, cb_f3, cb_f4, cb_f5, cb_f6, cb_f7
3916: dd cb_f8, cb_f9, cb_fa, cb_fb, cb_fc, cb_fd, cb_fe, cb_ff
3917:
3918: EDTable:
3919: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3920: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3921: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3922: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3923: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3924: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3925: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3926: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3927: dd ed_40, ed_41, ed_42, ed_43, ed_44, ed_45, ed_46, ed_47
3928: dd ed_48, ed_49, ed_4a, ed_4b, ed_4c, ed_4d, ed_4e, ed_4f
3929: dd ed_50, ed_51, ed_52, ed_53, ed_54, ed_55, ed_56, ed_57
3930: dd ed_58, ed_59, ed_5a, ed_5b, ed_5c, ed_5d, ed_5e, ed_5f
3931: dd ed_60, ed_61, ed_62, ed_63, ed_64, ed_65, ed_66, ed_67
3932: dd ed_68, ed_69, ed_6a, ed_6b, ed_6c, ed_6d, ed_6e, ed_6f
3933: dd ed_70, ed_71, ed_72, ed_73, ed_74, ed_75, ed_76, ed_xx
3934: dd ed_78, ed_79, ed_7a, ed_7b, ed_7c, ed_7d, ed_7e, ed_xx
3935: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3936: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3937: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3938: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3939: dd ed_a0, ed_a1, ed_a2, ed_a3, ed_xx, ed_xx, ed_xx, ed_xx
3940: dd ed_a8, ed_a9, ed_aa, ed_ab, ed_xx, ed_xx, ed_xx, ed_xx
3941: dd ed_b0, ed_b1, ed_b2, ed_b3, ed_xx, ed_xx, ed_xx, ed_xx
3942: dd ed_b8, ed_b9, ed_ba, ed_bb, ed_xx, ed_xx, ed_xx, ed_xx
3943: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3944: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3945: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3946: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3947: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3948: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3949: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3950: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3951:
3952: DDTable:
3953: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3954: dd dd_xx, dd_09, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3955: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3956: dd dd_xx, dd_19, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3957: dd dd_xx, dd_21, dd_22, dd_23, dd_24, dd_25, dd_26, dd_xx
3958: dd dd_xx, dd_29, dd_2a, dd_2b, dd_2c, dd_2d, dd_2e, dd_xx
3959: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_34, dd_35, dd_36, dd_xx
3960: dd dd_xx, dd_39, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3961: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_44, dd_45, dd_46, dd_xx
3962: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_4c, dd_4d, dd_4e, dd_xx
3963: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_54, dd_55, dd_56, dd_xx
3964: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_5c, dd_5d, dd_5e, dd_xx
3965: dd dd_60, dd_61, dd_62, dd_63, dd_xx, dd_65, dd_66, dd_67
3966: dd dd_68, dd_69, dd_6a, dd_6b, dd_6c, dd_xx, dd_6e, dd_6f
3967: dd dd_70, dd_71, dd_72, dd_73, dd_74, dd_75, dd_xx, dd_77
3968: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_7c, dd_7d, dd_7e, dd_xx
3969: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_84, dd_85, dd_86, dd_xx
3970: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_8c, dd_8d, dd_8e, dd_xx
3971: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_94, dd_95, dd_96, dd_xx
3972: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_9c, dd_9d, dd_9e, dd_xx
3973: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_a4, dd_a5, dd_a6, dd_xx
3974: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_ac, dd_ad, dd_ae, dd_xx
3975: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_b4, dd_b5, dd_b6, dd_xx
3976: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_bc, dd_bd, dd_be, dd_xx
3977: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3978: dd dd_xx, dd_xx, dd_xx, dd_cb, dd_xx, dd_xx, dd_xx, dd_xx
3979: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3980: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3981: dd dd_xx, dd_e1, dd_xx, dd_e3, dd_xx, dd_e5, dd_xx, dd_xx
3982: dd dd_xx, dd_e9, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3983: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3984: dd dd_xx, dd_f9, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3985:
3986: FDTable:
3987: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3988: dd fd_xx, fd_09, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3989: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3990: dd fd_xx, fd_19, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3991: dd fd_xx, fd_21, fd_22, fd_23, fd_24, fd_25, fd_26, fd_xx
3992: dd fd_xx, fd_29, fd_2a, fd_2b, fd_2c, fd_2d, fd_2e, fd_xx
3993: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_34, fd_35, fd_36, fd_xx
3994: dd fd_xx, fd_39, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3995: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_44, fd_45, fd_46, fd_xx
3996: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_4c, fd_4d, fd_4e, fd_xx
3997: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_54, fd_55, fd_56, fd_xx
3998: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_5c, fd_5d, fd_5e, fd_xx
3999: dd fd_60, fd_61, fd_62, fd_63, fd_xx, fd_65, fd_66, fd_67
4000: dd fd_68, fd_69, fd_6a, fd_6b, fd_6c, fd_xx, fd_6e, fd_6f
4001: dd fd_70, fd_71, fd_72, fd_73, fd_74, fd_75, fd_xx, fd_77
4002: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_7c, fd_7d, fd_7e, fd_xx
4003: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_84, fd_85, fd_86, fd_xx
4004: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_8c, fd_8d, fd_8e, fd_xx
4005: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_94, fd_95, fd_96, fd_xx
4006: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_9c, fd_9d, fd_9e, fd_xx
4007: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_a4, fd_a5, fd_a6, fd_xx
4008: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_ac, fd_ad, fd_ae, fd_xx
4009: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_b4, fd_b5, fd_b6, fd_xx
4010: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_bc, fd_bd, fd_be, fd_xx
4011: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4012: dd fd_xx, fd_xx, fd_xx, fd_cb, fd_xx, fd_xx, fd_xx, fd_xx
4013: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4014: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4015: dd fd_xx, fd_e1, fd_xx, fd_e3, fd_xx, fd_e5, fd_xx, fd_xx
4016: dd fd_xx, fd_e9, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4017: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4018: dd fd_xx, fd_f9, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4019:
4020: DDCBTable:
4021: dd ddcb_00, ddcb_01, ddcb_02, ddcb_03, ddcb_04, ddcb_05, ddcb_06, ddcb_07
4022: dd ddcb_08, ddcb_09, ddcb_0a, ddcb_0b, ddcb_0c, ddcb_0d, ddcb_0e, ddcb_0f
4023: dd ddcb_10, ddcb_11, ddcb_12, ddcb_13, ddcb_14, ddcb_15, ddcb_16, ddcb_17
4024: dd ddcb_18, ddcb_19, ddcb_1a, ddcb_1b, ddcb_1c, ddcb_1d, ddcb_1e, ddcb_1f
4025: dd ddcb_20, ddcb_21, ddcb_22, ddcb_23, ddcb_24, ddcb_25, ddcb_26, ddcb_27
4026: dd ddcb_28, ddcb_29, ddcb_2a, ddcb_2b, ddcb_2c, ddcb_2d, ddcb_2e, ddcb_2f
4027: dd ddcb_30, ddcb_31, ddcb_32, ddcb_33, ddcb_34, ddcb_35, ddcb_36, ddcb_37
4028: dd ddcb_38, ddcb_39, ddcb_3a, ddcb_3b, ddcb_3c, ddcb_3d, ddcb_3e, ddcb_3f
4029: dd ddcb_40, ddcb_41, ddcb_42, ddcb_43, ddcb_44, ddcb_45, ddcb_46, ddcb_47
4030: dd ddcb_48, ddcb_49, ddcb_4a, ddcb_4b, ddcb_4c, ddcb_4d, ddcb_4e, ddcb_4f
4031: dd ddcb_50, ddcb_51, ddcb_52, ddcb_53, ddcb_54, ddcb_55, ddcb_56, ddcb_57
4032: dd ddcb_58, ddcb_59, ddcb_5a, ddcb_5b, ddcb_5c, ddcb_5d, ddcb_5e, ddcb_5f
4033: dd ddcb_60, ddcb_61, ddcb_62, ddcb_63, ddcb_64, ddcb_65, ddcb_66, ddcb_67
4034: dd ddcb_68, ddcb_69, ddcb_6a, ddcb_6b, ddcb_6c, ddcb_6d, ddcb_6e, ddcb_6f
4035: dd ddcb_70, ddcb_71, ddcb_72, ddcb_73, ddcb_74, ddcb_75, ddcb_76, ddcb_77
4036: dd ddcb_78, ddcb_79, ddcb_7a, ddcb_7b, ddcb_7c, ddcb_7d, ddcb_7e, ddcb_7f
4037: dd ddcb_80, ddcb_81, ddcb_82, ddcb_83, ddcb_84, ddcb_85, ddcb_86, ddcb_87
4038: dd ddcb_88, ddcb_89, ddcb_8a, ddcb_8b, ddcb_8c, ddcb_8d, ddcb_8e, ddcb_8f
4039: dd ddcb_90, ddcb_91, ddcb_92, ddcb_93, ddcb_94, ddcb_95, ddcb_96, ddcb_97
4040: dd ddcb_98, ddcb_99, ddcb_9a, ddcb_9b, ddcb_9c, ddcb_9d, ddcb_9e, ddcb_9f
4041: dd ddcb_a0, ddcb_a1, ddcb_a2, ddcb_a3, ddcb_a4, ddcb_a5, ddcb_a6, ddcb_a7
4042: dd ddcb_a8, ddcb_a9, ddcb_aa, ddcb_ab, ddcb_ac, ddcb_ad, ddcb_ae, ddcb_af
4043: dd ddcb_b0, ddcb_b1, ddcb_b2, ddcb_b3, ddcb_b4, ddcb_b5, ddcb_b6, ddcb_b7
4044: dd ddcb_b8, ddcb_b9, ddcb_ba, ddcb_bb, ddcb_bc, ddcb_bd, ddcb_be, ddcb_bf
4045: dd ddcb_c0, ddcb_c1, ddcb_c2, ddcb_c3, ddcb_c4, ddcb_c5, ddcb_c6, ddcb_c7
4046: dd ddcb_c8, ddcb_c9, ddcb_ca, ddcb_cb, ddcb_cc, ddcb_cd, ddcb_ce, ddcb_cf
4047: dd ddcb_d0, ddcb_d1, ddcb_d2, ddcb_d3, ddcb_d4, ddcb_d5, ddcb_d6, ddcb_d7
4048: dd ddcb_d8, ddcb_d9, ddcb_da, ddcb_db, ddcb_dc, ddcb_dd, ddcb_de, ddcb_df
4049: dd ddcb_e0, ddcb_e1, ddcb_e2, ddcb_e3, ddcb_e4, ddcb_e5, ddcb_e6, ddcb_e7
4050: dd ddcb_e8, ddcb_e9, ddcb_ea, ddcb_eb, ddcb_ec, ddcb_ed, ddcb_ee, ddcb_ef
4051: dd ddcb_f0, ddcb_f1, ddcb_f2, ddcb_f3, ddcb_f4, ddcb_f5, ddcb_f6, ddcb_f7
4052: dd ddcb_f8, ddcb_f9, ddcb_fa, ddcb_fb, ddcb_fc, ddcb_fd, ddcb_fe, ddcb_ff
4053:
4054:
4055: ;----------------------------------------------------------------------------;
4056: ; flag tables ('borrowed' from MAZE, by Ishmair)
4057: INC_Table:
4058: DB 0,0,0,0,0,0,0,8,8,8,8,8,8,8,8,16,0,0,0,0
4059: DB 0,0,0,8,8,8,8,8,8,8,8,48,32,32,32,32,32,32,32,40
4060: DB 40,40,40,40,40,40,40,48,32,32,32,32,32,32,32,40,40,40,40,40
4061: DB 40,40,40,16,0,0,0,0,0,0,0,8,8,8,8,8,8,8,8,16
4062: DB 0,0,0,0,0,0,0,8,8,8,8,8,8,8,8,48,32,32,32,32
4063: DB 32,32,32,40,40,40,40,40,40,40,40,48,32,32,32,32,32,32,32,40
4064: DB 40,40,40,40,40,40,40,148,128,128,128,128,128,128,128,136,136,136,136,136
4065: DB 136,136,136,144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,176
4066: DB 160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,176,160,160,160,160
4067: DB 160,160,160,168,168,168,168,168,168,168,168,144,128,128,128,128,128,128,128,136
4068: DB 136,136,136,136,136,136,136,144,128,128,128,128,128,128,128,136,136,136,136,136
4069: DB 136,136,136,176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,176
4070: DB 160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,80
4071:
4072: DEC_Table:
4073: DB 186,66,2,2,2,2,2,2,2,10,10,10,10,10,10,10,26,2,2,2
4074: DB 2,2,2,2,2,10,10,10,10,10,10,10,26,34,34,34,34,34,34,34
4075: DB 34,42,42,42,42,42,42,42,58,34,34,34,34,34,34,34,34,42,42,42
4076: DB 42,42,42,42,58,2,2,2,2,2,2,2,2,10,10,10,10,10,10,10
4077: DB 26,2,2,2,2,2,2,2,2,10,10,10,10,10,10,10,26,34,34,34
4078: DB 34,34,34,34,34,42,42,42,42,42,42,42,58,34,34,34,34,34,34,34
4079: DB 34,42,42,42,42,42,42,42,62,130,130,130,130,130,130,130,130,138,138,138
4080: DB 138,138,138,138,154,130,130,130,130,130,130,130,130,138,138,138,138,138,138,138
4081: DB 154,162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,162,162,162
4082: DB 162,162,162,162,162,170,170,170,170,170,170,170,186,130,130,130,130,130,130,130
4083: DB 130,138,138,138,138,138,138,138,154,130,130,130,130,130,130,130,130,138,138,138
4084: DB 138,138,138,138,154,162,162,162,162,162,162,162,162,170,170,170,170,170,170,170
4085: DB 186,162,162,162,162,162,162,162,162,170,170,170,170,170,170,170
4086:
4087: ; DAA table ('borrowed' from Z80Emul, by unknown)
4088: DAA_Table:
4089: DW 04400h, 00001h, 00002h, 00403h, 00004h, 00405h, 00406h, 00007h
4090: DW 00808h, 00C09h, 01010h, 01411h, 01412h, 01013h, 01414h, 01015h
4091: DW 00010h, 00411h, 00412h, 00013h, 00414h, 00015h, 00016h, 00417h
4092: DW 00C18h, 00819h, 03020h, 03421h, 03422h, 03023h, 03424h, 03025h
4093: DW 02020h, 02421h, 02422h, 02023h, 02424h, 02025h, 02026h, 02427h
4094: DW 02C28h, 02829h, 03430h, 03031h, 03032h, 03433h, 03034h, 03435h
4095: DW 02430h, 02031h, 02032h, 02433h, 02034h, 02435h, 02436h, 02037h
4096: DW 02838h, 02C39h, 01040h, 01441h, 01442h, 01043h, 01444h, 01045h
4097: DW 00040h, 00441h, 00442h, 00043h, 00444h, 00045h, 00046h, 00447h
4098: DW 00C48h, 00849h, 01450h, 01051h, 01052h, 01453h, 01054h, 01455h
4099: DW 00450h, 00051h, 00052h, 00453h, 00054h, 00455h, 00456h, 00057h
4100: DW 00858h, 00C59h, 03460h, 03061h, 03062h, 03463h, 03064h, 03465h
4101: DW 02460h, 02061h, 02062h, 02463h, 02064h, 02465h, 02466h, 02067h
4102: DW 02868h, 02C69h, 03070h, 03471h, 03472h, 03073h, 03474h, 03075h
4103: DW 02070h, 02471h, 02472h, 02073h, 02474h, 02075h, 02076h, 02477h
4104: DW 02C78h, 02879h, 09080h, 09481h, 09482h, 09083h, 09484h, 09085h
4105: DW 08080h, 08481h, 08482h, 08083h, 08484h, 08085h, 08086h, 08487h
4106: DW 08C88h, 08889h, 09490h, 09091h, 09092h, 09493h, 09094h, 09495h
4107: DW 08490h, 08091h, 08092h, 08493h, 08094h, 08495h, 08496h, 08097h
4108: DW 08898h, 08C99h, 05500h, 01101h, 01102h, 01503h, 01104h, 01505h
4109: DW 04500h, 00101h, 00102h, 00503h, 00104h, 00505h, 00506h, 00107h
4110: DW 00908h, 00D09h, 01110h, 01511h, 01512h, 01113h, 01514h, 01115h
4111: DW 00110h, 00511h, 00512h, 00113h, 00514h, 00115h, 00116h, 00517h
4112: DW 00D18h, 00919h, 03120h, 03521h, 03522h, 03123h, 03524h, 03125h
4113: DW 02120h, 02521h, 02522h, 02123h, 02524h, 02125h, 02126h, 02527h
4114: DW 02D28h, 02929h, 03530h, 03131h, 03132h, 03533h, 03134h, 03535h
4115: DW 02530h, 02131h, 02132h, 02533h, 02134h, 02535h, 02536h, 02137h
4116: DW 02938h, 02D39h, 01140h, 01541h, 01542h, 01143h, 01544h, 01145h
4117: DW 00140h, 00541h, 00542h, 00143h, 00544h, 00145h, 00146h, 00547h
4118: DW 00D48h, 00949h, 01550h, 01151h, 01152h, 01553h, 01154h, 01555h
4119: DW 00550h, 00151h, 00152h, 00553h, 00154h, 00555h, 00556h, 00157h
4120: DW 00958h, 00D59h, 03560h, 03161h, 03162h, 03563h, 03164h, 03565h
4121: DW 02560h, 02161h, 02162h, 02563h, 02164h, 02565h, 02566h, 02167h
4122: DW 02968h, 02D69h, 03170h, 03571h, 03572h, 03173h, 03574h, 03175h
4123: DW 02170h, 02571h, 02572h, 02173h, 02574h, 02175h, 02176h, 02577h
4124: DW 02D78h, 02979h, 09180h, 09581h, 09582h, 09183h, 09584h, 09185h
4125: DW 08180h, 08581h, 08582h, 08183h, 08584h, 08185h, 08186h, 08587h
4126: DW 08D88h, 08989h, 09590h, 09191h, 09192h, 09593h, 09194h, 09595h
4127: DW 08590h, 08191h, 08192h, 08593h, 08194h, 08595h, 08596h, 08197h
4128: DW 08998h, 08D99h, 0B5A0h, 0B1A1h, 0B1A2h, 0B5A3h, 0B1A4h, 0B5A5h
4129: DW 0A5A0h, 0A1A1h, 0A1A2h, 0A5A3h, 0A1A4h, 0A5A5h, 0A5A6h, 0A1A7h
4130: DW 0A9A8h, 0ADA9h, 0B1B0h, 0B5B1h, 0B5B2h, 0B1B3h, 0B5B4h, 0B1B5h
4131: DW 0A1B0h, 0A5B1h, 0A5B2h, 0A1B3h, 0A5B4h, 0A1B5h, 0A1B6h, 0A5B7h
4132: DW 0ADB8h, 0A9B9h, 095C0h, 091C1h, 091C2h, 095C3h, 091C4h, 095C5h
4133: DW 085C0h, 081C1h, 081C2h, 085C3h, 081C4h, 085C5h, 085C6h, 081C7h
4134: DW 089C8h, 08DC9h, 091D0h, 095D1h, 095D2h, 091D3h, 095D4h, 091D5h
4135: DW 081D0h, 085D1h, 085D2h, 081D3h, 085D4h, 081D5h, 081D6h, 085D7h
4136: DW 08DD8h, 089D9h, 0B1E0h, 0B5E1h, 0B5E2h, 0B1E3h, 0B5E4h, 0B1E5h
4137: DW 0A1E0h, 0A5E1h, 0A5E2h, 0A1E3h, 0A5E4h, 0A1E5h, 0A1E6h, 0A5E7h
4138: DW 0ADE8h, 0A9E9h, 0B5F0h, 0B1F1h, 0B1F2h, 0B5F3h, 0B1F4h, 0B5F5h
4139: DW 0A5F0h, 0A1F1h, 0A1F2h, 0A5F3h, 0A1F4h, 0A5F5h, 0A5F6h, 0A1F7h
4140: DW 0A9F8h, 0ADF9h, 05500h, 01101h, 01102h, 01503h, 01104h, 01505h
4141: DW 04500h, 00101h, 00102h, 00503h, 00104h, 00505h, 00506h, 00107h
4142: DW 00908h, 00D09h, 01110h, 01511h, 01512h, 01113h, 01514h, 01115h
4143: DW 00110h, 00511h, 00512h, 00113h, 00514h, 00115h, 00116h, 00517h
4144: DW 00D18h, 00919h, 03120h, 03521h, 03522h, 03123h, 03524h, 03125h
4145: DW 02120h, 02521h, 02522h, 02123h, 02524h, 02125h, 02126h, 02527h
4146: DW 02D28h, 02929h, 03530h, 03131h, 03132h, 03533h, 03134h, 03535h
4147: DW 02530h, 02131h, 02132h, 02533h, 02134h, 02535h, 02536h, 02137h
4148: DW 02938h, 02D39h, 01140h, 01541h, 01542h, 01143h, 01544h, 01145h
4149: DW 00140h, 00541h, 00542h, 00143h, 00544h, 00145h, 00146h, 00547h
4150: DW 00D48h, 00949h, 01550h, 01151h, 01152h, 01553h, 01154h, 01555h
4151: DW 00550h, 00151h, 00152h, 00553h, 00154h, 00555h, 00556h, 00157h
4152: DW 00958h, 00D59h, 03560h, 03161h, 03162h, 03563h, 03164h, 03565h
4153: DW 04600h, 00201h, 00202h, 00603h, 00204h, 00605h, 00606h, 00207h
4154: DW 00A08h, 00E09h, 00204h, 00605h, 00606h, 00207h, 00A08h, 00E09h
4155: DW 00210h, 00611h, 00612h, 00213h, 00614h, 00215h, 00216h, 00617h
4156: DW 00E18h, 00A19h, 00614h, 00215h, 00216h, 00617h, 00E18h, 00A19h
4157: DW 02220h, 02621h, 02622h, 02223h, 02624h, 02225h, 02226h, 02627h
4158: DW 02E28h, 02A29h, 02624h, 02225h, 02226h, 02627h, 02E28h, 02A29h
4159: DW 02630h, 02231h, 02232h, 02633h, 02234h, 02635h, 02636h, 02237h
4160: DW 02A38h, 02E39h, 02234h, 02635h, 02636h, 02237h, 02A38h, 02E39h
4161: DW 00240h, 00641h, 00642h, 00243h, 00644h, 00245h, 00246h, 00647h
4162: DW 00E48h, 00A49h, 00644h, 00245h, 00246h, 00647h, 00E48h, 00A49h
4163: DW 00650h, 00251h, 00252h, 00653h, 00254h, 00655h, 00656h, 00257h
4164: DW 00A58h, 00E59h, 00254h, 00655h, 00656h, 00257h, 00A58h, 00E59h
4165: DW 02660h, 02261h, 02262h, 02663h, 02264h, 02665h, 02666h, 02267h
4166: DW 02A68h, 02E69h, 02264h, 02665h, 02666h, 02267h, 02A68h, 02E69h
4167: DW 02270h, 02671h, 02672h, 02273h, 02674h, 02275h, 02276h, 02677h
4168: DW 02E78h, 02A79h, 02674h, 02275h, 02276h, 02677h, 02E78h, 02A79h
4169: DW 08280h, 08681h, 08682h, 08283h, 08684h, 08285h, 08286h, 08687h
4170: DW 08E88h, 08A89h, 08684h, 08285h, 08286h, 08687h, 08E88h, 08A89h
4171: DW 08690h, 08291h, 08292h, 08693h, 08294h, 08695h, 08696h, 08297h
4172: DW 08A98h, 08E99h, 02334h, 02735h, 02736h, 02337h, 02B38h, 02F39h
4173: DW 00340h, 00741h, 00742h, 00343h, 00744h, 00345h, 00346h, 00747h
4174: DW 00F48h, 00B49h, 00744h, 00345h, 00346h, 00747h, 00F48h, 00B49h
4175: DW 00750h, 00351h, 00352h, 00753h, 00354h, 00755h, 00756h, 00357h
4176: DW 00B58h, 00F59h, 00354h, 00755h, 00756h, 00357h, 00B58h, 00F59h
4177: DW 02760h, 02361h, 02362h, 02763h, 02364h, 02765h, 02766h, 02367h
4178: DW 02B68h, 02F69h, 02364h, 02765h, 02766h, 02367h, 02B68h, 02F69h
4179: DW 02370h, 02771h, 02772h, 02373h, 02774h, 02375h, 02376h, 02777h
4180: DW 02F78h, 02B79h, 02774h, 02375h, 02376h, 02777h, 02F78h, 02B79h
4181: DW 08380h, 08781h, 08782h, 08383h, 08784h, 08385h, 08386h, 08787h
4182: DW 08F88h, 08B89h, 08784h, 08385h, 08386h, 08787h, 08F88h, 08B89h
4183: DW 08790h, 08391h, 08392h, 08793h, 08394h, 08795h, 08796h, 08397h
4184: DW 08B98h, 08F99h, 08394h, 08795h, 08796h, 08397h, 08B98h, 08F99h
4185: DW 0A7A0h, 0A3A1h, 0A3A2h, 0A7A3h, 0A3A4h, 0A7A5h, 0A7A6h, 0A3A7h
4186: DW 0ABA8h, 0AFA9h, 0A3A4h, 0A7A5h, 0A7A6h, 0A3A7h, 0ABA8h, 0AFA9h
4187: DW 0A3B0h, 0A7B1h, 0A7B2h, 0A3B3h, 0A7B4h, 0A3B5h, 0A3B6h, 0A7B7h
4188: DW 0AFB8h, 0ABB9h, 0A7B4h, 0A3B5h, 0A3B6h, 0A7B7h, 0AFB8h, 0ABB9h
4189: DW 087C0h, 083C1h, 083C2h, 087C3h, 083C4h, 087C5h, 087C6h, 083C7h
4190: DW 08BC8h, 08FC9h, 083C4h, 087C5h, 087C6h, 083C7h, 08BC8h, 08FC9h
4191: DW 083D0h, 087D1h, 087D2h, 083D3h, 087D4h, 083D5h, 083D6h, 087D7h
4192: DW 08FD8h, 08BD9h, 087D4h, 083D5h, 083D6h, 087D7h, 08FD8h, 08BD9h
4193: DW 0A3E0h, 0A7E1h, 0A7E2h, 0A3E3h, 0A7E4h, 0A3E5h, 0A3E6h, 0A7E7h
4194: DW 0AFE8h, 0ABE9h, 0A7E4h, 0A3E5h, 0A3E6h, 0A7E7h, 0AFE8h, 0ABE9h
4195: DW 0A7F0h, 0A3F1h, 0A3F2h, 0A7F3h, 0A3F4h, 0A7F5h, 0A7F6h, 0A3F7h
4196: DW 0ABF8h, 0AFF9h, 0A3F4h, 0A7F5h, 0A7F6h, 0A3F7h, 0ABF8h, 0AFF9h
4197: DW 04700h, 00301h, 00302h, 00703h, 00304h, 00705h, 00706h, 00307h
4198: DW 00B08h, 00F09h, 00304h, 00705h, 00706h, 00307h, 00B08h, 00F09h
4199: DW 00310h, 00711h, 00712h, 00313h, 00714h, 00315h, 00316h, 00717h
4200: DW 00F18h, 00B19h, 00714h, 00315h, 00316h, 00717h, 00F18h, 00B19h
4201: DW 02320h, 02721h, 02722h, 02323h, 02724h, 02325h, 02326h, 02727h
4202: DW 02F28h, 02B29h, 02724h, 02325h, 02326h, 02727h, 02F28h, 02B29h
4203: DW 02730h, 02331h, 02332h, 02733h, 02334h, 02735h, 02736h, 02337h
4204: DW 02B38h, 02F39h, 02334h, 02735h, 02736h, 02337h, 02B38h, 02F39h
4205: DW 00340h, 00741h, 00742h, 00343h, 00744h, 00345h, 00346h, 00747h
4206: DW 00F48h, 00B49h, 00744h, 00345h, 00346h, 00747h, 00F48h, 00B49h
4207: DW 00750h, 00351h, 00352h, 00753h, 00354h, 00755h, 00756h, 00357h
4208: DW 00B58h, 00F59h, 00354h, 00755h, 00756h, 00357h, 00B58h, 00F59h
4209: DW 02760h, 02361h, 02362h, 02763h, 02364h, 02765h, 02766h, 02367h
4210: DW 02B68h, 02F69h, 02364h, 02765h, 02766h, 02367h, 02B68h, 02F69h
4211: DW 02370h, 02771h, 02772h, 02373h, 02774h, 02375h, 02376h, 02777h
4212: DW 02F78h, 02B79h, 02774h, 02375h, 02376h, 02777h, 02F78h, 02B79h
4213: DW 08380h, 08781h, 08782h, 08383h, 08784h, 08385h, 08386h, 08787h
4214: DW 08F88h, 08B89h, 08784h, 08385h, 08386h, 08787h, 08F88h, 08B89h
4215: DW 08790h, 08391h, 08392h, 08793h, 08394h, 08795h, 08796h, 08397h
4216: DW 08B98h, 08F99h, 08394h, 08795h, 08796h, 08397h, 08B98h, 08F99h
4217: DW 00406h, 00007h, 00808h, 00C09h, 00C0Ah, 0080Bh, 00C0Ch, 0080Dh
4218: DW 0080Eh, 00C0Fh, 01010h, 01411h, 01412h, 01013h, 01414h, 01015h
4219: DW 00016h, 00417h, 00C18h, 00819h, 0081Ah, 00C1Bh, 0081Ch, 00C1Dh
4220: DW 00C1Eh, 0081Fh, 03020h, 03421h, 03422h, 03023h, 03424h, 03025h
4221: DW 02026h, 02427h, 02C28h, 02829h, 0282Ah, 02C2Bh, 0282Ch, 02C2Dh
4222: DW 02C2Eh, 0282Fh, 03430h, 03031h, 03032h, 03433h, 03034h, 03435h
4223: DW 02436h, 02037h, 02838h, 02C39h, 02C3Ah, 0283Bh, 02C3Ch, 0283Dh
4224: DW 0283Eh, 02C3Fh, 01040h, 01441h, 01442h, 01043h, 01444h, 01045h
4225: DW 00046h, 00447h, 00C48h, 00849h, 0084Ah, 00C4Bh, 0084Ch, 00C4Dh
4226: DW 00C4Eh, 0084Fh, 01450h, 01051h, 01052h, 01453h, 01054h, 01455h
4227: DW 00456h, 00057h, 00858h, 00C59h, 00C5Ah, 0085Bh, 00C5Ch, 0085Dh
4228: DW 0085Eh, 00C5Fh, 03460h, 03061h, 03062h, 03463h, 03064h, 03465h
4229: DW 02466h, 02067h, 02868h, 02C69h, 02C6Ah, 0286Bh, 02C6Ch, 0286Dh
4230: DW 0286Eh, 02C6Fh, 03070h, 03471h, 03472h, 03073h, 03474h, 03075h
4231: DW 02076h, 02477h, 02C78h, 02879h, 0287Ah, 02C7Bh, 0287Ch, 02C7Dh
4232: DW 02C7Eh, 0287Fh, 09080h, 09481h, 09482h, 09083h, 09484h, 09085h
4233: DW 08086h, 08487h, 08C88h, 08889h, 0888Ah, 08C8Bh, 0888Ch, 08C8Dh
4234: DW 08C8Eh, 0888Fh, 09490h, 09091h, 09092h, 09493h, 09094h, 09495h
4235: DW 08496h, 08097h, 08898h, 08C99h, 08C9Ah, 0889Bh, 08C9Ch, 0889Dh
4236: DW 0889Eh, 08C9Fh, 05500h, 01101h, 01102h, 01503h, 01104h, 01505h
4237: DW 00506h, 00107h, 00908h, 00D09h, 00D0Ah, 0090Bh, 00D0Ch, 0090Dh
4238: DW 0090Eh, 00D0Fh, 01110h, 01511h, 01512h, 01113h, 01514h, 01115h
4239: DW 00116h, 00517h, 00D18h, 00919h, 0091Ah, 00D1Bh, 0091Ch, 00D1Dh
4240: DW 00D1Eh, 0091Fh, 03120h, 03521h, 03522h, 03123h, 03524h, 03125h
4241: DW 02126h, 02527h, 02D28h, 02929h, 0292Ah, 02D2Bh, 0292Ch, 02D2Dh
4242: DW 02D2Eh, 0292Fh, 03530h, 03131h, 03132h, 03533h, 03134h, 03535h
4243: DW 02536h, 02137h, 02938h, 02D39h, 02D3Ah, 0293Bh, 02D3Ch, 0293Dh
4244: DW 0293Eh, 02D3Fh, 01140h, 01541h, 01542h, 01143h, 01544h, 01145h
4245: DW 00146h, 00547h, 00D48h, 00949h, 0094Ah, 00D4Bh, 0094Ch, 00D4Dh
4246: DW 00D4Eh, 0094Fh, 01550h, 01151h, 01152h, 01553h, 01154h, 01555h
4247: DW 00556h, 00157h, 00958h, 00D59h, 00D5Ah, 0095Bh, 00D5Ch, 0095Dh
4248: DW 0095Eh, 00D5Fh, 03560h, 03161h, 03162h, 03563h, 03164h, 03565h
4249: DW 02566h, 02167h, 02968h, 02D69h, 02D6Ah, 0296Bh, 02D6Ch, 0296Dh
4250: DW 0296Eh, 02D6Fh, 03170h, 03571h, 03572h, 03173h, 03574h, 03175h
4251: DW 02176h, 02577h, 02D78h, 02979h, 0297Ah, 02D7Bh, 0297Ch, 02D7Dh
4252: DW 02D7Eh, 0297Fh, 09180h, 09581h, 09582h, 09183h, 09584h, 09185h
4253: DW 08186h, 08587h, 08D88h, 08989h, 0898Ah, 08D8Bh, 0898Ch, 08D8Dh
4254: DW 08D8Eh, 0898Fh, 09590h, 09191h, 09192h, 09593h, 09194h, 09595h
4255: DW 08596h, 08197h, 08998h, 08D99h, 08D9Ah, 0899Bh, 08D9Ch, 0899Dh
4256: DW 0899Eh, 08D9Fh, 0B5A0h, 0B1A1h, 0B1A2h, 0B5A3h, 0B1A4h, 0B5A5h
4257: DW 0A5A6h, 0A1A7h, 0A9A8h, 0ADA9h, 0ADAAh, 0A9ABh, 0ADACh, 0A9ADh
4258: DW 0A9AEh, 0ADAFh, 0B1B0h, 0B5B1h, 0B5B2h, 0B1B3h, 0B5B4h, 0B1B5h
4259: DW 0A1B6h, 0A5B7h, 0ADB8h, 0A9B9h, 0A9BAh, 0ADBBh, 0A9BCh, 0ADBDh
4260: DW 0ADBEh, 0A9BFh, 095C0h, 091C1h, 091C2h, 095C3h, 091C4h, 095C5h
4261: DW 085C6h, 081C7h, 089C8h, 08DC9h, 08DCAh, 089CBh, 08DCCh, 089CDh
4262: DW 089CEh, 08DCFh, 091D0h, 095D1h, 095D2h, 091D3h, 095D4h, 091D5h
4263: DW 081D6h, 085D7h, 08DD8h, 089D9h, 089DAh, 08DDBh, 089DCh, 08DDDh
4264: DW 08DDEh, 089DFh, 0B1E0h, 0B5E1h, 0B5E2h, 0B1E3h, 0B5E4h, 0B1E5h
4265: DW 0A1E6h, 0A5E7h, 0ADE8h, 0A9E9h, 0A9EAh, 0ADEBh, 0A9ECh, 0ADEDh
4266: DW 0ADEEh, 0A9EFh, 0B5F0h, 0B1F1h, 0B1F2h, 0B5F3h, 0B1F4h, 0B5F5h
4267: DW 0A5F6h, 0A1F7h, 0A9F8h, 0ADF9h, 0ADFAh, 0A9FBh, 0ADFCh, 0A9FDh
4268: DW 0A9FEh, 0ADFFh, 05500h, 01101h, 01102h, 01503h, 01104h, 01505h
4269: DW 00506h, 00107h, 00908h, 00D09h, 00D0Ah, 0090Bh, 00D0Ch, 0090Dh
4270: DW 0090Eh, 00D0Fh, 01110h, 01511h, 01512h, 01113h, 01514h, 01115h
4271: DW 00116h, 00517h, 00D18h, 00919h, 0091Ah, 00D1Bh, 0091Ch, 00D1Dh
4272: DW 00D1Eh, 0091Fh, 03120h, 03521h, 03522h, 03123h, 03524h, 03125h
4273: DW 02126h, 02527h, 02D28h, 02929h, 0292Ah, 02D2Bh, 0292Ch, 02D2Dh
4274: DW 02D2Eh, 0292Fh, 03530h, 03131h, 03132h, 03533h, 03134h, 03535h
4275: DW 02536h, 02137h, 02938h, 02D39h, 02D3Ah, 0293Bh, 02D3Ch, 0293Dh
4276: DW 0293Eh, 02D3Fh, 01140h, 01541h, 01542h, 01143h, 01544h, 01145h
4277: DW 00146h, 00547h, 00D48h, 00949h, 0094Ah, 00D4Bh, 0094Ch, 00D4Dh
4278: DW 00D4Eh, 0094Fh, 01550h, 01151h, 01152h, 01553h, 01154h, 01555h
4279: DW 00556h, 00157h, 00958h, 00D59h, 00D5Ah, 0095Bh, 00D5Ch, 0095Dh
4280: DW 0095Eh, 00D5Fh, 03560h, 03161h, 03162h, 03563h, 03164h, 03565h
4281: DW 0BEFAh, 0BAFBh, 0BEFCh, 0BAFDh, 0BAFEh, 0BEFFh, 04600h, 00201h
4282: DW 00202h, 00603h, 00204h, 00605h, 00606h, 00207h, 00A08h, 00E09h
4283: DW 01E0Ah, 01A0Bh, 01E0Ch, 01A0Dh, 01A0Eh, 01E0Fh, 00210h, 00611h
4284: DW 00612h, 00213h, 00614h, 00215h, 00216h, 00617h, 00E18h, 00A19h
4285: DW 01A1Ah, 01E1Bh, 01A1Ch, 01E1Dh, 01E1Eh, 01A1Fh, 02220h, 02621h
4286: DW 02622h, 02223h, 02624h, 02225h, 02226h, 02627h, 02E28h, 02A29h
4287: DW 03A2Ah, 03E2Bh, 03A2Ch, 03E2Dh, 03E2Eh, 03A2Fh, 02630h, 02231h
4288: DW 02232h, 02633h, 02234h, 02635h, 02636h, 02237h, 02A38h, 02E39h
4289: DW 03E3Ah, 03A3Bh, 03E3Ch, 03A3Dh, 03A3Eh, 03E3Fh, 00240h, 00641h
4290: DW 00642h, 00243h, 00644h, 00245h, 00246h, 00647h, 00E48h, 00A49h
4291: DW 01A4Ah, 01E4Bh, 01A4Ch, 01E4Dh, 01E4Eh, 01A4Fh, 00650h, 00251h
4292: DW 00252h, 00653h, 00254h, 00655h, 00656h, 00257h, 00A58h, 00E59h
4293: DW 01E5Ah, 01A5Bh, 01E5Ch, 01A5Dh, 01A5Eh, 01E5Fh, 02660h, 02261h
4294: DW 02262h, 02663h, 02264h, 02665h, 02666h, 02267h, 02A68h, 02E69h
4295: DW 03E6Ah, 03A6Bh, 03E6Ch, 03A6Dh, 03A6Eh, 03E6Fh, 02270h, 02671h
4296: DW 02672h, 02273h, 02674h, 02275h, 02276h, 02677h, 02E78h, 02A79h
4297: DW 03A7Ah, 03E7Bh, 03A7Ch, 03E7Dh, 03E7Eh, 03A7Fh, 08280h, 08681h
4298: DW 08682h, 08283h, 08684h, 08285h, 08286h, 08687h, 08E88h, 08A89h
4299: DW 09A8Ah, 09E8Bh, 09A8Ch, 09E8Dh, 09E8Eh, 09A8Fh, 08690h, 08291h
4300: DW 08292h, 08693h, 02334h, 02735h, 02736h, 02337h, 02B38h, 02F39h
4301: DW 03F3Ah, 03B3Bh, 03F3Ch, 03B3Dh, 03B3Eh, 03F3Fh, 00340h, 00741h
4302: DW 00742h, 00343h, 00744h, 00345h, 00346h, 00747h, 00F48h, 00B49h
4303: DW 01B4Ah, 01F4Bh, 01B4Ch, 01F4Dh, 01F4Eh, 01B4Fh, 00750h, 00351h
4304: DW 00352h, 00753h, 00354h, 00755h, 00756h, 00357h, 00B58h, 00F59h
4305: DW 01F5Ah, 01B5Bh, 01F5Ch, 01B5Dh, 01B5Eh, 01F5Fh, 02760h, 02361h
4306: DW 02362h, 02763h, 02364h, 02765h, 02766h, 02367h, 02B68h, 02F69h
4307: DW 03F6Ah, 03B6Bh, 03F6Ch, 03B6Dh, 03B6Eh, 03F6Fh, 02370h, 02771h
4308: DW 02772h, 02373h, 02774h, 02375h, 02376h, 02777h, 02F78h, 02B79h
4309: DW 03B7Ah, 03F7Bh, 03B7Ch, 03F7Dh, 03F7Eh, 03B7Fh, 08380h, 08781h
4310: DW 08782h, 08383h, 08784h, 08385h, 08386h, 08787h, 08F88h, 08B89h
4311: DW 09B8Ah, 09F8Bh, 09B8Ch, 09F8Dh, 09F8Eh, 09B8Fh, 08790h, 08391h
4312: DW 08392h, 08793h, 08394h, 08795h, 08796h, 08397h, 08B98h, 08F99h
4313: DW 09F9Ah, 09B9Bh, 09F9Ch, 09B9Dh, 09B9Eh, 09F9Fh, 0A7A0h, 0A3A1h
4314: DW 0A3A2h, 0A7A3h, 0A3A4h, 0A7A5h, 0A7A6h, 0A3A7h, 0ABA8h, 0AFA9h
4315: DW 0BFAAh, 0BBABh, 0BFACh, 0BBADh, 0BBAEh, 0BFAFh, 0A3B0h, 0A7B1h
4316: DW 0A7B2h, 0A3B3h, 0A7B4h, 0A3B5h, 0A3B6h, 0A7B7h, 0AFB8h, 0ABB9h
4317: DW 0BBBAh, 0BFBBh, 0BBBCh, 0BFBDh, 0BFBEh, 0BBBFh, 087C0h, 083C1h
4318: DW 083C2h, 087C3h, 083C4h, 087C5h, 087C6h, 083C7h, 08BC8h, 08FC9h
4319: DW 09FCAh, 09BCBh, 09FCCh, 09BCDh, 09BCEh, 09FCFh, 083D0h, 087D1h
4320: DW 087D2h, 083D3h, 087D4h, 083D5h, 083D6h, 087D7h, 08FD8h, 08BD9h
4321: DW 09BDAh, 09FDBh, 09BDCh, 09FDDh, 09FDEh, 09BDFh, 0A3E0h, 0A7E1h
4322: DW 0A7E2h, 0A3E3h, 0A7E4h, 0A3E5h, 0A3E6h, 0A7E7h, 0AFE8h, 0ABE9h
4323: DW 0BBEAh, 0BFEBh, 0BBECh, 0BFEDh, 0BFEEh, 0BBEFh, 0A7F0h, 0A3F1h
4324: DW 0A3F2h, 0A7F3h, 0A3F4h, 0A7F5h, 0A7F6h, 0A3F7h, 0ABF8h, 0AFF9h
4325: DW 0BFFAh, 0BBFBh, 0BFFCh, 0BBFDh, 0BBFEh, 0BFFFh, 04700h, 00301h
4326: DW 00302h, 00703h, 00304h, 00705h, 00706h, 00307h, 00B08h, 00F09h
4327: DW 01F0Ah, 01B0Bh, 01F0Ch, 01B0Dh, 01B0Eh, 01F0Fh, 00310h, 00711h
4328: DW 00712h, 00313h, 00714h, 00315h, 00316h, 00717h, 00F18h, 00B19h
4329: DW 01B1Ah, 01F1Bh, 01B1Ch, 01F1Dh, 01F1Eh, 01B1Fh, 02320h, 02721h
4330: DW 02722h, 02323h, 02724h, 02325h, 02326h, 02727h, 02F28h, 02B29h
4331: DW 03B2Ah, 03F2Bh, 03B2Ch, 03F2Dh, 03F2Eh, 03B2Fh, 02730h, 02331h
4332: DW 02332h, 02733h, 02334h, 02735h, 02736h, 02337h, 02B38h, 02F39h
4333: DW 03F3Ah, 03B3Bh, 03F3Ch, 03B3Dh, 03B3Eh, 03F3Fh, 00340h, 00741h
4334: DW 00742h, 00343h, 00744h, 00345h, 00346h, 00747h, 00F48h, 00B49h
4335: DW 01B4Ah, 01F4Bh, 01B4Ch, 01F4Dh, 01F4Eh, 01B4Fh, 00750h, 00351h
4336: DW 00352h, 00753h, 00354h, 00755h, 00756h, 00357h, 00B58h, 00F59h
4337: DW 01F5Ah, 01B5Bh, 01F5Ch, 01B5Dh, 01B5Eh, 01F5Fh, 02760h, 02361h
4338: DW 02362h, 02763h, 02364h, 02765h, 02766h, 02367h, 02B68h, 02F69h
4339: DW 03F6Ah, 03B6Bh, 03F6Ch, 03B6Dh, 03B6Eh, 03F6Fh, 02370h, 02771h
4340: DW 02772h, 02373h, 02774h, 02375h, 02376h, 02777h, 02F78h, 02B79h
4341: DW 03B7Ah, 03F7Bh, 03B7Ch, 03F7Dh, 03F7Eh, 03B7Fh, 08380h, 08781h
4342: DW 08782h, 08383h, 08784h, 08385h, 08386h, 08787h, 08F88h, 08B89h
4343: DW 09B8Ah, 09F8Bh, 09B8Ch, 09F8Dh, 09F8Eh, 09B8Fh, 08790h, 08391h
4344: DW 08392h, 08793h, 08394h, 08795h, 08796h, 08397h, 08B98h, 08F99h
4345:
4346: NEG_Table:
4347: DB 0,66,255,187,254,187,253,187,252,187,251,187,250,187,249,187,248,187,247,179
4348: DB 246,179,245,179,244,179,243,179,242,179,241,179,240,163,239,187,238,187,237,187
4349: DB 236,187,235,187,234,187,233,187,232,187,231,179,230,179,229,179,228,179,227,179
4350: DB 226,179,225,179,224,163,223,155,222,155,221,155,220,155,219,155,218,155,217,155
4351: DB 216,155,215,147,214,147,213,147,212,147,211,147,210,147,209,147,208,131,207,155
4352: DB 206,155,205,155,204,155,203,155,202,155,201,155,200,155,199,147,198,147,197,147
4353: DB 196,147,195,147,194,147,193,147,192,131,191,187,190,187,189,187,188,187,187,187
4354: DB 186,187,185,187,184,187,183,179,182,179,181,179,180,179,179,179,178,179,177,179
4355: DB 176,163,175,187,174,187,173,187,172,187,171,187,170,187,169,187,168,187,167,179
4356: DB 166,179,165,179,164,179,163,179,162,179,161,179,160,163,159,155,158,155,157,155
4357: DB 156,155,155,155,154,155,153,155,152,155,151,147,150,147,149,147,148,147,147,147
4358: DB 146,147,145,147,144,131,143,155,142,155,141,155,140,155,139,155,138,155,137,155
4359: DB 136,155,135,147,134,147,133,147,132,147,131,147,130,147,129,147,128,135,127,59
4360: DB 126,59,125,59,124,59,123,59,122,59,121,59,120,59,119,51,118,51,117,51
4361: DB 116,51,115,51,114,51,113,51,112,35,111,59,110,59,109,59,108,59,107,59
4362: DB 106,59,105,59,104,59,103,51,102,51,101,51,100,51,99,51,98,51,97,51
4363: DB 96,35,95,27,94,27,93,27,92,27,91,27,90,27,89,27,88,27,87,19
4364: DB 86,19,85,19,84,19,83,19,82,19,81,19,80,3,79,27,78,27,77,27
4365: DB 76,27,75,27,74,27,73,27,72,27,71,19,70,19,69,19,68,19,67,19
4366: DB 66,19,65,19,64,3,63,59,62,59,61,59,60,59,59,59,58,59,57,59
4367: DB 56,59,55,51,54,51,53,51,52,51,51,51,50,51,49,51,48,35,47,59
4368: DB 46,59,45,59,44,59,43,59,42,59,41,59,40,59,39,51,38,51,37,51
4369: DB 36,51,35,51,34,51,33,51,32,35,31,27,30,27,29,27,28,27,27,27
4370: DB 26,27,25,27,24,27,23,19,22,19,21,19,20,19,19,19,18,19,17,19
4371: DB 16,3,15,27,14,27,13,27,12,27,11,27,10,27,9,27,8,27,7,19
4372: DB 6,19,5,19,4,19,3,19,2,19,1,19
4373:
4374: ;- the end ------ (blimey) --------------------------------------------------;
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.