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1.1 root 1: ;----------------------------------------------------------------------------;
2: ; RAZE-x86 Z80 emulator.
3: ; version 1.06
4: ;
5: ; Copyright (c) 1999 Richard Mitton
6: ;
7: ; This may only be distributed as part of the complete RAZE package.
8: ; See RAZE.TXT for license information.
9: ;----------------------------------------------------------------------------;
10:
11:
12: ; You are not expected to understand this.
13:
14:
15: ;----------------------------------------------------------------------------;
16: ; Comment these in/out for faster speed (less accurate):
17: %define EMULATE_UNDOC_FLAGS ; a couple of undocumented flags
18: %define EMULATE_BITS_3_5 ; bits 3/5 of the flags (undocumented)
19: %define EMULATE_WEIRD_STUFF ; misc *very obscure* undocumented behaviour
20: %define EMULATE_R_REGISTER ; precise R register (not usually needed)
21: ;;;;%define USE_FETCH_CALLBACK ; call a callback for every fetch (slow!)
22: ;----------------------------------------------------------------------------;
23:
24: ; Registers:
25: ; AF = ax (flags in AH)
26: ; HL = bx
27: ; BC = cx
28: ; PC = si
29: ; R = ebp
30: ;
31: ; GCC wants EBX, ESI, EDI, ESP, and EBP to be preserved at all times
32: ; DH should always be clear between macros
33: ; The high 16-bits of all registers should be clear at all times (except EBP)
34: ; This assumes LAHF will set bit 1 of AH. (supposed to be undefined...)
35:
36: BITS 32
37: SECTION .bss USE32
38:
39: ; Maximum number of memory handlers
40: %define MAX_MEM_HANDLERS 64
41:
42: ; The current context
43: align 16
44: context_start:
45: z80_AF resd 1
46: z80_BC resd 1
47: z80_DE resd 1
48: z80_HL resd 1
49: z80_IX resd 1
50: z80_IY resd 1
51: z80_PC resd 1
52: z80_SP resd 1
53: z80_AF2 resd 1
54: z80_BC2 resd 1
55: z80_DE2 resd 1
56: z80_HL2 resd 1
57: z80_IFF1 resb 1
58: z80_IFF2 resb 1
59: z80_R resd 1
60: z80_R2 resd 1
61: z80_I resb 1
62: z80_flag35 resb 1
63: z80_IM resb 1
64: z80_IRQVector resb 1
65: z80_IRQLine resb 1
66: z80_halted resb 1
67: z80_Extra_Cycles resd 1
68: registers_end:
69:
70: z80_Fetch resd 256
71: z80_Read resd (256*2)
72: z80_Write resd (256*2)
73: z80_In resd 1
74: z80_Out resd 1
75: z80_RetI resd 1
76: z80_Fetch_Callback resd 1
77: _read_handlers resd 4*MAX_MEM_HANDLERS
78: _write_handlers resd 4*MAX_MEM_HANDLERS
79: context_end:
80: resd 1 ; safety gap, so z80_reset can use 32-bit transfers
81:
82: ; Variables
83: z80_ICount resd 1
84: z80_Initial_ICount resd 1
85: z80_TempICount resd 1
86: z80_afterEI resb 1
87:
88: SECTION .text USE32
89: ;----------------------------------------------------------------------------;
90: ; Prepare to call a GCC function
91: %macro CALLGCC_START 0
92: mov [z80_AF], ezAF ; eax
93: mov [z80_BC], ezBC ; ecx
94: mov [z80_PC], ezPC ; esi
95: mov [z80_R], zR ; ebp
96: %endmacro
97:
98: ; Return from a GCC function
99: %macro CALLGCC_END 0
100: mov ezAF, [z80_AF] ; eax
101: mov ezBC, [z80_BC] ; ecx
102: mov ezPC, [z80_PC] ; esi
103: mov zR, [z80_R] ; ebp
104: %endmacro
105:
106: ; Read a byte from the PC, into DL
107: ; GETBYTE
108: %macro GETBYTE 0
109: %ifdef USE_FETCH_CALLBACK
110: CALLGCC_START
111: push ezPC
112: call [z80_Fetch_Callback]
113: add esp, 4
114: CALLGCC_END
115: %endif
116: mov edx, ezPC
117: shr edx, 8
118: mov edi, [z80_Fetch+edx*4]
119:
120: mov dl, [edi+ezPC]
121: inc zPC
122: xor edi, edi
123: %endmacro
124:
125: ; Read a byte from the PC, sign-extended into DI
126: ; GETDISP
127: %macro GETDISP 0
128: %ifdef USE_FETCH_CALLBACK
129: CALLGCC_START
130: push ezPC
131: call [z80_Fetch_Callback]
132: add esp, 4
133: CALLGCC_END
134: %endif
135: mov edx, ezPC
136: shr edx, 8
137: mov edx, [z80_Fetch+edx*4]
138:
139: movsx di, [edx+ezPC]
140: inc zPC
141: xor edx, edx
142: %endmacro
143:
144: ; Read a word from the PC, into DI
145: ; GETWORD
146: %macro GETWORD 0
147: %ifdef USE_FETCH_CALLBACK
148: CALLGCC_START
149: push ezPC
150: call [z80_Fetch_Callback]
151: add esp, 4
152: CALLGCC_END
153: %endif
154: mov [z80_BC], ezBC
155: mov edx, ezPC ; low byte
156: shr edx, 8
157: mov edi, [z80_Fetch+edx*4]
158:
159: mov dl, [edi+ezPC]
160: inc zPC
161:
162: %ifdef USE_FETCH_CALLBACK
163: push edx
164: CALLGCC_START
165: push ezPC
166: call [z80_Fetch_Callback]
167: add esp, 4
168: CALLGCC_END
169: pop edx
170: %endif
171: mov ecx, ezPC ; high byte
172: shr ecx, 8
173: mov edi, [z80_Fetch+ecx*4]
174:
175: mov dh, [edi+ezPC]
176: inc zPC
177: mov edi, edx
178: mov ezBC, [z80_BC]
179: xor edx, edx
180: %endmacro
181:
182: ; Read a byte from memory (DI) into DL
183: ; MEMREAD
184: %macro MEMREAD 0
185: CALLGCC_START
186: mov edx, edi
187: shr edx, 8
188: mov ecx, [z80_Read+edx*8]
189:
190: test ecx, ecx ; if handler exists, call it
191: jnz %%handler
192: ; no handler, so go direct
193: mov ecx, [z80_Read+edx*8+4]
194: mov dl, [ecx+edi]
195: jmp %%finish
196:
197: %%handler:
198: push edi
199: call ecx
200: xor edx, edx
201: add esp, 4
202: mov dl, al
203: %%finish:
204: CALLGCC_END
205: %endmacro
206:
207: ; Write a byte in DL to memory (DI)
208: %macro MEMWRITE 0
209: CALLGCC_START
210: xor eax, eax
211: mov al, dl
212:
213: mov edx, edi
214: shr edx, 8
215: mov ecx, [z80_Write+edx*8]
216:
217: test ecx, ecx ; if handler exists, call it
218: jnz %%handler
219: ; no handler, so go direct
220: mov ecx, [z80_Write+edx*8+4]
221: mov [ecx+edi], al
222: jmp %%finish
223:
224: %%handler:
225: push eax
226: push edi
227: call ecx
228: add esp, 8
229: %%finish:
230: CALLGCC_END
231: xor edx, edx
232: %endmacro
233:
234: ; Read a byte from port (DI) into DL
235: ; IOREAD
236: %macro IOREAD 0
237: push edi
238: CALLGCC_START
239: call [z80_In]
240: xor edx, edx
241: add esp, 4
242: mov dl, al
243: CALLGCC_END
244: %endmacro
245:
246: ; Write a byte in DL to port (DI)
247: %macro IOWRITE 0
248: CALLGCC_START
249: xor dh, dh
250: push edx
251: push edi
252: call [z80_Out]
253: add esp, 8
254: CALLGCC_END
255: xor edx, edx
256: %endmacro
257:
258: ; Align code to the default boundary
259: %macro ALIGN 0
260: align 4
261: %endmacro
262:
263: ; Define an instruction
264: ; DEF prefix, opcode, std_cycles, extra_cycles
265: %macro DEF 4
266: ALIGN
267: %define std_cycles %3
268: %define extra_cycles %4
269: %{1}_%2:
270: %endmacro
271:
272: ; Subtract the clock cycles for this instruction from the ICount
273: %macro DO_CYCLES 0
274: sub dword [z80_ICount], std_cycles
275: jbe near z80_finish
276: %endmacro
277:
278: ; Subtract the extra clock cycles for this instruction from the ICount
279: %macro DO_EXTRA_CYCLES 0
280: sub dword [z80_ICount], extra_cycles
281: jbe near z80_finish
282: %endmacro
283:
284: ; Finish straight away
285: %macro EXIT 0
286: jmp z80_finish
287: %endmacro
288:
289: ; Jump to the next instruction
290: %macro NEXT 0
291: %ifdef EMULATE_R_REGISTER
292: inc zR
293: %endif
294: GETBYTE
295: jmp [OpTable+edx*4]
296: %endmacro
297:
298: ; Check the IRQ line, cause an interrupt if needed
299: %macro CHECK_IRQ 0
300: cmp [z80_IRQLine], byte 0 ; check the IRQ line
301: je near %%finish
302: cmp [z80_IFF1], byte 0 ; check ints are enabled
303: je near %%finish
304:
305: ; disable interrupts
306: mov [z80_IFF1], byte 0
307: mov [z80_IFF2], byte 0
308: %ifdef EMULATE_R_REGISTER
309: inc zR
310: %endif
311:
312: mov [z80_halted], byte 0 ; Un-HALT the Z80
313:
314: mov edx, ezPC ; write the PC
315: dec zSP
316:
317: xchg dl, dh
318: mov edi, ezSP
319: MEMWRITE
320: dec zSP
321: mov edx, ezPC
322: mov edi, ezSP
323: MEMWRITE
324:
325: cmp [z80_IM], byte 0
326: jne %%not_im0
327: ; IM 0, 13 T-states
328: add [z80_Extra_Cycles], dword 13
329: mov dl, [z80_IRQVector]
330: sub dl, 0c7h
331: movzx ezPC, dl
332: jmp %%finish
333:
334: %%not_im0:
335: cmp [z80_IM], byte 1
336: jne %%not_im1
337: ; IM 1, 13 T-states
338: add [z80_Extra_Cycles], dword 13
339: mov ezPC, 38h
340: jmp %%finish
341:
342: %%not_im1:
343: ; IM 2, 19 T-states
344: add [z80_Extra_Cycles], dword 19
345: mov dl, [z80_IRQVector]
346: mov dh, zI
347: mov edi, edx
348: MEMREAD
349: inc di
350: mov ezPC, edx
351: MEMREAD
352: xchg dl, dh
353: or ezPC, edx
354: xor dh, dh
355: %%finish:
356: %endmacro
357:
358: ;----------------------------------------------------------------------------;
359: ; Helper functions
360:
361: ; Add A, %1
362: %macro DO_ADD 1
363: add zA, %1
364: %ifdef EMULATE_BITS_3_5
365: mov [z80_flag35], zA
366: %endif
367: lahf
368: jo %%set_overflow
369:
370: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C
371: jmp %%finish
372:
373: %%set_overflow:
374: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C
375: or zF, FLAG_P
376: %%finish:
377: %endmacro
378:
379: ; Sub A, %1
380: %macro DO_SUB 1
381: sub zA, %1
382: %ifdef EMULATE_BITS_3_5
383: mov [z80_flag35], zA
384: %endif
385: lahf
386: jo %%set_overflow
387:
388: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C|FLAG_N
389: jmp %%finish
390:
391: %%set_overflow:
392: or zF, FLAG_P
393: %%finish:
394: %endmacro
395:
396: ; Adc A, %1
397: %macro DO_ADC 1
398: ror zF, 1
399: adc zA, %1
400: %ifdef EMULATE_BITS_3_5
401: mov [z80_flag35], zA
402: %endif
403: lahf
404: jo %%set_overflow
405:
406: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C
407: jmp %%finish
408:
409: %%set_overflow:
410: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C
411: or zF, FLAG_P
412: %%finish:
413: %endmacro
414:
415: ; Sbc A, %1
416: %macro DO_SBC 1
417: ror zF, 1
418: sbb zA, %1
419: %ifdef EMULATE_BITS_3_5
420: mov [z80_flag35], zA
421: %endif
422: lahf
423: jo %%set_overflow
424:
425: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C|FLAG_N
426: jmp %%finish
427:
428: %%set_overflow:
429: or zF, FLAG_P
430: %%finish:
431: %endmacro
432:
433: ; And A, %1
434: %macro DO_AND 1
435: and zA, %1
436: %ifdef EMULATE_BITS_3_5
437: mov [z80_flag35], zA
438: %endif
439: lahf
440: and zF, ~(FLAG_N|FLAG_C) ; clear N and carry
441: or zF, FLAG_H ; set half-carry
442: %endmacro
443:
444: ; Or A, %1
445: %macro DO_OR 1
446: or zA, %1
447: %ifdef EMULATE_BITS_3_5
448: mov [z80_flag35], zA
449: %endif
450: lahf
451: and zF, ~(FLAG_N|FLAG_C|FLAG_H) ; clear N, carry and half-carry
452: %endmacro
453:
454: ; Xor A, %1
455: %macro DO_XOR 1
456: xor zA, %1
457: %ifdef EMULATE_BITS_3_5
458: mov [z80_flag35], zA
459: %endif
460: lahf
461: and zF, ~(FLAG_N|FLAG_C|FLAG_H) ; clear N, carry and half-carry
462: %endmacro
463:
464: ; Cp A, %1
465: %macro DO_CP 1
466: %ifdef EMULATE_BITS_3_5
467: mov ah, %1
468: mov [z80_flag35], ah
469: %endif
470: cmp zA, %1
471: lahf
472: jo %%overflow
473:
474: and zF, ~FLAG_P ; clear the overflow
475: or zF, FLAG_N ; set the N flag
476: jmp %%finish
477:
478: %%overflow:
479: or zF, FLAG_P|FLAG_N ; set the overflow and N flag
480: %%finish:
481: %endmacro
482:
483: ; Inc %1
484: %macro DO_INC 1
485: and zF, FLAG_C ; leave carry alone
486: %ifnidn %1, dl
487: mov dl, %1
488: %endif
489: or zF, [INC_Table+edx]
490: inc %1
491: %ifdef EMULATE_BITS_3_5
492: %ifnidn %1, dl
493: inc dl
494: %endif
495: mov [z80_flag35], dl
496: %endif
497: %endmacro
498:
499: ; Dec %1
500: %macro DO_DEC 1
501: and zF, FLAG_C ; leave carry alone
502: %ifnidn %1, dl
503: mov dl, %1
504: %endif
505: or zF, [DEC_Table+edx]
506: dec %1
507: %ifdef EMULATE_BITS_3_5
508: %ifnidn %1, dl
509: dec dl
510: %endif
511: mov [z80_flag35], dl
512: %endif
513: %endmacro
514:
515: ; Add16 %1, %2
516: %macro DO_ADD16 2
517: %ifidn %2, dx
518: %error "DX used as parameter for DO_ADD16!"
519: %endif
520: mov edi, e%2
521: %ifdef EMULATE_UNDOC_FLAGS
522: mov edx, e%1
523: %endif
524: and zF, FLAG_S|FLAG_Z|FLAG_P
525:
526: add %1, di ; do it
527: adc zF, 0 ; merge the new carry in
528:
529: %ifdef EMULATE_UNDOC_FLAGS
530: xor edx, e%1 ; work out our new half-carry
531: xor edx, edi
532: and dh, FLAG_H
533: or zF, dh
534: %endif
535:
536: %ifdef EMULATE_BITS_3_5
537: mov dl, h%1
538: mov [z80_flag35], dl
539: %endif
540: %ifdef EMULATE_UNDOC_FLAGS
541: xor dh, dh
542: %endif
543: %endmacro
544:
545: ; Adc16 %1, %2
546: %macro DO_ADC16 2
547: %ifidn %2, dx
548: %error "DX used as parameter for DO_ADC16!"
549: %endif
550: mov edi, e%2
551: %ifdef EMULATE_UNDOC_FLAGS
552: mov edx, e%1
553: %endif
554: ror zF, 1 ; load the carry
555: adc %1, %2
556: lahf
557: jo %%overflow
558:
559: and zF, ~(FLAG_N|FLAG_H|FLAG_P) ; clear N,H and overflow
560: jmp %%finish
561:
562: %%overflow:
563: and zF, ~(FLAG_N|FLAG_H) ; clear N and H
564: or zF, FLAG_P ; set overflow
565: %%finish:
566:
567: %ifdef EMULATE_UNDOC_FLAGS
568: xor edx, e%1 ; work out our new half-carry
569: xor edx, edi
570: and dh, FLAG_H
571: or zF, dh
572: %endif
573:
574: %ifdef EMULATE_BITS_3_5
575: mov dl, h%1
576: mov [z80_flag35], dl
577: %endif
578: %ifdef EMULATE_UNDOC_FLAGS
579: xor dh, dh
580: %endif
581: %endmacro
582:
583: ; Sbc16 %1, %2
584: %macro DO_SBC16 2
585: %ifidn %2, dx
586: %error "DX used as parameter for DO_SBC16!"
587: %endif
588: %ifdef EMULATE_UNDOC_FLAGS
589: mov edi, e%2
590: %endif
591: mov edx, e%1
592: ror zF, 1 ; load the carry
593: sbb %1, %2
594: lahf
595: jo %%overflow
596:
597: and zF, ~(FLAG_P|FLAG_H) ; clear H and overflow
598: or zF, FLAG_N ; set N
599: jmp %%finish
600:
601: %%overflow:
602: or zF, FLAG_N|FLAG_P ; set overflow and N
603: and zF, ~FLAG_H ; clear H
604: %%finish:
605:
606: %ifdef EMULATE_UNDOC_FLAGS
607: xor edx, e%1 ; work out our new half-carry
608: xor edx, edi
609: and dh, FLAG_H
610: or zF, dh
611: %endif
612:
613: %ifdef EMULATE_BITS_3_5
614: mov dl, h%1
615: mov [z80_flag35], dl
616: %endif
617: %ifdef EMULATE_UNDOC_FLAGS
618: xor dh, dh
619: %endif
620: %endmacro
621:
622: ; Rotate method, reg8
623: %macro DO_ROT 2
624: %ifidn %1, RLA
625: mov dl, zF
626: and dl, FLAG_S|FLAG_Z|FLAG_P
627: sahf
628: rcl zA, 1
629: adc dl, 0
630: %ifdef EMULATE_BITS_3_5
631: mov [z80_flag35], zA
632: %endif
633: mov zF, dl
634: %elifidn %1, RRA
635: mov dl, zF
636: and dl, FLAG_S|FLAG_Z|FLAG_P
637: sahf
638: rcr zA, 1
639: adc dl, 0
640: %ifdef EMULATE_BITS_3_5
641: mov [z80_flag35], zA
642: %endif
643: mov zF, dl
644: %elifidn %1, RLCA
645: and zF, FLAG_S|FLAG_Z|FLAG_P
646: rol zA, 1
647: adc zF, 0
648: %ifdef EMULATE_BITS_3_5
649: mov [z80_flag35], zA
650: %endif
651: %elifidn %1, RRCA
652: and zF, FLAG_S|FLAG_Z|FLAG_P
653: ror zA, 1
654: adc zF, 0
655: %ifdef EMULATE_BITS_3_5
656: mov [z80_flag35], zA
657: %endif
658: %else
659: %ifnidn %2, dl
660: mov dl, %2
661: %endif
662:
663: %ifidn %1, RLC
664: rol dl, 1
665: %elifidn %1, RRC
666: ror dl, 1
667: %elifidn %1, RL
668: sahf
669: rcl dl, 1
670: %elifidn %1, RR
671: sahf
672: rcr dl, 1
673: %endif
674:
675: adc dh, dh
676: test dl, dl
677: lahf
678: and zF, FLAG_S|FLAG_Z|FLAG_P
679: or zF, dh
680: %ifdef EMULATE_BITS_3_5
681: mov [z80_flag35], dl
682: %endif
683: %ifnidn %2, dl
684: mov %2, dl
685: %endif
686: xor dh, dh
687: %endif
688: %endmacro
689:
690: ; Shift method, reg8
691: %macro DO_SHF 2
692: %ifnidn %2, dl
693: mov dl, %2
694: %endif
695:
696: %ifidn %1, SLA
697: add dl, dl
698: adc dh, dh
699: %elifidn %1, SLL
700: add dl, dl
701: adc dh, dh
702: inc dl
703: %elifidn %1, SRA
704: sar dl, 1
705: adc dh, dh
706: %elifidn %1, SRL
707: shr dl, 1
708: adc dh, dh
709: %endif
710:
711: test dl, dl
712: lahf
713: and zF, FLAG_S|FLAG_Z|FLAG_P
714: or zF, dh
715: %ifdef EMULATE_BITS_3_5
716: mov [z80_flag35], dl
717: %endif
718: %ifnidn %2, dl
719: mov %2, dl
720: %endif
721: xor dh, dh
722: %endmacro
723:
724: ; BIT r,n n = bit (0-7)
725: ; r = 8-bit register
726: %macro DO_BIT 2
727: and zF, FLAG_C
728: test %1, (1 << %2)
729: %ifdef EMULATE_BITS_3_5
730: ; bit 3 and 5 are set from the register
731: ; (actually they are bizarrely set, but
732: ; there's no point emulating that, it's just
733: ; plain silly...)
734: %ifnidn %1, dl
735: mov dl, %1 ; put in DL if not there already
736: %endif
737: mov [z80_flag35], dl
738: %endif
739:
740: jz %%bit_is_clear
741: %ifidn %2, 7
742: or zF, FLAG_H|FLAG_S ; set sign bit, if testing bit 7
743: %else
744: or zF, FLAG_H ; set half-carry, and parity
745: %endif
746: jmp %%finish
747:
748: %%bit_is_clear:
749: or zF, FLAG_H|FLAG_Z|FLAG_P ; set half-carry, parity, and zero
750: %%finish:
751: %endmacro
752:
753: ; SET r,n n = bit (0-7)
754: ; r = 8-bit register
755: %macro DO_SET 2
756: or %1, (1 << %2)
757: %endmacro
758:
759: ; RES r,n n = bit (0-7)
760: ; r = 8-bit register
761: %macro DO_RES 2
762: and %1, ~(1 << %2)
763: %endmacro
764:
765: ;----------------------------------------------------------------------------;
766: ; Here are the interface functions:
767:
768: ; Move a register to another
769: ; LD_R_R d8, s8 s8 = src reg, d8 = dest reg
770: %macro LD_R_R 2
771: %ifnidn %1, %2
772: %ifidn %2, D
773: mov dl, zD
774: mov z%1, dl
775: %elifidn %2, E
776: mov dl, zE
777: mov z%1, dl
778: %else
779: mov z%1, z%2
780: %endif
781: %endif
782: DO_CYCLES
783: NEXT
784: %endmacro
785:
786: ; Move a register to another (IXh/IXl)
787: ; LD_XYr_XYr d8, s8 s8 = src reg, d8 = dest reg
788: %macro LD_XYr_XYr 2
789: %ifnidn %1, %2
790: mov dl, z%2
791: mov z%1, dl
792: %endif
793: DO_CYCLES
794: NEXT
795: %endmacro
796:
797: ; Move an immediate byte into a register
798: ; LD_R_N d8 d8 = dest reg
799: %macro LD_R_N 1
800: GETBYTE
801: mov z%1, dl
802: DO_CYCLES
803: NEXT
804: %endmacro
805:
806: ; Move from (RR) into a register
807: ; LD_R_mRR d8, s16 d8 = dest reg, s16 = src reg
808: %macro LD_R_mRR 2
809: mov edi, ez%2
810: MEMREAD
811: mov z%1, dl
812: DO_CYCLES
813: NEXT
814: %endmacro
815:
816: ; Move from (XY+dd) into a register
817: ; LD_R_mXY d8, s16 d8 = dest reg, s16 = src reg
818: %macro LD_R_mXY 2
819: GETDISP
820: add di, z%2
821: MEMREAD
822: mov z%1, dl
823: DO_CYCLES
824: NEXT
825: %endmacro
826:
827: ; Move from a register into (RR)
828: ; LD_mRR_R d16, s8 d16 = destreg, s8 = src reg
829: %macro LD_mRR_R 2
830: mov edi, ez%1
831: mov dl, z%2
832: MEMWRITE
833: DO_CYCLES
834: NEXT
835: %endmacro
836:
837: ; Move from a register into (XY+dd)
838: ; LD_mXY_R d16, s8 d16 = dest reg, s8 = src reg
839: %macro LD_mXY_R 2
840: GETDISP
841: add di, z%1
842: mov dl, z%2
843: MEMWRITE
844: DO_CYCLES
845: NEXT
846: %endmacro
847:
848: ; Move an immediate into (RR)
849: ; LD_mRR_N d16 d16 = dest reg
850: %macro LD_mRR_N 1
851: GETBYTE
852: mov edi, ez%1
853: MEMWRITE
854: DO_CYCLES
855: NEXT
856: %endmacro
857:
858: ; Move an immediate into (XY+dd)
859: ; LD_mXY_N d16 d16 = dest reg
860: %macro LD_mXY_N 1
861: GETDISP
862: add di, z%1
863: push edi
864: GETBYTE
865: pop edi
866: MEMWRITE
867: DO_CYCLES
868: NEXT
869: %endmacro
870:
871: ; Move from (NN) into a register
872: ; LD_R_mNN d8 d8 = dest reg
873: %macro LD_R_mNN 1
874: GETWORD
875: MEMREAD
876: mov z%1, dl
877: DO_CYCLES
878: NEXT
879: %endmacro
880:
881: ; Move from a register into (NN)
882: ; LD_mNN_R s8 s8 = src reg
883: %macro LD_mNN_R 1
884: GETWORD
885: mov dl, z%1
886: MEMWRITE
887: DO_CYCLES
888: NEXT
889: %endmacro
890:
891: ; Move the Interrupt register into a register
892: ; LD_R_I d8 d8 = dest reg
893: %macro LD_R_I 1
894: mov z%1, zI
895: and zF, FLAG_C ; keep old carry
896: mov dl, zF
897:
898: test z%1, z%1
899: lahf
900: and zF, FLAG_S|FLAG_Z ; set S/Z from the I register
901: or zF, dl
902: or zF, [z80_IFF2]
903: %ifdef EMULATE_BITS_3_5
904: mov [z80_flag35], z%1
905: %endif
906: DO_CYCLES
907: NEXT
908: %endmacro
909:
910: ; Move a register into the Interrupt register
911: ; LD_I_R s8 s8 = src reg
912: %macro LD_I_R 1
913: mov zI, z%1
914: DO_CYCLES
915: NEXT
916: %endmacro
917:
918: ; Move the Refresh register into a register
919: ; LD_R_Rf d8 d8 = dest reg
920: %macro LD_R_Rf 1
921: mov edx, [z80_R2]
922: and edx, 80h ; take bits 0-6 from R, bit 7 from R2
923:
924: %ifndef EMULATE_R_REGISTER
925: ; attempt to fake the R-register
926: ; take the ICount, invert it, divide by 4
927: ; this produces an increasing counter, roughly proportional to
928: ; the number of instructions done
929: mov zR, [z80_ICount]
930: not zR
931: shr zR, 2
932: %endif
933:
934: and zR, 7fh
935: or edx, zR
936: mov z%1, dl
937:
938: mov dl, zF
939: and dl, FLAG_C ; keep the old carry
940:
941: test z%1, z%1
942: lahf
943: and zF, FLAG_S|FLAG_Z
944: or zF, dl
945: or zF, [z80_IFF2]
946: %ifdef EMULATE_BITS_3_5
947: mov [z80_flag35], z%1
948: %endif
949: DO_CYCLES
950: NEXT
951: %endmacro
952:
953: ; Move a register into the Refresh register
954: ; LD_Rf_R s8 s8 = src reg
955: %macro LD_Rf_R 1
956: mov dl, z%1
957: mov zR, edx
958: mov [z80_R2], edx
959: DO_CYCLES
960: NEXT
961: %endmacro
962:
963: ; Move a 16-bit immediate into a register
964: ; LD_RR_NN d16 d16 = dest reg
965: %macro LD_RR_NN 1
966: GETWORD
967: mov ez%1, edi
968: DO_CYCLES
969: NEXT
970: %endmacro
971:
972: ; Move from (NN) into a 16-bit register
973: ; LD_RR_mNN d16 d16 = dest reg
974: %macro LD_RR_mNN 1
975: GETWORD
976: MEMREAD
977: mov lz%1, dl
978: inc di
979: MEMREAD
980: mov hz%1, dl
981: DO_CYCLES
982: NEXT
983: %endmacro
984:
985: ; Move from a 16-bit register into (NN)
986: ; LD_mNN_RR s16 s16 = src reg
987: %macro LD_mNN_RR 1
988: GETWORD
989: mov dl, lz%1
990: MEMWRITE
991: inc di
992: mov dl, hz%1
993: MEMWRITE
994: DO_CYCLES
995: NEXT
996: %endmacro
997:
998: ; Move from a 16-bit register into another
999: ; LD_RR_RR d16, s16 s16 = src reg, d16 = dest reg
1000: %macro LD_RR_RR 2
1001: mov ez%1, ez%2
1002: DO_CYCLES
1003: NEXT
1004: %endmacro
1005:
1006: ; Move from a 16-bit register into another
1007: ; LD_RR_XY d16, s16 s16 = src reg, d16 = dest reg
1008: %macro LD_RR_XY 2
1009: mov edi, ez%2
1010: mov ez%1, edi
1011: DO_CYCLES
1012: NEXT
1013: %endmacro
1014:
1015: ; Push a word on the stack
1016: ; PUSH_RR s16 s16 = src reg
1017: %macro PUSH_RR 1
1018: mov dl, hz%1
1019: dec zSP
1020: mov edi, ezSP
1021: MEMWRITE
1022: dec zSP
1023: mov edi, ezSP
1024: %ifidn %1, AF
1025: ; merge bits 3 and 5 in
1026: and zF, ~(FLAG_3|FLAG_5)
1027: mov dl, [z80_flag35]
1028: and dl, FLAG_3|FLAG_5
1029: or zF, dl
1030: %endif
1031: mov dl, lz%1
1032: MEMWRITE
1033: DO_CYCLES
1034: NEXT
1035: %endmacro
1036:
1037: ; Pop a word from the stack
1038: ; POP_RR s16 s16 = src reg
1039: %macro POP_RR 1
1040: mov edi, ezSP
1041: MEMREAD
1042: %ifidn %1, AF
1043: mov [z80_flag35], dl ; take out bits 3/5
1044: %endif
1045: mov lz%1, dl
1046: inc zSP
1047: mov edi, ezSP
1048: MEMREAD
1049: mov hz%1, dl
1050: inc zSP
1051: DO_CYCLES
1052: NEXT
1053: %endmacro
1054:
1055: ; Exchange 2 16-bit registers
1056: ; EX_RR_RR s16, d16 s16 = src reg, d16 = dest reg
1057: %macro EX_RR_RR 2
1058: xchg ez%1, ez%2
1059: DO_CYCLES
1060: NEXT
1061: %endmacro
1062:
1063: ; Exchange AF with AF'
1064: ; EX_AF_AF2
1065: %macro EX_AF_AF2 0
1066: ; Merge bits 3+5 of the flags in first
1067: and zF, ~(FLAG_3|FLAG_5)
1068: mov dl, [z80_flag35]
1069: and dl, FLAG_3|FLAG_5
1070: or zF, dl
1071: xchg ezAF, ezAF2
1072:
1073: ; Un-merge the flags again
1074: mov [z80_flag35], zF
1075: DO_CYCLES
1076: NEXT
1077: %endmacro
1078:
1079: ; Exchange the 16-bit registers with their primes
1080: ; EXX
1081: %macro EXX 0
1082: mov edi, ezDE
1083: xchg ezBC, ezBC2
1084: xchg ezHL, ezHL2
1085: xchg edi, ezDE2
1086: mov ezDE, edi
1087: DO_CYCLES
1088: NEXT
1089: %endmacro
1090:
1091: ; Exchange a 16-bit register with (RR)
1092: ; EX_RR_mRR d16, m16 d16 = dest reg, m16 = memory reg
1093: %macro EX_RR_mRR 2
1094: mov edi, ez%2 ; swap low byte
1095: MEMREAD
1096: xchg dl, lz%1
1097: MEMWRITE
1098:
1099: inc di ; swap high byte
1100: MEMREAD
1101: xchg dl, hz%1
1102: MEMWRITE
1103:
1104: DO_CYCLES
1105: NEXT
1106: %endmacro
1107:
1108: ; Move from (HL) to (DE), post-increment
1109: ; LDI
1110: %macro LDI 0
1111: mov edi, ezHL
1112: MEMREAD
1113: %ifdef EMULATE_BITS_3_5
1114: push edx
1115: %endif
1116: mov edi, ezDE
1117: MEMWRITE
1118:
1119: %ifdef EMULATE_BITS_3_5
1120: pop edx
1121: add dl, zA
1122: mov dh, dl
1123: shl dl, 4
1124: and edx, FLAG_5 | (FLAG_3 << 8)
1125: or dl, dh
1126: mov [z80_flag35], dl
1127: xor dh, dh
1128: %endif
1129:
1130: and zF, FLAG_S|FLAG_Z|FLAG_C
1131: inc zHL
1132: inc zDE
1133: dec zBC
1134: jz %%ldi_zero
1135: or zF, FLAG_P
1136: %%ldi_zero:
1137: DO_CYCLES
1138: NEXT
1139: %endmacro
1140:
1141: ; Move from (HL) to (DE), post-decrement
1142: ; LDD
1143: %macro LDD 0
1144: mov edi, ezHL
1145: MEMREAD
1146: %ifdef EMULATE_BITS_3_5
1147: push edx
1148: %endif
1149: mov edi, ezDE
1150: MEMWRITE
1151:
1152: %ifdef EMULATE_BITS_3_5
1153: pop edx
1154: add dl, zA
1155: mov dh, dl
1156: shl dl, 4
1157: and edx, FLAG_5 | (FLAG_3 << 8)
1158: or dl, dh
1159: mov [z80_flag35], dl
1160: xor dh, dh
1161: %endif
1162:
1163: and zF, FLAG_S|FLAG_Z|FLAG_C
1164: dec zHL
1165: dec zDE
1166: dec zBC
1167: jz %%ldd_zero
1168: or zF, FLAG_P
1169: %%ldd_zero:
1170: DO_CYCLES
1171: NEXT
1172: %endmacro
1173:
1174: ; Move from (HL) to (DE), post-increment, repeat
1175: ; LDIR
1176: %macro LDIR 0
1177: %ifdef EMULATE_WEIRD_STUFF
1178: ; Code marked with CG is from Charles Gallagher, to fix the
1179: ; Spectrum game 'Quazatron'
1180: push ezPC ; CG
1181: sub zPC, 2 ; CG
1182: mov edi, ezPC ; CG
1183: shr edi, 8 ; CG
1184: add ezPC, [z80_Fetch+edi*4] ; CG
1185: %endif
1186:
1187: %%ldir_loop:
1188: %ifdef EMULATE_WEIRD_STUFF
1189: cmp [ezPC], word 0b0edh ; CG - check for self modifiying code!
1190: jne near %%ldir_modified
1191: %endif
1192:
1193: mov edi, ezHL
1194: MEMREAD
1195: %ifdef EMULATE_BITS_3_5
1196: push edx
1197: %endif
1198: mov edi, ezDE
1199: MEMWRITE
1200: %ifdef EMULATE_BITS_3_5
1201: pop edx
1202: %endif
1203:
1204: inc zHL
1205: inc zDE
1206: dec zBC
1207: jz %%ldir_zero
1208:
1209: %ifdef EMULATE_R_REGISTER
1210: inc zR
1211: %endif
1212: sub [z80_ICount], dword extra_cycles
1213: ja near %%ldir_loop
1214:
1215: %ifdef EMULATE_WEIRD_STUFF
1216: pop ezPC ; CG
1217: %endif
1218:
1219: and zF, FLAG_S|FLAG_Z|FLAG_C
1220: %ifdef EMULATE_BITS_3_5
1221: add dl, zA
1222: mov dh, dl
1223: shl dl, 4
1224: and edx, FLAG_5 | (FLAG_3 << 8)
1225: or dl, dh
1226: mov [z80_flag35], dl
1227: xor dh, dh
1228: %endif
1229: or zF, FLAG_P
1230: sub zPC, 2 ; rewind to instruction start
1231: EXIT
1232:
1233: %ifdef EMULATE_WEIRD_STUFF
1234: %%ldir_modified:
1235: sub [esp], word 2 ; CG
1236: %endif
1237:
1238: %%ldir_zero:
1239: %ifdef EMULATE_WEIRD_STUFF
1240: pop ezPC ; CG
1241: %endif
1242: and zF, FLAG_S|FLAG_Z|FLAG_C
1243: %ifdef EMULATE_BITS_3_5
1244: add dl, zA
1245: mov dh, dl
1246: shl dl, 4
1247: and edx, FLAG_5 | (FLAG_3 << 8)
1248: or dl, dh
1249: mov [z80_flag35], dl
1250: xor dh, dh
1251: %endif
1252: DO_CYCLES
1253: NEXT
1254: %endmacro
1255:
1256: ; Move from (HL) to (DE), post-decrement, repeat
1257: ; LDDR
1258: %macro LDDR 0
1259: %%lddr_loop:
1260: mov edi, ezHL
1261: MEMREAD
1262: %ifdef EMULATE_BITS_3_5
1263: push edx
1264: %endif
1265: mov edi, ezDE
1266: MEMWRITE
1267: %ifdef EMULATE_BITS_3_5
1268: pop edx
1269: %endif
1270:
1271: dec zHL
1272: dec zDE
1273: dec zBC
1274: jz %%lddr_zero
1275:
1276: %ifdef EMULATE_R_REGISTER
1277: inc zR
1278: %endif
1279: sub [z80_ICount], dword extra_cycles
1280: ja near %%lddr_loop
1281:
1282: and zF, FLAG_S|FLAG_Z|FLAG_C
1283: %ifdef EMULATE_BITS_3_5
1284: add dl, zA
1285: mov dh, dl
1286: shl dl, 4
1287: and edx, FLAG_5 | (FLAG_3 << 8)
1288: or dl, dh
1289: mov [z80_flag35], dl
1290: xor dh, dh
1291: %endif
1292: or zF, FLAG_P
1293: sub zPC, 2 ; rewind to instruction start
1294: EXIT
1295:
1296: %%lddr_zero:
1297: and zF, FLAG_S|FLAG_Z|FLAG_C
1298: %ifdef EMULATE_BITS_3_5
1299: add dl, zA
1300: mov dh, dl
1301: shl dl, 4
1302: and edx, FLAG_5 | (FLAG_3 << 8)
1303: or dl, dh
1304: mov [z80_flag35], dl
1305: xor dh, dh
1306: %endif
1307: DO_CYCLES
1308: NEXT
1309: %endmacro
1310:
1311: ; Compare A against (HL), post-increment
1312: ; CPI
1313: %macro CPI 0
1314: mov edi, ezHL
1315: MEMREAD
1316:
1317: and zF, FLAG_C ; keep the old carry
1318: mov dh, zF
1319: cmp zA, dl
1320: lahf
1321: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1322: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1323:
1324: inc zHL
1325: dec zBC
1326: jz %%cpi_zero
1327: or zF, FLAG_P ; set P if BC != 0
1328: %%cpi_zero:
1329:
1330: %ifdef EMULATE_BITS_3_5
1331: mov dh, zA
1332: sub dh, dl
1333: test zF, FLAG_H
1334: jz %%cpi_hzero
1335: dec dh
1336: %%cpi_hzero:
1337:
1338: mov dl, dh
1339: shl dl, 4
1340: and edx, FLAG_5 | (FLAG_3 << 8)
1341: or dl, dh
1342: mov [z80_flag35], dl
1343: %endif
1344: xor dh, dh
1345:
1346: DO_CYCLES
1347: NEXT
1348: %endmacro
1349:
1350: ; Compare A against (HL), post-decrement
1351: ; CPD
1352: %macro CPD 0
1353: mov edi, ezHL
1354: MEMREAD
1355:
1356: and zF, FLAG_C ; keep the old carry
1357: mov dh, zF
1358: cmp zA, dl
1359: lahf
1360: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1361: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1362:
1363: dec zHL
1364: dec zBC
1365: jz %%cpd_zero
1366: or zF, FLAG_P ; set P if BC != 0
1367: %%cpd_zero:
1368:
1369: %ifdef EMULATE_BITS_3_5
1370: mov dh, zA
1371: sub dh, dl
1372: test zF, FLAG_H
1373: jz %%cpd_hzero
1374: dec dh
1375: %%cpd_hzero:
1376:
1377: mov dl, dh
1378: shl dl, 4
1379: and edx, FLAG_5 | (FLAG_3 << 8)
1380: or dl, dh
1381: mov [z80_flag35], dl
1382: %endif
1383: xor dh, dh
1384:
1385: DO_CYCLES
1386: NEXT
1387: %endmacro
1388:
1389: ; Compare A against (HL), post-increment, repeat
1390: ; CPIR
1391: %macro CPIR 0
1392: and zF, FLAG_C ; keep the old carry
1393: %%cpir_loop:
1394: mov edi, ezHL
1395: MEMREAD
1396:
1397: inc zHL
1398: dec zBC
1399: jz %%cpir_end_bc ; end due to BC=0
1400:
1401: %ifdef EMULATE_R_REGISTER
1402: inc zR
1403: %endif
1404: cmp zA, dl
1405: je %%cpir_end_equal ; end due to A=(HL)
1406:
1407: sub [z80_ICount], dword extra_cycles
1408: ja %%cpir_loop
1409:
1410: ; out of cycles, but not finished
1411: mov dh, zF
1412: cmp zA, dl
1413: lahf
1414: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1415: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1416:
1417: %ifdef EMULATE_BITS_3_5
1418: mov dh, zA
1419: sub dh, dl
1420: test zF, FLAG_H
1421: jz %%cpir_hzero
1422: dec dh
1423: %%cpir_hzero:
1424:
1425: mov dl, dh
1426: shl dl, 4
1427: and edx, FLAG_5 | (FLAG_3 << 8)
1428: or dl, dh
1429: mov [z80_flag35], dl
1430: %endif
1431: or zF, FLAG_P ; set P to indicate not finished
1432: sub zPC, 2 ; rewind to instruction start
1433: xor dh, dh
1434: EXIT
1435:
1436: %%cpir_end_equal:
1437: or zF, FLAG_P ; set P to indicate not finished
1438: %%cpir_end_bc:
1439: mov dh, zF
1440: cmp zA, dl
1441: lahf
1442: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1443: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1444:
1445: %ifdef EMULATE_BITS_3_5
1446: mov dh, zA
1447: sub dh, dl
1448: test zF, FLAG_H
1449: jz %%cpir_hzero2
1450: dec dh
1451: %%cpir_hzero2:
1452:
1453: mov dl, dh
1454: shl dl, 4
1455: and edx, FLAG_5 | (FLAG_3 << 8)
1456: or dl, dh
1457: mov [z80_flag35], dl
1458: %endif
1459: xor dh, dh
1460: DO_CYCLES
1461: NEXT
1462: %endmacro
1463:
1464: ; Compare A against (HL), post-decrement, repeat
1465: ; CPDR
1466: %macro CPDR 0
1467: and zF, FLAG_C ; keep the old carry
1468: %%cpdr_loop:
1469: mov edi, ezHL
1470: MEMREAD
1471:
1472: dec zHL
1473: dec zBC
1474: jz %%cpdr_end_bc ; end due to BC=0
1475:
1476: %ifdef EMULATE_R_REGISTER
1477: inc zR
1478: %endif
1479: cmp zA, dl
1480: je %%cpdr_end_equal ; end due to A=(HL)
1481:
1482: sub [z80_ICount], dword extra_cycles
1483: ja %%cpdr_loop
1484:
1485: ; out of cycles, but not finished
1486: mov dh, zF
1487: cmp zA, dl
1488: lahf
1489: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1490: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1491:
1492: %ifdef EMULATE_BITS_3_5
1493: mov dh, zA
1494: sub dh, dl
1495: test zF, FLAG_H
1496: jz %%cpdr_hzero
1497: dec dh
1498: %%cpdr_hzero:
1499:
1500: mov dl, dh
1501: shl dl, 4
1502: and edx, FLAG_5 | (FLAG_3 << 8)
1503: or dl, dh
1504: mov [z80_flag35], dl
1505: %endif
1506: or zF, FLAG_P ; set P to indicate not finished
1507: sub zPC, 2 ; rewind to instruction start
1508: xor dh, dh
1509: EXIT
1510:
1511: %%cpdr_end_equal:
1512: or zF, FLAG_P ; set P to indicate not finished
1513: %%cpdr_end_bc:
1514: mov dh, zF
1515: cmp zA, dl
1516: lahf
1517: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1518: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1519:
1520: %ifdef EMULATE_BITS_3_5
1521: mov dh, zA
1522: sub dh, dl
1523: test zF, FLAG_H
1524: jz %%cpdr_hzero2
1525: dec dh
1526: %%cpdr_hzero2:
1527:
1528: mov dl, dh
1529: shl dl, 4
1530: and edx, FLAG_5 | (FLAG_3 << 8)
1531: or dl, dh
1532: mov [z80_flag35], dl
1533: %endif
1534: xor dh, dh
1535: DO_CYCLES
1536: NEXT
1537: %endmacro
1538:
1539: ; Perform arithmetic on the A register
1540: ; ART_R method, src8
1541: %macro ART_R 2
1542: %ifidn %1, ADD
1543: DO_ADD z%2
1544: %elifidn %1, ADC
1545: DO_ADC z%2
1546: %elifidn %1, SUB
1547: DO_SUB z%2
1548: %elifidn %1, SBC
1549: DO_SBC z%2
1550: %endif
1551:
1552: DO_CYCLES
1553: NEXT
1554: %endmacro
1555:
1556: ; Perform arithmetic on the A register (using an immediate)
1557: ; ART_N method
1558: %macro ART_N 1
1559: GETBYTE
1560: %ifidn %1, ADD
1561: DO_ADD dl
1562: %elifidn %1, ADC
1563: DO_ADC dl
1564: %elifidn %1, SUB
1565: DO_SUB dl
1566: %elifidn %1, SBC
1567: DO_SBC dl
1568: %endif
1569:
1570: DO_CYCLES
1571: NEXT
1572: %endmacro
1573:
1574: ; Perform arithmetic on the A register, using (XY)
1575: ; ART_mXY method, src16
1576: %macro ART_mXY 2
1577: GETDISP
1578: add di, z%2
1579: MEMREAD
1580: %ifidn %1, ADD
1581: DO_ADD dl
1582: %elifidn %1, ADC
1583: DO_ADC dl
1584: %elifidn %1, SUB
1585: DO_SUB dl
1586: %elifidn %1, SBC
1587: DO_SBC dl
1588: %endif
1589:
1590: DO_CYCLES
1591: NEXT
1592: %endmacro
1593:
1594: ; Perform arithmetic on the A register using (RR)
1595: ; ART_mRR method, src16
1596: %macro ART_mRR 2
1597: mov edi, ez%2
1598: MEMREAD
1599: %ifidn %1, ADD
1600: DO_ADD dl
1601: %elifidn %1, ADC
1602: DO_ADC dl
1603: %elifidn %1, SUB
1604: DO_SUB dl
1605: %elifidn %1, SBC
1606: DO_SBC dl
1607: %endif
1608:
1609: DO_CYCLES
1610: NEXT
1611: %endmacro
1612:
1613: ; Perform logic on the A register
1614: ; LOG_R method, src8
1615: %macro LOG_R 2
1616: %ifidn %1, AND
1617: DO_AND z%2
1618: %elifidn %1, OR
1619: DO_OR z%2
1620: %elifidn %1, XOR
1621: DO_XOR z%2
1622: %endif
1623:
1624: DO_CYCLES
1625: NEXT
1626: %endmacro
1627:
1628: ; Perform logic on the A register (using an immediate)
1629: ; LOG_N method
1630: %macro LOG_N 1
1631: GETBYTE
1632: %ifidn %1, AND
1633: DO_AND dl
1634: %elifidn %1, OR
1635: DO_OR dl
1636: %elifidn %1, XOR
1637: DO_XOR dl
1638: %endif
1639:
1640: DO_CYCLES
1641: NEXT
1642: %endmacro
1643:
1644: ; Perform logic on the A register, using (RR)
1645: ; LOG_mRR method, src16
1646: %macro LOG_mRR 2
1647: mov edi, ez%2
1648: MEMREAD
1649: %ifidn %1, AND
1650: DO_AND dl
1651: %elifidn %1, OR
1652: DO_OR dl
1653: %elifidn %1, XOR
1654: DO_XOR dl
1655: %endif
1656:
1657: DO_CYCLES
1658: NEXT
1659: %endmacro
1660:
1661: ; Perform logic on the A register, using (XY+dd)
1662: ; LOG_mXY method, src16
1663: %macro LOG_mXY 2
1664: GETDISP
1665: add di, z%2
1666: MEMREAD
1667: %ifidn %1, AND
1668: DO_AND dl
1669: %elifidn %1, OR
1670: DO_OR dl
1671: %elifidn %1, XOR
1672: DO_XOR dl
1673: %endif
1674:
1675: DO_CYCLES
1676: NEXT
1677: %endmacro
1678:
1679: ; Compare against the A register
1680: ; CP_R src8
1681: %macro CP_R 1
1682: DO_CP z%1
1683:
1684: DO_CYCLES
1685: NEXT
1686: %endmacro
1687:
1688: ; Compare against the A register, using an immediate
1689: ; CP_N
1690: %macro CP_N 0
1691: GETBYTE
1692: DO_CP dl
1693:
1694: DO_CYCLES
1695: NEXT
1696: %endmacro
1697:
1698: ; Compare against the A register, using (RR)
1699: ; CP_mRR src16
1700: %macro CP_mRR 1
1701: mov edi, ez%1
1702: MEMREAD
1703: DO_CP dl
1704:
1705: DO_CYCLES
1706: NEXT
1707: %endmacro
1708:
1709: ; Compare against the A register, using (XY+dd)
1710: ; CP_mXY src16
1711: %macro CP_mXY 1
1712: GETDISP
1713: add di, z%1
1714: MEMREAD
1715: DO_CP dl
1716:
1717: DO_CYCLES
1718: NEXT
1719: %endmacro
1720:
1721: ; Inc/dec a register
1722: ; DECINC_R method, reg8
1723: %macro DECINC_R 2
1724: %ifidn %1, INC
1725: DO_INC z%2
1726: %elifidn %1, DEC
1727: DO_DEC z%2
1728: %endif
1729:
1730: DO_CYCLES
1731: NEXT
1732: %endmacro
1733:
1734: ; Inc/dec (RR)
1735: ; DECINC_mRR method
1736: %macro DECINC_mRR 2
1737: mov edi, ez%2
1738: MEMREAD
1739: %ifidn %1, INC
1740: DO_INC dl
1741: %elifidn %1, DEC
1742: DO_DEC dl
1743: %endif
1744: MEMWRITE
1745:
1746: DO_CYCLES
1747: NEXT
1748: %endmacro
1749:
1750: ; Inc/dec (XY+dd)
1751: ; DECINC_mXY method
1752: %macro DECINC_mXY 2
1753: GETDISP
1754: add di, z%2
1755: MEMREAD
1756: %ifidn %1, INC
1757: DO_INC dl
1758: %elifidn %1, DEC
1759: DO_DEC dl
1760: %endif
1761: MEMWRITE
1762:
1763: DO_CYCLES
1764: NEXT
1765: %endmacro
1766:
1767: ; Add two 16-bit registers
1768: ; ADD_RR_RR dest16, src16
1769: %macro ADD_RR_RR 2
1770: DO_ADD16 z%1, z%2
1771:
1772: DO_CYCLES
1773: NEXT
1774: %endmacro
1775:
1776: ; Add two 16-bit registers, with carry
1777: ; ADC_RR_RR dest16, src16
1778: %macro ADC_RR_RR 2
1779: DO_ADC16 z%1, z%2
1780:
1781: DO_CYCLES
1782: NEXT
1783: %endmacro
1784:
1785: ; Subtract two 16-bit registers, with carry
1786: ; SBC_RR_RR dest16, src16
1787: %macro SBC_RR_RR 2
1788: DO_SBC16 z%1, z%2
1789:
1790: DO_CYCLES
1791: NEXT
1792: %endmacro
1793:
1794: ; Inc/dec a 16-bit register
1795: ; DECINC_RR method, reg16
1796: %macro DECINC_RR 2
1797: %ifidn %1, INC
1798: inc z%2
1799: %elifidn %1, DEC
1800: dec z%2
1801: %endif
1802:
1803: DO_CYCLES
1804: NEXT
1805: %endmacro
1806:
1807: ; Rotate a register
1808: ; ROT_R method, reg8
1809: %macro ROT_R 2
1810: DO_ROT %1, z%2
1811:
1812: DO_CYCLES
1813: NEXT
1814: %endmacro
1815:
1816: ; Rotate (RR)
1817: ; ROT_mRR method, src16
1818: %macro ROT_mRR 2
1819: mov edi, ez%2
1820: MEMREAD
1821: DO_ROT %1, dl
1822: MEMWRITE
1823:
1824: DO_CYCLES
1825: NEXT
1826: %endmacro
1827:
1828: ; Rotate (XY+dd)
1829: ; ROT_mXY method
1830: %macro ROT_mXY 1
1831: MEMREAD
1832: DO_ROT %1, dl
1833: MEMWRITE
1834:
1835: DO_CYCLES
1836: NEXT
1837: %endmacro
1838:
1839: ; Rotate (XY+dd), and store into a register
1840: ; ROT_mXY_R method, dest8
1841: %macro ROT_mXY_R 2
1842: MEMREAD
1843: DO_ROT %1, dl
1844: mov z%2, dl
1845: MEMWRITE
1846:
1847: DO_CYCLES
1848: NEXT
1849: %endmacro
1850:
1851: ; Shift a register
1852: ; SHF_R method, reg8
1853: %macro SHF_R 2
1854: DO_SHF %1, z%2
1855:
1856: DO_CYCLES
1857: NEXT
1858: %endmacro
1859:
1860: ; Shift (RR)
1861: ; SHF_mRR method, src16
1862: %macro SHF_mRR 2
1863: mov edi, ez%2
1864: MEMREAD
1865: DO_SHF %1, dl
1866: MEMWRITE
1867:
1868: DO_CYCLES
1869: NEXT
1870: %endmacro
1871:
1872: ; Shift (XY+dd)
1873: ; SHF_mXY method
1874: %macro SHF_mXY 1
1875: MEMREAD
1876: DO_SHF %1, dl
1877: MEMWRITE
1878:
1879: DO_CYCLES
1880: NEXT
1881: %endmacro
1882:
1883: ; Shift (XY+dd), and store into a register
1884: ; SHF_mXY_R method, dest8
1885: %macro SHF_mXY_R 2
1886: MEMREAD
1887: DO_SHF %1, dl
1888: mov z%2, dl
1889: MEMWRITE
1890:
1891: DO_CYCLES
1892: NEXT
1893: %endmacro
1894:
1895: ; Rotate A/(HL) left, via nibbles
1896: ; RLD
1897: %macro RLD 0
1898: mov edi, ezHL
1899: MEMREAD
1900: mov dh, zA
1901: and zF, FLAG_C
1902: shl dh, 4
1903: rol dx, 4
1904: and zA, 0f0h
1905: or zA, dh
1906: mov dh, zF
1907: lahf
1908: and zF, FLAG_S|FLAG_Z|FLAG_P
1909: or zF, dh
1910: %ifdef EMULATE_BITS_3_5
1911: mov [z80_flag35], zA
1912: %endif
1913: MEMWRITE
1914:
1915: DO_CYCLES
1916: NEXT
1917: %endmacro
1918:
1919: ; Rotate A/(HL) right, via nibbles
1920: ; RRD
1921: %macro RRD 0
1922: mov edi, ezHL
1923: MEMREAD
1924: mov dh, zA
1925: and zF, FLAG_C
1926: ror dx, 4
1927: shr dh, 4
1928: and zA, 0f0h
1929: or zA, dh
1930: mov dh, zF
1931: lahf
1932: and zF, FLAG_S|FLAG_Z|FLAG_P
1933: or zF, dh
1934: %ifdef EMULATE_BITS_3_5
1935: mov [z80_flag35], zA
1936: %endif
1937: MEMWRITE
1938:
1939: DO_CYCLES
1940: NEXT
1941: %endmacro
1942:
1943: ; Bit-test a register
1944: ; BIT_R src8, bit
1945: %macro BIT_R_b 2
1946: DO_BIT z%1, %2
1947:
1948: DO_CYCLES
1949: NEXT
1950: %endmacro
1951:
1952: ; Bit-test (RR)
1953: ; BIT_mRR_b src16, bit
1954: %macro BIT_mRR_b 2
1955: and zF, FLAG_C
1956: mov edi, ez%1
1957: MEMREAD
1958:
1959: test dl, (1 << %2)
1960:
1961: ; bit 3 and 5 are always cleared
1962: ; (actually they are bizarrely set, but
1963: ; there's no point emulating that, it's just
1964: ; plain silly...)
1965:
1966: jz %%bit_is_clear
1967: %ifidn %2, 7
1968: or zF, FLAG_H|FLAG_S ; set sign bit, if testing bit 7
1969: %else
1970: or zF, FLAG_H ; set half-carry, and parity
1971: %endif
1972: jmp %%finish
1973:
1974: %%bit_is_clear:
1975: or zF, FLAG_H|FLAG_Z|FLAG_P ; set half-carry, parity, and zero
1976: %%finish:
1977:
1978: DO_CYCLES
1979: NEXT
1980: %endmacro
1981:
1982: ; Bit-test (XY+dd)
1983: ; BIT_mXY_b bit
1984: %macro BIT_mXY_b 1
1985: %ifdef EMULATE_BITS_3_5
1986: mov edx, edi
1987: mov [z80_flag35], dh
1988: %endif
1989:
1990: MEMREAD
1991: and zF, FLAG_C
1992: test dl, (1 << %1)
1993:
1994: jz %%bit_is_clear
1995: %ifidn %1, 7
1996: or zF, FLAG_H|FLAG_S ; set sign bit, if testing bit 7
1997: %else
1998: or zF, FLAG_H ; set half-carry, and parity
1999: %endif
2000: jmp %%finish
2001:
2002: %%bit_is_clear:
2003: or zF, FLAG_H|FLAG_Z|FLAG_P ; set half-carry, parity, and zero
2004: %%finish:
2005:
2006: DO_CYCLES
2007: NEXT
2008: %endmacro
2009:
2010: ; Bit-clear a register
2011: ; RES_R_b src8, bit
2012: %macro RES_R_b 2
2013: DO_RES z%1, %2
2014:
2015: DO_CYCLES
2016: NEXT
2017: %endmacro
2018:
2019: ; Bit-clear (RR)
2020: ; RES_mRR_b src16, bit
2021: %macro RES_mRR_b 2
2022: mov edi, ez%1
2023: MEMREAD
2024: DO_RES dl, %2
2025: MEMWRITE
2026:
2027: DO_CYCLES
2028: NEXT
2029: %endmacro
2030:
2031: ; Bit-clear (XY+dd)
2032: ; RES_mXY_b bit
2033: %macro RES_mXY_b 1
2034: MEMREAD
2035: DO_RES dl, %1
2036: MEMWRITE
2037:
2038: DO_CYCLES
2039: NEXT
2040: %endmacro
2041:
2042: ; Bit-clear (XY+dd), with extra store
2043: ; RES_mXY_b_R bit, dest8
2044: %macro RES_mXY_b_R 2
2045: MEMREAD
2046: DO_RES dl, %1
2047: mov z%2, dl
2048: MEMWRITE
2049:
2050: DO_CYCLES
2051: NEXT
2052: %endmacro
2053:
2054: ; Bit-set a register
2055: ; SET_R_b src8, bit
2056: %macro SET_R_b 2
2057: DO_SET z%1, %2
2058:
2059: DO_CYCLES
2060: NEXT
2061: %endmacro
2062:
2063: ; Bit-set (RR)
2064: ; SET_mRR_b src16, bit
2065: %macro SET_mRR_b 2
2066: mov edi, ez%1
2067: MEMREAD
2068: DO_SET dl, %2
2069: MEMWRITE
2070:
2071: DO_CYCLES
2072: NEXT
2073: %endmacro
2074:
2075: ; Bit-set (XY+dd)
2076: ; SET_mXY_b bit
2077: %macro SET_mXY_b 1
2078: MEMREAD
2079: DO_SET dl, %1
2080: MEMWRITE
2081:
2082: DO_CYCLES
2083: NEXT
2084: %endmacro
2085:
2086: ; Bit-set (XY+dd), with extra store
2087: ; SET_mXY_b_R bit, dest8
2088: %macro SET_mXY_b_R 2
2089: MEMREAD
2090: DO_SET dl, %1
2091: mov z%2, dl
2092: MEMWRITE
2093:
2094: DO_CYCLES
2095: NEXT
2096: %endmacro
2097:
2098: ; Jump to an absolute address
2099: ; JP_NN
2100: %macro JP_NN 0
2101: GETWORD
2102: mov ezPC, edi
2103: DO_CYCLES
2104: NEXT
2105: %endmacro
2106:
2107: ; Jump to an absolute address, conditionally
2108: ; JP_cc_NN nz,cc
2109: %macro JP_cc_NN 2
2110: test zF, FLAG_%2
2111: j%1 near %%dont_take_jump
2112: GETWORD
2113: mov ezPC, edi
2114: DO_CYCLES
2115: NEXT
2116:
2117: ALIGN
2118: %%dont_take_jump:
2119: add zPC, 2 ; skip address
2120: DO_CYCLES
2121: NEXT
2122: %endmacro
2123:
2124: ; Jump to an relative address
2125: ; JR_N
2126: %macro JR_N 0
2127: GETDISP
2128: add zPC, di
2129: DO_CYCLES
2130: NEXT
2131: %endmacro
2132:
2133: ; Jump to an relative address, conditionally
2134: ; JR_cc_N nz,cc
2135: %macro JR_cc_N 2
2136: test zF, FLAG_%2
2137: j%1 near %%dont_take_jump
2138: GETDISP
2139: add zPC, di
2140: DO_EXTRA_CYCLES
2141: NEXT
2142:
2143: ALIGN
2144: %%dont_take_jump:
2145: inc zPC ; skip over the displacement
2146: DO_CYCLES
2147: NEXT
2148: %endmacro
2149:
2150: ; Jump to an absolute address (in a register)
2151: ; JP_RR addr16
2152: %macro JP_RR 1
2153: mov ezPC, ez%1
2154: DO_CYCLES
2155: NEXT
2156: %endmacro
2157:
2158: ; Decrease B, if non-zero, jump to a relative address
2159: ; DJNZ_N
2160: %macro DJNZ_N 0
2161: dec zB
2162: jz near %%dont_take_jump
2163: GETDISP
2164: add zPC, di
2165: DO_EXTRA_CYCLES
2166: NEXT
2167:
2168: ALIGN
2169: %%dont_take_jump:
2170: inc zPC ; skip over the displacement
2171: DO_CYCLES
2172: NEXT
2173: %endmacro
2174:
2175: ; Call an absolute address
2176: ; CALL_NN
2177: %macro CALL_NN 0
2178: GETWORD
2179: mov edx, ezPC ; write the PC
2180: dec zSP
2181: push edi
2182:
2183: xchg dl, dh
2184: mov edi, ezSP
2185: MEMWRITE
2186: dec zSP
2187: mov edx, ezPC
2188: mov edi, ezSP
2189: MEMWRITE
2190:
2191: pop ezPC ; get the new PC
2192: DO_CYCLES
2193: NEXT
2194: %endmacro
2195:
2196: ; Call an absolute address, conditionally
2197: ; CALL_cc_NN
2198: %macro CALL_cc_NN 2
2199: test zF, FLAG_%2
2200: j%1 near %%dont_take_jump
2201: GETWORD
2202: mov edx, ezPC ; write the PC
2203: push edi
2204:
2205: dec zSP
2206: xchg dl, dh
2207: mov edi, ezSP
2208: MEMWRITE
2209: dec zSP
2210: mov edx, ezPC
2211: mov edi, ezSP
2212: MEMWRITE
2213:
2214: pop ezPC ; get the new PC
2215: DO_CYCLES
2216: NEXT
2217:
2218: ALIGN
2219: %%dont_take_jump:
2220: add zPC, 2 ; skip address
2221: DO_CYCLES
2222: NEXT
2223: %endmacro
2224:
2225: ; Pop the PC
2226: ; RET
2227: %macro RET 0
2228: mov edi, ezSP
2229: MEMREAD
2230: inc zSP
2231: mov ezPC, edx
2232: mov edi, ezSP
2233: MEMREAD
2234: xchg dl, dh
2235: or ezPC, edx
2236: inc zSP
2237:
2238: xor dh, dh
2239: DO_CYCLES
2240: NEXT
2241: %endmacro
2242:
2243: ; Pop the PC, conditionally
2244: ; RET_cc
2245: %macro RET_cc 2
2246: test zF, FLAG_%2
2247: j%1 near %%dont_take_jump
2248: mov edi, ezSP
2249: MEMREAD
2250: inc zSP
2251: mov ezPC, edx
2252: mov edi, ezSP
2253: MEMREAD
2254: xchg dl, dh
2255: or ezPC, edx
2256: inc zSP
2257:
2258: xor dh, dh
2259: DO_CYCLES
2260: NEXT
2261:
2262: ALIGN
2263: %%dont_take_jump:
2264: DO_CYCLES
2265: NEXT
2266: %endmacro
2267:
2268: ; Pop the PC, restore IFF1, signal the BUS
2269: ; RETI
2270: %macro RETI 0
2271: mov edi, ezSP
2272: MEMREAD
2273: mov ezPC, edx
2274: inc zSP
2275: mov edi, ezSP
2276: MEMREAD
2277: xchg dl, dh
2278: or ezPC, edx
2279: inc zSP
2280:
2281: mov dl, [z80_IFF2]
2282: mov [z80_IFF1], dl
2283: call [z80_RetI] ; signal the user handler
2284:
2285: DO_CYCLES
2286: NEXT
2287: %endmacro
2288:
2289: ; Pop the PC, restore IFF1
2290: ; RETN
2291: %macro RETN 0
2292: mov edi, ezSP
2293: MEMREAD
2294: mov ezPC, edx
2295: inc zSP
2296: mov edi, ezSP
2297: MEMREAD
2298: xchg dl, dh
2299: or ezPC, edx
2300: inc zSP
2301:
2302: mov dl, [z80_IFF2]
2303: mov [z80_IFF1], dl
2304: DO_CYCLES
2305: NEXT
2306: %endmacro
2307:
2308: ; Call an absolute address
2309: ; RST addr8
2310: %macro RST 1
2311: dec zSP
2312: mov edx, ezPC ; write the PC
2313: xchg dl, dh
2314: mov edi, ezSP
2315: MEMWRITE
2316: dec zSP
2317: mov edx, ezPC
2318: mov edi, ezSP
2319: MEMWRITE
2320:
2321: mov ezPC, %1 ; get the new PC
2322: DO_CYCLES
2323: NEXT
2324: %endmacro
2325:
2326: ; Out R to R*256+N
2327: ; OUT_N_R src8
2328: %macro OUT_N_R 1
2329: GETBYTE
2330: mov dh, z%1
2331: mov edi, edx
2332: mov dl, z%1
2333: IOWRITE
2334: DO_CYCLES
2335: NEXT
2336: %endmacro
2337:
2338: ; In from R*256+N, into R
2339: ; IN_R_N dest8
2340: %macro IN_R_N 1
2341: GETBYTE
2342: mov dh, z%1
2343: mov edi, edx
2344: IOREAD
2345: mov z%1, dl
2346: DO_CYCLES
2347: NEXT
2348: %endmacro
2349:
2350: ; In from BC
2351: ; IN_R dest8
2352: %macro IN_R 1
2353: mov edi, ezBC
2354: IOREAD
2355: mov dh, zF
2356: and dh, FLAG_C ; keep the old carry
2357: mov z%1, dl
2358: test dl, dl ; other flags come from the result
2359: lahf
2360: and zF, FLAG_S|FLAG_Z|FLAG_P
2361: or zF, dh
2362: %ifdef EMULATE_BITS_3_5
2363: mov [z80_flag35], dl
2364: %endif
2365: xor dh, dh
2366:
2367: DO_CYCLES
2368: NEXT
2369: %endmacro
2370:
2371: ; In from BC, ignore result
2372: ; IN_F
2373: %macro IN_F 0
2374: mov edi, ezBC
2375: IOREAD
2376: mov dh, zF
2377: and dh, FLAG_C ; keep the old carry
2378: test dl, dl ; other flags come from the result
2379: lahf
2380: and zF, FLAG_S|FLAG_Z|FLAG_P
2381: or zF, dh
2382: %ifdef EMULATE_BITS_3_5
2383: mov [z80_flag35], dl
2384: %endif
2385: xor dh, dh
2386:
2387: DO_CYCLES
2388: NEXT
2389: %endmacro
2390:
2391: ; Out to BC
2392: ; OUT_R src8
2393: %macro OUT_R 1
2394: mov edi, ezBC
2395: mov dl, z%1
2396: IOWRITE
2397: DO_CYCLES
2398: NEXT
2399: %endmacro
2400:
2401: ; Out zero to BC
2402: ; OUT_0
2403: %macro OUT_0 0
2404: mov edi, ezBC
2405: xor dl, dl
2406: IOWRITE
2407: DO_CYCLES
2408: NEXT
2409: %endmacro
2410:
2411: ; In from BC into (HL), increase HL, decrease B
2412: %macro INI 0
2413: ; FIXME - Parity flag is not emulated
2414: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2415:
2416: IOREAD ; read from the port
2417: mov edi, ezHL
2418: %ifdef EMULATE_WEIRD_STUFF
2419: push edx ; preserve the value
2420: %endif
2421: MEMWRITE ; write to (HL)
2422: %ifdef EMULATE_WEIRD_STUFF
2423: pop edx
2424: %endif
2425:
2426: inc zHL ; increase HL
2427: dec zB ; decrease B
2428: %ifdef EMULATE_BITS_3_5
2429: mov [z80_flag35], zB
2430: %endif
2431:
2432: lahf
2433: and zF, FLAG_S|FLAG_Z|FLAG_P
2434:
2435: ; This is a prime example of the weirdness of the Z80...
2436: %ifdef EMULATE_WEIRD_STUFF
2437: mov dh, zC
2438: inc dh
2439: add dh, dl
2440: jnc %%no_carry
2441: or zF, FLAG_H|FLAG_C
2442: %%no_carry:
2443: shr dl, 6
2444: and edx, FLAG_N
2445: or zF, dl
2446: %endif
2447: DO_CYCLES
2448: NEXT
2449: %endmacro
2450:
2451: ; In from BC into (HL), decrease HL, decrease B
2452: %macro IND 0
2453: ; FIXME - Parity flag is not emulated
2454: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2455:
2456: IOREAD ; read from the port
2457: mov edi, ezHL
2458: %ifdef EMULATE_WEIRD_STUFF
2459: push edx ; preserve the value
2460: %endif
2461: MEMWRITE ; write to (HL)
2462: %ifdef EMULATE_WEIRD_STUFF
2463: pop edx
2464: %endif
2465:
2466: dec zHL ; increase HL
2467: dec zB ; decrease B
2468: %ifdef EMULATE_BITS_3_5
2469: mov [z80_flag35], zB
2470: %endif
2471:
2472: lahf
2473: and zF, FLAG_S|FLAG_Z|FLAG_P
2474:
2475: ; This is a prime example of the weirdness of the Z80...
2476: %ifdef EMULATE_WEIRD_STUFF
2477: mov dh, zC
2478: dec dh
2479: add dh, dl
2480: jnc %%no_carry
2481: or zF, FLAG_H|FLAG_C
2482: %%no_carry:
2483: shr dl, 6
2484: and edx, FLAG_N
2485: or zF, dl
2486: %endif
2487: DO_CYCLES
2488: NEXT
2489: %endmacro
2490:
2491: ; In from BC into (HL), increase HL, decrease B, repeat
2492: %macro INIR 0
2493: ; FIXME - Parity flag is not emulated
2494: %%inir_loop:
2495: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2496:
2497: IOREAD ; read from the port
2498: mov edi, ezHL
2499: %ifdef EMULATE_WEIRD_STUFF
2500: push edx ; preserve the value
2501: %endif
2502: MEMWRITE ; write to (HL)
2503: %ifdef EMULATE_WEIRD_STUFF
2504: pop edx
2505: %endif
2506:
2507: inc zHL ; increase HL
2508: dec zB ; decrease B
2509: jz %%inir_zero
2510:
2511: sub [z80_ICount], dword extra_cycles
2512: ja near %%inir_loop ; repeat while cycles left and B>0
2513:
2514: ; out of cycles, but operation not finished
2515: %ifdef EMULATE_BITS_3_5
2516: mov [z80_flag35], zB
2517: %endif
2518:
2519: mov zF, zB
2520: and zF, FLAG_S
2521:
2522: ; This is a prime example of the weirdness of the Z80...
2523: %ifdef EMULATE_WEIRD_STUFF
2524: mov dh, zC
2525: inc dh
2526: add dh, dl
2527: jnc %%no_carry
2528: or zF, FLAG_H|FLAG_C
2529: %%no_carry:
2530: shr dl, 6
2531: and edx, FLAG_N
2532: or zF, dl
2533: %endif
2534: sub zPC, 2 ; rewind to instruction start
2535: EXIT
2536:
2537: ; B=0
2538: %%inir_zero:
2539: mov zF, FLAG_Z|FLAG_P
2540: %ifdef EMULATE_BITS_3_5
2541: mov [z80_flag35], zF
2542: %endif
2543:
2544: ; This is a prime example of the weirdness of the Z80...
2545: %ifdef EMULATE_WEIRD_STUFF
2546: mov dh, zC
2547: inc dh
2548: add dh, dl
2549: jnc %%no_carry2
2550: or zF, FLAG_H|FLAG_C
2551: %%no_carry2:
2552: shr dl, 6
2553: and edx, FLAG_N
2554: or zF, dl
2555: %endif
2556: DO_CYCLES
2557: NEXT
2558: %endmacro
2559:
2560: ; In from BC into (HL), decrease HL, decrease B, repeat
2561: %macro INDR 0
2562: ; FIXME - Parity flag is not emulated
2563: %%indr_loop:
2564: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2565:
2566: IOREAD ; read from the port
2567: mov edi, ezHL
2568: %ifdef EMULATE_WEIRD_STUFF
2569: push edx ; preserve the value
2570: %endif
2571: MEMWRITE ; write to (HL)
2572: %ifdef EMULATE_WEIRD_STUFF
2573: pop edx
2574: %endif
2575:
2576: dec zHL ; decrease HL
2577: dec zB ; decrease B
2578: jz %%indr_zero
2579:
2580: sub [z80_ICount], dword extra_cycles
2581: ja near %%indr_loop ; repeat while cycles left and B>0
2582:
2583: ; out of cycles, but operation not finished
2584: %ifdef EMULATE_BITS_3_5
2585: mov [z80_flag35], zB
2586: %endif
2587:
2588: mov zF, zB
2589: and zF, FLAG_S
2590:
2591: ; This is a prime example of the weirdness of the Z80...
2592: %ifdef EMULATE_WEIRD_STUFF
2593: mov dh, zC
2594: inc dh
2595: add dh, dl
2596: jnc %%no_carry
2597: or zF, FLAG_H|FLAG_C
2598: %%no_carry:
2599: shr dl, 6
2600: and edx, FLAG_N
2601: or zF, dl
2602: %endif
2603: sub zPC, 2 ; rewind to instruction start
2604: EXIT
2605:
2606: ; B=0
2607: %%indr_zero:
2608: mov zF, FLAG_Z|FLAG_P
2609: %ifdef EMULATE_BITS_3_5
2610: mov [z80_flag35], zF
2611: %endif
2612:
2613: ; This is a prime example of the weirdness of the Z80...
2614: %ifdef EMULATE_WEIRD_STUFF
2615: mov dh, zC
2616: inc dh
2617: add dh, dl
2618: jnc %%no_carry2
2619: or zF, FLAG_H|FLAG_C
2620: %%no_carry2:
2621: shr dl, 6
2622: and edx, FLAG_N
2623: or zF, dl
2624: %endif
2625: DO_CYCLES
2626: NEXT
2627: %endmacro
2628:
2629: ; Out from (HL) into BC, increase HL, decrease B
2630: %macro OUTI 0
2631: ; FIXME - Parity flag is not emulated
2632: mov edi, ezHL
2633:
2634: MEMREAD ; read from (HL)
2635: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2636: %ifdef EMULATE_WEIRD_STUFF
2637: push edx ; preserve the value
2638: %endif
2639: IOWRITE ; write to the port
2640: %ifdef EMULATE_WEIRD_STUFF
2641: pop edx
2642: %endif
2643:
2644: inc zHL ; increase HL
2645: dec zB ; decrease B
2646: %ifdef EMULATE_BITS_3_5
2647: mov [z80_flag35], zB
2648: %endif
2649:
2650: lahf
2651: and zF, FLAG_S|FLAG_Z|FLAG_P
2652:
2653: ; This is a prime example of the weirdness of the Z80...
2654: %ifdef EMULATE_WEIRD_STUFF
2655: mov dh, zC
2656: inc dh
2657: add dh, dl
2658: jnc %%no_carry
2659: or zF, FLAG_H|FLAG_C
2660: %%no_carry:
2661: shr dl, 6
2662: and edx, FLAG_N
2663: or zF, dl
2664: %endif
2665: DO_CYCLES
2666: NEXT
2667: %endmacro
2668:
2669: ; Out from (HL) into BC, decrease HL, decrease B
2670: %macro OUTD 0
2671: ; FIXME - Parity flag is not emulated
2672: mov edi, ezHL
2673:
2674: MEMREAD ; read from (HL)
2675: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2676: %ifdef EMULATE_WEIRD_STUFF
2677: push edx ; preserve the value
2678: %endif
2679: IOWRITE ; write to the port
2680: %ifdef EMULATE_WEIRD_STUFF
2681: pop edx
2682: %endif
2683:
2684: dec zHL ; decrease HL
2685: dec zB ; decrease B
2686: %ifdef EMULATE_BITS_3_5
2687: mov [z80_flag35], zB
2688: %endif
2689:
2690: lahf
2691: and zF, FLAG_S|FLAG_Z|FLAG_P
2692:
2693: ; This is a prime example of the weirdness of the Z80...
2694: %ifdef EMULATE_WEIRD_STUFF
2695: mov dh, zC
2696: inc dh
2697: add dh, dl
2698: jnc %%no_carry
2699: or zF, FLAG_H|FLAG_C
2700: %%no_carry:
2701: shr dl, 6
2702: and edx, FLAG_N
2703: or zF, dl
2704: %endif
2705: DO_CYCLES
2706: NEXT
2707: %endmacro
2708:
2709: ; Out from (HL) into BC, increase HL, decrease B, repeat
2710: %macro OTIR 0
2711: %%otir_loop:
2712: mov edi, ezHL
2713: MEMREAD
2714: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2715: %ifdef EMULATE_WEIRD_STUFF
2716: push edx ; preserve the value
2717: %endif
2718: IOWRITE
2719: %ifdef EMULATE_WEIRD_STUFF
2720: pop edx
2721: %endif
2722:
2723: inc zHL
2724: dec zB
2725: jz %%otir_zero
2726:
2727: %ifdef EMULATE_R_REGISTER
2728: inc zR
2729: %endif
2730: sub [z80_ICount], dword extra_cycles
2731: ja near %%otir_loop
2732:
2733: ; out of cycles, but not finished
2734: %ifdef EMULATE_BITS_3_5
2735: mov [z80_flag35], zB
2736: %endif
2737:
2738: mov zF, zB
2739: and zF, FLAG_S
2740:
2741: %ifdef EMULATE_WEIRD_STUFF
2742: mov dh, zC
2743: inc dh
2744: add dh, dl
2745: jnc %%otir_nocarry
2746: or zF, FLAG_H|FLAG_C
2747: %%otir_nocarry:
2748: shr dl, 6
2749: and edx, FLAG_N
2750: or zF, dl
2751: %endif
2752: sub zPC, 2 ; rewind to instruction start
2753: EXIT
2754:
2755: %%otir_zero:
2756: mov zF, FLAG_Z|FLAG_P
2757: %ifdef EMULATE_BITS_3_5
2758: mov [z80_flag35], zF
2759: %endif
2760: %ifdef EMULATE_WEIRD_STUFF
2761: mov dh, zC
2762: inc dh
2763: add dh, dl
2764: jnc %%otir_nocarry2
2765: or zF, FLAG_H|FLAG_C
2766: %%otir_nocarry2:
2767: shr dl, 6
2768: and edx, FLAG_N
2769: or zF, dl
2770: %endif
2771: DO_CYCLES
2772: NEXT
2773: %endmacro
2774:
2775: ; Out from (HL) into BC, decrease HL, decrease B, repeat
2776: %macro OTDR 0
2777: %%otdr_loop:
2778: mov edi, ezHL
2779: MEMREAD
2780: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2781: %ifdef EMULATE_WEIRD_STUFF
2782: push edx ; preserve the value
2783: %endif
2784: IOWRITE
2785: %ifdef EMULATE_WEIRD_STUFF
2786: pop edx
2787: %endif
2788:
2789: dec zHL
2790: dec zB
2791: jz %%otdr_zero
2792:
2793: %ifdef EMULATE_R_REGISTER
2794: inc zR
2795: %endif
2796: sub [z80_ICount], dword extra_cycles
2797: ja near %%otdr_loop
2798:
2799: ; out of cycles, but not finished
2800: %ifdef EMULATE_BITS_3_5
2801: mov [z80_flag35], zB
2802: %endif
2803:
2804: mov zF, zB
2805: and zF, FLAG_S
2806:
2807: %ifdef EMULATE_WEIRD_STUFF
2808: mov dh, zC
2809: inc dh
2810: add dh, dl
2811: jnc %%otdr_nocarry
2812: or zF, FLAG_H|FLAG_C
2813: %%otdr_nocarry:
2814: shr dl, 6
2815: and edx, FLAG_N
2816: or zF, dl
2817: %endif
2818: sub zPC, 2 ; rewind to instruction start
2819: EXIT
2820:
2821: %%otdr_zero:
2822: mov zF, FLAG_Z|FLAG_P
2823: %ifdef EMULATE_BITS_3_5
2824: mov [z80_flag35], zF
2825: %endif
2826: %ifdef EMULATE_WEIRD_STUFF
2827: mov dh, zC
2828: inc dh
2829: add dh, dl
2830: jnc %%otdr_nocarry2
2831: or zF, FLAG_H|FLAG_C
2832: %%otdr_nocarry2:
2833: shr dl, 6
2834: and edx, FLAG_N
2835: or zF, dl
2836: %endif
2837: DO_CYCLES
2838: NEXT
2839: %endmacro
2840:
2841: ; BCD adjust
2842: %macro DAA 0
2843: test zF, FLAG_H
2844: jnz %%daa_h_set
2845: and eax, 03ffh
2846: mov ax, [DAA_Table + eax*2]
2847: %ifdef EMULATE_BITS_3_5
2848: mov [z80_flag35], zF
2849: %endif
2850: DO_CYCLES
2851: NEXT
2852:
2853: %%daa_h_set:
2854: and eax, 03ffh
2855: mov ax, [DAA_Table + eax*2 + 4*512]
2856: %ifdef EMULATE_BITS_3_5
2857: mov [z80_flag35], zF
2858: %endif
2859: DO_CYCLES
2860: NEXT
2861: %endmacro
2862:
2863: ; Complement A
2864: %macro CPL 0
2865: not zA
2866: or zF, FLAG_H|FLAG_N
2867: %ifdef EMULATE_BITS_3_5
2868: mov [z80_flag35], zA
2869: %endif
2870: DO_CYCLES
2871: NEXT
2872: %endmacro
2873:
2874: ; Negate A
2875: %macro NEG 0
2876: neg zA
2877: lahf
2878: %ifdef EMULATE_BITS_3_5
2879: mov [z80_flag35], zA
2880: %endif
2881: jo %%neg_overflow
2882: and zF, ~FLAG_P
2883: DO_CYCLES
2884: NEXT
2885:
2886: %%neg_overflow:
2887: or zF, FLAG_P
2888: DO_CYCLES
2889: NEXT
2890: %endmacro
2891:
2892: ; Set carry flag
2893: %macro SCF 0
2894: and zF, FLAG_S|FLAG_Z|FLAG_P
2895: or zF, FLAG_C
2896: %ifdef EMULATE_BITS_3_5
2897: mov [z80_flag35], zA
2898: %endif
2899: DO_CYCLES
2900: NEXT
2901: %endmacro
2902:
2903: ; Complement carry flag
2904: %macro CCF 0
2905: test zF, FLAG_C
2906: jz %%set_carry
2907: and zF, FLAG_S|FLAG_Z|FLAG_P
2908: or zF, FLAG_H
2909: %ifdef EMULATE_BITS_3_5
2910: mov [z80_flag35], zA
2911: %endif
2912: DO_CYCLES
2913: NEXT
2914:
2915: %%set_carry:
2916: SCF
2917: %endmacro
2918:
2919: ; No operation
2920: %macro NOP 0
2921: DO_CYCLES
2922: NEXT
2923: %endmacro
2924:
2925: ; Halt the processor
2926: %macro HALT 0
2927: and [z80_ICount], dword 3
2928: sub [z80_ICount], dword 4
2929: mov [z80_halted], byte 1
2930: EXIT
2931: %endmacro
2932:
2933: ; Enable interrupts
2934: %macro EI 0
2935: mov dl, FLAG_P ; set the P/V bit, for use in "LD I,A" etc
2936: mov [z80_IFF1], dl
2937: mov [z80_IFF2], dl
2938:
2939: ; force the next instruction to be executed, regardless of ICount
2940: ; then force an IRQ check after it.
2941: mov [z80_afterEI], byte 1
2942: push eax
2943: mov eax, [z80_ICount] ; set ICount to zero, so it will terminate
2944: mov [z80_TempICount], eax ; after the next instruction.
2945: mov [z80_ICount], dword 1 ; we can then pick it up again and carry on.
2946: pop eax
2947: NEXT
2948: %endmacro
2949:
2950: ; Disable interrupts
2951: %macro DI 0
2952: xor edx, edx
2953: mov [z80_IFF1], dl
2954: mov [z80_IFF2], dl
2955: DO_CYCLES
2956: NEXT
2957: %endmacro
2958:
2959: ; Set interrupt mode
2960: %macro IM 1
2961: mov [z80_IM], byte %1
2962: DO_CYCLES
2963: NEXT
2964: %endmacro
2965:
2966: ;----------------------------------------------------------------------------;
2967: ; Bring in the opcodes...
2968: %include 'raze.inc'
2969: ;----------------------------------------------------------------------------;
2970:
2971: ;----------------------------------------------------------------------------;
2972: ; Support functions:
2973:
2974: DEF op, cb, 0, 0
2975: %ifdef EMULATE_R_REGISTER
2976: inc zR
2977: %endif
2978: GETBYTE
2979: jmp [CBTable+edx*4]
2980:
2981: DEF op, ed, 0, 0
2982: %ifdef EMULATE_R_REGISTER
2983: inc zR
2984: %endif
2985: GETBYTE
2986: jmp [EDTable+edx*4]
2987:
2988: DEF op, dd, 0, 0
2989: %ifdef EMULATE_R_REGISTER
2990: inc zR
2991: %endif
2992: GETBYTE
2993: jmp [DDTable+edx*4]
2994:
2995: DEF op, fd, 0, 0
2996: %ifdef EMULATE_R_REGISTER
2997: inc zR
2998: %endif
2999: GETBYTE
3000: jmp [FDTable+edx*4]
3001:
3002: DEF dd, cb, 0, 0
3003: %ifdef EMULATE_R_REGISTER
3004: inc zR
3005: %endif
3006: GETDISP
3007: add di, zIX
3008: push edi
3009: GETBYTE
3010: pop edi
3011: jmp [DDCBTable+edx*4]
3012:
3013: DEF fd, cb, 0, 0
3014: %ifdef EMULATE_R_REGISTER
3015: inc zR
3016: %endif
3017: GETDISP
3018: add di, zIY
3019: push edi
3020: GETBYTE
3021: pop edi
3022: jmp [DDCBTable+edx*4]
3023:
3024: DEF ed, xx, 8, 0
3025: %ifdef EMULATE_R_REGISTER
3026: inc zR
3027: %endif
3028: DO_CYCLES
3029: NEXT
3030:
3031: DEF dd, xx, 4, 0
3032: dec zPC
3033: DO_CYCLES
3034: NEXT
3035:
3036: DEF fd, xx, 0, 0
3037: dec zPC
3038: DO_CYCLES
3039: NEXT
3040:
3041: ; called when out-of-cycles
3042: z80_finish:
3043: cmp [z80_afterEI], byte 1 ; test for the post-EI behaviour
3044: jne near really_finish
3045: push eax
3046: mov eax, [z80_TempICount]
3047: mov [z80_ICount], eax
3048: mov [z80_afterEI], byte 0
3049: pop eax
3050: CHECK_IRQ
3051: sub dword [z80_ICount], 4 ; subtract EI's cycles
3052: jbe near z80_finish
3053: NEXT
3054:
3055: really_finish:
3056: ; merge bits 3 and 5 of the flags into the regs
3057: and zF, ~(FLAG_3|FLAG_5)
3058: mov dl, [z80_flag35]
3059: and dl, FLAG_3|FLAG_5
3060: or zF, dl
3061:
3062: mov [z80_AF], ezAF
3063: mov [z80_HL], ezHL
3064: mov [z80_BC], ezBC
3065: mov [z80_PC], ezPC
3066: mov [z80_R], zR
3067: pop ebp
3068: pop edi
3069: pop esi
3070: pop ebx
3071: mov eax, [z80_Initial_ICount]
3072: sub eax, [z80_ICount]
3073: ret
3074:
3075: z80_default_in:
3076: z80_default_read:
3077: mov eax, 0ffh
3078: ret
3079:
3080: z80_default_out:
3081: z80_default_write:
3082: z80_default_reti:
3083: z80_default_fetch_callback:
3084: ret
3085:
3086: ; called to look up a read handler
3087: ; address is on the stack
3088: read_dispatcher:
3089: mov eax, [esp+4]
3090: mov edx, _read_handlers
3091: rd_find:
3092: add edx, 16
3093: cmp [edx-16], eax
3094: ja rd_find
3095: cmp [edx-12], eax
3096: jb rd_find
3097:
3098: cmp [edx-8], dword 1
3099: je rd_handler
3100:
3101: add eax, [edx-4]
3102: movzx eax, byte [eax]
3103: ret
3104:
3105: rd_handler:
3106: jmp [edx-4] ; call the GCC function
3107:
3108: ; called to look up a write handler
3109: ; address+value are on the stack
3110: write_dispatcher:
3111: mov eax, [esp+4]
3112: mov edx, _write_handlers
3113: wd_find:
3114: add edx, 16
3115: cmp [edx-16], eax
3116: ja wd_find
3117: cmp [edx-12], eax
3118: jb wd_find
3119:
3120: cmp [edx-8], dword 1
3121: je wd_handler
3122:
3123: add eax, [edx-4]
3124: mov ecx, [esp+8]
3125: mov [eax], cl
3126: ret
3127:
3128: wd_handler:
3129: jmp [edx-4] ; call the GCC function
3130:
3131: ; int z80_emulate(int cycles)
3132: ; Emulate for 'cycles' T-states,
3133: ; Returns the number of cycles actually emulated.
3134: global z80_emulate
3135: z80_emulate:
3136: mov eax, [esp+4]
3137: push ebx
3138: push esi
3139: push edi
3140: push ebp
3141:
3142: add eax, [z80_Extra_Cycles]
3143: mov [z80_ICount], eax
3144: mov [z80_Initial_ICount], eax
3145: xor edx, edx
3146: xor edi, edi
3147: mov [z80_Extra_Cycles], edx
3148: mov [z80_afterEI], dl
3149: mov ezAF, [z80_AF]
3150: mov ezHL, [z80_HL]
3151: mov ezBC, [z80_BC]
3152: mov ezPC, [z80_PC]
3153: mov zR, [z80_R]
3154: mov [z80_flag35], zF ; take out bits 3/5
3155: cmp [z80_halted], byte 0
3156: je not_halted
3157: and [z80_ICount], dword 3 ; If we're halted, just skip it all.
3158: sub [z80_ICount], dword 4
3159: EXIT
3160: not_halted:
3161: NEXT
3162:
3163: ; void z80_reset(void)
3164: ; Resets the Z80.
3165: global z80_reset
3166: z80_reset:
3167: push edi
3168: xor eax, eax ; just zero it all
3169: mov edi, context_start
3170: mov ecx, (registers_end - context_start)
3171: rep stosb
3172: pop edi
3173: mov [z80_IX], word 0ffffh
3174: mov [z80_IY], word 0ffffh
3175: mov [z80_AF], word 04000h
3176: ret
3177:
3178: ; void z80_raise_IRQ(UBYTE vector)
3179: ; Causes an interrupt with the given vector.
3180: ; In IM 0, the vector has to be an RST opcode.
3181: ; If interrupts are disabled, the interrupt will still happen as long as
3182: ; the IRQ line stays raised.
3183: global z80_raise_IRQ
3184: z80_raise_IRQ:
3185: mov [z80_IRQLine], byte 1
3186: mov eax, [esp+4]
3187: mov [z80_IRQVector], al
3188:
3189: xor edx, edx
3190: push ebx
3191: push esi
3192: push edi
3193: push ebp
3194: CALLGCC_END ; grab our Z80 regs
3195:
3196: CHECK_IRQ
3197:
3198: CALLGCC_START
3199: pop ebp
3200: pop edi
3201: pop esi
3202: pop ebx
3203: ret
3204:
3205: ; void z80_lower_IRQ(void)
3206: ; Lowers the IRQ line.
3207: global z80_lower_IRQ
3208: z80_lower_IRQ:
3209: mov [z80_IRQLine], byte 0
3210: ret
3211:
3212: ; void z80_cause_NMI(void)
3213: ; Causes a non-maskable interrupt.
3214: ; This will always be accepted.
3215: ; There is no raise/lower functions, as the NMI is edge-triggered.
3216: global z80_cause_NMI
3217: z80_cause_NMI:
3218: xor edx, edx
3219: push ebx
3220: push esi
3221: push edi
3222: push ebp
3223: CALLGCC_END ; grab our Z80 regs
3224:
3225: ; disable interrupts
3226: mov [z80_IFF1], byte 0
3227:
3228: ; take up 11 T-states
3229: add [z80_Extra_Cycles], dword 11
3230: %ifdef EMULATE_R_REGISTER
3231: inc zR
3232: %endif
3233:
3234: mov [z80_halted], byte 0 ; Un-HALT us.
3235:
3236: mov edx, ezPC ; write the PC
3237: dec zSP
3238:
3239: xchg dl, dh
3240: mov edi, ezSP
3241: MEMWRITE
3242: dec zSP
3243: mov edx, ezPC
3244: mov edi, ezSP
3245: MEMWRITE
3246:
3247: mov ezPC, 66h ; set the new PC
3248:
3249: CALLGCC_START
3250: pop ebp
3251: pop edi
3252: pop esi
3253: pop ebx
3254: ret
3255:
3256: ; int z80_get_context_size(void)
3257: ; Returns the size of the context, in bytes
3258: global z80_get_context_size
3259: z80_get_context_size:
3260: mov eax, (context_end - context_start) + 4 ; +4 for a safety buffer
3261: ret
3262:
3263:
3264: ; void z80_set_context(void *context)
3265: ; Copy the given context to the current Z80.
3266: global z80_set_context
3267: z80_set_context:
3268: push esi
3269: push edi
3270: mov ecx, (context_end - context_start) / 4
3271: mov esi, [esp+12]
3272: mov edi, context_start
3273: rep movsd
3274: pop edi
3275: pop esi
3276: ret
3277:
3278: ; void z80_get_context(void *context)
3279: ; Copy the current Z80 to the given context.
3280: global z80_get_context
3281: z80_get_context:
3282: push esi
3283: push edi
3284: mov ecx, (context_end - context_start) / 4
3285: mov edi, [esp+12]
3286: mov esi, context_start
3287: rep movsd
3288: pop edi
3289: pop esi
3290: ret
3291:
3292: ; int z80_get_cycles_elapsed(void)
3293: ; Returns the number of cycles emulated since z80_emulate was called.
3294: global z80_get_cycles_elapsed
3295: z80_get_cycles_elapsed:
3296: mov eax, [z80_Initial_ICount]
3297: sub eax, [z80_ICount]
3298: cmp [z80_afterEI], byte 0
3299: je z80_gcd_fin
3300: sub eax, [z80_TempICount]
3301: z80_gcd_fin:
3302: ret
3303:
3304: ; void z80_stop_emulating(void)
3305: ; Stops the emulation dead. (waits for the current instruction to finish
3306: ; first though).
3307: ; The return value from z80_execute will obviously be lower than expected.
3308: global z80_stop_emulating
3309: z80_stop_emulating:
3310: mov eax, [z80_ICount]
3311: sub [z80_Initial_ICount], eax
3312: cmp [z80_afterEI], byte 0
3313: je z80_se_fin
3314: mov ecx, [z80_TempICount]
3315: sub [z80_Initial_ICount], ecx
3316: z80_se_fin:
3317: mov [z80_ICount], dword 0
3318: mov [z80_TempICount], dword 0
3319: ret
3320:
3321: ; void z80_skip_idle(void)
3322: ; Stops the emulation dead. (waits for the current instruction to finish
3323: ; first though).
3324: ; The return value from z80_execute will appear as though it had executed
3325: ; all the instructions like normal.
3326: global z80_skip_idle
3327: z80_skip_idle:
3328: mov [z80_ICount], dword 0
3329: mov [z80_TempICount], dword 0
3330: ret
3331:
3332: ; void z80_do_wait_states(int n)
3333: ; Halts the CPU temporarily, to execute 'n' memory wait states.
3334: global z80_do_wait_states
3335: z80_do_wait_states:
3336: add [z80_Initial_ICount], eax
3337: ret
3338:
3339: ; UWORD z80_get_reg(z80_register reg)
3340: ; Return the value of the specified register.
3341: global z80_get_reg
3342: z80_get_reg:
3343: mov ecx, [esp+4]
3344: cmp ecx, Z80_REG_HL2
3345: mov eax, [context_start + ecx*4]
3346: jbe getreg_simple
3347:
3348: cmp ecx, Z80_REG_IFF1
3349: mov al, [z80_IFF1]
3350: je getreg_boolean
3351:
3352: cmp ecx, Z80_REG_IFF2
3353: mov al, [z80_IFF2]
3354: je getreg_boolean
3355:
3356: cmp ecx, Z80_REG_IRQLine
3357: mov al, [z80_IRQLine]
3358: je getreg_boolean
3359:
3360: cmp ecx, Z80_REG_Halted
3361: mov al, [z80_halted]
3362: je getreg_boolean
3363:
3364: cmp ecx, Z80_REG_IM
3365: movzx eax, byte [z80_IM]
3366: je getreg_finish
3367:
3368: cmp ecx, Z80_REG_IRQVector
3369: movzx eax, byte [z80_IRQVector]
3370: je getreg_finish
3371:
3372: ; construct IR
3373: mov eax, [z80_R]
3374: and eax, 7fh
3375: mov edx, [z80_R2]
3376: and edx, 80h
3377: or eax, edx
3378: mov ah, byte [z80_I]
3379: ret
3380:
3381: getreg_simple:
3382: cmp ecx, Z80_REG_AF
3383: je getreg_swap
3384: cmp ecx, Z80_REG_AF2
3385: je getreg_swap
3386: getreg_finish:
3387: ret
3388: getreg_swap:
3389: xchg al, ah ; swap A and F
3390: ret
3391:
3392: getreg_boolean:
3393: and eax, 0ffh
3394: jz getreg_finish
3395: mov al, 1
3396: ret
3397:
3398: ; void z80_set_reg(z80_register reg, UWORD value)
3399: ; Set the specified register to a new value.
3400: global z80_set_reg
3401: z80_set_reg:
3402: mov ecx, [esp+4]
3403: mov eax, [esp+8]
3404: and eax, 0ffffh
3405: cmp ecx, Z80_REG_HL2
3406: jbe setreg_simple
3407:
3408: cmp ecx, Z80_REG_IFF1
3409: lea edx, [z80_IFF1]
3410: jbe setreg_boolean
3411:
3412: cmp ecx, Z80_REG_IFF2
3413: lea edx, [z80_IFF2]
3414: jbe setreg_boolean
3415:
3416: cmp ecx, Z80_REG_IRQLine
3417: lea edx, [z80_IRQLine]
3418: je setreg_boolean
3419:
3420: cmp ecx, Z80_REG_Halted
3421: lea edx, [z80_halted]
3422: je setreg_boolean
3423:
3424: cmp ecx, Z80_REG_IM
3425: lea edx, [z80_IM]
3426: je setreg_value
3427:
3428: cmp ecx, Z80_REG_IRQVector
3429: lea edx, [z80_IRQVector]
3430: je setreg_value
3431:
3432: ; deconstruct IR
3433: mov [z80_I], ah
3434: mov [z80_R2], eax
3435: mov [z80_R], eax
3436: ret
3437:
3438: setreg_simple:
3439: cmp ecx, Z80_REG_AF
3440: je setreg_swap
3441: cmp ecx, Z80_REG_AF2
3442: je setreg_swap
3443: setreg_finish:
3444: mov [context_start + ecx*4], eax
3445: ret
3446: setreg_swap:
3447: xchg al, ah ; swap A and F
3448: mov [context_start + ecx*4], eax
3449: ret
3450:
3451: setreg_boolean:
3452: test eax, eax
3453: jz setreg_value
3454: mov al, FLAG_P
3455:
3456: setreg_value:
3457: mov [edx], al
3458: ret
3459:
3460: ; void z80_init_memmap(void)
3461: ; Reset the current memory map
3462: global z80_init_memmap
3463: z80_init_memmap:
3464: mov [z80_In], dword z80_default_in
3465: mov [z80_Out], dword z80_default_out
3466: mov [z80_RetI], dword z80_default_reti
3467: mov [z80_Fetch_Callback], dword z80_default_fetch_callback
3468:
3469: push edi ; clear the memory handlers
3470: mov eax, -1
3471: mov ecx, MAX_MEM_HANDLERS*4
3472: mov edi, _read_handlers
3473: rep stosd
3474: mov ecx, MAX_MEM_HANDLERS*4
3475: mov edi, _write_handlers
3476: rep stosd
3477:
3478: ; reset the read table
3479: mov edi, z80_Read
3480: mov ecx, 100h
3481: clear_read:
3482: mov [edi], dword z80_default_read
3483: add edi, 8
3484: loop clear_read
3485:
3486: ; reset the write table
3487: mov edi, z80_Write
3488: mov ecx, 100h
3489: clear_write:
3490: mov [edi], dword z80_default_write
3491: add edi, 8
3492: loop clear_write
3493:
3494: pop edi
3495: ret
3496:
3497: ; void z80_end_memmap(void)
3498: ; Finishes the current memory map
3499: global z80_end_memmap
3500: z80_end_memmap:
3501: ; put the entry at the end of the read table
3502: mov edx, _read_handlers
3503: er_find:
3504: add edx, 16
3505: cmp [edx-16], dword (-1)
3506: jne er_find
3507: sub edx, 16
3508:
3509: ; put it in there
3510: mov [edx], dword 0
3511: mov [edx+4], dword 0ffffh
3512: mov [edx+8], dword 0
3513: mov [edx+12], dword z80_default_read
3514:
3515: ; put the entry at the end of the write table
3516: mov edx, _write_handlers
3517: ew_find:
3518: add edx, 16
3519: cmp [edx-16], dword (-1)
3520: jne ew_find
3521: sub edx, 16
3522:
3523: ; put it in there
3524: mov [edx], dword 0
3525: mov [edx+4], dword 0ffffh
3526: mov [edx+8], dword 0
3527: mov [edx+12], dword z80_default_write
3528: ret
3529:
3530: ; void z80_map_fetch(UWORD start, UWORD end, UBYTE *memory)
3531: ; Set the given area for op-code fetching
3532: ; start/end = the area it covers
3533: ; memory = the ROM/RAM to read from
3534: global z80_map_fetch
3535: z80_map_fetch:
3536: push ebx
3537: mov eax, [esp+8]
3538: mov ebx, [esp+12]
3539: mov ecx, [esp+16]
3540: and eax, 0ffffh
3541: and ebx, 0ffffh
3542: sub ecx, eax
3543:
3544: mf_loop:
3545: ; if there's no area left inbetween, stop now.
3546: mov edx, eax
3547: shr edx, 8
3548:
3549: cmp eax, ebx
3550: ja mf_finish
3551:
3552: mov [z80_Fetch+edx*4], ecx
3553: add eax, 0100h
3554: jmp mf_loop
3555:
3556: mf_finish:
3557: pop ebx
3558: ret
3559:
3560: ; void z80_map_read(UWORD start, UWORD end, UBYTE *memory)
3561: ; Moves a Z80_MAP_MAPPED area to use a different region of memory
3562: ; start/end = the area it covers (must be page-aligned)
3563: ; memory = the ROM/RAM to read from
3564: global z80_map_read
3565: z80_map_read:
3566: push ebx
3567: mov eax, [esp+8]
3568: mov ebx, [esp+12]
3569: mov ecx, [esp+16]
3570: and eax, 0ffffh
3571: and ebx, 0ffffh
3572: sub ecx, eax
3573:
3574: mr_loop:
3575: ; if there's no area left inbetween, stop now.
3576: mov edx, eax
3577: shr edx, 8
3578:
3579: cmp eax, ebx
3580: ja mr_finish
3581:
3582: mov [z80_Read+edx*8], dword 0
3583: mov [z80_Read+edx*8+4], ecx
3584: add eax, 0100h
3585: jmp mr_loop
3586:
3587: mr_finish:
3588: pop ebx
3589: ret
3590:
3591: ; void z80_map_write(UWORD start, UWORD end, UBYTE *memory)
3592: ; Moves a Z80_MAP_MAPPED area to use a different region of memory
3593: ; start/end = the area it covers (must be page-aligned)
3594: ; memory = the ROM/RAM to read from
3595: global z80_map_write
3596: z80_map_write:
3597: push ebx
3598: mov eax, [esp+8]
3599: mov ebx, [esp+12]
3600: mov ecx, [esp+16]
3601: and eax, 0ffffh
3602: and ebx, 0ffffh
3603: sub ecx, eax
3604:
3605: mw_loop:
3606: ; if there's no area left inbetween, stop now.
3607: mov edx, eax
3608: shr edx, 8
3609:
3610: cmp eax, ebx
3611: ja mw_finish
3612:
3613: mov [z80_Write+edx*8], dword 0
3614: mov [z80_Write+edx*8+4], ecx
3615: add eax, 0100h
3616: jmp mw_loop
3617:
3618: mw_finish:
3619: pop ebx
3620: ret
3621:
3622: ; void z80_add_read(UWORD start, UWORD end, int method, void *data)
3623: ; Add a READ memory handler to the memory map
3624: ; start/end = the area it covers
3625: ; method = 0 for direct, 1 for handled
3626: ; data = RAM for direct, handler for handled
3627: global z80_add_read
3628: z80_add_read:
3629: push ebx
3630: mov eax, [esp+8]
3631: mov ebx, [esp+12]
3632: mov ecx, [esp+20]
3633: and eax, 0ffffh
3634: and ebx, 0ffffh
3635:
3636: ; put the entry in the read table first
3637: mov edx, _read_handlers
3638: ar_find:
3639: add edx, 16
3640: cmp [edx-16], dword (-1)
3641: jne ar_find
3642: sub edx, 16
3643:
3644: ; put it in there
3645: mov [edx], eax
3646: mov [edx+4], ebx
3647: mov eax, [esp+16]
3648: mov [edx+8], eax
3649:
3650: mov eax, ecx ; if direct, subtract the start from the memory area
3651: push ebx
3652: mov ebx, [esp+12]
3653: and ebx, 0ffffh
3654: cmp [esp+20], dword 1
3655: je ar_dont_adjust
3656: sub eax, ebx
3657: ar_dont_adjust:
3658: mov [edx+12], eax
3659:
3660: mov eax, ebx
3661: pop ebx
3662:
3663: ; process the start, so it's page aligned
3664: test al, al
3665: jz ar_start_done
3666:
3667: ; put the start handler to go to the dispatcher
3668: mov edx, eax
3669: shr edx, 8
3670: mov [z80_Read+edx*8], dword read_dispatcher
3671: xor al, al
3672: add eax, 0100h
3673:
3674: ar_start_done:
3675: ; process the end, so it's page aligned
3676: cmp bl, 0ffh
3677: je ar_end_done
3678:
3679: ; put the end handler to go to the dispatcher
3680: mov edx, ebx
3681: shr edx, 8
3682: mov [z80_Read+edx*8], dword read_dispatcher
3683: mov bl, 0ffh
3684: sub ebx, 0100h
3685:
3686: ar_end_done:
3687:
3688: sub ecx, eax
3689: ar_loop:
3690: ; if there's no area left inbetween, stop now.
3691: mov edx, eax
3692: shr edx, 8
3693:
3694: cmp eax, ebx
3695: jg ar_finish
3696:
3697: cmp [esp+16], dword 0
3698: je ar_put_direct
3699:
3700: push ecx
3701: mov ecx, [esp+24]
3702: mov [z80_Read+edx*8], ecx
3703: pop ecx
3704: add eax, 0100h
3705: jmp ar_loop
3706:
3707: ar_put_direct:
3708: mov [z80_Read+edx*8], dword 0
3709: mov [z80_Read+edx*8+4], ecx
3710: add eax, 0100h
3711: jmp ar_loop
3712:
3713: ar_finish:
3714: pop ebx
3715: ret
3716:
3717: ; void z80_add_write(UWORD start, UWORD end, int method, void *data)
3718: ; Add a WRITE memory handler to the memory map
3719: ; start/end = the area it covers
3720: ; method = 0 for direct, 1 for handled
3721: ; data = RAM for direct, handler for handled
3722: global z80_add_write
3723: z80_add_write:
3724: push ebx
3725: mov eax, [esp+8]
3726: mov ebx, [esp+12]
3727: mov ecx, [esp+20]
3728: and eax, 0ffffh
3729: and ebx, 0ffffh
3730:
3731: ; put the entry in the read table first
3732: mov edx, _write_handlers
3733: aw_find:
3734: add edx, 16
3735: cmp [edx-16], dword (-1)
3736: jne aw_find
3737: sub edx, 16
3738:
3739: ; put it in there
3740: mov [edx], eax
3741: mov [edx+4], ebx
3742: mov eax, [esp+16]
3743: mov [edx+8], eax
3744:
3745: mov eax, ecx ; if direct, subtract the start from the memory area
3746: push ebx
3747: mov ebx, [esp+12]
3748: and ebx, 0ffffh
3749: cmp [esp+20], dword 1
3750: je aw_dont_adjust
3751: sub eax, ebx
3752: aw_dont_adjust:
3753: mov [edx+12], eax
3754:
3755: mov eax, ebx
3756: pop ebx
3757:
3758: ; process the start, so it's page aligned
3759: test al, al
3760: jz aw_start_done
3761:
3762: ; put the start handler to go to the dispatcher
3763: mov edx, eax
3764: shr edx, 8
3765: mov [z80_Write+edx*8], dword write_dispatcher
3766: xor al, al
3767: add eax, 0100h
3768:
3769: aw_start_done:
3770: ; process the end, so it's page aligned
3771: cmp bl, 0ffh
3772: je aw_end_done
3773:
3774: ; put the end handler to go to the dispatcher
3775: mov edx, ebx
3776: shr edx, 8
3777: mov [z80_Write+edx*8], dword write_dispatcher
3778: mov bl, 0ffh
3779: sub ebx, 0100h
3780:
3781: aw_end_done:
3782:
3783: sub ecx, eax
3784: aw_loop:
3785: ; if there's no area left inbetween, stop now.
3786: mov edx, eax
3787: shr edx, 8
3788:
3789: cmp eax, ebx
3790: jg aw_finish
3791:
3792: cmp [esp+16], dword 0
3793: je aw_put_direct
3794:
3795: push ecx
3796: mov ecx, [esp+24]
3797: mov [z80_Write+edx*8], ecx
3798: pop ecx
3799: add eax, 0100h
3800: jmp aw_loop
3801:
3802: aw_put_direct:
3803: mov [z80_Write+edx*8], dword 0
3804: mov [z80_Write+edx*8+4], ecx
3805: add eax, 0100h
3806: jmp aw_loop
3807:
3808: aw_finish:
3809: pop ebx
3810: ret
3811:
3812: ; void z80_set_in(UBYTE (*handler)(UWORD port))
3813: ; Set the IN port handler to the given function
3814: global z80_set_in
3815: z80_set_in:
3816: mov eax, [esp+4]
3817: mov [z80_In], eax
3818: ret
3819:
3820: ; void z80_set_out(void (*handler)(UWORD port, UBYTE value))
3821: ; Set the OUT port handler to the given function
3822: global z80_set_out
3823: z80_set_out:
3824: mov eax, [esp+4]
3825: mov [z80_Out], eax
3826: ret
3827:
3828: ; void z80_set_reti(void (*handler)(void))
3829: ; Set the RETI handler to the given function
3830: global z80_set_reti
3831: z80_set_reti:
3832: mov eax, [esp+4]
3833: mov [z80_RetI], eax
3834: ret
3835:
3836: ; void z80_set_fetch_callback(void (*handler)(UWORD pc))
3837: ; Set the fetch callback to the given function
3838: global z80_set_fetch_callback
3839: z80_set_fetch_callback:
3840: mov eax, [esp+4]
3841: mov [z80_Fetch_Callback], eax
3842: ret
3843:
3844: ;----------------------------------------------------------------------------;
3845: ; the jump tables
3846: OpTable:
3847: dd op_00, op_01, op_02, op_03, op_04, op_05, op_06, op_07
3848: dd op_08, op_09, op_0a, op_0b, op_0c, op_0d, op_0e, op_0f
3849: dd op_10, op_11, op_12, op_13, op_14, op_15, op_16, op_17
3850: dd op_18, op_19, op_1a, op_1b, op_1c, op_1d, op_1e, op_1f
3851: dd op_20, op_21, op_22, op_23, op_24, op_25, op_26, op_27
3852: dd op_28, op_29, op_2a, op_2b, op_2c, op_2d, op_2e, op_2f
3853: dd op_30, op_31, op_32, op_33, op_34, op_35, op_36, op_37
3854: dd op_38, op_39, op_3a, op_3b, op_3c, op_3d, op_3e, op_3f
3855: dd op_40, op_41, op_42, op_43, op_44, op_45, op_46, op_47
3856: dd op_48, op_49, op_4a, op_4b, op_4c, op_4d, op_4e, op_4f
3857: dd op_50, op_51, op_52, op_53, op_54, op_55, op_56, op_57
3858: dd op_58, op_59, op_5a, op_5b, op_5c, op_5d, op_5e, op_5f
3859: dd op_60, op_61, op_62, op_63, op_64, op_65, op_66, op_67
3860: dd op_68, op_69, op_6a, op_6b, op_6c, op_6d, op_6e, op_6f
3861: dd op_70, op_71, op_72, op_73, op_74, op_75, op_76, op_77
3862: dd op_78, op_79, op_7a, op_7b, op_7c, op_7d, op_7e, op_7f
3863: dd op_80, op_81, op_82, op_83, op_84, op_85, op_86, op_87
3864: dd op_88, op_89, op_8a, op_8b, op_8c, op_8d, op_8e, op_8f
3865: dd op_90, op_91, op_92, op_93, op_94, op_95, op_96, op_97
3866: dd op_98, op_99, op_9a, op_9b, op_9c, op_9d, op_9e, op_9f
3867: dd op_a0, op_a1, op_a2, op_a3, op_a4, op_a5, op_a6, op_a7
3868: dd op_a8, op_a9, op_aa, op_ab, op_ac, op_ad, op_ae, op_af
3869: dd op_b0, op_b1, op_b2, op_b3, op_b4, op_b5, op_b6, op_b7
3870: dd op_b8, op_b9, op_ba, op_bb, op_bc, op_bd, op_be, op_bf
3871: dd op_c0, op_c1, op_c2, op_c3, op_c4, op_c5, op_c6, op_c7
3872: dd op_c8, op_c9, op_ca, op_cb, op_cc, op_cd, op_ce, op_cf
3873: dd op_d0, op_d1, op_d2, op_d3, op_d4, op_d5, op_d6, op_d7
3874: dd op_d8, op_d9, op_da, op_db, op_dc, op_dd, op_de, op_df
3875: dd op_e0, op_e1, op_e2, op_e3, op_e4, op_e5, op_e6, op_e7
3876: dd op_e8, op_e9, op_ea, op_eb, op_ec, op_ed, op_ee, op_ef
3877: dd op_f0, op_f1, op_f2, op_f3, op_f4, op_f5, op_f6, op_f7
3878: dd op_f8, op_f9, op_fa, op_fb, op_fc, op_fd, op_fe, op_ff
3879:
3880: CBTable:
3881: dd cb_00, cb_01, cb_02, cb_03, cb_04, cb_05, cb_06, cb_07
3882: dd cb_08, cb_09, cb_0a, cb_0b, cb_0c, cb_0d, cb_0e, cb_0f
3883: dd cb_10, cb_11, cb_12, cb_13, cb_14, cb_15, cb_16, cb_17
3884: dd cb_18, cb_19, cb_1a, cb_1b, cb_1c, cb_1d, cb_1e, cb_1f
3885: dd cb_20, cb_21, cb_22, cb_23, cb_24, cb_25, cb_26, cb_27
3886: dd cb_28, cb_29, cb_2a, cb_2b, cb_2c, cb_2d, cb_2e, cb_2f
3887: dd cb_30, cb_31, cb_32, cb_33, cb_34, cb_35, cb_36, cb_37
3888: dd cb_38, cb_39, cb_3a, cb_3b, cb_3c, cb_3d, cb_3e, cb_3f
3889: dd cb_40, cb_41, cb_42, cb_43, cb_44, cb_45, cb_46, cb_47
3890: dd cb_48, cb_49, cb_4a, cb_4b, cb_4c, cb_4d, cb_4e, cb_4f
3891: dd cb_50, cb_51, cb_52, cb_53, cb_54, cb_55, cb_56, cb_57
3892: dd cb_58, cb_59, cb_5a, cb_5b, cb_5c, cb_5d, cb_5e, cb_5f
3893: dd cb_60, cb_61, cb_62, cb_63, cb_64, cb_65, cb_66, cb_67
3894: dd cb_68, cb_69, cb_6a, cb_6b, cb_6c, cb_6d, cb_6e, cb_6f
3895: dd cb_70, cb_71, cb_72, cb_73, cb_74, cb_75, cb_76, cb_77
3896: dd cb_78, cb_79, cb_7a, cb_7b, cb_7c, cb_7d, cb_7e, cb_7f
3897: dd cb_80, cb_81, cb_82, cb_83, cb_84, cb_85, cb_86, cb_87
3898: dd cb_88, cb_89, cb_8a, cb_8b, cb_8c, cb_8d, cb_8e, cb_8f
3899: dd cb_90, cb_91, cb_92, cb_93, cb_94, cb_95, cb_96, cb_97
3900: dd cb_98, cb_99, cb_9a, cb_9b, cb_9c, cb_9d, cb_9e, cb_9f
3901: dd cb_a0, cb_a1, cb_a2, cb_a3, cb_a4, cb_a5, cb_a6, cb_a7
3902: dd cb_a8, cb_a9, cb_aa, cb_ab, cb_ac, cb_ad, cb_ae, cb_af
3903: dd cb_b0, cb_b1, cb_b2, cb_b3, cb_b4, cb_b5, cb_b6, cb_b7
3904: dd cb_b8, cb_b9, cb_ba, cb_bb, cb_bc, cb_bd, cb_be, cb_bf
3905: dd cb_c0, cb_c1, cb_c2, cb_c3, cb_c4, cb_c5, cb_c6, cb_c7
3906: dd cb_c8, cb_c9, cb_ca, cb_cb, cb_cc, cb_cd, cb_ce, cb_cf
3907: dd cb_d0, cb_d1, cb_d2, cb_d3, cb_d4, cb_d5, cb_d6, cb_d7
3908: dd cb_d8, cb_d9, cb_da, cb_db, cb_dc, cb_dd, cb_de, cb_df
3909: dd cb_e0, cb_e1, cb_e2, cb_e3, cb_e4, cb_e5, cb_e6, cb_e7
3910: dd cb_e8, cb_e9, cb_ea, cb_eb, cb_ec, cb_ed, cb_ee, cb_ef
3911: dd cb_f0, cb_f1, cb_f2, cb_f3, cb_f4, cb_f5, cb_f6, cb_f7
3912: dd cb_f8, cb_f9, cb_fa, cb_fb, cb_fc, cb_fd, cb_fe, cb_ff
3913:
3914: EDTable:
3915: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3916: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3917: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3918: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3919: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3920: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3921: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3922: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3923: dd ed_40, ed_41, ed_42, ed_43, ed_44, ed_45, ed_46, ed_47
3924: dd ed_48, ed_49, ed_4a, ed_4b, ed_4c, ed_4d, ed_4e, ed_4f
3925: dd ed_50, ed_51, ed_52, ed_53, ed_54, ed_55, ed_56, ed_57
3926: dd ed_58, ed_59, ed_5a, ed_5b, ed_5c, ed_5d, ed_5e, ed_5f
3927: dd ed_60, ed_61, ed_62, ed_63, ed_64, ed_65, ed_66, ed_67
3928: dd ed_68, ed_69, ed_6a, ed_6b, ed_6c, ed_6d, ed_6e, ed_6f
3929: dd ed_70, ed_71, ed_72, ed_73, ed_74, ed_75, ed_76, ed_xx
3930: dd ed_78, ed_79, ed_7a, ed_7b, ed_7c, ed_7d, ed_7e, ed_xx
3931: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3932: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3933: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3934: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3935: dd ed_a0, ed_a1, ed_a2, ed_a3, ed_xx, ed_xx, ed_xx, ed_xx
3936: dd ed_a8, ed_a9, ed_aa, ed_ab, ed_xx, ed_xx, ed_xx, ed_xx
3937: dd ed_b0, ed_b1, ed_b2, ed_b3, ed_xx, ed_xx, ed_xx, ed_xx
3938: dd ed_b8, ed_b9, ed_ba, ed_bb, ed_xx, ed_xx, ed_xx, ed_xx
3939: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3940: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3941: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3942: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3943: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3944: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3945: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3946: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3947:
3948: DDTable:
3949: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3950: dd dd_xx, dd_09, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3951: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3952: dd dd_xx, dd_19, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3953: dd dd_xx, dd_21, dd_22, dd_23, dd_24, dd_25, dd_26, dd_xx
3954: dd dd_xx, dd_29, dd_2a, dd_2b, dd_2c, dd_2d, dd_2e, dd_xx
3955: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_34, dd_35, dd_36, dd_xx
3956: dd dd_xx, dd_39, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3957: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_44, dd_45, dd_46, dd_xx
3958: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_4c, dd_4d, dd_4e, dd_xx
3959: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_54, dd_55, dd_56, dd_xx
3960: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_5c, dd_5d, dd_5e, dd_xx
3961: dd dd_60, dd_61, dd_62, dd_63, dd_xx, dd_65, dd_66, dd_67
3962: dd dd_68, dd_69, dd_6a, dd_6b, dd_6c, dd_xx, dd_6e, dd_6f
3963: dd dd_70, dd_71, dd_72, dd_73, dd_74, dd_75, dd_xx, dd_77
3964: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_7c, dd_7d, dd_7e, dd_xx
3965: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_84, dd_85, dd_86, dd_xx
3966: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_8c, dd_8d, dd_8e, dd_xx
3967: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_94, dd_95, dd_96, dd_xx
3968: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_9c, dd_9d, dd_9e, dd_xx
3969: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_a4, dd_a5, dd_a6, dd_xx
3970: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_ac, dd_ad, dd_ae, dd_xx
3971: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_b4, dd_b5, dd_b6, dd_xx
3972: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_bc, dd_bd, dd_be, dd_xx
3973: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3974: dd dd_xx, dd_xx, dd_xx, dd_cb, dd_xx, dd_xx, dd_xx, dd_xx
3975: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3976: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3977: dd dd_xx, dd_e1, dd_xx, dd_e3, dd_xx, dd_e5, dd_xx, dd_xx
3978: dd dd_xx, dd_e9, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3979: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3980: dd dd_xx, dd_f9, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3981:
3982: FDTable:
3983: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3984: dd fd_xx, fd_09, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3985: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3986: dd fd_xx, fd_19, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3987: dd fd_xx, fd_21, fd_22, fd_23, fd_24, fd_25, fd_26, fd_xx
3988: dd fd_xx, fd_29, fd_2a, fd_2b, fd_2c, fd_2d, fd_2e, fd_xx
3989: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_34, fd_35, fd_36, fd_xx
3990: dd fd_xx, fd_39, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3991: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_44, fd_45, fd_46, fd_xx
3992: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_4c, fd_4d, fd_4e, fd_xx
3993: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_54, fd_55, fd_56, fd_xx
3994: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_5c, fd_5d, fd_5e, fd_xx
3995: dd fd_60, fd_61, fd_62, fd_63, fd_xx, fd_65, fd_66, fd_67
3996: dd fd_68, fd_69, fd_6a, fd_6b, fd_6c, fd_xx, fd_6e, fd_6f
3997: dd fd_70, fd_71, fd_72, fd_73, fd_74, fd_75, fd_xx, fd_77
3998: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_7c, fd_7d, fd_7e, fd_xx
3999: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_84, fd_85, fd_86, fd_xx
4000: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_8c, fd_8d, fd_8e, fd_xx
4001: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_94, fd_95, fd_96, fd_xx
4002: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_9c, fd_9d, fd_9e, fd_xx
4003: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_a4, fd_a5, fd_a6, fd_xx
4004: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_ac, fd_ad, fd_ae, fd_xx
4005: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_b4, fd_b5, fd_b6, fd_xx
4006: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_bc, fd_bd, fd_be, fd_xx
4007: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4008: dd fd_xx, fd_xx, fd_xx, fd_cb, fd_xx, fd_xx, fd_xx, fd_xx
4009: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4010: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4011: dd fd_xx, fd_e1, fd_xx, fd_e3, fd_xx, fd_e5, fd_xx, fd_xx
4012: dd fd_xx, fd_e9, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4013: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4014: dd fd_xx, fd_f9, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4015:
4016: DDCBTable:
4017: dd ddcb_00, ddcb_01, ddcb_02, ddcb_03, ddcb_04, ddcb_05, ddcb_06, ddcb_07
4018: dd ddcb_08, ddcb_09, ddcb_0a, ddcb_0b, ddcb_0c, ddcb_0d, ddcb_0e, ddcb_0f
4019: dd ddcb_10, ddcb_11, ddcb_12, ddcb_13, ddcb_14, ddcb_15, ddcb_16, ddcb_17
4020: dd ddcb_18, ddcb_19, ddcb_1a, ddcb_1b, ddcb_1c, ddcb_1d, ddcb_1e, ddcb_1f
4021: dd ddcb_20, ddcb_21, ddcb_22, ddcb_23, ddcb_24, ddcb_25, ddcb_26, ddcb_27
4022: dd ddcb_28, ddcb_29, ddcb_2a, ddcb_2b, ddcb_2c, ddcb_2d, ddcb_2e, ddcb_2f
4023: dd ddcb_30, ddcb_31, ddcb_32, ddcb_33, ddcb_34, ddcb_35, ddcb_36, ddcb_37
4024: dd ddcb_38, ddcb_39, ddcb_3a, ddcb_3b, ddcb_3c, ddcb_3d, ddcb_3e, ddcb_3f
4025: dd ddcb_40, ddcb_41, ddcb_42, ddcb_43, ddcb_44, ddcb_45, ddcb_46, ddcb_47
4026: dd ddcb_48, ddcb_49, ddcb_4a, ddcb_4b, ddcb_4c, ddcb_4d, ddcb_4e, ddcb_4f
4027: dd ddcb_50, ddcb_51, ddcb_52, ddcb_53, ddcb_54, ddcb_55, ddcb_56, ddcb_57
4028: dd ddcb_58, ddcb_59, ddcb_5a, ddcb_5b, ddcb_5c, ddcb_5d, ddcb_5e, ddcb_5f
4029: dd ddcb_60, ddcb_61, ddcb_62, ddcb_63, ddcb_64, ddcb_65, ddcb_66, ddcb_67
4030: dd ddcb_68, ddcb_69, ddcb_6a, ddcb_6b, ddcb_6c, ddcb_6d, ddcb_6e, ddcb_6f
4031: dd ddcb_70, ddcb_71, ddcb_72, ddcb_73, ddcb_74, ddcb_75, ddcb_76, ddcb_77
4032: dd ddcb_78, ddcb_79, ddcb_7a, ddcb_7b, ddcb_7c, ddcb_7d, ddcb_7e, ddcb_7f
4033: dd ddcb_80, ddcb_81, ddcb_82, ddcb_83, ddcb_84, ddcb_85, ddcb_86, ddcb_87
4034: dd ddcb_88, ddcb_89, ddcb_8a, ddcb_8b, ddcb_8c, ddcb_8d, ddcb_8e, ddcb_8f
4035: dd ddcb_90, ddcb_91, ddcb_92, ddcb_93, ddcb_94, ddcb_95, ddcb_96, ddcb_97
4036: dd ddcb_98, ddcb_99, ddcb_9a, ddcb_9b, ddcb_9c, ddcb_9d, ddcb_9e, ddcb_9f
4037: dd ddcb_a0, ddcb_a1, ddcb_a2, ddcb_a3, ddcb_a4, ddcb_a5, ddcb_a6, ddcb_a7
4038: dd ddcb_a8, ddcb_a9, ddcb_aa, ddcb_ab, ddcb_ac, ddcb_ad, ddcb_ae, ddcb_af
4039: dd ddcb_b0, ddcb_b1, ddcb_b2, ddcb_b3, ddcb_b4, ddcb_b5, ddcb_b6, ddcb_b7
4040: dd ddcb_b8, ddcb_b9, ddcb_ba, ddcb_bb, ddcb_bc, ddcb_bd, ddcb_be, ddcb_bf
4041: dd ddcb_c0, ddcb_c1, ddcb_c2, ddcb_c3, ddcb_c4, ddcb_c5, ddcb_c6, ddcb_c7
4042: dd ddcb_c8, ddcb_c9, ddcb_ca, ddcb_cb, ddcb_cc, ddcb_cd, ddcb_ce, ddcb_cf
4043: dd ddcb_d0, ddcb_d1, ddcb_d2, ddcb_d3, ddcb_d4, ddcb_d5, ddcb_d6, ddcb_d7
4044: dd ddcb_d8, ddcb_d9, ddcb_da, ddcb_db, ddcb_dc, ddcb_dd, ddcb_de, ddcb_df
4045: dd ddcb_e0, ddcb_e1, ddcb_e2, ddcb_e3, ddcb_e4, ddcb_e5, ddcb_e6, ddcb_e7
4046: dd ddcb_e8, ddcb_e9, ddcb_ea, ddcb_eb, ddcb_ec, ddcb_ed, ddcb_ee, ddcb_ef
4047: dd ddcb_f0, ddcb_f1, ddcb_f2, ddcb_f3, ddcb_f4, ddcb_f5, ddcb_f6, ddcb_f7
4048: dd ddcb_f8, ddcb_f9, ddcb_fa, ddcb_fb, ddcb_fc, ddcb_fd, ddcb_fe, ddcb_ff
4049:
4050:
4051: ;----------------------------------------------------------------------------;
4052: ; flag tables ('borrowed' from MAZE, by Ishmair)
4053: INC_Table:
4054: DB 0,0,0,0,0,0,0,8,8,8,8,8,8,8,8,16,0,0,0,0
4055: DB 0,0,0,8,8,8,8,8,8,8,8,48,32,32,32,32,32,32,32,40
4056: DB 40,40,40,40,40,40,40,48,32,32,32,32,32,32,32,40,40,40,40,40
4057: DB 40,40,40,16,0,0,0,0,0,0,0,8,8,8,8,8,8,8,8,16
4058: DB 0,0,0,0,0,0,0,8,8,8,8,8,8,8,8,48,32,32,32,32
4059: DB 32,32,32,40,40,40,40,40,40,40,40,48,32,32,32,32,32,32,32,40
4060: DB 40,40,40,40,40,40,40,148,128,128,128,128,128,128,128,136,136,136,136,136
4061: DB 136,136,136,144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,176
4062: DB 160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,176,160,160,160,160
4063: DB 160,160,160,168,168,168,168,168,168,168,168,144,128,128,128,128,128,128,128,136
4064: DB 136,136,136,136,136,136,136,144,128,128,128,128,128,128,128,136,136,136,136,136
4065: DB 136,136,136,176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,176
4066: DB 160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,80
4067:
4068: DEC_Table:
4069: DB 186,66,2,2,2,2,2,2,2,10,10,10,10,10,10,10,26,2,2,2
4070: DB 2,2,2,2,2,10,10,10,10,10,10,10,26,34,34,34,34,34,34,34
4071: DB 34,42,42,42,42,42,42,42,58,34,34,34,34,34,34,34,34,42,42,42
4072: DB 42,42,42,42,58,2,2,2,2,2,2,2,2,10,10,10,10,10,10,10
4073: DB 26,2,2,2,2,2,2,2,2,10,10,10,10,10,10,10,26,34,34,34
4074: DB 34,34,34,34,34,42,42,42,42,42,42,42,58,34,34,34,34,34,34,34
4075: DB 34,42,42,42,42,42,42,42,62,130,130,130,130,130,130,130,130,138,138,138
4076: DB 138,138,138,138,154,130,130,130,130,130,130,130,130,138,138,138,138,138,138,138
4077: DB 154,162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,162,162,162
4078: DB 162,162,162,162,162,170,170,170,170,170,170,170,186,130,130,130,130,130,130,130
4079: DB 130,138,138,138,138,138,138,138,154,130,130,130,130,130,130,130,130,138,138,138
4080: DB 138,138,138,138,154,162,162,162,162,162,162,162,162,170,170,170,170,170,170,170
4081: DB 186,162,162,162,162,162,162,162,162,170,170,170,170,170,170,170
4082:
4083: ; DAA table ('borrowed' from Z80Emul, by unknown)
4084: DAA_Table:
4085: DW 04400h, 00001h, 00002h, 00403h, 00004h, 00405h, 00406h, 00007h
4086: DW 00808h, 00C09h, 01010h, 01411h, 01412h, 01013h, 01414h, 01015h
4087: DW 00010h, 00411h, 00412h, 00013h, 00414h, 00015h, 00016h, 00417h
4088: DW 00C18h, 00819h, 03020h, 03421h, 03422h, 03023h, 03424h, 03025h
4089: DW 02020h, 02421h, 02422h, 02023h, 02424h, 02025h, 02026h, 02427h
4090: DW 02C28h, 02829h, 03430h, 03031h, 03032h, 03433h, 03034h, 03435h
4091: DW 02430h, 02031h, 02032h, 02433h, 02034h, 02435h, 02436h, 02037h
4092: DW 02838h, 02C39h, 01040h, 01441h, 01442h, 01043h, 01444h, 01045h
4093: DW 00040h, 00441h, 00442h, 00043h, 00444h, 00045h, 00046h, 00447h
4094: DW 00C48h, 00849h, 01450h, 01051h, 01052h, 01453h, 01054h, 01455h
4095: DW 00450h, 00051h, 00052h, 00453h, 00054h, 00455h, 00456h, 00057h
4096: DW 00858h, 00C59h, 03460h, 03061h, 03062h, 03463h, 03064h, 03465h
4097: DW 02460h, 02061h, 02062h, 02463h, 02064h, 02465h, 02466h, 02067h
4098: DW 02868h, 02C69h, 03070h, 03471h, 03472h, 03073h, 03474h, 03075h
4099: DW 02070h, 02471h, 02472h, 02073h, 02474h, 02075h, 02076h, 02477h
4100: DW 02C78h, 02879h, 09080h, 09481h, 09482h, 09083h, 09484h, 09085h
4101: DW 08080h, 08481h, 08482h, 08083h, 08484h, 08085h, 08086h, 08487h
4102: DW 08C88h, 08889h, 09490h, 09091h, 09092h, 09493h, 09094h, 09495h
4103: DW 08490h, 08091h, 08092h, 08493h, 08094h, 08495h, 08496h, 08097h
4104: DW 08898h, 08C99h, 05500h, 01101h, 01102h, 01503h, 01104h, 01505h
4105: DW 04500h, 00101h, 00102h, 00503h, 00104h, 00505h, 00506h, 00107h
4106: DW 00908h, 00D09h, 01110h, 01511h, 01512h, 01113h, 01514h, 01115h
4107: DW 00110h, 00511h, 00512h, 00113h, 00514h, 00115h, 00116h, 00517h
4108: DW 00D18h, 00919h, 03120h, 03521h, 03522h, 03123h, 03524h, 03125h
4109: DW 02120h, 02521h, 02522h, 02123h, 02524h, 02125h, 02126h, 02527h
4110: DW 02D28h, 02929h, 03530h, 03131h, 03132h, 03533h, 03134h, 03535h
4111: DW 02530h, 02131h, 02132h, 02533h, 02134h, 02535h, 02536h, 02137h
4112: DW 02938h, 02D39h, 01140h, 01541h, 01542h, 01143h, 01544h, 01145h
4113: DW 00140h, 00541h, 00542h, 00143h, 00544h, 00145h, 00146h, 00547h
4114: DW 00D48h, 00949h, 01550h, 01151h, 01152h, 01553h, 01154h, 01555h
4115: DW 00550h, 00151h, 00152h, 00553h, 00154h, 00555h, 00556h, 00157h
4116: DW 00958h, 00D59h, 03560h, 03161h, 03162h, 03563h, 03164h, 03565h
4117: DW 02560h, 02161h, 02162h, 02563h, 02164h, 02565h, 02566h, 02167h
4118: DW 02968h, 02D69h, 03170h, 03571h, 03572h, 03173h, 03574h, 03175h
4119: DW 02170h, 02571h, 02572h, 02173h, 02574h, 02175h, 02176h, 02577h
4120: DW 02D78h, 02979h, 09180h, 09581h, 09582h, 09183h, 09584h, 09185h
4121: DW 08180h, 08581h, 08582h, 08183h, 08584h, 08185h, 08186h, 08587h
4122: DW 08D88h, 08989h, 09590h, 09191h, 09192h, 09593h, 09194h, 09595h
4123: DW 08590h, 08191h, 08192h, 08593h, 08194h, 08595h, 08596h, 08197h
4124: DW 08998h, 08D99h, 0B5A0h, 0B1A1h, 0B1A2h, 0B5A3h, 0B1A4h, 0B5A5h
4125: DW 0A5A0h, 0A1A1h, 0A1A2h, 0A5A3h, 0A1A4h, 0A5A5h, 0A5A6h, 0A1A7h
4126: DW 0A9A8h, 0ADA9h, 0B1B0h, 0B5B1h, 0B5B2h, 0B1B3h, 0B5B4h, 0B1B5h
4127: DW 0A1B0h, 0A5B1h, 0A5B2h, 0A1B3h, 0A5B4h, 0A1B5h, 0A1B6h, 0A5B7h
4128: DW 0ADB8h, 0A9B9h, 095C0h, 091C1h, 091C2h, 095C3h, 091C4h, 095C5h
4129: DW 085C0h, 081C1h, 081C2h, 085C3h, 081C4h, 085C5h, 085C6h, 081C7h
4130: DW 089C8h, 08DC9h, 091D0h, 095D1h, 095D2h, 091D3h, 095D4h, 091D5h
4131: DW 081D0h, 085D1h, 085D2h, 081D3h, 085D4h, 081D5h, 081D6h, 085D7h
4132: DW 08DD8h, 089D9h, 0B1E0h, 0B5E1h, 0B5E2h, 0B1E3h, 0B5E4h, 0B1E5h
4133: DW 0A1E0h, 0A5E1h, 0A5E2h, 0A1E3h, 0A5E4h, 0A1E5h, 0A1E6h, 0A5E7h
4134: DW 0ADE8h, 0A9E9h, 0B5F0h, 0B1F1h, 0B1F2h, 0B5F3h, 0B1F4h, 0B5F5h
4135: DW 0A5F0h, 0A1F1h, 0A1F2h, 0A5F3h, 0A1F4h, 0A5F5h, 0A5F6h, 0A1F7h
4136: DW 0A9F8h, 0ADF9h, 05500h, 01101h, 01102h, 01503h, 01104h, 01505h
4137: DW 04500h, 00101h, 00102h, 00503h, 00104h, 00505h, 00506h, 00107h
4138: DW 00908h, 00D09h, 01110h, 01511h, 01512h, 01113h, 01514h, 01115h
4139: DW 00110h, 00511h, 00512h, 00113h, 00514h, 00115h, 00116h, 00517h
4140: DW 00D18h, 00919h, 03120h, 03521h, 03522h, 03123h, 03524h, 03125h
4141: DW 02120h, 02521h, 02522h, 02123h, 02524h, 02125h, 02126h, 02527h
4142: DW 02D28h, 02929h, 03530h, 03131h, 03132h, 03533h, 03134h, 03535h
4143: DW 02530h, 02131h, 02132h, 02533h, 02134h, 02535h, 02536h, 02137h
4144: DW 02938h, 02D39h, 01140h, 01541h, 01542h, 01143h, 01544h, 01145h
4145: DW 00140h, 00541h, 00542h, 00143h, 00544h, 00145h, 00146h, 00547h
4146: DW 00D48h, 00949h, 01550h, 01151h, 01152h, 01553h, 01154h, 01555h
4147: DW 00550h, 00151h, 00152h, 00553h, 00154h, 00555h, 00556h, 00157h
4148: DW 00958h, 00D59h, 03560h, 03161h, 03162h, 03563h, 03164h, 03565h
4149: DW 04600h, 00201h, 00202h, 00603h, 00204h, 00605h, 00606h, 00207h
4150: DW 00A08h, 00E09h, 00204h, 00605h, 00606h, 00207h, 00A08h, 00E09h
4151: DW 00210h, 00611h, 00612h, 00213h, 00614h, 00215h, 00216h, 00617h
4152: DW 00E18h, 00A19h, 00614h, 00215h, 00216h, 00617h, 00E18h, 00A19h
4153: DW 02220h, 02621h, 02622h, 02223h, 02624h, 02225h, 02226h, 02627h
4154: DW 02E28h, 02A29h, 02624h, 02225h, 02226h, 02627h, 02E28h, 02A29h
4155: DW 02630h, 02231h, 02232h, 02633h, 02234h, 02635h, 02636h, 02237h
4156: DW 02A38h, 02E39h, 02234h, 02635h, 02636h, 02237h, 02A38h, 02E39h
4157: DW 00240h, 00641h, 00642h, 00243h, 00644h, 00245h, 00246h, 00647h
4158: DW 00E48h, 00A49h, 00644h, 00245h, 00246h, 00647h, 00E48h, 00A49h
4159: DW 00650h, 00251h, 00252h, 00653h, 00254h, 00655h, 00656h, 00257h
4160: DW 00A58h, 00E59h, 00254h, 00655h, 00656h, 00257h, 00A58h, 00E59h
4161: DW 02660h, 02261h, 02262h, 02663h, 02264h, 02665h, 02666h, 02267h
4162: DW 02A68h, 02E69h, 02264h, 02665h, 02666h, 02267h, 02A68h, 02E69h
4163: DW 02270h, 02671h, 02672h, 02273h, 02674h, 02275h, 02276h, 02677h
4164: DW 02E78h, 02A79h, 02674h, 02275h, 02276h, 02677h, 02E78h, 02A79h
4165: DW 08280h, 08681h, 08682h, 08283h, 08684h, 08285h, 08286h, 08687h
4166: DW 08E88h, 08A89h, 08684h, 08285h, 08286h, 08687h, 08E88h, 08A89h
4167: DW 08690h, 08291h, 08292h, 08693h, 08294h, 08695h, 08696h, 08297h
4168: DW 08A98h, 08E99h, 02334h, 02735h, 02736h, 02337h, 02B38h, 02F39h
4169: DW 00340h, 00741h, 00742h, 00343h, 00744h, 00345h, 00346h, 00747h
4170: DW 00F48h, 00B49h, 00744h, 00345h, 00346h, 00747h, 00F48h, 00B49h
4171: DW 00750h, 00351h, 00352h, 00753h, 00354h, 00755h, 00756h, 00357h
4172: DW 00B58h, 00F59h, 00354h, 00755h, 00756h, 00357h, 00B58h, 00F59h
4173: DW 02760h, 02361h, 02362h, 02763h, 02364h, 02765h, 02766h, 02367h
4174: DW 02B68h, 02F69h, 02364h, 02765h, 02766h, 02367h, 02B68h, 02F69h
4175: DW 02370h, 02771h, 02772h, 02373h, 02774h, 02375h, 02376h, 02777h
4176: DW 02F78h, 02B79h, 02774h, 02375h, 02376h, 02777h, 02F78h, 02B79h
4177: DW 08380h, 08781h, 08782h, 08383h, 08784h, 08385h, 08386h, 08787h
4178: DW 08F88h, 08B89h, 08784h, 08385h, 08386h, 08787h, 08F88h, 08B89h
4179: DW 08790h, 08391h, 08392h, 08793h, 08394h, 08795h, 08796h, 08397h
4180: DW 08B98h, 08F99h, 08394h, 08795h, 08796h, 08397h, 08B98h, 08F99h
4181: DW 0A7A0h, 0A3A1h, 0A3A2h, 0A7A3h, 0A3A4h, 0A7A5h, 0A7A6h, 0A3A7h
4182: DW 0ABA8h, 0AFA9h, 0A3A4h, 0A7A5h, 0A7A6h, 0A3A7h, 0ABA8h, 0AFA9h
4183: DW 0A3B0h, 0A7B1h, 0A7B2h, 0A3B3h, 0A7B4h, 0A3B5h, 0A3B6h, 0A7B7h
4184: DW 0AFB8h, 0ABB9h, 0A7B4h, 0A3B5h, 0A3B6h, 0A7B7h, 0AFB8h, 0ABB9h
4185: DW 087C0h, 083C1h, 083C2h, 087C3h, 083C4h, 087C5h, 087C6h, 083C7h
4186: DW 08BC8h, 08FC9h, 083C4h, 087C5h, 087C6h, 083C7h, 08BC8h, 08FC9h
4187: DW 083D0h, 087D1h, 087D2h, 083D3h, 087D4h, 083D5h, 083D6h, 087D7h
4188: DW 08FD8h, 08BD9h, 087D4h, 083D5h, 083D6h, 087D7h, 08FD8h, 08BD9h
4189: DW 0A3E0h, 0A7E1h, 0A7E2h, 0A3E3h, 0A7E4h, 0A3E5h, 0A3E6h, 0A7E7h
4190: DW 0AFE8h, 0ABE9h, 0A7E4h, 0A3E5h, 0A3E6h, 0A7E7h, 0AFE8h, 0ABE9h
4191: DW 0A7F0h, 0A3F1h, 0A3F2h, 0A7F3h, 0A3F4h, 0A7F5h, 0A7F6h, 0A3F7h
4192: DW 0ABF8h, 0AFF9h, 0A3F4h, 0A7F5h, 0A7F6h, 0A3F7h, 0ABF8h, 0AFF9h
4193: DW 04700h, 00301h, 00302h, 00703h, 00304h, 00705h, 00706h, 00307h
4194: DW 00B08h, 00F09h, 00304h, 00705h, 00706h, 00307h, 00B08h, 00F09h
4195: DW 00310h, 00711h, 00712h, 00313h, 00714h, 00315h, 00316h, 00717h
4196: DW 00F18h, 00B19h, 00714h, 00315h, 00316h, 00717h, 00F18h, 00B19h
4197: DW 02320h, 02721h, 02722h, 02323h, 02724h, 02325h, 02326h, 02727h
4198: DW 02F28h, 02B29h, 02724h, 02325h, 02326h, 02727h, 02F28h, 02B29h
4199: DW 02730h, 02331h, 02332h, 02733h, 02334h, 02735h, 02736h, 02337h
4200: DW 02B38h, 02F39h, 02334h, 02735h, 02736h, 02337h, 02B38h, 02F39h
4201: DW 00340h, 00741h, 00742h, 00343h, 00744h, 00345h, 00346h, 00747h
4202: DW 00F48h, 00B49h, 00744h, 00345h, 00346h, 00747h, 00F48h, 00B49h
4203: DW 00750h, 00351h, 00352h, 00753h, 00354h, 00755h, 00756h, 00357h
4204: DW 00B58h, 00F59h, 00354h, 00755h, 00756h, 00357h, 00B58h, 00F59h
4205: DW 02760h, 02361h, 02362h, 02763h, 02364h, 02765h, 02766h, 02367h
4206: DW 02B68h, 02F69h, 02364h, 02765h, 02766h, 02367h, 02B68h, 02F69h
4207: DW 02370h, 02771h, 02772h, 02373h, 02774h, 02375h, 02376h, 02777h
4208: DW 02F78h, 02B79h, 02774h, 02375h, 02376h, 02777h, 02F78h, 02B79h
4209: DW 08380h, 08781h, 08782h, 08383h, 08784h, 08385h, 08386h, 08787h
4210: DW 08F88h, 08B89h, 08784h, 08385h, 08386h, 08787h, 08F88h, 08B89h
4211: DW 08790h, 08391h, 08392h, 08793h, 08394h, 08795h, 08796h, 08397h
4212: DW 08B98h, 08F99h, 08394h, 08795h, 08796h, 08397h, 08B98h, 08F99h
4213: DW 00406h, 00007h, 00808h, 00C09h, 00C0Ah, 0080Bh, 00C0Ch, 0080Dh
4214: DW 0080Eh, 00C0Fh, 01010h, 01411h, 01412h, 01013h, 01414h, 01015h
4215: DW 00016h, 00417h, 00C18h, 00819h, 0081Ah, 00C1Bh, 0081Ch, 00C1Dh
4216: DW 00C1Eh, 0081Fh, 03020h, 03421h, 03422h, 03023h, 03424h, 03025h
4217: DW 02026h, 02427h, 02C28h, 02829h, 0282Ah, 02C2Bh, 0282Ch, 02C2Dh
4218: DW 02C2Eh, 0282Fh, 03430h, 03031h, 03032h, 03433h, 03034h, 03435h
4219: DW 02436h, 02037h, 02838h, 02C39h, 02C3Ah, 0283Bh, 02C3Ch, 0283Dh
4220: DW 0283Eh, 02C3Fh, 01040h, 01441h, 01442h, 01043h, 01444h, 01045h
4221: DW 00046h, 00447h, 00C48h, 00849h, 0084Ah, 00C4Bh, 0084Ch, 00C4Dh
4222: DW 00C4Eh, 0084Fh, 01450h, 01051h, 01052h, 01453h, 01054h, 01455h
4223: DW 00456h, 00057h, 00858h, 00C59h, 00C5Ah, 0085Bh, 00C5Ch, 0085Dh
4224: DW 0085Eh, 00C5Fh, 03460h, 03061h, 03062h, 03463h, 03064h, 03465h
4225: DW 02466h, 02067h, 02868h, 02C69h, 02C6Ah, 0286Bh, 02C6Ch, 0286Dh
4226: DW 0286Eh, 02C6Fh, 03070h, 03471h, 03472h, 03073h, 03474h, 03075h
4227: DW 02076h, 02477h, 02C78h, 02879h, 0287Ah, 02C7Bh, 0287Ch, 02C7Dh
4228: DW 02C7Eh, 0287Fh, 09080h, 09481h, 09482h, 09083h, 09484h, 09085h
4229: DW 08086h, 08487h, 08C88h, 08889h, 0888Ah, 08C8Bh, 0888Ch, 08C8Dh
4230: DW 08C8Eh, 0888Fh, 09490h, 09091h, 09092h, 09493h, 09094h, 09495h
4231: DW 08496h, 08097h, 08898h, 08C99h, 08C9Ah, 0889Bh, 08C9Ch, 0889Dh
4232: DW 0889Eh, 08C9Fh, 05500h, 01101h, 01102h, 01503h, 01104h, 01505h
4233: DW 00506h, 00107h, 00908h, 00D09h, 00D0Ah, 0090Bh, 00D0Ch, 0090Dh
4234: DW 0090Eh, 00D0Fh, 01110h, 01511h, 01512h, 01113h, 01514h, 01115h
4235: DW 00116h, 00517h, 00D18h, 00919h, 0091Ah, 00D1Bh, 0091Ch, 00D1Dh
4236: DW 00D1Eh, 0091Fh, 03120h, 03521h, 03522h, 03123h, 03524h, 03125h
4237: DW 02126h, 02527h, 02D28h, 02929h, 0292Ah, 02D2Bh, 0292Ch, 02D2Dh
4238: DW 02D2Eh, 0292Fh, 03530h, 03131h, 03132h, 03533h, 03134h, 03535h
4239: DW 02536h, 02137h, 02938h, 02D39h, 02D3Ah, 0293Bh, 02D3Ch, 0293Dh
4240: DW 0293Eh, 02D3Fh, 01140h, 01541h, 01542h, 01143h, 01544h, 01145h
4241: DW 00146h, 00547h, 00D48h, 00949h, 0094Ah, 00D4Bh, 0094Ch, 00D4Dh
4242: DW 00D4Eh, 0094Fh, 01550h, 01151h, 01152h, 01553h, 01154h, 01555h
4243: DW 00556h, 00157h, 00958h, 00D59h, 00D5Ah, 0095Bh, 00D5Ch, 0095Dh
4244: DW 0095Eh, 00D5Fh, 03560h, 03161h, 03162h, 03563h, 03164h, 03565h
4245: DW 02566h, 02167h, 02968h, 02D69h, 02D6Ah, 0296Bh, 02D6Ch, 0296Dh
4246: DW 0296Eh, 02D6Fh, 03170h, 03571h, 03572h, 03173h, 03574h, 03175h
4247: DW 02176h, 02577h, 02D78h, 02979h, 0297Ah, 02D7Bh, 0297Ch, 02D7Dh
4248: DW 02D7Eh, 0297Fh, 09180h, 09581h, 09582h, 09183h, 09584h, 09185h
4249: DW 08186h, 08587h, 08D88h, 08989h, 0898Ah, 08D8Bh, 0898Ch, 08D8Dh
4250: DW 08D8Eh, 0898Fh, 09590h, 09191h, 09192h, 09593h, 09194h, 09595h
4251: DW 08596h, 08197h, 08998h, 08D99h, 08D9Ah, 0899Bh, 08D9Ch, 0899Dh
4252: DW 0899Eh, 08D9Fh, 0B5A0h, 0B1A1h, 0B1A2h, 0B5A3h, 0B1A4h, 0B5A5h
4253: DW 0A5A6h, 0A1A7h, 0A9A8h, 0ADA9h, 0ADAAh, 0A9ABh, 0ADACh, 0A9ADh
4254: DW 0A9AEh, 0ADAFh, 0B1B0h, 0B5B1h, 0B5B2h, 0B1B3h, 0B5B4h, 0B1B5h
4255: DW 0A1B6h, 0A5B7h, 0ADB8h, 0A9B9h, 0A9BAh, 0ADBBh, 0A9BCh, 0ADBDh
4256: DW 0ADBEh, 0A9BFh, 095C0h, 091C1h, 091C2h, 095C3h, 091C4h, 095C5h
4257: DW 085C6h, 081C7h, 089C8h, 08DC9h, 08DCAh, 089CBh, 08DCCh, 089CDh
4258: DW 089CEh, 08DCFh, 091D0h, 095D1h, 095D2h, 091D3h, 095D4h, 091D5h
4259: DW 081D6h, 085D7h, 08DD8h, 089D9h, 089DAh, 08DDBh, 089DCh, 08DDDh
4260: DW 08DDEh, 089DFh, 0B1E0h, 0B5E1h, 0B5E2h, 0B1E3h, 0B5E4h, 0B1E5h
4261: DW 0A1E6h, 0A5E7h, 0ADE8h, 0A9E9h, 0A9EAh, 0ADEBh, 0A9ECh, 0ADEDh
4262: DW 0ADEEh, 0A9EFh, 0B5F0h, 0B1F1h, 0B1F2h, 0B5F3h, 0B1F4h, 0B5F5h
4263: DW 0A5F6h, 0A1F7h, 0A9F8h, 0ADF9h, 0ADFAh, 0A9FBh, 0ADFCh, 0A9FDh
4264: DW 0A9FEh, 0ADFFh, 05500h, 01101h, 01102h, 01503h, 01104h, 01505h
4265: DW 00506h, 00107h, 00908h, 00D09h, 00D0Ah, 0090Bh, 00D0Ch, 0090Dh
4266: DW 0090Eh, 00D0Fh, 01110h, 01511h, 01512h, 01113h, 01514h, 01115h
4267: DW 00116h, 00517h, 00D18h, 00919h, 0091Ah, 00D1Bh, 0091Ch, 00D1Dh
4268: DW 00D1Eh, 0091Fh, 03120h, 03521h, 03522h, 03123h, 03524h, 03125h
4269: DW 02126h, 02527h, 02D28h, 02929h, 0292Ah, 02D2Bh, 0292Ch, 02D2Dh
4270: DW 02D2Eh, 0292Fh, 03530h, 03131h, 03132h, 03533h, 03134h, 03535h
4271: DW 02536h, 02137h, 02938h, 02D39h, 02D3Ah, 0293Bh, 02D3Ch, 0293Dh
4272: DW 0293Eh, 02D3Fh, 01140h, 01541h, 01542h, 01143h, 01544h, 01145h
4273: DW 00146h, 00547h, 00D48h, 00949h, 0094Ah, 00D4Bh, 0094Ch, 00D4Dh
4274: DW 00D4Eh, 0094Fh, 01550h, 01151h, 01152h, 01553h, 01154h, 01555h
4275: DW 00556h, 00157h, 00958h, 00D59h, 00D5Ah, 0095Bh, 00D5Ch, 0095Dh
4276: DW 0095Eh, 00D5Fh, 03560h, 03161h, 03162h, 03563h, 03164h, 03565h
4277: DW 0BEFAh, 0BAFBh, 0BEFCh, 0BAFDh, 0BAFEh, 0BEFFh, 04600h, 00201h
4278: DW 00202h, 00603h, 00204h, 00605h, 00606h, 00207h, 00A08h, 00E09h
4279: DW 01E0Ah, 01A0Bh, 01E0Ch, 01A0Dh, 01A0Eh, 01E0Fh, 00210h, 00611h
4280: DW 00612h, 00213h, 00614h, 00215h, 00216h, 00617h, 00E18h, 00A19h
4281: DW 01A1Ah, 01E1Bh, 01A1Ch, 01E1Dh, 01E1Eh, 01A1Fh, 02220h, 02621h
4282: DW 02622h, 02223h, 02624h, 02225h, 02226h, 02627h, 02E28h, 02A29h
4283: DW 03A2Ah, 03E2Bh, 03A2Ch, 03E2Dh, 03E2Eh, 03A2Fh, 02630h, 02231h
4284: DW 02232h, 02633h, 02234h, 02635h, 02636h, 02237h, 02A38h, 02E39h
4285: DW 03E3Ah, 03A3Bh, 03E3Ch, 03A3Dh, 03A3Eh, 03E3Fh, 00240h, 00641h
4286: DW 00642h, 00243h, 00644h, 00245h, 00246h, 00647h, 00E48h, 00A49h
4287: DW 01A4Ah, 01E4Bh, 01A4Ch, 01E4Dh, 01E4Eh, 01A4Fh, 00650h, 00251h
4288: DW 00252h, 00653h, 00254h, 00655h, 00656h, 00257h, 00A58h, 00E59h
4289: DW 01E5Ah, 01A5Bh, 01E5Ch, 01A5Dh, 01A5Eh, 01E5Fh, 02660h, 02261h
4290: DW 02262h, 02663h, 02264h, 02665h, 02666h, 02267h, 02A68h, 02E69h
4291: DW 03E6Ah, 03A6Bh, 03E6Ch, 03A6Dh, 03A6Eh, 03E6Fh, 02270h, 02671h
4292: DW 02672h, 02273h, 02674h, 02275h, 02276h, 02677h, 02E78h, 02A79h
4293: DW 03A7Ah, 03E7Bh, 03A7Ch, 03E7Dh, 03E7Eh, 03A7Fh, 08280h, 08681h
4294: DW 08682h, 08283h, 08684h, 08285h, 08286h, 08687h, 08E88h, 08A89h
4295: DW 09A8Ah, 09E8Bh, 09A8Ch, 09E8Dh, 09E8Eh, 09A8Fh, 08690h, 08291h
4296: DW 08292h, 08693h, 02334h, 02735h, 02736h, 02337h, 02B38h, 02F39h
4297: DW 03F3Ah, 03B3Bh, 03F3Ch, 03B3Dh, 03B3Eh, 03F3Fh, 00340h, 00741h
4298: DW 00742h, 00343h, 00744h, 00345h, 00346h, 00747h, 00F48h, 00B49h
4299: DW 01B4Ah, 01F4Bh, 01B4Ch, 01F4Dh, 01F4Eh, 01B4Fh, 00750h, 00351h
4300: DW 00352h, 00753h, 00354h, 00755h, 00756h, 00357h, 00B58h, 00F59h
4301: DW 01F5Ah, 01B5Bh, 01F5Ch, 01B5Dh, 01B5Eh, 01F5Fh, 02760h, 02361h
4302: DW 02362h, 02763h, 02364h, 02765h, 02766h, 02367h, 02B68h, 02F69h
4303: DW 03F6Ah, 03B6Bh, 03F6Ch, 03B6Dh, 03B6Eh, 03F6Fh, 02370h, 02771h
4304: DW 02772h, 02373h, 02774h, 02375h, 02376h, 02777h, 02F78h, 02B79h
4305: DW 03B7Ah, 03F7Bh, 03B7Ch, 03F7Dh, 03F7Eh, 03B7Fh, 08380h, 08781h
4306: DW 08782h, 08383h, 08784h, 08385h, 08386h, 08787h, 08F88h, 08B89h
4307: DW 09B8Ah, 09F8Bh, 09B8Ch, 09F8Dh, 09F8Eh, 09B8Fh, 08790h, 08391h
4308: DW 08392h, 08793h, 08394h, 08795h, 08796h, 08397h, 08B98h, 08F99h
4309: DW 09F9Ah, 09B9Bh, 09F9Ch, 09B9Dh, 09B9Eh, 09F9Fh, 0A7A0h, 0A3A1h
4310: DW 0A3A2h, 0A7A3h, 0A3A4h, 0A7A5h, 0A7A6h, 0A3A7h, 0ABA8h, 0AFA9h
4311: DW 0BFAAh, 0BBABh, 0BFACh, 0BBADh, 0BBAEh, 0BFAFh, 0A3B0h, 0A7B1h
4312: DW 0A7B2h, 0A3B3h, 0A7B4h, 0A3B5h, 0A3B6h, 0A7B7h, 0AFB8h, 0ABB9h
4313: DW 0BBBAh, 0BFBBh, 0BBBCh, 0BFBDh, 0BFBEh, 0BBBFh, 087C0h, 083C1h
4314: DW 083C2h, 087C3h, 083C4h, 087C5h, 087C6h, 083C7h, 08BC8h, 08FC9h
4315: DW 09FCAh, 09BCBh, 09FCCh, 09BCDh, 09BCEh, 09FCFh, 083D0h, 087D1h
4316: DW 087D2h, 083D3h, 087D4h, 083D5h, 083D6h, 087D7h, 08FD8h, 08BD9h
4317: DW 09BDAh, 09FDBh, 09BDCh, 09FDDh, 09FDEh, 09BDFh, 0A3E0h, 0A7E1h
4318: DW 0A7E2h, 0A3E3h, 0A7E4h, 0A3E5h, 0A3E6h, 0A7E7h, 0AFE8h, 0ABE9h
4319: DW 0BBEAh, 0BFEBh, 0BBECh, 0BFEDh, 0BFEEh, 0BBEFh, 0A7F0h, 0A3F1h
4320: DW 0A3F2h, 0A7F3h, 0A3F4h, 0A7F5h, 0A7F6h, 0A3F7h, 0ABF8h, 0AFF9h
4321: DW 0BFFAh, 0BBFBh, 0BFFCh, 0BBFDh, 0BBFEh, 0BFFFh, 04700h, 00301h
4322: DW 00302h, 00703h, 00304h, 00705h, 00706h, 00307h, 00B08h, 00F09h
4323: DW 01F0Ah, 01B0Bh, 01F0Ch, 01B0Dh, 01B0Eh, 01F0Fh, 00310h, 00711h
4324: DW 00712h, 00313h, 00714h, 00315h, 00316h, 00717h, 00F18h, 00B19h
4325: DW 01B1Ah, 01F1Bh, 01B1Ch, 01F1Dh, 01F1Eh, 01B1Fh, 02320h, 02721h
4326: DW 02722h, 02323h, 02724h, 02325h, 02326h, 02727h, 02F28h, 02B29h
4327: DW 03B2Ah, 03F2Bh, 03B2Ch, 03F2Dh, 03F2Eh, 03B2Fh, 02730h, 02331h
4328: DW 02332h, 02733h, 02334h, 02735h, 02736h, 02337h, 02B38h, 02F39h
4329: DW 03F3Ah, 03B3Bh, 03F3Ch, 03B3Dh, 03B3Eh, 03F3Fh, 00340h, 00741h
4330: DW 00742h, 00343h, 00744h, 00345h, 00346h, 00747h, 00F48h, 00B49h
4331: DW 01B4Ah, 01F4Bh, 01B4Ch, 01F4Dh, 01F4Eh, 01B4Fh, 00750h, 00351h
4332: DW 00352h, 00753h, 00354h, 00755h, 00756h, 00357h, 00B58h, 00F59h
4333: DW 01F5Ah, 01B5Bh, 01F5Ch, 01B5Dh, 01B5Eh, 01F5Fh, 02760h, 02361h
4334: DW 02362h, 02763h, 02364h, 02765h, 02766h, 02367h, 02B68h, 02F69h
4335: DW 03F6Ah, 03B6Bh, 03F6Ch, 03B6Dh, 03B6Eh, 03F6Fh, 02370h, 02771h
4336: DW 02772h, 02373h, 02774h, 02375h, 02376h, 02777h, 02F78h, 02B79h
4337: DW 03B7Ah, 03F7Bh, 03B7Ch, 03F7Dh, 03F7Eh, 03B7Fh, 08380h, 08781h
4338: DW 08782h, 08383h, 08784h, 08385h, 08386h, 08787h, 08F88h, 08B89h
4339: DW 09B8Ah, 09F8Bh, 09B8Ch, 09F8Dh, 09F8Eh, 09B8Fh, 08790h, 08391h
4340: DW 08392h, 08793h, 08394h, 08795h, 08796h, 08397h, 08B98h, 08F99h
4341:
4342: NEG_Table:
4343: DB 0,66,255,187,254,187,253,187,252,187,251,187,250,187,249,187,248,187,247,179
4344: DB 246,179,245,179,244,179,243,179,242,179,241,179,240,163,239,187,238,187,237,187
4345: DB 236,187,235,187,234,187,233,187,232,187,231,179,230,179,229,179,228,179,227,179
4346: DB 226,179,225,179,224,163,223,155,222,155,221,155,220,155,219,155,218,155,217,155
4347: DB 216,155,215,147,214,147,213,147,212,147,211,147,210,147,209,147,208,131,207,155
4348: DB 206,155,205,155,204,155,203,155,202,155,201,155,200,155,199,147,198,147,197,147
4349: DB 196,147,195,147,194,147,193,147,192,131,191,187,190,187,189,187,188,187,187,187
4350: DB 186,187,185,187,184,187,183,179,182,179,181,179,180,179,179,179,178,179,177,179
4351: DB 176,163,175,187,174,187,173,187,172,187,171,187,170,187,169,187,168,187,167,179
4352: DB 166,179,165,179,164,179,163,179,162,179,161,179,160,163,159,155,158,155,157,155
4353: DB 156,155,155,155,154,155,153,155,152,155,151,147,150,147,149,147,148,147,147,147
4354: DB 146,147,145,147,144,131,143,155,142,155,141,155,140,155,139,155,138,155,137,155
4355: DB 136,155,135,147,134,147,133,147,132,147,131,147,130,147,129,147,128,135,127,59
4356: DB 126,59,125,59,124,59,123,59,122,59,121,59,120,59,119,51,118,51,117,51
4357: DB 116,51,115,51,114,51,113,51,112,35,111,59,110,59,109,59,108,59,107,59
4358: DB 106,59,105,59,104,59,103,51,102,51,101,51,100,51,99,51,98,51,97,51
4359: DB 96,35,95,27,94,27,93,27,92,27,91,27,90,27,89,27,88,27,87,19
4360: DB 86,19,85,19,84,19,83,19,82,19,81,19,80,3,79,27,78,27,77,27
4361: DB 76,27,75,27,74,27,73,27,72,27,71,19,70,19,69,19,68,19,67,19
4362: DB 66,19,65,19,64,3,63,59,62,59,61,59,60,59,59,59,58,59,57,59
4363: DB 56,59,55,51,54,51,53,51,52,51,51,51,50,51,49,51,48,35,47,59
4364: DB 46,59,45,59,44,59,43,59,42,59,41,59,40,59,39,51,38,51,37,51
4365: DB 36,51,35,51,34,51,33,51,32,35,31,27,30,27,29,27,28,27,27,27
4366: DB 26,27,25,27,24,27,23,19,22,19,21,19,20,19,19,19,18,19,17,19
4367: DB 16,3,15,27,14,27,13,27,12,27,11,27,10,27,9,27,8,27,7,19
4368: DB 6,19,5,19,4,19,3,19,2,19,1,19
4369:
4370: ;- the end ------ (blimey) --------------------------------------------------;
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.