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1.1 root 1: ;----------------------------------------------------------------------------;
2: ; RAZE-x86 Z80 emulator.
3: ; version 1.06
4: ;
5: ; Copyright (c) 1999 Richard Mitton
6: ;
7: ; This may only be distributed as part of the complete RAZE package.
8: ; See RAZE.TXT for license information.
9: ;----------------------------------------------------------------------------;
10:
1.1.1.2 ! root 11: ; this is needed for compiling with allegro in coff mode
! 12: %macro cglobal 1
! 13: global %1
! 14: %endmacro
! 15: ;%macro cglobal 1
! 16: ; global _%1
! 17: ; %define %1 _%1
! 18: ;%endmacro
1.1 root 19:
20: ; You are not expected to understand this.
21:
22:
23: ;----------------------------------------------------------------------------;
24: ; Comment these in/out for faster speed (less accurate):
25: %define EMULATE_UNDOC_FLAGS ; a couple of undocumented flags
26: %define EMULATE_BITS_3_5 ; bits 3/5 of the flags (undocumented)
27: %define EMULATE_WEIRD_STUFF ; misc *very obscure* undocumented behaviour
28: %define EMULATE_R_REGISTER ; precise R register (not usually needed)
29: ;;;;%define USE_FETCH_CALLBACK ; call a callback for every fetch (slow!)
30: ;----------------------------------------------------------------------------;
31:
32: ; Registers:
33: ; AF = ax (flags in AH)
34: ; HL = bx
35: ; BC = cx
36: ; PC = si
37: ; R = ebp
38: ;
39: ; GCC wants EBX, ESI, EDI, ESP, and EBP to be preserved at all times
40: ; DH should always be clear between macros
41: ; The high 16-bits of all registers should be clear at all times (except EBP)
42: ; This assumes LAHF will set bit 1 of AH. (supposed to be undefined...)
43:
44: BITS 32
45: SECTION .bss USE32
46:
47: ; Maximum number of memory handlers
48: %define MAX_MEM_HANDLERS 64
49:
50: ; The current context
51: align 16
52: context_start:
53: z80_AF resd 1
54: z80_BC resd 1
55: z80_DE resd 1
56: z80_HL resd 1
57: z80_IX resd 1
58: z80_IY resd 1
59: z80_PC resd 1
60: z80_SP resd 1
61: z80_AF2 resd 1
62: z80_BC2 resd 1
63: z80_DE2 resd 1
64: z80_HL2 resd 1
65: z80_IFF1 resb 1
66: z80_IFF2 resb 1
67: z80_R resd 1
68: z80_R2 resd 1
69: z80_I resb 1
70: z80_flag35 resb 1
71: z80_IM resb 1
72: z80_IRQVector resb 1
73: z80_IRQLine resb 1
74: z80_halted resb 1
75: z80_Extra_Cycles resd 1
76: registers_end:
77:
78: z80_Fetch resd 256
79: z80_Read resd (256*2)
80: z80_Write resd (256*2)
81: z80_In resd 1
82: z80_Out resd 1
83: z80_RetI resd 1
84: z80_Fetch_Callback resd 1
85: _read_handlers resd 4*MAX_MEM_HANDLERS
86: _write_handlers resd 4*MAX_MEM_HANDLERS
87: context_end:
88: resd 1 ; safety gap, so z80_reset can use 32-bit transfers
89:
90: ; Variables
91: z80_ICount resd 1
92: z80_Initial_ICount resd 1
93: z80_TempICount resd 1
94: z80_afterEI resb 1
95:
96: SECTION .text USE32
97: ;----------------------------------------------------------------------------;
98: ; Prepare to call a GCC function
99: %macro CALLGCC_START 0
100: mov [z80_AF], ezAF ; eax
101: mov [z80_BC], ezBC ; ecx
102: mov [z80_PC], ezPC ; esi
103: mov [z80_R], zR ; ebp
104: %endmacro
105:
106: ; Return from a GCC function
107: %macro CALLGCC_END 0
108: mov ezAF, [z80_AF] ; eax
109: mov ezBC, [z80_BC] ; ecx
110: mov ezPC, [z80_PC] ; esi
111: mov zR, [z80_R] ; ebp
112: %endmacro
113:
114: ; Read a byte from the PC, into DL
115: ; GETBYTE
116: %macro GETBYTE 0
117: %ifdef USE_FETCH_CALLBACK
118: CALLGCC_START
119: push ezPC
120: call [z80_Fetch_Callback]
121: add esp, 4
122: CALLGCC_END
123: %endif
124: mov edx, ezPC
125: shr edx, 8
126: mov edi, [z80_Fetch+edx*4]
127:
128: mov dl, [edi+ezPC]
129: inc zPC
130: xor edi, edi
131: %endmacro
132:
133: ; Read a byte from the PC, sign-extended into DI
134: ; GETDISP
135: %macro GETDISP 0
136: %ifdef USE_FETCH_CALLBACK
137: CALLGCC_START
138: push ezPC
139: call [z80_Fetch_Callback]
140: add esp, 4
141: CALLGCC_END
142: %endif
143: mov edx, ezPC
144: shr edx, 8
145: mov edx, [z80_Fetch+edx*4]
146:
147: movsx di, [edx+ezPC]
148: inc zPC
149: xor edx, edx
150: %endmacro
151:
152: ; Read a word from the PC, into DI
153: ; GETWORD
154: %macro GETWORD 0
155: %ifdef USE_FETCH_CALLBACK
156: CALLGCC_START
157: push ezPC
158: call [z80_Fetch_Callback]
159: add esp, 4
160: CALLGCC_END
161: %endif
162: mov [z80_BC], ezBC
163: mov edx, ezPC ; low byte
164: shr edx, 8
165: mov edi, [z80_Fetch+edx*4]
166:
167: mov dl, [edi+ezPC]
168: inc zPC
169:
170: %ifdef USE_FETCH_CALLBACK
171: push edx
172: CALLGCC_START
173: push ezPC
174: call [z80_Fetch_Callback]
175: add esp, 4
176: CALLGCC_END
177: pop edx
178: %endif
179: mov ecx, ezPC ; high byte
180: shr ecx, 8
181: mov edi, [z80_Fetch+ecx*4]
182:
183: mov dh, [edi+ezPC]
184: inc zPC
185: mov edi, edx
186: mov ezBC, [z80_BC]
187: xor edx, edx
188: %endmacro
189:
190: ; Read a byte from memory (DI) into DL
191: ; MEMREAD
192: %macro MEMREAD 0
193: CALLGCC_START
194: mov edx, edi
195: shr edx, 8
196: mov ecx, [z80_Read+edx*8]
197:
198: test ecx, ecx ; if handler exists, call it
199: jnz %%handler
200: ; no handler, so go direct
201: mov ecx, [z80_Read+edx*8+4]
202: mov dl, [ecx+edi]
203: jmp %%finish
204:
205: %%handler:
206: push edi
207: call ecx
208: xor edx, edx
209: add esp, 4
210: mov dl, al
211: %%finish:
212: CALLGCC_END
213: %endmacro
214:
215: ; Write a byte in DL to memory (DI)
216: %macro MEMWRITE 0
217: CALLGCC_START
218: xor eax, eax
219: mov al, dl
220:
221: mov edx, edi
222: shr edx, 8
223: mov ecx, [z80_Write+edx*8]
224:
225: test ecx, ecx ; if handler exists, call it
226: jnz %%handler
227: ; no handler, so go direct
228: mov ecx, [z80_Write+edx*8+4]
229: mov [ecx+edi], al
230: jmp %%finish
231:
232: %%handler:
233: push eax
234: push edi
235: call ecx
236: add esp, 8
237: %%finish:
238: CALLGCC_END
239: xor edx, edx
240: %endmacro
241:
242: ; Read a byte from port (DI) into DL
243: ; IOREAD
244: %macro IOREAD 0
245: push edi
246: CALLGCC_START
247: call [z80_In]
248: xor edx, edx
249: add esp, 4
250: mov dl, al
251: CALLGCC_END
252: %endmacro
253:
254: ; Write a byte in DL to port (DI)
255: %macro IOWRITE 0
256: CALLGCC_START
257: xor dh, dh
258: push edx
259: push edi
260: call [z80_Out]
261: add esp, 8
262: CALLGCC_END
263: xor edx, edx
264: %endmacro
265:
266: ; Align code to the default boundary
267: %macro ALIGN 0
268: align 4
269: %endmacro
270:
271: ; Define an instruction
272: ; DEF prefix, opcode, std_cycles, extra_cycles
273: %macro DEF 4
274: ALIGN
275: %define std_cycles %3
276: %define extra_cycles %4
277: %{1}_%2:
278: %endmacro
279:
280: ; Subtract the clock cycles for this instruction from the ICount
281: %macro DO_CYCLES 0
282: sub dword [z80_ICount], std_cycles
283: jbe near z80_finish
284: %endmacro
285:
286: ; Subtract the extra clock cycles for this instruction from the ICount
287: %macro DO_EXTRA_CYCLES 0
288: sub dword [z80_ICount], extra_cycles
289: jbe near z80_finish
290: %endmacro
291:
292: ; Finish straight away
293: %macro EXIT 0
294: jmp z80_finish
295: %endmacro
296:
297: ; Jump to the next instruction
298: %macro NEXT 0
299: %ifdef EMULATE_R_REGISTER
300: inc zR
301: %endif
302: GETBYTE
303: jmp [OpTable+edx*4]
304: %endmacro
305:
306: ; Check the IRQ line, cause an interrupt if needed
307: %macro CHECK_IRQ 0
308: cmp [z80_IRQLine], byte 0 ; check the IRQ line
309: je near %%finish
310: cmp [z80_IFF1], byte 0 ; check ints are enabled
311: je near %%finish
312:
313: ; disable interrupts
314: mov [z80_IFF1], byte 0
315: mov [z80_IFF2], byte 0
316: %ifdef EMULATE_R_REGISTER
317: inc zR
318: %endif
319:
320: mov [z80_halted], byte 0 ; Un-HALT the Z80
321:
322: mov edx, ezPC ; write the PC
323: dec zSP
324:
325: xchg dl, dh
326: mov edi, ezSP
327: MEMWRITE
328: dec zSP
329: mov edx, ezPC
330: mov edi, ezSP
331: MEMWRITE
332:
333: cmp [z80_IM], byte 0
334: jne %%not_im0
335: ; IM 0, 13 T-states
336: add [z80_Extra_Cycles], dword 13
337: mov dl, [z80_IRQVector]
338: sub dl, 0c7h
339: movzx ezPC, dl
340: jmp %%finish
341:
342: %%not_im0:
343: cmp [z80_IM], byte 1
344: jne %%not_im1
345: ; IM 1, 13 T-states
346: add [z80_Extra_Cycles], dword 13
347: mov ezPC, 38h
348: jmp %%finish
349:
350: %%not_im1:
351: ; IM 2, 19 T-states
352: add [z80_Extra_Cycles], dword 19
353: mov dl, [z80_IRQVector]
354: mov dh, zI
355: mov edi, edx
356: MEMREAD
357: inc di
358: mov ezPC, edx
359: MEMREAD
360: xchg dl, dh
361: or ezPC, edx
362: xor dh, dh
363: %%finish:
364: %endmacro
365:
366: ;----------------------------------------------------------------------------;
367: ; Helper functions
368:
369: ; Add A, %1
370: %macro DO_ADD 1
371: add zA, %1
372: %ifdef EMULATE_BITS_3_5
373: mov [z80_flag35], zA
374: %endif
375: lahf
376: jo %%set_overflow
377:
378: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C
379: jmp %%finish
380:
381: %%set_overflow:
382: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C
383: or zF, FLAG_P
384: %%finish:
385: %endmacro
386:
387: ; Sub A, %1
388: %macro DO_SUB 1
389: sub zA, %1
390: %ifdef EMULATE_BITS_3_5
391: mov [z80_flag35], zA
392: %endif
393: lahf
394: jo %%set_overflow
395:
396: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C|FLAG_N
397: jmp %%finish
398:
399: %%set_overflow:
400: or zF, FLAG_P
401: %%finish:
402: %endmacro
403:
404: ; Adc A, %1
405: %macro DO_ADC 1
406: ror zF, 1
407: adc zA, %1
408: %ifdef EMULATE_BITS_3_5
409: mov [z80_flag35], zA
410: %endif
411: lahf
412: jo %%set_overflow
413:
414: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C
415: jmp %%finish
416:
417: %%set_overflow:
418: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C
419: or zF, FLAG_P
420: %%finish:
421: %endmacro
422:
423: ; Sbc A, %1
424: %macro DO_SBC 1
425: ror zF, 1
426: sbb zA, %1
427: %ifdef EMULATE_BITS_3_5
428: mov [z80_flag35], zA
429: %endif
430: lahf
431: jo %%set_overflow
432:
433: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_C|FLAG_N
434: jmp %%finish
435:
436: %%set_overflow:
437: or zF, FLAG_P
438: %%finish:
439: %endmacro
440:
441: ; And A, %1
442: %macro DO_AND 1
443: and zA, %1
444: %ifdef EMULATE_BITS_3_5
445: mov [z80_flag35], zA
446: %endif
447: lahf
448: and zF, ~(FLAG_N|FLAG_C) ; clear N and carry
449: or zF, FLAG_H ; set half-carry
450: %endmacro
451:
452: ; Or A, %1
453: %macro DO_OR 1
454: or zA, %1
455: %ifdef EMULATE_BITS_3_5
456: mov [z80_flag35], zA
457: %endif
458: lahf
459: and zF, ~(FLAG_N|FLAG_C|FLAG_H) ; clear N, carry and half-carry
460: %endmacro
461:
462: ; Xor A, %1
463: %macro DO_XOR 1
464: xor zA, %1
465: %ifdef EMULATE_BITS_3_5
466: mov [z80_flag35], zA
467: %endif
468: lahf
469: and zF, ~(FLAG_N|FLAG_C|FLAG_H) ; clear N, carry and half-carry
470: %endmacro
471:
472: ; Cp A, %1
473: %macro DO_CP 1
474: %ifdef EMULATE_BITS_3_5
475: mov ah, %1
476: mov [z80_flag35], ah
477: %endif
478: cmp zA, %1
479: lahf
480: jo %%overflow
481:
482: and zF, ~FLAG_P ; clear the overflow
483: or zF, FLAG_N ; set the N flag
484: jmp %%finish
485:
486: %%overflow:
487: or zF, FLAG_P|FLAG_N ; set the overflow and N flag
488: %%finish:
489: %endmacro
490:
491: ; Inc %1
492: %macro DO_INC 1
493: and zF, FLAG_C ; leave carry alone
494: %ifnidn %1, dl
495: mov dl, %1
496: %endif
497: or zF, [INC_Table+edx]
498: inc %1
499: %ifdef EMULATE_BITS_3_5
500: %ifnidn %1, dl
501: inc dl
502: %endif
503: mov [z80_flag35], dl
504: %endif
505: %endmacro
506:
507: ; Dec %1
508: %macro DO_DEC 1
509: and zF, FLAG_C ; leave carry alone
510: %ifnidn %1, dl
511: mov dl, %1
512: %endif
513: or zF, [DEC_Table+edx]
514: dec %1
515: %ifdef EMULATE_BITS_3_5
516: %ifnidn %1, dl
517: dec dl
518: %endif
519: mov [z80_flag35], dl
520: %endif
521: %endmacro
522:
523: ; Add16 %1, %2
524: %macro DO_ADD16 2
525: %ifidn %2, dx
526: %error "DX used as parameter for DO_ADD16!"
527: %endif
528: mov edi, e%2
529: %ifdef EMULATE_UNDOC_FLAGS
530: mov edx, e%1
531: %endif
532: and zF, FLAG_S|FLAG_Z|FLAG_P
533:
534: add %1, di ; do it
535: adc zF, 0 ; merge the new carry in
536:
537: %ifdef EMULATE_UNDOC_FLAGS
538: xor edx, e%1 ; work out our new half-carry
539: xor edx, edi
540: and dh, FLAG_H
541: or zF, dh
542: %endif
543:
544: %ifdef EMULATE_BITS_3_5
545: mov dl, h%1
546: mov [z80_flag35], dl
547: %endif
548: %ifdef EMULATE_UNDOC_FLAGS
549: xor dh, dh
550: %endif
551: %endmacro
552:
553: ; Adc16 %1, %2
554: %macro DO_ADC16 2
555: %ifidn %2, dx
556: %error "DX used as parameter for DO_ADC16!"
557: %endif
558: mov edi, e%2
559: %ifdef EMULATE_UNDOC_FLAGS
560: mov edx, e%1
561: %endif
562: ror zF, 1 ; load the carry
563: adc %1, %2
564: lahf
565: jo %%overflow
566:
567: and zF, ~(FLAG_N|FLAG_H|FLAG_P) ; clear N,H and overflow
568: jmp %%finish
569:
570: %%overflow:
571: and zF, ~(FLAG_N|FLAG_H) ; clear N and H
572: or zF, FLAG_P ; set overflow
573: %%finish:
574:
575: %ifdef EMULATE_UNDOC_FLAGS
576: xor edx, e%1 ; work out our new half-carry
577: xor edx, edi
578: and dh, FLAG_H
579: or zF, dh
580: %endif
581:
582: %ifdef EMULATE_BITS_3_5
583: mov dl, h%1
584: mov [z80_flag35], dl
585: %endif
586: %ifdef EMULATE_UNDOC_FLAGS
587: xor dh, dh
588: %endif
589: %endmacro
590:
591: ; Sbc16 %1, %2
592: %macro DO_SBC16 2
593: %ifidn %2, dx
594: %error "DX used as parameter for DO_SBC16!"
595: %endif
596: %ifdef EMULATE_UNDOC_FLAGS
597: mov edi, e%2
598: %endif
599: mov edx, e%1
600: ror zF, 1 ; load the carry
601: sbb %1, %2
602: lahf
603: jo %%overflow
604:
605: and zF, ~(FLAG_P|FLAG_H) ; clear H and overflow
606: or zF, FLAG_N ; set N
607: jmp %%finish
608:
609: %%overflow:
610: or zF, FLAG_N|FLAG_P ; set overflow and N
611: and zF, ~FLAG_H ; clear H
612: %%finish:
613:
614: %ifdef EMULATE_UNDOC_FLAGS
615: xor edx, e%1 ; work out our new half-carry
616: xor edx, edi
617: and dh, FLAG_H
618: or zF, dh
619: %endif
620:
621: %ifdef EMULATE_BITS_3_5
622: mov dl, h%1
623: mov [z80_flag35], dl
624: %endif
625: %ifdef EMULATE_UNDOC_FLAGS
626: xor dh, dh
627: %endif
628: %endmacro
629:
630: ; Rotate method, reg8
631: %macro DO_ROT 2
632: %ifidn %1, RLA
633: mov dl, zF
634: and dl, FLAG_S|FLAG_Z|FLAG_P
635: sahf
636: rcl zA, 1
637: adc dl, 0
638: %ifdef EMULATE_BITS_3_5
639: mov [z80_flag35], zA
640: %endif
641: mov zF, dl
642: %elifidn %1, RRA
643: mov dl, zF
644: and dl, FLAG_S|FLAG_Z|FLAG_P
645: sahf
646: rcr zA, 1
647: adc dl, 0
648: %ifdef EMULATE_BITS_3_5
649: mov [z80_flag35], zA
650: %endif
651: mov zF, dl
652: %elifidn %1, RLCA
653: and zF, FLAG_S|FLAG_Z|FLAG_P
654: rol zA, 1
655: adc zF, 0
656: %ifdef EMULATE_BITS_3_5
657: mov [z80_flag35], zA
658: %endif
659: %elifidn %1, RRCA
660: and zF, FLAG_S|FLAG_Z|FLAG_P
661: ror zA, 1
662: adc zF, 0
663: %ifdef EMULATE_BITS_3_5
664: mov [z80_flag35], zA
665: %endif
666: %else
667: %ifnidn %2, dl
668: mov dl, %2
669: %endif
670:
671: %ifidn %1, RLC
672: rol dl, 1
673: %elifidn %1, RRC
674: ror dl, 1
675: %elifidn %1, RL
676: sahf
677: rcl dl, 1
678: %elifidn %1, RR
679: sahf
680: rcr dl, 1
681: %endif
682:
683: adc dh, dh
684: test dl, dl
685: lahf
686: and zF, FLAG_S|FLAG_Z|FLAG_P
687: or zF, dh
688: %ifdef EMULATE_BITS_3_5
689: mov [z80_flag35], dl
690: %endif
691: %ifnidn %2, dl
692: mov %2, dl
693: %endif
694: xor dh, dh
695: %endif
696: %endmacro
697:
698: ; Shift method, reg8
699: %macro DO_SHF 2
700: %ifnidn %2, dl
701: mov dl, %2
702: %endif
703:
704: %ifidn %1, SLA
705: add dl, dl
706: adc dh, dh
707: %elifidn %1, SLL
708: add dl, dl
709: adc dh, dh
710: inc dl
711: %elifidn %1, SRA
712: sar dl, 1
713: adc dh, dh
714: %elifidn %1, SRL
715: shr dl, 1
716: adc dh, dh
717: %endif
718:
719: test dl, dl
720: lahf
721: and zF, FLAG_S|FLAG_Z|FLAG_P
722: or zF, dh
723: %ifdef EMULATE_BITS_3_5
724: mov [z80_flag35], dl
725: %endif
726: %ifnidn %2, dl
727: mov %2, dl
728: %endif
729: xor dh, dh
730: %endmacro
731:
732: ; BIT r,n n = bit (0-7)
733: ; r = 8-bit register
734: %macro DO_BIT 2
735: and zF, FLAG_C
736: test %1, (1 << %2)
737: %ifdef EMULATE_BITS_3_5
738: ; bit 3 and 5 are set from the register
739: ; (actually they are bizarrely set, but
740: ; there's no point emulating that, it's just
741: ; plain silly...)
742: %ifnidn %1, dl
743: mov dl, %1 ; put in DL if not there already
744: %endif
745: mov [z80_flag35], dl
746: %endif
747:
748: jz %%bit_is_clear
749: %ifidn %2, 7
750: or zF, FLAG_H|FLAG_S ; set sign bit, if testing bit 7
751: %else
752: or zF, FLAG_H ; set half-carry, and parity
753: %endif
754: jmp %%finish
755:
756: %%bit_is_clear:
757: or zF, FLAG_H|FLAG_Z|FLAG_P ; set half-carry, parity, and zero
758: %%finish:
759: %endmacro
760:
761: ; SET r,n n = bit (0-7)
762: ; r = 8-bit register
763: %macro DO_SET 2
764: or %1, (1 << %2)
765: %endmacro
766:
767: ; RES r,n n = bit (0-7)
768: ; r = 8-bit register
769: %macro DO_RES 2
770: and %1, ~(1 << %2)
771: %endmacro
772:
773: ;----------------------------------------------------------------------------;
774: ; Here are the interface functions:
775:
776: ; Move a register to another
777: ; LD_R_R d8, s8 s8 = src reg, d8 = dest reg
778: %macro LD_R_R 2
779: %ifnidn %1, %2
780: %ifidn %2, D
781: mov dl, zD
782: mov z%1, dl
783: %elifidn %2, E
784: mov dl, zE
785: mov z%1, dl
786: %else
787: mov z%1, z%2
788: %endif
789: %endif
790: DO_CYCLES
791: NEXT
792: %endmacro
793:
794: ; Move a register to another (IXh/IXl)
795: ; LD_XYr_XYr d8, s8 s8 = src reg, d8 = dest reg
796: %macro LD_XYr_XYr 2
797: %ifnidn %1, %2
798: mov dl, z%2
799: mov z%1, dl
800: %endif
801: DO_CYCLES
802: NEXT
803: %endmacro
804:
805: ; Move an immediate byte into a register
806: ; LD_R_N d8 d8 = dest reg
807: %macro LD_R_N 1
808: GETBYTE
809: mov z%1, dl
810: DO_CYCLES
811: NEXT
812: %endmacro
813:
814: ; Move from (RR) into a register
815: ; LD_R_mRR d8, s16 d8 = dest reg, s16 = src reg
816: %macro LD_R_mRR 2
817: mov edi, ez%2
818: MEMREAD
819: mov z%1, dl
820: DO_CYCLES
821: NEXT
822: %endmacro
823:
824: ; Move from (XY+dd) into a register
825: ; LD_R_mXY d8, s16 d8 = dest reg, s16 = src reg
826: %macro LD_R_mXY 2
827: GETDISP
828: add di, z%2
829: MEMREAD
830: mov z%1, dl
831: DO_CYCLES
832: NEXT
833: %endmacro
834:
835: ; Move from a register into (RR)
836: ; LD_mRR_R d16, s8 d16 = destreg, s8 = src reg
837: %macro LD_mRR_R 2
838: mov edi, ez%1
839: mov dl, z%2
840: MEMWRITE
841: DO_CYCLES
842: NEXT
843: %endmacro
844:
845: ; Move from a register into (XY+dd)
846: ; LD_mXY_R d16, s8 d16 = dest reg, s8 = src reg
847: %macro LD_mXY_R 2
848: GETDISP
849: add di, z%1
850: mov dl, z%2
851: MEMWRITE
852: DO_CYCLES
853: NEXT
854: %endmacro
855:
856: ; Move an immediate into (RR)
857: ; LD_mRR_N d16 d16 = dest reg
858: %macro LD_mRR_N 1
859: GETBYTE
860: mov edi, ez%1
861: MEMWRITE
862: DO_CYCLES
863: NEXT
864: %endmacro
865:
866: ; Move an immediate into (XY+dd)
867: ; LD_mXY_N d16 d16 = dest reg
868: %macro LD_mXY_N 1
869: GETDISP
870: add di, z%1
871: push edi
872: GETBYTE
873: pop edi
874: MEMWRITE
875: DO_CYCLES
876: NEXT
877: %endmacro
878:
879: ; Move from (NN) into a register
880: ; LD_R_mNN d8 d8 = dest reg
881: %macro LD_R_mNN 1
882: GETWORD
883: MEMREAD
884: mov z%1, dl
885: DO_CYCLES
886: NEXT
887: %endmacro
888:
889: ; Move from a register into (NN)
890: ; LD_mNN_R s8 s8 = src reg
891: %macro LD_mNN_R 1
892: GETWORD
893: mov dl, z%1
894: MEMWRITE
895: DO_CYCLES
896: NEXT
897: %endmacro
898:
899: ; Move the Interrupt register into a register
900: ; LD_R_I d8 d8 = dest reg
901: %macro LD_R_I 1
902: mov z%1, zI
903: and zF, FLAG_C ; keep old carry
904: mov dl, zF
905:
906: test z%1, z%1
907: lahf
908: and zF, FLAG_S|FLAG_Z ; set S/Z from the I register
909: or zF, dl
910: or zF, [z80_IFF2]
911: %ifdef EMULATE_BITS_3_5
912: mov [z80_flag35], z%1
913: %endif
914: DO_CYCLES
915: NEXT
916: %endmacro
917:
918: ; Move a register into the Interrupt register
919: ; LD_I_R s8 s8 = src reg
920: %macro LD_I_R 1
921: mov zI, z%1
922: DO_CYCLES
923: NEXT
924: %endmacro
925:
926: ; Move the Refresh register into a register
927: ; LD_R_Rf d8 d8 = dest reg
928: %macro LD_R_Rf 1
929: mov edx, [z80_R2]
930: and edx, 80h ; take bits 0-6 from R, bit 7 from R2
931:
932: %ifndef EMULATE_R_REGISTER
933: ; attempt to fake the R-register
934: ; take the ICount, invert it, divide by 4
935: ; this produces an increasing counter, roughly proportional to
936: ; the number of instructions done
937: mov zR, [z80_ICount]
938: not zR
939: shr zR, 2
940: %endif
941:
942: and zR, 7fh
943: or edx, zR
944: mov z%1, dl
945:
946: mov dl, zF
947: and dl, FLAG_C ; keep the old carry
948:
949: test z%1, z%1
950: lahf
951: and zF, FLAG_S|FLAG_Z
952: or zF, dl
953: or zF, [z80_IFF2]
954: %ifdef EMULATE_BITS_3_5
955: mov [z80_flag35], z%1
956: %endif
957: DO_CYCLES
958: NEXT
959: %endmacro
960:
961: ; Move a register into the Refresh register
962: ; LD_Rf_R s8 s8 = src reg
963: %macro LD_Rf_R 1
964: mov dl, z%1
965: mov zR, edx
966: mov [z80_R2], edx
967: DO_CYCLES
968: NEXT
969: %endmacro
970:
971: ; Move a 16-bit immediate into a register
972: ; LD_RR_NN d16 d16 = dest reg
973: %macro LD_RR_NN 1
974: GETWORD
975: mov ez%1, edi
976: DO_CYCLES
977: NEXT
978: %endmacro
979:
980: ; Move from (NN) into a 16-bit register
981: ; LD_RR_mNN d16 d16 = dest reg
982: %macro LD_RR_mNN 1
983: GETWORD
984: MEMREAD
985: mov lz%1, dl
986: inc di
987: MEMREAD
988: mov hz%1, dl
989: DO_CYCLES
990: NEXT
991: %endmacro
992:
993: ; Move from a 16-bit register into (NN)
994: ; LD_mNN_RR s16 s16 = src reg
995: %macro LD_mNN_RR 1
996: GETWORD
997: mov dl, lz%1
998: MEMWRITE
999: inc di
1000: mov dl, hz%1
1001: MEMWRITE
1002: DO_CYCLES
1003: NEXT
1004: %endmacro
1005:
1006: ; Move from a 16-bit register into another
1007: ; LD_RR_RR d16, s16 s16 = src reg, d16 = dest reg
1008: %macro LD_RR_RR 2
1009: mov ez%1, ez%2
1010: DO_CYCLES
1011: NEXT
1012: %endmacro
1013:
1014: ; Move from a 16-bit register into another
1015: ; LD_RR_XY d16, s16 s16 = src reg, d16 = dest reg
1016: %macro LD_RR_XY 2
1017: mov edi, ez%2
1018: mov ez%1, edi
1019: DO_CYCLES
1020: NEXT
1021: %endmacro
1022:
1023: ; Push a word on the stack
1024: ; PUSH_RR s16 s16 = src reg
1025: %macro PUSH_RR 1
1026: mov dl, hz%1
1027: dec zSP
1028: mov edi, ezSP
1029: MEMWRITE
1030: dec zSP
1031: mov edi, ezSP
1032: %ifidn %1, AF
1033: ; merge bits 3 and 5 in
1034: and zF, ~(FLAG_3|FLAG_5)
1035: mov dl, [z80_flag35]
1036: and dl, FLAG_3|FLAG_5
1037: or zF, dl
1038: %endif
1039: mov dl, lz%1
1040: MEMWRITE
1041: DO_CYCLES
1042: NEXT
1043: %endmacro
1044:
1045: ; Pop a word from the stack
1046: ; POP_RR s16 s16 = src reg
1047: %macro POP_RR 1
1048: mov edi, ezSP
1049: MEMREAD
1050: %ifidn %1, AF
1051: mov [z80_flag35], dl ; take out bits 3/5
1052: %endif
1053: mov lz%1, dl
1054: inc zSP
1055: mov edi, ezSP
1056: MEMREAD
1057: mov hz%1, dl
1058: inc zSP
1059: DO_CYCLES
1060: NEXT
1061: %endmacro
1062:
1063: ; Exchange 2 16-bit registers
1064: ; EX_RR_RR s16, d16 s16 = src reg, d16 = dest reg
1065: %macro EX_RR_RR 2
1066: xchg ez%1, ez%2
1067: DO_CYCLES
1068: NEXT
1069: %endmacro
1070:
1071: ; Exchange AF with AF'
1072: ; EX_AF_AF2
1073: %macro EX_AF_AF2 0
1074: ; Merge bits 3+5 of the flags in first
1075: and zF, ~(FLAG_3|FLAG_5)
1076: mov dl, [z80_flag35]
1077: and dl, FLAG_3|FLAG_5
1078: or zF, dl
1079: xchg ezAF, ezAF2
1080:
1081: ; Un-merge the flags again
1082: mov [z80_flag35], zF
1083: DO_CYCLES
1084: NEXT
1085: %endmacro
1086:
1087: ; Exchange the 16-bit registers with their primes
1088: ; EXX
1089: %macro EXX 0
1090: mov edi, ezDE
1091: xchg ezBC, ezBC2
1092: xchg ezHL, ezHL2
1093: xchg edi, ezDE2
1094: mov ezDE, edi
1095: DO_CYCLES
1096: NEXT
1097: %endmacro
1098:
1099: ; Exchange a 16-bit register with (RR)
1100: ; EX_RR_mRR d16, m16 d16 = dest reg, m16 = memory reg
1101: %macro EX_RR_mRR 2
1102: mov edi, ez%2 ; swap low byte
1103: MEMREAD
1104: xchg dl, lz%1
1105: MEMWRITE
1106:
1107: inc di ; swap high byte
1108: MEMREAD
1109: xchg dl, hz%1
1110: MEMWRITE
1111:
1112: DO_CYCLES
1113: NEXT
1114: %endmacro
1115:
1116: ; Move from (HL) to (DE), post-increment
1117: ; LDI
1118: %macro LDI 0
1119: mov edi, ezHL
1120: MEMREAD
1121: %ifdef EMULATE_BITS_3_5
1122: push edx
1123: %endif
1124: mov edi, ezDE
1125: MEMWRITE
1126:
1127: %ifdef EMULATE_BITS_3_5
1128: pop edx
1129: add dl, zA
1130: mov dh, dl
1131: shl dl, 4
1132: and edx, FLAG_5 | (FLAG_3 << 8)
1133: or dl, dh
1134: mov [z80_flag35], dl
1135: xor dh, dh
1136: %endif
1137:
1138: and zF, FLAG_S|FLAG_Z|FLAG_C
1139: inc zHL
1140: inc zDE
1141: dec zBC
1142: jz %%ldi_zero
1143: or zF, FLAG_P
1144: %%ldi_zero:
1145: DO_CYCLES
1146: NEXT
1147: %endmacro
1148:
1149: ; Move from (HL) to (DE), post-decrement
1150: ; LDD
1151: %macro LDD 0
1152: mov edi, ezHL
1153: MEMREAD
1154: %ifdef EMULATE_BITS_3_5
1155: push edx
1156: %endif
1157: mov edi, ezDE
1158: MEMWRITE
1159:
1160: %ifdef EMULATE_BITS_3_5
1161: pop edx
1162: add dl, zA
1163: mov dh, dl
1164: shl dl, 4
1165: and edx, FLAG_5 | (FLAG_3 << 8)
1166: or dl, dh
1167: mov [z80_flag35], dl
1168: xor dh, dh
1169: %endif
1170:
1171: and zF, FLAG_S|FLAG_Z|FLAG_C
1172: dec zHL
1173: dec zDE
1174: dec zBC
1175: jz %%ldd_zero
1176: or zF, FLAG_P
1177: %%ldd_zero:
1178: DO_CYCLES
1179: NEXT
1180: %endmacro
1181:
1182: ; Move from (HL) to (DE), post-increment, repeat
1183: ; LDIR
1184: %macro LDIR 0
1185: %ifdef EMULATE_WEIRD_STUFF
1186: ; Code marked with CG is from Charles Gallagher, to fix the
1187: ; Spectrum game 'Quazatron'
1188: push ezPC ; CG
1189: sub zPC, 2 ; CG
1190: mov edi, ezPC ; CG
1191: shr edi, 8 ; CG
1192: add ezPC, [z80_Fetch+edi*4] ; CG
1193: %endif
1194:
1195: %%ldir_loop:
1196: %ifdef EMULATE_WEIRD_STUFF
1197: cmp [ezPC], word 0b0edh ; CG - check for self modifiying code!
1198: jne near %%ldir_modified
1199: %endif
1200:
1201: mov edi, ezHL
1202: MEMREAD
1203: %ifdef EMULATE_BITS_3_5
1204: push edx
1205: %endif
1206: mov edi, ezDE
1207: MEMWRITE
1208: %ifdef EMULATE_BITS_3_5
1209: pop edx
1210: %endif
1211:
1212: inc zHL
1213: inc zDE
1214: dec zBC
1215: jz %%ldir_zero
1216:
1217: %ifdef EMULATE_R_REGISTER
1218: inc zR
1219: %endif
1220: sub [z80_ICount], dword extra_cycles
1221: ja near %%ldir_loop
1222:
1223: %ifdef EMULATE_WEIRD_STUFF
1224: pop ezPC ; CG
1225: %endif
1226:
1227: and zF, FLAG_S|FLAG_Z|FLAG_C
1228: %ifdef EMULATE_BITS_3_5
1229: add dl, zA
1230: mov dh, dl
1231: shl dl, 4
1232: and edx, FLAG_5 | (FLAG_3 << 8)
1233: or dl, dh
1234: mov [z80_flag35], dl
1235: xor dh, dh
1236: %endif
1237: or zF, FLAG_P
1238: sub zPC, 2 ; rewind to instruction start
1239: EXIT
1240:
1241: %ifdef EMULATE_WEIRD_STUFF
1242: %%ldir_modified:
1243: sub [esp], word 2 ; CG
1244: %endif
1245:
1246: %%ldir_zero:
1247: %ifdef EMULATE_WEIRD_STUFF
1248: pop ezPC ; CG
1249: %endif
1250: and zF, FLAG_S|FLAG_Z|FLAG_C
1251: %ifdef EMULATE_BITS_3_5
1252: add dl, zA
1253: mov dh, dl
1254: shl dl, 4
1255: and edx, FLAG_5 | (FLAG_3 << 8)
1256: or dl, dh
1257: mov [z80_flag35], dl
1258: xor dh, dh
1259: %endif
1260: DO_CYCLES
1261: NEXT
1262: %endmacro
1263:
1264: ; Move from (HL) to (DE), post-decrement, repeat
1265: ; LDDR
1266: %macro LDDR 0
1267: %%lddr_loop:
1268: mov edi, ezHL
1269: MEMREAD
1270: %ifdef EMULATE_BITS_3_5
1271: push edx
1272: %endif
1273: mov edi, ezDE
1274: MEMWRITE
1275: %ifdef EMULATE_BITS_3_5
1276: pop edx
1277: %endif
1278:
1279: dec zHL
1280: dec zDE
1281: dec zBC
1282: jz %%lddr_zero
1283:
1284: %ifdef EMULATE_R_REGISTER
1285: inc zR
1286: %endif
1287: sub [z80_ICount], dword extra_cycles
1288: ja near %%lddr_loop
1289:
1290: and zF, FLAG_S|FLAG_Z|FLAG_C
1291: %ifdef EMULATE_BITS_3_5
1292: add dl, zA
1293: mov dh, dl
1294: shl dl, 4
1295: and edx, FLAG_5 | (FLAG_3 << 8)
1296: or dl, dh
1297: mov [z80_flag35], dl
1298: xor dh, dh
1299: %endif
1300: or zF, FLAG_P
1301: sub zPC, 2 ; rewind to instruction start
1302: EXIT
1303:
1304: %%lddr_zero:
1305: and zF, FLAG_S|FLAG_Z|FLAG_C
1306: %ifdef EMULATE_BITS_3_5
1307: add dl, zA
1308: mov dh, dl
1309: shl dl, 4
1310: and edx, FLAG_5 | (FLAG_3 << 8)
1311: or dl, dh
1312: mov [z80_flag35], dl
1313: xor dh, dh
1314: %endif
1315: DO_CYCLES
1316: NEXT
1317: %endmacro
1318:
1319: ; Compare A against (HL), post-increment
1320: ; CPI
1321: %macro CPI 0
1322: mov edi, ezHL
1323: MEMREAD
1324:
1325: and zF, FLAG_C ; keep the old carry
1326: mov dh, zF
1327: cmp zA, dl
1328: lahf
1329: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1330: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1331:
1332: inc zHL
1333: dec zBC
1334: jz %%cpi_zero
1335: or zF, FLAG_P ; set P if BC != 0
1336: %%cpi_zero:
1337:
1338: %ifdef EMULATE_BITS_3_5
1339: mov dh, zA
1340: sub dh, dl
1341: test zF, FLAG_H
1342: jz %%cpi_hzero
1343: dec dh
1344: %%cpi_hzero:
1345:
1346: mov dl, dh
1347: shl dl, 4
1348: and edx, FLAG_5 | (FLAG_3 << 8)
1349: or dl, dh
1350: mov [z80_flag35], dl
1351: %endif
1352: xor dh, dh
1353:
1354: DO_CYCLES
1355: NEXT
1356: %endmacro
1357:
1358: ; Compare A against (HL), post-decrement
1359: ; CPD
1360: %macro CPD 0
1361: mov edi, ezHL
1362: MEMREAD
1363:
1364: and zF, FLAG_C ; keep the old carry
1365: mov dh, zF
1366: cmp zA, dl
1367: lahf
1368: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1369: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1370:
1371: dec zHL
1372: dec zBC
1373: jz %%cpd_zero
1374: or zF, FLAG_P ; set P if BC != 0
1375: %%cpd_zero:
1376:
1377: %ifdef EMULATE_BITS_3_5
1378: mov dh, zA
1379: sub dh, dl
1380: test zF, FLAG_H
1381: jz %%cpd_hzero
1382: dec dh
1383: %%cpd_hzero:
1384:
1385: mov dl, dh
1386: shl dl, 4
1387: and edx, FLAG_5 | (FLAG_3 << 8)
1388: or dl, dh
1389: mov [z80_flag35], dl
1390: %endif
1391: xor dh, dh
1392:
1393: DO_CYCLES
1394: NEXT
1395: %endmacro
1396:
1397: ; Compare A against (HL), post-increment, repeat
1398: ; CPIR
1399: %macro CPIR 0
1400: and zF, FLAG_C ; keep the old carry
1401: %%cpir_loop:
1402: mov edi, ezHL
1403: MEMREAD
1404:
1405: inc zHL
1406: dec zBC
1407: jz %%cpir_end_bc ; end due to BC=0
1408:
1409: %ifdef EMULATE_R_REGISTER
1410: inc zR
1411: %endif
1412: cmp zA, dl
1413: je %%cpir_end_equal ; end due to A=(HL)
1414:
1415: sub [z80_ICount], dword extra_cycles
1416: ja %%cpir_loop
1417:
1418: ; out of cycles, but not finished
1419: mov dh, zF
1420: cmp zA, dl
1421: lahf
1422: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1423: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1424:
1425: %ifdef EMULATE_BITS_3_5
1426: mov dh, zA
1427: sub dh, dl
1428: test zF, FLAG_H
1429: jz %%cpir_hzero
1430: dec dh
1431: %%cpir_hzero:
1432:
1433: mov dl, dh
1434: shl dl, 4
1435: and edx, FLAG_5 | (FLAG_3 << 8)
1436: or dl, dh
1437: mov [z80_flag35], dl
1438: %endif
1439: or zF, FLAG_P ; set P to indicate not finished
1440: sub zPC, 2 ; rewind to instruction start
1441: xor dh, dh
1442: EXIT
1443:
1444: %%cpir_end_equal:
1445: or zF, FLAG_P ; set P to indicate not finished
1446: %%cpir_end_bc:
1447: mov dh, zF
1448: cmp zA, dl
1449: lahf
1450: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1451: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1452:
1453: %ifdef EMULATE_BITS_3_5
1454: mov dh, zA
1455: sub dh, dl
1456: test zF, FLAG_H
1457: jz %%cpir_hzero2
1458: dec dh
1459: %%cpir_hzero2:
1460:
1461: mov dl, dh
1462: shl dl, 4
1463: and edx, FLAG_5 | (FLAG_3 << 8)
1464: or dl, dh
1465: mov [z80_flag35], dl
1466: %endif
1467: xor dh, dh
1468: DO_CYCLES
1469: NEXT
1470: %endmacro
1471:
1472: ; Compare A against (HL), post-decrement, repeat
1473: ; CPDR
1474: %macro CPDR 0
1475: and zF, FLAG_C ; keep the old carry
1476: %%cpdr_loop:
1477: mov edi, ezHL
1478: MEMREAD
1479:
1480: dec zHL
1481: dec zBC
1482: jz %%cpdr_end_bc ; end due to BC=0
1483:
1484: %ifdef EMULATE_R_REGISTER
1485: inc zR
1486: %endif
1487: cmp zA, dl
1488: je %%cpdr_end_equal ; end due to A=(HL)
1489:
1490: sub [z80_ICount], dword extra_cycles
1491: ja %%cpdr_loop
1492:
1493: ; out of cycles, but not finished
1494: mov dh, zF
1495: cmp zA, dl
1496: lahf
1497: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1498: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1499:
1500: %ifdef EMULATE_BITS_3_5
1501: mov dh, zA
1502: sub dh, dl
1503: test zF, FLAG_H
1504: jz %%cpdr_hzero
1505: dec dh
1506: %%cpdr_hzero:
1507:
1508: mov dl, dh
1509: shl dl, 4
1510: and edx, FLAG_5 | (FLAG_3 << 8)
1511: or dl, dh
1512: mov [z80_flag35], dl
1513: %endif
1514: or zF, FLAG_P ; set P to indicate not finished
1515: sub zPC, 2 ; rewind to instruction start
1516: xor dh, dh
1517: EXIT
1518:
1519: %%cpdr_end_equal:
1520: or zF, FLAG_P ; set P to indicate not finished
1521: %%cpdr_end_bc:
1522: mov dh, zF
1523: cmp zA, dl
1524: lahf
1525: and zF, FLAG_S|FLAG_Z|FLAG_H|FLAG_N
1526: or zF, dh ; SZHN from compare, C unchanged, rest are zero
1527:
1528: %ifdef EMULATE_BITS_3_5
1529: mov dh, zA
1530: sub dh, dl
1531: test zF, FLAG_H
1532: jz %%cpdr_hzero2
1533: dec dh
1534: %%cpdr_hzero2:
1535:
1536: mov dl, dh
1537: shl dl, 4
1538: and edx, FLAG_5 | (FLAG_3 << 8)
1539: or dl, dh
1540: mov [z80_flag35], dl
1541: %endif
1542: xor dh, dh
1543: DO_CYCLES
1544: NEXT
1545: %endmacro
1546:
1547: ; Perform arithmetic on the A register
1548: ; ART_R method, src8
1549: %macro ART_R 2
1550: %ifidn %1, ADD
1551: DO_ADD z%2
1552: %elifidn %1, ADC
1553: DO_ADC z%2
1554: %elifidn %1, SUB
1555: DO_SUB z%2
1556: %elifidn %1, SBC
1557: DO_SBC z%2
1558: %endif
1559:
1560: DO_CYCLES
1561: NEXT
1562: %endmacro
1563:
1564: ; Perform arithmetic on the A register (using an immediate)
1565: ; ART_N method
1566: %macro ART_N 1
1567: GETBYTE
1568: %ifidn %1, ADD
1569: DO_ADD dl
1570: %elifidn %1, ADC
1571: DO_ADC dl
1572: %elifidn %1, SUB
1573: DO_SUB dl
1574: %elifidn %1, SBC
1575: DO_SBC dl
1576: %endif
1577:
1578: DO_CYCLES
1579: NEXT
1580: %endmacro
1581:
1582: ; Perform arithmetic on the A register, using (XY)
1583: ; ART_mXY method, src16
1584: %macro ART_mXY 2
1585: GETDISP
1586: add di, z%2
1587: MEMREAD
1588: %ifidn %1, ADD
1589: DO_ADD dl
1590: %elifidn %1, ADC
1591: DO_ADC dl
1592: %elifidn %1, SUB
1593: DO_SUB dl
1594: %elifidn %1, SBC
1595: DO_SBC dl
1596: %endif
1597:
1598: DO_CYCLES
1599: NEXT
1600: %endmacro
1601:
1602: ; Perform arithmetic on the A register using (RR)
1603: ; ART_mRR method, src16
1604: %macro ART_mRR 2
1605: mov edi, ez%2
1606: MEMREAD
1607: %ifidn %1, ADD
1608: DO_ADD dl
1609: %elifidn %1, ADC
1610: DO_ADC dl
1611: %elifidn %1, SUB
1612: DO_SUB dl
1613: %elifidn %1, SBC
1614: DO_SBC dl
1615: %endif
1616:
1617: DO_CYCLES
1618: NEXT
1619: %endmacro
1620:
1621: ; Perform logic on the A register
1622: ; LOG_R method, src8
1623: %macro LOG_R 2
1624: %ifidn %1, AND
1625: DO_AND z%2
1626: %elifidn %1, OR
1627: DO_OR z%2
1628: %elifidn %1, XOR
1629: DO_XOR z%2
1630: %endif
1631:
1632: DO_CYCLES
1633: NEXT
1634: %endmacro
1635:
1636: ; Perform logic on the A register (using an immediate)
1637: ; LOG_N method
1638: %macro LOG_N 1
1639: GETBYTE
1640: %ifidn %1, AND
1641: DO_AND dl
1642: %elifidn %1, OR
1643: DO_OR dl
1644: %elifidn %1, XOR
1645: DO_XOR dl
1646: %endif
1647:
1648: DO_CYCLES
1649: NEXT
1650: %endmacro
1651:
1652: ; Perform logic on the A register, using (RR)
1653: ; LOG_mRR method, src16
1654: %macro LOG_mRR 2
1655: mov edi, ez%2
1656: MEMREAD
1657: %ifidn %1, AND
1658: DO_AND dl
1659: %elifidn %1, OR
1660: DO_OR dl
1661: %elifidn %1, XOR
1662: DO_XOR dl
1663: %endif
1664:
1665: DO_CYCLES
1666: NEXT
1667: %endmacro
1668:
1669: ; Perform logic on the A register, using (XY+dd)
1670: ; LOG_mXY method, src16
1671: %macro LOG_mXY 2
1672: GETDISP
1673: add di, z%2
1674: MEMREAD
1675: %ifidn %1, AND
1676: DO_AND dl
1677: %elifidn %1, OR
1678: DO_OR dl
1679: %elifidn %1, XOR
1680: DO_XOR dl
1681: %endif
1682:
1683: DO_CYCLES
1684: NEXT
1685: %endmacro
1686:
1687: ; Compare against the A register
1688: ; CP_R src8
1689: %macro CP_R 1
1690: DO_CP z%1
1691:
1692: DO_CYCLES
1693: NEXT
1694: %endmacro
1695:
1696: ; Compare against the A register, using an immediate
1697: ; CP_N
1698: %macro CP_N 0
1699: GETBYTE
1700: DO_CP dl
1701:
1702: DO_CYCLES
1703: NEXT
1704: %endmacro
1705:
1706: ; Compare against the A register, using (RR)
1707: ; CP_mRR src16
1708: %macro CP_mRR 1
1709: mov edi, ez%1
1710: MEMREAD
1711: DO_CP dl
1712:
1713: DO_CYCLES
1714: NEXT
1715: %endmacro
1716:
1717: ; Compare against the A register, using (XY+dd)
1718: ; CP_mXY src16
1719: %macro CP_mXY 1
1720: GETDISP
1721: add di, z%1
1722: MEMREAD
1723: DO_CP dl
1724:
1725: DO_CYCLES
1726: NEXT
1727: %endmacro
1728:
1729: ; Inc/dec a register
1730: ; DECINC_R method, reg8
1731: %macro DECINC_R 2
1732: %ifidn %1, INC
1733: DO_INC z%2
1734: %elifidn %1, DEC
1735: DO_DEC z%2
1736: %endif
1737:
1738: DO_CYCLES
1739: NEXT
1740: %endmacro
1741:
1742: ; Inc/dec (RR)
1743: ; DECINC_mRR method
1744: %macro DECINC_mRR 2
1745: mov edi, ez%2
1746: MEMREAD
1747: %ifidn %1, INC
1748: DO_INC dl
1749: %elifidn %1, DEC
1750: DO_DEC dl
1751: %endif
1752: MEMWRITE
1753:
1754: DO_CYCLES
1755: NEXT
1756: %endmacro
1757:
1758: ; Inc/dec (XY+dd)
1759: ; DECINC_mXY method
1760: %macro DECINC_mXY 2
1761: GETDISP
1762: add di, z%2
1763: MEMREAD
1764: %ifidn %1, INC
1765: DO_INC dl
1766: %elifidn %1, DEC
1767: DO_DEC dl
1768: %endif
1769: MEMWRITE
1770:
1771: DO_CYCLES
1772: NEXT
1773: %endmacro
1774:
1775: ; Add two 16-bit registers
1776: ; ADD_RR_RR dest16, src16
1777: %macro ADD_RR_RR 2
1778: DO_ADD16 z%1, z%2
1779:
1780: DO_CYCLES
1781: NEXT
1782: %endmacro
1783:
1784: ; Add two 16-bit registers, with carry
1785: ; ADC_RR_RR dest16, src16
1786: %macro ADC_RR_RR 2
1787: DO_ADC16 z%1, z%2
1788:
1789: DO_CYCLES
1790: NEXT
1791: %endmacro
1792:
1793: ; Subtract two 16-bit registers, with carry
1794: ; SBC_RR_RR dest16, src16
1795: %macro SBC_RR_RR 2
1796: DO_SBC16 z%1, z%2
1797:
1798: DO_CYCLES
1799: NEXT
1800: %endmacro
1801:
1802: ; Inc/dec a 16-bit register
1803: ; DECINC_RR method, reg16
1804: %macro DECINC_RR 2
1805: %ifidn %1, INC
1806: inc z%2
1807: %elifidn %1, DEC
1808: dec z%2
1809: %endif
1810:
1811: DO_CYCLES
1812: NEXT
1813: %endmacro
1814:
1815: ; Rotate a register
1816: ; ROT_R method, reg8
1817: %macro ROT_R 2
1818: DO_ROT %1, z%2
1819:
1820: DO_CYCLES
1821: NEXT
1822: %endmacro
1823:
1824: ; Rotate (RR)
1825: ; ROT_mRR method, src16
1826: %macro ROT_mRR 2
1827: mov edi, ez%2
1828: MEMREAD
1829: DO_ROT %1, dl
1830: MEMWRITE
1831:
1832: DO_CYCLES
1833: NEXT
1834: %endmacro
1835:
1836: ; Rotate (XY+dd)
1837: ; ROT_mXY method
1838: %macro ROT_mXY 1
1839: MEMREAD
1840: DO_ROT %1, dl
1841: MEMWRITE
1842:
1843: DO_CYCLES
1844: NEXT
1845: %endmacro
1846:
1847: ; Rotate (XY+dd), and store into a register
1848: ; ROT_mXY_R method, dest8
1849: %macro ROT_mXY_R 2
1850: MEMREAD
1851: DO_ROT %1, dl
1852: mov z%2, dl
1853: MEMWRITE
1854:
1855: DO_CYCLES
1856: NEXT
1857: %endmacro
1858:
1859: ; Shift a register
1860: ; SHF_R method, reg8
1861: %macro SHF_R 2
1862: DO_SHF %1, z%2
1863:
1864: DO_CYCLES
1865: NEXT
1866: %endmacro
1867:
1868: ; Shift (RR)
1869: ; SHF_mRR method, src16
1870: %macro SHF_mRR 2
1871: mov edi, ez%2
1872: MEMREAD
1873: DO_SHF %1, dl
1874: MEMWRITE
1875:
1876: DO_CYCLES
1877: NEXT
1878: %endmacro
1879:
1880: ; Shift (XY+dd)
1881: ; SHF_mXY method
1882: %macro SHF_mXY 1
1883: MEMREAD
1884: DO_SHF %1, dl
1885: MEMWRITE
1886:
1887: DO_CYCLES
1888: NEXT
1889: %endmacro
1890:
1891: ; Shift (XY+dd), and store into a register
1892: ; SHF_mXY_R method, dest8
1893: %macro SHF_mXY_R 2
1894: MEMREAD
1895: DO_SHF %1, dl
1896: mov z%2, dl
1897: MEMWRITE
1898:
1899: DO_CYCLES
1900: NEXT
1901: %endmacro
1902:
1903: ; Rotate A/(HL) left, via nibbles
1904: ; RLD
1905: %macro RLD 0
1906: mov edi, ezHL
1907: MEMREAD
1908: mov dh, zA
1909: and zF, FLAG_C
1910: shl dh, 4
1911: rol dx, 4
1912: and zA, 0f0h
1913: or zA, dh
1914: mov dh, zF
1915: lahf
1916: and zF, FLAG_S|FLAG_Z|FLAG_P
1917: or zF, dh
1918: %ifdef EMULATE_BITS_3_5
1919: mov [z80_flag35], zA
1920: %endif
1921: MEMWRITE
1922:
1923: DO_CYCLES
1924: NEXT
1925: %endmacro
1926:
1927: ; Rotate A/(HL) right, via nibbles
1928: ; RRD
1929: %macro RRD 0
1930: mov edi, ezHL
1931: MEMREAD
1932: mov dh, zA
1933: and zF, FLAG_C
1934: ror dx, 4
1935: shr dh, 4
1936: and zA, 0f0h
1937: or zA, dh
1938: mov dh, zF
1939: lahf
1940: and zF, FLAG_S|FLAG_Z|FLAG_P
1941: or zF, dh
1942: %ifdef EMULATE_BITS_3_5
1943: mov [z80_flag35], zA
1944: %endif
1945: MEMWRITE
1946:
1947: DO_CYCLES
1948: NEXT
1949: %endmacro
1950:
1951: ; Bit-test a register
1952: ; BIT_R src8, bit
1953: %macro BIT_R_b 2
1954: DO_BIT z%1, %2
1955:
1956: DO_CYCLES
1957: NEXT
1958: %endmacro
1959:
1960: ; Bit-test (RR)
1961: ; BIT_mRR_b src16, bit
1962: %macro BIT_mRR_b 2
1963: and zF, FLAG_C
1964: mov edi, ez%1
1965: MEMREAD
1966:
1967: test dl, (1 << %2)
1968:
1969: ; bit 3 and 5 are always cleared
1970: ; (actually they are bizarrely set, but
1971: ; there's no point emulating that, it's just
1972: ; plain silly...)
1973:
1974: jz %%bit_is_clear
1975: %ifidn %2, 7
1976: or zF, FLAG_H|FLAG_S ; set sign bit, if testing bit 7
1977: %else
1978: or zF, FLAG_H ; set half-carry, and parity
1979: %endif
1980: jmp %%finish
1981:
1982: %%bit_is_clear:
1983: or zF, FLAG_H|FLAG_Z|FLAG_P ; set half-carry, parity, and zero
1984: %%finish:
1985:
1986: DO_CYCLES
1987: NEXT
1988: %endmacro
1989:
1990: ; Bit-test (XY+dd)
1991: ; BIT_mXY_b bit
1992: %macro BIT_mXY_b 1
1993: %ifdef EMULATE_BITS_3_5
1994: mov edx, edi
1995: mov [z80_flag35], dh
1996: %endif
1997:
1998: MEMREAD
1999: and zF, FLAG_C
2000: test dl, (1 << %1)
2001:
2002: jz %%bit_is_clear
2003: %ifidn %1, 7
2004: or zF, FLAG_H|FLAG_S ; set sign bit, if testing bit 7
2005: %else
2006: or zF, FLAG_H ; set half-carry, and parity
2007: %endif
2008: jmp %%finish
2009:
2010: %%bit_is_clear:
2011: or zF, FLAG_H|FLAG_Z|FLAG_P ; set half-carry, parity, and zero
2012: %%finish:
2013:
2014: DO_CYCLES
2015: NEXT
2016: %endmacro
2017:
2018: ; Bit-clear a register
2019: ; RES_R_b src8, bit
2020: %macro RES_R_b 2
2021: DO_RES z%1, %2
2022:
2023: DO_CYCLES
2024: NEXT
2025: %endmacro
2026:
2027: ; Bit-clear (RR)
2028: ; RES_mRR_b src16, bit
2029: %macro RES_mRR_b 2
2030: mov edi, ez%1
2031: MEMREAD
2032: DO_RES dl, %2
2033: MEMWRITE
2034:
2035: DO_CYCLES
2036: NEXT
2037: %endmacro
2038:
2039: ; Bit-clear (XY+dd)
2040: ; RES_mXY_b bit
2041: %macro RES_mXY_b 1
2042: MEMREAD
2043: DO_RES dl, %1
2044: MEMWRITE
2045:
2046: DO_CYCLES
2047: NEXT
2048: %endmacro
2049:
2050: ; Bit-clear (XY+dd), with extra store
2051: ; RES_mXY_b_R bit, dest8
2052: %macro RES_mXY_b_R 2
2053: MEMREAD
2054: DO_RES dl, %1
2055: mov z%2, dl
2056: MEMWRITE
2057:
2058: DO_CYCLES
2059: NEXT
2060: %endmacro
2061:
2062: ; Bit-set a register
2063: ; SET_R_b src8, bit
2064: %macro SET_R_b 2
2065: DO_SET z%1, %2
2066:
2067: DO_CYCLES
2068: NEXT
2069: %endmacro
2070:
2071: ; Bit-set (RR)
2072: ; SET_mRR_b src16, bit
2073: %macro SET_mRR_b 2
2074: mov edi, ez%1
2075: MEMREAD
2076: DO_SET dl, %2
2077: MEMWRITE
2078:
2079: DO_CYCLES
2080: NEXT
2081: %endmacro
2082:
2083: ; Bit-set (XY+dd)
2084: ; SET_mXY_b bit
2085: %macro SET_mXY_b 1
2086: MEMREAD
2087: DO_SET dl, %1
2088: MEMWRITE
2089:
2090: DO_CYCLES
2091: NEXT
2092: %endmacro
2093:
2094: ; Bit-set (XY+dd), with extra store
2095: ; SET_mXY_b_R bit, dest8
2096: %macro SET_mXY_b_R 2
2097: MEMREAD
2098: DO_SET dl, %1
2099: mov z%2, dl
2100: MEMWRITE
2101:
2102: DO_CYCLES
2103: NEXT
2104: %endmacro
2105:
2106: ; Jump to an absolute address
2107: ; JP_NN
2108: %macro JP_NN 0
2109: GETWORD
2110: mov ezPC, edi
2111: DO_CYCLES
2112: NEXT
2113: %endmacro
2114:
2115: ; Jump to an absolute address, conditionally
2116: ; JP_cc_NN nz,cc
2117: %macro JP_cc_NN 2
2118: test zF, FLAG_%2
2119: j%1 near %%dont_take_jump
2120: GETWORD
2121: mov ezPC, edi
2122: DO_CYCLES
2123: NEXT
2124:
2125: ALIGN
2126: %%dont_take_jump:
2127: add zPC, 2 ; skip address
2128: DO_CYCLES
2129: NEXT
2130: %endmacro
2131:
2132: ; Jump to an relative address
2133: ; JR_N
2134: %macro JR_N 0
2135: GETDISP
2136: add zPC, di
2137: DO_CYCLES
2138: NEXT
2139: %endmacro
2140:
2141: ; Jump to an relative address, conditionally
2142: ; JR_cc_N nz,cc
2143: %macro JR_cc_N 2
2144: test zF, FLAG_%2
2145: j%1 near %%dont_take_jump
2146: GETDISP
2147: add zPC, di
2148: DO_EXTRA_CYCLES
2149: NEXT
2150:
2151: ALIGN
2152: %%dont_take_jump:
2153: inc zPC ; skip over the displacement
2154: DO_CYCLES
2155: NEXT
2156: %endmacro
2157:
2158: ; Jump to an absolute address (in a register)
2159: ; JP_RR addr16
2160: %macro JP_RR 1
2161: mov ezPC, ez%1
2162: DO_CYCLES
2163: NEXT
2164: %endmacro
2165:
2166: ; Decrease B, if non-zero, jump to a relative address
2167: ; DJNZ_N
2168: %macro DJNZ_N 0
2169: dec zB
2170: jz near %%dont_take_jump
2171: GETDISP
2172: add zPC, di
2173: DO_EXTRA_CYCLES
2174: NEXT
2175:
2176: ALIGN
2177: %%dont_take_jump:
2178: inc zPC ; skip over the displacement
2179: DO_CYCLES
2180: NEXT
2181: %endmacro
2182:
2183: ; Call an absolute address
2184: ; CALL_NN
2185: %macro CALL_NN 0
2186: GETWORD
2187: mov edx, ezPC ; write the PC
2188: dec zSP
2189: push edi
2190:
2191: xchg dl, dh
2192: mov edi, ezSP
2193: MEMWRITE
2194: dec zSP
2195: mov edx, ezPC
2196: mov edi, ezSP
2197: MEMWRITE
2198:
2199: pop ezPC ; get the new PC
2200: DO_CYCLES
2201: NEXT
2202: %endmacro
2203:
2204: ; Call an absolute address, conditionally
2205: ; CALL_cc_NN
2206: %macro CALL_cc_NN 2
2207: test zF, FLAG_%2
2208: j%1 near %%dont_take_jump
2209: GETWORD
2210: mov edx, ezPC ; write the PC
2211: push edi
2212:
2213: dec zSP
2214: xchg dl, dh
2215: mov edi, ezSP
2216: MEMWRITE
2217: dec zSP
2218: mov edx, ezPC
2219: mov edi, ezSP
2220: MEMWRITE
2221:
2222: pop ezPC ; get the new PC
2223: DO_CYCLES
2224: NEXT
2225:
2226: ALIGN
2227: %%dont_take_jump:
2228: add zPC, 2 ; skip address
2229: DO_CYCLES
2230: NEXT
2231: %endmacro
2232:
2233: ; Pop the PC
2234: ; RET
2235: %macro RET 0
2236: mov edi, ezSP
2237: MEMREAD
2238: inc zSP
2239: mov ezPC, edx
2240: mov edi, ezSP
2241: MEMREAD
2242: xchg dl, dh
2243: or ezPC, edx
2244: inc zSP
2245:
2246: xor dh, dh
2247: DO_CYCLES
2248: NEXT
2249: %endmacro
2250:
2251: ; Pop the PC, conditionally
2252: ; RET_cc
2253: %macro RET_cc 2
2254: test zF, FLAG_%2
2255: j%1 near %%dont_take_jump
2256: mov edi, ezSP
2257: MEMREAD
2258: inc zSP
2259: mov ezPC, edx
2260: mov edi, ezSP
2261: MEMREAD
2262: xchg dl, dh
2263: or ezPC, edx
2264: inc zSP
2265:
2266: xor dh, dh
2267: DO_CYCLES
2268: NEXT
2269:
2270: ALIGN
2271: %%dont_take_jump:
2272: DO_CYCLES
2273: NEXT
2274: %endmacro
2275:
2276: ; Pop the PC, restore IFF1, signal the BUS
2277: ; RETI
2278: %macro RETI 0
2279: mov edi, ezSP
2280: MEMREAD
2281: mov ezPC, edx
2282: inc zSP
2283: mov edi, ezSP
2284: MEMREAD
2285: xchg dl, dh
2286: or ezPC, edx
2287: inc zSP
2288:
2289: mov dl, [z80_IFF2]
2290: mov [z80_IFF1], dl
2291: call [z80_RetI] ; signal the user handler
2292:
2293: DO_CYCLES
2294: NEXT
2295: %endmacro
2296:
2297: ; Pop the PC, restore IFF1
2298: ; RETN
2299: %macro RETN 0
2300: mov edi, ezSP
2301: MEMREAD
2302: mov ezPC, edx
2303: inc zSP
2304: mov edi, ezSP
2305: MEMREAD
2306: xchg dl, dh
2307: or ezPC, edx
2308: inc zSP
2309:
2310: mov dl, [z80_IFF2]
2311: mov [z80_IFF1], dl
2312: DO_CYCLES
2313: NEXT
2314: %endmacro
2315:
2316: ; Call an absolute address
2317: ; RST addr8
2318: %macro RST 1
2319: dec zSP
2320: mov edx, ezPC ; write the PC
2321: xchg dl, dh
2322: mov edi, ezSP
2323: MEMWRITE
2324: dec zSP
2325: mov edx, ezPC
2326: mov edi, ezSP
2327: MEMWRITE
2328:
2329: mov ezPC, %1 ; get the new PC
2330: DO_CYCLES
2331: NEXT
2332: %endmacro
2333:
2334: ; Out R to R*256+N
2335: ; OUT_N_R src8
2336: %macro OUT_N_R 1
2337: GETBYTE
2338: mov dh, z%1
2339: mov edi, edx
2340: mov dl, z%1
2341: IOWRITE
2342: DO_CYCLES
2343: NEXT
2344: %endmacro
2345:
2346: ; In from R*256+N, into R
2347: ; IN_R_N dest8
2348: %macro IN_R_N 1
2349: GETBYTE
2350: mov dh, z%1
2351: mov edi, edx
2352: IOREAD
2353: mov z%1, dl
2354: DO_CYCLES
2355: NEXT
2356: %endmacro
2357:
2358: ; In from BC
2359: ; IN_R dest8
2360: %macro IN_R 1
2361: mov edi, ezBC
2362: IOREAD
2363: mov dh, zF
2364: and dh, FLAG_C ; keep the old carry
2365: mov z%1, dl
2366: test dl, dl ; other flags come from the result
2367: lahf
2368: and zF, FLAG_S|FLAG_Z|FLAG_P
2369: or zF, dh
2370: %ifdef EMULATE_BITS_3_5
2371: mov [z80_flag35], dl
2372: %endif
2373: xor dh, dh
2374:
2375: DO_CYCLES
2376: NEXT
2377: %endmacro
2378:
2379: ; In from BC, ignore result
2380: ; IN_F
2381: %macro IN_F 0
2382: mov edi, ezBC
2383: IOREAD
2384: mov dh, zF
2385: and dh, FLAG_C ; keep the old carry
2386: test dl, dl ; other flags come from the result
2387: lahf
2388: and zF, FLAG_S|FLAG_Z|FLAG_P
2389: or zF, dh
2390: %ifdef EMULATE_BITS_3_5
2391: mov [z80_flag35], dl
2392: %endif
2393: xor dh, dh
2394:
2395: DO_CYCLES
2396: NEXT
2397: %endmacro
2398:
2399: ; Out to BC
2400: ; OUT_R src8
2401: %macro OUT_R 1
2402: mov edi, ezBC
2403: mov dl, z%1
2404: IOWRITE
2405: DO_CYCLES
2406: NEXT
2407: %endmacro
2408:
2409: ; Out zero to BC
2410: ; OUT_0
2411: %macro OUT_0 0
2412: mov edi, ezBC
2413: xor dl, dl
2414: IOWRITE
2415: DO_CYCLES
2416: NEXT
2417: %endmacro
2418:
2419: ; In from BC into (HL), increase HL, decrease B
2420: %macro INI 0
2421: ; FIXME - Parity flag is not emulated
2422: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2423:
2424: IOREAD ; read from the port
2425: mov edi, ezHL
2426: %ifdef EMULATE_WEIRD_STUFF
2427: push edx ; preserve the value
2428: %endif
2429: MEMWRITE ; write to (HL)
2430: %ifdef EMULATE_WEIRD_STUFF
2431: pop edx
2432: %endif
2433:
2434: inc zHL ; increase HL
2435: dec zB ; decrease B
2436: %ifdef EMULATE_BITS_3_5
2437: mov [z80_flag35], zB
2438: %endif
2439:
2440: lahf
2441: and zF, FLAG_S|FLAG_Z|FLAG_P
2442:
2443: ; This is a prime example of the weirdness of the Z80...
2444: %ifdef EMULATE_WEIRD_STUFF
2445: mov dh, zC
2446: inc dh
2447: add dh, dl
2448: jnc %%no_carry
2449: or zF, FLAG_H|FLAG_C
2450: %%no_carry:
2451: shr dl, 6
2452: and edx, FLAG_N
2453: or zF, dl
2454: %endif
2455: DO_CYCLES
2456: NEXT
2457: %endmacro
2458:
2459: ; In from BC into (HL), decrease HL, decrease B
2460: %macro IND 0
2461: ; FIXME - Parity flag is not emulated
2462: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2463:
2464: IOREAD ; read from the port
2465: mov edi, ezHL
2466: %ifdef EMULATE_WEIRD_STUFF
2467: push edx ; preserve the value
2468: %endif
2469: MEMWRITE ; write to (HL)
2470: %ifdef EMULATE_WEIRD_STUFF
2471: pop edx
2472: %endif
2473:
2474: dec zHL ; increase HL
2475: dec zB ; decrease B
2476: %ifdef EMULATE_BITS_3_5
2477: mov [z80_flag35], zB
2478: %endif
2479:
2480: lahf
2481: and zF, FLAG_S|FLAG_Z|FLAG_P
2482:
2483: ; This is a prime example of the weirdness of the Z80...
2484: %ifdef EMULATE_WEIRD_STUFF
2485: mov dh, zC
2486: dec dh
2487: add dh, dl
2488: jnc %%no_carry
2489: or zF, FLAG_H|FLAG_C
2490: %%no_carry:
2491: shr dl, 6
2492: and edx, FLAG_N
2493: or zF, dl
2494: %endif
2495: DO_CYCLES
2496: NEXT
2497: %endmacro
2498:
2499: ; In from BC into (HL), increase HL, decrease B, repeat
2500: %macro INIR 0
2501: ; FIXME - Parity flag is not emulated
2502: %%inir_loop:
2503: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2504:
2505: IOREAD ; read from the port
2506: mov edi, ezHL
2507: %ifdef EMULATE_WEIRD_STUFF
2508: push edx ; preserve the value
2509: %endif
2510: MEMWRITE ; write to (HL)
2511: %ifdef EMULATE_WEIRD_STUFF
2512: pop edx
2513: %endif
2514:
2515: inc zHL ; increase HL
2516: dec zB ; decrease B
2517: jz %%inir_zero
2518:
2519: sub [z80_ICount], dword extra_cycles
2520: ja near %%inir_loop ; repeat while cycles left and B>0
2521:
2522: ; out of cycles, but operation not finished
2523: %ifdef EMULATE_BITS_3_5
2524: mov [z80_flag35], zB
2525: %endif
2526:
2527: mov zF, zB
2528: and zF, FLAG_S
2529:
2530: ; This is a prime example of the weirdness of the Z80...
2531: %ifdef EMULATE_WEIRD_STUFF
2532: mov dh, zC
2533: inc dh
2534: add dh, dl
2535: jnc %%no_carry
2536: or zF, FLAG_H|FLAG_C
2537: %%no_carry:
2538: shr dl, 6
2539: and edx, FLAG_N
2540: or zF, dl
2541: %endif
2542: sub zPC, 2 ; rewind to instruction start
2543: EXIT
2544:
2545: ; B=0
2546: %%inir_zero:
2547: mov zF, FLAG_Z|FLAG_P
2548: %ifdef EMULATE_BITS_3_5
2549: mov [z80_flag35], zF
2550: %endif
2551:
2552: ; This is a prime example of the weirdness of the Z80...
2553: %ifdef EMULATE_WEIRD_STUFF
2554: mov dh, zC
2555: inc dh
2556: add dh, dl
2557: jnc %%no_carry2
2558: or zF, FLAG_H|FLAG_C
2559: %%no_carry2:
2560: shr dl, 6
2561: and edx, FLAG_N
2562: or zF, dl
2563: %endif
2564: DO_CYCLES
2565: NEXT
2566: %endmacro
2567:
2568: ; In from BC into (HL), decrease HL, decrease B, repeat
2569: %macro INDR 0
2570: ; FIXME - Parity flag is not emulated
2571: %%indr_loop:
2572: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2573:
2574: IOREAD ; read from the port
2575: mov edi, ezHL
2576: %ifdef EMULATE_WEIRD_STUFF
2577: push edx ; preserve the value
2578: %endif
2579: MEMWRITE ; write to (HL)
2580: %ifdef EMULATE_WEIRD_STUFF
2581: pop edx
2582: %endif
2583:
2584: dec zHL ; decrease HL
2585: dec zB ; decrease B
2586: jz %%indr_zero
2587:
2588: sub [z80_ICount], dword extra_cycles
2589: ja near %%indr_loop ; repeat while cycles left and B>0
2590:
2591: ; out of cycles, but operation not finished
2592: %ifdef EMULATE_BITS_3_5
2593: mov [z80_flag35], zB
2594: %endif
2595:
2596: mov zF, zB
2597: and zF, FLAG_S
2598:
2599: ; This is a prime example of the weirdness of the Z80...
2600: %ifdef EMULATE_WEIRD_STUFF
2601: mov dh, zC
2602: inc dh
2603: add dh, dl
2604: jnc %%no_carry
2605: or zF, FLAG_H|FLAG_C
2606: %%no_carry:
2607: shr dl, 6
2608: and edx, FLAG_N
2609: or zF, dl
2610: %endif
2611: sub zPC, 2 ; rewind to instruction start
2612: EXIT
2613:
2614: ; B=0
2615: %%indr_zero:
2616: mov zF, FLAG_Z|FLAG_P
2617: %ifdef EMULATE_BITS_3_5
2618: mov [z80_flag35], zF
2619: %endif
2620:
2621: ; This is a prime example of the weirdness of the Z80...
2622: %ifdef EMULATE_WEIRD_STUFF
2623: mov dh, zC
2624: inc dh
2625: add dh, dl
2626: jnc %%no_carry2
2627: or zF, FLAG_H|FLAG_C
2628: %%no_carry2:
2629: shr dl, 6
2630: and edx, FLAG_N
2631: or zF, dl
2632: %endif
2633: DO_CYCLES
2634: NEXT
2635: %endmacro
2636:
2637: ; Out from (HL) into BC, increase HL, decrease B
2638: %macro OUTI 0
2639: ; FIXME - Parity flag is not emulated
2640: mov edi, ezHL
2641:
2642: MEMREAD ; read from (HL)
2643: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2644: %ifdef EMULATE_WEIRD_STUFF
2645: push edx ; preserve the value
2646: %endif
2647: IOWRITE ; write to the port
2648: %ifdef EMULATE_WEIRD_STUFF
2649: pop edx
2650: %endif
2651:
2652: inc zHL ; increase HL
2653: dec zB ; decrease B
2654: %ifdef EMULATE_BITS_3_5
2655: mov [z80_flag35], zB
2656: %endif
2657:
2658: lahf
2659: and zF, FLAG_S|FLAG_Z|FLAG_P
2660:
2661: ; This is a prime example of the weirdness of the Z80...
2662: %ifdef EMULATE_WEIRD_STUFF
2663: mov dh, zC
2664: inc dh
2665: add dh, dl
2666: jnc %%no_carry
2667: or zF, FLAG_H|FLAG_C
2668: %%no_carry:
2669: shr dl, 6
2670: and edx, FLAG_N
2671: or zF, dl
2672: %endif
2673: DO_CYCLES
2674: NEXT
2675: %endmacro
2676:
2677: ; Out from (HL) into BC, decrease HL, decrease B
2678: %macro OUTD 0
2679: ; FIXME - Parity flag is not emulated
2680: mov edi, ezHL
2681:
2682: MEMREAD ; read from (HL)
2683: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2684: %ifdef EMULATE_WEIRD_STUFF
2685: push edx ; preserve the value
2686: %endif
2687: IOWRITE ; write to the port
2688: %ifdef EMULATE_WEIRD_STUFF
2689: pop edx
2690: %endif
2691:
2692: dec zHL ; decrease HL
2693: dec zB ; decrease B
2694: %ifdef EMULATE_BITS_3_5
2695: mov [z80_flag35], zB
2696: %endif
2697:
2698: lahf
2699: and zF, FLAG_S|FLAG_Z|FLAG_P
2700:
2701: ; This is a prime example of the weirdness of the Z80...
2702: %ifdef EMULATE_WEIRD_STUFF
2703: mov dh, zC
2704: inc dh
2705: add dh, dl
2706: jnc %%no_carry
2707: or zF, FLAG_H|FLAG_C
2708: %%no_carry:
2709: shr dl, 6
2710: and edx, FLAG_N
2711: or zF, dl
2712: %endif
2713: DO_CYCLES
2714: NEXT
2715: %endmacro
2716:
2717: ; Out from (HL) into BC, increase HL, decrease B, repeat
2718: %macro OTIR 0
2719: %%otir_loop:
2720: mov edi, ezHL
2721: MEMREAD
2722: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2723: %ifdef EMULATE_WEIRD_STUFF
2724: push edx ; preserve the value
2725: %endif
2726: IOWRITE
2727: %ifdef EMULATE_WEIRD_STUFF
2728: pop edx
2729: %endif
2730:
2731: inc zHL
2732: dec zB
2733: jz %%otir_zero
2734:
2735: %ifdef EMULATE_R_REGISTER
2736: inc zR
2737: %endif
2738: sub [z80_ICount], dword extra_cycles
2739: ja near %%otir_loop
2740:
2741: ; out of cycles, but not finished
2742: %ifdef EMULATE_BITS_3_5
2743: mov [z80_flag35], zB
2744: %endif
2745:
2746: mov zF, zB
2747: and zF, FLAG_S
2748:
2749: %ifdef EMULATE_WEIRD_STUFF
2750: mov dh, zC
2751: inc dh
2752: add dh, dl
2753: jnc %%otir_nocarry
2754: or zF, FLAG_H|FLAG_C
2755: %%otir_nocarry:
2756: shr dl, 6
2757: and edx, FLAG_N
2758: or zF, dl
2759: %endif
2760: sub zPC, 2 ; rewind to instruction start
2761: EXIT
2762:
2763: %%otir_zero:
2764: mov zF, FLAG_Z|FLAG_P
2765: %ifdef EMULATE_BITS_3_5
2766: mov [z80_flag35], zF
2767: %endif
2768: %ifdef EMULATE_WEIRD_STUFF
2769: mov dh, zC
2770: inc dh
2771: add dh, dl
2772: jnc %%otir_nocarry2
2773: or zF, FLAG_H|FLAG_C
2774: %%otir_nocarry2:
2775: shr dl, 6
2776: and edx, FLAG_N
2777: or zF, dl
2778: %endif
2779: DO_CYCLES
2780: NEXT
2781: %endmacro
2782:
2783: ; Out from (HL) into BC, decrease HL, decrease B, repeat
2784: %macro OTDR 0
2785: %%otdr_loop:
2786: mov edi, ezHL
2787: MEMREAD
2788: movzx edi, zC ; high byte clear? (documentation is fuzzy)
2789: %ifdef EMULATE_WEIRD_STUFF
2790: push edx ; preserve the value
2791: %endif
2792: IOWRITE
2793: %ifdef EMULATE_WEIRD_STUFF
2794: pop edx
2795: %endif
2796:
2797: dec zHL
2798: dec zB
2799: jz %%otdr_zero
2800:
2801: %ifdef EMULATE_R_REGISTER
2802: inc zR
2803: %endif
2804: sub [z80_ICount], dword extra_cycles
2805: ja near %%otdr_loop
2806:
2807: ; out of cycles, but not finished
2808: %ifdef EMULATE_BITS_3_5
2809: mov [z80_flag35], zB
2810: %endif
2811:
2812: mov zF, zB
2813: and zF, FLAG_S
2814:
2815: %ifdef EMULATE_WEIRD_STUFF
2816: mov dh, zC
2817: inc dh
2818: add dh, dl
2819: jnc %%otdr_nocarry
2820: or zF, FLAG_H|FLAG_C
2821: %%otdr_nocarry:
2822: shr dl, 6
2823: and edx, FLAG_N
2824: or zF, dl
2825: %endif
2826: sub zPC, 2 ; rewind to instruction start
2827: EXIT
2828:
2829: %%otdr_zero:
2830: mov zF, FLAG_Z|FLAG_P
2831: %ifdef EMULATE_BITS_3_5
2832: mov [z80_flag35], zF
2833: %endif
2834: %ifdef EMULATE_WEIRD_STUFF
2835: mov dh, zC
2836: inc dh
2837: add dh, dl
2838: jnc %%otdr_nocarry2
2839: or zF, FLAG_H|FLAG_C
2840: %%otdr_nocarry2:
2841: shr dl, 6
2842: and edx, FLAG_N
2843: or zF, dl
2844: %endif
2845: DO_CYCLES
2846: NEXT
2847: %endmacro
2848:
2849: ; BCD adjust
2850: %macro DAA 0
2851: test zF, FLAG_H
2852: jnz %%daa_h_set
2853: and eax, 03ffh
2854: mov ax, [DAA_Table + eax*2]
2855: %ifdef EMULATE_BITS_3_5
2856: mov [z80_flag35], zF
2857: %endif
2858: DO_CYCLES
2859: NEXT
2860:
2861: %%daa_h_set:
2862: and eax, 03ffh
2863: mov ax, [DAA_Table + eax*2 + 4*512]
2864: %ifdef EMULATE_BITS_3_5
2865: mov [z80_flag35], zF
2866: %endif
2867: DO_CYCLES
2868: NEXT
2869: %endmacro
2870:
2871: ; Complement A
2872: %macro CPL 0
2873: not zA
2874: or zF, FLAG_H|FLAG_N
2875: %ifdef EMULATE_BITS_3_5
2876: mov [z80_flag35], zA
2877: %endif
2878: DO_CYCLES
2879: NEXT
2880: %endmacro
2881:
2882: ; Negate A
2883: %macro NEG 0
2884: neg zA
2885: lahf
2886: %ifdef EMULATE_BITS_3_5
2887: mov [z80_flag35], zA
2888: %endif
2889: jo %%neg_overflow
2890: and zF, ~FLAG_P
2891: DO_CYCLES
2892: NEXT
2893:
2894: %%neg_overflow:
2895: or zF, FLAG_P
2896: DO_CYCLES
2897: NEXT
2898: %endmacro
2899:
2900: ; Set carry flag
2901: %macro SCF 0
2902: and zF, FLAG_S|FLAG_Z|FLAG_P
2903: or zF, FLAG_C
2904: %ifdef EMULATE_BITS_3_5
2905: mov [z80_flag35], zA
2906: %endif
2907: DO_CYCLES
2908: NEXT
2909: %endmacro
2910:
2911: ; Complement carry flag
2912: %macro CCF 0
2913: test zF, FLAG_C
2914: jz %%set_carry
2915: and zF, FLAG_S|FLAG_Z|FLAG_P
2916: or zF, FLAG_H
2917: %ifdef EMULATE_BITS_3_5
2918: mov [z80_flag35], zA
2919: %endif
2920: DO_CYCLES
2921: NEXT
2922:
2923: %%set_carry:
2924: SCF
2925: %endmacro
2926:
2927: ; No operation
2928: %macro NOP 0
2929: DO_CYCLES
2930: NEXT
2931: %endmacro
2932:
2933: ; Halt the processor
2934: %macro HALT 0
2935: and [z80_ICount], dword 3
2936: sub [z80_ICount], dword 4
2937: mov [z80_halted], byte 1
2938: EXIT
2939: %endmacro
2940:
2941: ; Enable interrupts
2942: %macro EI 0
2943: mov dl, FLAG_P ; set the P/V bit, for use in "LD I,A" etc
2944: mov [z80_IFF1], dl
2945: mov [z80_IFF2], dl
2946:
2947: ; force the next instruction to be executed, regardless of ICount
2948: ; then force an IRQ check after it.
2949: mov [z80_afterEI], byte 1
2950: push eax
2951: mov eax, [z80_ICount] ; set ICount to zero, so it will terminate
2952: mov [z80_TempICount], eax ; after the next instruction.
2953: mov [z80_ICount], dword 1 ; we can then pick it up again and carry on.
2954: pop eax
2955: NEXT
2956: %endmacro
2957:
2958: ; Disable interrupts
2959: %macro DI 0
2960: xor edx, edx
2961: mov [z80_IFF1], dl
2962: mov [z80_IFF2], dl
2963: DO_CYCLES
2964: NEXT
2965: %endmacro
2966:
2967: ; Set interrupt mode
2968: %macro IM 1
2969: mov [z80_IM], byte %1
2970: DO_CYCLES
2971: NEXT
2972: %endmacro
2973:
2974: ;----------------------------------------------------------------------------;
2975: ; Bring in the opcodes...
2976: %include 'raze.inc'
2977: ;----------------------------------------------------------------------------;
2978:
2979: ;----------------------------------------------------------------------------;
2980: ; Support functions:
2981:
2982: DEF op, cb, 0, 0
2983: %ifdef EMULATE_R_REGISTER
2984: inc zR
2985: %endif
2986: GETBYTE
2987: jmp [CBTable+edx*4]
2988:
2989: DEF op, ed, 0, 0
2990: %ifdef EMULATE_R_REGISTER
2991: inc zR
2992: %endif
2993: GETBYTE
2994: jmp [EDTable+edx*4]
2995:
2996: DEF op, dd, 0, 0
2997: %ifdef EMULATE_R_REGISTER
2998: inc zR
2999: %endif
3000: GETBYTE
3001: jmp [DDTable+edx*4]
3002:
3003: DEF op, fd, 0, 0
3004: %ifdef EMULATE_R_REGISTER
3005: inc zR
3006: %endif
3007: GETBYTE
3008: jmp [FDTable+edx*4]
3009:
3010: DEF dd, cb, 0, 0
3011: %ifdef EMULATE_R_REGISTER
3012: inc zR
3013: %endif
3014: GETDISP
3015: add di, zIX
3016: push edi
3017: GETBYTE
3018: pop edi
3019: jmp [DDCBTable+edx*4]
3020:
3021: DEF fd, cb, 0, 0
3022: %ifdef EMULATE_R_REGISTER
3023: inc zR
3024: %endif
3025: GETDISP
3026: add di, zIY
3027: push edi
3028: GETBYTE
3029: pop edi
3030: jmp [DDCBTable+edx*4]
3031:
3032: DEF ed, xx, 8, 0
3033: %ifdef EMULATE_R_REGISTER
3034: inc zR
3035: %endif
3036: DO_CYCLES
3037: NEXT
3038:
3039: DEF dd, xx, 4, 0
3040: dec zPC
3041: DO_CYCLES
3042: NEXT
3043:
3044: DEF fd, xx, 0, 0
3045: dec zPC
3046: DO_CYCLES
3047: NEXT
3048:
3049: ; called when out-of-cycles
3050: z80_finish:
3051: cmp [z80_afterEI], byte 1 ; test for the post-EI behaviour
3052: jne near really_finish
3053: push eax
3054: mov eax, [z80_TempICount]
3055: mov [z80_ICount], eax
3056: mov [z80_afterEI], byte 0
3057: pop eax
3058: CHECK_IRQ
3059: sub dword [z80_ICount], 4 ; subtract EI's cycles
3060: jbe near z80_finish
3061: NEXT
3062:
3063: really_finish:
3064: ; merge bits 3 and 5 of the flags into the regs
3065: and zF, ~(FLAG_3|FLAG_5)
3066: mov dl, [z80_flag35]
3067: and dl, FLAG_3|FLAG_5
3068: or zF, dl
3069:
3070: mov [z80_AF], ezAF
3071: mov [z80_HL], ezHL
3072: mov [z80_BC], ezBC
3073: mov [z80_PC], ezPC
3074: mov [z80_R], zR
3075: pop ebp
3076: pop edi
3077: pop esi
3078: pop ebx
3079: mov eax, [z80_Initial_ICount]
3080: sub eax, [z80_ICount]
3081: ret
3082:
3083: z80_default_in:
3084: z80_default_read:
3085: mov eax, 0ffh
3086: ret
3087:
3088: z80_default_out:
3089: z80_default_write:
3090: z80_default_reti:
3091: z80_default_fetch_callback:
3092: ret
3093:
3094: ; called to look up a read handler
3095: ; address is on the stack
3096: read_dispatcher:
3097: mov eax, [esp+4]
3098: mov edx, _read_handlers
3099: rd_find:
3100: add edx, 16
3101: cmp [edx-16], eax
3102: ja rd_find
3103: cmp [edx-12], eax
3104: jb rd_find
3105:
3106: cmp [edx-8], dword 1
3107: je rd_handler
3108:
3109: add eax, [edx-4]
3110: movzx eax, byte [eax]
3111: ret
3112:
3113: rd_handler:
3114: jmp [edx-4] ; call the GCC function
3115:
3116: ; called to look up a write handler
3117: ; address+value are on the stack
3118: write_dispatcher:
3119: mov eax, [esp+4]
3120: mov edx, _write_handlers
3121: wd_find:
3122: add edx, 16
3123: cmp [edx-16], eax
3124: ja wd_find
3125: cmp [edx-12], eax
3126: jb wd_find
3127:
3128: cmp [edx-8], dword 1
3129: je wd_handler
3130:
3131: add eax, [edx-4]
3132: mov ecx, [esp+8]
3133: mov [eax], cl
3134: ret
3135:
3136: wd_handler:
3137: jmp [edx-4] ; call the GCC function
3138:
3139: ; int z80_emulate(int cycles)
3140: ; Emulate for 'cycles' T-states,
3141: ; Returns the number of cycles actually emulated.
1.1.1.2 ! root 3142: cglobal z80_emulate
1.1 root 3143: z80_emulate:
3144: mov eax, [esp+4]
3145: push ebx
3146: push esi
3147: push edi
3148: push ebp
3149:
3150: add eax, [z80_Extra_Cycles]
3151: mov [z80_ICount], eax
3152: mov [z80_Initial_ICount], eax
3153: xor edx, edx
3154: xor edi, edi
3155: mov [z80_Extra_Cycles], edx
3156: mov [z80_afterEI], dl
3157: mov ezAF, [z80_AF]
3158: mov ezHL, [z80_HL]
3159: mov ezBC, [z80_BC]
3160: mov ezPC, [z80_PC]
3161: mov zR, [z80_R]
3162: mov [z80_flag35], zF ; take out bits 3/5
3163: cmp [z80_halted], byte 0
3164: je not_halted
3165: and [z80_ICount], dword 3 ; If we're halted, just skip it all.
3166: sub [z80_ICount], dword 4
3167: EXIT
3168: not_halted:
3169: NEXT
3170:
3171: ; void z80_reset(void)
3172: ; Resets the Z80.
1.1.1.2 ! root 3173: cglobal z80_reset
1.1 root 3174: z80_reset:
3175: push edi
3176: xor eax, eax ; just zero it all
3177: mov edi, context_start
3178: mov ecx, (registers_end - context_start)
3179: rep stosb
3180: pop edi
3181: mov [z80_IX], word 0ffffh
3182: mov [z80_IY], word 0ffffh
3183: mov [z80_AF], word 04000h
3184: ret
3185:
3186: ; void z80_raise_IRQ(UBYTE vector)
3187: ; Causes an interrupt with the given vector.
3188: ; In IM 0, the vector has to be an RST opcode.
3189: ; If interrupts are disabled, the interrupt will still happen as long as
3190: ; the IRQ line stays raised.
1.1.1.2 ! root 3191: cglobal z80_raise_IRQ
1.1 root 3192: z80_raise_IRQ:
3193: mov [z80_IRQLine], byte 1
3194: mov eax, [esp+4]
3195: mov [z80_IRQVector], al
3196:
3197: xor edx, edx
3198: push ebx
3199: push esi
3200: push edi
3201: push ebp
3202: CALLGCC_END ; grab our Z80 regs
3203:
3204: CHECK_IRQ
3205:
3206: CALLGCC_START
3207: pop ebp
3208: pop edi
3209: pop esi
3210: pop ebx
3211: ret
3212:
3213: ; void z80_lower_IRQ(void)
3214: ; Lowers the IRQ line.
1.1.1.2 ! root 3215: cglobal z80_lower_IRQ
1.1 root 3216: z80_lower_IRQ:
3217: mov [z80_IRQLine], byte 0
3218: ret
3219:
3220: ; void z80_cause_NMI(void)
3221: ; Causes a non-maskable interrupt.
3222: ; This will always be accepted.
3223: ; There is no raise/lower functions, as the NMI is edge-triggered.
1.1.1.2 ! root 3224: cglobal z80_cause_NMI
1.1 root 3225: z80_cause_NMI:
3226: xor edx, edx
3227: push ebx
3228: push esi
3229: push edi
3230: push ebp
3231: CALLGCC_END ; grab our Z80 regs
3232:
3233: ; disable interrupts
3234: mov [z80_IFF1], byte 0
3235:
3236: ; take up 11 T-states
3237: add [z80_Extra_Cycles], dword 11
3238: %ifdef EMULATE_R_REGISTER
3239: inc zR
3240: %endif
3241:
3242: mov [z80_halted], byte 0 ; Un-HALT us.
3243:
3244: mov edx, ezPC ; write the PC
3245: dec zSP
3246:
3247: xchg dl, dh
3248: mov edi, ezSP
3249: MEMWRITE
3250: dec zSP
3251: mov edx, ezPC
3252: mov edi, ezSP
3253: MEMWRITE
3254:
3255: mov ezPC, 66h ; set the new PC
3256:
3257: CALLGCC_START
3258: pop ebp
3259: pop edi
3260: pop esi
3261: pop ebx
3262: ret
3263:
3264: ; int z80_get_context_size(void)
3265: ; Returns the size of the context, in bytes
1.1.1.2 ! root 3266: cglobal z80_get_context_size
1.1 root 3267: z80_get_context_size:
3268: mov eax, (context_end - context_start) + 4 ; +4 for a safety buffer
3269: ret
3270:
3271:
3272: ; void z80_set_context(void *context)
3273: ; Copy the given context to the current Z80.
1.1.1.2 ! root 3274: cglobal z80_set_context
1.1 root 3275: z80_set_context:
3276: push esi
3277: push edi
3278: mov ecx, (context_end - context_start) / 4
3279: mov esi, [esp+12]
3280: mov edi, context_start
3281: rep movsd
3282: pop edi
3283: pop esi
3284: ret
3285:
3286: ; void z80_get_context(void *context)
3287: ; Copy the current Z80 to the given context.
1.1.1.2 ! root 3288: cglobal z80_get_context
1.1 root 3289: z80_get_context:
3290: push esi
3291: push edi
3292: mov ecx, (context_end - context_start) / 4
3293: mov edi, [esp+12]
3294: mov esi, context_start
3295: rep movsd
3296: pop edi
3297: pop esi
3298: ret
3299:
3300: ; int z80_get_cycles_elapsed(void)
3301: ; Returns the number of cycles emulated since z80_emulate was called.
1.1.1.2 ! root 3302: cglobal z80_get_cycles_elapsed
1.1 root 3303: z80_get_cycles_elapsed:
3304: mov eax, [z80_Initial_ICount]
3305: sub eax, [z80_ICount]
3306: cmp [z80_afterEI], byte 0
3307: je z80_gcd_fin
3308: sub eax, [z80_TempICount]
3309: z80_gcd_fin:
3310: ret
3311:
3312: ; void z80_stop_emulating(void)
3313: ; Stops the emulation dead. (waits for the current instruction to finish
3314: ; first though).
3315: ; The return value from z80_execute will obviously be lower than expected.
1.1.1.2 ! root 3316: cglobal z80_stop_emulating
1.1 root 3317: z80_stop_emulating:
3318: mov eax, [z80_ICount]
3319: sub [z80_Initial_ICount], eax
3320: cmp [z80_afterEI], byte 0
3321: je z80_se_fin
3322: mov ecx, [z80_TempICount]
3323: sub [z80_Initial_ICount], ecx
3324: z80_se_fin:
3325: mov [z80_ICount], dword 0
3326: mov [z80_TempICount], dword 0
3327: ret
3328:
3329: ; void z80_skip_idle(void)
3330: ; Stops the emulation dead. (waits for the current instruction to finish
3331: ; first though).
3332: ; The return value from z80_execute will appear as though it had executed
3333: ; all the instructions like normal.
1.1.1.2 ! root 3334: cglobal z80_skip_idle
1.1 root 3335: z80_skip_idle:
3336: mov [z80_ICount], dword 0
3337: mov [z80_TempICount], dword 0
3338: ret
3339:
3340: ; void z80_do_wait_states(int n)
3341: ; Halts the CPU temporarily, to execute 'n' memory wait states.
1.1.1.2 ! root 3342: cglobal z80_do_wait_states
1.1 root 3343: z80_do_wait_states:
3344: add [z80_Initial_ICount], eax
3345: ret
3346:
3347: ; UWORD z80_get_reg(z80_register reg)
3348: ; Return the value of the specified register.
1.1.1.2 ! root 3349: cglobal z80_get_reg
1.1 root 3350: z80_get_reg:
3351: mov ecx, [esp+4]
3352: cmp ecx, Z80_REG_HL2
3353: mov eax, [context_start + ecx*4]
3354: jbe getreg_simple
3355:
3356: cmp ecx, Z80_REG_IFF1
3357: mov al, [z80_IFF1]
3358: je getreg_boolean
3359:
3360: cmp ecx, Z80_REG_IFF2
3361: mov al, [z80_IFF2]
3362: je getreg_boolean
3363:
3364: cmp ecx, Z80_REG_IRQLine
3365: mov al, [z80_IRQLine]
3366: je getreg_boolean
3367:
3368: cmp ecx, Z80_REG_Halted
3369: mov al, [z80_halted]
3370: je getreg_boolean
3371:
3372: cmp ecx, Z80_REG_IM
3373: movzx eax, byte [z80_IM]
3374: je getreg_finish
3375:
3376: cmp ecx, Z80_REG_IRQVector
3377: movzx eax, byte [z80_IRQVector]
3378: je getreg_finish
3379:
3380: ; construct IR
3381: mov eax, [z80_R]
3382: and eax, 7fh
3383: mov edx, [z80_R2]
3384: and edx, 80h
3385: or eax, edx
3386: mov ah, byte [z80_I]
3387: ret
3388:
3389: getreg_simple:
3390: cmp ecx, Z80_REG_AF
3391: je getreg_swap
3392: cmp ecx, Z80_REG_AF2
3393: je getreg_swap
3394: getreg_finish:
3395: ret
3396: getreg_swap:
3397: xchg al, ah ; swap A and F
3398: ret
3399:
3400: getreg_boolean:
3401: and eax, 0ffh
3402: jz getreg_finish
3403: mov al, 1
3404: ret
3405:
3406: ; void z80_set_reg(z80_register reg, UWORD value)
3407: ; Set the specified register to a new value.
1.1.1.2 ! root 3408: cglobal z80_set_reg
1.1 root 3409: z80_set_reg:
3410: mov ecx, [esp+4]
3411: mov eax, [esp+8]
3412: and eax, 0ffffh
3413: cmp ecx, Z80_REG_HL2
3414: jbe setreg_simple
3415:
3416: cmp ecx, Z80_REG_IFF1
3417: lea edx, [z80_IFF1]
3418: jbe setreg_boolean
3419:
3420: cmp ecx, Z80_REG_IFF2
3421: lea edx, [z80_IFF2]
3422: jbe setreg_boolean
3423:
3424: cmp ecx, Z80_REG_IRQLine
3425: lea edx, [z80_IRQLine]
3426: je setreg_boolean
3427:
3428: cmp ecx, Z80_REG_Halted
3429: lea edx, [z80_halted]
3430: je setreg_boolean
3431:
3432: cmp ecx, Z80_REG_IM
3433: lea edx, [z80_IM]
3434: je setreg_value
3435:
3436: cmp ecx, Z80_REG_IRQVector
3437: lea edx, [z80_IRQVector]
3438: je setreg_value
3439:
3440: ; deconstruct IR
3441: mov [z80_I], ah
3442: mov [z80_R2], eax
3443: mov [z80_R], eax
3444: ret
3445:
3446: setreg_simple:
3447: cmp ecx, Z80_REG_AF
3448: je setreg_swap
3449: cmp ecx, Z80_REG_AF2
3450: je setreg_swap
3451: setreg_finish:
3452: mov [context_start + ecx*4], eax
3453: ret
3454: setreg_swap:
3455: xchg al, ah ; swap A and F
3456: mov [context_start + ecx*4], eax
3457: ret
3458:
3459: setreg_boolean:
3460: test eax, eax
3461: jz setreg_value
3462: mov al, FLAG_P
3463:
3464: setreg_value:
3465: mov [edx], al
3466: ret
3467:
3468: ; void z80_init_memmap(void)
3469: ; Reset the current memory map
1.1.1.2 ! root 3470: cglobal z80_init_memmap
1.1 root 3471: z80_init_memmap:
3472: mov [z80_In], dword z80_default_in
3473: mov [z80_Out], dword z80_default_out
3474: mov [z80_RetI], dword z80_default_reti
3475: mov [z80_Fetch_Callback], dword z80_default_fetch_callback
3476:
3477: push edi ; clear the memory handlers
3478: mov eax, -1
3479: mov ecx, MAX_MEM_HANDLERS*4
3480: mov edi, _read_handlers
3481: rep stosd
3482: mov ecx, MAX_MEM_HANDLERS*4
3483: mov edi, _write_handlers
3484: rep stosd
3485:
3486: ; reset the read table
3487: mov edi, z80_Read
3488: mov ecx, 100h
3489: clear_read:
3490: mov [edi], dword z80_default_read
3491: add edi, 8
3492: loop clear_read
3493:
3494: ; reset the write table
3495: mov edi, z80_Write
3496: mov ecx, 100h
3497: clear_write:
3498: mov [edi], dword z80_default_write
3499: add edi, 8
3500: loop clear_write
3501:
3502: pop edi
3503: ret
3504:
3505: ; void z80_end_memmap(void)
3506: ; Finishes the current memory map
1.1.1.2 ! root 3507: cglobal z80_end_memmap
1.1 root 3508: z80_end_memmap:
3509: ; put the entry at the end of the read table
3510: mov edx, _read_handlers
3511: er_find:
3512: add edx, 16
3513: cmp [edx-16], dword (-1)
3514: jne er_find
3515: sub edx, 16
3516:
3517: ; put it in there
3518: mov [edx], dword 0
3519: mov [edx+4], dword 0ffffh
3520: mov [edx+8], dword 0
3521: mov [edx+12], dword z80_default_read
3522:
3523: ; put the entry at the end of the write table
3524: mov edx, _write_handlers
3525: ew_find:
3526: add edx, 16
3527: cmp [edx-16], dword (-1)
3528: jne ew_find
3529: sub edx, 16
3530:
3531: ; put it in there
3532: mov [edx], dword 0
3533: mov [edx+4], dword 0ffffh
3534: mov [edx+8], dword 0
3535: mov [edx+12], dword z80_default_write
3536: ret
3537:
3538: ; void z80_map_fetch(UWORD start, UWORD end, UBYTE *memory)
3539: ; Set the given area for op-code fetching
3540: ; start/end = the area it covers
3541: ; memory = the ROM/RAM to read from
1.1.1.2 ! root 3542: cglobal z80_map_fetch
1.1 root 3543: z80_map_fetch:
3544: push ebx
3545: mov eax, [esp+8]
3546: mov ebx, [esp+12]
3547: mov ecx, [esp+16]
3548: and eax, 0ffffh
3549: and ebx, 0ffffh
3550: sub ecx, eax
3551:
3552: mf_loop:
3553: ; if there's no area left inbetween, stop now.
3554: mov edx, eax
3555: shr edx, 8
3556:
3557: cmp eax, ebx
3558: ja mf_finish
3559:
3560: mov [z80_Fetch+edx*4], ecx
3561: add eax, 0100h
3562: jmp mf_loop
3563:
3564: mf_finish:
3565: pop ebx
3566: ret
3567:
3568: ; void z80_map_read(UWORD start, UWORD end, UBYTE *memory)
3569: ; Moves a Z80_MAP_MAPPED area to use a different region of memory
3570: ; start/end = the area it covers (must be page-aligned)
3571: ; memory = the ROM/RAM to read from
1.1.1.2 ! root 3572: cglobal z80_map_read
1.1 root 3573: z80_map_read:
3574: push ebx
3575: mov eax, [esp+8]
3576: mov ebx, [esp+12]
3577: mov ecx, [esp+16]
3578: and eax, 0ffffh
3579: and ebx, 0ffffh
3580: sub ecx, eax
3581:
3582: mr_loop:
3583: ; if there's no area left inbetween, stop now.
3584: mov edx, eax
3585: shr edx, 8
3586:
3587: cmp eax, ebx
3588: ja mr_finish
3589:
3590: mov [z80_Read+edx*8], dword 0
3591: mov [z80_Read+edx*8+4], ecx
3592: add eax, 0100h
3593: jmp mr_loop
3594:
3595: mr_finish:
3596: pop ebx
3597: ret
3598:
3599: ; void z80_map_write(UWORD start, UWORD end, UBYTE *memory)
3600: ; Moves a Z80_MAP_MAPPED area to use a different region of memory
3601: ; start/end = the area it covers (must be page-aligned)
3602: ; memory = the ROM/RAM to read from
1.1.1.2 ! root 3603: cglobal z80_map_write
1.1 root 3604: z80_map_write:
3605: push ebx
3606: mov eax, [esp+8]
3607: mov ebx, [esp+12]
3608: mov ecx, [esp+16]
3609: and eax, 0ffffh
3610: and ebx, 0ffffh
3611: sub ecx, eax
3612:
3613: mw_loop:
3614: ; if there's no area left inbetween, stop now.
3615: mov edx, eax
3616: shr edx, 8
3617:
3618: cmp eax, ebx
3619: ja mw_finish
3620:
3621: mov [z80_Write+edx*8], dword 0
3622: mov [z80_Write+edx*8+4], ecx
3623: add eax, 0100h
3624: jmp mw_loop
3625:
3626: mw_finish:
3627: pop ebx
3628: ret
3629:
3630: ; void z80_add_read(UWORD start, UWORD end, int method, void *data)
3631: ; Add a READ memory handler to the memory map
3632: ; start/end = the area it covers
3633: ; method = 0 for direct, 1 for handled
3634: ; data = RAM for direct, handler for handled
1.1.1.2 ! root 3635: cglobal z80_add_read
1.1 root 3636: z80_add_read:
3637: push ebx
3638: mov eax, [esp+8]
3639: mov ebx, [esp+12]
3640: mov ecx, [esp+20]
3641: and eax, 0ffffh
3642: and ebx, 0ffffh
3643:
3644: ; put the entry in the read table first
3645: mov edx, _read_handlers
3646: ar_find:
3647: add edx, 16
3648: cmp [edx-16], dword (-1)
3649: jne ar_find
3650: sub edx, 16
3651:
3652: ; put it in there
3653: mov [edx], eax
3654: mov [edx+4], ebx
3655: mov eax, [esp+16]
3656: mov [edx+8], eax
3657:
3658: mov eax, ecx ; if direct, subtract the start from the memory area
3659: push ebx
3660: mov ebx, [esp+12]
3661: and ebx, 0ffffh
3662: cmp [esp+20], dword 1
3663: je ar_dont_adjust
3664: sub eax, ebx
3665: ar_dont_adjust:
3666: mov [edx+12], eax
3667:
3668: mov eax, ebx
3669: pop ebx
3670:
3671: ; process the start, so it's page aligned
3672: test al, al
3673: jz ar_start_done
3674:
3675: ; put the start handler to go to the dispatcher
3676: mov edx, eax
3677: shr edx, 8
3678: mov [z80_Read+edx*8], dword read_dispatcher
3679: xor al, al
3680: add eax, 0100h
3681:
3682: ar_start_done:
3683: ; process the end, so it's page aligned
3684: cmp bl, 0ffh
3685: je ar_end_done
3686:
3687: ; put the end handler to go to the dispatcher
3688: mov edx, ebx
3689: shr edx, 8
3690: mov [z80_Read+edx*8], dword read_dispatcher
3691: mov bl, 0ffh
3692: sub ebx, 0100h
3693:
3694: ar_end_done:
3695:
3696: sub ecx, eax
3697: ar_loop:
3698: ; if there's no area left inbetween, stop now.
3699: mov edx, eax
3700: shr edx, 8
3701:
3702: cmp eax, ebx
3703: jg ar_finish
3704:
3705: cmp [esp+16], dword 0
3706: je ar_put_direct
3707:
3708: push ecx
3709: mov ecx, [esp+24]
3710: mov [z80_Read+edx*8], ecx
3711: pop ecx
3712: add eax, 0100h
3713: jmp ar_loop
3714:
3715: ar_put_direct:
3716: mov [z80_Read+edx*8], dword 0
3717: mov [z80_Read+edx*8+4], ecx
3718: add eax, 0100h
3719: jmp ar_loop
3720:
3721: ar_finish:
3722: pop ebx
3723: ret
3724:
3725: ; void z80_add_write(UWORD start, UWORD end, int method, void *data)
3726: ; Add a WRITE memory handler to the memory map
3727: ; start/end = the area it covers
3728: ; method = 0 for direct, 1 for handled
3729: ; data = RAM for direct, handler for handled
1.1.1.2 ! root 3730: cglobal z80_add_write
1.1 root 3731: z80_add_write:
3732: push ebx
3733: mov eax, [esp+8]
3734: mov ebx, [esp+12]
3735: mov ecx, [esp+20]
3736: and eax, 0ffffh
3737: and ebx, 0ffffh
3738:
3739: ; put the entry in the read table first
3740: mov edx, _write_handlers
3741: aw_find:
3742: add edx, 16
3743: cmp [edx-16], dword (-1)
3744: jne aw_find
3745: sub edx, 16
3746:
3747: ; put it in there
3748: mov [edx], eax
3749: mov [edx+4], ebx
3750: mov eax, [esp+16]
3751: mov [edx+8], eax
3752:
3753: mov eax, ecx ; if direct, subtract the start from the memory area
3754: push ebx
3755: mov ebx, [esp+12]
3756: and ebx, 0ffffh
3757: cmp [esp+20], dword 1
3758: je aw_dont_adjust
3759: sub eax, ebx
3760: aw_dont_adjust:
3761: mov [edx+12], eax
3762:
3763: mov eax, ebx
3764: pop ebx
3765:
3766: ; process the start, so it's page aligned
3767: test al, al
3768: jz aw_start_done
3769:
3770: ; put the start handler to go to the dispatcher
3771: mov edx, eax
3772: shr edx, 8
3773: mov [z80_Write+edx*8], dword write_dispatcher
3774: xor al, al
3775: add eax, 0100h
3776:
3777: aw_start_done:
3778: ; process the end, so it's page aligned
3779: cmp bl, 0ffh
3780: je aw_end_done
3781:
3782: ; put the end handler to go to the dispatcher
3783: mov edx, ebx
3784: shr edx, 8
3785: mov [z80_Write+edx*8], dword write_dispatcher
3786: mov bl, 0ffh
3787: sub ebx, 0100h
3788:
3789: aw_end_done:
3790:
3791: sub ecx, eax
3792: aw_loop:
3793: ; if there's no area left inbetween, stop now.
3794: mov edx, eax
3795: shr edx, 8
3796:
3797: cmp eax, ebx
3798: jg aw_finish
3799:
3800: cmp [esp+16], dword 0
3801: je aw_put_direct
3802:
3803: push ecx
3804: mov ecx, [esp+24]
3805: mov [z80_Write+edx*8], ecx
3806: pop ecx
3807: add eax, 0100h
3808: jmp aw_loop
3809:
3810: aw_put_direct:
3811: mov [z80_Write+edx*8], dword 0
3812: mov [z80_Write+edx*8+4], ecx
3813: add eax, 0100h
3814: jmp aw_loop
3815:
3816: aw_finish:
3817: pop ebx
3818: ret
3819:
3820: ; void z80_set_in(UBYTE (*handler)(UWORD port))
3821: ; Set the IN port handler to the given function
1.1.1.2 ! root 3822: cglobal z80_set_in
1.1 root 3823: z80_set_in:
3824: mov eax, [esp+4]
3825: mov [z80_In], eax
3826: ret
3827:
3828: ; void z80_set_out(void (*handler)(UWORD port, UBYTE value))
3829: ; Set the OUT port handler to the given function
1.1.1.2 ! root 3830: cglobal z80_set_out
1.1 root 3831: z80_set_out:
3832: mov eax, [esp+4]
3833: mov [z80_Out], eax
3834: ret
3835:
3836: ; void z80_set_reti(void (*handler)(void))
3837: ; Set the RETI handler to the given function
1.1.1.2 ! root 3838: cglobal z80_set_reti
1.1 root 3839: z80_set_reti:
3840: mov eax, [esp+4]
3841: mov [z80_RetI], eax
3842: ret
3843:
3844: ; void z80_set_fetch_callback(void (*handler)(UWORD pc))
3845: ; Set the fetch callback to the given function
1.1.1.2 ! root 3846: cglobal z80_set_fetch_callback
1.1 root 3847: z80_set_fetch_callback:
3848: mov eax, [esp+4]
3849: mov [z80_Fetch_Callback], eax
3850: ret
3851:
3852: ;----------------------------------------------------------------------------;
3853: ; the jump tables
3854: OpTable:
3855: dd op_00, op_01, op_02, op_03, op_04, op_05, op_06, op_07
3856: dd op_08, op_09, op_0a, op_0b, op_0c, op_0d, op_0e, op_0f
3857: dd op_10, op_11, op_12, op_13, op_14, op_15, op_16, op_17
3858: dd op_18, op_19, op_1a, op_1b, op_1c, op_1d, op_1e, op_1f
3859: dd op_20, op_21, op_22, op_23, op_24, op_25, op_26, op_27
3860: dd op_28, op_29, op_2a, op_2b, op_2c, op_2d, op_2e, op_2f
3861: dd op_30, op_31, op_32, op_33, op_34, op_35, op_36, op_37
3862: dd op_38, op_39, op_3a, op_3b, op_3c, op_3d, op_3e, op_3f
3863: dd op_40, op_41, op_42, op_43, op_44, op_45, op_46, op_47
3864: dd op_48, op_49, op_4a, op_4b, op_4c, op_4d, op_4e, op_4f
3865: dd op_50, op_51, op_52, op_53, op_54, op_55, op_56, op_57
3866: dd op_58, op_59, op_5a, op_5b, op_5c, op_5d, op_5e, op_5f
3867: dd op_60, op_61, op_62, op_63, op_64, op_65, op_66, op_67
3868: dd op_68, op_69, op_6a, op_6b, op_6c, op_6d, op_6e, op_6f
3869: dd op_70, op_71, op_72, op_73, op_74, op_75, op_76, op_77
3870: dd op_78, op_79, op_7a, op_7b, op_7c, op_7d, op_7e, op_7f
3871: dd op_80, op_81, op_82, op_83, op_84, op_85, op_86, op_87
3872: dd op_88, op_89, op_8a, op_8b, op_8c, op_8d, op_8e, op_8f
3873: dd op_90, op_91, op_92, op_93, op_94, op_95, op_96, op_97
3874: dd op_98, op_99, op_9a, op_9b, op_9c, op_9d, op_9e, op_9f
3875: dd op_a0, op_a1, op_a2, op_a3, op_a4, op_a5, op_a6, op_a7
3876: dd op_a8, op_a9, op_aa, op_ab, op_ac, op_ad, op_ae, op_af
3877: dd op_b0, op_b1, op_b2, op_b3, op_b4, op_b5, op_b6, op_b7
3878: dd op_b8, op_b9, op_ba, op_bb, op_bc, op_bd, op_be, op_bf
3879: dd op_c0, op_c1, op_c2, op_c3, op_c4, op_c5, op_c6, op_c7
3880: dd op_c8, op_c9, op_ca, op_cb, op_cc, op_cd, op_ce, op_cf
3881: dd op_d0, op_d1, op_d2, op_d3, op_d4, op_d5, op_d6, op_d7
3882: dd op_d8, op_d9, op_da, op_db, op_dc, op_dd, op_de, op_df
3883: dd op_e0, op_e1, op_e2, op_e3, op_e4, op_e5, op_e6, op_e7
3884: dd op_e8, op_e9, op_ea, op_eb, op_ec, op_ed, op_ee, op_ef
3885: dd op_f0, op_f1, op_f2, op_f3, op_f4, op_f5, op_f6, op_f7
3886: dd op_f8, op_f9, op_fa, op_fb, op_fc, op_fd, op_fe, op_ff
3887:
3888: CBTable:
3889: dd cb_00, cb_01, cb_02, cb_03, cb_04, cb_05, cb_06, cb_07
3890: dd cb_08, cb_09, cb_0a, cb_0b, cb_0c, cb_0d, cb_0e, cb_0f
3891: dd cb_10, cb_11, cb_12, cb_13, cb_14, cb_15, cb_16, cb_17
3892: dd cb_18, cb_19, cb_1a, cb_1b, cb_1c, cb_1d, cb_1e, cb_1f
3893: dd cb_20, cb_21, cb_22, cb_23, cb_24, cb_25, cb_26, cb_27
3894: dd cb_28, cb_29, cb_2a, cb_2b, cb_2c, cb_2d, cb_2e, cb_2f
3895: dd cb_30, cb_31, cb_32, cb_33, cb_34, cb_35, cb_36, cb_37
3896: dd cb_38, cb_39, cb_3a, cb_3b, cb_3c, cb_3d, cb_3e, cb_3f
3897: dd cb_40, cb_41, cb_42, cb_43, cb_44, cb_45, cb_46, cb_47
3898: dd cb_48, cb_49, cb_4a, cb_4b, cb_4c, cb_4d, cb_4e, cb_4f
3899: dd cb_50, cb_51, cb_52, cb_53, cb_54, cb_55, cb_56, cb_57
3900: dd cb_58, cb_59, cb_5a, cb_5b, cb_5c, cb_5d, cb_5e, cb_5f
3901: dd cb_60, cb_61, cb_62, cb_63, cb_64, cb_65, cb_66, cb_67
3902: dd cb_68, cb_69, cb_6a, cb_6b, cb_6c, cb_6d, cb_6e, cb_6f
3903: dd cb_70, cb_71, cb_72, cb_73, cb_74, cb_75, cb_76, cb_77
3904: dd cb_78, cb_79, cb_7a, cb_7b, cb_7c, cb_7d, cb_7e, cb_7f
3905: dd cb_80, cb_81, cb_82, cb_83, cb_84, cb_85, cb_86, cb_87
3906: dd cb_88, cb_89, cb_8a, cb_8b, cb_8c, cb_8d, cb_8e, cb_8f
3907: dd cb_90, cb_91, cb_92, cb_93, cb_94, cb_95, cb_96, cb_97
3908: dd cb_98, cb_99, cb_9a, cb_9b, cb_9c, cb_9d, cb_9e, cb_9f
3909: dd cb_a0, cb_a1, cb_a2, cb_a3, cb_a4, cb_a5, cb_a6, cb_a7
3910: dd cb_a8, cb_a9, cb_aa, cb_ab, cb_ac, cb_ad, cb_ae, cb_af
3911: dd cb_b0, cb_b1, cb_b2, cb_b3, cb_b4, cb_b5, cb_b6, cb_b7
3912: dd cb_b8, cb_b9, cb_ba, cb_bb, cb_bc, cb_bd, cb_be, cb_bf
3913: dd cb_c0, cb_c1, cb_c2, cb_c3, cb_c4, cb_c5, cb_c6, cb_c7
3914: dd cb_c8, cb_c9, cb_ca, cb_cb, cb_cc, cb_cd, cb_ce, cb_cf
3915: dd cb_d0, cb_d1, cb_d2, cb_d3, cb_d4, cb_d5, cb_d6, cb_d7
3916: dd cb_d8, cb_d9, cb_da, cb_db, cb_dc, cb_dd, cb_de, cb_df
3917: dd cb_e0, cb_e1, cb_e2, cb_e3, cb_e4, cb_e5, cb_e6, cb_e7
3918: dd cb_e8, cb_e9, cb_ea, cb_eb, cb_ec, cb_ed, cb_ee, cb_ef
3919: dd cb_f0, cb_f1, cb_f2, cb_f3, cb_f4, cb_f5, cb_f6, cb_f7
3920: dd cb_f8, cb_f9, cb_fa, cb_fb, cb_fc, cb_fd, cb_fe, cb_ff
3921:
3922: EDTable:
3923: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3924: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3925: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3926: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3927: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3928: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3929: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3930: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3931: dd ed_40, ed_41, ed_42, ed_43, ed_44, ed_45, ed_46, ed_47
3932: dd ed_48, ed_49, ed_4a, ed_4b, ed_4c, ed_4d, ed_4e, ed_4f
3933: dd ed_50, ed_51, ed_52, ed_53, ed_54, ed_55, ed_56, ed_57
3934: dd ed_58, ed_59, ed_5a, ed_5b, ed_5c, ed_5d, ed_5e, ed_5f
3935: dd ed_60, ed_61, ed_62, ed_63, ed_64, ed_65, ed_66, ed_67
3936: dd ed_68, ed_69, ed_6a, ed_6b, ed_6c, ed_6d, ed_6e, ed_6f
3937: dd ed_70, ed_71, ed_72, ed_73, ed_74, ed_75, ed_76, ed_xx
3938: dd ed_78, ed_79, ed_7a, ed_7b, ed_7c, ed_7d, ed_7e, ed_xx
3939: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3940: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3941: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3942: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3943: dd ed_a0, ed_a1, ed_a2, ed_a3, ed_xx, ed_xx, ed_xx, ed_xx
3944: dd ed_a8, ed_a9, ed_aa, ed_ab, ed_xx, ed_xx, ed_xx, ed_xx
3945: dd ed_b0, ed_b1, ed_b2, ed_b3, ed_xx, ed_xx, ed_xx, ed_xx
3946: dd ed_b8, ed_b9, ed_ba, ed_bb, ed_xx, ed_xx, ed_xx, ed_xx
3947: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3948: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3949: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3950: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3951: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3952: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3953: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3954: dd ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx, ed_xx
3955:
3956: DDTable:
3957: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3958: dd dd_xx, dd_09, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3959: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3960: dd dd_xx, dd_19, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3961: dd dd_xx, dd_21, dd_22, dd_23, dd_24, dd_25, dd_26, dd_xx
3962: dd dd_xx, dd_29, dd_2a, dd_2b, dd_2c, dd_2d, dd_2e, dd_xx
3963: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_34, dd_35, dd_36, dd_xx
3964: dd dd_xx, dd_39, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3965: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_44, dd_45, dd_46, dd_xx
3966: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_4c, dd_4d, dd_4e, dd_xx
3967: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_54, dd_55, dd_56, dd_xx
3968: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_5c, dd_5d, dd_5e, dd_xx
3969: dd dd_60, dd_61, dd_62, dd_63, dd_xx, dd_65, dd_66, dd_67
3970: dd dd_68, dd_69, dd_6a, dd_6b, dd_6c, dd_xx, dd_6e, dd_6f
3971: dd dd_70, dd_71, dd_72, dd_73, dd_74, dd_75, dd_xx, dd_77
3972: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_7c, dd_7d, dd_7e, dd_xx
3973: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_84, dd_85, dd_86, dd_xx
3974: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_8c, dd_8d, dd_8e, dd_xx
3975: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_94, dd_95, dd_96, dd_xx
3976: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_9c, dd_9d, dd_9e, dd_xx
3977: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_a4, dd_a5, dd_a6, dd_xx
3978: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_ac, dd_ad, dd_ae, dd_xx
3979: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_b4, dd_b5, dd_b6, dd_xx
3980: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_bc, dd_bd, dd_be, dd_xx
3981: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3982: dd dd_xx, dd_xx, dd_xx, dd_cb, dd_xx, dd_xx, dd_xx, dd_xx
3983: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3984: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3985: dd dd_xx, dd_e1, dd_xx, dd_e3, dd_xx, dd_e5, dd_xx, dd_xx
3986: dd dd_xx, dd_e9, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3987: dd dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3988: dd dd_xx, dd_f9, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx, dd_xx
3989:
3990: FDTable:
3991: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3992: dd fd_xx, fd_09, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3993: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3994: dd fd_xx, fd_19, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3995: dd fd_xx, fd_21, fd_22, fd_23, fd_24, fd_25, fd_26, fd_xx
3996: dd fd_xx, fd_29, fd_2a, fd_2b, fd_2c, fd_2d, fd_2e, fd_xx
3997: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_34, fd_35, fd_36, fd_xx
3998: dd fd_xx, fd_39, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
3999: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_44, fd_45, fd_46, fd_xx
4000: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_4c, fd_4d, fd_4e, fd_xx
4001: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_54, fd_55, fd_56, fd_xx
4002: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_5c, fd_5d, fd_5e, fd_xx
4003: dd fd_60, fd_61, fd_62, fd_63, fd_xx, fd_65, fd_66, fd_67
4004: dd fd_68, fd_69, fd_6a, fd_6b, fd_6c, fd_xx, fd_6e, fd_6f
4005: dd fd_70, fd_71, fd_72, fd_73, fd_74, fd_75, fd_xx, fd_77
4006: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_7c, fd_7d, fd_7e, fd_xx
4007: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_84, fd_85, fd_86, fd_xx
4008: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_8c, fd_8d, fd_8e, fd_xx
4009: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_94, fd_95, fd_96, fd_xx
4010: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_9c, fd_9d, fd_9e, fd_xx
4011: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_a4, fd_a5, fd_a6, fd_xx
4012: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_ac, fd_ad, fd_ae, fd_xx
4013: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_b4, fd_b5, fd_b6, fd_xx
4014: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_bc, fd_bd, fd_be, fd_xx
4015: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4016: dd fd_xx, fd_xx, fd_xx, fd_cb, fd_xx, fd_xx, fd_xx, fd_xx
4017: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4018: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4019: dd fd_xx, fd_e1, fd_xx, fd_e3, fd_xx, fd_e5, fd_xx, fd_xx
4020: dd fd_xx, fd_e9, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4021: dd fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4022: dd fd_xx, fd_f9, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx, fd_xx
4023:
4024: DDCBTable:
4025: dd ddcb_00, ddcb_01, ddcb_02, ddcb_03, ddcb_04, ddcb_05, ddcb_06, ddcb_07
4026: dd ddcb_08, ddcb_09, ddcb_0a, ddcb_0b, ddcb_0c, ddcb_0d, ddcb_0e, ddcb_0f
4027: dd ddcb_10, ddcb_11, ddcb_12, ddcb_13, ddcb_14, ddcb_15, ddcb_16, ddcb_17
4028: dd ddcb_18, ddcb_19, ddcb_1a, ddcb_1b, ddcb_1c, ddcb_1d, ddcb_1e, ddcb_1f
4029: dd ddcb_20, ddcb_21, ddcb_22, ddcb_23, ddcb_24, ddcb_25, ddcb_26, ddcb_27
4030: dd ddcb_28, ddcb_29, ddcb_2a, ddcb_2b, ddcb_2c, ddcb_2d, ddcb_2e, ddcb_2f
4031: dd ddcb_30, ddcb_31, ddcb_32, ddcb_33, ddcb_34, ddcb_35, ddcb_36, ddcb_37
4032: dd ddcb_38, ddcb_39, ddcb_3a, ddcb_3b, ddcb_3c, ddcb_3d, ddcb_3e, ddcb_3f
4033: dd ddcb_40, ddcb_41, ddcb_42, ddcb_43, ddcb_44, ddcb_45, ddcb_46, ddcb_47
4034: dd ddcb_48, ddcb_49, ddcb_4a, ddcb_4b, ddcb_4c, ddcb_4d, ddcb_4e, ddcb_4f
4035: dd ddcb_50, ddcb_51, ddcb_52, ddcb_53, ddcb_54, ddcb_55, ddcb_56, ddcb_57
4036: dd ddcb_58, ddcb_59, ddcb_5a, ddcb_5b, ddcb_5c, ddcb_5d, ddcb_5e, ddcb_5f
4037: dd ddcb_60, ddcb_61, ddcb_62, ddcb_63, ddcb_64, ddcb_65, ddcb_66, ddcb_67
4038: dd ddcb_68, ddcb_69, ddcb_6a, ddcb_6b, ddcb_6c, ddcb_6d, ddcb_6e, ddcb_6f
4039: dd ddcb_70, ddcb_71, ddcb_72, ddcb_73, ddcb_74, ddcb_75, ddcb_76, ddcb_77
4040: dd ddcb_78, ddcb_79, ddcb_7a, ddcb_7b, ddcb_7c, ddcb_7d, ddcb_7e, ddcb_7f
4041: dd ddcb_80, ddcb_81, ddcb_82, ddcb_83, ddcb_84, ddcb_85, ddcb_86, ddcb_87
4042: dd ddcb_88, ddcb_89, ddcb_8a, ddcb_8b, ddcb_8c, ddcb_8d, ddcb_8e, ddcb_8f
4043: dd ddcb_90, ddcb_91, ddcb_92, ddcb_93, ddcb_94, ddcb_95, ddcb_96, ddcb_97
4044: dd ddcb_98, ddcb_99, ddcb_9a, ddcb_9b, ddcb_9c, ddcb_9d, ddcb_9e, ddcb_9f
4045: dd ddcb_a0, ddcb_a1, ddcb_a2, ddcb_a3, ddcb_a4, ddcb_a5, ddcb_a6, ddcb_a7
4046: dd ddcb_a8, ddcb_a9, ddcb_aa, ddcb_ab, ddcb_ac, ddcb_ad, ddcb_ae, ddcb_af
4047: dd ddcb_b0, ddcb_b1, ddcb_b2, ddcb_b3, ddcb_b4, ddcb_b5, ddcb_b6, ddcb_b7
4048: dd ddcb_b8, ddcb_b9, ddcb_ba, ddcb_bb, ddcb_bc, ddcb_bd, ddcb_be, ddcb_bf
4049: dd ddcb_c0, ddcb_c1, ddcb_c2, ddcb_c3, ddcb_c4, ddcb_c5, ddcb_c6, ddcb_c7
4050: dd ddcb_c8, ddcb_c9, ddcb_ca, ddcb_cb, ddcb_cc, ddcb_cd, ddcb_ce, ddcb_cf
4051: dd ddcb_d0, ddcb_d1, ddcb_d2, ddcb_d3, ddcb_d4, ddcb_d5, ddcb_d6, ddcb_d7
4052: dd ddcb_d8, ddcb_d9, ddcb_da, ddcb_db, ddcb_dc, ddcb_dd, ddcb_de, ddcb_df
4053: dd ddcb_e0, ddcb_e1, ddcb_e2, ddcb_e3, ddcb_e4, ddcb_e5, ddcb_e6, ddcb_e7
4054: dd ddcb_e8, ddcb_e9, ddcb_ea, ddcb_eb, ddcb_ec, ddcb_ed, ddcb_ee, ddcb_ef
4055: dd ddcb_f0, ddcb_f1, ddcb_f2, ddcb_f3, ddcb_f4, ddcb_f5, ddcb_f6, ddcb_f7
4056: dd ddcb_f8, ddcb_f9, ddcb_fa, ddcb_fb, ddcb_fc, ddcb_fd, ddcb_fe, ddcb_ff
4057:
4058:
4059: ;----------------------------------------------------------------------------;
4060: ; flag tables ('borrowed' from MAZE, by Ishmair)
4061: INC_Table:
4062: DB 0,0,0,0,0,0,0,8,8,8,8,8,8,8,8,16,0,0,0,0
4063: DB 0,0,0,8,8,8,8,8,8,8,8,48,32,32,32,32,32,32,32,40
4064: DB 40,40,40,40,40,40,40,48,32,32,32,32,32,32,32,40,40,40,40,40
4065: DB 40,40,40,16,0,0,0,0,0,0,0,8,8,8,8,8,8,8,8,16
4066: DB 0,0,0,0,0,0,0,8,8,8,8,8,8,8,8,48,32,32,32,32
4067: DB 32,32,32,40,40,40,40,40,40,40,40,48,32,32,32,32,32,32,32,40
4068: DB 40,40,40,40,40,40,40,148,128,128,128,128,128,128,128,136,136,136,136,136
4069: DB 136,136,136,144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,176
4070: DB 160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,176,160,160,160,160
4071: DB 160,160,160,168,168,168,168,168,168,168,168,144,128,128,128,128,128,128,128,136
4072: DB 136,136,136,136,136,136,136,144,128,128,128,128,128,128,128,136,136,136,136,136
4073: DB 136,136,136,176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,176
4074: DB 160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,80
4075:
4076: DEC_Table:
4077: DB 186,66,2,2,2,2,2,2,2,10,10,10,10,10,10,10,26,2,2,2
4078: DB 2,2,2,2,2,10,10,10,10,10,10,10,26,34,34,34,34,34,34,34
4079: DB 34,42,42,42,42,42,42,42,58,34,34,34,34,34,34,34,34,42,42,42
4080: DB 42,42,42,42,58,2,2,2,2,2,2,2,2,10,10,10,10,10,10,10
4081: DB 26,2,2,2,2,2,2,2,2,10,10,10,10,10,10,10,26,34,34,34
4082: DB 34,34,34,34,34,42,42,42,42,42,42,42,58,34,34,34,34,34,34,34
4083: DB 34,42,42,42,42,42,42,42,62,130,130,130,130,130,130,130,130,138,138,138
4084: DB 138,138,138,138,154,130,130,130,130,130,130,130,130,138,138,138,138,138,138,138
4085: DB 154,162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,162,162,162
4086: DB 162,162,162,162,162,170,170,170,170,170,170,170,186,130,130,130,130,130,130,130
4087: DB 130,138,138,138,138,138,138,138,154,130,130,130,130,130,130,130,130,138,138,138
4088: DB 138,138,138,138,154,162,162,162,162,162,162,162,162,170,170,170,170,170,170,170
4089: DB 186,162,162,162,162,162,162,162,162,170,170,170,170,170,170,170
4090:
4091: ; DAA table ('borrowed' from Z80Emul, by unknown)
4092: DAA_Table:
4093: DW 04400h, 00001h, 00002h, 00403h, 00004h, 00405h, 00406h, 00007h
4094: DW 00808h, 00C09h, 01010h, 01411h, 01412h, 01013h, 01414h, 01015h
4095: DW 00010h, 00411h, 00412h, 00013h, 00414h, 00015h, 00016h, 00417h
4096: DW 00C18h, 00819h, 03020h, 03421h, 03422h, 03023h, 03424h, 03025h
4097: DW 02020h, 02421h, 02422h, 02023h, 02424h, 02025h, 02026h, 02427h
4098: DW 02C28h, 02829h, 03430h, 03031h, 03032h, 03433h, 03034h, 03435h
4099: DW 02430h, 02031h, 02032h, 02433h, 02034h, 02435h, 02436h, 02037h
4100: DW 02838h, 02C39h, 01040h, 01441h, 01442h, 01043h, 01444h, 01045h
4101: DW 00040h, 00441h, 00442h, 00043h, 00444h, 00045h, 00046h, 00447h
4102: DW 00C48h, 00849h, 01450h, 01051h, 01052h, 01453h, 01054h, 01455h
4103: DW 00450h, 00051h, 00052h, 00453h, 00054h, 00455h, 00456h, 00057h
4104: DW 00858h, 00C59h, 03460h, 03061h, 03062h, 03463h, 03064h, 03465h
4105: DW 02460h, 02061h, 02062h, 02463h, 02064h, 02465h, 02466h, 02067h
4106: DW 02868h, 02C69h, 03070h, 03471h, 03472h, 03073h, 03474h, 03075h
4107: DW 02070h, 02471h, 02472h, 02073h, 02474h, 02075h, 02076h, 02477h
4108: DW 02C78h, 02879h, 09080h, 09481h, 09482h, 09083h, 09484h, 09085h
4109: DW 08080h, 08481h, 08482h, 08083h, 08484h, 08085h, 08086h, 08487h
4110: DW 08C88h, 08889h, 09490h, 09091h, 09092h, 09493h, 09094h, 09495h
4111: DW 08490h, 08091h, 08092h, 08493h, 08094h, 08495h, 08496h, 08097h
4112: DW 08898h, 08C99h, 05500h, 01101h, 01102h, 01503h, 01104h, 01505h
4113: DW 04500h, 00101h, 00102h, 00503h, 00104h, 00505h, 00506h, 00107h
4114: DW 00908h, 00D09h, 01110h, 01511h, 01512h, 01113h, 01514h, 01115h
4115: DW 00110h, 00511h, 00512h, 00113h, 00514h, 00115h, 00116h, 00517h
4116: DW 00D18h, 00919h, 03120h, 03521h, 03522h, 03123h, 03524h, 03125h
4117: DW 02120h, 02521h, 02522h, 02123h, 02524h, 02125h, 02126h, 02527h
4118: DW 02D28h, 02929h, 03530h, 03131h, 03132h, 03533h, 03134h, 03535h
4119: DW 02530h, 02131h, 02132h, 02533h, 02134h, 02535h, 02536h, 02137h
4120: DW 02938h, 02D39h, 01140h, 01541h, 01542h, 01143h, 01544h, 01145h
4121: DW 00140h, 00541h, 00542h, 00143h, 00544h, 00145h, 00146h, 00547h
4122: DW 00D48h, 00949h, 01550h, 01151h, 01152h, 01553h, 01154h, 01555h
4123: DW 00550h, 00151h, 00152h, 00553h, 00154h, 00555h, 00556h, 00157h
4124: DW 00958h, 00D59h, 03560h, 03161h, 03162h, 03563h, 03164h, 03565h
4125: DW 02560h, 02161h, 02162h, 02563h, 02164h, 02565h, 02566h, 02167h
4126: DW 02968h, 02D69h, 03170h, 03571h, 03572h, 03173h, 03574h, 03175h
4127: DW 02170h, 02571h, 02572h, 02173h, 02574h, 02175h, 02176h, 02577h
4128: DW 02D78h, 02979h, 09180h, 09581h, 09582h, 09183h, 09584h, 09185h
4129: DW 08180h, 08581h, 08582h, 08183h, 08584h, 08185h, 08186h, 08587h
4130: DW 08D88h, 08989h, 09590h, 09191h, 09192h, 09593h, 09194h, 09595h
4131: DW 08590h, 08191h, 08192h, 08593h, 08194h, 08595h, 08596h, 08197h
4132: DW 08998h, 08D99h, 0B5A0h, 0B1A1h, 0B1A2h, 0B5A3h, 0B1A4h, 0B5A5h
4133: DW 0A5A0h, 0A1A1h, 0A1A2h, 0A5A3h, 0A1A4h, 0A5A5h, 0A5A6h, 0A1A7h
4134: DW 0A9A8h, 0ADA9h, 0B1B0h, 0B5B1h, 0B5B2h, 0B1B3h, 0B5B4h, 0B1B5h
4135: DW 0A1B0h, 0A5B1h, 0A5B2h, 0A1B3h, 0A5B4h, 0A1B5h, 0A1B6h, 0A5B7h
4136: DW 0ADB8h, 0A9B9h, 095C0h, 091C1h, 091C2h, 095C3h, 091C4h, 095C5h
4137: DW 085C0h, 081C1h, 081C2h, 085C3h, 081C4h, 085C5h, 085C6h, 081C7h
4138: DW 089C8h, 08DC9h, 091D0h, 095D1h, 095D2h, 091D3h, 095D4h, 091D5h
4139: DW 081D0h, 085D1h, 085D2h, 081D3h, 085D4h, 081D5h, 081D6h, 085D7h
4140: DW 08DD8h, 089D9h, 0B1E0h, 0B5E1h, 0B5E2h, 0B1E3h, 0B5E4h, 0B1E5h
4141: DW 0A1E0h, 0A5E1h, 0A5E2h, 0A1E3h, 0A5E4h, 0A1E5h, 0A1E6h, 0A5E7h
4142: DW 0ADE8h, 0A9E9h, 0B5F0h, 0B1F1h, 0B1F2h, 0B5F3h, 0B1F4h, 0B5F5h
4143: DW 0A5F0h, 0A1F1h, 0A1F2h, 0A5F3h, 0A1F4h, 0A5F5h, 0A5F6h, 0A1F7h
4144: DW 0A9F8h, 0ADF9h, 05500h, 01101h, 01102h, 01503h, 01104h, 01505h
4145: DW 04500h, 00101h, 00102h, 00503h, 00104h, 00505h, 00506h, 00107h
4146: DW 00908h, 00D09h, 01110h, 01511h, 01512h, 01113h, 01514h, 01115h
4147: DW 00110h, 00511h, 00512h, 00113h, 00514h, 00115h, 00116h, 00517h
4148: DW 00D18h, 00919h, 03120h, 03521h, 03522h, 03123h, 03524h, 03125h
4149: DW 02120h, 02521h, 02522h, 02123h, 02524h, 02125h, 02126h, 02527h
4150: DW 02D28h, 02929h, 03530h, 03131h, 03132h, 03533h, 03134h, 03535h
4151: DW 02530h, 02131h, 02132h, 02533h, 02134h, 02535h, 02536h, 02137h
4152: DW 02938h, 02D39h, 01140h, 01541h, 01542h, 01143h, 01544h, 01145h
4153: DW 00140h, 00541h, 00542h, 00143h, 00544h, 00145h, 00146h, 00547h
4154: DW 00D48h, 00949h, 01550h, 01151h, 01152h, 01553h, 01154h, 01555h
4155: DW 00550h, 00151h, 00152h, 00553h, 00154h, 00555h, 00556h, 00157h
4156: DW 00958h, 00D59h, 03560h, 03161h, 03162h, 03563h, 03164h, 03565h
4157: DW 04600h, 00201h, 00202h, 00603h, 00204h, 00605h, 00606h, 00207h
4158: DW 00A08h, 00E09h, 00204h, 00605h, 00606h, 00207h, 00A08h, 00E09h
4159: DW 00210h, 00611h, 00612h, 00213h, 00614h, 00215h, 00216h, 00617h
4160: DW 00E18h, 00A19h, 00614h, 00215h, 00216h, 00617h, 00E18h, 00A19h
4161: DW 02220h, 02621h, 02622h, 02223h, 02624h, 02225h, 02226h, 02627h
4162: DW 02E28h, 02A29h, 02624h, 02225h, 02226h, 02627h, 02E28h, 02A29h
4163: DW 02630h, 02231h, 02232h, 02633h, 02234h, 02635h, 02636h, 02237h
4164: DW 02A38h, 02E39h, 02234h, 02635h, 02636h, 02237h, 02A38h, 02E39h
4165: DW 00240h, 00641h, 00642h, 00243h, 00644h, 00245h, 00246h, 00647h
4166: DW 00E48h, 00A49h, 00644h, 00245h, 00246h, 00647h, 00E48h, 00A49h
4167: DW 00650h, 00251h, 00252h, 00653h, 00254h, 00655h, 00656h, 00257h
4168: DW 00A58h, 00E59h, 00254h, 00655h, 00656h, 00257h, 00A58h, 00E59h
4169: DW 02660h, 02261h, 02262h, 02663h, 02264h, 02665h, 02666h, 02267h
4170: DW 02A68h, 02E69h, 02264h, 02665h, 02666h, 02267h, 02A68h, 02E69h
4171: DW 02270h, 02671h, 02672h, 02273h, 02674h, 02275h, 02276h, 02677h
4172: DW 02E78h, 02A79h, 02674h, 02275h, 02276h, 02677h, 02E78h, 02A79h
4173: DW 08280h, 08681h, 08682h, 08283h, 08684h, 08285h, 08286h, 08687h
4174: DW 08E88h, 08A89h, 08684h, 08285h, 08286h, 08687h, 08E88h, 08A89h
4175: DW 08690h, 08291h, 08292h, 08693h, 08294h, 08695h, 08696h, 08297h
4176: DW 08A98h, 08E99h, 02334h, 02735h, 02736h, 02337h, 02B38h, 02F39h
4177: DW 00340h, 00741h, 00742h, 00343h, 00744h, 00345h, 00346h, 00747h
4178: DW 00F48h, 00B49h, 00744h, 00345h, 00346h, 00747h, 00F48h, 00B49h
4179: DW 00750h, 00351h, 00352h, 00753h, 00354h, 00755h, 00756h, 00357h
4180: DW 00B58h, 00F59h, 00354h, 00755h, 00756h, 00357h, 00B58h, 00F59h
4181: DW 02760h, 02361h, 02362h, 02763h, 02364h, 02765h, 02766h, 02367h
4182: DW 02B68h, 02F69h, 02364h, 02765h, 02766h, 02367h, 02B68h, 02F69h
4183: DW 02370h, 02771h, 02772h, 02373h, 02774h, 02375h, 02376h, 02777h
4184: DW 02F78h, 02B79h, 02774h, 02375h, 02376h, 02777h, 02F78h, 02B79h
4185: DW 08380h, 08781h, 08782h, 08383h, 08784h, 08385h, 08386h, 08787h
4186: DW 08F88h, 08B89h, 08784h, 08385h, 08386h, 08787h, 08F88h, 08B89h
4187: DW 08790h, 08391h, 08392h, 08793h, 08394h, 08795h, 08796h, 08397h
4188: DW 08B98h, 08F99h, 08394h, 08795h, 08796h, 08397h, 08B98h, 08F99h
4189: DW 0A7A0h, 0A3A1h, 0A3A2h, 0A7A3h, 0A3A4h, 0A7A5h, 0A7A6h, 0A3A7h
4190: DW 0ABA8h, 0AFA9h, 0A3A4h, 0A7A5h, 0A7A6h, 0A3A7h, 0ABA8h, 0AFA9h
4191: DW 0A3B0h, 0A7B1h, 0A7B2h, 0A3B3h, 0A7B4h, 0A3B5h, 0A3B6h, 0A7B7h
4192: DW 0AFB8h, 0ABB9h, 0A7B4h, 0A3B5h, 0A3B6h, 0A7B7h, 0AFB8h, 0ABB9h
4193: DW 087C0h, 083C1h, 083C2h, 087C3h, 083C4h, 087C5h, 087C6h, 083C7h
4194: DW 08BC8h, 08FC9h, 083C4h, 087C5h, 087C6h, 083C7h, 08BC8h, 08FC9h
4195: DW 083D0h, 087D1h, 087D2h, 083D3h, 087D4h, 083D5h, 083D6h, 087D7h
4196: DW 08FD8h, 08BD9h, 087D4h, 083D5h, 083D6h, 087D7h, 08FD8h, 08BD9h
4197: DW 0A3E0h, 0A7E1h, 0A7E2h, 0A3E3h, 0A7E4h, 0A3E5h, 0A3E6h, 0A7E7h
4198: DW 0AFE8h, 0ABE9h, 0A7E4h, 0A3E5h, 0A3E6h, 0A7E7h, 0AFE8h, 0ABE9h
4199: DW 0A7F0h, 0A3F1h, 0A3F2h, 0A7F3h, 0A3F4h, 0A7F5h, 0A7F6h, 0A3F7h
4200: DW 0ABF8h, 0AFF9h, 0A3F4h, 0A7F5h, 0A7F6h, 0A3F7h, 0ABF8h, 0AFF9h
4201: DW 04700h, 00301h, 00302h, 00703h, 00304h, 00705h, 00706h, 00307h
4202: DW 00B08h, 00F09h, 00304h, 00705h, 00706h, 00307h, 00B08h, 00F09h
4203: DW 00310h, 00711h, 00712h, 00313h, 00714h, 00315h, 00316h, 00717h
4204: DW 00F18h, 00B19h, 00714h, 00315h, 00316h, 00717h, 00F18h, 00B19h
4205: DW 02320h, 02721h, 02722h, 02323h, 02724h, 02325h, 02326h, 02727h
4206: DW 02F28h, 02B29h, 02724h, 02325h, 02326h, 02727h, 02F28h, 02B29h
4207: DW 02730h, 02331h, 02332h, 02733h, 02334h, 02735h, 02736h, 02337h
4208: DW 02B38h, 02F39h, 02334h, 02735h, 02736h, 02337h, 02B38h, 02F39h
4209: DW 00340h, 00741h, 00742h, 00343h, 00744h, 00345h, 00346h, 00747h
4210: DW 00F48h, 00B49h, 00744h, 00345h, 00346h, 00747h, 00F48h, 00B49h
4211: DW 00750h, 00351h, 00352h, 00753h, 00354h, 00755h, 00756h, 00357h
4212: DW 00B58h, 00F59h, 00354h, 00755h, 00756h, 00357h, 00B58h, 00F59h
4213: DW 02760h, 02361h, 02362h, 02763h, 02364h, 02765h, 02766h, 02367h
4214: DW 02B68h, 02F69h, 02364h, 02765h, 02766h, 02367h, 02B68h, 02F69h
4215: DW 02370h, 02771h, 02772h, 02373h, 02774h, 02375h, 02376h, 02777h
4216: DW 02F78h, 02B79h, 02774h, 02375h, 02376h, 02777h, 02F78h, 02B79h
4217: DW 08380h, 08781h, 08782h, 08383h, 08784h, 08385h, 08386h, 08787h
4218: DW 08F88h, 08B89h, 08784h, 08385h, 08386h, 08787h, 08F88h, 08B89h
4219: DW 08790h, 08391h, 08392h, 08793h, 08394h, 08795h, 08796h, 08397h
4220: DW 08B98h, 08F99h, 08394h, 08795h, 08796h, 08397h, 08B98h, 08F99h
4221: DW 00406h, 00007h, 00808h, 00C09h, 00C0Ah, 0080Bh, 00C0Ch, 0080Dh
4222: DW 0080Eh, 00C0Fh, 01010h, 01411h, 01412h, 01013h, 01414h, 01015h
4223: DW 00016h, 00417h, 00C18h, 00819h, 0081Ah, 00C1Bh, 0081Ch, 00C1Dh
4224: DW 00C1Eh, 0081Fh, 03020h, 03421h, 03422h, 03023h, 03424h, 03025h
4225: DW 02026h, 02427h, 02C28h, 02829h, 0282Ah, 02C2Bh, 0282Ch, 02C2Dh
4226: DW 02C2Eh, 0282Fh, 03430h, 03031h, 03032h, 03433h, 03034h, 03435h
4227: DW 02436h, 02037h, 02838h, 02C39h, 02C3Ah, 0283Bh, 02C3Ch, 0283Dh
4228: DW 0283Eh, 02C3Fh, 01040h, 01441h, 01442h, 01043h, 01444h, 01045h
4229: DW 00046h, 00447h, 00C48h, 00849h, 0084Ah, 00C4Bh, 0084Ch, 00C4Dh
4230: DW 00C4Eh, 0084Fh, 01450h, 01051h, 01052h, 01453h, 01054h, 01455h
4231: DW 00456h, 00057h, 00858h, 00C59h, 00C5Ah, 0085Bh, 00C5Ch, 0085Dh
4232: DW 0085Eh, 00C5Fh, 03460h, 03061h, 03062h, 03463h, 03064h, 03465h
4233: DW 02466h, 02067h, 02868h, 02C69h, 02C6Ah, 0286Bh, 02C6Ch, 0286Dh
4234: DW 0286Eh, 02C6Fh, 03070h, 03471h, 03472h, 03073h, 03474h, 03075h
4235: DW 02076h, 02477h, 02C78h, 02879h, 0287Ah, 02C7Bh, 0287Ch, 02C7Dh
4236: DW 02C7Eh, 0287Fh, 09080h, 09481h, 09482h, 09083h, 09484h, 09085h
4237: DW 08086h, 08487h, 08C88h, 08889h, 0888Ah, 08C8Bh, 0888Ch, 08C8Dh
4238: DW 08C8Eh, 0888Fh, 09490h, 09091h, 09092h, 09493h, 09094h, 09495h
4239: DW 08496h, 08097h, 08898h, 08C99h, 08C9Ah, 0889Bh, 08C9Ch, 0889Dh
4240: DW 0889Eh, 08C9Fh, 05500h, 01101h, 01102h, 01503h, 01104h, 01505h
4241: DW 00506h, 00107h, 00908h, 00D09h, 00D0Ah, 0090Bh, 00D0Ch, 0090Dh
4242: DW 0090Eh, 00D0Fh, 01110h, 01511h, 01512h, 01113h, 01514h, 01115h
4243: DW 00116h, 00517h, 00D18h, 00919h, 0091Ah, 00D1Bh, 0091Ch, 00D1Dh
4244: DW 00D1Eh, 0091Fh, 03120h, 03521h, 03522h, 03123h, 03524h, 03125h
4245: DW 02126h, 02527h, 02D28h, 02929h, 0292Ah, 02D2Bh, 0292Ch, 02D2Dh
4246: DW 02D2Eh, 0292Fh, 03530h, 03131h, 03132h, 03533h, 03134h, 03535h
4247: DW 02536h, 02137h, 02938h, 02D39h, 02D3Ah, 0293Bh, 02D3Ch, 0293Dh
4248: DW 0293Eh, 02D3Fh, 01140h, 01541h, 01542h, 01143h, 01544h, 01145h
4249: DW 00146h, 00547h, 00D48h, 00949h, 0094Ah, 00D4Bh, 0094Ch, 00D4Dh
4250: DW 00D4Eh, 0094Fh, 01550h, 01151h, 01152h, 01553h, 01154h, 01555h
4251: DW 00556h, 00157h, 00958h, 00D59h, 00D5Ah, 0095Bh, 00D5Ch, 0095Dh
4252: DW 0095Eh, 00D5Fh, 03560h, 03161h, 03162h, 03563h, 03164h, 03565h
4253: DW 02566h, 02167h, 02968h, 02D69h, 02D6Ah, 0296Bh, 02D6Ch, 0296Dh
4254: DW 0296Eh, 02D6Fh, 03170h, 03571h, 03572h, 03173h, 03574h, 03175h
4255: DW 02176h, 02577h, 02D78h, 02979h, 0297Ah, 02D7Bh, 0297Ch, 02D7Dh
4256: DW 02D7Eh, 0297Fh, 09180h, 09581h, 09582h, 09183h, 09584h, 09185h
4257: DW 08186h, 08587h, 08D88h, 08989h, 0898Ah, 08D8Bh, 0898Ch, 08D8Dh
4258: DW 08D8Eh, 0898Fh, 09590h, 09191h, 09192h, 09593h, 09194h, 09595h
4259: DW 08596h, 08197h, 08998h, 08D99h, 08D9Ah, 0899Bh, 08D9Ch, 0899Dh
4260: DW 0899Eh, 08D9Fh, 0B5A0h, 0B1A1h, 0B1A2h, 0B5A3h, 0B1A4h, 0B5A5h
4261: DW 0A5A6h, 0A1A7h, 0A9A8h, 0ADA9h, 0ADAAh, 0A9ABh, 0ADACh, 0A9ADh
4262: DW 0A9AEh, 0ADAFh, 0B1B0h, 0B5B1h, 0B5B2h, 0B1B3h, 0B5B4h, 0B1B5h
4263: DW 0A1B6h, 0A5B7h, 0ADB8h, 0A9B9h, 0A9BAh, 0ADBBh, 0A9BCh, 0ADBDh
4264: DW 0ADBEh, 0A9BFh, 095C0h, 091C1h, 091C2h, 095C3h, 091C4h, 095C5h
4265: DW 085C6h, 081C7h, 089C8h, 08DC9h, 08DCAh, 089CBh, 08DCCh, 089CDh
4266: DW 089CEh, 08DCFh, 091D0h, 095D1h, 095D2h, 091D3h, 095D4h, 091D5h
4267: DW 081D6h, 085D7h, 08DD8h, 089D9h, 089DAh, 08DDBh, 089DCh, 08DDDh
4268: DW 08DDEh, 089DFh, 0B1E0h, 0B5E1h, 0B5E2h, 0B1E3h, 0B5E4h, 0B1E5h
4269: DW 0A1E6h, 0A5E7h, 0ADE8h, 0A9E9h, 0A9EAh, 0ADEBh, 0A9ECh, 0ADEDh
4270: DW 0ADEEh, 0A9EFh, 0B5F0h, 0B1F1h, 0B1F2h, 0B5F3h, 0B1F4h, 0B5F5h
4271: DW 0A5F6h, 0A1F7h, 0A9F8h, 0ADF9h, 0ADFAh, 0A9FBh, 0ADFCh, 0A9FDh
4272: DW 0A9FEh, 0ADFFh, 05500h, 01101h, 01102h, 01503h, 01104h, 01505h
4273: DW 00506h, 00107h, 00908h, 00D09h, 00D0Ah, 0090Bh, 00D0Ch, 0090Dh
4274: DW 0090Eh, 00D0Fh, 01110h, 01511h, 01512h, 01113h, 01514h, 01115h
4275: DW 00116h, 00517h, 00D18h, 00919h, 0091Ah, 00D1Bh, 0091Ch, 00D1Dh
4276: DW 00D1Eh, 0091Fh, 03120h, 03521h, 03522h, 03123h, 03524h, 03125h
4277: DW 02126h, 02527h, 02D28h, 02929h, 0292Ah, 02D2Bh, 0292Ch, 02D2Dh
4278: DW 02D2Eh, 0292Fh, 03530h, 03131h, 03132h, 03533h, 03134h, 03535h
4279: DW 02536h, 02137h, 02938h, 02D39h, 02D3Ah, 0293Bh, 02D3Ch, 0293Dh
4280: DW 0293Eh, 02D3Fh, 01140h, 01541h, 01542h, 01143h, 01544h, 01145h
4281: DW 00146h, 00547h, 00D48h, 00949h, 0094Ah, 00D4Bh, 0094Ch, 00D4Dh
4282: DW 00D4Eh, 0094Fh, 01550h, 01151h, 01152h, 01553h, 01154h, 01555h
4283: DW 00556h, 00157h, 00958h, 00D59h, 00D5Ah, 0095Bh, 00D5Ch, 0095Dh
4284: DW 0095Eh, 00D5Fh, 03560h, 03161h, 03162h, 03563h, 03164h, 03565h
4285: DW 0BEFAh, 0BAFBh, 0BEFCh, 0BAFDh, 0BAFEh, 0BEFFh, 04600h, 00201h
4286: DW 00202h, 00603h, 00204h, 00605h, 00606h, 00207h, 00A08h, 00E09h
4287: DW 01E0Ah, 01A0Bh, 01E0Ch, 01A0Dh, 01A0Eh, 01E0Fh, 00210h, 00611h
4288: DW 00612h, 00213h, 00614h, 00215h, 00216h, 00617h, 00E18h, 00A19h
4289: DW 01A1Ah, 01E1Bh, 01A1Ch, 01E1Dh, 01E1Eh, 01A1Fh, 02220h, 02621h
4290: DW 02622h, 02223h, 02624h, 02225h, 02226h, 02627h, 02E28h, 02A29h
4291: DW 03A2Ah, 03E2Bh, 03A2Ch, 03E2Dh, 03E2Eh, 03A2Fh, 02630h, 02231h
4292: DW 02232h, 02633h, 02234h, 02635h, 02636h, 02237h, 02A38h, 02E39h
4293: DW 03E3Ah, 03A3Bh, 03E3Ch, 03A3Dh, 03A3Eh, 03E3Fh, 00240h, 00641h
4294: DW 00642h, 00243h, 00644h, 00245h, 00246h, 00647h, 00E48h, 00A49h
4295: DW 01A4Ah, 01E4Bh, 01A4Ch, 01E4Dh, 01E4Eh, 01A4Fh, 00650h, 00251h
4296: DW 00252h, 00653h, 00254h, 00655h, 00656h, 00257h, 00A58h, 00E59h
4297: DW 01E5Ah, 01A5Bh, 01E5Ch, 01A5Dh, 01A5Eh, 01E5Fh, 02660h, 02261h
4298: DW 02262h, 02663h, 02264h, 02665h, 02666h, 02267h, 02A68h, 02E69h
4299: DW 03E6Ah, 03A6Bh, 03E6Ch, 03A6Dh, 03A6Eh, 03E6Fh, 02270h, 02671h
4300: DW 02672h, 02273h, 02674h, 02275h, 02276h, 02677h, 02E78h, 02A79h
4301: DW 03A7Ah, 03E7Bh, 03A7Ch, 03E7Dh, 03E7Eh, 03A7Fh, 08280h, 08681h
4302: DW 08682h, 08283h, 08684h, 08285h, 08286h, 08687h, 08E88h, 08A89h
4303: DW 09A8Ah, 09E8Bh, 09A8Ch, 09E8Dh, 09E8Eh, 09A8Fh, 08690h, 08291h
4304: DW 08292h, 08693h, 02334h, 02735h, 02736h, 02337h, 02B38h, 02F39h
4305: DW 03F3Ah, 03B3Bh, 03F3Ch, 03B3Dh, 03B3Eh, 03F3Fh, 00340h, 00741h
4306: DW 00742h, 00343h, 00744h, 00345h, 00346h, 00747h, 00F48h, 00B49h
4307: DW 01B4Ah, 01F4Bh, 01B4Ch, 01F4Dh, 01F4Eh, 01B4Fh, 00750h, 00351h
4308: DW 00352h, 00753h, 00354h, 00755h, 00756h, 00357h, 00B58h, 00F59h
4309: DW 01F5Ah, 01B5Bh, 01F5Ch, 01B5Dh, 01B5Eh, 01F5Fh, 02760h, 02361h
4310: DW 02362h, 02763h, 02364h, 02765h, 02766h, 02367h, 02B68h, 02F69h
4311: DW 03F6Ah, 03B6Bh, 03F6Ch, 03B6Dh, 03B6Eh, 03F6Fh, 02370h, 02771h
4312: DW 02772h, 02373h, 02774h, 02375h, 02376h, 02777h, 02F78h, 02B79h
4313: DW 03B7Ah, 03F7Bh, 03B7Ch, 03F7Dh, 03F7Eh, 03B7Fh, 08380h, 08781h
4314: DW 08782h, 08383h, 08784h, 08385h, 08386h, 08787h, 08F88h, 08B89h
4315: DW 09B8Ah, 09F8Bh, 09B8Ch, 09F8Dh, 09F8Eh, 09B8Fh, 08790h, 08391h
4316: DW 08392h, 08793h, 08394h, 08795h, 08796h, 08397h, 08B98h, 08F99h
4317: DW 09F9Ah, 09B9Bh, 09F9Ch, 09B9Dh, 09B9Eh, 09F9Fh, 0A7A0h, 0A3A1h
4318: DW 0A3A2h, 0A7A3h, 0A3A4h, 0A7A5h, 0A7A6h, 0A3A7h, 0ABA8h, 0AFA9h
4319: DW 0BFAAh, 0BBABh, 0BFACh, 0BBADh, 0BBAEh, 0BFAFh, 0A3B0h, 0A7B1h
4320: DW 0A7B2h, 0A3B3h, 0A7B4h, 0A3B5h, 0A3B6h, 0A7B7h, 0AFB8h, 0ABB9h
4321: DW 0BBBAh, 0BFBBh, 0BBBCh, 0BFBDh, 0BFBEh, 0BBBFh, 087C0h, 083C1h
4322: DW 083C2h, 087C3h, 083C4h, 087C5h, 087C6h, 083C7h, 08BC8h, 08FC9h
4323: DW 09FCAh, 09BCBh, 09FCCh, 09BCDh, 09BCEh, 09FCFh, 083D0h, 087D1h
4324: DW 087D2h, 083D3h, 087D4h, 083D5h, 083D6h, 087D7h, 08FD8h, 08BD9h
4325: DW 09BDAh, 09FDBh, 09BDCh, 09FDDh, 09FDEh, 09BDFh, 0A3E0h, 0A7E1h
4326: DW 0A7E2h, 0A3E3h, 0A7E4h, 0A3E5h, 0A3E6h, 0A7E7h, 0AFE8h, 0ABE9h
4327: DW 0BBEAh, 0BFEBh, 0BBECh, 0BFEDh, 0BFEEh, 0BBEFh, 0A7F0h, 0A3F1h
4328: DW 0A3F2h, 0A7F3h, 0A3F4h, 0A7F5h, 0A7F6h, 0A3F7h, 0ABF8h, 0AFF9h
4329: DW 0BFFAh, 0BBFBh, 0BFFCh, 0BBFDh, 0BBFEh, 0BFFFh, 04700h, 00301h
4330: DW 00302h, 00703h, 00304h, 00705h, 00706h, 00307h, 00B08h, 00F09h
4331: DW 01F0Ah, 01B0Bh, 01F0Ch, 01B0Dh, 01B0Eh, 01F0Fh, 00310h, 00711h
4332: DW 00712h, 00313h, 00714h, 00315h, 00316h, 00717h, 00F18h, 00B19h
4333: DW 01B1Ah, 01F1Bh, 01B1Ch, 01F1Dh, 01F1Eh, 01B1Fh, 02320h, 02721h
4334: DW 02722h, 02323h, 02724h, 02325h, 02326h, 02727h, 02F28h, 02B29h
4335: DW 03B2Ah, 03F2Bh, 03B2Ch, 03F2Dh, 03F2Eh, 03B2Fh, 02730h, 02331h
4336: DW 02332h, 02733h, 02334h, 02735h, 02736h, 02337h, 02B38h, 02F39h
4337: DW 03F3Ah, 03B3Bh, 03F3Ch, 03B3Dh, 03B3Eh, 03F3Fh, 00340h, 00741h
4338: DW 00742h, 00343h, 00744h, 00345h, 00346h, 00747h, 00F48h, 00B49h
4339: DW 01B4Ah, 01F4Bh, 01B4Ch, 01F4Dh, 01F4Eh, 01B4Fh, 00750h, 00351h
4340: DW 00352h, 00753h, 00354h, 00755h, 00756h, 00357h, 00B58h, 00F59h
4341: DW 01F5Ah, 01B5Bh, 01F5Ch, 01B5Dh, 01B5Eh, 01F5Fh, 02760h, 02361h
4342: DW 02362h, 02763h, 02364h, 02765h, 02766h, 02367h, 02B68h, 02F69h
4343: DW 03F6Ah, 03B6Bh, 03F6Ch, 03B6Dh, 03B6Eh, 03F6Fh, 02370h, 02771h
4344: DW 02772h, 02373h, 02774h, 02375h, 02376h, 02777h, 02F78h, 02B79h
4345: DW 03B7Ah, 03F7Bh, 03B7Ch, 03F7Dh, 03F7Eh, 03B7Fh, 08380h, 08781h
4346: DW 08782h, 08383h, 08784h, 08385h, 08386h, 08787h, 08F88h, 08B89h
4347: DW 09B8Ah, 09F8Bh, 09B8Ch, 09F8Dh, 09F8Eh, 09B8Fh, 08790h, 08391h
4348: DW 08392h, 08793h, 08394h, 08795h, 08796h, 08397h, 08B98h, 08F99h
4349:
4350: NEG_Table:
4351: DB 0,66,255,187,254,187,253,187,252,187,251,187,250,187,249,187,248,187,247,179
4352: DB 246,179,245,179,244,179,243,179,242,179,241,179,240,163,239,187,238,187,237,187
4353: DB 236,187,235,187,234,187,233,187,232,187,231,179,230,179,229,179,228,179,227,179
4354: DB 226,179,225,179,224,163,223,155,222,155,221,155,220,155,219,155,218,155,217,155
4355: DB 216,155,215,147,214,147,213,147,212,147,211,147,210,147,209,147,208,131,207,155
4356: DB 206,155,205,155,204,155,203,155,202,155,201,155,200,155,199,147,198,147,197,147
4357: DB 196,147,195,147,194,147,193,147,192,131,191,187,190,187,189,187,188,187,187,187
4358: DB 186,187,185,187,184,187,183,179,182,179,181,179,180,179,179,179,178,179,177,179
4359: DB 176,163,175,187,174,187,173,187,172,187,171,187,170,187,169,187,168,187,167,179
4360: DB 166,179,165,179,164,179,163,179,162,179,161,179,160,163,159,155,158,155,157,155
4361: DB 156,155,155,155,154,155,153,155,152,155,151,147,150,147,149,147,148,147,147,147
4362: DB 146,147,145,147,144,131,143,155,142,155,141,155,140,155,139,155,138,155,137,155
4363: DB 136,155,135,147,134,147,133,147,132,147,131,147,130,147,129,147,128,135,127,59
4364: DB 126,59,125,59,124,59,123,59,122,59,121,59,120,59,119,51,118,51,117,51
4365: DB 116,51,115,51,114,51,113,51,112,35,111,59,110,59,109,59,108,59,107,59
4366: DB 106,59,105,59,104,59,103,51,102,51,101,51,100,51,99,51,98,51,97,51
4367: DB 96,35,95,27,94,27,93,27,92,27,91,27,90,27,89,27,88,27,87,19
4368: DB 86,19,85,19,84,19,83,19,82,19,81,19,80,3,79,27,78,27,77,27
4369: DB 76,27,75,27,74,27,73,27,72,27,71,19,70,19,69,19,68,19,67,19
4370: DB 66,19,65,19,64,3,63,59,62,59,61,59,60,59,59,59,58,59,57,59
4371: DB 56,59,55,51,54,51,53,51,52,51,51,51,50,51,49,51,48,35,47,59
4372: DB 46,59,45,59,44,59,43,59,42,59,41,59,40,59,39,51,38,51,37,51
4373: DB 36,51,35,51,34,51,33,51,32,35,31,27,30,27,29,27,28,27,27,27
4374: DB 26,27,25,27,24,27,23,19,22,19,21,19,20,19,19,19,18,19,17,19
4375: DB 16,3,15,27,14,27,13,27,12,27,11,27,10,27,9,27,8,27,7,19
4376: DB 6,19,5,19,4,19,3,19,2,19,1,19
4377:
4378: ;- the end ------ (blimey) --------------------------------------------------;
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.