![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to raze.reg CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Generator SEGA Genesis emulator] / generator / raze|
Return to raze.reg CVS log | Up to [Generator SEGA Genesis emulator] / generator / raze |
1.1 root 1: ; RAZE - register definitions
2:
3: ;----------------------------------------------------------------------------;
4: ; Flags
5: %define FLAG_C 01h ; carry
6: %define FLAG_N 02h ; negative
7: %define FLAG_P 04h ; parity/overflow
8: %define FLAG_3 08h ; bit 3
9: %define FLAG_H 10h ; half-carry
10: %define FLAG_5 20h ; bit 5
11: %define FLAG_Z 40h ; zero
12: %define FLAG_S 80h ; sign
13:
14: ; set the register mappings.
15: ; we avoid bugs this way and make it simpler.
16:
17: ; 16-bit registers
18: %define zAF ax
19: %define zHL bx
20: %define zBC cx
21: %define zDE word [z80_DE]
22: %define zPC si
23: %define zSP word [z80_SP]
24: %define zIX word [z80_IX]
25: %define zIY word [z80_IY]
26:
27: ; 16-bit registers, zero-extended to 32-bit
28: ; for when a dword transfer is better
29: %define ezAF eax
30: %define ezHL ebx
31: %define ezBC ecx
32: %define ezDE dword [z80_DE]
33: %define ezPC esi
34: %define ezSP dword [z80_SP]
35: %define ezIX dword [z80_IX]
36: %define ezIY dword [z80_IY]
37:
38: ; 8-bit registers
39: %define zF ah
40: %define zA al
41: %define zB ch
42: %define zC cl
43: %define zD byte [z80_DE+1]
44: %define zE byte [z80_DE]
45: %define zH bh
46: %define zL bl
47: %define zIXh byte [z80_IX+1]
48: %define zIXl byte [z80_IX]
49: %define zIYh byte [z80_IY+1]
50: %define zIYl byte [z80_IY]
51:
52: ; 8-bit registers, (accessible by 16-bit registers with l or h)
53: %define hzAF zA
54: %define lzAF zF
55: %define hzBC zB
56: %define lzBC zC
57: %define hzDE zD
58: %define lzDE zE
59: %define hzHL zH
60: %define lzHL zL
61: %define hzIX zIXh
62: %define lzIX zIXl
63: %define hzIY zIYh
64: %define lzIY zIYl
65: %define hzSP byte [z80_SP+1]
66: %define lzSP byte [z80_SP]
67:
68: ; 16-bit registers (prime)
69: %define zAF2 word [z80_AF2]
70: %define zHL2 word [z80_HL2]
71: %define zBC2 word [z80_BC2]
72: %define zDE2 word [z80_DE2]
73:
74: ; 16-bit registers (prime), zero-extended to 32-bit
75: ; for when a dword transfer is better
76: %define ezAF2 dword [z80_AF2]
77: %define ezHL2 dword [z80_HL2]
78: %define ezBC2 dword [z80_BC2]
79: %define ezDE2 dword [z80_DE2]
80:
81: ; Misc
82: %define zI byte [z80_I]
83: %define zR ebp
84:
85: ; get/set reg values
86: %define Z80_REG_AF 0
87: %define Z80_REG_BC 1
88: %define Z80_REG_DE 2
89: %define Z80_REG_HL 3
90: %define Z80_REG_IX 4
91: %define Z80_REG_IY 5
92: %define Z80_REG_PC 6
93: %define Z80_REG_SP 7
94: %define Z80_REG_AF2 8
95: %define Z80_REG_BC2 9
96: %define Z80_REG_DE2 10
97: %define Z80_REG_HL2 11
98: %define Z80_REG_IFF1 12
99: %define Z80_REG_IFF2 13
100: %define Z80_REG_IR 14
101: %define Z80_REG_IM 15
102: %define Z80_REG_IRQVector 16
103: %define Z80_REG_IRQLine 17
104: %define Z80_REG_Halted 18
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.