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1.1 root 1: /*****************************************************************************/
2: /* Generator - Sega Genesis emulation - (c) James Ponder 1997-1998 */
3: /*****************************************************************************/
4: /* */
5: /* cpu68k-0.c */
6: /* */
7: /*****************************************************************************/
8:
9: #include "generator.h"
10: #include "cpu68k.h"
11: #include "mem68k.h"
12: #include "reg68k.h"
13:
14: #include "cpu68k-inline.h"
15:
16: #include <stdio.h>
17:
18: void cpu_op_0a(t_ipc *ipc) /* OR */ {
19: /* mask fff8, bits 0000, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
20: uint8 srcdata = ipc->src;
21: int dstreg = (ipc->opcode >> 0) & 7;
22: uint8 dstdata = DATAREG(dstreg);
23: uint8 outdata = dstdata;
24:
25: outdata|= srcdata;
26: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
27: PC+= 4;
28: }
29:
30: void cpu_op_0b(t_ipc *ipc) /* OR */ {
31: /* mask fff8, bits 0000, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
32: uint8 srcdata = ipc->src;
33: int dstreg = (ipc->opcode >> 0) & 7;
34: uint8 dstdata = DATAREG(dstreg);
35: uint8 outdata = dstdata;
36:
37: outdata|= srcdata;
38: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
39:
40: NFLAG = ((sint8)outdata) < 0;
41: ZFLAG = !outdata;
42: VFLAG = 0;
43: CFLAG = 0;
44: PC+= 4;
45: }
46:
47: void cpu_op_1a(t_ipc *ipc) /* OR */ {
48: /* mask fff8, bits 0010, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
49: uint8 srcdata = ipc->src;
50: int dstreg = (ipc->opcode >> 0) & 7;
51: uint32 dstaddr = ADDRREG(dstreg);
52: uint8 dstdata = fetchbyte(dstaddr);
53: uint8 outdata = dstdata;
54:
55: outdata|= srcdata;
56: storebyte(dstaddr, outdata);
57: PC+= 4;
58: }
59:
60: void cpu_op_1b(t_ipc *ipc) /* OR */ {
61: /* mask fff8, bits 0010, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
62: uint8 srcdata = ipc->src;
63: int dstreg = (ipc->opcode >> 0) & 7;
64: uint32 dstaddr = ADDRREG(dstreg);
65: uint8 dstdata = fetchbyte(dstaddr);
66: uint8 outdata = dstdata;
67:
68: outdata|= srcdata;
69: storebyte(dstaddr, outdata);
70:
71: NFLAG = ((sint8)outdata) < 0;
72: ZFLAG = !outdata;
73: VFLAG = 0;
74: CFLAG = 0;
75: PC+= 4;
76: }
77:
78: void cpu_op_2a(t_ipc *ipc) /* OR */ {
79: /* mask fff8, bits 0018, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
80: uint8 srcdata = ipc->src;
81: int dstreg = (ipc->opcode >> 0) & 7;
82: uint32 dstaddr = ADDRREG(dstreg);
83: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
84: uint8 dstdata = fetchbyte(dstaddr);
85: uint8 outdata = dstdata;
86:
87: outdata|= srcdata;
88: storebyte(dstaddr, outdata);
89: PC+= 4;
90: }
91:
92: void cpu_op_2b(t_ipc *ipc) /* OR */ {
93: /* mask fff8, bits 0018, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
94: uint8 srcdata = ipc->src;
95: int dstreg = (ipc->opcode >> 0) & 7;
96: uint32 dstaddr = ADDRREG(dstreg);
97: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
98: uint8 dstdata = fetchbyte(dstaddr);
99: uint8 outdata = dstdata;
100:
101: outdata|= srcdata;
102: storebyte(dstaddr, outdata);
103:
104: NFLAG = ((sint8)outdata) < 0;
105: ZFLAG = !outdata;
106: VFLAG = 0;
107: CFLAG = 0;
108: PC+= 4;
109: }
110:
111: void cpu_op_3a(t_ipc *ipc) /* OR */ {
112: /* mask fff8, bits 0020, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
113: uint8 srcdata = ipc->src;
114: int dstreg = (ipc->opcode >> 0) & 7;
115: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
116: uint8 dstdata = fetchbyte(dstaddr);
117: uint8 outdata = dstdata;
118:
119: outdata|= srcdata;
120: storebyte(dstaddr, outdata);
121: PC+= 4;
122: }
123:
124: void cpu_op_3b(t_ipc *ipc) /* OR */ {
125: /* mask fff8, bits 0020, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
126: uint8 srcdata = ipc->src;
127: int dstreg = (ipc->opcode >> 0) & 7;
128: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
129: uint8 dstdata = fetchbyte(dstaddr);
130: uint8 outdata = dstdata;
131:
132: outdata|= srcdata;
133: storebyte(dstaddr, outdata);
134:
135: NFLAG = ((sint8)outdata) < 0;
136: ZFLAG = !outdata;
137: VFLAG = 0;
138: CFLAG = 0;
139: PC+= 4;
140: }
141:
142: void cpu_op_4a(t_ipc *ipc) /* OR */ {
143: /* mask fff8, bits 0028, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
144: uint8 srcdata = ipc->src;
145: int dstreg = (ipc->opcode >> 0) & 7;
146: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
147: uint8 dstdata = fetchbyte(dstaddr);
148: uint8 outdata = dstdata;
149:
150: outdata|= srcdata;
151: storebyte(dstaddr, outdata);
152: PC+= 6;
153: }
154:
155: void cpu_op_4b(t_ipc *ipc) /* OR */ {
156: /* mask fff8, bits 0028, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
157: uint8 srcdata = ipc->src;
158: int dstreg = (ipc->opcode >> 0) & 7;
159: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
160: uint8 dstdata = fetchbyte(dstaddr);
161: uint8 outdata = dstdata;
162:
163: outdata|= srcdata;
164: storebyte(dstaddr, outdata);
165:
166: NFLAG = ((sint8)outdata) < 0;
167: ZFLAG = !outdata;
168: VFLAG = 0;
169: CFLAG = 0;
170: PC+= 6;
171: }
172:
173: void cpu_op_5a(t_ipc *ipc) /* OR */ {
174: /* mask fff8, bits 0030, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
175: uint8 srcdata = ipc->src;
176: int dstreg = (ipc->opcode >> 0) & 7;
177: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
178: uint8 dstdata = fetchbyte(dstaddr);
179: uint8 outdata = dstdata;
180:
181: outdata|= srcdata;
182: storebyte(dstaddr, outdata);
183: PC+= 6;
184: }
185:
186: void cpu_op_5b(t_ipc *ipc) /* OR */ {
187: /* mask fff8, bits 0030, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
188: uint8 srcdata = ipc->src;
189: int dstreg = (ipc->opcode >> 0) & 7;
190: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
191: uint8 dstdata = fetchbyte(dstaddr);
192: uint8 outdata = dstdata;
193:
194: outdata|= srcdata;
195: storebyte(dstaddr, outdata);
196:
197: NFLAG = ((sint8)outdata) < 0;
198: ZFLAG = !outdata;
199: VFLAG = 0;
200: CFLAG = 0;
201: PC+= 6;
202: }
203:
204: void cpu_op_6a(t_ipc *ipc) /* OR */ {
205: /* mask ffff, bits 0038, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
206: uint8 srcdata = ipc->src;
207: uint32 dstaddr = ipc->dst;
208: uint8 dstdata = fetchbyte(dstaddr);
209: uint8 outdata = dstdata;
210:
211: outdata|= srcdata;
212: storebyte(dstaddr, outdata);
213: PC+= 6;
214: }
215:
216: void cpu_op_6b(t_ipc *ipc) /* OR */ {
217: /* mask ffff, bits 0038, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
218: uint8 srcdata = ipc->src;
219: uint32 dstaddr = ipc->dst;
220: uint8 dstdata = fetchbyte(dstaddr);
221: uint8 outdata = dstdata;
222:
223: outdata|= srcdata;
224: storebyte(dstaddr, outdata);
225:
226: NFLAG = ((sint8)outdata) < 0;
227: ZFLAG = !outdata;
228: VFLAG = 0;
229: CFLAG = 0;
230: PC+= 6;
231: }
232:
233: void cpu_op_7a(t_ipc *ipc) /* OR */ {
234: /* mask ffff, bits 0039, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
235: uint8 srcdata = ipc->src;
236: uint32 dstaddr = ipc->dst;
237: uint8 dstdata = fetchbyte(dstaddr);
238: uint8 outdata = dstdata;
239:
240: outdata|= srcdata;
241: storebyte(dstaddr, outdata);
242: PC+= 8;
243: }
244:
245: void cpu_op_7b(t_ipc *ipc) /* OR */ {
246: /* mask ffff, bits 0039, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
247: uint8 srcdata = ipc->src;
248: uint32 dstaddr = ipc->dst;
249: uint8 dstdata = fetchbyte(dstaddr);
250: uint8 outdata = dstdata;
251:
252: outdata|= srcdata;
253: storebyte(dstaddr, outdata);
254:
255: NFLAG = ((sint8)outdata) < 0;
256: ZFLAG = !outdata;
257: VFLAG = 0;
258: CFLAG = 0;
259: PC+= 8;
260: }
261:
262: void cpu_op_8a(t_ipc *ipc) /* OR */ {
263: /* mask fff8, bits 0040, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
264: uint16 srcdata = ipc->src;
265: int dstreg = (ipc->opcode >> 0) & 7;
266: uint16 dstdata = DATAREG(dstreg);
267: uint16 outdata = dstdata;
268:
269: outdata|= srcdata;
270: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
271: PC+= 4;
272: }
273:
274: void cpu_op_8b(t_ipc *ipc) /* OR */ {
275: /* mask fff8, bits 0040, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
276: uint16 srcdata = ipc->src;
277: int dstreg = (ipc->opcode >> 0) & 7;
278: uint16 dstdata = DATAREG(dstreg);
279: uint16 outdata = dstdata;
280:
281: outdata|= srcdata;
282: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
283:
284: NFLAG = ((sint16)outdata) < 0;
285: ZFLAG = !outdata;
286: VFLAG = 0;
287: CFLAG = 0;
288: PC+= 4;
289: }
290:
291: void cpu_op_9a(t_ipc *ipc) /* OR */ {
292: /* mask fff8, bits 0050, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
293: uint16 srcdata = ipc->src;
294: int dstreg = (ipc->opcode >> 0) & 7;
295: uint32 dstaddr = ADDRREG(dstreg);
296: uint16 dstdata = fetchword(dstaddr);
297: uint16 outdata = dstdata;
298:
299: outdata|= srcdata;
300: storeword(dstaddr, outdata);
301: PC+= 4;
302: }
303:
304: void cpu_op_9b(t_ipc *ipc) /* OR */ {
305: /* mask fff8, bits 0050, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
306: uint16 srcdata = ipc->src;
307: int dstreg = (ipc->opcode >> 0) & 7;
308: uint32 dstaddr = ADDRREG(dstreg);
309: uint16 dstdata = fetchword(dstaddr);
310: uint16 outdata = dstdata;
311:
312: outdata|= srcdata;
313: storeword(dstaddr, outdata);
314:
315: NFLAG = ((sint16)outdata) < 0;
316: ZFLAG = !outdata;
317: VFLAG = 0;
318: CFLAG = 0;
319: PC+= 4;
320: }
321:
322: void cpu_op_10a(t_ipc *ipc) /* OR */ {
323: /* mask fff8, bits 0058, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
324: uint16 srcdata = ipc->src;
325: int dstreg = (ipc->opcode >> 0) & 7;
326: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
327: uint16 dstdata = fetchword(dstaddr);
328: uint16 outdata = dstdata;
329:
330: outdata|= srcdata;
331: storeword(dstaddr, outdata);
332: PC+= 4;
333: }
334:
335: void cpu_op_10b(t_ipc *ipc) /* OR */ {
336: /* mask fff8, bits 0058, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
337: uint16 srcdata = ipc->src;
338: int dstreg = (ipc->opcode >> 0) & 7;
339: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
340: uint16 dstdata = fetchword(dstaddr);
341: uint16 outdata = dstdata;
342:
343: outdata|= srcdata;
344: storeword(dstaddr, outdata);
345:
346: NFLAG = ((sint16)outdata) < 0;
347: ZFLAG = !outdata;
348: VFLAG = 0;
349: CFLAG = 0;
350: PC+= 4;
351: }
352:
353: void cpu_op_11a(t_ipc *ipc) /* OR */ {
354: /* mask fff8, bits 0060, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
355: uint16 srcdata = ipc->src;
356: int dstreg = (ipc->opcode >> 0) & 7;
357: uint32 dstaddr = ADDRREG(dstreg)-=2;
358: uint16 dstdata = fetchword(dstaddr);
359: uint16 outdata = dstdata;
360:
361: outdata|= srcdata;
362: storeword(dstaddr, outdata);
363: PC+= 4;
364: }
365:
366: void cpu_op_11b(t_ipc *ipc) /* OR */ {
367: /* mask fff8, bits 0060, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
368: uint16 srcdata = ipc->src;
369: int dstreg = (ipc->opcode >> 0) & 7;
370: uint32 dstaddr = ADDRREG(dstreg)-=2;
371: uint16 dstdata = fetchword(dstaddr);
372: uint16 outdata = dstdata;
373:
374: outdata|= srcdata;
375: storeword(dstaddr, outdata);
376:
377: NFLAG = ((sint16)outdata) < 0;
378: ZFLAG = !outdata;
379: VFLAG = 0;
380: CFLAG = 0;
381: PC+= 4;
382: }
383:
384: void cpu_op_12a(t_ipc *ipc) /* OR */ {
385: /* mask fff8, bits 0068, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
386: uint16 srcdata = ipc->src;
387: int dstreg = (ipc->opcode >> 0) & 7;
388: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
389: uint16 dstdata = fetchword(dstaddr);
390: uint16 outdata = dstdata;
391:
392: outdata|= srcdata;
393: storeword(dstaddr, outdata);
394: PC+= 6;
395: }
396:
397: void cpu_op_12b(t_ipc *ipc) /* OR */ {
398: /* mask fff8, bits 0068, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
399: uint16 srcdata = ipc->src;
400: int dstreg = (ipc->opcode >> 0) & 7;
401: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
402: uint16 dstdata = fetchword(dstaddr);
403: uint16 outdata = dstdata;
404:
405: outdata|= srcdata;
406: storeword(dstaddr, outdata);
407:
408: NFLAG = ((sint16)outdata) < 0;
409: ZFLAG = !outdata;
410: VFLAG = 0;
411: CFLAG = 0;
412: PC+= 6;
413: }
414:
415: void cpu_op_13a(t_ipc *ipc) /* OR */ {
416: /* mask fff8, bits 0070, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
417: uint16 srcdata = ipc->src;
418: int dstreg = (ipc->opcode >> 0) & 7;
419: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
420: uint16 dstdata = fetchword(dstaddr);
421: uint16 outdata = dstdata;
422:
423: outdata|= srcdata;
424: storeword(dstaddr, outdata);
425: PC+= 6;
426: }
427:
428: void cpu_op_13b(t_ipc *ipc) /* OR */ {
429: /* mask fff8, bits 0070, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
430: uint16 srcdata = ipc->src;
431: int dstreg = (ipc->opcode >> 0) & 7;
432: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
433: uint16 dstdata = fetchword(dstaddr);
434: uint16 outdata = dstdata;
435:
436: outdata|= srcdata;
437: storeword(dstaddr, outdata);
438:
439: NFLAG = ((sint16)outdata) < 0;
440: ZFLAG = !outdata;
441: VFLAG = 0;
442: CFLAG = 0;
443: PC+= 6;
444: }
445:
446: void cpu_op_14a(t_ipc *ipc) /* OR */ {
447: /* mask ffff, bits 0078, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
448: uint16 srcdata = ipc->src;
449: uint32 dstaddr = ipc->dst;
450: uint16 dstdata = fetchword(dstaddr);
451: uint16 outdata = dstdata;
452:
453: outdata|= srcdata;
454: storeword(dstaddr, outdata);
455: PC+= 6;
456: }
457:
458: void cpu_op_14b(t_ipc *ipc) /* OR */ {
459: /* mask ffff, bits 0078, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
460: uint16 srcdata = ipc->src;
461: uint32 dstaddr = ipc->dst;
462: uint16 dstdata = fetchword(dstaddr);
463: uint16 outdata = dstdata;
464:
465: outdata|= srcdata;
466: storeword(dstaddr, outdata);
467:
468: NFLAG = ((sint16)outdata) < 0;
469: ZFLAG = !outdata;
470: VFLAG = 0;
471: CFLAG = 0;
472: PC+= 6;
473: }
474:
475: void cpu_op_15a(t_ipc *ipc) /* OR */ {
476: /* mask ffff, bits 0079, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
477: uint16 srcdata = ipc->src;
478: uint32 dstaddr = ipc->dst;
479: uint16 dstdata = fetchword(dstaddr);
480: uint16 outdata = dstdata;
481:
482: outdata|= srcdata;
483: storeword(dstaddr, outdata);
484: PC+= 8;
485: }
486:
487: void cpu_op_15b(t_ipc *ipc) /* OR */ {
488: /* mask ffff, bits 0079, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
489: uint16 srcdata = ipc->src;
490: uint32 dstaddr = ipc->dst;
491: uint16 dstdata = fetchword(dstaddr);
492: uint16 outdata = dstdata;
493:
494: outdata|= srcdata;
495: storeword(dstaddr, outdata);
496:
497: NFLAG = ((sint16)outdata) < 0;
498: ZFLAG = !outdata;
499: VFLAG = 0;
500: CFLAG = 0;
501: PC+= 8;
502: }
503:
504: void cpu_op_16a(t_ipc *ipc) /* OR */ {
505: /* mask fff8, bits 0080, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
506: uint32 srcdata = ipc->src;
507: int dstreg = (ipc->opcode >> 0) & 7;
508: uint32 dstdata = DATAREG(dstreg);
509: uint32 outdata = dstdata;
510:
511: outdata|= srcdata;
512: DATAREG(dstreg) = outdata;
513: PC+= 6;
514: }
515:
516: void cpu_op_16b(t_ipc *ipc) /* OR */ {
517: /* mask fff8, bits 0080, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
518: uint32 srcdata = ipc->src;
519: int dstreg = (ipc->opcode >> 0) & 7;
520: uint32 dstdata = DATAREG(dstreg);
521: uint32 outdata = dstdata;
522:
523: outdata|= srcdata;
524: DATAREG(dstreg) = outdata;
525:
526: NFLAG = ((sint32)outdata) < 0;
527: ZFLAG = !outdata;
528: VFLAG = 0;
529: CFLAG = 0;
530: PC+= 6;
531: }
532:
533: void cpu_op_17a(t_ipc *ipc) /* OR */ {
534: /* mask fff8, bits 0090, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
535: uint32 srcdata = ipc->src;
536: int dstreg = (ipc->opcode >> 0) & 7;
537: uint32 dstaddr = ADDRREG(dstreg);
538: uint32 dstdata = fetchlong(dstaddr);
539: uint32 outdata = dstdata;
540:
541: outdata|= srcdata;
542: storelong(dstaddr, outdata);
543: PC+= 6;
544: }
545:
546: void cpu_op_17b(t_ipc *ipc) /* OR */ {
547: /* mask fff8, bits 0090, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
548: uint32 srcdata = ipc->src;
549: int dstreg = (ipc->opcode >> 0) & 7;
550: uint32 dstaddr = ADDRREG(dstreg);
551: uint32 dstdata = fetchlong(dstaddr);
552: uint32 outdata = dstdata;
553:
554: outdata|= srcdata;
555: storelong(dstaddr, outdata);
556:
557: NFLAG = ((sint32)outdata) < 0;
558: ZFLAG = !outdata;
559: VFLAG = 0;
560: CFLAG = 0;
561: PC+= 6;
562: }
563:
564: void cpu_op_18a(t_ipc *ipc) /* OR */ {
565: /* mask fff8, bits 0098, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
566: uint32 srcdata = ipc->src;
567: int dstreg = (ipc->opcode >> 0) & 7;
568: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
569: uint32 dstdata = fetchlong(dstaddr);
570: uint32 outdata = dstdata;
571:
572: outdata|= srcdata;
573: storelong(dstaddr, outdata);
574: PC+= 6;
575: }
576:
577: void cpu_op_18b(t_ipc *ipc) /* OR */ {
578: /* mask fff8, bits 0098, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
579: uint32 srcdata = ipc->src;
580: int dstreg = (ipc->opcode >> 0) & 7;
581: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
582: uint32 dstdata = fetchlong(dstaddr);
583: uint32 outdata = dstdata;
584:
585: outdata|= srcdata;
586: storelong(dstaddr, outdata);
587:
588: NFLAG = ((sint32)outdata) < 0;
589: ZFLAG = !outdata;
590: VFLAG = 0;
591: CFLAG = 0;
592: PC+= 6;
593: }
594:
595: void cpu_op_19a(t_ipc *ipc) /* OR */ {
596: /* mask fff8, bits 00a0, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
597: uint32 srcdata = ipc->src;
598: int dstreg = (ipc->opcode >> 0) & 7;
599: uint32 dstaddr = ADDRREG(dstreg)-=4;
600: uint32 dstdata = fetchlong(dstaddr);
601: uint32 outdata = dstdata;
602:
603: outdata|= srcdata;
604: storelong(dstaddr, outdata);
605: PC+= 6;
606: }
607:
608: void cpu_op_19b(t_ipc *ipc) /* OR */ {
609: /* mask fff8, bits 00a0, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
610: uint32 srcdata = ipc->src;
611: int dstreg = (ipc->opcode >> 0) & 7;
612: uint32 dstaddr = ADDRREG(dstreg)-=4;
613: uint32 dstdata = fetchlong(dstaddr);
614: uint32 outdata = dstdata;
615:
616: outdata|= srcdata;
617: storelong(dstaddr, outdata);
618:
619: NFLAG = ((sint32)outdata) < 0;
620: ZFLAG = !outdata;
621: VFLAG = 0;
622: CFLAG = 0;
623: PC+= 6;
624: }
625:
626: void cpu_op_20a(t_ipc *ipc) /* OR */ {
627: /* mask fff8, bits 00a8, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
628: uint32 srcdata = ipc->src;
629: int dstreg = (ipc->opcode >> 0) & 7;
630: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
631: uint32 dstdata = fetchlong(dstaddr);
632: uint32 outdata = dstdata;
633:
634: outdata|= srcdata;
635: storelong(dstaddr, outdata);
636: PC+= 8;
637: }
638:
639: void cpu_op_20b(t_ipc *ipc) /* OR */ {
640: /* mask fff8, bits 00a8, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
641: uint32 srcdata = ipc->src;
642: int dstreg = (ipc->opcode >> 0) & 7;
643: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
644: uint32 dstdata = fetchlong(dstaddr);
645: uint32 outdata = dstdata;
646:
647: outdata|= srcdata;
648: storelong(dstaddr, outdata);
649:
650: NFLAG = ((sint32)outdata) < 0;
651: ZFLAG = !outdata;
652: VFLAG = 0;
653: CFLAG = 0;
654: PC+= 8;
655: }
656:
657: void cpu_op_21a(t_ipc *ipc) /* OR */ {
658: /* mask fff8, bits 00b0, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
659: uint32 srcdata = ipc->src;
660: int dstreg = (ipc->opcode >> 0) & 7;
661: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
662: uint32 dstdata = fetchlong(dstaddr);
663: uint32 outdata = dstdata;
664:
665: outdata|= srcdata;
666: storelong(dstaddr, outdata);
667: PC+= 8;
668: }
669:
670: void cpu_op_21b(t_ipc *ipc) /* OR */ {
671: /* mask fff8, bits 00b0, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
672: uint32 srcdata = ipc->src;
673: int dstreg = (ipc->opcode >> 0) & 7;
674: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
675: uint32 dstdata = fetchlong(dstaddr);
676: uint32 outdata = dstdata;
677:
678: outdata|= srcdata;
679: storelong(dstaddr, outdata);
680:
681: NFLAG = ((sint32)outdata) < 0;
682: ZFLAG = !outdata;
683: VFLAG = 0;
684: CFLAG = 0;
685: PC+= 8;
686: }
687:
688: void cpu_op_22a(t_ipc *ipc) /* OR */ {
689: /* mask ffff, bits 00b8, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
690: uint32 srcdata = ipc->src;
691: uint32 dstaddr = ipc->dst;
692: uint32 dstdata = fetchlong(dstaddr);
693: uint32 outdata = dstdata;
694:
695: outdata|= srcdata;
696: storelong(dstaddr, outdata);
697: PC+= 8;
698: }
699:
700: void cpu_op_22b(t_ipc *ipc) /* OR */ {
701: /* mask ffff, bits 00b8, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
702: uint32 srcdata = ipc->src;
703: uint32 dstaddr = ipc->dst;
704: uint32 dstdata = fetchlong(dstaddr);
705: uint32 outdata = dstdata;
706:
707: outdata|= srcdata;
708: storelong(dstaddr, outdata);
709:
710: NFLAG = ((sint32)outdata) < 0;
711: ZFLAG = !outdata;
712: VFLAG = 0;
713: CFLAG = 0;
714: PC+= 8;
715: }
716:
717: void cpu_op_23a(t_ipc *ipc) /* OR */ {
718: /* mask ffff, bits 00b9, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
719: uint32 srcdata = ipc->src;
720: uint32 dstaddr = ipc->dst;
721: uint32 dstdata = fetchlong(dstaddr);
722: uint32 outdata = dstdata;
723:
724: outdata|= srcdata;
725: storelong(dstaddr, outdata);
726: PC+= 10;
727: }
728:
729: void cpu_op_23b(t_ipc *ipc) /* OR */ {
730: /* mask ffff, bits 00b9, mnemonic 1, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
731: uint32 srcdata = ipc->src;
732: uint32 dstaddr = ipc->dst;
733: uint32 dstdata = fetchlong(dstaddr);
734: uint32 outdata = dstdata;
735:
736: outdata|= srcdata;
737: storelong(dstaddr, outdata);
738:
739: NFLAG = ((sint32)outdata) < 0;
740: ZFLAG = !outdata;
741: VFLAG = 0;
742: CFLAG = 0;
743: PC+= 10;
744: }
745:
746: void cpu_op_24a(t_ipc *ipc) /* ORSR */ {
747: /* mask ffff, bits 003c, mnemonic 2, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 11, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
748: uint8 srcdata = ipc->src;
749: unsigned int sr = reg68k_sr.sr_struct.s;
750:
751: SR|= srcdata;
752: if (sr != (uint8)reg68k_sr.sr_struct.s) {
753: /* mode change, swap SP and A7 */
754: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
755: }
756: PC+= 4;
757: }
758:
759: void cpu_op_25a(t_ipc *ipc) /* ORSR */ {
760: /* mask ffff, bits 007c, mnemonic 2, priv -1, endblk 0, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
761: uint16 srcdata = ipc->src;
762: unsigned int sr = reg68k_sr.sr_struct.s;
763:
764: if (!SFLAG)
765: reg68k_vector(V_PRIVILEGE, PC+4);
766:
767: SR|= srcdata;
768: if (sr != (uint8)reg68k_sr.sr_struct.s) {
769: /* mode change, swap SP and A7 */
770: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
771: }
772: PC+= 4;
773: }
774:
775: void cpu_op_26a(t_ipc *ipc) /* AND */ {
776: /* mask fff8, bits 0200, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
777: uint8 srcdata = ipc->src;
778: int dstreg = (ipc->opcode >> 0) & 7;
779: uint8 dstdata = DATAREG(dstreg);
780: uint8 outdata = dstdata;
781:
782: outdata&= srcdata;
783: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
784: PC+= 4;
785: }
786:
787: void cpu_op_26b(t_ipc *ipc) /* AND */ {
788: /* mask fff8, bits 0200, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
789: uint8 srcdata = ipc->src;
790: int dstreg = (ipc->opcode >> 0) & 7;
791: uint8 dstdata = DATAREG(dstreg);
792: uint8 outdata = dstdata;
793:
794: outdata&= srcdata;
795: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
796:
797: NFLAG = ((sint8)outdata) < 0;
798: ZFLAG = !outdata;
799: VFLAG = 0;
800: CFLAG = 0;
801: PC+= 4;
802: }
803:
804: void cpu_op_27a(t_ipc *ipc) /* AND */ {
805: /* mask fff8, bits 0210, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
806: uint8 srcdata = ipc->src;
807: int dstreg = (ipc->opcode >> 0) & 7;
808: uint32 dstaddr = ADDRREG(dstreg);
809: uint8 dstdata = fetchbyte(dstaddr);
810: uint8 outdata = dstdata;
811:
812: outdata&= srcdata;
813: storebyte(dstaddr, outdata);
814: PC+= 4;
815: }
816:
817: void cpu_op_27b(t_ipc *ipc) /* AND */ {
818: /* mask fff8, bits 0210, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
819: uint8 srcdata = ipc->src;
820: int dstreg = (ipc->opcode >> 0) & 7;
821: uint32 dstaddr = ADDRREG(dstreg);
822: uint8 dstdata = fetchbyte(dstaddr);
823: uint8 outdata = dstdata;
824:
825: outdata&= srcdata;
826: storebyte(dstaddr, outdata);
827:
828: NFLAG = ((sint8)outdata) < 0;
829: ZFLAG = !outdata;
830: VFLAG = 0;
831: CFLAG = 0;
832: PC+= 4;
833: }
834:
835: void cpu_op_28a(t_ipc *ipc) /* AND */ {
836: /* mask fff8, bits 0218, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
837: uint8 srcdata = ipc->src;
838: int dstreg = (ipc->opcode >> 0) & 7;
839: uint32 dstaddr = ADDRREG(dstreg);
840: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
841: uint8 dstdata = fetchbyte(dstaddr);
842: uint8 outdata = dstdata;
843:
844: outdata&= srcdata;
845: storebyte(dstaddr, outdata);
846: PC+= 4;
847: }
848:
849: void cpu_op_28b(t_ipc *ipc) /* AND */ {
850: /* mask fff8, bits 0218, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
851: uint8 srcdata = ipc->src;
852: int dstreg = (ipc->opcode >> 0) & 7;
853: uint32 dstaddr = ADDRREG(dstreg);
854: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
855: uint8 dstdata = fetchbyte(dstaddr);
856: uint8 outdata = dstdata;
857:
858: outdata&= srcdata;
859: storebyte(dstaddr, outdata);
860:
861: NFLAG = ((sint8)outdata) < 0;
862: ZFLAG = !outdata;
863: VFLAG = 0;
864: CFLAG = 0;
865: PC+= 4;
866: }
867:
868: void cpu_op_29a(t_ipc *ipc) /* AND */ {
869: /* mask fff8, bits 0220, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
870: uint8 srcdata = ipc->src;
871: int dstreg = (ipc->opcode >> 0) & 7;
872: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
873: uint8 dstdata = fetchbyte(dstaddr);
874: uint8 outdata = dstdata;
875:
876: outdata&= srcdata;
877: storebyte(dstaddr, outdata);
878: PC+= 4;
879: }
880:
881: void cpu_op_29b(t_ipc *ipc) /* AND */ {
882: /* mask fff8, bits 0220, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
883: uint8 srcdata = ipc->src;
884: int dstreg = (ipc->opcode >> 0) & 7;
885: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
886: uint8 dstdata = fetchbyte(dstaddr);
887: uint8 outdata = dstdata;
888:
889: outdata&= srcdata;
890: storebyte(dstaddr, outdata);
891:
892: NFLAG = ((sint8)outdata) < 0;
893: ZFLAG = !outdata;
894: VFLAG = 0;
895: CFLAG = 0;
896: PC+= 4;
897: }
898:
899: void cpu_op_30a(t_ipc *ipc) /* AND */ {
900: /* mask fff8, bits 0228, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
901: uint8 srcdata = ipc->src;
902: int dstreg = (ipc->opcode >> 0) & 7;
903: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
904: uint8 dstdata = fetchbyte(dstaddr);
905: uint8 outdata = dstdata;
906:
907: outdata&= srcdata;
908: storebyte(dstaddr, outdata);
909: PC+= 6;
910: }
911:
912: void cpu_op_30b(t_ipc *ipc) /* AND */ {
913: /* mask fff8, bits 0228, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
914: uint8 srcdata = ipc->src;
915: int dstreg = (ipc->opcode >> 0) & 7;
916: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
917: uint8 dstdata = fetchbyte(dstaddr);
918: uint8 outdata = dstdata;
919:
920: outdata&= srcdata;
921: storebyte(dstaddr, outdata);
922:
923: NFLAG = ((sint8)outdata) < 0;
924: ZFLAG = !outdata;
925: VFLAG = 0;
926: CFLAG = 0;
927: PC+= 6;
928: }
929:
930: void cpu_op_31a(t_ipc *ipc) /* AND */ {
931: /* mask fff8, bits 0230, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
932: uint8 srcdata = ipc->src;
933: int dstreg = (ipc->opcode >> 0) & 7;
934: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
935: uint8 dstdata = fetchbyte(dstaddr);
936: uint8 outdata = dstdata;
937:
938: outdata&= srcdata;
939: storebyte(dstaddr, outdata);
940: PC+= 6;
941: }
942:
943: void cpu_op_31b(t_ipc *ipc) /* AND */ {
944: /* mask fff8, bits 0230, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
945: uint8 srcdata = ipc->src;
946: int dstreg = (ipc->opcode >> 0) & 7;
947: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
948: uint8 dstdata = fetchbyte(dstaddr);
949: uint8 outdata = dstdata;
950:
951: outdata&= srcdata;
952: storebyte(dstaddr, outdata);
953:
954: NFLAG = ((sint8)outdata) < 0;
955: ZFLAG = !outdata;
956: VFLAG = 0;
957: CFLAG = 0;
958: PC+= 6;
959: }
960:
961: void cpu_op_32a(t_ipc *ipc) /* AND */ {
962: /* mask ffff, bits 0238, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
963: uint8 srcdata = ipc->src;
964: uint32 dstaddr = ipc->dst;
965: uint8 dstdata = fetchbyte(dstaddr);
966: uint8 outdata = dstdata;
967:
968: outdata&= srcdata;
969: storebyte(dstaddr, outdata);
970: PC+= 6;
971: }
972:
973: void cpu_op_32b(t_ipc *ipc) /* AND */ {
974: /* mask ffff, bits 0238, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
975: uint8 srcdata = ipc->src;
976: uint32 dstaddr = ipc->dst;
977: uint8 dstdata = fetchbyte(dstaddr);
978: uint8 outdata = dstdata;
979:
980: outdata&= srcdata;
981: storebyte(dstaddr, outdata);
982:
983: NFLAG = ((sint8)outdata) < 0;
984: ZFLAG = !outdata;
985: VFLAG = 0;
986: CFLAG = 0;
987: PC+= 6;
988: }
989:
990: void cpu_op_33a(t_ipc *ipc) /* AND */ {
991: /* mask ffff, bits 0239, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
992: uint8 srcdata = ipc->src;
993: uint32 dstaddr = ipc->dst;
994: uint8 dstdata = fetchbyte(dstaddr);
995: uint8 outdata = dstdata;
996:
997: outdata&= srcdata;
998: storebyte(dstaddr, outdata);
999: PC+= 8;
1000: }
1001:
1002: void cpu_op_33b(t_ipc *ipc) /* AND */ {
1003: /* mask ffff, bits 0239, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
1004: uint8 srcdata = ipc->src;
1005: uint32 dstaddr = ipc->dst;
1006: uint8 dstdata = fetchbyte(dstaddr);
1007: uint8 outdata = dstdata;
1008:
1009: outdata&= srcdata;
1010: storebyte(dstaddr, outdata);
1011:
1012: NFLAG = ((sint8)outdata) < 0;
1013: ZFLAG = !outdata;
1014: VFLAG = 0;
1015: CFLAG = 0;
1016: PC+= 8;
1017: }
1018:
1019: void cpu_op_34a(t_ipc *ipc) /* AND */ {
1020: /* mask fff8, bits 0240, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
1021: uint16 srcdata = ipc->src;
1022: int dstreg = (ipc->opcode >> 0) & 7;
1023: uint16 dstdata = DATAREG(dstreg);
1024: uint16 outdata = dstdata;
1025:
1026: outdata&= srcdata;
1027: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
1028: PC+= 4;
1029: }
1030:
1031: void cpu_op_34b(t_ipc *ipc) /* AND */ {
1032: /* mask fff8, bits 0240, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
1033: uint16 srcdata = ipc->src;
1034: int dstreg = (ipc->opcode >> 0) & 7;
1035: uint16 dstdata = DATAREG(dstreg);
1036: uint16 outdata = dstdata;
1037:
1038: outdata&= srcdata;
1039: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
1040:
1041: NFLAG = ((sint16)outdata) < 0;
1042: ZFLAG = !outdata;
1043: VFLAG = 0;
1044: CFLAG = 0;
1045: PC+= 4;
1046: }
1047:
1048: void cpu_op_35a(t_ipc *ipc) /* AND */ {
1049: /* mask fff8, bits 0250, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
1050: uint16 srcdata = ipc->src;
1051: int dstreg = (ipc->opcode >> 0) & 7;
1052: uint32 dstaddr = ADDRREG(dstreg);
1053: uint16 dstdata = fetchword(dstaddr);
1054: uint16 outdata = dstdata;
1055:
1056: outdata&= srcdata;
1057: storeword(dstaddr, outdata);
1058: PC+= 4;
1059: }
1060:
1061: void cpu_op_35b(t_ipc *ipc) /* AND */ {
1062: /* mask fff8, bits 0250, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
1063: uint16 srcdata = ipc->src;
1064: int dstreg = (ipc->opcode >> 0) & 7;
1065: uint32 dstaddr = ADDRREG(dstreg);
1066: uint16 dstdata = fetchword(dstaddr);
1067: uint16 outdata = dstdata;
1068:
1069: outdata&= srcdata;
1070: storeword(dstaddr, outdata);
1071:
1072: NFLAG = ((sint16)outdata) < 0;
1073: ZFLAG = !outdata;
1074: VFLAG = 0;
1075: CFLAG = 0;
1076: PC+= 4;
1077: }
1078:
1079: void cpu_op_36a(t_ipc *ipc) /* AND */ {
1080: /* mask fff8, bits 0258, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
1081: uint16 srcdata = ipc->src;
1082: int dstreg = (ipc->opcode >> 0) & 7;
1083: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
1084: uint16 dstdata = fetchword(dstaddr);
1085: uint16 outdata = dstdata;
1086:
1087: outdata&= srcdata;
1088: storeword(dstaddr, outdata);
1089: PC+= 4;
1090: }
1091:
1092: void cpu_op_36b(t_ipc *ipc) /* AND */ {
1093: /* mask fff8, bits 0258, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
1094: uint16 srcdata = ipc->src;
1095: int dstreg = (ipc->opcode >> 0) & 7;
1096: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
1097: uint16 dstdata = fetchword(dstaddr);
1098: uint16 outdata = dstdata;
1099:
1100: outdata&= srcdata;
1101: storeword(dstaddr, outdata);
1102:
1103: NFLAG = ((sint16)outdata) < 0;
1104: ZFLAG = !outdata;
1105: VFLAG = 0;
1106: CFLAG = 0;
1107: PC+= 4;
1108: }
1109:
1110: void cpu_op_37a(t_ipc *ipc) /* AND */ {
1111: /* mask fff8, bits 0260, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
1112: uint16 srcdata = ipc->src;
1113: int dstreg = (ipc->opcode >> 0) & 7;
1114: uint32 dstaddr = ADDRREG(dstreg)-=2;
1115: uint16 dstdata = fetchword(dstaddr);
1116: uint16 outdata = dstdata;
1117:
1118: outdata&= srcdata;
1119: storeword(dstaddr, outdata);
1120: PC+= 4;
1121: }
1122:
1123: void cpu_op_37b(t_ipc *ipc) /* AND */ {
1124: /* mask fff8, bits 0260, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
1125: uint16 srcdata = ipc->src;
1126: int dstreg = (ipc->opcode >> 0) & 7;
1127: uint32 dstaddr = ADDRREG(dstreg)-=2;
1128: uint16 dstdata = fetchword(dstaddr);
1129: uint16 outdata = dstdata;
1130:
1131: outdata&= srcdata;
1132: storeword(dstaddr, outdata);
1133:
1134: NFLAG = ((sint16)outdata) < 0;
1135: ZFLAG = !outdata;
1136: VFLAG = 0;
1137: CFLAG = 0;
1138: PC+= 4;
1139: }
1140:
1141: void cpu_op_38a(t_ipc *ipc) /* AND */ {
1142: /* mask fff8, bits 0268, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
1143: uint16 srcdata = ipc->src;
1144: int dstreg = (ipc->opcode >> 0) & 7;
1145: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1146: uint16 dstdata = fetchword(dstaddr);
1147: uint16 outdata = dstdata;
1148:
1149: outdata&= srcdata;
1150: storeword(dstaddr, outdata);
1151: PC+= 6;
1152: }
1153:
1154: void cpu_op_38b(t_ipc *ipc) /* AND */ {
1155: /* mask fff8, bits 0268, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
1156: uint16 srcdata = ipc->src;
1157: int dstreg = (ipc->opcode >> 0) & 7;
1158: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1159: uint16 dstdata = fetchword(dstaddr);
1160: uint16 outdata = dstdata;
1161:
1162: outdata&= srcdata;
1163: storeword(dstaddr, outdata);
1164:
1165: NFLAG = ((sint16)outdata) < 0;
1166: ZFLAG = !outdata;
1167: VFLAG = 0;
1168: CFLAG = 0;
1169: PC+= 6;
1170: }
1171:
1172: void cpu_op_39a(t_ipc *ipc) /* AND */ {
1173: /* mask fff8, bits 0270, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
1174: uint16 srcdata = ipc->src;
1175: int dstreg = (ipc->opcode >> 0) & 7;
1176: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1177: uint16 dstdata = fetchword(dstaddr);
1178: uint16 outdata = dstdata;
1179:
1180: outdata&= srcdata;
1181: storeword(dstaddr, outdata);
1182: PC+= 6;
1183: }
1184:
1185: void cpu_op_39b(t_ipc *ipc) /* AND */ {
1186: /* mask fff8, bits 0270, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
1187: uint16 srcdata = ipc->src;
1188: int dstreg = (ipc->opcode >> 0) & 7;
1189: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1190: uint16 dstdata = fetchword(dstaddr);
1191: uint16 outdata = dstdata;
1192:
1193: outdata&= srcdata;
1194: storeword(dstaddr, outdata);
1195:
1196: NFLAG = ((sint16)outdata) < 0;
1197: ZFLAG = !outdata;
1198: VFLAG = 0;
1199: CFLAG = 0;
1200: PC+= 6;
1201: }
1202:
1203: void cpu_op_40a(t_ipc *ipc) /* AND */ {
1204: /* mask ffff, bits 0278, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
1205: uint16 srcdata = ipc->src;
1206: uint32 dstaddr = ipc->dst;
1207: uint16 dstdata = fetchword(dstaddr);
1208: uint16 outdata = dstdata;
1209:
1210: outdata&= srcdata;
1211: storeword(dstaddr, outdata);
1212: PC+= 6;
1213: }
1214:
1215: void cpu_op_40b(t_ipc *ipc) /* AND */ {
1216: /* mask ffff, bits 0278, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
1217: uint16 srcdata = ipc->src;
1218: uint32 dstaddr = ipc->dst;
1219: uint16 dstdata = fetchword(dstaddr);
1220: uint16 outdata = dstdata;
1221:
1222: outdata&= srcdata;
1223: storeword(dstaddr, outdata);
1224:
1225: NFLAG = ((sint16)outdata) < 0;
1226: ZFLAG = !outdata;
1227: VFLAG = 0;
1228: CFLAG = 0;
1229: PC+= 6;
1230: }
1231:
1232: void cpu_op_41a(t_ipc *ipc) /* AND */ {
1233: /* mask ffff, bits 0279, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
1234: uint16 srcdata = ipc->src;
1235: uint32 dstaddr = ipc->dst;
1236: uint16 dstdata = fetchword(dstaddr);
1237: uint16 outdata = dstdata;
1238:
1239: outdata&= srcdata;
1240: storeword(dstaddr, outdata);
1241: PC+= 8;
1242: }
1243:
1244: void cpu_op_41b(t_ipc *ipc) /* AND */ {
1245: /* mask ffff, bits 0279, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
1246: uint16 srcdata = ipc->src;
1247: uint32 dstaddr = ipc->dst;
1248: uint16 dstdata = fetchword(dstaddr);
1249: uint16 outdata = dstdata;
1250:
1251: outdata&= srcdata;
1252: storeword(dstaddr, outdata);
1253:
1254: NFLAG = ((sint16)outdata) < 0;
1255: ZFLAG = !outdata;
1256: VFLAG = 0;
1257: CFLAG = 0;
1258: PC+= 8;
1259: }
1260:
1261: void cpu_op_42a(t_ipc *ipc) /* AND */ {
1262: /* mask fff8, bits 0280, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
1263: uint32 srcdata = ipc->src;
1264: int dstreg = (ipc->opcode >> 0) & 7;
1265: uint32 dstdata = DATAREG(dstreg);
1266: uint32 outdata = dstdata;
1267:
1268: outdata&= srcdata;
1269: DATAREG(dstreg) = outdata;
1270: PC+= 6;
1271: }
1272:
1273: void cpu_op_42b(t_ipc *ipc) /* AND */ {
1274: /* mask fff8, bits 0280, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
1275: uint32 srcdata = ipc->src;
1276: int dstreg = (ipc->opcode >> 0) & 7;
1277: uint32 dstdata = DATAREG(dstreg);
1278: uint32 outdata = dstdata;
1279:
1280: outdata&= srcdata;
1281: DATAREG(dstreg) = outdata;
1282:
1283: NFLAG = ((sint32)outdata) < 0;
1284: ZFLAG = !outdata;
1285: VFLAG = 0;
1286: CFLAG = 0;
1287: PC+= 6;
1288: }
1289:
1290: void cpu_op_43a(t_ipc *ipc) /* AND */ {
1291: /* mask fff8, bits 0290, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
1292: uint32 srcdata = ipc->src;
1293: int dstreg = (ipc->opcode >> 0) & 7;
1294: uint32 dstaddr = ADDRREG(dstreg);
1295: uint32 dstdata = fetchlong(dstaddr);
1296: uint32 outdata = dstdata;
1297:
1298: outdata&= srcdata;
1299: storelong(dstaddr, outdata);
1300: PC+= 6;
1301: }
1302:
1303: void cpu_op_43b(t_ipc *ipc) /* AND */ {
1304: /* mask fff8, bits 0290, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
1305: uint32 srcdata = ipc->src;
1306: int dstreg = (ipc->opcode >> 0) & 7;
1307: uint32 dstaddr = ADDRREG(dstreg);
1308: uint32 dstdata = fetchlong(dstaddr);
1309: uint32 outdata = dstdata;
1310:
1311: outdata&= srcdata;
1312: storelong(dstaddr, outdata);
1313:
1314: NFLAG = ((sint32)outdata) < 0;
1315: ZFLAG = !outdata;
1316: VFLAG = 0;
1317: CFLAG = 0;
1318: PC+= 6;
1319: }
1320:
1321: void cpu_op_44a(t_ipc *ipc) /* AND */ {
1322: /* mask fff8, bits 0298, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
1323: uint32 srcdata = ipc->src;
1324: int dstreg = (ipc->opcode >> 0) & 7;
1325: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
1326: uint32 dstdata = fetchlong(dstaddr);
1327: uint32 outdata = dstdata;
1328:
1329: outdata&= srcdata;
1330: storelong(dstaddr, outdata);
1331: PC+= 6;
1332: }
1333:
1334: void cpu_op_44b(t_ipc *ipc) /* AND */ {
1335: /* mask fff8, bits 0298, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
1336: uint32 srcdata = ipc->src;
1337: int dstreg = (ipc->opcode >> 0) & 7;
1338: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
1339: uint32 dstdata = fetchlong(dstaddr);
1340: uint32 outdata = dstdata;
1341:
1342: outdata&= srcdata;
1343: storelong(dstaddr, outdata);
1344:
1345: NFLAG = ((sint32)outdata) < 0;
1346: ZFLAG = !outdata;
1347: VFLAG = 0;
1348: CFLAG = 0;
1349: PC+= 6;
1350: }
1351:
1352: void cpu_op_45a(t_ipc *ipc) /* AND */ {
1353: /* mask fff8, bits 02a0, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
1354: uint32 srcdata = ipc->src;
1355: int dstreg = (ipc->opcode >> 0) & 7;
1356: uint32 dstaddr = ADDRREG(dstreg)-=4;
1357: uint32 dstdata = fetchlong(dstaddr);
1358: uint32 outdata = dstdata;
1359:
1360: outdata&= srcdata;
1361: storelong(dstaddr, outdata);
1362: PC+= 6;
1363: }
1364:
1365: void cpu_op_45b(t_ipc *ipc) /* AND */ {
1366: /* mask fff8, bits 02a0, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
1367: uint32 srcdata = ipc->src;
1368: int dstreg = (ipc->opcode >> 0) & 7;
1369: uint32 dstaddr = ADDRREG(dstreg)-=4;
1370: uint32 dstdata = fetchlong(dstaddr);
1371: uint32 outdata = dstdata;
1372:
1373: outdata&= srcdata;
1374: storelong(dstaddr, outdata);
1375:
1376: NFLAG = ((sint32)outdata) < 0;
1377: ZFLAG = !outdata;
1378: VFLAG = 0;
1379: CFLAG = 0;
1380: PC+= 6;
1381: }
1382:
1383: void cpu_op_46a(t_ipc *ipc) /* AND */ {
1384: /* mask fff8, bits 02a8, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
1385: uint32 srcdata = ipc->src;
1386: int dstreg = (ipc->opcode >> 0) & 7;
1387: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1388: uint32 dstdata = fetchlong(dstaddr);
1389: uint32 outdata = dstdata;
1390:
1391: outdata&= srcdata;
1392: storelong(dstaddr, outdata);
1393: PC+= 8;
1394: }
1395:
1396: void cpu_op_46b(t_ipc *ipc) /* AND */ {
1397: /* mask fff8, bits 02a8, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
1398: uint32 srcdata = ipc->src;
1399: int dstreg = (ipc->opcode >> 0) & 7;
1400: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1401: uint32 dstdata = fetchlong(dstaddr);
1402: uint32 outdata = dstdata;
1403:
1404: outdata&= srcdata;
1405: storelong(dstaddr, outdata);
1406:
1407: NFLAG = ((sint32)outdata) < 0;
1408: ZFLAG = !outdata;
1409: VFLAG = 0;
1410: CFLAG = 0;
1411: PC+= 8;
1412: }
1413:
1414: void cpu_op_47a(t_ipc *ipc) /* AND */ {
1415: /* mask fff8, bits 02b0, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
1416: uint32 srcdata = ipc->src;
1417: int dstreg = (ipc->opcode >> 0) & 7;
1418: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1419: uint32 dstdata = fetchlong(dstaddr);
1420: uint32 outdata = dstdata;
1421:
1422: outdata&= srcdata;
1423: storelong(dstaddr, outdata);
1424: PC+= 8;
1425: }
1426:
1427: void cpu_op_47b(t_ipc *ipc) /* AND */ {
1428: /* mask fff8, bits 02b0, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
1429: uint32 srcdata = ipc->src;
1430: int dstreg = (ipc->opcode >> 0) & 7;
1431: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1432: uint32 dstdata = fetchlong(dstaddr);
1433: uint32 outdata = dstdata;
1434:
1435: outdata&= srcdata;
1436: storelong(dstaddr, outdata);
1437:
1438: NFLAG = ((sint32)outdata) < 0;
1439: ZFLAG = !outdata;
1440: VFLAG = 0;
1441: CFLAG = 0;
1442: PC+= 8;
1443: }
1444:
1445: void cpu_op_48a(t_ipc *ipc) /* AND */ {
1446: /* mask ffff, bits 02b8, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
1447: uint32 srcdata = ipc->src;
1448: uint32 dstaddr = ipc->dst;
1449: uint32 dstdata = fetchlong(dstaddr);
1450: uint32 outdata = dstdata;
1451:
1452: outdata&= srcdata;
1453: storelong(dstaddr, outdata);
1454: PC+= 8;
1455: }
1456:
1457: void cpu_op_48b(t_ipc *ipc) /* AND */ {
1458: /* mask ffff, bits 02b8, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
1459: uint32 srcdata = ipc->src;
1460: uint32 dstaddr = ipc->dst;
1461: uint32 dstdata = fetchlong(dstaddr);
1462: uint32 outdata = dstdata;
1463:
1464: outdata&= srcdata;
1465: storelong(dstaddr, outdata);
1466:
1467: NFLAG = ((sint32)outdata) < 0;
1468: ZFLAG = !outdata;
1469: VFLAG = 0;
1470: CFLAG = 0;
1471: PC+= 8;
1472: }
1473:
1474: void cpu_op_49a(t_ipc *ipc) /* AND */ {
1475: /* mask ffff, bits 02b9, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
1476: uint32 srcdata = ipc->src;
1477: uint32 dstaddr = ipc->dst;
1478: uint32 dstdata = fetchlong(dstaddr);
1479: uint32 outdata = dstdata;
1480:
1481: outdata&= srcdata;
1482: storelong(dstaddr, outdata);
1483: PC+= 10;
1484: }
1485:
1486: void cpu_op_49b(t_ipc *ipc) /* AND */ {
1487: /* mask ffff, bits 02b9, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
1488: uint32 srcdata = ipc->src;
1489: uint32 dstaddr = ipc->dst;
1490: uint32 dstdata = fetchlong(dstaddr);
1491: uint32 outdata = dstdata;
1492:
1493: outdata&= srcdata;
1494: storelong(dstaddr, outdata);
1495:
1496: NFLAG = ((sint32)outdata) < 0;
1497: ZFLAG = !outdata;
1498: VFLAG = 0;
1499: CFLAG = 0;
1500: PC+= 10;
1501: }
1502:
1503: void cpu_op_50a(t_ipc *ipc) /* ANDSR */ {
1504: /* mask ffff, bits 023c, mnemonic 4, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 11, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1505: uint8 srcdata = ipc->src;
1506: unsigned int sr = reg68k_sr.sr_struct.s;
1507:
1508: SR = (SR & 0xFF00) | (SR & srcdata);
1509: if (sr != (uint8)reg68k_sr.sr_struct.s) {
1510: /* mode change, swap SP and A7 */
1511: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
1512: }
1513: PC+= 4;
1514: }
1515:
1516: void cpu_op_51a(t_ipc *ipc) /* ANDSR */ {
1517: /* mask ffff, bits 027c, mnemonic 4, priv -1, endblk 0, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1518: uint16 srcdata = ipc->src;
1519: unsigned int sr = reg68k_sr.sr_struct.s;
1520:
1521: if (!SFLAG)
1522: reg68k_vector(V_PRIVILEGE, PC+4);
1523:
1524: SR&= srcdata;
1525: if (sr != (uint8)reg68k_sr.sr_struct.s) {
1526: /* mode change, swap SP and A7 */
1527: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
1528: }
1529: PC+= 4;
1530: }
1531:
1532: void cpu_op_52a(t_ipc *ipc) /* SUB */ {
1533: /* mask fff8, bits 0400, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
1534: uint8 srcdata = ipc->src;
1535: int dstreg = (ipc->opcode >> 0) & 7;
1536: uint8 dstdata = DATAREG(dstreg);
1537: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1538:
1539: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
1540: PC+= 4;
1541: }
1542:
1543: void cpu_op_52b(t_ipc *ipc) /* SUB */ {
1544: /* mask fff8, bits 0400, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
1545: uint8 srcdata = ipc->src;
1546: int dstreg = (ipc->opcode >> 0) & 7;
1547: uint8 dstdata = DATAREG(dstreg);
1548: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1549:
1550: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
1551:
1552: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
1553: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1554: XFLAG = CFLAG = srcdata > dstdata;
1555: NFLAG = ((sint8)outdata) < 0;
1556: ZFLAG = !outdata;
1557: PC+= 4;
1558: }
1559:
1560: void cpu_op_53a(t_ipc *ipc) /* SUB */ {
1561: /* mask fff8, bits 0410, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
1562: uint8 srcdata = ipc->src;
1563: int dstreg = (ipc->opcode >> 0) & 7;
1564: uint32 dstaddr = ADDRREG(dstreg);
1565: uint8 dstdata = fetchbyte(dstaddr);
1566: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1567:
1568: storebyte(dstaddr, outdata);
1569: PC+= 4;
1570: }
1571:
1572: void cpu_op_53b(t_ipc *ipc) /* SUB */ {
1573: /* mask fff8, bits 0410, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
1574: uint8 srcdata = ipc->src;
1575: int dstreg = (ipc->opcode >> 0) & 7;
1576: uint32 dstaddr = ADDRREG(dstreg);
1577: uint8 dstdata = fetchbyte(dstaddr);
1578: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1579:
1580: storebyte(dstaddr, outdata);
1581:
1582: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
1583: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1584: XFLAG = CFLAG = srcdata > dstdata;
1585: NFLAG = ((sint8)outdata) < 0;
1586: ZFLAG = !outdata;
1587: PC+= 4;
1588: }
1589:
1590: void cpu_op_54a(t_ipc *ipc) /* SUB */ {
1591: /* mask fff8, bits 0418, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
1592: uint8 srcdata = ipc->src;
1593: int dstreg = (ipc->opcode >> 0) & 7;
1594: uint32 dstaddr = ADDRREG(dstreg);
1595: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
1596: uint8 dstdata = fetchbyte(dstaddr);
1597: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1598:
1599: storebyte(dstaddr, outdata);
1600: PC+= 4;
1601: }
1602:
1603: void cpu_op_54b(t_ipc *ipc) /* SUB */ {
1604: /* mask fff8, bits 0418, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
1605: uint8 srcdata = ipc->src;
1606: int dstreg = (ipc->opcode >> 0) & 7;
1607: uint32 dstaddr = ADDRREG(dstreg);
1608: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
1609: uint8 dstdata = fetchbyte(dstaddr);
1610: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1611:
1612: storebyte(dstaddr, outdata);
1613:
1614: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
1615: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1616: XFLAG = CFLAG = srcdata > dstdata;
1617: NFLAG = ((sint8)outdata) < 0;
1618: ZFLAG = !outdata;
1619: PC+= 4;
1620: }
1621:
1622: void cpu_op_55a(t_ipc *ipc) /* SUB */ {
1623: /* mask fff8, bits 0420, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
1624: uint8 srcdata = ipc->src;
1625: int dstreg = (ipc->opcode >> 0) & 7;
1626: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
1627: uint8 dstdata = fetchbyte(dstaddr);
1628: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1629:
1630: storebyte(dstaddr, outdata);
1631: PC+= 4;
1632: }
1633:
1634: void cpu_op_55b(t_ipc *ipc) /* SUB */ {
1635: /* mask fff8, bits 0420, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
1636: uint8 srcdata = ipc->src;
1637: int dstreg = (ipc->opcode >> 0) & 7;
1638: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
1639: uint8 dstdata = fetchbyte(dstaddr);
1640: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1641:
1642: storebyte(dstaddr, outdata);
1643:
1644: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
1645: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1646: XFLAG = CFLAG = srcdata > dstdata;
1647: NFLAG = ((sint8)outdata) < 0;
1648: ZFLAG = !outdata;
1649: PC+= 4;
1650: }
1651:
1652: void cpu_op_56a(t_ipc *ipc) /* SUB */ {
1653: /* mask fff8, bits 0428, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
1654: uint8 srcdata = ipc->src;
1655: int dstreg = (ipc->opcode >> 0) & 7;
1656: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1657: uint8 dstdata = fetchbyte(dstaddr);
1658: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1659:
1660: storebyte(dstaddr, outdata);
1661: PC+= 6;
1662: }
1663:
1664: void cpu_op_56b(t_ipc *ipc) /* SUB */ {
1665: /* mask fff8, bits 0428, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
1666: uint8 srcdata = ipc->src;
1667: int dstreg = (ipc->opcode >> 0) & 7;
1668: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1669: uint8 dstdata = fetchbyte(dstaddr);
1670: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1671:
1672: storebyte(dstaddr, outdata);
1673:
1674: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
1675: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1676: XFLAG = CFLAG = srcdata > dstdata;
1677: NFLAG = ((sint8)outdata) < 0;
1678: ZFLAG = !outdata;
1679: PC+= 6;
1680: }
1681:
1682: void cpu_op_57a(t_ipc *ipc) /* SUB */ {
1683: /* mask fff8, bits 0430, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
1684: uint8 srcdata = ipc->src;
1685: int dstreg = (ipc->opcode >> 0) & 7;
1686: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1687: uint8 dstdata = fetchbyte(dstaddr);
1688: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1689:
1690: storebyte(dstaddr, outdata);
1691: PC+= 6;
1692: }
1693:
1694: void cpu_op_57b(t_ipc *ipc) /* SUB */ {
1695: /* mask fff8, bits 0430, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
1696: uint8 srcdata = ipc->src;
1697: int dstreg = (ipc->opcode >> 0) & 7;
1698: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1699: uint8 dstdata = fetchbyte(dstaddr);
1700: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1701:
1702: storebyte(dstaddr, outdata);
1703:
1704: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
1705: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1706: XFLAG = CFLAG = srcdata > dstdata;
1707: NFLAG = ((sint8)outdata) < 0;
1708: ZFLAG = !outdata;
1709: PC+= 6;
1710: }
1711:
1712: void cpu_op_58a(t_ipc *ipc) /* SUB */ {
1713: /* mask ffff, bits 0438, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
1714: uint8 srcdata = ipc->src;
1715: uint32 dstaddr = ipc->dst;
1716: uint8 dstdata = fetchbyte(dstaddr);
1717: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1718:
1719: storebyte(dstaddr, outdata);
1720: PC+= 6;
1721: }
1722:
1723: void cpu_op_58b(t_ipc *ipc) /* SUB */ {
1724: /* mask ffff, bits 0438, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
1725: uint8 srcdata = ipc->src;
1726: uint32 dstaddr = ipc->dst;
1727: uint8 dstdata = fetchbyte(dstaddr);
1728: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1729:
1730: storebyte(dstaddr, outdata);
1731:
1732: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
1733: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1734: XFLAG = CFLAG = srcdata > dstdata;
1735: NFLAG = ((sint8)outdata) < 0;
1736: ZFLAG = !outdata;
1737: PC+= 6;
1738: }
1739:
1740: void cpu_op_59a(t_ipc *ipc) /* SUB */ {
1741: /* mask ffff, bits 0439, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
1742: uint8 srcdata = ipc->src;
1743: uint32 dstaddr = ipc->dst;
1744: uint8 dstdata = fetchbyte(dstaddr);
1745: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1746:
1747: storebyte(dstaddr, outdata);
1748: PC+= 8;
1749: }
1750:
1751: void cpu_op_59b(t_ipc *ipc) /* SUB */ {
1752: /* mask ffff, bits 0439, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
1753: uint8 srcdata = ipc->src;
1754: uint32 dstaddr = ipc->dst;
1755: uint8 dstdata = fetchbyte(dstaddr);
1756: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
1757:
1758: storebyte(dstaddr, outdata);
1759:
1760: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
1761: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1762: XFLAG = CFLAG = srcdata > dstdata;
1763: NFLAG = ((sint8)outdata) < 0;
1764: ZFLAG = !outdata;
1765: PC+= 8;
1766: }
1767:
1768: void cpu_op_60a(t_ipc *ipc) /* SUB */ {
1769: /* mask fff8, bits 0440, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
1770: uint16 srcdata = ipc->src;
1771: int dstreg = (ipc->opcode >> 0) & 7;
1772: uint16 dstdata = DATAREG(dstreg);
1773: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1774:
1775: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
1776: PC+= 4;
1777: }
1778:
1779: void cpu_op_60b(t_ipc *ipc) /* SUB */ {
1780: /* mask fff8, bits 0440, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
1781: uint16 srcdata = ipc->src;
1782: int dstreg = (ipc->opcode >> 0) & 7;
1783: uint16 dstdata = DATAREG(dstreg);
1784: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1785:
1786: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
1787:
1788: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1789: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1790: XFLAG = CFLAG = srcdata > dstdata;
1791: NFLAG = ((sint16)outdata) < 0;
1792: ZFLAG = !outdata;
1793: PC+= 4;
1794: }
1795:
1796: void cpu_op_61a(t_ipc *ipc) /* SUB */ {
1797: /* mask fff8, bits 0450, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
1798: uint16 srcdata = ipc->src;
1799: int dstreg = (ipc->opcode >> 0) & 7;
1800: uint32 dstaddr = ADDRREG(dstreg);
1801: uint16 dstdata = fetchword(dstaddr);
1802: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1803:
1804: storeword(dstaddr, outdata);
1805: PC+= 4;
1806: }
1807:
1808: void cpu_op_61b(t_ipc *ipc) /* SUB */ {
1809: /* mask fff8, bits 0450, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
1810: uint16 srcdata = ipc->src;
1811: int dstreg = (ipc->opcode >> 0) & 7;
1812: uint32 dstaddr = ADDRREG(dstreg);
1813: uint16 dstdata = fetchword(dstaddr);
1814: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1815:
1816: storeword(dstaddr, outdata);
1817:
1818: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1819: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1820: XFLAG = CFLAG = srcdata > dstdata;
1821: NFLAG = ((sint16)outdata) < 0;
1822: ZFLAG = !outdata;
1823: PC+= 4;
1824: }
1825:
1826: void cpu_op_62a(t_ipc *ipc) /* SUB */ {
1827: /* mask fff8, bits 0458, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
1828: uint16 srcdata = ipc->src;
1829: int dstreg = (ipc->opcode >> 0) & 7;
1830: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
1831: uint16 dstdata = fetchword(dstaddr);
1832: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1833:
1834: storeword(dstaddr, outdata);
1835: PC+= 4;
1836: }
1837:
1838: void cpu_op_62b(t_ipc *ipc) /* SUB */ {
1839: /* mask fff8, bits 0458, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
1840: uint16 srcdata = ipc->src;
1841: int dstreg = (ipc->opcode >> 0) & 7;
1842: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
1843: uint16 dstdata = fetchword(dstaddr);
1844: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1845:
1846: storeword(dstaddr, outdata);
1847:
1848: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1849: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1850: XFLAG = CFLAG = srcdata > dstdata;
1851: NFLAG = ((sint16)outdata) < 0;
1852: ZFLAG = !outdata;
1853: PC+= 4;
1854: }
1855:
1856: void cpu_op_63a(t_ipc *ipc) /* SUB */ {
1857: /* mask fff8, bits 0460, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
1858: uint16 srcdata = ipc->src;
1859: int dstreg = (ipc->opcode >> 0) & 7;
1860: uint32 dstaddr = ADDRREG(dstreg)-=2;
1861: uint16 dstdata = fetchword(dstaddr);
1862: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1863:
1864: storeword(dstaddr, outdata);
1865: PC+= 4;
1866: }
1867:
1868: void cpu_op_63b(t_ipc *ipc) /* SUB */ {
1869: /* mask fff8, bits 0460, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
1870: uint16 srcdata = ipc->src;
1871: int dstreg = (ipc->opcode >> 0) & 7;
1872: uint32 dstaddr = ADDRREG(dstreg)-=2;
1873: uint16 dstdata = fetchword(dstaddr);
1874: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1875:
1876: storeword(dstaddr, outdata);
1877:
1878: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1879: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1880: XFLAG = CFLAG = srcdata > dstdata;
1881: NFLAG = ((sint16)outdata) < 0;
1882: ZFLAG = !outdata;
1883: PC+= 4;
1884: }
1885:
1886: void cpu_op_64a(t_ipc *ipc) /* SUB */ {
1887: /* mask fff8, bits 0468, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
1888: uint16 srcdata = ipc->src;
1889: int dstreg = (ipc->opcode >> 0) & 7;
1890: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1891: uint16 dstdata = fetchword(dstaddr);
1892: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1893:
1894: storeword(dstaddr, outdata);
1895: PC+= 6;
1896: }
1897:
1898: void cpu_op_64b(t_ipc *ipc) /* SUB */ {
1899: /* mask fff8, bits 0468, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
1900: uint16 srcdata = ipc->src;
1901: int dstreg = (ipc->opcode >> 0) & 7;
1902: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1903: uint16 dstdata = fetchword(dstaddr);
1904: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1905:
1906: storeword(dstaddr, outdata);
1907:
1908: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1909: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1910: XFLAG = CFLAG = srcdata > dstdata;
1911: NFLAG = ((sint16)outdata) < 0;
1912: ZFLAG = !outdata;
1913: PC+= 6;
1914: }
1915:
1916: void cpu_op_65a(t_ipc *ipc) /* SUB */ {
1917: /* mask fff8, bits 0470, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
1918: uint16 srcdata = ipc->src;
1919: int dstreg = (ipc->opcode >> 0) & 7;
1920: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1921: uint16 dstdata = fetchword(dstaddr);
1922: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1923:
1924: storeword(dstaddr, outdata);
1925: PC+= 6;
1926: }
1927:
1928: void cpu_op_65b(t_ipc *ipc) /* SUB */ {
1929: /* mask fff8, bits 0470, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
1930: uint16 srcdata = ipc->src;
1931: int dstreg = (ipc->opcode >> 0) & 7;
1932: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1933: uint16 dstdata = fetchword(dstaddr);
1934: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1935:
1936: storeword(dstaddr, outdata);
1937:
1938: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1939: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1940: XFLAG = CFLAG = srcdata > dstdata;
1941: NFLAG = ((sint16)outdata) < 0;
1942: ZFLAG = !outdata;
1943: PC+= 6;
1944: }
1945:
1946: void cpu_op_66a(t_ipc *ipc) /* SUB */ {
1947: /* mask ffff, bits 0478, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
1948: uint16 srcdata = ipc->src;
1949: uint32 dstaddr = ipc->dst;
1950: uint16 dstdata = fetchword(dstaddr);
1951: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1952:
1953: storeword(dstaddr, outdata);
1954: PC+= 6;
1955: }
1956:
1957: void cpu_op_66b(t_ipc *ipc) /* SUB */ {
1958: /* mask ffff, bits 0478, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
1959: uint16 srcdata = ipc->src;
1960: uint32 dstaddr = ipc->dst;
1961: uint16 dstdata = fetchword(dstaddr);
1962: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1963:
1964: storeword(dstaddr, outdata);
1965:
1966: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1967: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1968: XFLAG = CFLAG = srcdata > dstdata;
1969: NFLAG = ((sint16)outdata) < 0;
1970: ZFLAG = !outdata;
1971: PC+= 6;
1972: }
1973:
1974: void cpu_op_67a(t_ipc *ipc) /* SUB */ {
1975: /* mask ffff, bits 0479, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
1976: uint16 srcdata = ipc->src;
1977: uint32 dstaddr = ipc->dst;
1978: uint16 dstdata = fetchword(dstaddr);
1979: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1980:
1981: storeword(dstaddr, outdata);
1982: PC+= 8;
1983: }
1984:
1985: void cpu_op_67b(t_ipc *ipc) /* SUB */ {
1986: /* mask ffff, bits 0479, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
1987: uint16 srcdata = ipc->src;
1988: uint32 dstaddr = ipc->dst;
1989: uint16 dstdata = fetchword(dstaddr);
1990: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1991:
1992: storeword(dstaddr, outdata);
1993:
1994: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1995: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1996: XFLAG = CFLAG = srcdata > dstdata;
1997: NFLAG = ((sint16)outdata) < 0;
1998: ZFLAG = !outdata;
1999: PC+= 8;
2000: }
2001:
2002: void cpu_op_68a(t_ipc *ipc) /* SUB */ {
2003: /* mask fff8, bits 0480, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
2004: uint32 srcdata = ipc->src;
2005: int dstreg = (ipc->opcode >> 0) & 7;
2006: uint32 dstdata = DATAREG(dstreg);
2007: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2008:
2009: DATAREG(dstreg) = outdata;
2010: PC+= 6;
2011: }
2012:
2013: void cpu_op_68b(t_ipc *ipc) /* SUB */ {
2014: /* mask fff8, bits 0480, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
2015: uint32 srcdata = ipc->src;
2016: int dstreg = (ipc->opcode >> 0) & 7;
2017: uint32 dstdata = DATAREG(dstreg);
2018: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2019:
2020: DATAREG(dstreg) = outdata;
2021:
2022: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2023: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2024: XFLAG = CFLAG = srcdata > dstdata;
2025: NFLAG = ((sint32)outdata) < 0;
2026: ZFLAG = !outdata;
2027: PC+= 6;
2028: }
2029:
2030: void cpu_op_69a(t_ipc *ipc) /* SUB */ {
2031: /* mask fff8, bits 0490, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
2032: uint32 srcdata = ipc->src;
2033: int dstreg = (ipc->opcode >> 0) & 7;
2034: uint32 dstaddr = ADDRREG(dstreg);
2035: uint32 dstdata = fetchlong(dstaddr);
2036: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2037:
2038: storelong(dstaddr, outdata);
2039: PC+= 6;
2040: }
2041:
2042: void cpu_op_69b(t_ipc *ipc) /* SUB */ {
2043: /* mask fff8, bits 0490, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
2044: uint32 srcdata = ipc->src;
2045: int dstreg = (ipc->opcode >> 0) & 7;
2046: uint32 dstaddr = ADDRREG(dstreg);
2047: uint32 dstdata = fetchlong(dstaddr);
2048: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2049:
2050: storelong(dstaddr, outdata);
2051:
2052: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2053: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2054: XFLAG = CFLAG = srcdata > dstdata;
2055: NFLAG = ((sint32)outdata) < 0;
2056: ZFLAG = !outdata;
2057: PC+= 6;
2058: }
2059:
2060: void cpu_op_70a(t_ipc *ipc) /* SUB */ {
2061: /* mask fff8, bits 0498, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
2062: uint32 srcdata = ipc->src;
2063: int dstreg = (ipc->opcode >> 0) & 7;
2064: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
2065: uint32 dstdata = fetchlong(dstaddr);
2066: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2067:
2068: storelong(dstaddr, outdata);
2069: PC+= 6;
2070: }
2071:
2072: void cpu_op_70b(t_ipc *ipc) /* SUB */ {
2073: /* mask fff8, bits 0498, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
2074: uint32 srcdata = ipc->src;
2075: int dstreg = (ipc->opcode >> 0) & 7;
2076: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
2077: uint32 dstdata = fetchlong(dstaddr);
2078: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2079:
2080: storelong(dstaddr, outdata);
2081:
2082: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2083: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2084: XFLAG = CFLAG = srcdata > dstdata;
2085: NFLAG = ((sint32)outdata) < 0;
2086: ZFLAG = !outdata;
2087: PC+= 6;
2088: }
2089:
2090: void cpu_op_71a(t_ipc *ipc) /* SUB */ {
2091: /* mask fff8, bits 04a0, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
2092: uint32 srcdata = ipc->src;
2093: int dstreg = (ipc->opcode >> 0) & 7;
2094: uint32 dstaddr = ADDRREG(dstreg)-=4;
2095: uint32 dstdata = fetchlong(dstaddr);
2096: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2097:
2098: storelong(dstaddr, outdata);
2099: PC+= 6;
2100: }
2101:
2102: void cpu_op_71b(t_ipc *ipc) /* SUB */ {
2103: /* mask fff8, bits 04a0, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
2104: uint32 srcdata = ipc->src;
2105: int dstreg = (ipc->opcode >> 0) & 7;
2106: uint32 dstaddr = ADDRREG(dstreg)-=4;
2107: uint32 dstdata = fetchlong(dstaddr);
2108: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2109:
2110: storelong(dstaddr, outdata);
2111:
2112: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2113: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2114: XFLAG = CFLAG = srcdata > dstdata;
2115: NFLAG = ((sint32)outdata) < 0;
2116: ZFLAG = !outdata;
2117: PC+= 6;
2118: }
2119:
2120: void cpu_op_72a(t_ipc *ipc) /* SUB */ {
2121: /* mask fff8, bits 04a8, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
2122: uint32 srcdata = ipc->src;
2123: int dstreg = (ipc->opcode >> 0) & 7;
2124: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2125: uint32 dstdata = fetchlong(dstaddr);
2126: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2127:
2128: storelong(dstaddr, outdata);
2129: PC+= 8;
2130: }
2131:
2132: void cpu_op_72b(t_ipc *ipc) /* SUB */ {
2133: /* mask fff8, bits 04a8, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
2134: uint32 srcdata = ipc->src;
2135: int dstreg = (ipc->opcode >> 0) & 7;
2136: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2137: uint32 dstdata = fetchlong(dstaddr);
2138: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2139:
2140: storelong(dstaddr, outdata);
2141:
2142: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2143: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2144: XFLAG = CFLAG = srcdata > dstdata;
2145: NFLAG = ((sint32)outdata) < 0;
2146: ZFLAG = !outdata;
2147: PC+= 8;
2148: }
2149:
2150: void cpu_op_73a(t_ipc *ipc) /* SUB */ {
2151: /* mask fff8, bits 04b0, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
2152: uint32 srcdata = ipc->src;
2153: int dstreg = (ipc->opcode >> 0) & 7;
2154: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2155: uint32 dstdata = fetchlong(dstaddr);
2156: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2157:
2158: storelong(dstaddr, outdata);
2159: PC+= 8;
2160: }
2161:
2162: void cpu_op_73b(t_ipc *ipc) /* SUB */ {
2163: /* mask fff8, bits 04b0, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
2164: uint32 srcdata = ipc->src;
2165: int dstreg = (ipc->opcode >> 0) & 7;
2166: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2167: uint32 dstdata = fetchlong(dstaddr);
2168: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2169:
2170: storelong(dstaddr, outdata);
2171:
2172: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2173: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2174: XFLAG = CFLAG = srcdata > dstdata;
2175: NFLAG = ((sint32)outdata) < 0;
2176: ZFLAG = !outdata;
2177: PC+= 8;
2178: }
2179:
2180: void cpu_op_74a(t_ipc *ipc) /* SUB */ {
2181: /* mask ffff, bits 04b8, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
2182: uint32 srcdata = ipc->src;
2183: uint32 dstaddr = ipc->dst;
2184: uint32 dstdata = fetchlong(dstaddr);
2185: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2186:
2187: storelong(dstaddr, outdata);
2188: PC+= 8;
2189: }
2190:
2191: void cpu_op_74b(t_ipc *ipc) /* SUB */ {
2192: /* mask ffff, bits 04b8, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
2193: uint32 srcdata = ipc->src;
2194: uint32 dstaddr = ipc->dst;
2195: uint32 dstdata = fetchlong(dstaddr);
2196: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2197:
2198: storelong(dstaddr, outdata);
2199:
2200: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2201: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2202: XFLAG = CFLAG = srcdata > dstdata;
2203: NFLAG = ((sint32)outdata) < 0;
2204: ZFLAG = !outdata;
2205: PC+= 8;
2206: }
2207:
2208: void cpu_op_75a(t_ipc *ipc) /* SUB */ {
2209: /* mask ffff, bits 04b9, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
2210: uint32 srcdata = ipc->src;
2211: uint32 dstaddr = ipc->dst;
2212: uint32 dstdata = fetchlong(dstaddr);
2213: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2214:
2215: storelong(dstaddr, outdata);
2216: PC+= 10;
2217: }
2218:
2219: void cpu_op_75b(t_ipc *ipc) /* SUB */ {
2220: /* mask ffff, bits 04b9, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
2221: uint32 srcdata = ipc->src;
2222: uint32 dstaddr = ipc->dst;
2223: uint32 dstdata = fetchlong(dstaddr);
2224: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2225:
2226: storelong(dstaddr, outdata);
2227:
2228: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2229: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2230: XFLAG = CFLAG = srcdata > dstdata;
2231: NFLAG = ((sint32)outdata) < 0;
2232: ZFLAG = !outdata;
2233: PC+= 10;
2234: }
2235:
2236: void cpu_op_76a(t_ipc *ipc) /* ADD */ {
2237: /* mask fff8, bits 0600, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
2238: uint8 srcdata = ipc->src;
2239: int dstreg = (ipc->opcode >> 0) & 7;
2240: uint8 dstdata = DATAREG(dstreg);
2241: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2242:
2243: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
2244: PC+= 4;
2245: }
2246:
2247: void cpu_op_76b(t_ipc *ipc) /* ADD */ {
2248: /* mask fff8, bits 0600, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
2249: uint8 srcdata = ipc->src;
2250: int dstreg = (ipc->opcode >> 0) & 7;
2251: uint8 dstdata = DATAREG(dstreg);
2252: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2253:
2254: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
2255:
2256: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
2257: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2258: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
2259: NFLAG = ((sint8)outdata) < 0;
2260: ZFLAG = !outdata;
2261: PC+= 4;
2262: }
2263:
2264: void cpu_op_77a(t_ipc *ipc) /* ADD */ {
2265: /* mask fff8, bits 0610, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
2266: uint8 srcdata = ipc->src;
2267: int dstreg = (ipc->opcode >> 0) & 7;
2268: uint32 dstaddr = ADDRREG(dstreg);
2269: uint8 dstdata = fetchbyte(dstaddr);
2270: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2271:
2272: storebyte(dstaddr, outdata);
2273: PC+= 4;
2274: }
2275:
2276: void cpu_op_77b(t_ipc *ipc) /* ADD */ {
2277: /* mask fff8, bits 0610, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
2278: uint8 srcdata = ipc->src;
2279: int dstreg = (ipc->opcode >> 0) & 7;
2280: uint32 dstaddr = ADDRREG(dstreg);
2281: uint8 dstdata = fetchbyte(dstaddr);
2282: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2283:
2284: storebyte(dstaddr, outdata);
2285:
2286: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
2287: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2288: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
2289: NFLAG = ((sint8)outdata) < 0;
2290: ZFLAG = !outdata;
2291: PC+= 4;
2292: }
2293:
2294: void cpu_op_78a(t_ipc *ipc) /* ADD */ {
2295: /* mask fff8, bits 0618, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
2296: uint8 srcdata = ipc->src;
2297: int dstreg = (ipc->opcode >> 0) & 7;
2298: uint32 dstaddr = ADDRREG(dstreg);
2299: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2300: uint8 dstdata = fetchbyte(dstaddr);
2301: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2302:
2303: storebyte(dstaddr, outdata);
2304: PC+= 4;
2305: }
2306:
2307: void cpu_op_78b(t_ipc *ipc) /* ADD */ {
2308: /* mask fff8, bits 0618, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
2309: uint8 srcdata = ipc->src;
2310: int dstreg = (ipc->opcode >> 0) & 7;
2311: uint32 dstaddr = ADDRREG(dstreg);
2312: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2313: uint8 dstdata = fetchbyte(dstaddr);
2314: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2315:
2316: storebyte(dstaddr, outdata);
2317:
2318: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
2319: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2320: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
2321: NFLAG = ((sint8)outdata) < 0;
2322: ZFLAG = !outdata;
2323: PC+= 4;
2324: }
2325:
2326: void cpu_op_79a(t_ipc *ipc) /* ADD */ {
2327: /* mask fff8, bits 0620, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
2328: uint8 srcdata = ipc->src;
2329: int dstreg = (ipc->opcode >> 0) & 7;
2330: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2331: uint8 dstdata = fetchbyte(dstaddr);
2332: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2333:
2334: storebyte(dstaddr, outdata);
2335: PC+= 4;
2336: }
2337:
2338: void cpu_op_79b(t_ipc *ipc) /* ADD */ {
2339: /* mask fff8, bits 0620, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
2340: uint8 srcdata = ipc->src;
2341: int dstreg = (ipc->opcode >> 0) & 7;
2342: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2343: uint8 dstdata = fetchbyte(dstaddr);
2344: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2345:
2346: storebyte(dstaddr, outdata);
2347:
2348: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
2349: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2350: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
2351: NFLAG = ((sint8)outdata) < 0;
2352: ZFLAG = !outdata;
2353: PC+= 4;
2354: }
2355:
2356: void cpu_op_80a(t_ipc *ipc) /* ADD */ {
2357: /* mask fff8, bits 0628, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
2358: uint8 srcdata = ipc->src;
2359: int dstreg = (ipc->opcode >> 0) & 7;
2360: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2361: uint8 dstdata = fetchbyte(dstaddr);
2362: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2363:
2364: storebyte(dstaddr, outdata);
2365: PC+= 6;
2366: }
2367:
2368: void cpu_op_80b(t_ipc *ipc) /* ADD */ {
2369: /* mask fff8, bits 0628, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
2370: uint8 srcdata = ipc->src;
2371: int dstreg = (ipc->opcode >> 0) & 7;
2372: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2373: uint8 dstdata = fetchbyte(dstaddr);
2374: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2375:
2376: storebyte(dstaddr, outdata);
2377:
2378: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
2379: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2380: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
2381: NFLAG = ((sint8)outdata) < 0;
2382: ZFLAG = !outdata;
2383: PC+= 6;
2384: }
2385:
2386: void cpu_op_81a(t_ipc *ipc) /* ADD */ {
2387: /* mask fff8, bits 0630, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
2388: uint8 srcdata = ipc->src;
2389: int dstreg = (ipc->opcode >> 0) & 7;
2390: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2391: uint8 dstdata = fetchbyte(dstaddr);
2392: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2393:
2394: storebyte(dstaddr, outdata);
2395: PC+= 6;
2396: }
2397:
2398: void cpu_op_81b(t_ipc *ipc) /* ADD */ {
2399: /* mask fff8, bits 0630, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
2400: uint8 srcdata = ipc->src;
2401: int dstreg = (ipc->opcode >> 0) & 7;
2402: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2403: uint8 dstdata = fetchbyte(dstaddr);
2404: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2405:
2406: storebyte(dstaddr, outdata);
2407:
2408: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
2409: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2410: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
2411: NFLAG = ((sint8)outdata) < 0;
2412: ZFLAG = !outdata;
2413: PC+= 6;
2414: }
2415:
2416: void cpu_op_82a(t_ipc *ipc) /* ADD */ {
2417: /* mask ffff, bits 0638, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
2418: uint8 srcdata = ipc->src;
2419: uint32 dstaddr = ipc->dst;
2420: uint8 dstdata = fetchbyte(dstaddr);
2421: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2422:
2423: storebyte(dstaddr, outdata);
2424: PC+= 6;
2425: }
2426:
2427: void cpu_op_82b(t_ipc *ipc) /* ADD */ {
2428: /* mask ffff, bits 0638, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
2429: uint8 srcdata = ipc->src;
2430: uint32 dstaddr = ipc->dst;
2431: uint8 dstdata = fetchbyte(dstaddr);
2432: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2433:
2434: storebyte(dstaddr, outdata);
2435:
2436: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
2437: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2438: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
2439: NFLAG = ((sint8)outdata) < 0;
2440: ZFLAG = !outdata;
2441: PC+= 6;
2442: }
2443:
2444: void cpu_op_83a(t_ipc *ipc) /* ADD */ {
2445: /* mask ffff, bits 0639, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
2446: uint8 srcdata = ipc->src;
2447: uint32 dstaddr = ipc->dst;
2448: uint8 dstdata = fetchbyte(dstaddr);
2449: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2450:
2451: storebyte(dstaddr, outdata);
2452: PC+= 8;
2453: }
2454:
2455: void cpu_op_83b(t_ipc *ipc) /* ADD */ {
2456: /* mask ffff, bits 0639, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
2457: uint8 srcdata = ipc->src;
2458: uint32 dstaddr = ipc->dst;
2459: uint8 dstdata = fetchbyte(dstaddr);
2460: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
2461:
2462: storebyte(dstaddr, outdata);
2463:
2464: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
2465: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2466: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
2467: NFLAG = ((sint8)outdata) < 0;
2468: ZFLAG = !outdata;
2469: PC+= 8;
2470: }
2471:
2472: void cpu_op_84a(t_ipc *ipc) /* ADD */ {
2473: /* mask fff8, bits 0640, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
2474: uint16 srcdata = ipc->src;
2475: int dstreg = (ipc->opcode >> 0) & 7;
2476: uint16 dstdata = DATAREG(dstreg);
2477: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2478:
2479: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
2480: PC+= 4;
2481: }
2482:
2483: void cpu_op_84b(t_ipc *ipc) /* ADD */ {
2484: /* mask fff8, bits 0640, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
2485: uint16 srcdata = ipc->src;
2486: int dstreg = (ipc->opcode >> 0) & 7;
2487: uint16 dstdata = DATAREG(dstreg);
2488: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2489:
2490: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
2491:
2492: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
2493: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2494: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
2495: NFLAG = ((sint16)outdata) < 0;
2496: ZFLAG = !outdata;
2497: PC+= 4;
2498: }
2499:
2500: void cpu_op_85a(t_ipc *ipc) /* ADD */ {
2501: /* mask fff8, bits 0650, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
2502: uint16 srcdata = ipc->src;
2503: int dstreg = (ipc->opcode >> 0) & 7;
2504: uint32 dstaddr = ADDRREG(dstreg);
2505: uint16 dstdata = fetchword(dstaddr);
2506: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2507:
2508: storeword(dstaddr, outdata);
2509: PC+= 4;
2510: }
2511:
2512: void cpu_op_85b(t_ipc *ipc) /* ADD */ {
2513: /* mask fff8, bits 0650, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
2514: uint16 srcdata = ipc->src;
2515: int dstreg = (ipc->opcode >> 0) & 7;
2516: uint32 dstaddr = ADDRREG(dstreg);
2517: uint16 dstdata = fetchword(dstaddr);
2518: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2519:
2520: storeword(dstaddr, outdata);
2521:
2522: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
2523: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2524: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
2525: NFLAG = ((sint16)outdata) < 0;
2526: ZFLAG = !outdata;
2527: PC+= 4;
2528: }
2529:
2530: void cpu_op_86a(t_ipc *ipc) /* ADD */ {
2531: /* mask fff8, bits 0658, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
2532: uint16 srcdata = ipc->src;
2533: int dstreg = (ipc->opcode >> 0) & 7;
2534: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
2535: uint16 dstdata = fetchword(dstaddr);
2536: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2537:
2538: storeword(dstaddr, outdata);
2539: PC+= 4;
2540: }
2541:
2542: void cpu_op_86b(t_ipc *ipc) /* ADD */ {
2543: /* mask fff8, bits 0658, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
2544: uint16 srcdata = ipc->src;
2545: int dstreg = (ipc->opcode >> 0) & 7;
2546: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
2547: uint16 dstdata = fetchword(dstaddr);
2548: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2549:
2550: storeword(dstaddr, outdata);
2551:
2552: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
2553: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2554: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
2555: NFLAG = ((sint16)outdata) < 0;
2556: ZFLAG = !outdata;
2557: PC+= 4;
2558: }
2559:
2560: void cpu_op_87a(t_ipc *ipc) /* ADD */ {
2561: /* mask fff8, bits 0660, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
2562: uint16 srcdata = ipc->src;
2563: int dstreg = (ipc->opcode >> 0) & 7;
2564: uint32 dstaddr = ADDRREG(dstreg)-=2;
2565: uint16 dstdata = fetchword(dstaddr);
2566: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2567:
2568: storeword(dstaddr, outdata);
2569: PC+= 4;
2570: }
2571:
2572: void cpu_op_87b(t_ipc *ipc) /* ADD */ {
2573: /* mask fff8, bits 0660, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
2574: uint16 srcdata = ipc->src;
2575: int dstreg = (ipc->opcode >> 0) & 7;
2576: uint32 dstaddr = ADDRREG(dstreg)-=2;
2577: uint16 dstdata = fetchword(dstaddr);
2578: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2579:
2580: storeword(dstaddr, outdata);
2581:
2582: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
2583: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2584: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
2585: NFLAG = ((sint16)outdata) < 0;
2586: ZFLAG = !outdata;
2587: PC+= 4;
2588: }
2589:
2590: void cpu_op_88a(t_ipc *ipc) /* ADD */ {
2591: /* mask fff8, bits 0668, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
2592: uint16 srcdata = ipc->src;
2593: int dstreg = (ipc->opcode >> 0) & 7;
2594: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2595: uint16 dstdata = fetchword(dstaddr);
2596: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2597:
2598: storeword(dstaddr, outdata);
2599: PC+= 6;
2600: }
2601:
2602: void cpu_op_88b(t_ipc *ipc) /* ADD */ {
2603: /* mask fff8, bits 0668, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
2604: uint16 srcdata = ipc->src;
2605: int dstreg = (ipc->opcode >> 0) & 7;
2606: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2607: uint16 dstdata = fetchword(dstaddr);
2608: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2609:
2610: storeword(dstaddr, outdata);
2611:
2612: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
2613: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2614: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
2615: NFLAG = ((sint16)outdata) < 0;
2616: ZFLAG = !outdata;
2617: PC+= 6;
2618: }
2619:
2620: void cpu_op_89a(t_ipc *ipc) /* ADD */ {
2621: /* mask fff8, bits 0670, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
2622: uint16 srcdata = ipc->src;
2623: int dstreg = (ipc->opcode >> 0) & 7;
2624: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2625: uint16 dstdata = fetchword(dstaddr);
2626: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2627:
2628: storeword(dstaddr, outdata);
2629: PC+= 6;
2630: }
2631:
2632: void cpu_op_89b(t_ipc *ipc) /* ADD */ {
2633: /* mask fff8, bits 0670, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
2634: uint16 srcdata = ipc->src;
2635: int dstreg = (ipc->opcode >> 0) & 7;
2636: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2637: uint16 dstdata = fetchword(dstaddr);
2638: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2639:
2640: storeword(dstaddr, outdata);
2641:
2642: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
2643: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2644: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
2645: NFLAG = ((sint16)outdata) < 0;
2646: ZFLAG = !outdata;
2647: PC+= 6;
2648: }
2649:
2650: void cpu_op_90a(t_ipc *ipc) /* ADD */ {
2651: /* mask ffff, bits 0678, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
2652: uint16 srcdata = ipc->src;
2653: uint32 dstaddr = ipc->dst;
2654: uint16 dstdata = fetchword(dstaddr);
2655: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2656:
2657: storeword(dstaddr, outdata);
2658: PC+= 6;
2659: }
2660:
2661: void cpu_op_90b(t_ipc *ipc) /* ADD */ {
2662: /* mask ffff, bits 0678, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
2663: uint16 srcdata = ipc->src;
2664: uint32 dstaddr = ipc->dst;
2665: uint16 dstdata = fetchword(dstaddr);
2666: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2667:
2668: storeword(dstaddr, outdata);
2669:
2670: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
2671: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2672: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
2673: NFLAG = ((sint16)outdata) < 0;
2674: ZFLAG = !outdata;
2675: PC+= 6;
2676: }
2677:
2678: void cpu_op_91a(t_ipc *ipc) /* ADD */ {
2679: /* mask ffff, bits 0679, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
2680: uint16 srcdata = ipc->src;
2681: uint32 dstaddr = ipc->dst;
2682: uint16 dstdata = fetchword(dstaddr);
2683: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2684:
2685: storeword(dstaddr, outdata);
2686: PC+= 8;
2687: }
2688:
2689: void cpu_op_91b(t_ipc *ipc) /* ADD */ {
2690: /* mask ffff, bits 0679, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
2691: uint16 srcdata = ipc->src;
2692: uint32 dstaddr = ipc->dst;
2693: uint16 dstdata = fetchword(dstaddr);
2694: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
2695:
2696: storeword(dstaddr, outdata);
2697:
2698: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
2699: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2700: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
2701: NFLAG = ((sint16)outdata) < 0;
2702: ZFLAG = !outdata;
2703: PC+= 8;
2704: }
2705:
2706: void cpu_op_92a(t_ipc *ipc) /* ADD */ {
2707: /* mask fff8, bits 0680, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
2708: uint32 srcdata = ipc->src;
2709: int dstreg = (ipc->opcode >> 0) & 7;
2710: uint32 dstdata = DATAREG(dstreg);
2711: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2712:
2713: DATAREG(dstreg) = outdata;
2714: PC+= 6;
2715: }
2716:
2717: void cpu_op_92b(t_ipc *ipc) /* ADD */ {
2718: /* mask fff8, bits 0680, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
2719: uint32 srcdata = ipc->src;
2720: int dstreg = (ipc->opcode >> 0) & 7;
2721: uint32 dstdata = DATAREG(dstreg);
2722: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2723:
2724: DATAREG(dstreg) = outdata;
2725:
2726: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2727: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2728: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2729: NFLAG = ((sint32)outdata) < 0;
2730: ZFLAG = !outdata;
2731: PC+= 6;
2732: }
2733:
2734: void cpu_op_93a(t_ipc *ipc) /* ADD */ {
2735: /* mask fff8, bits 0690, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
2736: uint32 srcdata = ipc->src;
2737: int dstreg = (ipc->opcode >> 0) & 7;
2738: uint32 dstaddr = ADDRREG(dstreg);
2739: uint32 dstdata = fetchlong(dstaddr);
2740: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2741:
2742: storelong(dstaddr, outdata);
2743: PC+= 6;
2744: }
2745:
2746: void cpu_op_93b(t_ipc *ipc) /* ADD */ {
2747: /* mask fff8, bits 0690, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
2748: uint32 srcdata = ipc->src;
2749: int dstreg = (ipc->opcode >> 0) & 7;
2750: uint32 dstaddr = ADDRREG(dstreg);
2751: uint32 dstdata = fetchlong(dstaddr);
2752: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2753:
2754: storelong(dstaddr, outdata);
2755:
2756: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2757: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2758: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2759: NFLAG = ((sint32)outdata) < 0;
2760: ZFLAG = !outdata;
2761: PC+= 6;
2762: }
2763:
2764: void cpu_op_94a(t_ipc *ipc) /* ADD */ {
2765: /* mask fff8, bits 0698, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
2766: uint32 srcdata = ipc->src;
2767: int dstreg = (ipc->opcode >> 0) & 7;
2768: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
2769: uint32 dstdata = fetchlong(dstaddr);
2770: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2771:
2772: storelong(dstaddr, outdata);
2773: PC+= 6;
2774: }
2775:
2776: void cpu_op_94b(t_ipc *ipc) /* ADD */ {
2777: /* mask fff8, bits 0698, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
2778: uint32 srcdata = ipc->src;
2779: int dstreg = (ipc->opcode >> 0) & 7;
2780: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
2781: uint32 dstdata = fetchlong(dstaddr);
2782: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2783:
2784: storelong(dstaddr, outdata);
2785:
2786: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2787: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2788: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2789: NFLAG = ((sint32)outdata) < 0;
2790: ZFLAG = !outdata;
2791: PC+= 6;
2792: }
2793:
2794: void cpu_op_95a(t_ipc *ipc) /* ADD */ {
2795: /* mask fff8, bits 06a0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
2796: uint32 srcdata = ipc->src;
2797: int dstreg = (ipc->opcode >> 0) & 7;
2798: uint32 dstaddr = ADDRREG(dstreg)-=4;
2799: uint32 dstdata = fetchlong(dstaddr);
2800: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2801:
2802: storelong(dstaddr, outdata);
2803: PC+= 6;
2804: }
2805:
2806: void cpu_op_95b(t_ipc *ipc) /* ADD */ {
2807: /* mask fff8, bits 06a0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
2808: uint32 srcdata = ipc->src;
2809: int dstreg = (ipc->opcode >> 0) & 7;
2810: uint32 dstaddr = ADDRREG(dstreg)-=4;
2811: uint32 dstdata = fetchlong(dstaddr);
2812: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2813:
2814: storelong(dstaddr, outdata);
2815:
2816: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2817: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2818: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2819: NFLAG = ((sint32)outdata) < 0;
2820: ZFLAG = !outdata;
2821: PC+= 6;
2822: }
2823:
2824: void cpu_op_96a(t_ipc *ipc) /* ADD */ {
2825: /* mask fff8, bits 06a8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
2826: uint32 srcdata = ipc->src;
2827: int dstreg = (ipc->opcode >> 0) & 7;
2828: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2829: uint32 dstdata = fetchlong(dstaddr);
2830: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2831:
2832: storelong(dstaddr, outdata);
2833: PC+= 8;
2834: }
2835:
2836: void cpu_op_96b(t_ipc *ipc) /* ADD */ {
2837: /* mask fff8, bits 06a8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
2838: uint32 srcdata = ipc->src;
2839: int dstreg = (ipc->opcode >> 0) & 7;
2840: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2841: uint32 dstdata = fetchlong(dstaddr);
2842: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2843:
2844: storelong(dstaddr, outdata);
2845:
2846: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2847: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2848: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2849: NFLAG = ((sint32)outdata) < 0;
2850: ZFLAG = !outdata;
2851: PC+= 8;
2852: }
2853:
2854: void cpu_op_97a(t_ipc *ipc) /* ADD */ {
2855: /* mask fff8, bits 06b0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
2856: uint32 srcdata = ipc->src;
2857: int dstreg = (ipc->opcode >> 0) & 7;
2858: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2859: uint32 dstdata = fetchlong(dstaddr);
2860: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2861:
2862: storelong(dstaddr, outdata);
2863: PC+= 8;
2864: }
2865:
2866: void cpu_op_97b(t_ipc *ipc) /* ADD */ {
2867: /* mask fff8, bits 06b0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
2868: uint32 srcdata = ipc->src;
2869: int dstreg = (ipc->opcode >> 0) & 7;
2870: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2871: uint32 dstdata = fetchlong(dstaddr);
2872: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2873:
2874: storelong(dstaddr, outdata);
2875:
2876: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2877: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2878: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2879: NFLAG = ((sint32)outdata) < 0;
2880: ZFLAG = !outdata;
2881: PC+= 8;
2882: }
2883:
2884: void cpu_op_98a(t_ipc *ipc) /* ADD */ {
2885: /* mask ffff, bits 06b8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
2886: uint32 srcdata = ipc->src;
2887: uint32 dstaddr = ipc->dst;
2888: uint32 dstdata = fetchlong(dstaddr);
2889: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2890:
2891: storelong(dstaddr, outdata);
2892: PC+= 8;
2893: }
2894:
2895: void cpu_op_98b(t_ipc *ipc) /* ADD */ {
2896: /* mask ffff, bits 06b8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
2897: uint32 srcdata = ipc->src;
2898: uint32 dstaddr = ipc->dst;
2899: uint32 dstdata = fetchlong(dstaddr);
2900: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2901:
2902: storelong(dstaddr, outdata);
2903:
2904: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2905: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2906: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2907: NFLAG = ((sint32)outdata) < 0;
2908: ZFLAG = !outdata;
2909: PC+= 8;
2910: }
2911:
2912: void cpu_op_99a(t_ipc *ipc) /* ADD */ {
2913: /* mask ffff, bits 06b9, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
2914: uint32 srcdata = ipc->src;
2915: uint32 dstaddr = ipc->dst;
2916: uint32 dstdata = fetchlong(dstaddr);
2917: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2918:
2919: storelong(dstaddr, outdata);
2920: PC+= 10;
2921: }
2922:
2923: void cpu_op_99b(t_ipc *ipc) /* ADD */ {
2924: /* mask ffff, bits 06b9, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
2925: uint32 srcdata = ipc->src;
2926: uint32 dstaddr = ipc->dst;
2927: uint32 dstdata = fetchlong(dstaddr);
2928: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2929:
2930: storelong(dstaddr, outdata);
2931:
2932: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2933: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2934: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2935: NFLAG = ((sint32)outdata) < 0;
2936: ZFLAG = !outdata;
2937: PC+= 10;
2938: }
2939:
2940: void cpu_op_100a(t_ipc *ipc) /* BTST */ {
2941: /* mask fff8, bits 0810, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
2942: uint8 srcdata = ipc->src;
2943: int dstreg = (ipc->opcode >> 0) & 7;
2944: uint32 dstaddr = ADDRREG(dstreg);
2945: uint8 dstdata = fetchbyte(dstaddr);
2946: uint32 bitpos = 1<<(srcdata & 7);
2947:
2948: ZFLAG = !(dstdata & bitpos);
2949: PC+= 4;
2950: }
2951:
2952: void cpu_op_100b(t_ipc *ipc) /* BTST */ {
2953: /* mask fff8, bits 0810, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
2954: uint8 srcdata = ipc->src;
2955: int dstreg = (ipc->opcode >> 0) & 7;
2956: uint32 dstaddr = ADDRREG(dstreg);
2957: uint8 dstdata = fetchbyte(dstaddr);
2958: uint32 bitpos = 1<<(srcdata & 7);
2959:
2960: ZFLAG = !(dstdata & bitpos);
2961: PC+= 4;
2962: }
2963:
2964: void cpu_op_101a(t_ipc *ipc) /* BTST */ {
2965: /* mask fff8, bits 0818, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
2966: uint8 srcdata = ipc->src;
2967: int dstreg = (ipc->opcode >> 0) & 7;
2968: uint32 dstaddr = ADDRREG(dstreg);
2969: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2970: uint8 dstdata = fetchbyte(dstaddr);
2971: uint32 bitpos = 1<<(srcdata & 7);
2972:
2973: ZFLAG = !(dstdata & bitpos);
2974: PC+= 4;
2975: }
2976:
2977: void cpu_op_101b(t_ipc *ipc) /* BTST */ {
2978: /* mask fff8, bits 0818, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
2979: uint8 srcdata = ipc->src;
2980: int dstreg = (ipc->opcode >> 0) & 7;
2981: uint32 dstaddr = ADDRREG(dstreg);
2982: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2983: uint8 dstdata = fetchbyte(dstaddr);
2984: uint32 bitpos = 1<<(srcdata & 7);
2985:
2986: ZFLAG = !(dstdata & bitpos);
2987: PC+= 4;
2988: }
2989:
2990: void cpu_op_102a(t_ipc *ipc) /* BTST */ {
2991: /* mask fff8, bits 0820, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
2992: uint8 srcdata = ipc->src;
2993: int dstreg = (ipc->opcode >> 0) & 7;
2994: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2995: uint8 dstdata = fetchbyte(dstaddr);
2996: uint32 bitpos = 1<<(srcdata & 7);
2997:
2998: ZFLAG = !(dstdata & bitpos);
2999: PC+= 4;
3000: }
3001:
3002: void cpu_op_102b(t_ipc *ipc) /* BTST */ {
3003: /* mask fff8, bits 0820, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
3004: uint8 srcdata = ipc->src;
3005: int dstreg = (ipc->opcode >> 0) & 7;
3006: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
3007: uint8 dstdata = fetchbyte(dstaddr);
3008: uint32 bitpos = 1<<(srcdata & 7);
3009:
3010: ZFLAG = !(dstdata & bitpos);
3011: PC+= 4;
3012: }
3013:
3014: void cpu_op_103a(t_ipc *ipc) /* BTST */ {
3015: /* mask fff8, bits 0828, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
3016: uint8 srcdata = ipc->src;
3017: int dstreg = (ipc->opcode >> 0) & 7;
3018: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
3019: uint8 dstdata = fetchbyte(dstaddr);
3020: uint32 bitpos = 1<<(srcdata & 7);
3021:
3022: ZFLAG = !(dstdata & bitpos);
3023: PC+= 6;
3024: }
3025:
3026: void cpu_op_103b(t_ipc *ipc) /* BTST */ {
3027: /* mask fff8, bits 0828, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
3028: uint8 srcdata = ipc->src;
3029: int dstreg = (ipc->opcode >> 0) & 7;
3030: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
3031: uint8 dstdata = fetchbyte(dstaddr);
3032: uint32 bitpos = 1<<(srcdata & 7);
3033:
3034: ZFLAG = !(dstdata & bitpos);
3035: PC+= 6;
3036: }
3037:
3038: void cpu_op_104a(t_ipc *ipc) /* BTST */ {
3039: /* mask fff8, bits 0830, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
3040: uint8 srcdata = ipc->src;
3041: int dstreg = (ipc->opcode >> 0) & 7;
3042: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
3043: uint8 dstdata = fetchbyte(dstaddr);
3044: uint32 bitpos = 1<<(srcdata & 7);
3045:
3046: ZFLAG = !(dstdata & bitpos);
3047: PC+= 6;
3048: }
3049:
3050: void cpu_op_104b(t_ipc *ipc) /* BTST */ {
3051: /* mask fff8, bits 0830, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
3052: uint8 srcdata = ipc->src;
3053: int dstreg = (ipc->opcode >> 0) & 7;
3054: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
3055: uint8 dstdata = fetchbyte(dstaddr);
3056: uint32 bitpos = 1<<(srcdata & 7);
3057:
3058: ZFLAG = !(dstdata & bitpos);
3059: PC+= 6;
3060: }
3061:
3062: void cpu_op_105a(t_ipc *ipc) /* BTST */ {
3063: /* mask ffff, bits 0838, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
3064: uint8 srcdata = ipc->src;
3065: uint32 dstaddr = ipc->dst;
3066: uint8 dstdata = fetchbyte(dstaddr);
3067: uint32 bitpos = 1<<(srcdata & 7);
3068:
3069: ZFLAG = !(dstdata & bitpos);
3070: PC+= 6;
3071: }
3072:
3073: void cpu_op_105b(t_ipc *ipc) /* BTST */ {
3074: /* mask ffff, bits 0838, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
3075: uint8 srcdata = ipc->src;
3076: uint32 dstaddr = ipc->dst;
3077: uint8 dstdata = fetchbyte(dstaddr);
3078: uint32 bitpos = 1<<(srcdata & 7);
3079:
3080: ZFLAG = !(dstdata & bitpos);
3081: PC+= 6;
3082: }
3083:
3084: void cpu_op_106a(t_ipc *ipc) /* BTST */ {
3085: /* mask ffff, bits 0839, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
3086: uint8 srcdata = ipc->src;
3087: uint32 dstaddr = ipc->dst;
3088: uint8 dstdata = fetchbyte(dstaddr);
3089: uint32 bitpos = 1<<(srcdata & 7);
3090:
3091: ZFLAG = !(dstdata & bitpos);
3092: PC+= 8;
3093: }
3094:
3095: void cpu_op_106b(t_ipc *ipc) /* BTST */ {
3096: /* mask ffff, bits 0839, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
3097: uint8 srcdata = ipc->src;
3098: uint32 dstaddr = ipc->dst;
3099: uint8 dstdata = fetchbyte(dstaddr);
3100: uint32 bitpos = 1<<(srcdata & 7);
3101:
3102: ZFLAG = !(dstdata & bitpos);
3103: PC+= 8;
3104: }
3105:
3106: void cpu_op_107a(t_ipc *ipc) /* BTST */ {
3107: /* mask ffff, bits 083a, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 9, sbitpos 0, dbitpos 0, immvalue 0 */
3108: uint8 srcdata = ipc->src;
3109: uint32 dstaddr = ipc->dst;
3110: uint8 dstdata = fetchbyte(dstaddr);
3111: uint32 bitpos = 1<<(srcdata & 7);
3112:
3113: ZFLAG = !(dstdata & bitpos);
3114: PC+= 6;
3115: }
3116:
3117: void cpu_op_107b(t_ipc *ipc) /* BTST */ {
3118: /* mask ffff, bits 083a, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 9, sbitpos 0, dbitpos 0, immvalue 0 */
3119: uint8 srcdata = ipc->src;
3120: uint32 dstaddr = ipc->dst;
3121: uint8 dstdata = fetchbyte(dstaddr);
3122: uint32 bitpos = 1<<(srcdata & 7);
3123:
3124: ZFLAG = !(dstdata & bitpos);
3125: PC+= 6;
3126: }
3127:
3128: void cpu_op_108a(t_ipc *ipc) /* BTST */ {
3129: /* mask ffff, bits 083b, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 10, sbitpos 0, dbitpos 0, immvalue 0 */
3130: uint8 srcdata = ipc->src;
3131: uint32 dstaddr = idxval_dst(ipc);
3132: uint8 dstdata = fetchbyte(dstaddr);
3133: uint32 bitpos = 1<<(srcdata & 7);
3134:
3135: ZFLAG = !(dstdata & bitpos);
3136: PC+= 6;
3137: }
3138:
3139: void cpu_op_108b(t_ipc *ipc) /* BTST */ {
3140: /* mask ffff, bits 083b, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 10, sbitpos 0, dbitpos 0, immvalue 0 */
3141: uint8 srcdata = ipc->src;
3142: uint32 dstaddr = idxval_dst(ipc);
3143: uint8 dstdata = fetchbyte(dstaddr);
3144: uint32 bitpos = 1<<(srcdata & 7);
3145:
3146: ZFLAG = !(dstdata & bitpos);
3147: PC+= 6;
3148: }
3149:
3150: void cpu_op_109a(t_ipc *ipc) /* BCHG */ {
3151: /* mask fff8, bits 0850, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
3152: uint8 srcdata = ipc->src;
3153: int dstreg = (ipc->opcode >> 0) & 7;
3154: uint32 dstaddr = ADDRREG(dstreg);
3155: uint8 dstdata = fetchbyte(dstaddr);
3156: uint32 bitpos = 1<<(srcdata & 7);
3157: uint8 outdata = dstdata ^ bitpos;
3158: storebyte(dstaddr, outdata);
3159:
3160: ZFLAG = !(dstdata & bitpos);
3161: PC+= 4;
3162: }
3163:
3164: void cpu_op_109b(t_ipc *ipc) /* BCHG */ {
3165: /* mask fff8, bits 0850, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
3166: uint8 srcdata = ipc->src;
3167: int dstreg = (ipc->opcode >> 0) & 7;
3168: uint32 dstaddr = ADDRREG(dstreg);
3169: uint8 dstdata = fetchbyte(dstaddr);
3170: uint32 bitpos = 1<<(srcdata & 7);
3171: uint8 outdata = dstdata ^ bitpos;
3172: storebyte(dstaddr, outdata);
3173:
3174: ZFLAG = !(dstdata & bitpos);
3175: PC+= 4;
3176: }
3177:
3178: void cpu_op_110a(t_ipc *ipc) /* BCHG */ {
3179: /* mask fff8, bits 0858, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
3180: uint8 srcdata = ipc->src;
3181: int dstreg = (ipc->opcode >> 0) & 7;
3182: uint32 dstaddr = ADDRREG(dstreg);
3183: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
3184: uint8 dstdata = fetchbyte(dstaddr);
3185: uint32 bitpos = 1<<(srcdata & 7);
3186: uint8 outdata = dstdata ^ bitpos;
3187: storebyte(dstaddr, outdata);
3188:
3189: ZFLAG = !(dstdata & bitpos);
3190: PC+= 4;
3191: }
3192:
3193: void cpu_op_110b(t_ipc *ipc) /* BCHG */ {
3194: /* mask fff8, bits 0858, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
3195: uint8 srcdata = ipc->src;
3196: int dstreg = (ipc->opcode >> 0) & 7;
3197: uint32 dstaddr = ADDRREG(dstreg);
3198: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
3199: uint8 dstdata = fetchbyte(dstaddr);
3200: uint32 bitpos = 1<<(srcdata & 7);
3201: uint8 outdata = dstdata ^ bitpos;
3202: storebyte(dstaddr, outdata);
3203:
3204: ZFLAG = !(dstdata & bitpos);
3205: PC+= 4;
3206: }
3207:
3208: void cpu_op_111a(t_ipc *ipc) /* BCHG */ {
3209: /* mask fff8, bits 0860, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
3210: uint8 srcdata = ipc->src;
3211: int dstreg = (ipc->opcode >> 0) & 7;
3212: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
3213: uint8 dstdata = fetchbyte(dstaddr);
3214: uint32 bitpos = 1<<(srcdata & 7);
3215: uint8 outdata = dstdata ^ bitpos;
3216: storebyte(dstaddr, outdata);
3217:
3218: ZFLAG = !(dstdata & bitpos);
3219: PC+= 4;
3220: }
3221:
3222: void cpu_op_111b(t_ipc *ipc) /* BCHG */ {
3223: /* mask fff8, bits 0860, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
3224: uint8 srcdata = ipc->src;
3225: int dstreg = (ipc->opcode >> 0) & 7;
3226: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
3227: uint8 dstdata = fetchbyte(dstaddr);
3228: uint32 bitpos = 1<<(srcdata & 7);
3229: uint8 outdata = dstdata ^ bitpos;
3230: storebyte(dstaddr, outdata);
3231:
3232: ZFLAG = !(dstdata & bitpos);
3233: PC+= 4;
3234: }
3235:
3236: void cpu_op_112a(t_ipc *ipc) /* BCHG */ {
3237: /* mask fff8, bits 0868, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
3238: uint8 srcdata = ipc->src;
3239: int dstreg = (ipc->opcode >> 0) & 7;
3240: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
3241: uint8 dstdata = fetchbyte(dstaddr);
3242: uint32 bitpos = 1<<(srcdata & 7);
3243: uint8 outdata = dstdata ^ bitpos;
3244: storebyte(dstaddr, outdata);
3245:
3246: ZFLAG = !(dstdata & bitpos);
3247: PC+= 6;
3248: }
3249:
3250: void cpu_op_112b(t_ipc *ipc) /* BCHG */ {
3251: /* mask fff8, bits 0868, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
3252: uint8 srcdata = ipc->src;
3253: int dstreg = (ipc->opcode >> 0) & 7;
3254: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
3255: uint8 dstdata = fetchbyte(dstaddr);
3256: uint32 bitpos = 1<<(srcdata & 7);
3257: uint8 outdata = dstdata ^ bitpos;
3258: storebyte(dstaddr, outdata);
3259:
3260: ZFLAG = !(dstdata & bitpos);
3261: PC+= 6;
3262: }
3263:
3264: void cpu_op_113a(t_ipc *ipc) /* BCHG */ {
3265: /* mask fff8, bits 0870, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
3266: uint8 srcdata = ipc->src;
3267: int dstreg = (ipc->opcode >> 0) & 7;
3268: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
3269: uint8 dstdata = fetchbyte(dstaddr);
3270: uint32 bitpos = 1<<(srcdata & 7);
3271: uint8 outdata = dstdata ^ bitpos;
3272: storebyte(dstaddr, outdata);
3273:
3274: ZFLAG = !(dstdata & bitpos);
3275: PC+= 6;
3276: }
3277:
3278: void cpu_op_113b(t_ipc *ipc) /* BCHG */ {
3279: /* mask fff8, bits 0870, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
3280: uint8 srcdata = ipc->src;
3281: int dstreg = (ipc->opcode >> 0) & 7;
3282: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
3283: uint8 dstdata = fetchbyte(dstaddr);
3284: uint32 bitpos = 1<<(srcdata & 7);
3285: uint8 outdata = dstdata ^ bitpos;
3286: storebyte(dstaddr, outdata);
3287:
3288: ZFLAG = !(dstdata & bitpos);
3289: PC+= 6;
3290: }
3291:
3292: void cpu_op_114a(t_ipc *ipc) /* BCHG */ {
3293: /* mask ffff, bits 0878, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
3294: uint8 srcdata = ipc->src;
3295: uint32 dstaddr = ipc->dst;
3296: uint8 dstdata = fetchbyte(dstaddr);
3297: uint32 bitpos = 1<<(srcdata & 7);
3298: uint8 outdata = dstdata ^ bitpos;
3299: storebyte(dstaddr, outdata);
3300:
3301: ZFLAG = !(dstdata & bitpos);
3302: PC+= 6;
3303: }
3304:
3305: void cpu_op_114b(t_ipc *ipc) /* BCHG */ {
3306: /* mask ffff, bits 0878, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
3307: uint8 srcdata = ipc->src;
3308: uint32 dstaddr = ipc->dst;
3309: uint8 dstdata = fetchbyte(dstaddr);
3310: uint32 bitpos = 1<<(srcdata & 7);
3311: uint8 outdata = dstdata ^ bitpos;
3312: storebyte(dstaddr, outdata);
3313:
3314: ZFLAG = !(dstdata & bitpos);
3315: PC+= 6;
3316: }
3317:
3318: void cpu_op_115a(t_ipc *ipc) /* BCHG */ {
3319: /* mask ffff, bits 0879, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
3320: uint8 srcdata = ipc->src;
3321: uint32 dstaddr = ipc->dst;
3322: uint8 dstdata = fetchbyte(dstaddr);
3323: uint32 bitpos = 1<<(srcdata & 7);
3324: uint8 outdata = dstdata ^ bitpos;
3325: storebyte(dstaddr, outdata);
3326:
3327: ZFLAG = !(dstdata & bitpos);
3328: PC+= 8;
3329: }
3330:
3331: void cpu_op_115b(t_ipc *ipc) /* BCHG */ {
3332: /* mask ffff, bits 0879, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
3333: uint8 srcdata = ipc->src;
3334: uint32 dstaddr = ipc->dst;
3335: uint8 dstdata = fetchbyte(dstaddr);
3336: uint32 bitpos = 1<<(srcdata & 7);
3337: uint8 outdata = dstdata ^ bitpos;
3338: storebyte(dstaddr, outdata);
3339:
3340: ZFLAG = !(dstdata & bitpos);
3341: PC+= 8;
3342: }
3343:
3344: void cpu_op_116a(t_ipc *ipc) /* BCLR */ {
3345: /* mask fff8, bits 0890, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
3346: uint8 srcdata = ipc->src;
3347: int dstreg = (ipc->opcode >> 0) & 7;
3348: uint32 dstaddr = ADDRREG(dstreg);
3349: uint8 dstdata = fetchbyte(dstaddr);
3350: uint32 bitpos = 1<<(srcdata & 7);
3351: uint8 outdata = dstdata & ~bitpos;
3352: storebyte(dstaddr, outdata);
3353:
3354: ZFLAG = !(dstdata & bitpos);
3355: PC+= 4;
3356: }
3357:
3358: void cpu_op_116b(t_ipc *ipc) /* BCLR */ {
3359: /* mask fff8, bits 0890, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
3360: uint8 srcdata = ipc->src;
3361: int dstreg = (ipc->opcode >> 0) & 7;
3362: uint32 dstaddr = ADDRREG(dstreg);
3363: uint8 dstdata = fetchbyte(dstaddr);
3364: uint32 bitpos = 1<<(srcdata & 7);
3365: uint8 outdata = dstdata & ~bitpos;
3366: storebyte(dstaddr, outdata);
3367:
3368: ZFLAG = !(dstdata & bitpos);
3369: PC+= 4;
3370: }
3371:
3372: void cpu_op_117a(t_ipc *ipc) /* BCLR */ {
3373: /* mask fff8, bits 0898, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
3374: uint8 srcdata = ipc->src;
3375: int dstreg = (ipc->opcode >> 0) & 7;
3376: uint32 dstaddr = ADDRREG(dstreg);
3377: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
3378: uint8 dstdata = fetchbyte(dstaddr);
3379: uint32 bitpos = 1<<(srcdata & 7);
3380: uint8 outdata = dstdata & ~bitpos;
3381: storebyte(dstaddr, outdata);
3382:
3383: ZFLAG = !(dstdata & bitpos);
3384: PC+= 4;
3385: }
3386:
3387: void cpu_op_117b(t_ipc *ipc) /* BCLR */ {
3388: /* mask fff8, bits 0898, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
3389: uint8 srcdata = ipc->src;
3390: int dstreg = (ipc->opcode >> 0) & 7;
3391: uint32 dstaddr = ADDRREG(dstreg);
3392: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
3393: uint8 dstdata = fetchbyte(dstaddr);
3394: uint32 bitpos = 1<<(srcdata & 7);
3395: uint8 outdata = dstdata & ~bitpos;
3396: storebyte(dstaddr, outdata);
3397:
3398: ZFLAG = !(dstdata & bitpos);
3399: PC+= 4;
3400: }
3401:
3402: void cpu_op_118a(t_ipc *ipc) /* BCLR */ {
3403: /* mask fff8, bits 08a0, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
3404: uint8 srcdata = ipc->src;
3405: int dstreg = (ipc->opcode >> 0) & 7;
3406: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
3407: uint8 dstdata = fetchbyte(dstaddr);
3408: uint32 bitpos = 1<<(srcdata & 7);
3409: uint8 outdata = dstdata & ~bitpos;
3410: storebyte(dstaddr, outdata);
3411:
3412: ZFLAG = !(dstdata & bitpos);
3413: PC+= 4;
3414: }
3415:
3416: void cpu_op_118b(t_ipc *ipc) /* BCLR */ {
3417: /* mask fff8, bits 08a0, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
3418: uint8 srcdata = ipc->src;
3419: int dstreg = (ipc->opcode >> 0) & 7;
3420: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
3421: uint8 dstdata = fetchbyte(dstaddr);
3422: uint32 bitpos = 1<<(srcdata & 7);
3423: uint8 outdata = dstdata & ~bitpos;
3424: storebyte(dstaddr, outdata);
3425:
3426: ZFLAG = !(dstdata & bitpos);
3427: PC+= 4;
3428: }
3429:
3430: void cpu_op_119a(t_ipc *ipc) /* BCLR */ {
3431: /* mask fff8, bits 08a8, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
3432: uint8 srcdata = ipc->src;
3433: int dstreg = (ipc->opcode >> 0) & 7;
3434: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
3435: uint8 dstdata = fetchbyte(dstaddr);
3436: uint32 bitpos = 1<<(srcdata & 7);
3437: uint8 outdata = dstdata & ~bitpos;
3438: storebyte(dstaddr, outdata);
3439:
3440: ZFLAG = !(dstdata & bitpos);
3441: PC+= 6;
3442: }
3443:
3444: void cpu_op_119b(t_ipc *ipc) /* BCLR */ {
3445: /* mask fff8, bits 08a8, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
3446: uint8 srcdata = ipc->src;
3447: int dstreg = (ipc->opcode >> 0) & 7;
3448: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
3449: uint8 dstdata = fetchbyte(dstaddr);
3450: uint32 bitpos = 1<<(srcdata & 7);
3451: uint8 outdata = dstdata & ~bitpos;
3452: storebyte(dstaddr, outdata);
3453:
3454: ZFLAG = !(dstdata & bitpos);
3455: PC+= 6;
3456: }
3457:
3458: void cpu_op_120a(t_ipc *ipc) /* BCLR */ {
3459: /* mask fff8, bits 08b0, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
3460: uint8 srcdata = ipc->src;
3461: int dstreg = (ipc->opcode >> 0) & 7;
3462: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
3463: uint8 dstdata = fetchbyte(dstaddr);
3464: uint32 bitpos = 1<<(srcdata & 7);
3465: uint8 outdata = dstdata & ~bitpos;
3466: storebyte(dstaddr, outdata);
3467:
3468: ZFLAG = !(dstdata & bitpos);
3469: PC+= 6;
3470: }
3471:
3472: void cpu_op_120b(t_ipc *ipc) /* BCLR */ {
3473: /* mask fff8, bits 08b0, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
3474: uint8 srcdata = ipc->src;
3475: int dstreg = (ipc->opcode >> 0) & 7;
3476: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
3477: uint8 dstdata = fetchbyte(dstaddr);
3478: uint32 bitpos = 1<<(srcdata & 7);
3479: uint8 outdata = dstdata & ~bitpos;
3480: storebyte(dstaddr, outdata);
3481:
3482: ZFLAG = !(dstdata & bitpos);
3483: PC+= 6;
3484: }
3485:
3486: void cpu_op_121a(t_ipc *ipc) /* BCLR */ {
3487: /* mask ffff, bits 08b8, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
3488: uint8 srcdata = ipc->src;
3489: uint32 dstaddr = ipc->dst;
3490: uint8 dstdata = fetchbyte(dstaddr);
3491: uint32 bitpos = 1<<(srcdata & 7);
3492: uint8 outdata = dstdata & ~bitpos;
3493: storebyte(dstaddr, outdata);
3494:
3495: ZFLAG = !(dstdata & bitpos);
3496: PC+= 6;
3497: }
3498:
3499: void cpu_op_121b(t_ipc *ipc) /* BCLR */ {
3500: /* mask ffff, bits 08b8, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
3501: uint8 srcdata = ipc->src;
3502: uint32 dstaddr = ipc->dst;
3503: uint8 dstdata = fetchbyte(dstaddr);
3504: uint32 bitpos = 1<<(srcdata & 7);
3505: uint8 outdata = dstdata & ~bitpos;
3506: storebyte(dstaddr, outdata);
3507:
3508: ZFLAG = !(dstdata & bitpos);
3509: PC+= 6;
3510: }
3511:
3512: void cpu_op_122a(t_ipc *ipc) /* BCLR */ {
3513: /* mask ffff, bits 08b9, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
3514: uint8 srcdata = ipc->src;
3515: uint32 dstaddr = ipc->dst;
3516: uint8 dstdata = fetchbyte(dstaddr);
3517: uint32 bitpos = 1<<(srcdata & 7);
3518: uint8 outdata = dstdata & ~bitpos;
3519: storebyte(dstaddr, outdata);
3520:
3521: ZFLAG = !(dstdata & bitpos);
3522: PC+= 8;
3523: }
3524:
3525: void cpu_op_122b(t_ipc *ipc) /* BCLR */ {
3526: /* mask ffff, bits 08b9, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
3527: uint8 srcdata = ipc->src;
3528: uint32 dstaddr = ipc->dst;
3529: uint8 dstdata = fetchbyte(dstaddr);
3530: uint32 bitpos = 1<<(srcdata & 7);
3531: uint8 outdata = dstdata & ~bitpos;
3532: storebyte(dstaddr, outdata);
3533:
3534: ZFLAG = !(dstdata & bitpos);
3535: PC+= 8;
3536: }
3537:
3538: void cpu_op_123a(t_ipc *ipc) /* BSET */ {
3539: /* mask fff8, bits 08d0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
3540: uint8 srcdata = ipc->src;
3541: int dstreg = (ipc->opcode >> 0) & 7;
3542: uint32 dstaddr = ADDRREG(dstreg);
3543: uint8 dstdata = fetchbyte(dstaddr);
3544: uint32 bitpos = 1<<(srcdata & 7);
3545: uint8 outdata = dstdata | bitpos;
3546: storebyte(dstaddr, outdata);
3547:
3548: ZFLAG = !(dstdata & bitpos);
3549: PC+= 4;
3550: }
3551:
3552: void cpu_op_123b(t_ipc *ipc) /* BSET */ {
3553: /* mask fff8, bits 08d0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
3554: uint8 srcdata = ipc->src;
3555: int dstreg = (ipc->opcode >> 0) & 7;
3556: uint32 dstaddr = ADDRREG(dstreg);
3557: uint8 dstdata = fetchbyte(dstaddr);
3558: uint32 bitpos = 1<<(srcdata & 7);
3559: uint8 outdata = dstdata | bitpos;
3560: storebyte(dstaddr, outdata);
3561:
3562: ZFLAG = !(dstdata & bitpos);
3563: PC+= 4;
3564: }
3565:
3566: void cpu_op_124a(t_ipc *ipc) /* BSET */ {
3567: /* mask fff8, bits 08d8, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
3568: uint8 srcdata = ipc->src;
3569: int dstreg = (ipc->opcode >> 0) & 7;
3570: uint32 dstaddr = ADDRREG(dstreg);
3571: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
3572: uint8 dstdata = fetchbyte(dstaddr);
3573: uint32 bitpos = 1<<(srcdata & 7);
3574: uint8 outdata = dstdata | bitpos;
3575: storebyte(dstaddr, outdata);
3576:
3577: ZFLAG = !(dstdata & bitpos);
3578: PC+= 4;
3579: }
3580:
3581: void cpu_op_124b(t_ipc *ipc) /* BSET */ {
3582: /* mask fff8, bits 08d8, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
3583: uint8 srcdata = ipc->src;
3584: int dstreg = (ipc->opcode >> 0) & 7;
3585: uint32 dstaddr = ADDRREG(dstreg);
3586: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
3587: uint8 dstdata = fetchbyte(dstaddr);
3588: uint32 bitpos = 1<<(srcdata & 7);
3589: uint8 outdata = dstdata | bitpos;
3590: storebyte(dstaddr, outdata);
3591:
3592: ZFLAG = !(dstdata & bitpos);
3593: PC+= 4;
3594: }
3595:
3596: void cpu_op_125a(t_ipc *ipc) /* BSET */ {
3597: /* mask fff8, bits 08e0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
3598: uint8 srcdata = ipc->src;
3599: int dstreg = (ipc->opcode >> 0) & 7;
3600: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
3601: uint8 dstdata = fetchbyte(dstaddr);
3602: uint32 bitpos = 1<<(srcdata & 7);
3603: uint8 outdata = dstdata | bitpos;
3604: storebyte(dstaddr, outdata);
3605:
3606: ZFLAG = !(dstdata & bitpos);
3607: PC+= 4;
3608: }
3609:
3610: void cpu_op_125b(t_ipc *ipc) /* BSET */ {
3611: /* mask fff8, bits 08e0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
3612: uint8 srcdata = ipc->src;
3613: int dstreg = (ipc->opcode >> 0) & 7;
3614: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
3615: uint8 dstdata = fetchbyte(dstaddr);
3616: uint32 bitpos = 1<<(srcdata & 7);
3617: uint8 outdata = dstdata | bitpos;
3618: storebyte(dstaddr, outdata);
3619:
3620: ZFLAG = !(dstdata & bitpos);
3621: PC+= 4;
3622: }
3623:
3624: void cpu_op_126a(t_ipc *ipc) /* BSET */ {
3625: /* mask fff8, bits 08e8, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
3626: uint8 srcdata = ipc->src;
3627: int dstreg = (ipc->opcode >> 0) & 7;
3628: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
3629: uint8 dstdata = fetchbyte(dstaddr);
3630: uint32 bitpos = 1<<(srcdata & 7);
3631: uint8 outdata = dstdata | bitpos;
3632: storebyte(dstaddr, outdata);
3633:
3634: ZFLAG = !(dstdata & bitpos);
3635: PC+= 6;
3636: }
3637:
3638: void cpu_op_126b(t_ipc *ipc) /* BSET */ {
3639: /* mask fff8, bits 08e8, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
3640: uint8 srcdata = ipc->src;
3641: int dstreg = (ipc->opcode >> 0) & 7;
3642: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
3643: uint8 dstdata = fetchbyte(dstaddr);
3644: uint32 bitpos = 1<<(srcdata & 7);
3645: uint8 outdata = dstdata | bitpos;
3646: storebyte(dstaddr, outdata);
3647:
3648: ZFLAG = !(dstdata & bitpos);
3649: PC+= 6;
3650: }
3651:
3652: void cpu_op_127a(t_ipc *ipc) /* BSET */ {
3653: /* mask fff8, bits 08f0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
3654: uint8 srcdata = ipc->src;
3655: int dstreg = (ipc->opcode >> 0) & 7;
3656: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
3657: uint8 dstdata = fetchbyte(dstaddr);
3658: uint32 bitpos = 1<<(srcdata & 7);
3659: uint8 outdata = dstdata | bitpos;
3660: storebyte(dstaddr, outdata);
3661:
3662: ZFLAG = !(dstdata & bitpos);
3663: PC+= 6;
3664: }
3665:
3666: void cpu_op_127b(t_ipc *ipc) /* BSET */ {
3667: /* mask fff8, bits 08f0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
3668: uint8 srcdata = ipc->src;
3669: int dstreg = (ipc->opcode >> 0) & 7;
3670: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
3671: uint8 dstdata = fetchbyte(dstaddr);
3672: uint32 bitpos = 1<<(srcdata & 7);
3673: uint8 outdata = dstdata | bitpos;
3674: storebyte(dstaddr, outdata);
3675:
3676: ZFLAG = !(dstdata & bitpos);
3677: PC+= 6;
3678: }
3679:
3680: void cpu_op_128a(t_ipc *ipc) /* BSET */ {
3681: /* mask ffff, bits 08f8, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
3682: uint8 srcdata = ipc->src;
3683: uint32 dstaddr = ipc->dst;
3684: uint8 dstdata = fetchbyte(dstaddr);
3685: uint32 bitpos = 1<<(srcdata & 7);
3686: uint8 outdata = dstdata | bitpos;
3687: storebyte(dstaddr, outdata);
3688:
3689: ZFLAG = !(dstdata & bitpos);
3690: PC+= 6;
3691: }
3692:
3693: void cpu_op_128b(t_ipc *ipc) /* BSET */ {
3694: /* mask ffff, bits 08f8, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
3695: uint8 srcdata = ipc->src;
3696: uint32 dstaddr = ipc->dst;
3697: uint8 dstdata = fetchbyte(dstaddr);
3698: uint32 bitpos = 1<<(srcdata & 7);
3699: uint8 outdata = dstdata | bitpos;
3700: storebyte(dstaddr, outdata);
3701:
3702: ZFLAG = !(dstdata & bitpos);
3703: PC+= 6;
3704: }
3705:
3706: void cpu_op_129a(t_ipc *ipc) /* BSET */ {
3707: /* mask ffff, bits 08f9, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
3708: uint8 srcdata = ipc->src;
3709: uint32 dstaddr = ipc->dst;
3710: uint8 dstdata = fetchbyte(dstaddr);
3711: uint32 bitpos = 1<<(srcdata & 7);
3712: uint8 outdata = dstdata | bitpos;
3713: storebyte(dstaddr, outdata);
3714:
3715: ZFLAG = !(dstdata & bitpos);
3716: PC+= 8;
3717: }
3718:
3719: void cpu_op_129b(t_ipc *ipc) /* BSET */ {
3720: /* mask ffff, bits 08f9, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
3721: uint8 srcdata = ipc->src;
3722: uint32 dstaddr = ipc->dst;
3723: uint8 dstdata = fetchbyte(dstaddr);
3724: uint32 bitpos = 1<<(srcdata & 7);
3725: uint8 outdata = dstdata | bitpos;
3726: storebyte(dstaddr, outdata);
3727:
3728: ZFLAG = !(dstdata & bitpos);
3729: PC+= 8;
3730: }
3731:
3732: void cpu_op_130a(t_ipc *ipc) /* BTST */ {
3733: /* mask fff8, bits 0800, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
3734: uint8 srcdata = ipc->src;
3735: int dstreg = (ipc->opcode >> 0) & 7;
3736: uint32 dstdata = DATAREG(dstreg);
3737: uint32 bitpos = 1<<(srcdata & 31);
3738:
3739: ZFLAG = !(dstdata & bitpos);
3740: PC+= 4;
3741: }
3742:
3743: void cpu_op_130b(t_ipc *ipc) /* BTST */ {
3744: /* mask fff8, bits 0800, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
3745: uint8 srcdata = ipc->src;
3746: int dstreg = (ipc->opcode >> 0) & 7;
3747: uint32 dstdata = DATAREG(dstreg);
3748: uint32 bitpos = 1<<(srcdata & 31);
3749:
3750: ZFLAG = !(dstdata & bitpos);
3751: PC+= 4;
3752: }
3753:
3754: void cpu_op_131a(t_ipc *ipc) /* BCHG */ {
3755: /* mask fff8, bits 0840, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
3756: uint8 srcdata = ipc->src;
3757: int dstreg = (ipc->opcode >> 0) & 7;
3758: uint32 dstdata = DATAREG(dstreg);
3759: uint32 bitpos = 1<<(srcdata & 31);
3760: uint32 outdata = dstdata ^ bitpos;
3761: DATAREG(dstreg) = outdata;
3762:
3763: ZFLAG = !(dstdata & bitpos);
3764: PC+= 4;
3765: }
3766:
3767: void cpu_op_131b(t_ipc *ipc) /* BCHG */ {
3768: /* mask fff8, bits 0840, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
3769: uint8 srcdata = ipc->src;
3770: int dstreg = (ipc->opcode >> 0) & 7;
3771: uint32 dstdata = DATAREG(dstreg);
3772: uint32 bitpos = 1<<(srcdata & 31);
3773: uint32 outdata = dstdata ^ bitpos;
3774: DATAREG(dstreg) = outdata;
3775:
3776: ZFLAG = !(dstdata & bitpos);
3777: PC+= 4;
3778: }
3779:
3780: void cpu_op_132a(t_ipc *ipc) /* BCLR */ {
3781: /* mask fff8, bits 0880, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
3782: uint8 srcdata = ipc->src;
3783: int dstreg = (ipc->opcode >> 0) & 7;
3784: uint32 dstdata = DATAREG(dstreg);
3785: uint32 bitpos = 1<<(srcdata & 31);
3786: uint32 outdata = dstdata & ~bitpos;
3787: DATAREG(dstreg) = outdata;
3788:
3789: ZFLAG = !(dstdata & bitpos);
3790: PC+= 4;
3791: }
3792:
3793: void cpu_op_132b(t_ipc *ipc) /* BCLR */ {
3794: /* mask fff8, bits 0880, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
3795: uint8 srcdata = ipc->src;
3796: int dstreg = (ipc->opcode >> 0) & 7;
3797: uint32 dstdata = DATAREG(dstreg);
3798: uint32 bitpos = 1<<(srcdata & 31);
3799: uint32 outdata = dstdata & ~bitpos;
3800: DATAREG(dstreg) = outdata;
3801:
3802: ZFLAG = !(dstdata & bitpos);
3803: PC+= 4;
3804: }
3805:
3806: void cpu_op_133a(t_ipc *ipc) /* BSET */ {
3807: /* mask fff8, bits 08c0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
3808: uint8 srcdata = ipc->src;
3809: int dstreg = (ipc->opcode >> 0) & 7;
3810: uint32 dstdata = DATAREG(dstreg);
3811: uint32 bitpos = 1<<(srcdata & 31);
3812: uint32 outdata = dstdata | bitpos;
3813: DATAREG(dstreg) = outdata;
3814:
3815: ZFLAG = !(dstdata & bitpos);
3816: PC+= 4;
3817: }
3818:
3819: void cpu_op_133b(t_ipc *ipc) /* BSET */ {
3820: /* mask fff8, bits 08c0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
3821: uint8 srcdata = ipc->src;
3822: int dstreg = (ipc->opcode >> 0) & 7;
3823: uint32 dstdata = DATAREG(dstreg);
3824: uint32 bitpos = 1<<(srcdata & 31);
3825: uint32 outdata = dstdata | bitpos;
3826: DATAREG(dstreg) = outdata;
3827:
3828: ZFLAG = !(dstdata & bitpos);
3829: PC+= 4;
3830: }
3831:
3832: void cpu_op_134a(t_ipc *ipc) /* EORSR */ {
3833: /* mask ffff, bits 0a3c, mnemonic 6, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 11, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3834: uint8 srcdata = ipc->src;
3835: unsigned int sr = reg68k_sr.sr_struct.s;
3836:
3837: SR^= srcdata;
3838: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3839: /* mode change, swap SP and A7 */
3840: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3841: }
3842: PC+= 4;
3843: }
3844:
3845: void cpu_op_135a(t_ipc *ipc) /* EORSR */ {
3846: /* mask ffff, bits 0a7c, mnemonic 6, priv -1, endblk 0, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3847: uint16 srcdata = ipc->src;
3848: unsigned int sr = reg68k_sr.sr_struct.s;
3849:
3850: if (!SFLAG)
3851: reg68k_vector(V_PRIVILEGE, PC+4);
3852:
3853: SR^= srcdata;
3854: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3855: /* mode change, swap SP and A7 */
3856: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3857: }
3858: PC+= 4;
3859: }
3860:
3861: void cpu_op_136a(t_ipc *ipc) /* EOR */ {
3862: /* mask fff8, bits 0a00, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
3863: uint8 srcdata = ipc->src;
3864: int dstreg = (ipc->opcode >> 0) & 7;
3865: uint8 dstdata = DATAREG(dstreg);
3866: uint8 outdata = dstdata;
3867:
3868: outdata^= srcdata;
3869: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
3870: PC+= 4;
3871: }
3872:
3873: void cpu_op_136b(t_ipc *ipc) /* EOR */ {
3874: /* mask fff8, bits 0a00, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
3875: uint8 srcdata = ipc->src;
3876: int dstreg = (ipc->opcode >> 0) & 7;
3877: uint8 dstdata = DATAREG(dstreg);
3878: uint8 outdata = dstdata;
3879:
3880: outdata^= srcdata;
3881: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
3882:
3883: NFLAG = ((sint8)outdata) < 0;
3884: ZFLAG = !outdata;
3885: VFLAG = 0;
3886: CFLAG = 0;
3887: PC+= 4;
3888: }
3889:
3890: void cpu_op_137a(t_ipc *ipc) /* EOR */ {
3891: /* mask fff8, bits 0a10, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
3892: uint8 srcdata = ipc->src;
3893: int dstreg = (ipc->opcode >> 0) & 7;
3894: uint32 dstaddr = ADDRREG(dstreg);
3895: uint8 dstdata = fetchbyte(dstaddr);
3896: uint8 outdata = dstdata;
3897:
3898: outdata^= srcdata;
3899: storebyte(dstaddr, outdata);
3900: PC+= 4;
3901: }
3902:
3903: void cpu_op_137b(t_ipc *ipc) /* EOR */ {
3904: /* mask fff8, bits 0a10, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
3905: uint8 srcdata = ipc->src;
3906: int dstreg = (ipc->opcode >> 0) & 7;
3907: uint32 dstaddr = ADDRREG(dstreg);
3908: uint8 dstdata = fetchbyte(dstaddr);
3909: uint8 outdata = dstdata;
3910:
3911: outdata^= srcdata;
3912: storebyte(dstaddr, outdata);
3913:
3914: NFLAG = ((sint8)outdata) < 0;
3915: ZFLAG = !outdata;
3916: VFLAG = 0;
3917: CFLAG = 0;
3918: PC+= 4;
3919: }
3920:
3921: void cpu_op_138a(t_ipc *ipc) /* EOR */ {
3922: /* mask fff8, bits 0a18, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
3923: uint8 srcdata = ipc->src;
3924: int dstreg = (ipc->opcode >> 0) & 7;
3925: uint32 dstaddr = ADDRREG(dstreg);
3926: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
3927: uint8 dstdata = fetchbyte(dstaddr);
3928: uint8 outdata = dstdata;
3929:
3930: outdata^= srcdata;
3931: storebyte(dstaddr, outdata);
3932: PC+= 4;
3933: }
3934:
3935: void cpu_op_138b(t_ipc *ipc) /* EOR */ {
3936: /* mask fff8, bits 0a18, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
3937: uint8 srcdata = ipc->src;
3938: int dstreg = (ipc->opcode >> 0) & 7;
3939: uint32 dstaddr = ADDRREG(dstreg);
3940: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
3941: uint8 dstdata = fetchbyte(dstaddr);
3942: uint8 outdata = dstdata;
3943:
3944: outdata^= srcdata;
3945: storebyte(dstaddr, outdata);
3946:
3947: NFLAG = ((sint8)outdata) < 0;
3948: ZFLAG = !outdata;
3949: VFLAG = 0;
3950: CFLAG = 0;
3951: PC+= 4;
3952: }
3953:
3954: void cpu_op_139a(t_ipc *ipc) /* EOR */ {
3955: /* mask fff8, bits 0a20, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
3956: uint8 srcdata = ipc->src;
3957: int dstreg = (ipc->opcode >> 0) & 7;
3958: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
3959: uint8 dstdata = fetchbyte(dstaddr);
3960: uint8 outdata = dstdata;
3961:
3962: outdata^= srcdata;
3963: storebyte(dstaddr, outdata);
3964: PC+= 4;
3965: }
3966:
3967: void cpu_op_139b(t_ipc *ipc) /* EOR */ {
3968: /* mask fff8, bits 0a20, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
3969: uint8 srcdata = ipc->src;
3970: int dstreg = (ipc->opcode >> 0) & 7;
3971: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
3972: uint8 dstdata = fetchbyte(dstaddr);
3973: uint8 outdata = dstdata;
3974:
3975: outdata^= srcdata;
3976: storebyte(dstaddr, outdata);
3977:
3978: NFLAG = ((sint8)outdata) < 0;
3979: ZFLAG = !outdata;
3980: VFLAG = 0;
3981: CFLAG = 0;
3982: PC+= 4;
3983: }
3984:
3985: void cpu_op_140a(t_ipc *ipc) /* EOR */ {
3986: /* mask fff8, bits 0a28, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
3987: uint8 srcdata = ipc->src;
3988: int dstreg = (ipc->opcode >> 0) & 7;
3989: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
3990: uint8 dstdata = fetchbyte(dstaddr);
3991: uint8 outdata = dstdata;
3992:
3993: outdata^= srcdata;
3994: storebyte(dstaddr, outdata);
3995: PC+= 6;
3996: }
3997:
3998: void cpu_op_140b(t_ipc *ipc) /* EOR */ {
3999: /* mask fff8, bits 0a28, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
4000: uint8 srcdata = ipc->src;
4001: int dstreg = (ipc->opcode >> 0) & 7;
4002: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
4003: uint8 dstdata = fetchbyte(dstaddr);
4004: uint8 outdata = dstdata;
4005:
4006: outdata^= srcdata;
4007: storebyte(dstaddr, outdata);
4008:
4009: NFLAG = ((sint8)outdata) < 0;
4010: ZFLAG = !outdata;
4011: VFLAG = 0;
4012: CFLAG = 0;
4013: PC+= 6;
4014: }
4015:
4016: void cpu_op_141a(t_ipc *ipc) /* EOR */ {
4017: /* mask fff8, bits 0a30, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
4018: uint8 srcdata = ipc->src;
4019: int dstreg = (ipc->opcode >> 0) & 7;
4020: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
4021: uint8 dstdata = fetchbyte(dstaddr);
4022: uint8 outdata = dstdata;
4023:
4024: outdata^= srcdata;
4025: storebyte(dstaddr, outdata);
4026: PC+= 6;
4027: }
4028:
4029: void cpu_op_141b(t_ipc *ipc) /* EOR */ {
4030: /* mask fff8, bits 0a30, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
4031: uint8 srcdata = ipc->src;
4032: int dstreg = (ipc->opcode >> 0) & 7;
4033: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
4034: uint8 dstdata = fetchbyte(dstaddr);
4035: uint8 outdata = dstdata;
4036:
4037: outdata^= srcdata;
4038: storebyte(dstaddr, outdata);
4039:
4040: NFLAG = ((sint8)outdata) < 0;
4041: ZFLAG = !outdata;
4042: VFLAG = 0;
4043: CFLAG = 0;
4044: PC+= 6;
4045: }
4046:
4047: void cpu_op_142a(t_ipc *ipc) /* EOR */ {
4048: /* mask ffff, bits 0a38, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
4049: uint8 srcdata = ipc->src;
4050: uint32 dstaddr = ipc->dst;
4051: uint8 dstdata = fetchbyte(dstaddr);
4052: uint8 outdata = dstdata;
4053:
4054: outdata^= srcdata;
4055: storebyte(dstaddr, outdata);
4056: PC+= 6;
4057: }
4058:
4059: void cpu_op_142b(t_ipc *ipc) /* EOR */ {
4060: /* mask ffff, bits 0a38, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
4061: uint8 srcdata = ipc->src;
4062: uint32 dstaddr = ipc->dst;
4063: uint8 dstdata = fetchbyte(dstaddr);
4064: uint8 outdata = dstdata;
4065:
4066: outdata^= srcdata;
4067: storebyte(dstaddr, outdata);
4068:
4069: NFLAG = ((sint8)outdata) < 0;
4070: ZFLAG = !outdata;
4071: VFLAG = 0;
4072: CFLAG = 0;
4073: PC+= 6;
4074: }
4075:
4076: void cpu_op_143a(t_ipc *ipc) /* EOR */ {
4077: /* mask ffff, bits 0a39, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
4078: uint8 srcdata = ipc->src;
4079: uint32 dstaddr = ipc->dst;
4080: uint8 dstdata = fetchbyte(dstaddr);
4081: uint8 outdata = dstdata;
4082:
4083: outdata^= srcdata;
4084: storebyte(dstaddr, outdata);
4085: PC+= 8;
4086: }
4087:
4088: void cpu_op_143b(t_ipc *ipc) /* EOR */ {
4089: /* mask ffff, bits 0a39, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
4090: uint8 srcdata = ipc->src;
4091: uint32 dstaddr = ipc->dst;
4092: uint8 dstdata = fetchbyte(dstaddr);
4093: uint8 outdata = dstdata;
4094:
4095: outdata^= srcdata;
4096: storebyte(dstaddr, outdata);
4097:
4098: NFLAG = ((sint8)outdata) < 0;
4099: ZFLAG = !outdata;
4100: VFLAG = 0;
4101: CFLAG = 0;
4102: PC+= 8;
4103: }
4104:
4105: void cpu_op_144a(t_ipc *ipc) /* EOR */ {
4106: /* mask fff8, bits 0a40, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4107: uint16 srcdata = ipc->src;
4108: int dstreg = (ipc->opcode >> 0) & 7;
4109: uint16 dstdata = DATAREG(dstreg);
4110: uint16 outdata = dstdata;
4111:
4112: outdata^= srcdata;
4113: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
4114: PC+= 4;
4115: }
4116:
4117: void cpu_op_144b(t_ipc *ipc) /* EOR */ {
4118: /* mask fff8, bits 0a40, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4119: uint16 srcdata = ipc->src;
4120: int dstreg = (ipc->opcode >> 0) & 7;
4121: uint16 dstdata = DATAREG(dstreg);
4122: uint16 outdata = dstdata;
4123:
4124: outdata^= srcdata;
4125: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
4126:
4127: NFLAG = ((sint16)outdata) < 0;
4128: ZFLAG = !outdata;
4129: VFLAG = 0;
4130: CFLAG = 0;
4131: PC+= 4;
4132: }
4133:
4134: void cpu_op_145a(t_ipc *ipc) /* EOR */ {
4135: /* mask fff8, bits 0a50, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
4136: uint16 srcdata = ipc->src;
4137: int dstreg = (ipc->opcode >> 0) & 7;
4138: uint32 dstaddr = ADDRREG(dstreg);
4139: uint16 dstdata = fetchword(dstaddr);
4140: uint16 outdata = dstdata;
4141:
4142: outdata^= srcdata;
4143: storeword(dstaddr, outdata);
4144: PC+= 4;
4145: }
4146:
4147: void cpu_op_145b(t_ipc *ipc) /* EOR */ {
4148: /* mask fff8, bits 0a50, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
4149: uint16 srcdata = ipc->src;
4150: int dstreg = (ipc->opcode >> 0) & 7;
4151: uint32 dstaddr = ADDRREG(dstreg);
4152: uint16 dstdata = fetchword(dstaddr);
4153: uint16 outdata = dstdata;
4154:
4155: outdata^= srcdata;
4156: storeword(dstaddr, outdata);
4157:
4158: NFLAG = ((sint16)outdata) < 0;
4159: ZFLAG = !outdata;
4160: VFLAG = 0;
4161: CFLAG = 0;
4162: PC+= 4;
4163: }
4164:
4165: void cpu_op_146a(t_ipc *ipc) /* EOR */ {
4166: /* mask fff8, bits 0a58, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
4167: uint16 srcdata = ipc->src;
4168: int dstreg = (ipc->opcode >> 0) & 7;
4169: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
4170: uint16 dstdata = fetchword(dstaddr);
4171: uint16 outdata = dstdata;
4172:
4173: outdata^= srcdata;
4174: storeword(dstaddr, outdata);
4175: PC+= 4;
4176: }
4177:
4178: void cpu_op_146b(t_ipc *ipc) /* EOR */ {
4179: /* mask fff8, bits 0a58, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
4180: uint16 srcdata = ipc->src;
4181: int dstreg = (ipc->opcode >> 0) & 7;
4182: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
4183: uint16 dstdata = fetchword(dstaddr);
4184: uint16 outdata = dstdata;
4185:
4186: outdata^= srcdata;
4187: storeword(dstaddr, outdata);
4188:
4189: NFLAG = ((sint16)outdata) < 0;
4190: ZFLAG = !outdata;
4191: VFLAG = 0;
4192: CFLAG = 0;
4193: PC+= 4;
4194: }
4195:
4196: void cpu_op_147a(t_ipc *ipc) /* EOR */ {
4197: /* mask fff8, bits 0a60, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
4198: uint16 srcdata = ipc->src;
4199: int dstreg = (ipc->opcode >> 0) & 7;
4200: uint32 dstaddr = ADDRREG(dstreg)-=2;
4201: uint16 dstdata = fetchword(dstaddr);
4202: uint16 outdata = dstdata;
4203:
4204: outdata^= srcdata;
4205: storeword(dstaddr, outdata);
4206: PC+= 4;
4207: }
4208:
4209: void cpu_op_147b(t_ipc *ipc) /* EOR */ {
4210: /* mask fff8, bits 0a60, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
4211: uint16 srcdata = ipc->src;
4212: int dstreg = (ipc->opcode >> 0) & 7;
4213: uint32 dstaddr = ADDRREG(dstreg)-=2;
4214: uint16 dstdata = fetchword(dstaddr);
4215: uint16 outdata = dstdata;
4216:
4217: outdata^= srcdata;
4218: storeword(dstaddr, outdata);
4219:
4220: NFLAG = ((sint16)outdata) < 0;
4221: ZFLAG = !outdata;
4222: VFLAG = 0;
4223: CFLAG = 0;
4224: PC+= 4;
4225: }
4226:
4227: void cpu_op_148a(t_ipc *ipc) /* EOR */ {
4228: /* mask fff8, bits 0a68, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
4229: uint16 srcdata = ipc->src;
4230: int dstreg = (ipc->opcode >> 0) & 7;
4231: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
4232: uint16 dstdata = fetchword(dstaddr);
4233: uint16 outdata = dstdata;
4234:
4235: outdata^= srcdata;
4236: storeword(dstaddr, outdata);
4237: PC+= 6;
4238: }
4239:
4240: void cpu_op_148b(t_ipc *ipc) /* EOR */ {
4241: /* mask fff8, bits 0a68, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
4242: uint16 srcdata = ipc->src;
4243: int dstreg = (ipc->opcode >> 0) & 7;
4244: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
4245: uint16 dstdata = fetchword(dstaddr);
4246: uint16 outdata = dstdata;
4247:
4248: outdata^= srcdata;
4249: storeword(dstaddr, outdata);
4250:
4251: NFLAG = ((sint16)outdata) < 0;
4252: ZFLAG = !outdata;
4253: VFLAG = 0;
4254: CFLAG = 0;
4255: PC+= 6;
4256: }
4257:
4258: void cpu_op_149a(t_ipc *ipc) /* EOR */ {
4259: /* mask fff8, bits 0a70, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
4260: uint16 srcdata = ipc->src;
4261: int dstreg = (ipc->opcode >> 0) & 7;
4262: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
4263: uint16 dstdata = fetchword(dstaddr);
4264: uint16 outdata = dstdata;
4265:
4266: outdata^= srcdata;
4267: storeword(dstaddr, outdata);
4268: PC+= 6;
4269: }
4270:
4271: void cpu_op_149b(t_ipc *ipc) /* EOR */ {
4272: /* mask fff8, bits 0a70, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
4273: uint16 srcdata = ipc->src;
4274: int dstreg = (ipc->opcode >> 0) & 7;
4275: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
4276: uint16 dstdata = fetchword(dstaddr);
4277: uint16 outdata = dstdata;
4278:
4279: outdata^= srcdata;
4280: storeword(dstaddr, outdata);
4281:
4282: NFLAG = ((sint16)outdata) < 0;
4283: ZFLAG = !outdata;
4284: VFLAG = 0;
4285: CFLAG = 0;
4286: PC+= 6;
4287: }
4288:
4289: void cpu_op_150a(t_ipc *ipc) /* EOR */ {
4290: /* mask ffff, bits 0a78, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
4291: uint16 srcdata = ipc->src;
4292: uint32 dstaddr = ipc->dst;
4293: uint16 dstdata = fetchword(dstaddr);
4294: uint16 outdata = dstdata;
4295:
4296: outdata^= srcdata;
4297: storeword(dstaddr, outdata);
4298: PC+= 6;
4299: }
4300:
4301: void cpu_op_150b(t_ipc *ipc) /* EOR */ {
4302: /* mask ffff, bits 0a78, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
4303: uint16 srcdata = ipc->src;
4304: uint32 dstaddr = ipc->dst;
4305: uint16 dstdata = fetchword(dstaddr);
4306: uint16 outdata = dstdata;
4307:
4308: outdata^= srcdata;
4309: storeword(dstaddr, outdata);
4310:
4311: NFLAG = ((sint16)outdata) < 0;
4312: ZFLAG = !outdata;
4313: VFLAG = 0;
4314: CFLAG = 0;
4315: PC+= 6;
4316: }
4317:
4318: void cpu_op_151a(t_ipc *ipc) /* EOR */ {
4319: /* mask ffff, bits 0a79, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
4320: uint16 srcdata = ipc->src;
4321: uint32 dstaddr = ipc->dst;
4322: uint16 dstdata = fetchword(dstaddr);
4323: uint16 outdata = dstdata;
4324:
4325: outdata^= srcdata;
4326: storeword(dstaddr, outdata);
4327: PC+= 8;
4328: }
4329:
4330: void cpu_op_151b(t_ipc *ipc) /* EOR */ {
4331: /* mask ffff, bits 0a79, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
4332: uint16 srcdata = ipc->src;
4333: uint32 dstaddr = ipc->dst;
4334: uint16 dstdata = fetchword(dstaddr);
4335: uint16 outdata = dstdata;
4336:
4337: outdata^= srcdata;
4338: storeword(dstaddr, outdata);
4339:
4340: NFLAG = ((sint16)outdata) < 0;
4341: ZFLAG = !outdata;
4342: VFLAG = 0;
4343: CFLAG = 0;
4344: PC+= 8;
4345: }
4346:
4347: void cpu_op_152a(t_ipc *ipc) /* EOR */ {
4348: /* mask fff8, bits 0a80, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4349: uint32 srcdata = ipc->src;
4350: int dstreg = (ipc->opcode >> 0) & 7;
4351: uint32 dstdata = DATAREG(dstreg);
4352: uint32 outdata = dstdata;
4353:
4354: outdata^= srcdata;
4355: DATAREG(dstreg) = outdata;
4356: PC+= 6;
4357: }
4358:
4359: void cpu_op_152b(t_ipc *ipc) /* EOR */ {
4360: /* mask fff8, bits 0a80, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4361: uint32 srcdata = ipc->src;
4362: int dstreg = (ipc->opcode >> 0) & 7;
4363: uint32 dstdata = DATAREG(dstreg);
4364: uint32 outdata = dstdata;
4365:
4366: outdata^= srcdata;
4367: DATAREG(dstreg) = outdata;
4368:
4369: NFLAG = ((sint32)outdata) < 0;
4370: ZFLAG = !outdata;
4371: VFLAG = 0;
4372: CFLAG = 0;
4373: PC+= 6;
4374: }
4375:
4376: void cpu_op_153a(t_ipc *ipc) /* EOR */ {
4377: /* mask fff8, bits 0a90, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
4378: uint32 srcdata = ipc->src;
4379: int dstreg = (ipc->opcode >> 0) & 7;
4380: uint32 dstaddr = ADDRREG(dstreg);
4381: uint32 dstdata = fetchlong(dstaddr);
4382: uint32 outdata = dstdata;
4383:
4384: outdata^= srcdata;
4385: storelong(dstaddr, outdata);
4386: PC+= 6;
4387: }
4388:
4389: void cpu_op_153b(t_ipc *ipc) /* EOR */ {
4390: /* mask fff8, bits 0a90, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
4391: uint32 srcdata = ipc->src;
4392: int dstreg = (ipc->opcode >> 0) & 7;
4393: uint32 dstaddr = ADDRREG(dstreg);
4394: uint32 dstdata = fetchlong(dstaddr);
4395: uint32 outdata = dstdata;
4396:
4397: outdata^= srcdata;
4398: storelong(dstaddr, outdata);
4399:
4400: NFLAG = ((sint32)outdata) < 0;
4401: ZFLAG = !outdata;
4402: VFLAG = 0;
4403: CFLAG = 0;
4404: PC+= 6;
4405: }
4406:
4407: void cpu_op_154a(t_ipc *ipc) /* EOR */ {
4408: /* mask fff8, bits 0a98, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
4409: uint32 srcdata = ipc->src;
4410: int dstreg = (ipc->opcode >> 0) & 7;
4411: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
4412: uint32 dstdata = fetchlong(dstaddr);
4413: uint32 outdata = dstdata;
4414:
4415: outdata^= srcdata;
4416: storelong(dstaddr, outdata);
4417: PC+= 6;
4418: }
4419:
4420: void cpu_op_154b(t_ipc *ipc) /* EOR */ {
4421: /* mask fff8, bits 0a98, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
4422: uint32 srcdata = ipc->src;
4423: int dstreg = (ipc->opcode >> 0) & 7;
4424: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
4425: uint32 dstdata = fetchlong(dstaddr);
4426: uint32 outdata = dstdata;
4427:
4428: outdata^= srcdata;
4429: storelong(dstaddr, outdata);
4430:
4431: NFLAG = ((sint32)outdata) < 0;
4432: ZFLAG = !outdata;
4433: VFLAG = 0;
4434: CFLAG = 0;
4435: PC+= 6;
4436: }
4437:
4438: void cpu_op_155a(t_ipc *ipc) /* EOR */ {
4439: /* mask fff8, bits 0aa0, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
4440: uint32 srcdata = ipc->src;
4441: int dstreg = (ipc->opcode >> 0) & 7;
4442: uint32 dstaddr = ADDRREG(dstreg)-=4;
4443: uint32 dstdata = fetchlong(dstaddr);
4444: uint32 outdata = dstdata;
4445:
4446: outdata^= srcdata;
4447: storelong(dstaddr, outdata);
4448: PC+= 6;
4449: }
4450:
4451: void cpu_op_155b(t_ipc *ipc) /* EOR */ {
4452: /* mask fff8, bits 0aa0, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
4453: uint32 srcdata = ipc->src;
4454: int dstreg = (ipc->opcode >> 0) & 7;
4455: uint32 dstaddr = ADDRREG(dstreg)-=4;
4456: uint32 dstdata = fetchlong(dstaddr);
4457: uint32 outdata = dstdata;
4458:
4459: outdata^= srcdata;
4460: storelong(dstaddr, outdata);
4461:
4462: NFLAG = ((sint32)outdata) < 0;
4463: ZFLAG = !outdata;
4464: VFLAG = 0;
4465: CFLAG = 0;
4466: PC+= 6;
4467: }
4468:
4469: void cpu_op_156a(t_ipc *ipc) /* EOR */ {
4470: /* mask fff8, bits 0aa8, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
4471: uint32 srcdata = ipc->src;
4472: int dstreg = (ipc->opcode >> 0) & 7;
4473: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
4474: uint32 dstdata = fetchlong(dstaddr);
4475: uint32 outdata = dstdata;
4476:
4477: outdata^= srcdata;
4478: storelong(dstaddr, outdata);
4479: PC+= 8;
4480: }
4481:
4482: void cpu_op_156b(t_ipc *ipc) /* EOR */ {
4483: /* mask fff8, bits 0aa8, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
4484: uint32 srcdata = ipc->src;
4485: int dstreg = (ipc->opcode >> 0) & 7;
4486: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
4487: uint32 dstdata = fetchlong(dstaddr);
4488: uint32 outdata = dstdata;
4489:
4490: outdata^= srcdata;
4491: storelong(dstaddr, outdata);
4492:
4493: NFLAG = ((sint32)outdata) < 0;
4494: ZFLAG = !outdata;
4495: VFLAG = 0;
4496: CFLAG = 0;
4497: PC+= 8;
4498: }
4499:
4500: void cpu_op_157a(t_ipc *ipc) /* EOR */ {
4501: /* mask fff8, bits 0ab0, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
4502: uint32 srcdata = ipc->src;
4503: int dstreg = (ipc->opcode >> 0) & 7;
4504: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
4505: uint32 dstdata = fetchlong(dstaddr);
4506: uint32 outdata = dstdata;
4507:
4508: outdata^= srcdata;
4509: storelong(dstaddr, outdata);
4510: PC+= 8;
4511: }
4512:
4513: void cpu_op_157b(t_ipc *ipc) /* EOR */ {
4514: /* mask fff8, bits 0ab0, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
4515: uint32 srcdata = ipc->src;
4516: int dstreg = (ipc->opcode >> 0) & 7;
4517: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
4518: uint32 dstdata = fetchlong(dstaddr);
4519: uint32 outdata = dstdata;
4520:
4521: outdata^= srcdata;
4522: storelong(dstaddr, outdata);
4523:
4524: NFLAG = ((sint32)outdata) < 0;
4525: ZFLAG = !outdata;
4526: VFLAG = 0;
4527: CFLAG = 0;
4528: PC+= 8;
4529: }
4530:
4531: void cpu_op_158a(t_ipc *ipc) /* EOR */ {
4532: /* mask ffff, bits 0ab8, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
4533: uint32 srcdata = ipc->src;
4534: uint32 dstaddr = ipc->dst;
4535: uint32 dstdata = fetchlong(dstaddr);
4536: uint32 outdata = dstdata;
4537:
4538: outdata^= srcdata;
4539: storelong(dstaddr, outdata);
4540: PC+= 8;
4541: }
4542:
4543: void cpu_op_158b(t_ipc *ipc) /* EOR */ {
4544: /* mask ffff, bits 0ab8, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
4545: uint32 srcdata = ipc->src;
4546: uint32 dstaddr = ipc->dst;
4547: uint32 dstdata = fetchlong(dstaddr);
4548: uint32 outdata = dstdata;
4549:
4550: outdata^= srcdata;
4551: storelong(dstaddr, outdata);
4552:
4553: NFLAG = ((sint32)outdata) < 0;
4554: ZFLAG = !outdata;
4555: VFLAG = 0;
4556: CFLAG = 0;
4557: PC+= 8;
4558: }
4559:
4560: void cpu_op_159a(t_ipc *ipc) /* EOR */ {
4561: /* mask ffff, bits 0ab9, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
4562: uint32 srcdata = ipc->src;
4563: uint32 dstaddr = ipc->dst;
4564: uint32 dstdata = fetchlong(dstaddr);
4565: uint32 outdata = dstdata;
4566:
4567: outdata^= srcdata;
4568: storelong(dstaddr, outdata);
4569: PC+= 10;
4570: }
4571:
4572: void cpu_op_159b(t_ipc *ipc) /* EOR */ {
4573: /* mask ffff, bits 0ab9, mnemonic 5, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
4574: uint32 srcdata = ipc->src;
4575: uint32 dstaddr = ipc->dst;
4576: uint32 dstdata = fetchlong(dstaddr);
4577: uint32 outdata = dstdata;
4578:
4579: outdata^= srcdata;
4580: storelong(dstaddr, outdata);
4581:
4582: NFLAG = ((sint32)outdata) < 0;
4583: ZFLAG = !outdata;
4584: VFLAG = 0;
4585: CFLAG = 0;
4586: PC+= 10;
4587: }
4588:
4589: void cpu_op_160a(t_ipc *ipc) /* CMP */ {
4590: /* mask fff8, bits 0c00, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4591: uint8 srcdata = ipc->src;
4592: int dstreg = (ipc->opcode >> 0) & 7;
4593: uint8 dstdata = DATAREG(dstreg);
4594: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4595: PC+= 4;
4596: }
4597:
4598: void cpu_op_160b(t_ipc *ipc) /* CMP */ {
4599: /* mask fff8, bits 0c00, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4600: uint8 srcdata = ipc->src;
4601: int dstreg = (ipc->opcode >> 0) & 7;
4602: uint8 dstdata = DATAREG(dstreg);
4603: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4604:
4605: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
4606: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
4607: CFLAG = srcdata > dstdata;
4608: NFLAG = ((sint8)outdata) < 0;
4609: ZFLAG = !outdata;
4610: PC+= 4;
4611: }
4612:
4613: void cpu_op_161a(t_ipc *ipc) /* CMP */ {
4614: /* mask fff8, bits 0c10, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
4615: uint8 srcdata = ipc->src;
4616: int dstreg = (ipc->opcode >> 0) & 7;
4617: uint32 dstaddr = ADDRREG(dstreg);
4618: uint8 dstdata = fetchbyte(dstaddr);
4619: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4620: PC+= 4;
4621: }
4622:
4623: void cpu_op_161b(t_ipc *ipc) /* CMP */ {
4624: /* mask fff8, bits 0c10, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
4625: uint8 srcdata = ipc->src;
4626: int dstreg = (ipc->opcode >> 0) & 7;
4627: uint32 dstaddr = ADDRREG(dstreg);
4628: uint8 dstdata = fetchbyte(dstaddr);
4629: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4630:
4631: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
4632: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
4633: CFLAG = srcdata > dstdata;
4634: NFLAG = ((sint8)outdata) < 0;
4635: ZFLAG = !outdata;
4636: PC+= 4;
4637: }
4638:
4639: void cpu_op_162a(t_ipc *ipc) /* CMP */ {
4640: /* mask fff8, bits 0c18, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
4641: uint8 srcdata = ipc->src;
4642: int dstreg = (ipc->opcode >> 0) & 7;
4643: uint32 dstaddr = ADDRREG(dstreg);
4644: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
4645: uint8 dstdata = fetchbyte(dstaddr);
4646: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4647: PC+= 4;
4648: }
4649:
4650: void cpu_op_162b(t_ipc *ipc) /* CMP */ {
4651: /* mask fff8, bits 0c18, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
4652: uint8 srcdata = ipc->src;
4653: int dstreg = (ipc->opcode >> 0) & 7;
4654: uint32 dstaddr = ADDRREG(dstreg);
4655: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
4656: uint8 dstdata = fetchbyte(dstaddr);
4657: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4658:
4659: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
4660: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
4661: CFLAG = srcdata > dstdata;
4662: NFLAG = ((sint8)outdata) < 0;
4663: ZFLAG = !outdata;
4664: PC+= 4;
4665: }
4666:
4667: void cpu_op_163a(t_ipc *ipc) /* CMP */ {
4668: /* mask fff8, bits 0c20, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
4669: uint8 srcdata = ipc->src;
4670: int dstreg = (ipc->opcode >> 0) & 7;
4671: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
4672: uint8 dstdata = fetchbyte(dstaddr);
4673: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4674: PC+= 4;
4675: }
4676:
4677: void cpu_op_163b(t_ipc *ipc) /* CMP */ {
4678: /* mask fff8, bits 0c20, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
4679: uint8 srcdata = ipc->src;
4680: int dstreg = (ipc->opcode >> 0) & 7;
4681: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
4682: uint8 dstdata = fetchbyte(dstaddr);
4683: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4684:
4685: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
4686: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
4687: CFLAG = srcdata > dstdata;
4688: NFLAG = ((sint8)outdata) < 0;
4689: ZFLAG = !outdata;
4690: PC+= 4;
4691: }
4692:
4693: void cpu_op_164a(t_ipc *ipc) /* CMP */ {
4694: /* mask fff8, bits 0c28, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
4695: uint8 srcdata = ipc->src;
4696: int dstreg = (ipc->opcode >> 0) & 7;
4697: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
4698: uint8 dstdata = fetchbyte(dstaddr);
4699: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4700: PC+= 6;
4701: }
4702:
4703: void cpu_op_164b(t_ipc *ipc) /* CMP */ {
4704: /* mask fff8, bits 0c28, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
4705: uint8 srcdata = ipc->src;
4706: int dstreg = (ipc->opcode >> 0) & 7;
4707: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
4708: uint8 dstdata = fetchbyte(dstaddr);
4709: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4710:
4711: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
4712: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
4713: CFLAG = srcdata > dstdata;
4714: NFLAG = ((sint8)outdata) < 0;
4715: ZFLAG = !outdata;
4716: PC+= 6;
4717: }
4718:
4719: void cpu_op_165a(t_ipc *ipc) /* CMP */ {
4720: /* mask fff8, bits 0c30, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
4721: uint8 srcdata = ipc->src;
4722: int dstreg = (ipc->opcode >> 0) & 7;
4723: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
4724: uint8 dstdata = fetchbyte(dstaddr);
4725: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4726: PC+= 6;
4727: }
4728:
4729: void cpu_op_165b(t_ipc *ipc) /* CMP */ {
4730: /* mask fff8, bits 0c30, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
4731: uint8 srcdata = ipc->src;
4732: int dstreg = (ipc->opcode >> 0) & 7;
4733: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
4734: uint8 dstdata = fetchbyte(dstaddr);
4735: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4736:
4737: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
4738: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
4739: CFLAG = srcdata > dstdata;
4740: NFLAG = ((sint8)outdata) < 0;
4741: ZFLAG = !outdata;
4742: PC+= 6;
4743: }
4744:
4745: void cpu_op_166a(t_ipc *ipc) /* CMP */ {
4746: /* mask ffff, bits 0c38, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
4747: uint8 srcdata = ipc->src;
4748: uint32 dstaddr = ipc->dst;
4749: uint8 dstdata = fetchbyte(dstaddr);
4750: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4751: PC+= 6;
4752: }
4753:
4754: void cpu_op_166b(t_ipc *ipc) /* CMP */ {
4755: /* mask ffff, bits 0c38, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
4756: uint8 srcdata = ipc->src;
4757: uint32 dstaddr = ipc->dst;
4758: uint8 dstdata = fetchbyte(dstaddr);
4759: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4760:
4761: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
4762: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
4763: CFLAG = srcdata > dstdata;
4764: NFLAG = ((sint8)outdata) < 0;
4765: ZFLAG = !outdata;
4766: PC+= 6;
4767: }
4768:
4769: void cpu_op_167a(t_ipc *ipc) /* CMP */ {
4770: /* mask ffff, bits 0c39, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
4771: uint8 srcdata = ipc->src;
4772: uint32 dstaddr = ipc->dst;
4773: uint8 dstdata = fetchbyte(dstaddr);
4774: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4775: PC+= 8;
4776: }
4777:
4778: void cpu_op_167b(t_ipc *ipc) /* CMP */ {
4779: /* mask ffff, bits 0c39, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
4780: uint8 srcdata = ipc->src;
4781: uint32 dstaddr = ipc->dst;
4782: uint8 dstdata = fetchbyte(dstaddr);
4783: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
4784:
4785: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
4786: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
4787: CFLAG = srcdata > dstdata;
4788: NFLAG = ((sint8)outdata) < 0;
4789: ZFLAG = !outdata;
4790: PC+= 8;
4791: }
4792:
4793: void cpu_op_168a(t_ipc *ipc) /* CMP */ {
4794: /* mask fff8, bits 0c40, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4795: uint16 srcdata = ipc->src;
4796: int dstreg = (ipc->opcode >> 0) & 7;
4797: uint16 dstdata = DATAREG(dstreg);
4798: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4799: PC+= 4;
4800: }
4801:
4802: void cpu_op_168b(t_ipc *ipc) /* CMP */ {
4803: /* mask fff8, bits 0c40, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4804: uint16 srcdata = ipc->src;
4805: int dstreg = (ipc->opcode >> 0) & 7;
4806: uint16 dstdata = DATAREG(dstreg);
4807: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4808:
4809: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
4810: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
4811: CFLAG = srcdata > dstdata;
4812: NFLAG = ((sint16)outdata) < 0;
4813: ZFLAG = !outdata;
4814: PC+= 4;
4815: }
4816:
4817: void cpu_op_169a(t_ipc *ipc) /* CMP */ {
4818: /* mask fff8, bits 0c50, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
4819: uint16 srcdata = ipc->src;
4820: int dstreg = (ipc->opcode >> 0) & 7;
4821: uint32 dstaddr = ADDRREG(dstreg);
4822: uint16 dstdata = fetchword(dstaddr);
4823: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4824: PC+= 4;
4825: }
4826:
4827: void cpu_op_169b(t_ipc *ipc) /* CMP */ {
4828: /* mask fff8, bits 0c50, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
4829: uint16 srcdata = ipc->src;
4830: int dstreg = (ipc->opcode >> 0) & 7;
4831: uint32 dstaddr = ADDRREG(dstreg);
4832: uint16 dstdata = fetchword(dstaddr);
4833: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4834:
4835: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
4836: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
4837: CFLAG = srcdata > dstdata;
4838: NFLAG = ((sint16)outdata) < 0;
4839: ZFLAG = !outdata;
4840: PC+= 4;
4841: }
4842:
4843: void cpu_op_170a(t_ipc *ipc) /* CMP */ {
4844: /* mask fff8, bits 0c58, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
4845: uint16 srcdata = ipc->src;
4846: int dstreg = (ipc->opcode >> 0) & 7;
4847: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
4848: uint16 dstdata = fetchword(dstaddr);
4849: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4850: PC+= 4;
4851: }
4852:
4853: void cpu_op_170b(t_ipc *ipc) /* CMP */ {
4854: /* mask fff8, bits 0c58, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
4855: uint16 srcdata = ipc->src;
4856: int dstreg = (ipc->opcode >> 0) & 7;
4857: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
4858: uint16 dstdata = fetchword(dstaddr);
4859: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4860:
4861: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
4862: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
4863: CFLAG = srcdata > dstdata;
4864: NFLAG = ((sint16)outdata) < 0;
4865: ZFLAG = !outdata;
4866: PC+= 4;
4867: }
4868:
4869: void cpu_op_171a(t_ipc *ipc) /* CMP */ {
4870: /* mask fff8, bits 0c60, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
4871: uint16 srcdata = ipc->src;
4872: int dstreg = (ipc->opcode >> 0) & 7;
4873: uint32 dstaddr = ADDRREG(dstreg)-=2;
4874: uint16 dstdata = fetchword(dstaddr);
4875: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4876: PC+= 4;
4877: }
4878:
4879: void cpu_op_171b(t_ipc *ipc) /* CMP */ {
4880: /* mask fff8, bits 0c60, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
4881: uint16 srcdata = ipc->src;
4882: int dstreg = (ipc->opcode >> 0) & 7;
4883: uint32 dstaddr = ADDRREG(dstreg)-=2;
4884: uint16 dstdata = fetchword(dstaddr);
4885: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4886:
4887: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
4888: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
4889: CFLAG = srcdata > dstdata;
4890: NFLAG = ((sint16)outdata) < 0;
4891: ZFLAG = !outdata;
4892: PC+= 4;
4893: }
4894:
4895: void cpu_op_172a(t_ipc *ipc) /* CMP */ {
4896: /* mask fff8, bits 0c68, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
4897: uint16 srcdata = ipc->src;
4898: int dstreg = (ipc->opcode >> 0) & 7;
4899: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
4900: uint16 dstdata = fetchword(dstaddr);
4901: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4902: PC+= 6;
4903: }
4904:
4905: void cpu_op_172b(t_ipc *ipc) /* CMP */ {
4906: /* mask fff8, bits 0c68, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
4907: uint16 srcdata = ipc->src;
4908: int dstreg = (ipc->opcode >> 0) & 7;
4909: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
4910: uint16 dstdata = fetchword(dstaddr);
4911: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4912:
4913: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
4914: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
4915: CFLAG = srcdata > dstdata;
4916: NFLAG = ((sint16)outdata) < 0;
4917: ZFLAG = !outdata;
4918: PC+= 6;
4919: }
4920:
4921: void cpu_op_173a(t_ipc *ipc) /* CMP */ {
4922: /* mask fff8, bits 0c70, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
4923: uint16 srcdata = ipc->src;
4924: int dstreg = (ipc->opcode >> 0) & 7;
4925: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
4926: uint16 dstdata = fetchword(dstaddr);
4927: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4928: PC+= 6;
4929: }
4930:
4931: void cpu_op_173b(t_ipc *ipc) /* CMP */ {
4932: /* mask fff8, bits 0c70, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
4933: uint16 srcdata = ipc->src;
4934: int dstreg = (ipc->opcode >> 0) & 7;
4935: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
4936: uint16 dstdata = fetchword(dstaddr);
4937: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4938:
4939: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
4940: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
4941: CFLAG = srcdata > dstdata;
4942: NFLAG = ((sint16)outdata) < 0;
4943: ZFLAG = !outdata;
4944: PC+= 6;
4945: }
4946:
4947: void cpu_op_174a(t_ipc *ipc) /* CMP */ {
4948: /* mask ffff, bits 0c78, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
4949: uint16 srcdata = ipc->src;
4950: uint32 dstaddr = ipc->dst;
4951: uint16 dstdata = fetchword(dstaddr);
4952: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4953: PC+= 6;
4954: }
4955:
4956: void cpu_op_174b(t_ipc *ipc) /* CMP */ {
4957: /* mask ffff, bits 0c78, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
4958: uint16 srcdata = ipc->src;
4959: uint32 dstaddr = ipc->dst;
4960: uint16 dstdata = fetchword(dstaddr);
4961: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4962:
4963: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
4964: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
4965: CFLAG = srcdata > dstdata;
4966: NFLAG = ((sint16)outdata) < 0;
4967: ZFLAG = !outdata;
4968: PC+= 6;
4969: }
4970:
4971: void cpu_op_175a(t_ipc *ipc) /* CMP */ {
4972: /* mask ffff, bits 0c79, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
4973: uint16 srcdata = ipc->src;
4974: uint32 dstaddr = ipc->dst;
4975: uint16 dstdata = fetchword(dstaddr);
4976: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4977: PC+= 8;
4978: }
4979:
4980: void cpu_op_175b(t_ipc *ipc) /* CMP */ {
4981: /* mask ffff, bits 0c79, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
4982: uint16 srcdata = ipc->src;
4983: uint32 dstaddr = ipc->dst;
4984: uint16 dstdata = fetchword(dstaddr);
4985: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
4986:
4987: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
4988: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
4989: CFLAG = srcdata > dstdata;
4990: NFLAG = ((sint16)outdata) < 0;
4991: ZFLAG = !outdata;
4992: PC+= 8;
4993: }
4994:
4995: void cpu_op_176a(t_ipc *ipc) /* CMP */ {
4996: /* mask fff8, bits 0c80, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4997: uint32 srcdata = ipc->src;
4998: int dstreg = (ipc->opcode >> 0) & 7;
4999: uint32 dstdata = DATAREG(dstreg);
5000: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5001: PC+= 6;
5002: }
5003:
5004: void cpu_op_176b(t_ipc *ipc) /* CMP */ {
5005: /* mask fff8, bits 0c80, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
5006: uint32 srcdata = ipc->src;
5007: int dstreg = (ipc->opcode >> 0) & 7;
5008: uint32 dstdata = DATAREG(dstreg);
5009: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5010:
5011: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
5012: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
5013: CFLAG = srcdata > dstdata;
5014: NFLAG = ((sint32)outdata) < 0;
5015: ZFLAG = !outdata;
5016: PC+= 6;
5017: }
5018:
5019: void cpu_op_177a(t_ipc *ipc) /* CMP */ {
5020: /* mask fff8, bits 0c90, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
5021: uint32 srcdata = ipc->src;
5022: int dstreg = (ipc->opcode >> 0) & 7;
5023: uint32 dstaddr = ADDRREG(dstreg);
5024: uint32 dstdata = fetchlong(dstaddr);
5025: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5026: PC+= 6;
5027: }
5028:
5029: void cpu_op_177b(t_ipc *ipc) /* CMP */ {
5030: /* mask fff8, bits 0c90, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
5031: uint32 srcdata = ipc->src;
5032: int dstreg = (ipc->opcode >> 0) & 7;
5033: uint32 dstaddr = ADDRREG(dstreg);
5034: uint32 dstdata = fetchlong(dstaddr);
5035: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5036:
5037: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
5038: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
5039: CFLAG = srcdata > dstdata;
5040: NFLAG = ((sint32)outdata) < 0;
5041: ZFLAG = !outdata;
5042: PC+= 6;
5043: }
5044:
5045: void cpu_op_178a(t_ipc *ipc) /* CMP */ {
5046: /* mask fff8, bits 0c98, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
5047: uint32 srcdata = ipc->src;
5048: int dstreg = (ipc->opcode >> 0) & 7;
5049: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
5050: uint32 dstdata = fetchlong(dstaddr);
5051: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5052: PC+= 6;
5053: }
5054:
5055: void cpu_op_178b(t_ipc *ipc) /* CMP */ {
5056: /* mask fff8, bits 0c98, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
5057: uint32 srcdata = ipc->src;
5058: int dstreg = (ipc->opcode >> 0) & 7;
5059: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
5060: uint32 dstdata = fetchlong(dstaddr);
5061: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5062:
5063: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
5064: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
5065: CFLAG = srcdata > dstdata;
5066: NFLAG = ((sint32)outdata) < 0;
5067: ZFLAG = !outdata;
5068: PC+= 6;
5069: }
5070:
5071: void cpu_op_179a(t_ipc *ipc) /* CMP */ {
5072: /* mask fff8, bits 0ca0, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
5073: uint32 srcdata = ipc->src;
5074: int dstreg = (ipc->opcode >> 0) & 7;
5075: uint32 dstaddr = ADDRREG(dstreg)-=4;
5076: uint32 dstdata = fetchlong(dstaddr);
5077: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5078: PC+= 6;
5079: }
5080:
5081: void cpu_op_179b(t_ipc *ipc) /* CMP */ {
5082: /* mask fff8, bits 0ca0, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
5083: uint32 srcdata = ipc->src;
5084: int dstreg = (ipc->opcode >> 0) & 7;
5085: uint32 dstaddr = ADDRREG(dstreg)-=4;
5086: uint32 dstdata = fetchlong(dstaddr);
5087: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5088:
5089: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
5090: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
5091: CFLAG = srcdata > dstdata;
5092: NFLAG = ((sint32)outdata) < 0;
5093: ZFLAG = !outdata;
5094: PC+= 6;
5095: }
5096:
5097: void cpu_op_180a(t_ipc *ipc) /* CMP */ {
5098: /* mask fff8, bits 0ca8, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
5099: uint32 srcdata = ipc->src;
5100: int dstreg = (ipc->opcode >> 0) & 7;
5101: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
5102: uint32 dstdata = fetchlong(dstaddr);
5103: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5104: PC+= 8;
5105: }
5106:
5107: void cpu_op_180b(t_ipc *ipc) /* CMP */ {
5108: /* mask fff8, bits 0ca8, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
5109: uint32 srcdata = ipc->src;
5110: int dstreg = (ipc->opcode >> 0) & 7;
5111: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
5112: uint32 dstdata = fetchlong(dstaddr);
5113: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5114:
5115: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
5116: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
5117: CFLAG = srcdata > dstdata;
5118: NFLAG = ((sint32)outdata) < 0;
5119: ZFLAG = !outdata;
5120: PC+= 8;
5121: }
5122:
5123: void cpu_op_181a(t_ipc *ipc) /* CMP */ {
5124: /* mask fff8, bits 0cb0, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
5125: uint32 srcdata = ipc->src;
5126: int dstreg = (ipc->opcode >> 0) & 7;
5127: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
5128: uint32 dstdata = fetchlong(dstaddr);
5129: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5130: PC+= 8;
5131: }
5132:
5133: void cpu_op_181b(t_ipc *ipc) /* CMP */ {
5134: /* mask fff8, bits 0cb0, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
5135: uint32 srcdata = ipc->src;
5136: int dstreg = (ipc->opcode >> 0) & 7;
5137: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
5138: uint32 dstdata = fetchlong(dstaddr);
5139: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5140:
5141: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
5142: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
5143: CFLAG = srcdata > dstdata;
5144: NFLAG = ((sint32)outdata) < 0;
5145: ZFLAG = !outdata;
5146: PC+= 8;
5147: }
5148:
5149: void cpu_op_182a(t_ipc *ipc) /* CMP */ {
5150: /* mask ffff, bits 0cb8, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
5151: uint32 srcdata = ipc->src;
5152: uint32 dstaddr = ipc->dst;
5153: uint32 dstdata = fetchlong(dstaddr);
5154: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5155: PC+= 8;
5156: }
5157:
5158: void cpu_op_182b(t_ipc *ipc) /* CMP */ {
5159: /* mask ffff, bits 0cb8, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
5160: uint32 srcdata = ipc->src;
5161: uint32 dstaddr = ipc->dst;
5162: uint32 dstdata = fetchlong(dstaddr);
5163: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5164:
5165: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
5166: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
5167: CFLAG = srcdata > dstdata;
5168: NFLAG = ((sint32)outdata) < 0;
5169: ZFLAG = !outdata;
5170: PC+= 8;
5171: }
5172:
5173: void cpu_op_183a(t_ipc *ipc) /* CMP */ {
5174: /* mask ffff, bits 0cb9, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
5175: uint32 srcdata = ipc->src;
5176: uint32 dstaddr = ipc->dst;
5177: uint32 dstdata = fetchlong(dstaddr);
5178: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5179: PC+= 10;
5180: }
5181:
5182: void cpu_op_183b(t_ipc *ipc) /* CMP */ {
5183: /* mask ffff, bits 0cb9, mnemonic 15, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
5184: uint32 srcdata = ipc->src;
5185: uint32 dstaddr = ipc->dst;
5186: uint32 dstdata = fetchlong(dstaddr);
5187: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
5188:
5189: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
5190: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
5191: CFLAG = srcdata > dstdata;
5192: NFLAG = ((sint32)outdata) < 0;
5193: ZFLAG = !outdata;
5194: PC+= 10;
5195: }
5196:
5197: void cpu_op_184a(t_ipc *ipc) /* MOVEPMR */ {
5198: /* mask f1f8, bits 0108, mnemonic 23, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5199: int srcreg = (ipc->opcode >> 0) & 7;
5200: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
5201: int dstreg = (ipc->opcode >> 9) & 7;
5202: uint16 dstdata = DATAREG(dstreg);
5203: uint16 outdata = (fetchbyte(srcaddr) << 8) + fetchbyte(srcaddr+2);
5204:
5205: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
5206: PC+= 4;
5207: }
5208:
5209: void cpu_op_185a(t_ipc *ipc) /* MOVEPMR */ {
5210: /* mask f1f8, bits 0148, mnemonic 23, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5211: int srcreg = (ipc->opcode >> 0) & 7;
5212: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
5213: int dstreg = (ipc->opcode >> 9) & 7;
5214: uint32 dstdata = DATAREG(dstreg);
5215: uint32 outdata = (fetchbyte(srcaddr) << 24) | (fetchbyte(srcaddr+2) << 16) |
5216: (fetchbyte(srcaddr+4) << 8) | fetchbyte(srcaddr+6);
5217:
5218: DATAREG(dstreg) = outdata;
5219: PC+= 4;
5220: }
5221:
5222: void cpu_op_186a(t_ipc *ipc) /* MOVEPRM */ {
5223: /* mask f1f8, bits 0188, mnemonic 24, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
5224: int srcreg = (ipc->opcode >> 9) & 7;
5225: uint16 srcdata = DATAREG(srcreg);
5226: int dstreg = (ipc->opcode >> 0) & 7;
5227: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
5228:
5229: storebyte(dstaddr, (srcdata >> 8) & 0xFF);
5230: storebyte(dstaddr+2, srcdata & 0xFF);
5231: PC+= 4;
5232: }
5233:
5234: void cpu_op_187a(t_ipc *ipc) /* MOVEPRM */ {
5235: /* mask f1f8, bits 01c8, mnemonic 24, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
5236: int srcreg = (ipc->opcode >> 9) & 7;
5237: uint32 srcdata = DATAREG(srcreg);
5238: int dstreg = (ipc->opcode >> 0) & 7;
5239: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
5240:
5241: storebyte(dstaddr, (srcdata >> 24) & 0xFF);
5242: storebyte(dstaddr+2, (srcdata >> 16) & 0xFF);
5243: storebyte(dstaddr+4, (srcdata >> 8) & 0xFF);
5244: storebyte(dstaddr+6, srcdata & 0xFF);
5245: PC+= 4;
5246: }
5247:
5248: void cpu_op_188a(t_ipc *ipc) /* BTST */ {
5249: /* mask f1f8, bits 0110, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
5250: int srcreg = (ipc->opcode >> 9) & 7;
5251: uint8 srcdata = DATAREG(srcreg);
5252: int dstreg = (ipc->opcode >> 0) & 7;
5253: uint32 dstaddr = ADDRREG(dstreg);
5254: uint8 dstdata = fetchbyte(dstaddr);
5255: uint32 bitpos = 1<<(srcdata & 7);
5256:
5257: ZFLAG = !(dstdata & bitpos);
5258: PC+= 2;
5259: }
5260:
5261: void cpu_op_188b(t_ipc *ipc) /* BTST */ {
5262: /* mask f1f8, bits 0110, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
5263: int srcreg = (ipc->opcode >> 9) & 7;
5264: uint8 srcdata = DATAREG(srcreg);
5265: int dstreg = (ipc->opcode >> 0) & 7;
5266: uint32 dstaddr = ADDRREG(dstreg);
5267: uint8 dstdata = fetchbyte(dstaddr);
5268: uint32 bitpos = 1<<(srcdata & 7);
5269:
5270: ZFLAG = !(dstdata & bitpos);
5271: PC+= 2;
5272: }
5273:
5274: void cpu_op_189a(t_ipc *ipc) /* BTST */ {
5275: /* mask f1f8, bits 0118, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
5276: int srcreg = (ipc->opcode >> 9) & 7;
5277: uint8 srcdata = DATAREG(srcreg);
5278: int dstreg = (ipc->opcode >> 0) & 7;
5279: uint32 dstaddr = ADDRREG(dstreg);
5280: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
5281: uint8 dstdata = fetchbyte(dstaddr);
5282: uint32 bitpos = 1<<(srcdata & 7);
5283:
5284: ZFLAG = !(dstdata & bitpos);
5285: PC+= 2;
5286: }
5287:
5288: void cpu_op_189b(t_ipc *ipc) /* BTST */ {
5289: /* mask f1f8, bits 0118, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
5290: int srcreg = (ipc->opcode >> 9) & 7;
5291: uint8 srcdata = DATAREG(srcreg);
5292: int dstreg = (ipc->opcode >> 0) & 7;
5293: uint32 dstaddr = ADDRREG(dstreg);
5294: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
5295: uint8 dstdata = fetchbyte(dstaddr);
5296: uint32 bitpos = 1<<(srcdata & 7);
5297:
5298: ZFLAG = !(dstdata & bitpos);
5299: PC+= 2;
5300: }
5301:
5302: void cpu_op_190a(t_ipc *ipc) /* BTST */ {
5303: /* mask f1f8, bits 0120, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
5304: int srcreg = (ipc->opcode >> 9) & 7;
5305: uint8 srcdata = DATAREG(srcreg);
5306: int dstreg = (ipc->opcode >> 0) & 7;
5307: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
5308: uint8 dstdata = fetchbyte(dstaddr);
5309: uint32 bitpos = 1<<(srcdata & 7);
5310:
5311: ZFLAG = !(dstdata & bitpos);
5312: PC+= 2;
5313: }
5314:
5315: void cpu_op_190b(t_ipc *ipc) /* BTST */ {
5316: /* mask f1f8, bits 0120, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
5317: int srcreg = (ipc->opcode >> 9) & 7;
5318: uint8 srcdata = DATAREG(srcreg);
5319: int dstreg = (ipc->opcode >> 0) & 7;
5320: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
5321: uint8 dstdata = fetchbyte(dstaddr);
5322: uint32 bitpos = 1<<(srcdata & 7);
5323:
5324: ZFLAG = !(dstdata & bitpos);
5325: PC+= 2;
5326: }
5327:
5328: void cpu_op_191a(t_ipc *ipc) /* BTST */ {
5329: /* mask f1f8, bits 0128, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
5330: int srcreg = (ipc->opcode >> 9) & 7;
5331: uint8 srcdata = DATAREG(srcreg);
5332: int dstreg = (ipc->opcode >> 0) & 7;
5333: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
5334: uint8 dstdata = fetchbyte(dstaddr);
5335: uint32 bitpos = 1<<(srcdata & 7);
5336:
5337: ZFLAG = !(dstdata & bitpos);
5338: PC+= 4;
5339: }
5340:
5341: void cpu_op_191b(t_ipc *ipc) /* BTST */ {
5342: /* mask f1f8, bits 0128, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
5343: int srcreg = (ipc->opcode >> 9) & 7;
5344: uint8 srcdata = DATAREG(srcreg);
5345: int dstreg = (ipc->opcode >> 0) & 7;
5346: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
5347: uint8 dstdata = fetchbyte(dstaddr);
5348: uint32 bitpos = 1<<(srcdata & 7);
5349:
5350: ZFLAG = !(dstdata & bitpos);
5351: PC+= 4;
5352: }
5353:
5354: void cpu_op_192a(t_ipc *ipc) /* BTST */ {
5355: /* mask f1f8, bits 0130, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
5356: int srcreg = (ipc->opcode >> 9) & 7;
5357: uint8 srcdata = DATAREG(srcreg);
5358: int dstreg = (ipc->opcode >> 0) & 7;
5359: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
5360: uint8 dstdata = fetchbyte(dstaddr);
5361: uint32 bitpos = 1<<(srcdata & 7);
5362:
5363: ZFLAG = !(dstdata & bitpos);
5364: PC+= 4;
5365: }
5366:
5367: void cpu_op_192b(t_ipc *ipc) /* BTST */ {
5368: /* mask f1f8, bits 0130, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
5369: int srcreg = (ipc->opcode >> 9) & 7;
5370: uint8 srcdata = DATAREG(srcreg);
5371: int dstreg = (ipc->opcode >> 0) & 7;
5372: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
5373: uint8 dstdata = fetchbyte(dstaddr);
5374: uint32 bitpos = 1<<(srcdata & 7);
5375:
5376: ZFLAG = !(dstdata & bitpos);
5377: PC+= 4;
5378: }
5379:
5380: void cpu_op_193a(t_ipc *ipc) /* BTST */ {
5381: /* mask f1ff, bits 0138, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
5382: int srcreg = (ipc->opcode >> 9) & 7;
5383: uint8 srcdata = DATAREG(srcreg);
5384: uint32 dstaddr = ipc->dst;
5385: uint8 dstdata = fetchbyte(dstaddr);
5386: uint32 bitpos = 1<<(srcdata & 7);
5387:
5388: ZFLAG = !(dstdata & bitpos);
5389: PC+= 4;
5390: }
5391:
5392: void cpu_op_193b(t_ipc *ipc) /* BTST */ {
5393: /* mask f1ff, bits 0138, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
5394: int srcreg = (ipc->opcode >> 9) & 7;
5395: uint8 srcdata = DATAREG(srcreg);
5396: uint32 dstaddr = ipc->dst;
5397: uint8 dstdata = fetchbyte(dstaddr);
5398: uint32 bitpos = 1<<(srcdata & 7);
5399:
5400: ZFLAG = !(dstdata & bitpos);
5401: PC+= 4;
5402: }
5403:
5404: void cpu_op_194a(t_ipc *ipc) /* BTST */ {
5405: /* mask f1ff, bits 0139, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
5406: int srcreg = (ipc->opcode >> 9) & 7;
5407: uint8 srcdata = DATAREG(srcreg);
5408: uint32 dstaddr = ipc->dst;
5409: uint8 dstdata = fetchbyte(dstaddr);
5410: uint32 bitpos = 1<<(srcdata & 7);
5411:
5412: ZFLAG = !(dstdata & bitpos);
5413: PC+= 6;
5414: }
5415:
5416: void cpu_op_194b(t_ipc *ipc) /* BTST */ {
5417: /* mask f1ff, bits 0139, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
5418: int srcreg = (ipc->opcode >> 9) & 7;
5419: uint8 srcdata = DATAREG(srcreg);
5420: uint32 dstaddr = ipc->dst;
5421: uint8 dstdata = fetchbyte(dstaddr);
5422: uint32 bitpos = 1<<(srcdata & 7);
5423:
5424: ZFLAG = !(dstdata & bitpos);
5425: PC+= 6;
5426: }
5427:
5428: void cpu_op_195a(t_ipc *ipc) /* BTST */ {
5429: /* mask f1ff, bits 013a, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 9, sbitpos 9, dbitpos 0, immvalue 0 */
5430: int srcreg = (ipc->opcode >> 9) & 7;
5431: uint8 srcdata = DATAREG(srcreg);
5432: uint32 dstaddr = ipc->dst;
5433: uint8 dstdata = fetchbyte(dstaddr);
5434: uint32 bitpos = 1<<(srcdata & 7);
5435:
5436: ZFLAG = !(dstdata & bitpos);
5437: PC+= 4;
5438: }
5439:
5440: void cpu_op_195b(t_ipc *ipc) /* BTST */ {
5441: /* mask f1ff, bits 013a, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 9, sbitpos 9, dbitpos 0, immvalue 0 */
5442: int srcreg = (ipc->opcode >> 9) & 7;
5443: uint8 srcdata = DATAREG(srcreg);
5444: uint32 dstaddr = ipc->dst;
5445: uint8 dstdata = fetchbyte(dstaddr);
5446: uint32 bitpos = 1<<(srcdata & 7);
5447:
5448: ZFLAG = !(dstdata & bitpos);
5449: PC+= 4;
5450: }
5451:
5452: void cpu_op_196a(t_ipc *ipc) /* BTST */ {
5453: /* mask f1ff, bits 013b, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 10, sbitpos 9, dbitpos 0, immvalue 0 */
5454: int srcreg = (ipc->opcode >> 9) & 7;
5455: uint8 srcdata = DATAREG(srcreg);
5456: uint32 dstaddr = idxval_dst(ipc);
5457: uint8 dstdata = fetchbyte(dstaddr);
5458: uint32 bitpos = 1<<(srcdata & 7);
5459:
5460: ZFLAG = !(dstdata & bitpos);
5461: PC+= 4;
5462: }
5463:
5464: void cpu_op_196b(t_ipc *ipc) /* BTST */ {
5465: /* mask f1ff, bits 013b, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 10, sbitpos 9, dbitpos 0, immvalue 0 */
5466: int srcreg = (ipc->opcode >> 9) & 7;
5467: uint8 srcdata = DATAREG(srcreg);
5468: uint32 dstaddr = idxval_dst(ipc);
5469: uint8 dstdata = fetchbyte(dstaddr);
5470: uint32 bitpos = 1<<(srcdata & 7);
5471:
5472: ZFLAG = !(dstdata & bitpos);
5473: PC+= 4;
5474: }
5475:
5476: void cpu_op_197a(t_ipc *ipc) /* BCHG */ {
5477: /* mask f1f8, bits 0150, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
5478: int srcreg = (ipc->opcode >> 9) & 7;
5479: uint8 srcdata = DATAREG(srcreg);
5480: int dstreg = (ipc->opcode >> 0) & 7;
5481: uint32 dstaddr = ADDRREG(dstreg);
5482: uint8 dstdata = fetchbyte(dstaddr);
5483: uint32 bitpos = 1<<(srcdata & 7);
5484: uint8 outdata = dstdata ^ bitpos;
5485: storebyte(dstaddr, outdata);
5486:
5487: ZFLAG = !(dstdata & bitpos);
5488: PC+= 2;
5489: }
5490:
5491: void cpu_op_197b(t_ipc *ipc) /* BCHG */ {
5492: /* mask f1f8, bits 0150, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
5493: int srcreg = (ipc->opcode >> 9) & 7;
5494: uint8 srcdata = DATAREG(srcreg);
5495: int dstreg = (ipc->opcode >> 0) & 7;
5496: uint32 dstaddr = ADDRREG(dstreg);
5497: uint8 dstdata = fetchbyte(dstaddr);
5498: uint32 bitpos = 1<<(srcdata & 7);
5499: uint8 outdata = dstdata ^ bitpos;
5500: storebyte(dstaddr, outdata);
5501:
5502: ZFLAG = !(dstdata & bitpos);
5503: PC+= 2;
5504: }
5505:
5506: void cpu_op_198a(t_ipc *ipc) /* BCHG */ {
5507: /* mask f1f8, bits 0158, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
5508: int srcreg = (ipc->opcode >> 9) & 7;
5509: uint8 srcdata = DATAREG(srcreg);
5510: int dstreg = (ipc->opcode >> 0) & 7;
5511: uint32 dstaddr = ADDRREG(dstreg);
5512: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
5513: uint8 dstdata = fetchbyte(dstaddr);
5514: uint32 bitpos = 1<<(srcdata & 7);
5515: uint8 outdata = dstdata ^ bitpos;
5516: storebyte(dstaddr, outdata);
5517:
5518: ZFLAG = !(dstdata & bitpos);
5519: PC+= 2;
5520: }
5521:
5522: void cpu_op_198b(t_ipc *ipc) /* BCHG */ {
5523: /* mask f1f8, bits 0158, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
5524: int srcreg = (ipc->opcode >> 9) & 7;
5525: uint8 srcdata = DATAREG(srcreg);
5526: int dstreg = (ipc->opcode >> 0) & 7;
5527: uint32 dstaddr = ADDRREG(dstreg);
5528: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
5529: uint8 dstdata = fetchbyte(dstaddr);
5530: uint32 bitpos = 1<<(srcdata & 7);
5531: uint8 outdata = dstdata ^ bitpos;
5532: storebyte(dstaddr, outdata);
5533:
5534: ZFLAG = !(dstdata & bitpos);
5535: PC+= 2;
5536: }
5537:
5538: void cpu_op_199a(t_ipc *ipc) /* BCHG */ {
5539: /* mask f1f8, bits 0160, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
5540: int srcreg = (ipc->opcode >> 9) & 7;
5541: uint8 srcdata = DATAREG(srcreg);
5542: int dstreg = (ipc->opcode >> 0) & 7;
5543: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
5544: uint8 dstdata = fetchbyte(dstaddr);
5545: uint32 bitpos = 1<<(srcdata & 7);
5546: uint8 outdata = dstdata ^ bitpos;
5547: storebyte(dstaddr, outdata);
5548:
5549: ZFLAG = !(dstdata & bitpos);
5550: PC+= 2;
5551: }
5552:
5553: void cpu_op_199b(t_ipc *ipc) /* BCHG */ {
5554: /* mask f1f8, bits 0160, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
5555: int srcreg = (ipc->opcode >> 9) & 7;
5556: uint8 srcdata = DATAREG(srcreg);
5557: int dstreg = (ipc->opcode >> 0) & 7;
5558: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
5559: uint8 dstdata = fetchbyte(dstaddr);
5560: uint32 bitpos = 1<<(srcdata & 7);
5561: uint8 outdata = dstdata ^ bitpos;
5562: storebyte(dstaddr, outdata);
5563:
5564: ZFLAG = !(dstdata & bitpos);
5565: PC+= 2;
5566: }
5567:
5568: void cpu_op_200a(t_ipc *ipc) /* BCHG */ {
5569: /* mask f1f8, bits 0168, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
5570: int srcreg = (ipc->opcode >> 9) & 7;
5571: uint8 srcdata = DATAREG(srcreg);
5572: int dstreg = (ipc->opcode >> 0) & 7;
5573: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
5574: uint8 dstdata = fetchbyte(dstaddr);
5575: uint32 bitpos = 1<<(srcdata & 7);
5576: uint8 outdata = dstdata ^ bitpos;
5577: storebyte(dstaddr, outdata);
5578:
5579: ZFLAG = !(dstdata & bitpos);
5580: PC+= 4;
5581: }
5582:
5583: void cpu_op_200b(t_ipc *ipc) /* BCHG */ {
5584: /* mask f1f8, bits 0168, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
5585: int srcreg = (ipc->opcode >> 9) & 7;
5586: uint8 srcdata = DATAREG(srcreg);
5587: int dstreg = (ipc->opcode >> 0) & 7;
5588: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
5589: uint8 dstdata = fetchbyte(dstaddr);
5590: uint32 bitpos = 1<<(srcdata & 7);
5591: uint8 outdata = dstdata ^ bitpos;
5592: storebyte(dstaddr, outdata);
5593:
5594: ZFLAG = !(dstdata & bitpos);
5595: PC+= 4;
5596: }
5597:
5598: void cpu_op_201a(t_ipc *ipc) /* BCHG */ {
5599: /* mask f1f8, bits 0170, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
5600: int srcreg = (ipc->opcode >> 9) & 7;
5601: uint8 srcdata = DATAREG(srcreg);
5602: int dstreg = (ipc->opcode >> 0) & 7;
5603: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
5604: uint8 dstdata = fetchbyte(dstaddr);
5605: uint32 bitpos = 1<<(srcdata & 7);
5606: uint8 outdata = dstdata ^ bitpos;
5607: storebyte(dstaddr, outdata);
5608:
5609: ZFLAG = !(dstdata & bitpos);
5610: PC+= 4;
5611: }
5612:
5613: void cpu_op_201b(t_ipc *ipc) /* BCHG */ {
5614: /* mask f1f8, bits 0170, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
5615: int srcreg = (ipc->opcode >> 9) & 7;
5616: uint8 srcdata = DATAREG(srcreg);
5617: int dstreg = (ipc->opcode >> 0) & 7;
5618: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
5619: uint8 dstdata = fetchbyte(dstaddr);
5620: uint32 bitpos = 1<<(srcdata & 7);
5621: uint8 outdata = dstdata ^ bitpos;
5622: storebyte(dstaddr, outdata);
5623:
5624: ZFLAG = !(dstdata & bitpos);
5625: PC+= 4;
5626: }
5627:
5628: void cpu_op_202a(t_ipc *ipc) /* BCHG */ {
5629: /* mask f1ff, bits 0178, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
5630: int srcreg = (ipc->opcode >> 9) & 7;
5631: uint8 srcdata = DATAREG(srcreg);
5632: uint32 dstaddr = ipc->dst;
5633: uint8 dstdata = fetchbyte(dstaddr);
5634: uint32 bitpos = 1<<(srcdata & 7);
5635: uint8 outdata = dstdata ^ bitpos;
5636: storebyte(dstaddr, outdata);
5637:
5638: ZFLAG = !(dstdata & bitpos);
5639: PC+= 4;
5640: }
5641:
5642: void cpu_op_202b(t_ipc *ipc) /* BCHG */ {
5643: /* mask f1ff, bits 0178, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
5644: int srcreg = (ipc->opcode >> 9) & 7;
5645: uint8 srcdata = DATAREG(srcreg);
5646: uint32 dstaddr = ipc->dst;
5647: uint8 dstdata = fetchbyte(dstaddr);
5648: uint32 bitpos = 1<<(srcdata & 7);
5649: uint8 outdata = dstdata ^ bitpos;
5650: storebyte(dstaddr, outdata);
5651:
5652: ZFLAG = !(dstdata & bitpos);
5653: PC+= 4;
5654: }
5655:
5656: void cpu_op_203a(t_ipc *ipc) /* BCHG */ {
5657: /* mask f1ff, bits 0179, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
5658: int srcreg = (ipc->opcode >> 9) & 7;
5659: uint8 srcdata = DATAREG(srcreg);
5660: uint32 dstaddr = ipc->dst;
5661: uint8 dstdata = fetchbyte(dstaddr);
5662: uint32 bitpos = 1<<(srcdata & 7);
5663: uint8 outdata = dstdata ^ bitpos;
5664: storebyte(dstaddr, outdata);
5665:
5666: ZFLAG = !(dstdata & bitpos);
5667: PC+= 6;
5668: }
5669:
5670: void cpu_op_203b(t_ipc *ipc) /* BCHG */ {
5671: /* mask f1ff, bits 0179, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
5672: int srcreg = (ipc->opcode >> 9) & 7;
5673: uint8 srcdata = DATAREG(srcreg);
5674: uint32 dstaddr = ipc->dst;
5675: uint8 dstdata = fetchbyte(dstaddr);
5676: uint32 bitpos = 1<<(srcdata & 7);
5677: uint8 outdata = dstdata ^ bitpos;
5678: storebyte(dstaddr, outdata);
5679:
5680: ZFLAG = !(dstdata & bitpos);
5681: PC+= 6;
5682: }
5683:
5684: void cpu_op_204a(t_ipc *ipc) /* BCLR */ {
5685: /* mask f1f8, bits 0190, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
5686: int srcreg = (ipc->opcode >> 9) & 7;
5687: uint8 srcdata = DATAREG(srcreg);
5688: int dstreg = (ipc->opcode >> 0) & 7;
5689: uint32 dstaddr = ADDRREG(dstreg);
5690: uint8 dstdata = fetchbyte(dstaddr);
5691: uint32 bitpos = 1<<(srcdata & 7);
5692: uint8 outdata = dstdata & ~bitpos;
5693: storebyte(dstaddr, outdata);
5694:
5695: ZFLAG = !(dstdata & bitpos);
5696: PC+= 2;
5697: }
5698:
5699: void cpu_op_204b(t_ipc *ipc) /* BCLR */ {
5700: /* mask f1f8, bits 0190, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
5701: int srcreg = (ipc->opcode >> 9) & 7;
5702: uint8 srcdata = DATAREG(srcreg);
5703: int dstreg = (ipc->opcode >> 0) & 7;
5704: uint32 dstaddr = ADDRREG(dstreg);
5705: uint8 dstdata = fetchbyte(dstaddr);
5706: uint32 bitpos = 1<<(srcdata & 7);
5707: uint8 outdata = dstdata & ~bitpos;
5708: storebyte(dstaddr, outdata);
5709:
5710: ZFLAG = !(dstdata & bitpos);
5711: PC+= 2;
5712: }
5713:
5714: void cpu_op_205a(t_ipc *ipc) /* BCLR */ {
5715: /* mask f1f8, bits 0198, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
5716: int srcreg = (ipc->opcode >> 9) & 7;
5717: uint8 srcdata = DATAREG(srcreg);
5718: int dstreg = (ipc->opcode >> 0) & 7;
5719: uint32 dstaddr = ADDRREG(dstreg);
5720: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
5721: uint8 dstdata = fetchbyte(dstaddr);
5722: uint32 bitpos = 1<<(srcdata & 7);
5723: uint8 outdata = dstdata & ~bitpos;
5724: storebyte(dstaddr, outdata);
5725:
5726: ZFLAG = !(dstdata & bitpos);
5727: PC+= 2;
5728: }
5729:
5730: void cpu_op_205b(t_ipc *ipc) /* BCLR */ {
5731: /* mask f1f8, bits 0198, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
5732: int srcreg = (ipc->opcode >> 9) & 7;
5733: uint8 srcdata = DATAREG(srcreg);
5734: int dstreg = (ipc->opcode >> 0) & 7;
5735: uint32 dstaddr = ADDRREG(dstreg);
5736: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
5737: uint8 dstdata = fetchbyte(dstaddr);
5738: uint32 bitpos = 1<<(srcdata & 7);
5739: uint8 outdata = dstdata & ~bitpos;
5740: storebyte(dstaddr, outdata);
5741:
5742: ZFLAG = !(dstdata & bitpos);
5743: PC+= 2;
5744: }
5745:
5746: void cpu_op_206a(t_ipc *ipc) /* BCLR */ {
5747: /* mask f1f8, bits 01a0, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
5748: int srcreg = (ipc->opcode >> 9) & 7;
5749: uint8 srcdata = DATAREG(srcreg);
5750: int dstreg = (ipc->opcode >> 0) & 7;
5751: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
5752: uint8 dstdata = fetchbyte(dstaddr);
5753: uint32 bitpos = 1<<(srcdata & 7);
5754: uint8 outdata = dstdata & ~bitpos;
5755: storebyte(dstaddr, outdata);
5756:
5757: ZFLAG = !(dstdata & bitpos);
5758: PC+= 2;
5759: }
5760:
5761: void cpu_op_206b(t_ipc *ipc) /* BCLR */ {
5762: /* mask f1f8, bits 01a0, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
5763: int srcreg = (ipc->opcode >> 9) & 7;
5764: uint8 srcdata = DATAREG(srcreg);
5765: int dstreg = (ipc->opcode >> 0) & 7;
5766: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
5767: uint8 dstdata = fetchbyte(dstaddr);
5768: uint32 bitpos = 1<<(srcdata & 7);
5769: uint8 outdata = dstdata & ~bitpos;
5770: storebyte(dstaddr, outdata);
5771:
5772: ZFLAG = !(dstdata & bitpos);
5773: PC+= 2;
5774: }
5775:
5776: void cpu_op_207a(t_ipc *ipc) /* BCLR */ {
5777: /* mask f1f8, bits 01a8, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
5778: int srcreg = (ipc->opcode >> 9) & 7;
5779: uint8 srcdata = DATAREG(srcreg);
5780: int dstreg = (ipc->opcode >> 0) & 7;
5781: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
5782: uint8 dstdata = fetchbyte(dstaddr);
5783: uint32 bitpos = 1<<(srcdata & 7);
5784: uint8 outdata = dstdata & ~bitpos;
5785: storebyte(dstaddr, outdata);
5786:
5787: ZFLAG = !(dstdata & bitpos);
5788: PC+= 4;
5789: }
5790:
5791: void cpu_op_207b(t_ipc *ipc) /* BCLR */ {
5792: /* mask f1f8, bits 01a8, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
5793: int srcreg = (ipc->opcode >> 9) & 7;
5794: uint8 srcdata = DATAREG(srcreg);
5795: int dstreg = (ipc->opcode >> 0) & 7;
5796: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
5797: uint8 dstdata = fetchbyte(dstaddr);
5798: uint32 bitpos = 1<<(srcdata & 7);
5799: uint8 outdata = dstdata & ~bitpos;
5800: storebyte(dstaddr, outdata);
5801:
5802: ZFLAG = !(dstdata & bitpos);
5803: PC+= 4;
5804: }
5805:
5806: void cpu_op_208a(t_ipc *ipc) /* BCLR */ {
5807: /* mask f1f8, bits 01b0, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
5808: int srcreg = (ipc->opcode >> 9) & 7;
5809: uint8 srcdata = DATAREG(srcreg);
5810: int dstreg = (ipc->opcode >> 0) & 7;
5811: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
5812: uint8 dstdata = fetchbyte(dstaddr);
5813: uint32 bitpos = 1<<(srcdata & 7);
5814: uint8 outdata = dstdata & ~bitpos;
5815: storebyte(dstaddr, outdata);
5816:
5817: ZFLAG = !(dstdata & bitpos);
5818: PC+= 4;
5819: }
5820:
5821: void cpu_op_208b(t_ipc *ipc) /* BCLR */ {
5822: /* mask f1f8, bits 01b0, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
5823: int srcreg = (ipc->opcode >> 9) & 7;
5824: uint8 srcdata = DATAREG(srcreg);
5825: int dstreg = (ipc->opcode >> 0) & 7;
5826: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
5827: uint8 dstdata = fetchbyte(dstaddr);
5828: uint32 bitpos = 1<<(srcdata & 7);
5829: uint8 outdata = dstdata & ~bitpos;
5830: storebyte(dstaddr, outdata);
5831:
5832: ZFLAG = !(dstdata & bitpos);
5833: PC+= 4;
5834: }
5835:
5836: void cpu_op_209a(t_ipc *ipc) /* BCLR */ {
5837: /* mask f1ff, bits 01b8, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
5838: int srcreg = (ipc->opcode >> 9) & 7;
5839: uint8 srcdata = DATAREG(srcreg);
5840: uint32 dstaddr = ipc->dst;
5841: uint8 dstdata = fetchbyte(dstaddr);
5842: uint32 bitpos = 1<<(srcdata & 7);
5843: uint8 outdata = dstdata & ~bitpos;
5844: storebyte(dstaddr, outdata);
5845:
5846: ZFLAG = !(dstdata & bitpos);
5847: PC+= 4;
5848: }
5849:
5850: void cpu_op_209b(t_ipc *ipc) /* BCLR */ {
5851: /* mask f1ff, bits 01b8, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
5852: int srcreg = (ipc->opcode >> 9) & 7;
5853: uint8 srcdata = DATAREG(srcreg);
5854: uint32 dstaddr = ipc->dst;
5855: uint8 dstdata = fetchbyte(dstaddr);
5856: uint32 bitpos = 1<<(srcdata & 7);
5857: uint8 outdata = dstdata & ~bitpos;
5858: storebyte(dstaddr, outdata);
5859:
5860: ZFLAG = !(dstdata & bitpos);
5861: PC+= 4;
5862: }
5863:
5864: void cpu_op_210a(t_ipc *ipc) /* BCLR */ {
5865: /* mask f1ff, bits 01b9, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
5866: int srcreg = (ipc->opcode >> 9) & 7;
5867: uint8 srcdata = DATAREG(srcreg);
5868: uint32 dstaddr = ipc->dst;
5869: uint8 dstdata = fetchbyte(dstaddr);
5870: uint32 bitpos = 1<<(srcdata & 7);
5871: uint8 outdata = dstdata & ~bitpos;
5872: storebyte(dstaddr, outdata);
5873:
5874: ZFLAG = !(dstdata & bitpos);
5875: PC+= 6;
5876: }
5877:
5878: void cpu_op_210b(t_ipc *ipc) /* BCLR */ {
5879: /* mask f1ff, bits 01b9, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
5880: int srcreg = (ipc->opcode >> 9) & 7;
5881: uint8 srcdata = DATAREG(srcreg);
5882: uint32 dstaddr = ipc->dst;
5883: uint8 dstdata = fetchbyte(dstaddr);
5884: uint32 bitpos = 1<<(srcdata & 7);
5885: uint8 outdata = dstdata & ~bitpos;
5886: storebyte(dstaddr, outdata);
5887:
5888: ZFLAG = !(dstdata & bitpos);
5889: PC+= 6;
5890: }
5891:
5892: void cpu_op_211a(t_ipc *ipc) /* BSET */ {
5893: /* mask f1f8, bits 01d0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
5894: int srcreg = (ipc->opcode >> 9) & 7;
5895: uint8 srcdata = DATAREG(srcreg);
5896: int dstreg = (ipc->opcode >> 0) & 7;
5897: uint32 dstaddr = ADDRREG(dstreg);
5898: uint8 dstdata = fetchbyte(dstaddr);
5899: uint32 bitpos = 1<<(srcdata & 7);
5900: uint8 outdata = dstdata | bitpos;
5901: storebyte(dstaddr, outdata);
5902:
5903: ZFLAG = !(dstdata & bitpos);
5904: PC+= 2;
5905: }
5906:
5907: void cpu_op_211b(t_ipc *ipc) /* BSET */ {
5908: /* mask f1f8, bits 01d0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
5909: int srcreg = (ipc->opcode >> 9) & 7;
5910: uint8 srcdata = DATAREG(srcreg);
5911: int dstreg = (ipc->opcode >> 0) & 7;
5912: uint32 dstaddr = ADDRREG(dstreg);
5913: uint8 dstdata = fetchbyte(dstaddr);
5914: uint32 bitpos = 1<<(srcdata & 7);
5915: uint8 outdata = dstdata | bitpos;
5916: storebyte(dstaddr, outdata);
5917:
5918: ZFLAG = !(dstdata & bitpos);
5919: PC+= 2;
5920: }
5921:
5922: void cpu_op_212a(t_ipc *ipc) /* BSET */ {
5923: /* mask f1f8, bits 01d8, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
5924: int srcreg = (ipc->opcode >> 9) & 7;
5925: uint8 srcdata = DATAREG(srcreg);
5926: int dstreg = (ipc->opcode >> 0) & 7;
5927: uint32 dstaddr = ADDRREG(dstreg);
5928: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
5929: uint8 dstdata = fetchbyte(dstaddr);
5930: uint32 bitpos = 1<<(srcdata & 7);
5931: uint8 outdata = dstdata | bitpos;
5932: storebyte(dstaddr, outdata);
5933:
5934: ZFLAG = !(dstdata & bitpos);
5935: PC+= 2;
5936: }
5937:
5938: void cpu_op_212b(t_ipc *ipc) /* BSET */ {
5939: /* mask f1f8, bits 01d8, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
5940: int srcreg = (ipc->opcode >> 9) & 7;
5941: uint8 srcdata = DATAREG(srcreg);
5942: int dstreg = (ipc->opcode >> 0) & 7;
5943: uint32 dstaddr = ADDRREG(dstreg);
5944: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
5945: uint8 dstdata = fetchbyte(dstaddr);
5946: uint32 bitpos = 1<<(srcdata & 7);
5947: uint8 outdata = dstdata | bitpos;
5948: storebyte(dstaddr, outdata);
5949:
5950: ZFLAG = !(dstdata & bitpos);
5951: PC+= 2;
5952: }
5953:
5954: void cpu_op_213a(t_ipc *ipc) /* BSET */ {
5955: /* mask f1f8, bits 01e0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
5956: int srcreg = (ipc->opcode >> 9) & 7;
5957: uint8 srcdata = DATAREG(srcreg);
5958: int dstreg = (ipc->opcode >> 0) & 7;
5959: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
5960: uint8 dstdata = fetchbyte(dstaddr);
5961: uint32 bitpos = 1<<(srcdata & 7);
5962: uint8 outdata = dstdata | bitpos;
5963: storebyte(dstaddr, outdata);
5964:
5965: ZFLAG = !(dstdata & bitpos);
5966: PC+= 2;
5967: }
5968:
5969: void cpu_op_213b(t_ipc *ipc) /* BSET */ {
5970: /* mask f1f8, bits 01e0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
5971: int srcreg = (ipc->opcode >> 9) & 7;
5972: uint8 srcdata = DATAREG(srcreg);
5973: int dstreg = (ipc->opcode >> 0) & 7;
5974: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
5975: uint8 dstdata = fetchbyte(dstaddr);
5976: uint32 bitpos = 1<<(srcdata & 7);
5977: uint8 outdata = dstdata | bitpos;
5978: storebyte(dstaddr, outdata);
5979:
5980: ZFLAG = !(dstdata & bitpos);
5981: PC+= 2;
5982: }
5983:
5984: void cpu_op_214a(t_ipc *ipc) /* BSET */ {
5985: /* mask f1f8, bits 01e8, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
5986: int srcreg = (ipc->opcode >> 9) & 7;
5987: uint8 srcdata = DATAREG(srcreg);
5988: int dstreg = (ipc->opcode >> 0) & 7;
5989: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
5990: uint8 dstdata = fetchbyte(dstaddr);
5991: uint32 bitpos = 1<<(srcdata & 7);
5992: uint8 outdata = dstdata | bitpos;
5993: storebyte(dstaddr, outdata);
5994:
5995: ZFLAG = !(dstdata & bitpos);
5996: PC+= 4;
5997: }
5998:
5999: void cpu_op_214b(t_ipc *ipc) /* BSET */ {
6000: /* mask f1f8, bits 01e8, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
6001: int srcreg = (ipc->opcode >> 9) & 7;
6002: uint8 srcdata = DATAREG(srcreg);
6003: int dstreg = (ipc->opcode >> 0) & 7;
6004: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
6005: uint8 dstdata = fetchbyte(dstaddr);
6006: uint32 bitpos = 1<<(srcdata & 7);
6007: uint8 outdata = dstdata | bitpos;
6008: storebyte(dstaddr, outdata);
6009:
6010: ZFLAG = !(dstdata & bitpos);
6011: PC+= 4;
6012: }
6013:
6014: void cpu_op_215a(t_ipc *ipc) /* BSET */ {
6015: /* mask f1f8, bits 01f0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
6016: int srcreg = (ipc->opcode >> 9) & 7;
6017: uint8 srcdata = DATAREG(srcreg);
6018: int dstreg = (ipc->opcode >> 0) & 7;
6019: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
6020: uint8 dstdata = fetchbyte(dstaddr);
6021: uint32 bitpos = 1<<(srcdata & 7);
6022: uint8 outdata = dstdata | bitpos;
6023: storebyte(dstaddr, outdata);
6024:
6025: ZFLAG = !(dstdata & bitpos);
6026: PC+= 4;
6027: }
6028:
6029: void cpu_op_215b(t_ipc *ipc) /* BSET */ {
6030: /* mask f1f8, bits 01f0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
6031: int srcreg = (ipc->opcode >> 9) & 7;
6032: uint8 srcdata = DATAREG(srcreg);
6033: int dstreg = (ipc->opcode >> 0) & 7;
6034: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
6035: uint8 dstdata = fetchbyte(dstaddr);
6036: uint32 bitpos = 1<<(srcdata & 7);
6037: uint8 outdata = dstdata | bitpos;
6038: storebyte(dstaddr, outdata);
6039:
6040: ZFLAG = !(dstdata & bitpos);
6041: PC+= 4;
6042: }
6043:
6044: void cpu_op_216a(t_ipc *ipc) /* BSET */ {
6045: /* mask f1ff, bits 01f8, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
6046: int srcreg = (ipc->opcode >> 9) & 7;
6047: uint8 srcdata = DATAREG(srcreg);
6048: uint32 dstaddr = ipc->dst;
6049: uint8 dstdata = fetchbyte(dstaddr);
6050: uint32 bitpos = 1<<(srcdata & 7);
6051: uint8 outdata = dstdata | bitpos;
6052: storebyte(dstaddr, outdata);
6053:
6054: ZFLAG = !(dstdata & bitpos);
6055: PC+= 4;
6056: }
6057:
6058: void cpu_op_216b(t_ipc *ipc) /* BSET */ {
6059: /* mask f1ff, bits 01f8, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
6060: int srcreg = (ipc->opcode >> 9) & 7;
6061: uint8 srcdata = DATAREG(srcreg);
6062: uint32 dstaddr = ipc->dst;
6063: uint8 dstdata = fetchbyte(dstaddr);
6064: uint32 bitpos = 1<<(srcdata & 7);
6065: uint8 outdata = dstdata | bitpos;
6066: storebyte(dstaddr, outdata);
6067:
6068: ZFLAG = !(dstdata & bitpos);
6069: PC+= 4;
6070: }
6071:
6072: void cpu_op_217a(t_ipc *ipc) /* BSET */ {
6073: /* mask f1ff, bits 01f9, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
6074: int srcreg = (ipc->opcode >> 9) & 7;
6075: uint8 srcdata = DATAREG(srcreg);
6076: uint32 dstaddr = ipc->dst;
6077: uint8 dstdata = fetchbyte(dstaddr);
6078: uint32 bitpos = 1<<(srcdata & 7);
6079: uint8 outdata = dstdata | bitpos;
6080: storebyte(dstaddr, outdata);
6081:
6082: ZFLAG = !(dstdata & bitpos);
6083: PC+= 6;
6084: }
6085:
6086: void cpu_op_217b(t_ipc *ipc) /* BSET */ {
6087: /* mask f1ff, bits 01f9, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 1, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
6088: int srcreg = (ipc->opcode >> 9) & 7;
6089: uint8 srcdata = DATAREG(srcreg);
6090: uint32 dstaddr = ipc->dst;
6091: uint8 dstdata = fetchbyte(dstaddr);
6092: uint32 bitpos = 1<<(srcdata & 7);
6093: uint8 outdata = dstdata | bitpos;
6094: storebyte(dstaddr, outdata);
6095:
6096: ZFLAG = !(dstdata & bitpos);
6097: PC+= 6;
6098: }
6099:
6100: void cpu_op_218a(t_ipc *ipc) /* BTST */ {
6101: /* mask f1f8, bits 0100, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 0, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
6102: int srcreg = (ipc->opcode >> 9) & 7;
6103: uint32 srcdata = DATAREG(srcreg);
6104: int dstreg = (ipc->opcode >> 0) & 7;
6105: uint32 dstdata = DATAREG(dstreg);
6106: uint32 bitpos = 1<<(srcdata & 31);
6107:
6108: ZFLAG = !(dstdata & bitpos);
6109: PC+= 2;
6110: }
6111:
6112: void cpu_op_218b(t_ipc *ipc) /* BTST */ {
6113: /* mask f1f8, bits 0100, mnemonic 17, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 0, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
6114: int srcreg = (ipc->opcode >> 9) & 7;
6115: uint32 srcdata = DATAREG(srcreg);
6116: int dstreg = (ipc->opcode >> 0) & 7;
6117: uint32 dstdata = DATAREG(dstreg);
6118: uint32 bitpos = 1<<(srcdata & 31);
6119:
6120: ZFLAG = !(dstdata & bitpos);
6121: PC+= 2;
6122: }
6123:
6124: void cpu_op_219a(t_ipc *ipc) /* BCHG */ {
6125: /* mask f1f8, bits 0140, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 0, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
6126: int srcreg = (ipc->opcode >> 9) & 7;
6127: uint32 srcdata = DATAREG(srcreg);
6128: int dstreg = (ipc->opcode >> 0) & 7;
6129: uint32 dstdata = DATAREG(dstreg);
6130: uint32 bitpos = 1<<(srcdata & 31);
6131: uint32 outdata = dstdata ^ bitpos;
6132: DATAREG(dstreg) = outdata;
6133:
6134: ZFLAG = !(dstdata & bitpos);
6135: PC+= 2;
6136: }
6137:
6138: void cpu_op_219b(t_ipc *ipc) /* BCHG */ {
6139: /* mask f1f8, bits 0140, mnemonic 18, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 0, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
6140: int srcreg = (ipc->opcode >> 9) & 7;
6141: uint32 srcdata = DATAREG(srcreg);
6142: int dstreg = (ipc->opcode >> 0) & 7;
6143: uint32 dstdata = DATAREG(dstreg);
6144: uint32 bitpos = 1<<(srcdata & 31);
6145: uint32 outdata = dstdata ^ bitpos;
6146: DATAREG(dstreg) = outdata;
6147:
6148: ZFLAG = !(dstdata & bitpos);
6149: PC+= 2;
6150: }
6151:
6152: void cpu_op_220a(t_ipc *ipc) /* BCLR */ {
6153: /* mask f1f8, bits 0180, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 0, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
6154: int srcreg = (ipc->opcode >> 9) & 7;
6155: uint32 srcdata = DATAREG(srcreg);
6156: int dstreg = (ipc->opcode >> 0) & 7;
6157: uint32 dstdata = DATAREG(dstreg);
6158: uint32 bitpos = 1<<(srcdata & 31);
6159: uint32 outdata = dstdata & ~bitpos;
6160: DATAREG(dstreg) = outdata;
6161:
6162: ZFLAG = !(dstdata & bitpos);
6163: PC+= 2;
6164: }
6165:
6166: void cpu_op_220b(t_ipc *ipc) /* BCLR */ {
6167: /* mask f1f8, bits 0180, mnemonic 19, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 0, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
6168: int srcreg = (ipc->opcode >> 9) & 7;
6169: uint32 srcdata = DATAREG(srcreg);
6170: int dstreg = (ipc->opcode >> 0) & 7;
6171: uint32 dstdata = DATAREG(dstreg);
6172: uint32 bitpos = 1<<(srcdata & 31);
6173: uint32 outdata = dstdata & ~bitpos;
6174: DATAREG(dstreg) = outdata;
6175:
6176: ZFLAG = !(dstdata & bitpos);
6177: PC+= 2;
6178: }
6179:
6180: void cpu_op_221a(t_ipc *ipc) /* BSET */ {
6181: /* mask f1f8, bits 01c0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 0, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
6182: int srcreg = (ipc->opcode >> 9) & 7;
6183: uint32 srcdata = DATAREG(srcreg);
6184: int dstreg = (ipc->opcode >> 0) & 7;
6185: uint32 dstdata = DATAREG(dstreg);
6186: uint32 bitpos = 1<<(srcdata & 31);
6187: uint32 outdata = dstdata | bitpos;
6188: DATAREG(dstreg) = outdata;
6189:
6190: ZFLAG = !(dstdata & bitpos);
6191: PC+= 2;
6192: }
6193:
6194: void cpu_op_221b(t_ipc *ipc) /* BSET */ {
6195: /* mask f1f8, bits 01c0, mnemonic 20, priv 0, endblk 0, imm_notzero 0, used 0 set 4, size 3, stype 0, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
6196: int srcreg = (ipc->opcode >> 9) & 7;
6197: uint32 srcdata = DATAREG(srcreg);
6198: int dstreg = (ipc->opcode >> 0) & 7;
6199: uint32 dstdata = DATAREG(dstreg);
6200: uint32 bitpos = 1<<(srcdata & 31);
6201: uint32 outdata = dstdata | bitpos;
6202: DATAREG(dstreg) = outdata;
6203:
6204: ZFLAG = !(dstdata & bitpos);
6205: PC+= 2;
6206: }
6207:
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