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1.1 root 1: /*****************************************************************************/
2: /* Generator - Sega Genesis emulation - (c) James Ponder 1997-1998 */
3: /*****************************************************************************/
4: /* */
5: /* cpu68k-1.c */
6: /* */
7: /*****************************************************************************/
8:
9: #include "generator.h"
10: #include "cpu68k.h"
11: #include "mem68k.h"
12: #include "reg68k.h"
13:
14: #include "cpu68k-inline.h"
15:
16: #include <stdio.h>
17:
18: void cpu_op_222a(t_ipc *ipc) /* MOVE */ {
19: /* mask f1f8, bits 1000, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
20: int srcreg = (ipc->opcode >> 0) & 7;
21: uint8 srcdata = DATAREG(srcreg);
22: int dstreg = (ipc->opcode >> 9) & 7;
23: uint8 outdata = srcdata;
24:
25: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
26: PC+= 2;
27: }
28:
29: void cpu_op_222b(t_ipc *ipc) /* MOVE */ {
30: /* mask f1f8, bits 1000, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
31: int srcreg = (ipc->opcode >> 0) & 7;
32: uint8 srcdata = DATAREG(srcreg);
33: int dstreg = (ipc->opcode >> 9) & 7;
34: uint8 outdata = srcdata;
35:
36: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
37:
38: VFLAG = 0;
39: CFLAG = 0;
40: NFLAG = ((sint8)outdata) < 0;
41: ZFLAG = !outdata;
42: PC+= 2;
43: }
44:
45: void cpu_op_223a(t_ipc *ipc) /* MOVE */ {
46: /* mask f1f8, bits 1080, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
47: int srcreg = (ipc->opcode >> 0) & 7;
48: uint8 srcdata = DATAREG(srcreg);
49: int dstreg = (ipc->opcode >> 9) & 7;
50: uint32 dstaddr = ADDRREG(dstreg);
51: uint8 outdata = srcdata;
52:
53: storebyte(dstaddr, outdata);
54: PC+= 2;
55: }
56:
57: void cpu_op_223b(t_ipc *ipc) /* MOVE */ {
58: /* mask f1f8, bits 1080, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
59: int srcreg = (ipc->opcode >> 0) & 7;
60: uint8 srcdata = DATAREG(srcreg);
61: int dstreg = (ipc->opcode >> 9) & 7;
62: uint32 dstaddr = ADDRREG(dstreg);
63: uint8 outdata = srcdata;
64:
65: storebyte(dstaddr, outdata);
66:
67: VFLAG = 0;
68: CFLAG = 0;
69: NFLAG = ((sint8)outdata) < 0;
70: ZFLAG = !outdata;
71: PC+= 2;
72: }
73:
74: void cpu_op_224a(t_ipc *ipc) /* MOVE */ {
75: /* mask f1f8, bits 10c0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
76: int srcreg = (ipc->opcode >> 0) & 7;
77: uint8 srcdata = DATAREG(srcreg);
78: int dstreg = (ipc->opcode >> 9) & 7;
79: uint32 dstaddr = ADDRREG(dstreg);
80: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
81: uint8 outdata = srcdata;
82:
83: storebyte(dstaddr, outdata);
84: PC+= 2;
85: }
86:
87: void cpu_op_224b(t_ipc *ipc) /* MOVE */ {
88: /* mask f1f8, bits 10c0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
89: int srcreg = (ipc->opcode >> 0) & 7;
90: uint8 srcdata = DATAREG(srcreg);
91: int dstreg = (ipc->opcode >> 9) & 7;
92: uint32 dstaddr = ADDRREG(dstreg);
93: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
94: uint8 outdata = srcdata;
95:
96: storebyte(dstaddr, outdata);
97:
98: VFLAG = 0;
99: CFLAG = 0;
100: NFLAG = ((sint8)outdata) < 0;
101: ZFLAG = !outdata;
102: PC+= 2;
103: }
104:
105: void cpu_op_225a(t_ipc *ipc) /* MOVE */ {
106: /* mask f1f8, bits 1100, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
107: int srcreg = (ipc->opcode >> 0) & 7;
108: uint8 srcdata = DATAREG(srcreg);
109: int dstreg = (ipc->opcode >> 9) & 7;
110: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
111: uint8 outdata = srcdata;
112:
113: storebyte(dstaddr, outdata);
114: PC+= 2;
115: }
116:
117: void cpu_op_225b(t_ipc *ipc) /* MOVE */ {
118: /* mask f1f8, bits 1100, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
119: int srcreg = (ipc->opcode >> 0) & 7;
120: uint8 srcdata = DATAREG(srcreg);
121: int dstreg = (ipc->opcode >> 9) & 7;
122: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
123: uint8 outdata = srcdata;
124:
125: storebyte(dstaddr, outdata);
126:
127: VFLAG = 0;
128: CFLAG = 0;
129: NFLAG = ((sint8)outdata) < 0;
130: ZFLAG = !outdata;
131: PC+= 2;
132: }
133:
134: void cpu_op_226a(t_ipc *ipc) /* MOVE */ {
135: /* mask f1f8, bits 1140, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
136: int srcreg = (ipc->opcode >> 0) & 7;
137: uint8 srcdata = DATAREG(srcreg);
138: int dstreg = (ipc->opcode >> 9) & 7;
139: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
140: uint8 outdata = srcdata;
141:
142: storebyte(dstaddr, outdata);
143: PC+= 4;
144: }
145:
146: void cpu_op_226b(t_ipc *ipc) /* MOVE */ {
147: /* mask f1f8, bits 1140, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
148: int srcreg = (ipc->opcode >> 0) & 7;
149: uint8 srcdata = DATAREG(srcreg);
150: int dstreg = (ipc->opcode >> 9) & 7;
151: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
152: uint8 outdata = srcdata;
153:
154: storebyte(dstaddr, outdata);
155:
156: VFLAG = 0;
157: CFLAG = 0;
158: NFLAG = ((sint8)outdata) < 0;
159: ZFLAG = !outdata;
160: PC+= 4;
161: }
162:
163: void cpu_op_227a(t_ipc *ipc) /* MOVE */ {
164: /* mask f1f8, bits 1180, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
165: int srcreg = (ipc->opcode >> 0) & 7;
166: uint8 srcdata = DATAREG(srcreg);
167: int dstreg = (ipc->opcode >> 9) & 7;
168: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
169: uint8 outdata = srcdata;
170:
171: storebyte(dstaddr, outdata);
172: PC+= 4;
173: }
174:
175: void cpu_op_227b(t_ipc *ipc) /* MOVE */ {
176: /* mask f1f8, bits 1180, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
177: int srcreg = (ipc->opcode >> 0) & 7;
178: uint8 srcdata = DATAREG(srcreg);
179: int dstreg = (ipc->opcode >> 9) & 7;
180: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
181: uint8 outdata = srcdata;
182:
183: storebyte(dstaddr, outdata);
184:
185: VFLAG = 0;
186: CFLAG = 0;
187: NFLAG = ((sint8)outdata) < 0;
188: ZFLAG = !outdata;
189: PC+= 4;
190: }
191:
192: void cpu_op_228a(t_ipc *ipc) /* MOVE */ {
193: /* mask fff8, bits 11c0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
194: int srcreg = (ipc->opcode >> 0) & 7;
195: uint8 srcdata = DATAREG(srcreg);
196: uint32 dstaddr = ipc->dst;
197: uint8 outdata = srcdata;
198:
199: storebyte(dstaddr, outdata);
200: PC+= 4;
201: }
202:
203: void cpu_op_228b(t_ipc *ipc) /* MOVE */ {
204: /* mask fff8, bits 11c0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
205: int srcreg = (ipc->opcode >> 0) & 7;
206: uint8 srcdata = DATAREG(srcreg);
207: uint32 dstaddr = ipc->dst;
208: uint8 outdata = srcdata;
209:
210: storebyte(dstaddr, outdata);
211:
212: VFLAG = 0;
213: CFLAG = 0;
214: NFLAG = ((sint8)outdata) < 0;
215: ZFLAG = !outdata;
216: PC+= 4;
217: }
218:
219: void cpu_op_229a(t_ipc *ipc) /* MOVE */ {
220: /* mask fff8, bits 13c0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
221: int srcreg = (ipc->opcode >> 0) & 7;
222: uint8 srcdata = DATAREG(srcreg);
223: uint32 dstaddr = ipc->dst;
224: uint8 outdata = srcdata;
225:
226: storebyte(dstaddr, outdata);
227: PC+= 6;
228: }
229:
230: void cpu_op_229b(t_ipc *ipc) /* MOVE */ {
231: /* mask fff8, bits 13c0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
232: int srcreg = (ipc->opcode >> 0) & 7;
233: uint8 srcdata = DATAREG(srcreg);
234: uint32 dstaddr = ipc->dst;
235: uint8 outdata = srcdata;
236:
237: storebyte(dstaddr, outdata);
238:
239: VFLAG = 0;
240: CFLAG = 0;
241: NFLAG = ((sint8)outdata) < 0;
242: ZFLAG = !outdata;
243: PC+= 6;
244: }
245:
246: void cpu_op_230a(t_ipc *ipc) /* MOVE */ {
247: /* mask f1f8, bits 1008, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
248: int srcreg = (ipc->opcode >> 0) & 7;
249: uint8 srcdata = ADDRREG(srcreg);
250: int dstreg = (ipc->opcode >> 9) & 7;
251: uint8 outdata = srcdata;
252:
253: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
254: PC+= 2;
255: }
256:
257: void cpu_op_230b(t_ipc *ipc) /* MOVE */ {
258: /* mask f1f8, bits 1008, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
259: int srcreg = (ipc->opcode >> 0) & 7;
260: uint8 srcdata = ADDRREG(srcreg);
261: int dstreg = (ipc->opcode >> 9) & 7;
262: uint8 outdata = srcdata;
263:
264: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
265:
266: VFLAG = 0;
267: CFLAG = 0;
268: NFLAG = ((sint8)outdata) < 0;
269: ZFLAG = !outdata;
270: PC+= 2;
271: }
272:
273: void cpu_op_231a(t_ipc *ipc) /* MOVE */ {
274: /* mask f1f8, bits 1088, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
275: int srcreg = (ipc->opcode >> 0) & 7;
276: uint8 srcdata = ADDRREG(srcreg);
277: int dstreg = (ipc->opcode >> 9) & 7;
278: uint32 dstaddr = ADDRREG(dstreg);
279: uint8 outdata = srcdata;
280:
281: storebyte(dstaddr, outdata);
282: PC+= 2;
283: }
284:
285: void cpu_op_231b(t_ipc *ipc) /* MOVE */ {
286: /* mask f1f8, bits 1088, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
287: int srcreg = (ipc->opcode >> 0) & 7;
288: uint8 srcdata = ADDRREG(srcreg);
289: int dstreg = (ipc->opcode >> 9) & 7;
290: uint32 dstaddr = ADDRREG(dstreg);
291: uint8 outdata = srcdata;
292:
293: storebyte(dstaddr, outdata);
294:
295: VFLAG = 0;
296: CFLAG = 0;
297: NFLAG = ((sint8)outdata) < 0;
298: ZFLAG = !outdata;
299: PC+= 2;
300: }
301:
302: void cpu_op_232a(t_ipc *ipc) /* MOVE */ {
303: /* mask f1f8, bits 10c8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
304: int srcreg = (ipc->opcode >> 0) & 7;
305: uint8 srcdata = ADDRREG(srcreg);
306: int dstreg = (ipc->opcode >> 9) & 7;
307: uint32 dstaddr = ADDRREG(dstreg);
308: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
309: uint8 outdata = srcdata;
310:
311: storebyte(dstaddr, outdata);
312: PC+= 2;
313: }
314:
315: void cpu_op_232b(t_ipc *ipc) /* MOVE */ {
316: /* mask f1f8, bits 10c8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
317: int srcreg = (ipc->opcode >> 0) & 7;
318: uint8 srcdata = ADDRREG(srcreg);
319: int dstreg = (ipc->opcode >> 9) & 7;
320: uint32 dstaddr = ADDRREG(dstreg);
321: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
322: uint8 outdata = srcdata;
323:
324: storebyte(dstaddr, outdata);
325:
326: VFLAG = 0;
327: CFLAG = 0;
328: NFLAG = ((sint8)outdata) < 0;
329: ZFLAG = !outdata;
330: PC+= 2;
331: }
332:
333: void cpu_op_233a(t_ipc *ipc) /* MOVE */ {
334: /* mask f1f8, bits 1108, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
335: int srcreg = (ipc->opcode >> 0) & 7;
336: uint8 srcdata = ADDRREG(srcreg);
337: int dstreg = (ipc->opcode >> 9) & 7;
338: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
339: uint8 outdata = srcdata;
340:
341: storebyte(dstaddr, outdata);
342: PC+= 2;
343: }
344:
345: void cpu_op_233b(t_ipc *ipc) /* MOVE */ {
346: /* mask f1f8, bits 1108, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
347: int srcreg = (ipc->opcode >> 0) & 7;
348: uint8 srcdata = ADDRREG(srcreg);
349: int dstreg = (ipc->opcode >> 9) & 7;
350: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
351: uint8 outdata = srcdata;
352:
353: storebyte(dstaddr, outdata);
354:
355: VFLAG = 0;
356: CFLAG = 0;
357: NFLAG = ((sint8)outdata) < 0;
358: ZFLAG = !outdata;
359: PC+= 2;
360: }
361:
362: void cpu_op_234a(t_ipc *ipc) /* MOVE */ {
363: /* mask f1f8, bits 1148, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
364: int srcreg = (ipc->opcode >> 0) & 7;
365: uint8 srcdata = ADDRREG(srcreg);
366: int dstreg = (ipc->opcode >> 9) & 7;
367: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
368: uint8 outdata = srcdata;
369:
370: storebyte(dstaddr, outdata);
371: PC+= 4;
372: }
373:
374: void cpu_op_234b(t_ipc *ipc) /* MOVE */ {
375: /* mask f1f8, bits 1148, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
376: int srcreg = (ipc->opcode >> 0) & 7;
377: uint8 srcdata = ADDRREG(srcreg);
378: int dstreg = (ipc->opcode >> 9) & 7;
379: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
380: uint8 outdata = srcdata;
381:
382: storebyte(dstaddr, outdata);
383:
384: VFLAG = 0;
385: CFLAG = 0;
386: NFLAG = ((sint8)outdata) < 0;
387: ZFLAG = !outdata;
388: PC+= 4;
389: }
390:
391: void cpu_op_235a(t_ipc *ipc) /* MOVE */ {
392: /* mask f1f8, bits 1188, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
393: int srcreg = (ipc->opcode >> 0) & 7;
394: uint8 srcdata = ADDRREG(srcreg);
395: int dstreg = (ipc->opcode >> 9) & 7;
396: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
397: uint8 outdata = srcdata;
398:
399: storebyte(dstaddr, outdata);
400: PC+= 4;
401: }
402:
403: void cpu_op_235b(t_ipc *ipc) /* MOVE */ {
404: /* mask f1f8, bits 1188, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
405: int srcreg = (ipc->opcode >> 0) & 7;
406: uint8 srcdata = ADDRREG(srcreg);
407: int dstreg = (ipc->opcode >> 9) & 7;
408: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
409: uint8 outdata = srcdata;
410:
411: storebyte(dstaddr, outdata);
412:
413: VFLAG = 0;
414: CFLAG = 0;
415: NFLAG = ((sint8)outdata) < 0;
416: ZFLAG = !outdata;
417: PC+= 4;
418: }
419:
420: void cpu_op_236a(t_ipc *ipc) /* MOVE */ {
421: /* mask fff8, bits 11c8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
422: int srcreg = (ipc->opcode >> 0) & 7;
423: uint8 srcdata = ADDRREG(srcreg);
424: uint32 dstaddr = ipc->dst;
425: uint8 outdata = srcdata;
426:
427: storebyte(dstaddr, outdata);
428: PC+= 4;
429: }
430:
431: void cpu_op_236b(t_ipc *ipc) /* MOVE */ {
432: /* mask fff8, bits 11c8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
433: int srcreg = (ipc->opcode >> 0) & 7;
434: uint8 srcdata = ADDRREG(srcreg);
435: uint32 dstaddr = ipc->dst;
436: uint8 outdata = srcdata;
437:
438: storebyte(dstaddr, outdata);
439:
440: VFLAG = 0;
441: CFLAG = 0;
442: NFLAG = ((sint8)outdata) < 0;
443: ZFLAG = !outdata;
444: PC+= 4;
445: }
446:
447: void cpu_op_237a(t_ipc *ipc) /* MOVE */ {
448: /* mask fff8, bits 13c8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
449: int srcreg = (ipc->opcode >> 0) & 7;
450: uint8 srcdata = ADDRREG(srcreg);
451: uint32 dstaddr = ipc->dst;
452: uint8 outdata = srcdata;
453:
454: storebyte(dstaddr, outdata);
455: PC+= 6;
456: }
457:
458: void cpu_op_237b(t_ipc *ipc) /* MOVE */ {
459: /* mask fff8, bits 13c8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 1, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
460: int srcreg = (ipc->opcode >> 0) & 7;
461: uint8 srcdata = ADDRREG(srcreg);
462: uint32 dstaddr = ipc->dst;
463: uint8 outdata = srcdata;
464:
465: storebyte(dstaddr, outdata);
466:
467: VFLAG = 0;
468: CFLAG = 0;
469: NFLAG = ((sint8)outdata) < 0;
470: ZFLAG = !outdata;
471: PC+= 6;
472: }
473:
474: void cpu_op_238a(t_ipc *ipc) /* MOVE */ {
475: /* mask f1f8, bits 1010, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
476: int srcreg = (ipc->opcode >> 0) & 7;
477: uint32 srcaddr = ADDRREG(srcreg);
478: uint8 srcdata = fetchbyte(srcaddr);
479: int dstreg = (ipc->opcode >> 9) & 7;
480: uint8 outdata = srcdata;
481:
482: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
483: PC+= 2;
484: }
485:
486: void cpu_op_238b(t_ipc *ipc) /* MOVE */ {
487: /* mask f1f8, bits 1010, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
488: int srcreg = (ipc->opcode >> 0) & 7;
489: uint32 srcaddr = ADDRREG(srcreg);
490: uint8 srcdata = fetchbyte(srcaddr);
491: int dstreg = (ipc->opcode >> 9) & 7;
492: uint8 outdata = srcdata;
493:
494: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
495:
496: VFLAG = 0;
497: CFLAG = 0;
498: NFLAG = ((sint8)outdata) < 0;
499: ZFLAG = !outdata;
500: PC+= 2;
501: }
502:
503: void cpu_op_239a(t_ipc *ipc) /* MOVE */ {
504: /* mask f1f8, bits 1090, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
505: int srcreg = (ipc->opcode >> 0) & 7;
506: uint32 srcaddr = ADDRREG(srcreg);
507: uint8 srcdata = fetchbyte(srcaddr);
508: int dstreg = (ipc->opcode >> 9) & 7;
509: uint32 dstaddr = ADDRREG(dstreg);
510: uint8 outdata = srcdata;
511:
512: storebyte(dstaddr, outdata);
513: PC+= 2;
514: }
515:
516: void cpu_op_239b(t_ipc *ipc) /* MOVE */ {
517: /* mask f1f8, bits 1090, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
518: int srcreg = (ipc->opcode >> 0) & 7;
519: uint32 srcaddr = ADDRREG(srcreg);
520: uint8 srcdata = fetchbyte(srcaddr);
521: int dstreg = (ipc->opcode >> 9) & 7;
522: uint32 dstaddr = ADDRREG(dstreg);
523: uint8 outdata = srcdata;
524:
525: storebyte(dstaddr, outdata);
526:
527: VFLAG = 0;
528: CFLAG = 0;
529: NFLAG = ((sint8)outdata) < 0;
530: ZFLAG = !outdata;
531: PC+= 2;
532: }
533:
534: void cpu_op_240a(t_ipc *ipc) /* MOVE */ {
535: /* mask f1f8, bits 10d0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
536: int srcreg = (ipc->opcode >> 0) & 7;
537: uint32 srcaddr = ADDRREG(srcreg);
538: uint8 srcdata = fetchbyte(srcaddr);
539: int dstreg = (ipc->opcode >> 9) & 7;
540: uint32 dstaddr = ADDRREG(dstreg);
541: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
542: uint8 outdata = srcdata;
543:
544: storebyte(dstaddr, outdata);
545: PC+= 2;
546: }
547:
548: void cpu_op_240b(t_ipc *ipc) /* MOVE */ {
549: /* mask f1f8, bits 10d0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
550: int srcreg = (ipc->opcode >> 0) & 7;
551: uint32 srcaddr = ADDRREG(srcreg);
552: uint8 srcdata = fetchbyte(srcaddr);
553: int dstreg = (ipc->opcode >> 9) & 7;
554: uint32 dstaddr = ADDRREG(dstreg);
555: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
556: uint8 outdata = srcdata;
557:
558: storebyte(dstaddr, outdata);
559:
560: VFLAG = 0;
561: CFLAG = 0;
562: NFLAG = ((sint8)outdata) < 0;
563: ZFLAG = !outdata;
564: PC+= 2;
565: }
566:
567: void cpu_op_241a(t_ipc *ipc) /* MOVE */ {
568: /* mask f1f8, bits 1110, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
569: int srcreg = (ipc->opcode >> 0) & 7;
570: uint32 srcaddr = ADDRREG(srcreg);
571: uint8 srcdata = fetchbyte(srcaddr);
572: int dstreg = (ipc->opcode >> 9) & 7;
573: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
574: uint8 outdata = srcdata;
575:
576: storebyte(dstaddr, outdata);
577: PC+= 2;
578: }
579:
580: void cpu_op_241b(t_ipc *ipc) /* MOVE */ {
581: /* mask f1f8, bits 1110, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
582: int srcreg = (ipc->opcode >> 0) & 7;
583: uint32 srcaddr = ADDRREG(srcreg);
584: uint8 srcdata = fetchbyte(srcaddr);
585: int dstreg = (ipc->opcode >> 9) & 7;
586: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
587: uint8 outdata = srcdata;
588:
589: storebyte(dstaddr, outdata);
590:
591: VFLAG = 0;
592: CFLAG = 0;
593: NFLAG = ((sint8)outdata) < 0;
594: ZFLAG = !outdata;
595: PC+= 2;
596: }
597:
598: void cpu_op_242a(t_ipc *ipc) /* MOVE */ {
599: /* mask f1f8, bits 1150, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
600: int srcreg = (ipc->opcode >> 0) & 7;
601: uint32 srcaddr = ADDRREG(srcreg);
602: uint8 srcdata = fetchbyte(srcaddr);
603: int dstreg = (ipc->opcode >> 9) & 7;
604: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
605: uint8 outdata = srcdata;
606:
607: storebyte(dstaddr, outdata);
608: PC+= 4;
609: }
610:
611: void cpu_op_242b(t_ipc *ipc) /* MOVE */ {
612: /* mask f1f8, bits 1150, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
613: int srcreg = (ipc->opcode >> 0) & 7;
614: uint32 srcaddr = ADDRREG(srcreg);
615: uint8 srcdata = fetchbyte(srcaddr);
616: int dstreg = (ipc->opcode >> 9) & 7;
617: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
618: uint8 outdata = srcdata;
619:
620: storebyte(dstaddr, outdata);
621:
622: VFLAG = 0;
623: CFLAG = 0;
624: NFLAG = ((sint8)outdata) < 0;
625: ZFLAG = !outdata;
626: PC+= 4;
627: }
628:
629: void cpu_op_243a(t_ipc *ipc) /* MOVE */ {
630: /* mask f1f8, bits 1190, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
631: int srcreg = (ipc->opcode >> 0) & 7;
632: uint32 srcaddr = ADDRREG(srcreg);
633: uint8 srcdata = fetchbyte(srcaddr);
634: int dstreg = (ipc->opcode >> 9) & 7;
635: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
636: uint8 outdata = srcdata;
637:
638: storebyte(dstaddr, outdata);
639: PC+= 4;
640: }
641:
642: void cpu_op_243b(t_ipc *ipc) /* MOVE */ {
643: /* mask f1f8, bits 1190, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
644: int srcreg = (ipc->opcode >> 0) & 7;
645: uint32 srcaddr = ADDRREG(srcreg);
646: uint8 srcdata = fetchbyte(srcaddr);
647: int dstreg = (ipc->opcode >> 9) & 7;
648: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
649: uint8 outdata = srcdata;
650:
651: storebyte(dstaddr, outdata);
652:
653: VFLAG = 0;
654: CFLAG = 0;
655: NFLAG = ((sint8)outdata) < 0;
656: ZFLAG = !outdata;
657: PC+= 4;
658: }
659:
660: void cpu_op_244a(t_ipc *ipc) /* MOVE */ {
661: /* mask fff8, bits 11d0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
662: int srcreg = (ipc->opcode >> 0) & 7;
663: uint32 srcaddr = ADDRREG(srcreg);
664: uint8 srcdata = fetchbyte(srcaddr);
665: uint32 dstaddr = ipc->dst;
666: uint8 outdata = srcdata;
667:
668: storebyte(dstaddr, outdata);
669: PC+= 4;
670: }
671:
672: void cpu_op_244b(t_ipc *ipc) /* MOVE */ {
673: /* mask fff8, bits 11d0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
674: int srcreg = (ipc->opcode >> 0) & 7;
675: uint32 srcaddr = ADDRREG(srcreg);
676: uint8 srcdata = fetchbyte(srcaddr);
677: uint32 dstaddr = ipc->dst;
678: uint8 outdata = srcdata;
679:
680: storebyte(dstaddr, outdata);
681:
682: VFLAG = 0;
683: CFLAG = 0;
684: NFLAG = ((sint8)outdata) < 0;
685: ZFLAG = !outdata;
686: PC+= 4;
687: }
688:
689: void cpu_op_245a(t_ipc *ipc) /* MOVE */ {
690: /* mask fff8, bits 13d0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
691: int srcreg = (ipc->opcode >> 0) & 7;
692: uint32 srcaddr = ADDRREG(srcreg);
693: uint8 srcdata = fetchbyte(srcaddr);
694: uint32 dstaddr = ipc->dst;
695: uint8 outdata = srcdata;
696:
697: storebyte(dstaddr, outdata);
698: PC+= 6;
699: }
700:
701: void cpu_op_245b(t_ipc *ipc) /* MOVE */ {
702: /* mask fff8, bits 13d0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
703: int srcreg = (ipc->opcode >> 0) & 7;
704: uint32 srcaddr = ADDRREG(srcreg);
705: uint8 srcdata = fetchbyte(srcaddr);
706: uint32 dstaddr = ipc->dst;
707: uint8 outdata = srcdata;
708:
709: storebyte(dstaddr, outdata);
710:
711: VFLAG = 0;
712: CFLAG = 0;
713: NFLAG = ((sint8)outdata) < 0;
714: ZFLAG = !outdata;
715: PC+= 6;
716: }
717:
718: void cpu_op_246a(t_ipc *ipc) /* MOVE */ {
719: /* mask f1f8, bits 1018, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
720: int srcreg = (ipc->opcode >> 0) & 7;
721: uint32 srcaddr = ADDRREG(srcreg);
722: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
723: uint8 srcdata = fetchbyte(srcaddr);
724: int dstreg = (ipc->opcode >> 9) & 7;
725: uint8 outdata = srcdata;
726:
727: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
728: PC+= 2;
729: }
730:
731: void cpu_op_246b(t_ipc *ipc) /* MOVE */ {
732: /* mask f1f8, bits 1018, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
733: int srcreg = (ipc->opcode >> 0) & 7;
734: uint32 srcaddr = ADDRREG(srcreg);
735: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
736: uint8 srcdata = fetchbyte(srcaddr);
737: int dstreg = (ipc->opcode >> 9) & 7;
738: uint8 outdata = srcdata;
739:
740: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
741:
742: VFLAG = 0;
743: CFLAG = 0;
744: NFLAG = ((sint8)outdata) < 0;
745: ZFLAG = !outdata;
746: PC+= 2;
747: }
748:
749: void cpu_op_247a(t_ipc *ipc) /* MOVE */ {
750: /* mask f1f8, bits 1098, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
751: int srcreg = (ipc->opcode >> 0) & 7;
752: uint32 srcaddr = ADDRREG(srcreg);
753: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
754: uint8 srcdata = fetchbyte(srcaddr);
755: int dstreg = (ipc->opcode >> 9) & 7;
756: uint32 dstaddr = ADDRREG(dstreg);
757: uint8 outdata = srcdata;
758:
759: storebyte(dstaddr, outdata);
760: PC+= 2;
761: }
762:
763: void cpu_op_247b(t_ipc *ipc) /* MOVE */ {
764: /* mask f1f8, bits 1098, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
765: int srcreg = (ipc->opcode >> 0) & 7;
766: uint32 srcaddr = ADDRREG(srcreg);
767: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
768: uint8 srcdata = fetchbyte(srcaddr);
769: int dstreg = (ipc->opcode >> 9) & 7;
770: uint32 dstaddr = ADDRREG(dstreg);
771: uint8 outdata = srcdata;
772:
773: storebyte(dstaddr, outdata);
774:
775: VFLAG = 0;
776: CFLAG = 0;
777: NFLAG = ((sint8)outdata) < 0;
778: ZFLAG = !outdata;
779: PC+= 2;
780: }
781:
782: void cpu_op_248a(t_ipc *ipc) /* MOVE */ {
783: /* mask f1f8, bits 10d8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
784: int srcreg = (ipc->opcode >> 0) & 7;
785: uint32 srcaddr = ADDRREG(srcreg);
786: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
787: uint8 srcdata = fetchbyte(srcaddr);
788: int dstreg = (ipc->opcode >> 9) & 7;
789: uint32 dstaddr = ADDRREG(dstreg);
790: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
791: uint8 outdata = srcdata;
792:
793: storebyte(dstaddr, outdata);
794: PC+= 2;
795: }
796:
797: void cpu_op_248b(t_ipc *ipc) /* MOVE */ {
798: /* mask f1f8, bits 10d8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
799: int srcreg = (ipc->opcode >> 0) & 7;
800: uint32 srcaddr = ADDRREG(srcreg);
801: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
802: uint8 srcdata = fetchbyte(srcaddr);
803: int dstreg = (ipc->opcode >> 9) & 7;
804: uint32 dstaddr = ADDRREG(dstreg);
805: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
806: uint8 outdata = srcdata;
807:
808: storebyte(dstaddr, outdata);
809:
810: VFLAG = 0;
811: CFLAG = 0;
812: NFLAG = ((sint8)outdata) < 0;
813: ZFLAG = !outdata;
814: PC+= 2;
815: }
816:
817: void cpu_op_249a(t_ipc *ipc) /* MOVE */ {
818: /* mask f1f8, bits 1118, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
819: int srcreg = (ipc->opcode >> 0) & 7;
820: uint32 srcaddr = ADDRREG(srcreg);
821: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
822: uint8 srcdata = fetchbyte(srcaddr);
823: int dstreg = (ipc->opcode >> 9) & 7;
824: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
825: uint8 outdata = srcdata;
826:
827: storebyte(dstaddr, outdata);
828: PC+= 2;
829: }
830:
831: void cpu_op_249b(t_ipc *ipc) /* MOVE */ {
832: /* mask f1f8, bits 1118, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
833: int srcreg = (ipc->opcode >> 0) & 7;
834: uint32 srcaddr = ADDRREG(srcreg);
835: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
836: uint8 srcdata = fetchbyte(srcaddr);
837: int dstreg = (ipc->opcode >> 9) & 7;
838: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
839: uint8 outdata = srcdata;
840:
841: storebyte(dstaddr, outdata);
842:
843: VFLAG = 0;
844: CFLAG = 0;
845: NFLAG = ((sint8)outdata) < 0;
846: ZFLAG = !outdata;
847: PC+= 2;
848: }
849:
850: void cpu_op_250a(t_ipc *ipc) /* MOVE */ {
851: /* mask f1f8, bits 1158, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
852: int srcreg = (ipc->opcode >> 0) & 7;
853: uint32 srcaddr = ADDRREG(srcreg);
854: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
855: uint8 srcdata = fetchbyte(srcaddr);
856: int dstreg = (ipc->opcode >> 9) & 7;
857: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
858: uint8 outdata = srcdata;
859:
860: storebyte(dstaddr, outdata);
861: PC+= 4;
862: }
863:
864: void cpu_op_250b(t_ipc *ipc) /* MOVE */ {
865: /* mask f1f8, bits 1158, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
866: int srcreg = (ipc->opcode >> 0) & 7;
867: uint32 srcaddr = ADDRREG(srcreg);
868: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
869: uint8 srcdata = fetchbyte(srcaddr);
870: int dstreg = (ipc->opcode >> 9) & 7;
871: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
872: uint8 outdata = srcdata;
873:
874: storebyte(dstaddr, outdata);
875:
876: VFLAG = 0;
877: CFLAG = 0;
878: NFLAG = ((sint8)outdata) < 0;
879: ZFLAG = !outdata;
880: PC+= 4;
881: }
882:
883: void cpu_op_251a(t_ipc *ipc) /* MOVE */ {
884: /* mask f1f8, bits 1198, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
885: int srcreg = (ipc->opcode >> 0) & 7;
886: uint32 srcaddr = ADDRREG(srcreg);
887: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
888: uint8 srcdata = fetchbyte(srcaddr);
889: int dstreg = (ipc->opcode >> 9) & 7;
890: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
891: uint8 outdata = srcdata;
892:
893: storebyte(dstaddr, outdata);
894: PC+= 4;
895: }
896:
897: void cpu_op_251b(t_ipc *ipc) /* MOVE */ {
898: /* mask f1f8, bits 1198, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
899: int srcreg = (ipc->opcode >> 0) & 7;
900: uint32 srcaddr = ADDRREG(srcreg);
901: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
902: uint8 srcdata = fetchbyte(srcaddr);
903: int dstreg = (ipc->opcode >> 9) & 7;
904: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
905: uint8 outdata = srcdata;
906:
907: storebyte(dstaddr, outdata);
908:
909: VFLAG = 0;
910: CFLAG = 0;
911: NFLAG = ((sint8)outdata) < 0;
912: ZFLAG = !outdata;
913: PC+= 4;
914: }
915:
916: void cpu_op_252a(t_ipc *ipc) /* MOVE */ {
917: /* mask fff8, bits 11d8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
918: int srcreg = (ipc->opcode >> 0) & 7;
919: uint32 srcaddr = ADDRREG(srcreg);
920: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
921: uint8 srcdata = fetchbyte(srcaddr);
922: uint32 dstaddr = ipc->dst;
923: uint8 outdata = srcdata;
924:
925: storebyte(dstaddr, outdata);
926: PC+= 4;
927: }
928:
929: void cpu_op_252b(t_ipc *ipc) /* MOVE */ {
930: /* mask fff8, bits 11d8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
931: int srcreg = (ipc->opcode >> 0) & 7;
932: uint32 srcaddr = ADDRREG(srcreg);
933: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
934: uint8 srcdata = fetchbyte(srcaddr);
935: uint32 dstaddr = ipc->dst;
936: uint8 outdata = srcdata;
937:
938: storebyte(dstaddr, outdata);
939:
940: VFLAG = 0;
941: CFLAG = 0;
942: NFLAG = ((sint8)outdata) < 0;
943: ZFLAG = !outdata;
944: PC+= 4;
945: }
946:
947: void cpu_op_253a(t_ipc *ipc) /* MOVE */ {
948: /* mask fff8, bits 13d8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
949: int srcreg = (ipc->opcode >> 0) & 7;
950: uint32 srcaddr = ADDRREG(srcreg);
951: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
952: uint8 srcdata = fetchbyte(srcaddr);
953: uint32 dstaddr = ipc->dst;
954: uint8 outdata = srcdata;
955:
956: storebyte(dstaddr, outdata);
957: PC+= 6;
958: }
959:
960: void cpu_op_253b(t_ipc *ipc) /* MOVE */ {
961: /* mask fff8, bits 13d8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
962: int srcreg = (ipc->opcode >> 0) & 7;
963: uint32 srcaddr = ADDRREG(srcreg);
964: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
965: uint8 srcdata = fetchbyte(srcaddr);
966: uint32 dstaddr = ipc->dst;
967: uint8 outdata = srcdata;
968:
969: storebyte(dstaddr, outdata);
970:
971: VFLAG = 0;
972: CFLAG = 0;
973: NFLAG = ((sint8)outdata) < 0;
974: ZFLAG = !outdata;
975: PC+= 6;
976: }
977:
978: void cpu_op_254a(t_ipc *ipc) /* MOVE */ {
979: /* mask f1f8, bits 1020, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
980: int srcreg = (ipc->opcode >> 0) & 7;
981: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
982: uint8 srcdata = fetchbyte(srcaddr);
983: int dstreg = (ipc->opcode >> 9) & 7;
984: uint8 outdata = srcdata;
985:
986: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
987: PC+= 2;
988: }
989:
990: void cpu_op_254b(t_ipc *ipc) /* MOVE */ {
991: /* mask f1f8, bits 1020, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
992: int srcreg = (ipc->opcode >> 0) & 7;
993: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
994: uint8 srcdata = fetchbyte(srcaddr);
995: int dstreg = (ipc->opcode >> 9) & 7;
996: uint8 outdata = srcdata;
997:
998: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
999:
1000: VFLAG = 0;
1001: CFLAG = 0;
1002: NFLAG = ((sint8)outdata) < 0;
1003: ZFLAG = !outdata;
1004: PC+= 2;
1005: }
1006:
1007: void cpu_op_255a(t_ipc *ipc) /* MOVE */ {
1008: /* mask f1f8, bits 10a0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
1009: int srcreg = (ipc->opcode >> 0) & 7;
1010: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1011: uint8 srcdata = fetchbyte(srcaddr);
1012: int dstreg = (ipc->opcode >> 9) & 7;
1013: uint32 dstaddr = ADDRREG(dstreg);
1014: uint8 outdata = srcdata;
1015:
1016: storebyte(dstaddr, outdata);
1017: PC+= 2;
1018: }
1019:
1020: void cpu_op_255b(t_ipc *ipc) /* MOVE */ {
1021: /* mask f1f8, bits 10a0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
1022: int srcreg = (ipc->opcode >> 0) & 7;
1023: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1024: uint8 srcdata = fetchbyte(srcaddr);
1025: int dstreg = (ipc->opcode >> 9) & 7;
1026: uint32 dstaddr = ADDRREG(dstreg);
1027: uint8 outdata = srcdata;
1028:
1029: storebyte(dstaddr, outdata);
1030:
1031: VFLAG = 0;
1032: CFLAG = 0;
1033: NFLAG = ((sint8)outdata) < 0;
1034: ZFLAG = !outdata;
1035: PC+= 2;
1036: }
1037:
1038: void cpu_op_256a(t_ipc *ipc) /* MOVE */ {
1039: /* mask f1f8, bits 10e0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
1040: int srcreg = (ipc->opcode >> 0) & 7;
1041: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1042: uint8 srcdata = fetchbyte(srcaddr);
1043: int dstreg = (ipc->opcode >> 9) & 7;
1044: uint32 dstaddr = ADDRREG(dstreg);
1045: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
1046: uint8 outdata = srcdata;
1047:
1048: storebyte(dstaddr, outdata);
1049: PC+= 2;
1050: }
1051:
1052: void cpu_op_256b(t_ipc *ipc) /* MOVE */ {
1053: /* mask f1f8, bits 10e0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
1054: int srcreg = (ipc->opcode >> 0) & 7;
1055: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1056: uint8 srcdata = fetchbyte(srcaddr);
1057: int dstreg = (ipc->opcode >> 9) & 7;
1058: uint32 dstaddr = ADDRREG(dstreg);
1059: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
1060: uint8 outdata = srcdata;
1061:
1062: storebyte(dstaddr, outdata);
1063:
1064: VFLAG = 0;
1065: CFLAG = 0;
1066: NFLAG = ((sint8)outdata) < 0;
1067: ZFLAG = !outdata;
1068: PC+= 2;
1069: }
1070:
1071: void cpu_op_257a(t_ipc *ipc) /* MOVE */ {
1072: /* mask f1f8, bits 1120, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
1073: int srcreg = (ipc->opcode >> 0) & 7;
1074: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1075: uint8 srcdata = fetchbyte(srcaddr);
1076: int dstreg = (ipc->opcode >> 9) & 7;
1077: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
1078: uint8 outdata = srcdata;
1079:
1080: storebyte(dstaddr, outdata);
1081: PC+= 2;
1082: }
1083:
1084: void cpu_op_257b(t_ipc *ipc) /* MOVE */ {
1085: /* mask f1f8, bits 1120, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
1086: int srcreg = (ipc->opcode >> 0) & 7;
1087: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1088: uint8 srcdata = fetchbyte(srcaddr);
1089: int dstreg = (ipc->opcode >> 9) & 7;
1090: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
1091: uint8 outdata = srcdata;
1092:
1093: storebyte(dstaddr, outdata);
1094:
1095: VFLAG = 0;
1096: CFLAG = 0;
1097: NFLAG = ((sint8)outdata) < 0;
1098: ZFLAG = !outdata;
1099: PC+= 2;
1100: }
1101:
1102: void cpu_op_258a(t_ipc *ipc) /* MOVE */ {
1103: /* mask f1f8, bits 1160, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
1104: int srcreg = (ipc->opcode >> 0) & 7;
1105: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1106: uint8 srcdata = fetchbyte(srcaddr);
1107: int dstreg = (ipc->opcode >> 9) & 7;
1108: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1109: uint8 outdata = srcdata;
1110:
1111: storebyte(dstaddr, outdata);
1112: PC+= 4;
1113: }
1114:
1115: void cpu_op_258b(t_ipc *ipc) /* MOVE */ {
1116: /* mask f1f8, bits 1160, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
1117: int srcreg = (ipc->opcode >> 0) & 7;
1118: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1119: uint8 srcdata = fetchbyte(srcaddr);
1120: int dstreg = (ipc->opcode >> 9) & 7;
1121: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1122: uint8 outdata = srcdata;
1123:
1124: storebyte(dstaddr, outdata);
1125:
1126: VFLAG = 0;
1127: CFLAG = 0;
1128: NFLAG = ((sint8)outdata) < 0;
1129: ZFLAG = !outdata;
1130: PC+= 4;
1131: }
1132:
1133: void cpu_op_259a(t_ipc *ipc) /* MOVE */ {
1134: /* mask f1f8, bits 11a0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
1135: int srcreg = (ipc->opcode >> 0) & 7;
1136: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1137: uint8 srcdata = fetchbyte(srcaddr);
1138: int dstreg = (ipc->opcode >> 9) & 7;
1139: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1140: uint8 outdata = srcdata;
1141:
1142: storebyte(dstaddr, outdata);
1143: PC+= 4;
1144: }
1145:
1146: void cpu_op_259b(t_ipc *ipc) /* MOVE */ {
1147: /* mask f1f8, bits 11a0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
1148: int srcreg = (ipc->opcode >> 0) & 7;
1149: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1150: uint8 srcdata = fetchbyte(srcaddr);
1151: int dstreg = (ipc->opcode >> 9) & 7;
1152: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1153: uint8 outdata = srcdata;
1154:
1155: storebyte(dstaddr, outdata);
1156:
1157: VFLAG = 0;
1158: CFLAG = 0;
1159: NFLAG = ((sint8)outdata) < 0;
1160: ZFLAG = !outdata;
1161: PC+= 4;
1162: }
1163:
1164: void cpu_op_260a(t_ipc *ipc) /* MOVE */ {
1165: /* mask fff8, bits 11e0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
1166: int srcreg = (ipc->opcode >> 0) & 7;
1167: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1168: uint8 srcdata = fetchbyte(srcaddr);
1169: uint32 dstaddr = ipc->dst;
1170: uint8 outdata = srcdata;
1171:
1172: storebyte(dstaddr, outdata);
1173: PC+= 4;
1174: }
1175:
1176: void cpu_op_260b(t_ipc *ipc) /* MOVE */ {
1177: /* mask fff8, bits 11e0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
1178: int srcreg = (ipc->opcode >> 0) & 7;
1179: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1180: uint8 srcdata = fetchbyte(srcaddr);
1181: uint32 dstaddr = ipc->dst;
1182: uint8 outdata = srcdata;
1183:
1184: storebyte(dstaddr, outdata);
1185:
1186: VFLAG = 0;
1187: CFLAG = 0;
1188: NFLAG = ((sint8)outdata) < 0;
1189: ZFLAG = !outdata;
1190: PC+= 4;
1191: }
1192:
1193: void cpu_op_261a(t_ipc *ipc) /* MOVE */ {
1194: /* mask fff8, bits 13e0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
1195: int srcreg = (ipc->opcode >> 0) & 7;
1196: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1197: uint8 srcdata = fetchbyte(srcaddr);
1198: uint32 dstaddr = ipc->dst;
1199: uint8 outdata = srcdata;
1200:
1201: storebyte(dstaddr, outdata);
1202: PC+= 6;
1203: }
1204:
1205: void cpu_op_261b(t_ipc *ipc) /* MOVE */ {
1206: /* mask fff8, bits 13e0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
1207: int srcreg = (ipc->opcode >> 0) & 7;
1208: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1209: uint8 srcdata = fetchbyte(srcaddr);
1210: uint32 dstaddr = ipc->dst;
1211: uint8 outdata = srcdata;
1212:
1213: storebyte(dstaddr, outdata);
1214:
1215: VFLAG = 0;
1216: CFLAG = 0;
1217: NFLAG = ((sint8)outdata) < 0;
1218: ZFLAG = !outdata;
1219: PC+= 6;
1220: }
1221:
1222: void cpu_op_262a(t_ipc *ipc) /* MOVE */ {
1223: /* mask f1f8, bits 1028, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
1224: int srcreg = (ipc->opcode >> 0) & 7;
1225: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1226: uint8 srcdata = fetchbyte(srcaddr);
1227: int dstreg = (ipc->opcode >> 9) & 7;
1228: uint8 outdata = srcdata;
1229:
1230: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
1231: PC+= 4;
1232: }
1233:
1234: void cpu_op_262b(t_ipc *ipc) /* MOVE */ {
1235: /* mask f1f8, bits 1028, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
1236: int srcreg = (ipc->opcode >> 0) & 7;
1237: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1238: uint8 srcdata = fetchbyte(srcaddr);
1239: int dstreg = (ipc->opcode >> 9) & 7;
1240: uint8 outdata = srcdata;
1241:
1242: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
1243:
1244: VFLAG = 0;
1245: CFLAG = 0;
1246: NFLAG = ((sint8)outdata) < 0;
1247: ZFLAG = !outdata;
1248: PC+= 4;
1249: }
1250:
1251: void cpu_op_263a(t_ipc *ipc) /* MOVE */ {
1252: /* mask f1f8, bits 10a8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
1253: int srcreg = (ipc->opcode >> 0) & 7;
1254: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1255: uint8 srcdata = fetchbyte(srcaddr);
1256: int dstreg = (ipc->opcode >> 9) & 7;
1257: uint32 dstaddr = ADDRREG(dstreg);
1258: uint8 outdata = srcdata;
1259:
1260: storebyte(dstaddr, outdata);
1261: PC+= 4;
1262: }
1263:
1264: void cpu_op_263b(t_ipc *ipc) /* MOVE */ {
1265: /* mask f1f8, bits 10a8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
1266: int srcreg = (ipc->opcode >> 0) & 7;
1267: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1268: uint8 srcdata = fetchbyte(srcaddr);
1269: int dstreg = (ipc->opcode >> 9) & 7;
1270: uint32 dstaddr = ADDRREG(dstreg);
1271: uint8 outdata = srcdata;
1272:
1273: storebyte(dstaddr, outdata);
1274:
1275: VFLAG = 0;
1276: CFLAG = 0;
1277: NFLAG = ((sint8)outdata) < 0;
1278: ZFLAG = !outdata;
1279: PC+= 4;
1280: }
1281:
1282: void cpu_op_264a(t_ipc *ipc) /* MOVE */ {
1283: /* mask f1f8, bits 10e8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
1284: int srcreg = (ipc->opcode >> 0) & 7;
1285: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1286: uint8 srcdata = fetchbyte(srcaddr);
1287: int dstreg = (ipc->opcode >> 9) & 7;
1288: uint32 dstaddr = ADDRREG(dstreg);
1289: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
1290: uint8 outdata = srcdata;
1291:
1292: storebyte(dstaddr, outdata);
1293: PC+= 4;
1294: }
1295:
1296: void cpu_op_264b(t_ipc *ipc) /* MOVE */ {
1297: /* mask f1f8, bits 10e8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
1298: int srcreg = (ipc->opcode >> 0) & 7;
1299: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1300: uint8 srcdata = fetchbyte(srcaddr);
1301: int dstreg = (ipc->opcode >> 9) & 7;
1302: uint32 dstaddr = ADDRREG(dstreg);
1303: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
1304: uint8 outdata = srcdata;
1305:
1306: storebyte(dstaddr, outdata);
1307:
1308: VFLAG = 0;
1309: CFLAG = 0;
1310: NFLAG = ((sint8)outdata) < 0;
1311: ZFLAG = !outdata;
1312: PC+= 4;
1313: }
1314:
1315: void cpu_op_265a(t_ipc *ipc) /* MOVE */ {
1316: /* mask f1f8, bits 1128, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
1317: int srcreg = (ipc->opcode >> 0) & 7;
1318: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1319: uint8 srcdata = fetchbyte(srcaddr);
1320: int dstreg = (ipc->opcode >> 9) & 7;
1321: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
1322: uint8 outdata = srcdata;
1323:
1324: storebyte(dstaddr, outdata);
1325: PC+= 4;
1326: }
1327:
1328: void cpu_op_265b(t_ipc *ipc) /* MOVE */ {
1329: /* mask f1f8, bits 1128, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
1330: int srcreg = (ipc->opcode >> 0) & 7;
1331: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1332: uint8 srcdata = fetchbyte(srcaddr);
1333: int dstreg = (ipc->opcode >> 9) & 7;
1334: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
1335: uint8 outdata = srcdata;
1336:
1337: storebyte(dstaddr, outdata);
1338:
1339: VFLAG = 0;
1340: CFLAG = 0;
1341: NFLAG = ((sint8)outdata) < 0;
1342: ZFLAG = !outdata;
1343: PC+= 4;
1344: }
1345:
1346: void cpu_op_266a(t_ipc *ipc) /* MOVE */ {
1347: /* mask f1f8, bits 1168, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
1348: int srcreg = (ipc->opcode >> 0) & 7;
1349: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1350: uint8 srcdata = fetchbyte(srcaddr);
1351: int dstreg = (ipc->opcode >> 9) & 7;
1352: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1353: uint8 outdata = srcdata;
1354:
1355: storebyte(dstaddr, outdata);
1356: PC+= 6;
1357: }
1358:
1359: void cpu_op_266b(t_ipc *ipc) /* MOVE */ {
1360: /* mask f1f8, bits 1168, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
1361: int srcreg = (ipc->opcode >> 0) & 7;
1362: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1363: uint8 srcdata = fetchbyte(srcaddr);
1364: int dstreg = (ipc->opcode >> 9) & 7;
1365: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1366: uint8 outdata = srcdata;
1367:
1368: storebyte(dstaddr, outdata);
1369:
1370: VFLAG = 0;
1371: CFLAG = 0;
1372: NFLAG = ((sint8)outdata) < 0;
1373: ZFLAG = !outdata;
1374: PC+= 6;
1375: }
1376:
1377: void cpu_op_267a(t_ipc *ipc) /* MOVE */ {
1378: /* mask f1f8, bits 11a8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
1379: int srcreg = (ipc->opcode >> 0) & 7;
1380: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1381: uint8 srcdata = fetchbyte(srcaddr);
1382: int dstreg = (ipc->opcode >> 9) & 7;
1383: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1384: uint8 outdata = srcdata;
1385:
1386: storebyte(dstaddr, outdata);
1387: PC+= 6;
1388: }
1389:
1390: void cpu_op_267b(t_ipc *ipc) /* MOVE */ {
1391: /* mask f1f8, bits 11a8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
1392: int srcreg = (ipc->opcode >> 0) & 7;
1393: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1394: uint8 srcdata = fetchbyte(srcaddr);
1395: int dstreg = (ipc->opcode >> 9) & 7;
1396: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1397: uint8 outdata = srcdata;
1398:
1399: storebyte(dstaddr, outdata);
1400:
1401: VFLAG = 0;
1402: CFLAG = 0;
1403: NFLAG = ((sint8)outdata) < 0;
1404: ZFLAG = !outdata;
1405: PC+= 6;
1406: }
1407:
1408: void cpu_op_268a(t_ipc *ipc) /* MOVE */ {
1409: /* mask fff8, bits 11e8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
1410: int srcreg = (ipc->opcode >> 0) & 7;
1411: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1412: uint8 srcdata = fetchbyte(srcaddr);
1413: uint32 dstaddr = ipc->dst;
1414: uint8 outdata = srcdata;
1415:
1416: storebyte(dstaddr, outdata);
1417: PC+= 6;
1418: }
1419:
1420: void cpu_op_268b(t_ipc *ipc) /* MOVE */ {
1421: /* mask fff8, bits 11e8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
1422: int srcreg = (ipc->opcode >> 0) & 7;
1423: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1424: uint8 srcdata = fetchbyte(srcaddr);
1425: uint32 dstaddr = ipc->dst;
1426: uint8 outdata = srcdata;
1427:
1428: storebyte(dstaddr, outdata);
1429:
1430: VFLAG = 0;
1431: CFLAG = 0;
1432: NFLAG = ((sint8)outdata) < 0;
1433: ZFLAG = !outdata;
1434: PC+= 6;
1435: }
1436:
1437: void cpu_op_269a(t_ipc *ipc) /* MOVE */ {
1438: /* mask fff8, bits 13e8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
1439: int srcreg = (ipc->opcode >> 0) & 7;
1440: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1441: uint8 srcdata = fetchbyte(srcaddr);
1442: uint32 dstaddr = ipc->dst;
1443: uint8 outdata = srcdata;
1444:
1445: storebyte(dstaddr, outdata);
1446: PC+= 8;
1447: }
1448:
1449: void cpu_op_269b(t_ipc *ipc) /* MOVE */ {
1450: /* mask fff8, bits 13e8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
1451: int srcreg = (ipc->opcode >> 0) & 7;
1452: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1453: uint8 srcdata = fetchbyte(srcaddr);
1454: uint32 dstaddr = ipc->dst;
1455: uint8 outdata = srcdata;
1456:
1457: storebyte(dstaddr, outdata);
1458:
1459: VFLAG = 0;
1460: CFLAG = 0;
1461: NFLAG = ((sint8)outdata) < 0;
1462: ZFLAG = !outdata;
1463: PC+= 8;
1464: }
1465:
1466: void cpu_op_270a(t_ipc *ipc) /* MOVE */ {
1467: /* mask f1f8, bits 1030, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
1468: int srcreg = (ipc->opcode >> 0) & 7;
1469: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1470: uint8 srcdata = fetchbyte(srcaddr);
1471: int dstreg = (ipc->opcode >> 9) & 7;
1472: uint8 outdata = srcdata;
1473:
1474: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
1475: PC+= 4;
1476: }
1477:
1478: void cpu_op_270b(t_ipc *ipc) /* MOVE */ {
1479: /* mask f1f8, bits 1030, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
1480: int srcreg = (ipc->opcode >> 0) & 7;
1481: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1482: uint8 srcdata = fetchbyte(srcaddr);
1483: int dstreg = (ipc->opcode >> 9) & 7;
1484: uint8 outdata = srcdata;
1485:
1486: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
1487:
1488: VFLAG = 0;
1489: CFLAG = 0;
1490: NFLAG = ((sint8)outdata) < 0;
1491: ZFLAG = !outdata;
1492: PC+= 4;
1493: }
1494:
1495: void cpu_op_271a(t_ipc *ipc) /* MOVE */ {
1496: /* mask f1f8, bits 10b0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
1497: int srcreg = (ipc->opcode >> 0) & 7;
1498: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1499: uint8 srcdata = fetchbyte(srcaddr);
1500: int dstreg = (ipc->opcode >> 9) & 7;
1501: uint32 dstaddr = ADDRREG(dstreg);
1502: uint8 outdata = srcdata;
1503:
1504: storebyte(dstaddr, outdata);
1505: PC+= 4;
1506: }
1507:
1508: void cpu_op_271b(t_ipc *ipc) /* MOVE */ {
1509: /* mask f1f8, bits 10b0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
1510: int srcreg = (ipc->opcode >> 0) & 7;
1511: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1512: uint8 srcdata = fetchbyte(srcaddr);
1513: int dstreg = (ipc->opcode >> 9) & 7;
1514: uint32 dstaddr = ADDRREG(dstreg);
1515: uint8 outdata = srcdata;
1516:
1517: storebyte(dstaddr, outdata);
1518:
1519: VFLAG = 0;
1520: CFLAG = 0;
1521: NFLAG = ((sint8)outdata) < 0;
1522: ZFLAG = !outdata;
1523: PC+= 4;
1524: }
1525:
1526: void cpu_op_272a(t_ipc *ipc) /* MOVE */ {
1527: /* mask f1f8, bits 10f0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
1528: int srcreg = (ipc->opcode >> 0) & 7;
1529: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1530: uint8 srcdata = fetchbyte(srcaddr);
1531: int dstreg = (ipc->opcode >> 9) & 7;
1532: uint32 dstaddr = ADDRREG(dstreg);
1533: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
1534: uint8 outdata = srcdata;
1535:
1536: storebyte(dstaddr, outdata);
1537: PC+= 4;
1538: }
1539:
1540: void cpu_op_272b(t_ipc *ipc) /* MOVE */ {
1541: /* mask f1f8, bits 10f0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
1542: int srcreg = (ipc->opcode >> 0) & 7;
1543: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1544: uint8 srcdata = fetchbyte(srcaddr);
1545: int dstreg = (ipc->opcode >> 9) & 7;
1546: uint32 dstaddr = ADDRREG(dstreg);
1547: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
1548: uint8 outdata = srcdata;
1549:
1550: storebyte(dstaddr, outdata);
1551:
1552: VFLAG = 0;
1553: CFLAG = 0;
1554: NFLAG = ((sint8)outdata) < 0;
1555: ZFLAG = !outdata;
1556: PC+= 4;
1557: }
1558:
1559: void cpu_op_273a(t_ipc *ipc) /* MOVE */ {
1560: /* mask f1f8, bits 1130, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
1561: int srcreg = (ipc->opcode >> 0) & 7;
1562: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1563: uint8 srcdata = fetchbyte(srcaddr);
1564: int dstreg = (ipc->opcode >> 9) & 7;
1565: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
1566: uint8 outdata = srcdata;
1567:
1568: storebyte(dstaddr, outdata);
1569: PC+= 4;
1570: }
1571:
1572: void cpu_op_273b(t_ipc *ipc) /* MOVE */ {
1573: /* mask f1f8, bits 1130, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
1574: int srcreg = (ipc->opcode >> 0) & 7;
1575: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1576: uint8 srcdata = fetchbyte(srcaddr);
1577: int dstreg = (ipc->opcode >> 9) & 7;
1578: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
1579: uint8 outdata = srcdata;
1580:
1581: storebyte(dstaddr, outdata);
1582:
1583: VFLAG = 0;
1584: CFLAG = 0;
1585: NFLAG = ((sint8)outdata) < 0;
1586: ZFLAG = !outdata;
1587: PC+= 4;
1588: }
1589:
1590: void cpu_op_274a(t_ipc *ipc) /* MOVE */ {
1591: /* mask f1f8, bits 1170, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
1592: int srcreg = (ipc->opcode >> 0) & 7;
1593: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1594: uint8 srcdata = fetchbyte(srcaddr);
1595: int dstreg = (ipc->opcode >> 9) & 7;
1596: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1597: uint8 outdata = srcdata;
1598:
1599: storebyte(dstaddr, outdata);
1600: PC+= 6;
1601: }
1602:
1603: void cpu_op_274b(t_ipc *ipc) /* MOVE */ {
1604: /* mask f1f8, bits 1170, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
1605: int srcreg = (ipc->opcode >> 0) & 7;
1606: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1607: uint8 srcdata = fetchbyte(srcaddr);
1608: int dstreg = (ipc->opcode >> 9) & 7;
1609: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1610: uint8 outdata = srcdata;
1611:
1612: storebyte(dstaddr, outdata);
1613:
1614: VFLAG = 0;
1615: CFLAG = 0;
1616: NFLAG = ((sint8)outdata) < 0;
1617: ZFLAG = !outdata;
1618: PC+= 6;
1619: }
1620:
1621: void cpu_op_275a(t_ipc *ipc) /* MOVE */ {
1622: /* mask f1f8, bits 11b0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
1623: int srcreg = (ipc->opcode >> 0) & 7;
1624: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1625: uint8 srcdata = fetchbyte(srcaddr);
1626: int dstreg = (ipc->opcode >> 9) & 7;
1627: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1628: uint8 outdata = srcdata;
1629:
1630: storebyte(dstaddr, outdata);
1631: PC+= 6;
1632: }
1633:
1634: void cpu_op_275b(t_ipc *ipc) /* MOVE */ {
1635: /* mask f1f8, bits 11b0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
1636: int srcreg = (ipc->opcode >> 0) & 7;
1637: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1638: uint8 srcdata = fetchbyte(srcaddr);
1639: int dstreg = (ipc->opcode >> 9) & 7;
1640: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1641: uint8 outdata = srcdata;
1642:
1643: storebyte(dstaddr, outdata);
1644:
1645: VFLAG = 0;
1646: CFLAG = 0;
1647: NFLAG = ((sint8)outdata) < 0;
1648: ZFLAG = !outdata;
1649: PC+= 6;
1650: }
1651:
1652: void cpu_op_276a(t_ipc *ipc) /* MOVE */ {
1653: /* mask fff8, bits 11f0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
1654: int srcreg = (ipc->opcode >> 0) & 7;
1655: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1656: uint8 srcdata = fetchbyte(srcaddr);
1657: uint32 dstaddr = ipc->dst;
1658: uint8 outdata = srcdata;
1659:
1660: storebyte(dstaddr, outdata);
1661: PC+= 6;
1662: }
1663:
1664: void cpu_op_276b(t_ipc *ipc) /* MOVE */ {
1665: /* mask fff8, bits 11f0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
1666: int srcreg = (ipc->opcode >> 0) & 7;
1667: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1668: uint8 srcdata = fetchbyte(srcaddr);
1669: uint32 dstaddr = ipc->dst;
1670: uint8 outdata = srcdata;
1671:
1672: storebyte(dstaddr, outdata);
1673:
1674: VFLAG = 0;
1675: CFLAG = 0;
1676: NFLAG = ((sint8)outdata) < 0;
1677: ZFLAG = !outdata;
1678: PC+= 6;
1679: }
1680:
1681: void cpu_op_277a(t_ipc *ipc) /* MOVE */ {
1682: /* mask fff8, bits 13f0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
1683: int srcreg = (ipc->opcode >> 0) & 7;
1684: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1685: uint8 srcdata = fetchbyte(srcaddr);
1686: uint32 dstaddr = ipc->dst;
1687: uint8 outdata = srcdata;
1688:
1689: storebyte(dstaddr, outdata);
1690: PC+= 8;
1691: }
1692:
1693: void cpu_op_277b(t_ipc *ipc) /* MOVE */ {
1694: /* mask fff8, bits 13f0, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
1695: int srcreg = (ipc->opcode >> 0) & 7;
1696: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1697: uint8 srcdata = fetchbyte(srcaddr);
1698: uint32 dstaddr = ipc->dst;
1699: uint8 outdata = srcdata;
1700:
1701: storebyte(dstaddr, outdata);
1702:
1703: VFLAG = 0;
1704: CFLAG = 0;
1705: NFLAG = ((sint8)outdata) < 0;
1706: ZFLAG = !outdata;
1707: PC+= 8;
1708: }
1709:
1710: void cpu_op_278a(t_ipc *ipc) /* MOVE */ {
1711: /* mask f1ff, bits 1038, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
1712: uint32 srcaddr = ipc->src;
1713: uint8 srcdata = fetchbyte(srcaddr);
1714: int dstreg = (ipc->opcode >> 9) & 7;
1715: uint8 outdata = srcdata;
1716:
1717: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
1718: PC+= 4;
1719: }
1720:
1721: void cpu_op_278b(t_ipc *ipc) /* MOVE */ {
1722: /* mask f1ff, bits 1038, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
1723: uint32 srcaddr = ipc->src;
1724: uint8 srcdata = fetchbyte(srcaddr);
1725: int dstreg = (ipc->opcode >> 9) & 7;
1726: uint8 outdata = srcdata;
1727:
1728: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
1729:
1730: VFLAG = 0;
1731: CFLAG = 0;
1732: NFLAG = ((sint8)outdata) < 0;
1733: ZFLAG = !outdata;
1734: PC+= 4;
1735: }
1736:
1737: void cpu_op_279a(t_ipc *ipc) /* MOVE */ {
1738: /* mask f1ff, bits 10b8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
1739: uint32 srcaddr = ipc->src;
1740: uint8 srcdata = fetchbyte(srcaddr);
1741: int dstreg = (ipc->opcode >> 9) & 7;
1742: uint32 dstaddr = ADDRREG(dstreg);
1743: uint8 outdata = srcdata;
1744:
1745: storebyte(dstaddr, outdata);
1746: PC+= 4;
1747: }
1748:
1749: void cpu_op_279b(t_ipc *ipc) /* MOVE */ {
1750: /* mask f1ff, bits 10b8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
1751: uint32 srcaddr = ipc->src;
1752: uint8 srcdata = fetchbyte(srcaddr);
1753: int dstreg = (ipc->opcode >> 9) & 7;
1754: uint32 dstaddr = ADDRREG(dstreg);
1755: uint8 outdata = srcdata;
1756:
1757: storebyte(dstaddr, outdata);
1758:
1759: VFLAG = 0;
1760: CFLAG = 0;
1761: NFLAG = ((sint8)outdata) < 0;
1762: ZFLAG = !outdata;
1763: PC+= 4;
1764: }
1765:
1766: void cpu_op_280a(t_ipc *ipc) /* MOVE */ {
1767: /* mask f1ff, bits 10f8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
1768: uint32 srcaddr = ipc->src;
1769: uint8 srcdata = fetchbyte(srcaddr);
1770: int dstreg = (ipc->opcode >> 9) & 7;
1771: uint32 dstaddr = ADDRREG(dstreg);
1772: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
1773: uint8 outdata = srcdata;
1774:
1775: storebyte(dstaddr, outdata);
1776: PC+= 4;
1777: }
1778:
1779: void cpu_op_280b(t_ipc *ipc) /* MOVE */ {
1780: /* mask f1ff, bits 10f8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
1781: uint32 srcaddr = ipc->src;
1782: uint8 srcdata = fetchbyte(srcaddr);
1783: int dstreg = (ipc->opcode >> 9) & 7;
1784: uint32 dstaddr = ADDRREG(dstreg);
1785: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
1786: uint8 outdata = srcdata;
1787:
1788: storebyte(dstaddr, outdata);
1789:
1790: VFLAG = 0;
1791: CFLAG = 0;
1792: NFLAG = ((sint8)outdata) < 0;
1793: ZFLAG = !outdata;
1794: PC+= 4;
1795: }
1796:
1797: void cpu_op_281a(t_ipc *ipc) /* MOVE */ {
1798: /* mask f1ff, bits 1138, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
1799: uint32 srcaddr = ipc->src;
1800: uint8 srcdata = fetchbyte(srcaddr);
1801: int dstreg = (ipc->opcode >> 9) & 7;
1802: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
1803: uint8 outdata = srcdata;
1804:
1805: storebyte(dstaddr, outdata);
1806: PC+= 4;
1807: }
1808:
1809: void cpu_op_281b(t_ipc *ipc) /* MOVE */ {
1810: /* mask f1ff, bits 1138, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
1811: uint32 srcaddr = ipc->src;
1812: uint8 srcdata = fetchbyte(srcaddr);
1813: int dstreg = (ipc->opcode >> 9) & 7;
1814: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
1815: uint8 outdata = srcdata;
1816:
1817: storebyte(dstaddr, outdata);
1818:
1819: VFLAG = 0;
1820: CFLAG = 0;
1821: NFLAG = ((sint8)outdata) < 0;
1822: ZFLAG = !outdata;
1823: PC+= 4;
1824: }
1825:
1826: void cpu_op_282a(t_ipc *ipc) /* MOVE */ {
1827: /* mask f1ff, bits 1178, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
1828: uint32 srcaddr = ipc->src;
1829: uint8 srcdata = fetchbyte(srcaddr);
1830: int dstreg = (ipc->opcode >> 9) & 7;
1831: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1832: uint8 outdata = srcdata;
1833:
1834: storebyte(dstaddr, outdata);
1835: PC+= 6;
1836: }
1837:
1838: void cpu_op_282b(t_ipc *ipc) /* MOVE */ {
1839: /* mask f1ff, bits 1178, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
1840: uint32 srcaddr = ipc->src;
1841: uint8 srcdata = fetchbyte(srcaddr);
1842: int dstreg = (ipc->opcode >> 9) & 7;
1843: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1844: uint8 outdata = srcdata;
1845:
1846: storebyte(dstaddr, outdata);
1847:
1848: VFLAG = 0;
1849: CFLAG = 0;
1850: NFLAG = ((sint8)outdata) < 0;
1851: ZFLAG = !outdata;
1852: PC+= 6;
1853: }
1854:
1855: void cpu_op_283a(t_ipc *ipc) /* MOVE */ {
1856: /* mask f1ff, bits 11b8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
1857: uint32 srcaddr = ipc->src;
1858: uint8 srcdata = fetchbyte(srcaddr);
1859: int dstreg = (ipc->opcode >> 9) & 7;
1860: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1861: uint8 outdata = srcdata;
1862:
1863: storebyte(dstaddr, outdata);
1864: PC+= 6;
1865: }
1866:
1867: void cpu_op_283b(t_ipc *ipc) /* MOVE */ {
1868: /* mask f1ff, bits 11b8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
1869: uint32 srcaddr = ipc->src;
1870: uint8 srcdata = fetchbyte(srcaddr);
1871: int dstreg = (ipc->opcode >> 9) & 7;
1872: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1873: uint8 outdata = srcdata;
1874:
1875: storebyte(dstaddr, outdata);
1876:
1877: VFLAG = 0;
1878: CFLAG = 0;
1879: NFLAG = ((sint8)outdata) < 0;
1880: ZFLAG = !outdata;
1881: PC+= 6;
1882: }
1883:
1884: void cpu_op_284a(t_ipc *ipc) /* MOVE */ {
1885: /* mask ffff, bits 11f8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
1886: uint32 srcaddr = ipc->src;
1887: uint8 srcdata = fetchbyte(srcaddr);
1888: uint32 dstaddr = ipc->dst;
1889: uint8 outdata = srcdata;
1890:
1891: storebyte(dstaddr, outdata);
1892: PC+= 6;
1893: }
1894:
1895: void cpu_op_284b(t_ipc *ipc) /* MOVE */ {
1896: /* mask ffff, bits 11f8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
1897: uint32 srcaddr = ipc->src;
1898: uint8 srcdata = fetchbyte(srcaddr);
1899: uint32 dstaddr = ipc->dst;
1900: uint8 outdata = srcdata;
1901:
1902: storebyte(dstaddr, outdata);
1903:
1904: VFLAG = 0;
1905: CFLAG = 0;
1906: NFLAG = ((sint8)outdata) < 0;
1907: ZFLAG = !outdata;
1908: PC+= 6;
1909: }
1910:
1911: void cpu_op_285a(t_ipc *ipc) /* MOVE */ {
1912: /* mask ffff, bits 13f8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
1913: uint32 srcaddr = ipc->src;
1914: uint8 srcdata = fetchbyte(srcaddr);
1915: uint32 dstaddr = ipc->dst;
1916: uint8 outdata = srcdata;
1917:
1918: storebyte(dstaddr, outdata);
1919: PC+= 8;
1920: }
1921:
1922: void cpu_op_285b(t_ipc *ipc) /* MOVE */ {
1923: /* mask ffff, bits 13f8, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
1924: uint32 srcaddr = ipc->src;
1925: uint8 srcdata = fetchbyte(srcaddr);
1926: uint32 dstaddr = ipc->dst;
1927: uint8 outdata = srcdata;
1928:
1929: storebyte(dstaddr, outdata);
1930:
1931: VFLAG = 0;
1932: CFLAG = 0;
1933: NFLAG = ((sint8)outdata) < 0;
1934: ZFLAG = !outdata;
1935: PC+= 8;
1936: }
1937:
1938: void cpu_op_286a(t_ipc *ipc) /* MOVE */ {
1939: /* mask f1ff, bits 1039, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
1940: uint32 srcaddr = ipc->src;
1941: uint8 srcdata = fetchbyte(srcaddr);
1942: int dstreg = (ipc->opcode >> 9) & 7;
1943: uint8 outdata = srcdata;
1944:
1945: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
1946: PC+= 6;
1947: }
1948:
1949: void cpu_op_286b(t_ipc *ipc) /* MOVE */ {
1950: /* mask f1ff, bits 1039, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
1951: uint32 srcaddr = ipc->src;
1952: uint8 srcdata = fetchbyte(srcaddr);
1953: int dstreg = (ipc->opcode >> 9) & 7;
1954: uint8 outdata = srcdata;
1955:
1956: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
1957:
1958: VFLAG = 0;
1959: CFLAG = 0;
1960: NFLAG = ((sint8)outdata) < 0;
1961: ZFLAG = !outdata;
1962: PC+= 6;
1963: }
1964:
1965: void cpu_op_287a(t_ipc *ipc) /* MOVE */ {
1966: /* mask f1ff, bits 10b9, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
1967: uint32 srcaddr = ipc->src;
1968: uint8 srcdata = fetchbyte(srcaddr);
1969: int dstreg = (ipc->opcode >> 9) & 7;
1970: uint32 dstaddr = ADDRREG(dstreg);
1971: uint8 outdata = srcdata;
1972:
1973: storebyte(dstaddr, outdata);
1974: PC+= 6;
1975: }
1976:
1977: void cpu_op_287b(t_ipc *ipc) /* MOVE */ {
1978: /* mask f1ff, bits 10b9, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
1979: uint32 srcaddr = ipc->src;
1980: uint8 srcdata = fetchbyte(srcaddr);
1981: int dstreg = (ipc->opcode >> 9) & 7;
1982: uint32 dstaddr = ADDRREG(dstreg);
1983: uint8 outdata = srcdata;
1984:
1985: storebyte(dstaddr, outdata);
1986:
1987: VFLAG = 0;
1988: CFLAG = 0;
1989: NFLAG = ((sint8)outdata) < 0;
1990: ZFLAG = !outdata;
1991: PC+= 6;
1992: }
1993:
1994: void cpu_op_288a(t_ipc *ipc) /* MOVE */ {
1995: /* mask f1ff, bits 10f9, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
1996: uint32 srcaddr = ipc->src;
1997: uint8 srcdata = fetchbyte(srcaddr);
1998: int dstreg = (ipc->opcode >> 9) & 7;
1999: uint32 dstaddr = ADDRREG(dstreg);
2000: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2001: uint8 outdata = srcdata;
2002:
2003: storebyte(dstaddr, outdata);
2004: PC+= 6;
2005: }
2006:
2007: void cpu_op_288b(t_ipc *ipc) /* MOVE */ {
2008: /* mask f1ff, bits 10f9, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
2009: uint32 srcaddr = ipc->src;
2010: uint8 srcdata = fetchbyte(srcaddr);
2011: int dstreg = (ipc->opcode >> 9) & 7;
2012: uint32 dstaddr = ADDRREG(dstreg);
2013: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2014: uint8 outdata = srcdata;
2015:
2016: storebyte(dstaddr, outdata);
2017:
2018: VFLAG = 0;
2019: CFLAG = 0;
2020: NFLAG = ((sint8)outdata) < 0;
2021: ZFLAG = !outdata;
2022: PC+= 6;
2023: }
2024:
2025: void cpu_op_289a(t_ipc *ipc) /* MOVE */ {
2026: /* mask f1ff, bits 1139, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
2027: uint32 srcaddr = ipc->src;
2028: uint8 srcdata = fetchbyte(srcaddr);
2029: int dstreg = (ipc->opcode >> 9) & 7;
2030: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2031: uint8 outdata = srcdata;
2032:
2033: storebyte(dstaddr, outdata);
2034: PC+= 6;
2035: }
2036:
2037: void cpu_op_289b(t_ipc *ipc) /* MOVE */ {
2038: /* mask f1ff, bits 1139, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
2039: uint32 srcaddr = ipc->src;
2040: uint8 srcdata = fetchbyte(srcaddr);
2041: int dstreg = (ipc->opcode >> 9) & 7;
2042: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2043: uint8 outdata = srcdata;
2044:
2045: storebyte(dstaddr, outdata);
2046:
2047: VFLAG = 0;
2048: CFLAG = 0;
2049: NFLAG = ((sint8)outdata) < 0;
2050: ZFLAG = !outdata;
2051: PC+= 6;
2052: }
2053:
2054: void cpu_op_290a(t_ipc *ipc) /* MOVE */ {
2055: /* mask f1ff, bits 1179, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
2056: uint32 srcaddr = ipc->src;
2057: uint8 srcdata = fetchbyte(srcaddr);
2058: int dstreg = (ipc->opcode >> 9) & 7;
2059: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2060: uint8 outdata = srcdata;
2061:
2062: storebyte(dstaddr, outdata);
2063: PC+= 8;
2064: }
2065:
2066: void cpu_op_290b(t_ipc *ipc) /* MOVE */ {
2067: /* mask f1ff, bits 1179, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
2068: uint32 srcaddr = ipc->src;
2069: uint8 srcdata = fetchbyte(srcaddr);
2070: int dstreg = (ipc->opcode >> 9) & 7;
2071: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2072: uint8 outdata = srcdata;
2073:
2074: storebyte(dstaddr, outdata);
2075:
2076: VFLAG = 0;
2077: CFLAG = 0;
2078: NFLAG = ((sint8)outdata) < 0;
2079: ZFLAG = !outdata;
2080: PC+= 8;
2081: }
2082:
2083: void cpu_op_291a(t_ipc *ipc) /* MOVE */ {
2084: /* mask f1ff, bits 11b9, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
2085: uint32 srcaddr = ipc->src;
2086: uint8 srcdata = fetchbyte(srcaddr);
2087: int dstreg = (ipc->opcode >> 9) & 7;
2088: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2089: uint8 outdata = srcdata;
2090:
2091: storebyte(dstaddr, outdata);
2092: PC+= 8;
2093: }
2094:
2095: void cpu_op_291b(t_ipc *ipc) /* MOVE */ {
2096: /* mask f1ff, bits 11b9, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
2097: uint32 srcaddr = ipc->src;
2098: uint8 srcdata = fetchbyte(srcaddr);
2099: int dstreg = (ipc->opcode >> 9) & 7;
2100: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2101: uint8 outdata = srcdata;
2102:
2103: storebyte(dstaddr, outdata);
2104:
2105: VFLAG = 0;
2106: CFLAG = 0;
2107: NFLAG = ((sint8)outdata) < 0;
2108: ZFLAG = !outdata;
2109: PC+= 8;
2110: }
2111:
2112: void cpu_op_292a(t_ipc *ipc) /* MOVE */ {
2113: /* mask ffff, bits 11f9, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
2114: uint32 srcaddr = ipc->src;
2115: uint8 srcdata = fetchbyte(srcaddr);
2116: uint32 dstaddr = ipc->dst;
2117: uint8 outdata = srcdata;
2118:
2119: storebyte(dstaddr, outdata);
2120: PC+= 8;
2121: }
2122:
2123: void cpu_op_292b(t_ipc *ipc) /* MOVE */ {
2124: /* mask ffff, bits 11f9, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
2125: uint32 srcaddr = ipc->src;
2126: uint8 srcdata = fetchbyte(srcaddr);
2127: uint32 dstaddr = ipc->dst;
2128: uint8 outdata = srcdata;
2129:
2130: storebyte(dstaddr, outdata);
2131:
2132: VFLAG = 0;
2133: CFLAG = 0;
2134: NFLAG = ((sint8)outdata) < 0;
2135: ZFLAG = !outdata;
2136: PC+= 8;
2137: }
2138:
2139: void cpu_op_293a(t_ipc *ipc) /* MOVE */ {
2140: /* mask ffff, bits 13f9, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
2141: uint32 srcaddr = ipc->src;
2142: uint8 srcdata = fetchbyte(srcaddr);
2143: uint32 dstaddr = ipc->dst;
2144: uint8 outdata = srcdata;
2145:
2146: storebyte(dstaddr, outdata);
2147: PC+= 10;
2148: }
2149:
2150: void cpu_op_293b(t_ipc *ipc) /* MOVE */ {
2151: /* mask ffff, bits 13f9, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
2152: uint32 srcaddr = ipc->src;
2153: uint8 srcdata = fetchbyte(srcaddr);
2154: uint32 dstaddr = ipc->dst;
2155: uint8 outdata = srcdata;
2156:
2157: storebyte(dstaddr, outdata);
2158:
2159: VFLAG = 0;
2160: CFLAG = 0;
2161: NFLAG = ((sint8)outdata) < 0;
2162: ZFLAG = !outdata;
2163: PC+= 10;
2164: }
2165:
2166: void cpu_op_294a(t_ipc *ipc) /* MOVE */ {
2167: /* mask f1ff, bits 103a, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
2168: uint32 srcaddr = ipc->src;
2169: uint8 srcdata = fetchbyte(srcaddr);
2170: int dstreg = (ipc->opcode >> 9) & 7;
2171: uint8 outdata = srcdata;
2172:
2173: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
2174: PC+= 4;
2175: }
2176:
2177: void cpu_op_294b(t_ipc *ipc) /* MOVE */ {
2178: /* mask f1ff, bits 103a, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
2179: uint32 srcaddr = ipc->src;
2180: uint8 srcdata = fetchbyte(srcaddr);
2181: int dstreg = (ipc->opcode >> 9) & 7;
2182: uint8 outdata = srcdata;
2183:
2184: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
2185:
2186: VFLAG = 0;
2187: CFLAG = 0;
2188: NFLAG = ((sint8)outdata) < 0;
2189: ZFLAG = !outdata;
2190: PC+= 4;
2191: }
2192:
2193: void cpu_op_295a(t_ipc *ipc) /* MOVE */ {
2194: /* mask f1ff, bits 10ba, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
2195: uint32 srcaddr = ipc->src;
2196: uint8 srcdata = fetchbyte(srcaddr);
2197: int dstreg = (ipc->opcode >> 9) & 7;
2198: uint32 dstaddr = ADDRREG(dstreg);
2199: uint8 outdata = srcdata;
2200:
2201: storebyte(dstaddr, outdata);
2202: PC+= 4;
2203: }
2204:
2205: void cpu_op_295b(t_ipc *ipc) /* MOVE */ {
2206: /* mask f1ff, bits 10ba, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
2207: uint32 srcaddr = ipc->src;
2208: uint8 srcdata = fetchbyte(srcaddr);
2209: int dstreg = (ipc->opcode >> 9) & 7;
2210: uint32 dstaddr = ADDRREG(dstreg);
2211: uint8 outdata = srcdata;
2212:
2213: storebyte(dstaddr, outdata);
2214:
2215: VFLAG = 0;
2216: CFLAG = 0;
2217: NFLAG = ((sint8)outdata) < 0;
2218: ZFLAG = !outdata;
2219: PC+= 4;
2220: }
2221:
2222: void cpu_op_296a(t_ipc *ipc) /* MOVE */ {
2223: /* mask f1ff, bits 10fa, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
2224: uint32 srcaddr = ipc->src;
2225: uint8 srcdata = fetchbyte(srcaddr);
2226: int dstreg = (ipc->opcode >> 9) & 7;
2227: uint32 dstaddr = ADDRREG(dstreg);
2228: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2229: uint8 outdata = srcdata;
2230:
2231: storebyte(dstaddr, outdata);
2232: PC+= 4;
2233: }
2234:
2235: void cpu_op_296b(t_ipc *ipc) /* MOVE */ {
2236: /* mask f1ff, bits 10fa, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
2237: uint32 srcaddr = ipc->src;
2238: uint8 srcdata = fetchbyte(srcaddr);
2239: int dstreg = (ipc->opcode >> 9) & 7;
2240: uint32 dstaddr = ADDRREG(dstreg);
2241: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2242: uint8 outdata = srcdata;
2243:
2244: storebyte(dstaddr, outdata);
2245:
2246: VFLAG = 0;
2247: CFLAG = 0;
2248: NFLAG = ((sint8)outdata) < 0;
2249: ZFLAG = !outdata;
2250: PC+= 4;
2251: }
2252:
2253: void cpu_op_297a(t_ipc *ipc) /* MOVE */ {
2254: /* mask f1ff, bits 113a, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
2255: uint32 srcaddr = ipc->src;
2256: uint8 srcdata = fetchbyte(srcaddr);
2257: int dstreg = (ipc->opcode >> 9) & 7;
2258: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2259: uint8 outdata = srcdata;
2260:
2261: storebyte(dstaddr, outdata);
2262: PC+= 4;
2263: }
2264:
2265: void cpu_op_297b(t_ipc *ipc) /* MOVE */ {
2266: /* mask f1ff, bits 113a, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
2267: uint32 srcaddr = ipc->src;
2268: uint8 srcdata = fetchbyte(srcaddr);
2269: int dstreg = (ipc->opcode >> 9) & 7;
2270: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2271: uint8 outdata = srcdata;
2272:
2273: storebyte(dstaddr, outdata);
2274:
2275: VFLAG = 0;
2276: CFLAG = 0;
2277: NFLAG = ((sint8)outdata) < 0;
2278: ZFLAG = !outdata;
2279: PC+= 4;
2280: }
2281:
2282: void cpu_op_298a(t_ipc *ipc) /* MOVE */ {
2283: /* mask f1ff, bits 117a, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
2284: uint32 srcaddr = ipc->src;
2285: uint8 srcdata = fetchbyte(srcaddr);
2286: int dstreg = (ipc->opcode >> 9) & 7;
2287: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2288: uint8 outdata = srcdata;
2289:
2290: storebyte(dstaddr, outdata);
2291: PC+= 6;
2292: }
2293:
2294: void cpu_op_298b(t_ipc *ipc) /* MOVE */ {
2295: /* mask f1ff, bits 117a, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
2296: uint32 srcaddr = ipc->src;
2297: uint8 srcdata = fetchbyte(srcaddr);
2298: int dstreg = (ipc->opcode >> 9) & 7;
2299: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2300: uint8 outdata = srcdata;
2301:
2302: storebyte(dstaddr, outdata);
2303:
2304: VFLAG = 0;
2305: CFLAG = 0;
2306: NFLAG = ((sint8)outdata) < 0;
2307: ZFLAG = !outdata;
2308: PC+= 6;
2309: }
2310:
2311: void cpu_op_299a(t_ipc *ipc) /* MOVE */ {
2312: /* mask f1ff, bits 11ba, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
2313: uint32 srcaddr = ipc->src;
2314: uint8 srcdata = fetchbyte(srcaddr);
2315: int dstreg = (ipc->opcode >> 9) & 7;
2316: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2317: uint8 outdata = srcdata;
2318:
2319: storebyte(dstaddr, outdata);
2320: PC+= 6;
2321: }
2322:
2323: void cpu_op_299b(t_ipc *ipc) /* MOVE */ {
2324: /* mask f1ff, bits 11ba, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
2325: uint32 srcaddr = ipc->src;
2326: uint8 srcdata = fetchbyte(srcaddr);
2327: int dstreg = (ipc->opcode >> 9) & 7;
2328: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2329: uint8 outdata = srcdata;
2330:
2331: storebyte(dstaddr, outdata);
2332:
2333: VFLAG = 0;
2334: CFLAG = 0;
2335: NFLAG = ((sint8)outdata) < 0;
2336: ZFLAG = !outdata;
2337: PC+= 6;
2338: }
2339:
2340: void cpu_op_300a(t_ipc *ipc) /* MOVE */ {
2341: /* mask ffff, bits 11fa, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
2342: uint32 srcaddr = ipc->src;
2343: uint8 srcdata = fetchbyte(srcaddr);
2344: uint32 dstaddr = ipc->dst;
2345: uint8 outdata = srcdata;
2346:
2347: storebyte(dstaddr, outdata);
2348: PC+= 6;
2349: }
2350:
2351: void cpu_op_300b(t_ipc *ipc) /* MOVE */ {
2352: /* mask ffff, bits 11fa, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
2353: uint32 srcaddr = ipc->src;
2354: uint8 srcdata = fetchbyte(srcaddr);
2355: uint32 dstaddr = ipc->dst;
2356: uint8 outdata = srcdata;
2357:
2358: storebyte(dstaddr, outdata);
2359:
2360: VFLAG = 0;
2361: CFLAG = 0;
2362: NFLAG = ((sint8)outdata) < 0;
2363: ZFLAG = !outdata;
2364: PC+= 6;
2365: }
2366:
2367: void cpu_op_301a(t_ipc *ipc) /* MOVE */ {
2368: /* mask ffff, bits 13fa, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
2369: uint32 srcaddr = ipc->src;
2370: uint8 srcdata = fetchbyte(srcaddr);
2371: uint32 dstaddr = ipc->dst;
2372: uint8 outdata = srcdata;
2373:
2374: storebyte(dstaddr, outdata);
2375: PC+= 8;
2376: }
2377:
2378: void cpu_op_301b(t_ipc *ipc) /* MOVE */ {
2379: /* mask ffff, bits 13fa, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
2380: uint32 srcaddr = ipc->src;
2381: uint8 srcdata = fetchbyte(srcaddr);
2382: uint32 dstaddr = ipc->dst;
2383: uint8 outdata = srcdata;
2384:
2385: storebyte(dstaddr, outdata);
2386:
2387: VFLAG = 0;
2388: CFLAG = 0;
2389: NFLAG = ((sint8)outdata) < 0;
2390: ZFLAG = !outdata;
2391: PC+= 8;
2392: }
2393:
2394: void cpu_op_302a(t_ipc *ipc) /* MOVE */ {
2395: /* mask f1ff, bits 103b, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
2396: uint32 srcaddr = idxval_src(ipc);
2397: uint8 srcdata = fetchbyte(srcaddr);
2398: int dstreg = (ipc->opcode >> 9) & 7;
2399: uint8 outdata = srcdata;
2400:
2401: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
2402: PC+= 4;
2403: }
2404:
2405: void cpu_op_302b(t_ipc *ipc) /* MOVE */ {
2406: /* mask f1ff, bits 103b, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
2407: uint32 srcaddr = idxval_src(ipc);
2408: uint8 srcdata = fetchbyte(srcaddr);
2409: int dstreg = (ipc->opcode >> 9) & 7;
2410: uint8 outdata = srcdata;
2411:
2412: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
2413:
2414: VFLAG = 0;
2415: CFLAG = 0;
2416: NFLAG = ((sint8)outdata) < 0;
2417: ZFLAG = !outdata;
2418: PC+= 4;
2419: }
2420:
2421: void cpu_op_303a(t_ipc *ipc) /* MOVE */ {
2422: /* mask f1ff, bits 10bb, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
2423: uint32 srcaddr = idxval_src(ipc);
2424: uint8 srcdata = fetchbyte(srcaddr);
2425: int dstreg = (ipc->opcode >> 9) & 7;
2426: uint32 dstaddr = ADDRREG(dstreg);
2427: uint8 outdata = srcdata;
2428:
2429: storebyte(dstaddr, outdata);
2430: PC+= 4;
2431: }
2432:
2433: void cpu_op_303b(t_ipc *ipc) /* MOVE */ {
2434: /* mask f1ff, bits 10bb, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
2435: uint32 srcaddr = idxval_src(ipc);
2436: uint8 srcdata = fetchbyte(srcaddr);
2437: int dstreg = (ipc->opcode >> 9) & 7;
2438: uint32 dstaddr = ADDRREG(dstreg);
2439: uint8 outdata = srcdata;
2440:
2441: storebyte(dstaddr, outdata);
2442:
2443: VFLAG = 0;
2444: CFLAG = 0;
2445: NFLAG = ((sint8)outdata) < 0;
2446: ZFLAG = !outdata;
2447: PC+= 4;
2448: }
2449:
2450: void cpu_op_304a(t_ipc *ipc) /* MOVE */ {
2451: /* mask f1ff, bits 10fb, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
2452: uint32 srcaddr = idxval_src(ipc);
2453: uint8 srcdata = fetchbyte(srcaddr);
2454: int dstreg = (ipc->opcode >> 9) & 7;
2455: uint32 dstaddr = ADDRREG(dstreg);
2456: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2457: uint8 outdata = srcdata;
2458:
2459: storebyte(dstaddr, outdata);
2460: PC+= 4;
2461: }
2462:
2463: void cpu_op_304b(t_ipc *ipc) /* MOVE */ {
2464: /* mask f1ff, bits 10fb, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
2465: uint32 srcaddr = idxval_src(ipc);
2466: uint8 srcdata = fetchbyte(srcaddr);
2467: int dstreg = (ipc->opcode >> 9) & 7;
2468: uint32 dstaddr = ADDRREG(dstreg);
2469: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2470: uint8 outdata = srcdata;
2471:
2472: storebyte(dstaddr, outdata);
2473:
2474: VFLAG = 0;
2475: CFLAG = 0;
2476: NFLAG = ((sint8)outdata) < 0;
2477: ZFLAG = !outdata;
2478: PC+= 4;
2479: }
2480:
2481: void cpu_op_305a(t_ipc *ipc) /* MOVE */ {
2482: /* mask f1ff, bits 113b, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
2483: uint32 srcaddr = idxval_src(ipc);
2484: uint8 srcdata = fetchbyte(srcaddr);
2485: int dstreg = (ipc->opcode >> 9) & 7;
2486: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2487: uint8 outdata = srcdata;
2488:
2489: storebyte(dstaddr, outdata);
2490: PC+= 4;
2491: }
2492:
2493: void cpu_op_305b(t_ipc *ipc) /* MOVE */ {
2494: /* mask f1ff, bits 113b, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
2495: uint32 srcaddr = idxval_src(ipc);
2496: uint8 srcdata = fetchbyte(srcaddr);
2497: int dstreg = (ipc->opcode >> 9) & 7;
2498: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2499: uint8 outdata = srcdata;
2500:
2501: storebyte(dstaddr, outdata);
2502:
2503: VFLAG = 0;
2504: CFLAG = 0;
2505: NFLAG = ((sint8)outdata) < 0;
2506: ZFLAG = !outdata;
2507: PC+= 4;
2508: }
2509:
2510: void cpu_op_306a(t_ipc *ipc) /* MOVE */ {
2511: /* mask f1ff, bits 117b, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
2512: uint32 srcaddr = idxval_src(ipc);
2513: uint8 srcdata = fetchbyte(srcaddr);
2514: int dstreg = (ipc->opcode >> 9) & 7;
2515: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2516: uint8 outdata = srcdata;
2517:
2518: storebyte(dstaddr, outdata);
2519: PC+= 6;
2520: }
2521:
2522: void cpu_op_306b(t_ipc *ipc) /* MOVE */ {
2523: /* mask f1ff, bits 117b, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
2524: uint32 srcaddr = idxval_src(ipc);
2525: uint8 srcdata = fetchbyte(srcaddr);
2526: int dstreg = (ipc->opcode >> 9) & 7;
2527: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2528: uint8 outdata = srcdata;
2529:
2530: storebyte(dstaddr, outdata);
2531:
2532: VFLAG = 0;
2533: CFLAG = 0;
2534: NFLAG = ((sint8)outdata) < 0;
2535: ZFLAG = !outdata;
2536: PC+= 6;
2537: }
2538:
2539: void cpu_op_307a(t_ipc *ipc) /* MOVE */ {
2540: /* mask f1ff, bits 11bb, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
2541: uint32 srcaddr = idxval_src(ipc);
2542: uint8 srcdata = fetchbyte(srcaddr);
2543: int dstreg = (ipc->opcode >> 9) & 7;
2544: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2545: uint8 outdata = srcdata;
2546:
2547: storebyte(dstaddr, outdata);
2548: PC+= 6;
2549: }
2550:
2551: void cpu_op_307b(t_ipc *ipc) /* MOVE */ {
2552: /* mask f1ff, bits 11bb, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
2553: uint32 srcaddr = idxval_src(ipc);
2554: uint8 srcdata = fetchbyte(srcaddr);
2555: int dstreg = (ipc->opcode >> 9) & 7;
2556: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2557: uint8 outdata = srcdata;
2558:
2559: storebyte(dstaddr, outdata);
2560:
2561: VFLAG = 0;
2562: CFLAG = 0;
2563: NFLAG = ((sint8)outdata) < 0;
2564: ZFLAG = !outdata;
2565: PC+= 6;
2566: }
2567:
2568: void cpu_op_308a(t_ipc *ipc) /* MOVE */ {
2569: /* mask ffff, bits 11fb, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
2570: uint32 srcaddr = idxval_src(ipc);
2571: uint8 srcdata = fetchbyte(srcaddr);
2572: uint32 dstaddr = ipc->dst;
2573: uint8 outdata = srcdata;
2574:
2575: storebyte(dstaddr, outdata);
2576: PC+= 6;
2577: }
2578:
2579: void cpu_op_308b(t_ipc *ipc) /* MOVE */ {
2580: /* mask ffff, bits 11fb, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
2581: uint32 srcaddr = idxval_src(ipc);
2582: uint8 srcdata = fetchbyte(srcaddr);
2583: uint32 dstaddr = ipc->dst;
2584: uint8 outdata = srcdata;
2585:
2586: storebyte(dstaddr, outdata);
2587:
2588: VFLAG = 0;
2589: CFLAG = 0;
2590: NFLAG = ((sint8)outdata) < 0;
2591: ZFLAG = !outdata;
2592: PC+= 6;
2593: }
2594:
2595: void cpu_op_309a(t_ipc *ipc) /* MOVE */ {
2596: /* mask ffff, bits 13fb, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
2597: uint32 srcaddr = idxval_src(ipc);
2598: uint8 srcdata = fetchbyte(srcaddr);
2599: uint32 dstaddr = ipc->dst;
2600: uint8 outdata = srcdata;
2601:
2602: storebyte(dstaddr, outdata);
2603: PC+= 8;
2604: }
2605:
2606: void cpu_op_309b(t_ipc *ipc) /* MOVE */ {
2607: /* mask ffff, bits 13fb, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
2608: uint32 srcaddr = idxval_src(ipc);
2609: uint8 srcdata = fetchbyte(srcaddr);
2610: uint32 dstaddr = ipc->dst;
2611: uint8 outdata = srcdata;
2612:
2613: storebyte(dstaddr, outdata);
2614:
2615: VFLAG = 0;
2616: CFLAG = 0;
2617: NFLAG = ((sint8)outdata) < 0;
2618: ZFLAG = !outdata;
2619: PC+= 8;
2620: }
2621:
2622: void cpu_op_310a(t_ipc *ipc) /* MOVE */ {
2623: /* mask f1ff, bits 103c, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
2624: uint8 srcdata = ipc->src;
2625: int dstreg = (ipc->opcode >> 9) & 7;
2626: uint8 outdata = srcdata;
2627:
2628: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
2629: PC+= 4;
2630: }
2631:
2632: void cpu_op_310b(t_ipc *ipc) /* MOVE */ {
2633: /* mask f1ff, bits 103c, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
2634: uint8 srcdata = ipc->src;
2635: int dstreg = (ipc->opcode >> 9) & 7;
2636: uint8 outdata = srcdata;
2637:
2638: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
2639:
2640: VFLAG = 0;
2641: CFLAG = 0;
2642: NFLAG = ((sint8)outdata) < 0;
2643: ZFLAG = !outdata;
2644: PC+= 4;
2645: }
2646:
2647: void cpu_op_311a(t_ipc *ipc) /* MOVE */ {
2648: /* mask f1ff, bits 10bc, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
2649: uint8 srcdata = ipc->src;
2650: int dstreg = (ipc->opcode >> 9) & 7;
2651: uint32 dstaddr = ADDRREG(dstreg);
2652: uint8 outdata = srcdata;
2653:
2654: storebyte(dstaddr, outdata);
2655: PC+= 4;
2656: }
2657:
2658: void cpu_op_311b(t_ipc *ipc) /* MOVE */ {
2659: /* mask f1ff, bits 10bc, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 2, sbitpos 0, dbitpos 9, immvalue 0 */
2660: uint8 srcdata = ipc->src;
2661: int dstreg = (ipc->opcode >> 9) & 7;
2662: uint32 dstaddr = ADDRREG(dstreg);
2663: uint8 outdata = srcdata;
2664:
2665: storebyte(dstaddr, outdata);
2666:
2667: VFLAG = 0;
2668: CFLAG = 0;
2669: NFLAG = ((sint8)outdata) < 0;
2670: ZFLAG = !outdata;
2671: PC+= 4;
2672: }
2673:
2674: void cpu_op_312a(t_ipc *ipc) /* MOVE */ {
2675: /* mask f1ff, bits 10fc, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
2676: uint8 srcdata = ipc->src;
2677: int dstreg = (ipc->opcode >> 9) & 7;
2678: uint32 dstaddr = ADDRREG(dstreg);
2679: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2680: uint8 outdata = srcdata;
2681:
2682: storebyte(dstaddr, outdata);
2683: PC+= 4;
2684: }
2685:
2686: void cpu_op_312b(t_ipc *ipc) /* MOVE */ {
2687: /* mask f1ff, bits 10fc, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 3, sbitpos 0, dbitpos 9, immvalue 0 */
2688: uint8 srcdata = ipc->src;
2689: int dstreg = (ipc->opcode >> 9) & 7;
2690: uint32 dstaddr = ADDRREG(dstreg);
2691: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2692: uint8 outdata = srcdata;
2693:
2694: storebyte(dstaddr, outdata);
2695:
2696: VFLAG = 0;
2697: CFLAG = 0;
2698: NFLAG = ((sint8)outdata) < 0;
2699: ZFLAG = !outdata;
2700: PC+= 4;
2701: }
2702:
2703: void cpu_op_313a(t_ipc *ipc) /* MOVE */ {
2704: /* mask f1ff, bits 113c, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
2705: uint8 srcdata = ipc->src;
2706: int dstreg = (ipc->opcode >> 9) & 7;
2707: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2708: uint8 outdata = srcdata;
2709:
2710: storebyte(dstaddr, outdata);
2711: PC+= 4;
2712: }
2713:
2714: void cpu_op_313b(t_ipc *ipc) /* MOVE */ {
2715: /* mask f1ff, bits 113c, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */
2716: uint8 srcdata = ipc->src;
2717: int dstreg = (ipc->opcode >> 9) & 7;
2718: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2719: uint8 outdata = srcdata;
2720:
2721: storebyte(dstaddr, outdata);
2722:
2723: VFLAG = 0;
2724: CFLAG = 0;
2725: NFLAG = ((sint8)outdata) < 0;
2726: ZFLAG = !outdata;
2727: PC+= 4;
2728: }
2729:
2730: void cpu_op_314a(t_ipc *ipc) /* MOVE */ {
2731: /* mask f1ff, bits 117c, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
2732: uint8 srcdata = ipc->src;
2733: int dstreg = (ipc->opcode >> 9) & 7;
2734: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2735: uint8 outdata = srcdata;
2736:
2737: storebyte(dstaddr, outdata);
2738: PC+= 6;
2739: }
2740:
2741: void cpu_op_314b(t_ipc *ipc) /* MOVE */ {
2742: /* mask f1ff, bits 117c, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 5, sbitpos 0, dbitpos 9, immvalue 0 */
2743: uint8 srcdata = ipc->src;
2744: int dstreg = (ipc->opcode >> 9) & 7;
2745: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2746: uint8 outdata = srcdata;
2747:
2748: storebyte(dstaddr, outdata);
2749:
2750: VFLAG = 0;
2751: CFLAG = 0;
2752: NFLAG = ((sint8)outdata) < 0;
2753: ZFLAG = !outdata;
2754: PC+= 6;
2755: }
2756:
2757: void cpu_op_315a(t_ipc *ipc) /* MOVE */ {
2758: /* mask f1ff, bits 11bc, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
2759: uint8 srcdata = ipc->src;
2760: int dstreg = (ipc->opcode >> 9) & 7;
2761: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2762: uint8 outdata = srcdata;
2763:
2764: storebyte(dstaddr, outdata);
2765: PC+= 6;
2766: }
2767:
2768: void cpu_op_315b(t_ipc *ipc) /* MOVE */ {
2769: /* mask f1ff, bits 11bc, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 6, sbitpos 0, dbitpos 9, immvalue 0 */
2770: uint8 srcdata = ipc->src;
2771: int dstreg = (ipc->opcode >> 9) & 7;
2772: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2773: uint8 outdata = srcdata;
2774:
2775: storebyte(dstaddr, outdata);
2776:
2777: VFLAG = 0;
2778: CFLAG = 0;
2779: NFLAG = ((sint8)outdata) < 0;
2780: ZFLAG = !outdata;
2781: PC+= 6;
2782: }
2783:
2784: void cpu_op_316a(t_ipc *ipc) /* MOVE */ {
2785: /* mask ffff, bits 11fc, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
2786: uint8 srcdata = ipc->src;
2787: uint32 dstaddr = ipc->dst;
2788: uint8 outdata = srcdata;
2789:
2790: storebyte(dstaddr, outdata);
2791: PC+= 6;
2792: }
2793:
2794: void cpu_op_316b(t_ipc *ipc) /* MOVE */ {
2795: /* mask ffff, bits 11fc, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 7, sbitpos 0, dbitpos 9, immvalue 0 */
2796: uint8 srcdata = ipc->src;
2797: uint32 dstaddr = ipc->dst;
2798: uint8 outdata = srcdata;
2799:
2800: storebyte(dstaddr, outdata);
2801:
2802: VFLAG = 0;
2803: CFLAG = 0;
2804: NFLAG = ((sint8)outdata) < 0;
2805: ZFLAG = !outdata;
2806: PC+= 6;
2807: }
2808:
2809: void cpu_op_317a(t_ipc *ipc) /* MOVE */ {
2810: /* mask ffff, bits 13fc, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
2811: uint8 srcdata = ipc->src;
2812: uint32 dstaddr = ipc->dst;
2813: uint8 outdata = srcdata;
2814:
2815: storebyte(dstaddr, outdata);
2816: PC+= 8;
2817: }
2818:
2819: void cpu_op_317b(t_ipc *ipc) /* MOVE */ {
2820: /* mask ffff, bits 13fc, mnemonic 21, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 8, sbitpos 0, dbitpos 9, immvalue 0 */
2821: uint8 srcdata = ipc->src;
2822: uint32 dstaddr = ipc->dst;
2823: uint8 outdata = srcdata;
2824:
2825: storebyte(dstaddr, outdata);
2826:
2827: VFLAG = 0;
2828: CFLAG = 0;
2829: NFLAG = ((sint8)outdata) < 0;
2830: ZFLAG = !outdata;
2831: PC+= 8;
2832: }
2833:
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