![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to cpu68k-4.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Generator SEGA Genesis emulator] / generator / src / out|
Return to cpu68k-4.c CVS log | Up to [Generator SEGA Genesis emulator] / generator / src / out |
1.1 root 1: /*****************************************************************************/
2: /* Generator - Sega Genesis emulation - (c) James Ponder 1997-1998 */
3: /*****************************************************************************/
4: /* */
5: /* cpu68k-4.c */
6: /* */
7: /*****************************************************************************/
8:
9: #include "generator.h"
10: #include "cpu68k.h"
11: #include "mem68k.h"
12: #include "reg68k.h"
13:
14: #include "cpu68k-inline.h"
15:
16: #include <stdio.h>
17:
18: void cpu_op_534a(t_ipc *ipc) /* NEGX */ {
19: /* mask fff8, bits 4000, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
20: int srcreg = (ipc->opcode >> 0) & 7;
21: uint8 srcdata = DATAREG(srcreg);
22: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
23:
24: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
25: PC+= 2;
26: }
27:
28: void cpu_op_534b(t_ipc *ipc) /* NEGX */ {
29: /* mask fff8, bits 4000, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
30: int srcreg = (ipc->opcode >> 0) & 7;
31: uint8 srcdata = DATAREG(srcreg);
32: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
33:
34: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
35:
36: VFLAG = ((sint8)srcdata < 0) && ((sint8)outdata < 0);
37: XFLAG = CFLAG = ((sint8)srcdata < 0) || ((sint8)outdata < 0);
38: NFLAG = ((sint8)outdata) < 0;
39: if (outdata) ZFLAG = 0;
40: PC+= 2;
41: }
42:
43: void cpu_op_535a(t_ipc *ipc) /* NEGX */ {
44: /* mask fff8, bits 4010, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
45: int srcreg = (ipc->opcode >> 0) & 7;
46: uint32 srcaddr = ADDRREG(srcreg);
47: uint8 srcdata = fetchbyte(srcaddr);
48: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
49:
50: storebyte(srcaddr, outdata);
51: PC+= 2;
52: }
53:
54: void cpu_op_535b(t_ipc *ipc) /* NEGX */ {
55: /* mask fff8, bits 4010, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
56: int srcreg = (ipc->opcode >> 0) & 7;
57: uint32 srcaddr = ADDRREG(srcreg);
58: uint8 srcdata = fetchbyte(srcaddr);
59: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
60:
61: storebyte(srcaddr, outdata);
62:
63: VFLAG = ((sint8)srcdata < 0) && ((sint8)outdata < 0);
64: XFLAG = CFLAG = ((sint8)srcdata < 0) || ((sint8)outdata < 0);
65: NFLAG = ((sint8)outdata) < 0;
66: if (outdata) ZFLAG = 0;
67: PC+= 2;
68: }
69:
70: void cpu_op_536a(t_ipc *ipc) /* NEGX */ {
71: /* mask fff8, bits 4018, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
72: int srcreg = (ipc->opcode >> 0) & 7;
73: uint32 srcaddr = ADDRREG(srcreg);
74: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
75: uint8 srcdata = fetchbyte(srcaddr);
76: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
77:
78: storebyte(srcaddr, outdata);
79: PC+= 2;
80: }
81:
82: void cpu_op_536b(t_ipc *ipc) /* NEGX */ {
83: /* mask fff8, bits 4018, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
84: int srcreg = (ipc->opcode >> 0) & 7;
85: uint32 srcaddr = ADDRREG(srcreg);
86: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
87: uint8 srcdata = fetchbyte(srcaddr);
88: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
89:
90: storebyte(srcaddr, outdata);
91:
92: VFLAG = ((sint8)srcdata < 0) && ((sint8)outdata < 0);
93: XFLAG = CFLAG = ((sint8)srcdata < 0) || ((sint8)outdata < 0);
94: NFLAG = ((sint8)outdata) < 0;
95: if (outdata) ZFLAG = 0;
96: PC+= 2;
97: }
98:
99: void cpu_op_537a(t_ipc *ipc) /* NEGX */ {
100: /* mask fff8, bits 4020, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
101: int srcreg = (ipc->opcode >> 0) & 7;
102: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
103: uint8 srcdata = fetchbyte(srcaddr);
104: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
105:
106: storebyte(srcaddr, outdata);
107: PC+= 2;
108: }
109:
110: void cpu_op_537b(t_ipc *ipc) /* NEGX */ {
111: /* mask fff8, bits 4020, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
112: int srcreg = (ipc->opcode >> 0) & 7;
113: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
114: uint8 srcdata = fetchbyte(srcaddr);
115: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
116:
117: storebyte(srcaddr, outdata);
118:
119: VFLAG = ((sint8)srcdata < 0) && ((sint8)outdata < 0);
120: XFLAG = CFLAG = ((sint8)srcdata < 0) || ((sint8)outdata < 0);
121: NFLAG = ((sint8)outdata) < 0;
122: if (outdata) ZFLAG = 0;
123: PC+= 2;
124: }
125:
126: void cpu_op_538a(t_ipc *ipc) /* NEGX */ {
127: /* mask fff8, bits 4028, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
128: int srcreg = (ipc->opcode >> 0) & 7;
129: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
130: uint8 srcdata = fetchbyte(srcaddr);
131: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
132:
133: storebyte(srcaddr, outdata);
134: PC+= 4;
135: }
136:
137: void cpu_op_538b(t_ipc *ipc) /* NEGX */ {
138: /* mask fff8, bits 4028, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
139: int srcreg = (ipc->opcode >> 0) & 7;
140: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
141: uint8 srcdata = fetchbyte(srcaddr);
142: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
143:
144: storebyte(srcaddr, outdata);
145:
146: VFLAG = ((sint8)srcdata < 0) && ((sint8)outdata < 0);
147: XFLAG = CFLAG = ((sint8)srcdata < 0) || ((sint8)outdata < 0);
148: NFLAG = ((sint8)outdata) < 0;
149: if (outdata) ZFLAG = 0;
150: PC+= 4;
151: }
152:
153: void cpu_op_539a(t_ipc *ipc) /* NEGX */ {
154: /* mask fff8, bits 4030, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
155: int srcreg = (ipc->opcode >> 0) & 7;
156: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
157: uint8 srcdata = fetchbyte(srcaddr);
158: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
159:
160: storebyte(srcaddr, outdata);
161: PC+= 4;
162: }
163:
164: void cpu_op_539b(t_ipc *ipc) /* NEGX */ {
165: /* mask fff8, bits 4030, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
166: int srcreg = (ipc->opcode >> 0) & 7;
167: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
168: uint8 srcdata = fetchbyte(srcaddr);
169: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
170:
171: storebyte(srcaddr, outdata);
172:
173: VFLAG = ((sint8)srcdata < 0) && ((sint8)outdata < 0);
174: XFLAG = CFLAG = ((sint8)srcdata < 0) || ((sint8)outdata < 0);
175: NFLAG = ((sint8)outdata) < 0;
176: if (outdata) ZFLAG = 0;
177: PC+= 4;
178: }
179:
180: void cpu_op_540a(t_ipc *ipc) /* NEGX */ {
181: /* mask ffff, bits 4038, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
182: uint32 srcaddr = ipc->src;
183: uint8 srcdata = fetchbyte(srcaddr);
184: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
185:
186: storebyte(srcaddr, outdata);
187: PC+= 4;
188: }
189:
190: void cpu_op_540b(t_ipc *ipc) /* NEGX */ {
191: /* mask ffff, bits 4038, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
192: uint32 srcaddr = ipc->src;
193: uint8 srcdata = fetchbyte(srcaddr);
194: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
195:
196: storebyte(srcaddr, outdata);
197:
198: VFLAG = ((sint8)srcdata < 0) && ((sint8)outdata < 0);
199: XFLAG = CFLAG = ((sint8)srcdata < 0) || ((sint8)outdata < 0);
200: NFLAG = ((sint8)outdata) < 0;
201: if (outdata) ZFLAG = 0;
202: PC+= 4;
203: }
204:
205: void cpu_op_541a(t_ipc *ipc) /* NEGX */ {
206: /* mask ffff, bits 4039, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
207: uint32 srcaddr = ipc->src;
208: uint8 srcdata = fetchbyte(srcaddr);
209: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
210:
211: storebyte(srcaddr, outdata);
212: PC+= 6;
213: }
214:
215: void cpu_op_541b(t_ipc *ipc) /* NEGX */ {
216: /* mask ffff, bits 4039, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
217: uint32 srcaddr = ipc->src;
218: uint8 srcdata = fetchbyte(srcaddr);
219: uint8 outdata = 0 - (sint8)srcdata - XFLAG;
220:
221: storebyte(srcaddr, outdata);
222:
223: VFLAG = ((sint8)srcdata < 0) && ((sint8)outdata < 0);
224: XFLAG = CFLAG = ((sint8)srcdata < 0) || ((sint8)outdata < 0);
225: NFLAG = ((sint8)outdata) < 0;
226: if (outdata) ZFLAG = 0;
227: PC+= 6;
228: }
229:
230: void cpu_op_542a(t_ipc *ipc) /* NEGX */ {
231: /* mask fff8, bits 4040, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
232: int srcreg = (ipc->opcode >> 0) & 7;
233: uint16 srcdata = DATAREG(srcreg);
234: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
235:
236: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xffff) | outdata;
237: PC+= 2;
238: }
239:
240: void cpu_op_542b(t_ipc *ipc) /* NEGX */ {
241: /* mask fff8, bits 4040, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
242: int srcreg = (ipc->opcode >> 0) & 7;
243: uint16 srcdata = DATAREG(srcreg);
244: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
245:
246: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xffff) | outdata;
247:
248: VFLAG = ((sint16)srcdata < 0) && ((sint16)outdata < 0);
249: XFLAG = CFLAG = ((sint16)srcdata < 0) || ((sint16)outdata < 0);
250: NFLAG = ((sint16)outdata) < 0;
251: if (outdata) ZFLAG = 0;
252: PC+= 2;
253: }
254:
255: void cpu_op_543a(t_ipc *ipc) /* NEGX */ {
256: /* mask fff8, bits 4050, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
257: int srcreg = (ipc->opcode >> 0) & 7;
258: uint32 srcaddr = ADDRREG(srcreg);
259: uint16 srcdata = fetchword(srcaddr);
260: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
261:
262: storeword(srcaddr, outdata);
263: PC+= 2;
264: }
265:
266: void cpu_op_543b(t_ipc *ipc) /* NEGX */ {
267: /* mask fff8, bits 4050, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
268: int srcreg = (ipc->opcode >> 0) & 7;
269: uint32 srcaddr = ADDRREG(srcreg);
270: uint16 srcdata = fetchword(srcaddr);
271: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
272:
273: storeword(srcaddr, outdata);
274:
275: VFLAG = ((sint16)srcdata < 0) && ((sint16)outdata < 0);
276: XFLAG = CFLAG = ((sint16)srcdata < 0) || ((sint16)outdata < 0);
277: NFLAG = ((sint16)outdata) < 0;
278: if (outdata) ZFLAG = 0;
279: PC+= 2;
280: }
281:
282: void cpu_op_544a(t_ipc *ipc) /* NEGX */ {
283: /* mask fff8, bits 4058, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
284: int srcreg = (ipc->opcode >> 0) & 7;
285: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
286: uint16 srcdata = fetchword(srcaddr);
287: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
288:
289: storeword(srcaddr, outdata);
290: PC+= 2;
291: }
292:
293: void cpu_op_544b(t_ipc *ipc) /* NEGX */ {
294: /* mask fff8, bits 4058, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
295: int srcreg = (ipc->opcode >> 0) & 7;
296: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
297: uint16 srcdata = fetchword(srcaddr);
298: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
299:
300: storeword(srcaddr, outdata);
301:
302: VFLAG = ((sint16)srcdata < 0) && ((sint16)outdata < 0);
303: XFLAG = CFLAG = ((sint16)srcdata < 0) || ((sint16)outdata < 0);
304: NFLAG = ((sint16)outdata) < 0;
305: if (outdata) ZFLAG = 0;
306: PC+= 2;
307: }
308:
309: void cpu_op_545a(t_ipc *ipc) /* NEGX */ {
310: /* mask fff8, bits 4060, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
311: int srcreg = (ipc->opcode >> 0) & 7;
312: uint32 srcaddr = ADDRREG(srcreg)-=2;
313: uint16 srcdata = fetchword(srcaddr);
314: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
315:
316: storeword(srcaddr, outdata);
317: PC+= 2;
318: }
319:
320: void cpu_op_545b(t_ipc *ipc) /* NEGX */ {
321: /* mask fff8, bits 4060, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
322: int srcreg = (ipc->opcode >> 0) & 7;
323: uint32 srcaddr = ADDRREG(srcreg)-=2;
324: uint16 srcdata = fetchword(srcaddr);
325: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
326:
327: storeword(srcaddr, outdata);
328:
329: VFLAG = ((sint16)srcdata < 0) && ((sint16)outdata < 0);
330: XFLAG = CFLAG = ((sint16)srcdata < 0) || ((sint16)outdata < 0);
331: NFLAG = ((sint16)outdata) < 0;
332: if (outdata) ZFLAG = 0;
333: PC+= 2;
334: }
335:
336: void cpu_op_546a(t_ipc *ipc) /* NEGX */ {
337: /* mask fff8, bits 4068, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
338: int srcreg = (ipc->opcode >> 0) & 7;
339: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
340: uint16 srcdata = fetchword(srcaddr);
341: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
342:
343: storeword(srcaddr, outdata);
344: PC+= 4;
345: }
346:
347: void cpu_op_546b(t_ipc *ipc) /* NEGX */ {
348: /* mask fff8, bits 4068, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
349: int srcreg = (ipc->opcode >> 0) & 7;
350: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
351: uint16 srcdata = fetchword(srcaddr);
352: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
353:
354: storeword(srcaddr, outdata);
355:
356: VFLAG = ((sint16)srcdata < 0) && ((sint16)outdata < 0);
357: XFLAG = CFLAG = ((sint16)srcdata < 0) || ((sint16)outdata < 0);
358: NFLAG = ((sint16)outdata) < 0;
359: if (outdata) ZFLAG = 0;
360: PC+= 4;
361: }
362:
363: void cpu_op_547a(t_ipc *ipc) /* NEGX */ {
364: /* mask fff8, bits 4070, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
365: int srcreg = (ipc->opcode >> 0) & 7;
366: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
367: uint16 srcdata = fetchword(srcaddr);
368: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
369:
370: storeword(srcaddr, outdata);
371: PC+= 4;
372: }
373:
374: void cpu_op_547b(t_ipc *ipc) /* NEGX */ {
375: /* mask fff8, bits 4070, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
376: int srcreg = (ipc->opcode >> 0) & 7;
377: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
378: uint16 srcdata = fetchword(srcaddr);
379: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
380:
381: storeword(srcaddr, outdata);
382:
383: VFLAG = ((sint16)srcdata < 0) && ((sint16)outdata < 0);
384: XFLAG = CFLAG = ((sint16)srcdata < 0) || ((sint16)outdata < 0);
385: NFLAG = ((sint16)outdata) < 0;
386: if (outdata) ZFLAG = 0;
387: PC+= 4;
388: }
389:
390: void cpu_op_548a(t_ipc *ipc) /* NEGX */ {
391: /* mask ffff, bits 4078, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
392: uint32 srcaddr = ipc->src;
393: uint16 srcdata = fetchword(srcaddr);
394: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
395:
396: storeword(srcaddr, outdata);
397: PC+= 4;
398: }
399:
400: void cpu_op_548b(t_ipc *ipc) /* NEGX */ {
401: /* mask ffff, bits 4078, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
402: uint32 srcaddr = ipc->src;
403: uint16 srcdata = fetchword(srcaddr);
404: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
405:
406: storeword(srcaddr, outdata);
407:
408: VFLAG = ((sint16)srcdata < 0) && ((sint16)outdata < 0);
409: XFLAG = CFLAG = ((sint16)srcdata < 0) || ((sint16)outdata < 0);
410: NFLAG = ((sint16)outdata) < 0;
411: if (outdata) ZFLAG = 0;
412: PC+= 4;
413: }
414:
415: void cpu_op_549a(t_ipc *ipc) /* NEGX */ {
416: /* mask ffff, bits 4079, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
417: uint32 srcaddr = ipc->src;
418: uint16 srcdata = fetchword(srcaddr);
419: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
420:
421: storeword(srcaddr, outdata);
422: PC+= 6;
423: }
424:
425: void cpu_op_549b(t_ipc *ipc) /* NEGX */ {
426: /* mask ffff, bits 4079, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
427: uint32 srcaddr = ipc->src;
428: uint16 srcdata = fetchword(srcaddr);
429: uint16 outdata = 0 - (sint16)srcdata - XFLAG;
430:
431: storeword(srcaddr, outdata);
432:
433: VFLAG = ((sint16)srcdata < 0) && ((sint16)outdata < 0);
434: XFLAG = CFLAG = ((sint16)srcdata < 0) || ((sint16)outdata < 0);
435: NFLAG = ((sint16)outdata) < 0;
436: if (outdata) ZFLAG = 0;
437: PC+= 6;
438: }
439:
440: void cpu_op_550a(t_ipc *ipc) /* NEGX */ {
441: /* mask fff8, bits 4080, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
442: int srcreg = (ipc->opcode >> 0) & 7;
443: uint32 srcdata = DATAREG(srcreg);
444: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
445:
446: DATAREG(srcreg) = outdata;
447: PC+= 2;
448: }
449:
450: void cpu_op_550b(t_ipc *ipc) /* NEGX */ {
451: /* mask fff8, bits 4080, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
452: int srcreg = (ipc->opcode >> 0) & 7;
453: uint32 srcdata = DATAREG(srcreg);
454: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
455:
456: DATAREG(srcreg) = outdata;
457:
458: VFLAG = ((sint32)srcdata < 0) && ((sint32)outdata < 0);
459: XFLAG = CFLAG = ((sint32)srcdata < 0) || ((sint32)outdata < 0);
460: NFLAG = ((sint32)outdata) < 0;
461: if (outdata) ZFLAG = 0;
462: PC+= 2;
463: }
464:
465: void cpu_op_551a(t_ipc *ipc) /* NEGX */ {
466: /* mask fff8, bits 4090, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
467: int srcreg = (ipc->opcode >> 0) & 7;
468: uint32 srcaddr = ADDRREG(srcreg);
469: uint32 srcdata = fetchlong(srcaddr);
470: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
471:
472: storelong(srcaddr, outdata);
473: PC+= 2;
474: }
475:
476: void cpu_op_551b(t_ipc *ipc) /* NEGX */ {
477: /* mask fff8, bits 4090, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
478: int srcreg = (ipc->opcode >> 0) & 7;
479: uint32 srcaddr = ADDRREG(srcreg);
480: uint32 srcdata = fetchlong(srcaddr);
481: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
482:
483: storelong(srcaddr, outdata);
484:
485: VFLAG = ((sint32)srcdata < 0) && ((sint32)outdata < 0);
486: XFLAG = CFLAG = ((sint32)srcdata < 0) || ((sint32)outdata < 0);
487: NFLAG = ((sint32)outdata) < 0;
488: if (outdata) ZFLAG = 0;
489: PC+= 2;
490: }
491:
492: void cpu_op_552a(t_ipc *ipc) /* NEGX */ {
493: /* mask fff8, bits 4098, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
494: int srcreg = (ipc->opcode >> 0) & 7;
495: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4);
496: uint32 srcdata = fetchlong(srcaddr);
497: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
498:
499: storelong(srcaddr, outdata);
500: PC+= 2;
501: }
502:
503: void cpu_op_552b(t_ipc *ipc) /* NEGX */ {
504: /* mask fff8, bits 4098, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
505: int srcreg = (ipc->opcode >> 0) & 7;
506: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4);
507: uint32 srcdata = fetchlong(srcaddr);
508: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
509:
510: storelong(srcaddr, outdata);
511:
512: VFLAG = ((sint32)srcdata < 0) && ((sint32)outdata < 0);
513: XFLAG = CFLAG = ((sint32)srcdata < 0) || ((sint32)outdata < 0);
514: NFLAG = ((sint32)outdata) < 0;
515: if (outdata) ZFLAG = 0;
516: PC+= 2;
517: }
518:
519: void cpu_op_553a(t_ipc *ipc) /* NEGX */ {
520: /* mask fff8, bits 40a0, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
521: int srcreg = (ipc->opcode >> 0) & 7;
522: uint32 srcaddr = ADDRREG(srcreg)-=4;
523: uint32 srcdata = fetchlong(srcaddr);
524: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
525:
526: storelong(srcaddr, outdata);
527: PC+= 2;
528: }
529:
530: void cpu_op_553b(t_ipc *ipc) /* NEGX */ {
531: /* mask fff8, bits 40a0, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
532: int srcreg = (ipc->opcode >> 0) & 7;
533: uint32 srcaddr = ADDRREG(srcreg)-=4;
534: uint32 srcdata = fetchlong(srcaddr);
535: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
536:
537: storelong(srcaddr, outdata);
538:
539: VFLAG = ((sint32)srcdata < 0) && ((sint32)outdata < 0);
540: XFLAG = CFLAG = ((sint32)srcdata < 0) || ((sint32)outdata < 0);
541: NFLAG = ((sint32)outdata) < 0;
542: if (outdata) ZFLAG = 0;
543: PC+= 2;
544: }
545:
546: void cpu_op_554a(t_ipc *ipc) /* NEGX */ {
547: /* mask fff8, bits 40a8, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
548: int srcreg = (ipc->opcode >> 0) & 7;
549: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
550: uint32 srcdata = fetchlong(srcaddr);
551: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
552:
553: storelong(srcaddr, outdata);
554: PC+= 4;
555: }
556:
557: void cpu_op_554b(t_ipc *ipc) /* NEGX */ {
558: /* mask fff8, bits 40a8, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
559: int srcreg = (ipc->opcode >> 0) & 7;
560: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
561: uint32 srcdata = fetchlong(srcaddr);
562: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
563:
564: storelong(srcaddr, outdata);
565:
566: VFLAG = ((sint32)srcdata < 0) && ((sint32)outdata < 0);
567: XFLAG = CFLAG = ((sint32)srcdata < 0) || ((sint32)outdata < 0);
568: NFLAG = ((sint32)outdata) < 0;
569: if (outdata) ZFLAG = 0;
570: PC+= 4;
571: }
572:
573: void cpu_op_555a(t_ipc *ipc) /* NEGX */ {
574: /* mask fff8, bits 40b0, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
575: int srcreg = (ipc->opcode >> 0) & 7;
576: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
577: uint32 srcdata = fetchlong(srcaddr);
578: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
579:
580: storelong(srcaddr, outdata);
581: PC+= 4;
582: }
583:
584: void cpu_op_555b(t_ipc *ipc) /* NEGX */ {
585: /* mask fff8, bits 40b0, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
586: int srcreg = (ipc->opcode >> 0) & 7;
587: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
588: uint32 srcdata = fetchlong(srcaddr);
589: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
590:
591: storelong(srcaddr, outdata);
592:
593: VFLAG = ((sint32)srcdata < 0) && ((sint32)outdata < 0);
594: XFLAG = CFLAG = ((sint32)srcdata < 0) || ((sint32)outdata < 0);
595: NFLAG = ((sint32)outdata) < 0;
596: if (outdata) ZFLAG = 0;
597: PC+= 4;
598: }
599:
600: void cpu_op_556a(t_ipc *ipc) /* NEGX */ {
601: /* mask ffff, bits 40b8, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
602: uint32 srcaddr = ipc->src;
603: uint32 srcdata = fetchlong(srcaddr);
604: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
605:
606: storelong(srcaddr, outdata);
607: PC+= 4;
608: }
609:
610: void cpu_op_556b(t_ipc *ipc) /* NEGX */ {
611: /* mask ffff, bits 40b8, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
612: uint32 srcaddr = ipc->src;
613: uint32 srcdata = fetchlong(srcaddr);
614: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
615:
616: storelong(srcaddr, outdata);
617:
618: VFLAG = ((sint32)srcdata < 0) && ((sint32)outdata < 0);
619: XFLAG = CFLAG = ((sint32)srcdata < 0) || ((sint32)outdata < 0);
620: NFLAG = ((sint32)outdata) < 0;
621: if (outdata) ZFLAG = 0;
622: PC+= 4;
623: }
624:
625: void cpu_op_557a(t_ipc *ipc) /* NEGX */ {
626: /* mask ffff, bits 40b9, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
627: uint32 srcaddr = ipc->src;
628: uint32 srcdata = fetchlong(srcaddr);
629: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
630:
631: storelong(srcaddr, outdata);
632: PC+= 6;
633: }
634:
635: void cpu_op_557b(t_ipc *ipc) /* NEGX */ {
636: /* mask ffff, bits 40b9, mnemonic 32, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
637: uint32 srcaddr = ipc->src;
638: uint32 srcdata = fetchlong(srcaddr);
639: uint32 outdata = 0 - (sint32)srcdata - XFLAG;
640:
641: storelong(srcaddr, outdata);
642:
643: VFLAG = ((sint32)srcdata < 0) && ((sint32)outdata < 0);
644: XFLAG = CFLAG = ((sint32)srcdata < 0) || ((sint32)outdata < 0);
645: NFLAG = ((sint32)outdata) < 0;
646: if (outdata) ZFLAG = 0;
647: PC+= 6;
648: }
649:
650: void cpu_op_558a(t_ipc *ipc) /* CLR */ {
651: /* mask fff8, bits 4200, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
652: int srcreg = (ipc->opcode >> 0) & 7;
653: uint8 srcdata = DATAREG(srcreg);
654: uint8 outdata = 0;
655:
656: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
657: PC+= 2;
658: }
659:
660: void cpu_op_558b(t_ipc *ipc) /* CLR */ {
661: /* mask fff8, bits 4200, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
662: int srcreg = (ipc->opcode >> 0) & 7;
663: uint8 srcdata = DATAREG(srcreg);
664: uint8 outdata = 0;
665:
666: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
667:
668: VFLAG = 0;
669: CFLAG = 0;
670: NFLAG = 0;
671: ZFLAG = 1;
672: PC+= 2;
673: }
674:
675: void cpu_op_559a(t_ipc *ipc) /* CLR */ {
676: /* mask fff8, bits 4210, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
677: int srcreg = (ipc->opcode >> 0) & 7;
678: uint32 srcaddr = ADDRREG(srcreg);
679: uint8 srcdata = fetchbyte(srcaddr);
680: uint8 outdata = 0;
681:
682: storebyte(srcaddr, outdata);
683: PC+= 2;
684: }
685:
686: void cpu_op_559b(t_ipc *ipc) /* CLR */ {
687: /* mask fff8, bits 4210, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
688: int srcreg = (ipc->opcode >> 0) & 7;
689: uint32 srcaddr = ADDRREG(srcreg);
690: uint8 srcdata = fetchbyte(srcaddr);
691: uint8 outdata = 0;
692:
693: storebyte(srcaddr, outdata);
694:
695: VFLAG = 0;
696: CFLAG = 0;
697: NFLAG = 0;
698: ZFLAG = 1;
699: PC+= 2;
700: }
701:
702: void cpu_op_560a(t_ipc *ipc) /* CLR */ {
703: /* mask fff8, bits 4218, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
704: int srcreg = (ipc->opcode >> 0) & 7;
705: uint32 srcaddr = ADDRREG(srcreg);
706: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
707: uint8 srcdata = fetchbyte(srcaddr);
708: uint8 outdata = 0;
709:
710: storebyte(srcaddr, outdata);
711: PC+= 2;
712: }
713:
714: void cpu_op_560b(t_ipc *ipc) /* CLR */ {
715: /* mask fff8, bits 4218, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
716: int srcreg = (ipc->opcode >> 0) & 7;
717: uint32 srcaddr = ADDRREG(srcreg);
718: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
719: uint8 srcdata = fetchbyte(srcaddr);
720: uint8 outdata = 0;
721:
722: storebyte(srcaddr, outdata);
723:
724: VFLAG = 0;
725: CFLAG = 0;
726: NFLAG = 0;
727: ZFLAG = 1;
728: PC+= 2;
729: }
730:
731: void cpu_op_561a(t_ipc *ipc) /* CLR */ {
732: /* mask fff8, bits 4220, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
733: int srcreg = (ipc->opcode >> 0) & 7;
734: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
735: uint8 srcdata = fetchbyte(srcaddr);
736: uint8 outdata = 0;
737:
738: storebyte(srcaddr, outdata);
739: PC+= 2;
740: }
741:
742: void cpu_op_561b(t_ipc *ipc) /* CLR */ {
743: /* mask fff8, bits 4220, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
744: int srcreg = (ipc->opcode >> 0) & 7;
745: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
746: uint8 srcdata = fetchbyte(srcaddr);
747: uint8 outdata = 0;
748:
749: storebyte(srcaddr, outdata);
750:
751: VFLAG = 0;
752: CFLAG = 0;
753: NFLAG = 0;
754: ZFLAG = 1;
755: PC+= 2;
756: }
757:
758: void cpu_op_562a(t_ipc *ipc) /* CLR */ {
759: /* mask fff8, bits 4228, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
760: int srcreg = (ipc->opcode >> 0) & 7;
761: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
762: uint8 srcdata = fetchbyte(srcaddr);
763: uint8 outdata = 0;
764:
765: storebyte(srcaddr, outdata);
766: PC+= 4;
767: }
768:
769: void cpu_op_562b(t_ipc *ipc) /* CLR */ {
770: /* mask fff8, bits 4228, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
771: int srcreg = (ipc->opcode >> 0) & 7;
772: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
773: uint8 srcdata = fetchbyte(srcaddr);
774: uint8 outdata = 0;
775:
776: storebyte(srcaddr, outdata);
777:
778: VFLAG = 0;
779: CFLAG = 0;
780: NFLAG = 0;
781: ZFLAG = 1;
782: PC+= 4;
783: }
784:
785: void cpu_op_563a(t_ipc *ipc) /* CLR */ {
786: /* mask fff8, bits 4230, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
787: int srcreg = (ipc->opcode >> 0) & 7;
788: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
789: uint8 srcdata = fetchbyte(srcaddr);
790: uint8 outdata = 0;
791:
792: storebyte(srcaddr, outdata);
793: PC+= 4;
794: }
795:
796: void cpu_op_563b(t_ipc *ipc) /* CLR */ {
797: /* mask fff8, bits 4230, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
798: int srcreg = (ipc->opcode >> 0) & 7;
799: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
800: uint8 srcdata = fetchbyte(srcaddr);
801: uint8 outdata = 0;
802:
803: storebyte(srcaddr, outdata);
804:
805: VFLAG = 0;
806: CFLAG = 0;
807: NFLAG = 0;
808: ZFLAG = 1;
809: PC+= 4;
810: }
811:
812: void cpu_op_564a(t_ipc *ipc) /* CLR */ {
813: /* mask ffff, bits 4238, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
814: uint32 srcaddr = ipc->src;
815: uint8 srcdata = fetchbyte(srcaddr);
816: uint8 outdata = 0;
817:
818: storebyte(srcaddr, outdata);
819: PC+= 4;
820: }
821:
822: void cpu_op_564b(t_ipc *ipc) /* CLR */ {
823: /* mask ffff, bits 4238, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
824: uint32 srcaddr = ipc->src;
825: uint8 srcdata = fetchbyte(srcaddr);
826: uint8 outdata = 0;
827:
828: storebyte(srcaddr, outdata);
829:
830: VFLAG = 0;
831: CFLAG = 0;
832: NFLAG = 0;
833: ZFLAG = 1;
834: PC+= 4;
835: }
836:
837: void cpu_op_565a(t_ipc *ipc) /* CLR */ {
838: /* mask ffff, bits 4239, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
839: uint32 srcaddr = ipc->src;
840: uint8 srcdata = fetchbyte(srcaddr);
841: uint8 outdata = 0;
842:
843: storebyte(srcaddr, outdata);
844: PC+= 6;
845: }
846:
847: void cpu_op_565b(t_ipc *ipc) /* CLR */ {
848: /* mask ffff, bits 4239, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
849: uint32 srcaddr = ipc->src;
850: uint8 srcdata = fetchbyte(srcaddr);
851: uint8 outdata = 0;
852:
853: storebyte(srcaddr, outdata);
854:
855: VFLAG = 0;
856: CFLAG = 0;
857: NFLAG = 0;
858: ZFLAG = 1;
859: PC+= 6;
860: }
861:
862: void cpu_op_566a(t_ipc *ipc) /* CLR */ {
863: /* mask fff8, bits 4240, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
864: int srcreg = (ipc->opcode >> 0) & 7;
865: uint16 srcdata = DATAREG(srcreg);
866: uint16 outdata = 0;
867:
868: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xffff) | outdata;
869: PC+= 2;
870: }
871:
872: void cpu_op_566b(t_ipc *ipc) /* CLR */ {
873: /* mask fff8, bits 4240, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
874: int srcreg = (ipc->opcode >> 0) & 7;
875: uint16 srcdata = DATAREG(srcreg);
876: uint16 outdata = 0;
877:
878: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xffff) | outdata;
879:
880: VFLAG = 0;
881: CFLAG = 0;
882: NFLAG = 0;
883: ZFLAG = 1;
884: PC+= 2;
885: }
886:
887: void cpu_op_567a(t_ipc *ipc) /* CLR */ {
888: /* mask fff8, bits 4250, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
889: int srcreg = (ipc->opcode >> 0) & 7;
890: uint32 srcaddr = ADDRREG(srcreg);
891: uint16 srcdata = fetchword(srcaddr);
892: uint16 outdata = 0;
893:
894: storeword(srcaddr, outdata);
895: PC+= 2;
896: }
897:
898: void cpu_op_567b(t_ipc *ipc) /* CLR */ {
899: /* mask fff8, bits 4250, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
900: int srcreg = (ipc->opcode >> 0) & 7;
901: uint32 srcaddr = ADDRREG(srcreg);
902: uint16 srcdata = fetchword(srcaddr);
903: uint16 outdata = 0;
904:
905: storeword(srcaddr, outdata);
906:
907: VFLAG = 0;
908: CFLAG = 0;
909: NFLAG = 0;
910: ZFLAG = 1;
911: PC+= 2;
912: }
913:
914: void cpu_op_568a(t_ipc *ipc) /* CLR */ {
915: /* mask fff8, bits 4258, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
916: int srcreg = (ipc->opcode >> 0) & 7;
917: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
918: uint16 srcdata = fetchword(srcaddr);
919: uint16 outdata = 0;
920:
921: storeword(srcaddr, outdata);
922: PC+= 2;
923: }
924:
925: void cpu_op_568b(t_ipc *ipc) /* CLR */ {
926: /* mask fff8, bits 4258, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
927: int srcreg = (ipc->opcode >> 0) & 7;
928: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
929: uint16 srcdata = fetchword(srcaddr);
930: uint16 outdata = 0;
931:
932: storeword(srcaddr, outdata);
933:
934: VFLAG = 0;
935: CFLAG = 0;
936: NFLAG = 0;
937: ZFLAG = 1;
938: PC+= 2;
939: }
940:
941: void cpu_op_569a(t_ipc *ipc) /* CLR */ {
942: /* mask fff8, bits 4260, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
943: int srcreg = (ipc->opcode >> 0) & 7;
944: uint32 srcaddr = ADDRREG(srcreg)-=2;
945: uint16 srcdata = fetchword(srcaddr);
946: uint16 outdata = 0;
947:
948: storeword(srcaddr, outdata);
949: PC+= 2;
950: }
951:
952: void cpu_op_569b(t_ipc *ipc) /* CLR */ {
953: /* mask fff8, bits 4260, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
954: int srcreg = (ipc->opcode >> 0) & 7;
955: uint32 srcaddr = ADDRREG(srcreg)-=2;
956: uint16 srcdata = fetchword(srcaddr);
957: uint16 outdata = 0;
958:
959: storeword(srcaddr, outdata);
960:
961: VFLAG = 0;
962: CFLAG = 0;
963: NFLAG = 0;
964: ZFLAG = 1;
965: PC+= 2;
966: }
967:
968: void cpu_op_570a(t_ipc *ipc) /* CLR */ {
969: /* mask fff8, bits 4268, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
970: int srcreg = (ipc->opcode >> 0) & 7;
971: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
972: uint16 srcdata = fetchword(srcaddr);
973: uint16 outdata = 0;
974:
975: storeword(srcaddr, outdata);
976: PC+= 4;
977: }
978:
979: void cpu_op_570b(t_ipc *ipc) /* CLR */ {
980: /* mask fff8, bits 4268, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
981: int srcreg = (ipc->opcode >> 0) & 7;
982: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
983: uint16 srcdata = fetchword(srcaddr);
984: uint16 outdata = 0;
985:
986: storeword(srcaddr, outdata);
987:
988: VFLAG = 0;
989: CFLAG = 0;
990: NFLAG = 0;
991: ZFLAG = 1;
992: PC+= 4;
993: }
994:
995: void cpu_op_571a(t_ipc *ipc) /* CLR */ {
996: /* mask fff8, bits 4270, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
997: int srcreg = (ipc->opcode >> 0) & 7;
998: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
999: uint16 srcdata = fetchword(srcaddr);
1000: uint16 outdata = 0;
1001:
1002: storeword(srcaddr, outdata);
1003: PC+= 4;
1004: }
1005:
1006: void cpu_op_571b(t_ipc *ipc) /* CLR */ {
1007: /* mask fff8, bits 4270, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1008: int srcreg = (ipc->opcode >> 0) & 7;
1009: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1010: uint16 srcdata = fetchword(srcaddr);
1011: uint16 outdata = 0;
1012:
1013: storeword(srcaddr, outdata);
1014:
1015: VFLAG = 0;
1016: CFLAG = 0;
1017: NFLAG = 0;
1018: ZFLAG = 1;
1019: PC+= 4;
1020: }
1021:
1022: void cpu_op_572a(t_ipc *ipc) /* CLR */ {
1023: /* mask ffff, bits 4278, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1024: uint32 srcaddr = ipc->src;
1025: uint16 srcdata = fetchword(srcaddr);
1026: uint16 outdata = 0;
1027:
1028: storeword(srcaddr, outdata);
1029: PC+= 4;
1030: }
1031:
1032: void cpu_op_572b(t_ipc *ipc) /* CLR */ {
1033: /* mask ffff, bits 4278, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1034: uint32 srcaddr = ipc->src;
1035: uint16 srcdata = fetchword(srcaddr);
1036: uint16 outdata = 0;
1037:
1038: storeword(srcaddr, outdata);
1039:
1040: VFLAG = 0;
1041: CFLAG = 0;
1042: NFLAG = 0;
1043: ZFLAG = 1;
1044: PC+= 4;
1045: }
1046:
1047: void cpu_op_573a(t_ipc *ipc) /* CLR */ {
1048: /* mask ffff, bits 4279, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1049: uint32 srcaddr = ipc->src;
1050: uint16 srcdata = fetchword(srcaddr);
1051: uint16 outdata = 0;
1052:
1053: storeword(srcaddr, outdata);
1054: PC+= 6;
1055: }
1056:
1057: void cpu_op_573b(t_ipc *ipc) /* CLR */ {
1058: /* mask ffff, bits 4279, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1059: uint32 srcaddr = ipc->src;
1060: uint16 srcdata = fetchword(srcaddr);
1061: uint16 outdata = 0;
1062:
1063: storeword(srcaddr, outdata);
1064:
1065: VFLAG = 0;
1066: CFLAG = 0;
1067: NFLAG = 0;
1068: ZFLAG = 1;
1069: PC+= 6;
1070: }
1071:
1072: void cpu_op_574a(t_ipc *ipc) /* CLR */ {
1073: /* mask fff8, bits 4280, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1074: int srcreg = (ipc->opcode >> 0) & 7;
1075: uint32 srcdata = DATAREG(srcreg);
1076: uint32 outdata = 0;
1077:
1078: DATAREG(srcreg) = outdata;
1079: PC+= 2;
1080: }
1081:
1082: void cpu_op_574b(t_ipc *ipc) /* CLR */ {
1083: /* mask fff8, bits 4280, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1084: int srcreg = (ipc->opcode >> 0) & 7;
1085: uint32 srcdata = DATAREG(srcreg);
1086: uint32 outdata = 0;
1087:
1088: DATAREG(srcreg) = outdata;
1089:
1090: VFLAG = 0;
1091: CFLAG = 0;
1092: NFLAG = 0;
1093: ZFLAG = 1;
1094: PC+= 2;
1095: }
1096:
1097: void cpu_op_575a(t_ipc *ipc) /* CLR */ {
1098: /* mask fff8, bits 4290, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1099: int srcreg = (ipc->opcode >> 0) & 7;
1100: uint32 srcaddr = ADDRREG(srcreg);
1101: uint32 srcdata = fetchlong(srcaddr);
1102: uint32 outdata = 0;
1103:
1104: storelong(srcaddr, outdata);
1105: PC+= 2;
1106: }
1107:
1108: void cpu_op_575b(t_ipc *ipc) /* CLR */ {
1109: /* mask fff8, bits 4290, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1110: int srcreg = (ipc->opcode >> 0) & 7;
1111: uint32 srcaddr = ADDRREG(srcreg);
1112: uint32 srcdata = fetchlong(srcaddr);
1113: uint32 outdata = 0;
1114:
1115: storelong(srcaddr, outdata);
1116:
1117: VFLAG = 0;
1118: CFLAG = 0;
1119: NFLAG = 0;
1120: ZFLAG = 1;
1121: PC+= 2;
1122: }
1123:
1124: void cpu_op_576a(t_ipc *ipc) /* CLR */ {
1125: /* mask fff8, bits 4298, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1126: int srcreg = (ipc->opcode >> 0) & 7;
1127: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4);
1128: uint32 srcdata = fetchlong(srcaddr);
1129: uint32 outdata = 0;
1130:
1131: storelong(srcaddr, outdata);
1132: PC+= 2;
1133: }
1134:
1135: void cpu_op_576b(t_ipc *ipc) /* CLR */ {
1136: /* mask fff8, bits 4298, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1137: int srcreg = (ipc->opcode >> 0) & 7;
1138: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4);
1139: uint32 srcdata = fetchlong(srcaddr);
1140: uint32 outdata = 0;
1141:
1142: storelong(srcaddr, outdata);
1143:
1144: VFLAG = 0;
1145: CFLAG = 0;
1146: NFLAG = 0;
1147: ZFLAG = 1;
1148: PC+= 2;
1149: }
1150:
1151: void cpu_op_577a(t_ipc *ipc) /* CLR */ {
1152: /* mask fff8, bits 42a0, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1153: int srcreg = (ipc->opcode >> 0) & 7;
1154: uint32 srcaddr = ADDRREG(srcreg)-=4;
1155: uint32 srcdata = fetchlong(srcaddr);
1156: uint32 outdata = 0;
1157:
1158: storelong(srcaddr, outdata);
1159: PC+= 2;
1160: }
1161:
1162: void cpu_op_577b(t_ipc *ipc) /* CLR */ {
1163: /* mask fff8, bits 42a0, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1164: int srcreg = (ipc->opcode >> 0) & 7;
1165: uint32 srcaddr = ADDRREG(srcreg)-=4;
1166: uint32 srcdata = fetchlong(srcaddr);
1167: uint32 outdata = 0;
1168:
1169: storelong(srcaddr, outdata);
1170:
1171: VFLAG = 0;
1172: CFLAG = 0;
1173: NFLAG = 0;
1174: ZFLAG = 1;
1175: PC+= 2;
1176: }
1177:
1178: void cpu_op_578a(t_ipc *ipc) /* CLR */ {
1179: /* mask fff8, bits 42a8, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1180: int srcreg = (ipc->opcode >> 0) & 7;
1181: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1182: uint32 srcdata = fetchlong(srcaddr);
1183: uint32 outdata = 0;
1184:
1185: storelong(srcaddr, outdata);
1186: PC+= 4;
1187: }
1188:
1189: void cpu_op_578b(t_ipc *ipc) /* CLR */ {
1190: /* mask fff8, bits 42a8, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1191: int srcreg = (ipc->opcode >> 0) & 7;
1192: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1193: uint32 srcdata = fetchlong(srcaddr);
1194: uint32 outdata = 0;
1195:
1196: storelong(srcaddr, outdata);
1197:
1198: VFLAG = 0;
1199: CFLAG = 0;
1200: NFLAG = 0;
1201: ZFLAG = 1;
1202: PC+= 4;
1203: }
1204:
1205: void cpu_op_579a(t_ipc *ipc) /* CLR */ {
1206: /* mask fff8, bits 42b0, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1207: int srcreg = (ipc->opcode >> 0) & 7;
1208: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1209: uint32 srcdata = fetchlong(srcaddr);
1210: uint32 outdata = 0;
1211:
1212: storelong(srcaddr, outdata);
1213: PC+= 4;
1214: }
1215:
1216: void cpu_op_579b(t_ipc *ipc) /* CLR */ {
1217: /* mask fff8, bits 42b0, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1218: int srcreg = (ipc->opcode >> 0) & 7;
1219: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1220: uint32 srcdata = fetchlong(srcaddr);
1221: uint32 outdata = 0;
1222:
1223: storelong(srcaddr, outdata);
1224:
1225: VFLAG = 0;
1226: CFLAG = 0;
1227: NFLAG = 0;
1228: ZFLAG = 1;
1229: PC+= 4;
1230: }
1231:
1232: void cpu_op_580a(t_ipc *ipc) /* CLR */ {
1233: /* mask ffff, bits 42b8, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1234: uint32 srcaddr = ipc->src;
1235: uint32 srcdata = fetchlong(srcaddr);
1236: uint32 outdata = 0;
1237:
1238: storelong(srcaddr, outdata);
1239: PC+= 4;
1240: }
1241:
1242: void cpu_op_580b(t_ipc *ipc) /* CLR */ {
1243: /* mask ffff, bits 42b8, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1244: uint32 srcaddr = ipc->src;
1245: uint32 srcdata = fetchlong(srcaddr);
1246: uint32 outdata = 0;
1247:
1248: storelong(srcaddr, outdata);
1249:
1250: VFLAG = 0;
1251: CFLAG = 0;
1252: NFLAG = 0;
1253: ZFLAG = 1;
1254: PC+= 4;
1255: }
1256:
1257: void cpu_op_581a(t_ipc *ipc) /* CLR */ {
1258: /* mask ffff, bits 42b9, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1259: uint32 srcaddr = ipc->src;
1260: uint32 srcdata = fetchlong(srcaddr);
1261: uint32 outdata = 0;
1262:
1263: storelong(srcaddr, outdata);
1264: PC+= 6;
1265: }
1266:
1267: void cpu_op_581b(t_ipc *ipc) /* CLR */ {
1268: /* mask ffff, bits 42b9, mnemonic 33, priv 0, endblk 0, imm_notzero 0, used -2 set -1, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1269: uint32 srcaddr = ipc->src;
1270: uint32 srcdata = fetchlong(srcaddr);
1271: uint32 outdata = 0;
1272:
1273: storelong(srcaddr, outdata);
1274:
1275: VFLAG = 0;
1276: CFLAG = 0;
1277: NFLAG = 0;
1278: ZFLAG = 1;
1279: PC+= 6;
1280: }
1281:
1282: void cpu_op_582a(t_ipc *ipc) /* NEG */ {
1283: /* mask fff8, bits 4400, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1284: int srcreg = (ipc->opcode >> 0) & 7;
1285: uint8 srcdata = DATAREG(srcreg);
1286: uint8 outdata = 0 - (sint8)srcdata;
1287:
1288: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
1289: PC+= 2;
1290: }
1291:
1292: void cpu_op_582b(t_ipc *ipc) /* NEG */ {
1293: /* mask fff8, bits 4400, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1294: int srcreg = (ipc->opcode >> 0) & 7;
1295: uint8 srcdata = DATAREG(srcreg);
1296: uint8 outdata = 0 - (sint8)srcdata;
1297:
1298: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
1299:
1300: VFLAG = (srcdata == (1u<<7));
1301: XFLAG = CFLAG = srcdata ? 1 : 0;
1302: NFLAG = ((sint8)outdata) < 0;
1303: ZFLAG = !outdata;
1304: PC+= 2;
1305: }
1306:
1307: void cpu_op_583a(t_ipc *ipc) /* NEG */ {
1308: /* mask fff8, bits 4410, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1309: int srcreg = (ipc->opcode >> 0) & 7;
1310: uint32 srcaddr = ADDRREG(srcreg);
1311: uint8 srcdata = fetchbyte(srcaddr);
1312: uint8 outdata = 0 - (sint8)srcdata;
1313:
1314: storebyte(srcaddr, outdata);
1315: PC+= 2;
1316: }
1317:
1318: void cpu_op_583b(t_ipc *ipc) /* NEG */ {
1319: /* mask fff8, bits 4410, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1320: int srcreg = (ipc->opcode >> 0) & 7;
1321: uint32 srcaddr = ADDRREG(srcreg);
1322: uint8 srcdata = fetchbyte(srcaddr);
1323: uint8 outdata = 0 - (sint8)srcdata;
1324:
1325: storebyte(srcaddr, outdata);
1326:
1327: VFLAG = (srcdata == (1u<<7));
1328: XFLAG = CFLAG = srcdata ? 1 : 0;
1329: NFLAG = ((sint8)outdata) < 0;
1330: ZFLAG = !outdata;
1331: PC+= 2;
1332: }
1333:
1334: void cpu_op_584a(t_ipc *ipc) /* NEG */ {
1335: /* mask fff8, bits 4418, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1336: int srcreg = (ipc->opcode >> 0) & 7;
1337: uint32 srcaddr = ADDRREG(srcreg);
1338: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
1339: uint8 srcdata = fetchbyte(srcaddr);
1340: uint8 outdata = 0 - (sint8)srcdata;
1341:
1342: storebyte(srcaddr, outdata);
1343: PC+= 2;
1344: }
1345:
1346: void cpu_op_584b(t_ipc *ipc) /* NEG */ {
1347: /* mask fff8, bits 4418, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1348: int srcreg = (ipc->opcode >> 0) & 7;
1349: uint32 srcaddr = ADDRREG(srcreg);
1350: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
1351: uint8 srcdata = fetchbyte(srcaddr);
1352: uint8 outdata = 0 - (sint8)srcdata;
1353:
1354: storebyte(srcaddr, outdata);
1355:
1356: VFLAG = (srcdata == (1u<<7));
1357: XFLAG = CFLAG = srcdata ? 1 : 0;
1358: NFLAG = ((sint8)outdata) < 0;
1359: ZFLAG = !outdata;
1360: PC+= 2;
1361: }
1362:
1363: void cpu_op_585a(t_ipc *ipc) /* NEG */ {
1364: /* mask fff8, bits 4420, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1365: int srcreg = (ipc->opcode >> 0) & 7;
1366: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1367: uint8 srcdata = fetchbyte(srcaddr);
1368: uint8 outdata = 0 - (sint8)srcdata;
1369:
1370: storebyte(srcaddr, outdata);
1371: PC+= 2;
1372: }
1373:
1374: void cpu_op_585b(t_ipc *ipc) /* NEG */ {
1375: /* mask fff8, bits 4420, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1376: int srcreg = (ipc->opcode >> 0) & 7;
1377: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1378: uint8 srcdata = fetchbyte(srcaddr);
1379: uint8 outdata = 0 - (sint8)srcdata;
1380:
1381: storebyte(srcaddr, outdata);
1382:
1383: VFLAG = (srcdata == (1u<<7));
1384: XFLAG = CFLAG = srcdata ? 1 : 0;
1385: NFLAG = ((sint8)outdata) < 0;
1386: ZFLAG = !outdata;
1387: PC+= 2;
1388: }
1389:
1390: void cpu_op_586a(t_ipc *ipc) /* NEG */ {
1391: /* mask fff8, bits 4428, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1392: int srcreg = (ipc->opcode >> 0) & 7;
1393: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1394: uint8 srcdata = fetchbyte(srcaddr);
1395: uint8 outdata = 0 - (sint8)srcdata;
1396:
1397: storebyte(srcaddr, outdata);
1398: PC+= 4;
1399: }
1400:
1401: void cpu_op_586b(t_ipc *ipc) /* NEG */ {
1402: /* mask fff8, bits 4428, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1403: int srcreg = (ipc->opcode >> 0) & 7;
1404: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1405: uint8 srcdata = fetchbyte(srcaddr);
1406: uint8 outdata = 0 - (sint8)srcdata;
1407:
1408: storebyte(srcaddr, outdata);
1409:
1410: VFLAG = (srcdata == (1u<<7));
1411: XFLAG = CFLAG = srcdata ? 1 : 0;
1412: NFLAG = ((sint8)outdata) < 0;
1413: ZFLAG = !outdata;
1414: PC+= 4;
1415: }
1416:
1417: void cpu_op_587a(t_ipc *ipc) /* NEG */ {
1418: /* mask fff8, bits 4430, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1419: int srcreg = (ipc->opcode >> 0) & 7;
1420: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1421: uint8 srcdata = fetchbyte(srcaddr);
1422: uint8 outdata = 0 - (sint8)srcdata;
1423:
1424: storebyte(srcaddr, outdata);
1425: PC+= 4;
1426: }
1427:
1428: void cpu_op_587b(t_ipc *ipc) /* NEG */ {
1429: /* mask fff8, bits 4430, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1430: int srcreg = (ipc->opcode >> 0) & 7;
1431: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1432: uint8 srcdata = fetchbyte(srcaddr);
1433: uint8 outdata = 0 - (sint8)srcdata;
1434:
1435: storebyte(srcaddr, outdata);
1436:
1437: VFLAG = (srcdata == (1u<<7));
1438: XFLAG = CFLAG = srcdata ? 1 : 0;
1439: NFLAG = ((sint8)outdata) < 0;
1440: ZFLAG = !outdata;
1441: PC+= 4;
1442: }
1443:
1444: void cpu_op_588a(t_ipc *ipc) /* NEG */ {
1445: /* mask ffff, bits 4438, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1446: uint32 srcaddr = ipc->src;
1447: uint8 srcdata = fetchbyte(srcaddr);
1448: uint8 outdata = 0 - (sint8)srcdata;
1449:
1450: storebyte(srcaddr, outdata);
1451: PC+= 4;
1452: }
1453:
1454: void cpu_op_588b(t_ipc *ipc) /* NEG */ {
1455: /* mask ffff, bits 4438, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1456: uint32 srcaddr = ipc->src;
1457: uint8 srcdata = fetchbyte(srcaddr);
1458: uint8 outdata = 0 - (sint8)srcdata;
1459:
1460: storebyte(srcaddr, outdata);
1461:
1462: VFLAG = (srcdata == (1u<<7));
1463: XFLAG = CFLAG = srcdata ? 1 : 0;
1464: NFLAG = ((sint8)outdata) < 0;
1465: ZFLAG = !outdata;
1466: PC+= 4;
1467: }
1468:
1469: void cpu_op_589a(t_ipc *ipc) /* NEG */ {
1470: /* mask ffff, bits 4439, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1471: uint32 srcaddr = ipc->src;
1472: uint8 srcdata = fetchbyte(srcaddr);
1473: uint8 outdata = 0 - (sint8)srcdata;
1474:
1475: storebyte(srcaddr, outdata);
1476: PC+= 6;
1477: }
1478:
1479: void cpu_op_589b(t_ipc *ipc) /* NEG */ {
1480: /* mask ffff, bits 4439, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1481: uint32 srcaddr = ipc->src;
1482: uint8 srcdata = fetchbyte(srcaddr);
1483: uint8 outdata = 0 - (sint8)srcdata;
1484:
1485: storebyte(srcaddr, outdata);
1486:
1487: VFLAG = (srcdata == (1u<<7));
1488: XFLAG = CFLAG = srcdata ? 1 : 0;
1489: NFLAG = ((sint8)outdata) < 0;
1490: ZFLAG = !outdata;
1491: PC+= 6;
1492: }
1493:
1494: void cpu_op_590a(t_ipc *ipc) /* NEG */ {
1495: /* mask fff8, bits 4440, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1496: int srcreg = (ipc->opcode >> 0) & 7;
1497: uint16 srcdata = DATAREG(srcreg);
1498: uint16 outdata = 0 - (sint16)srcdata;
1499:
1500: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xffff) | outdata;
1501: PC+= 2;
1502: }
1503:
1504: void cpu_op_590b(t_ipc *ipc) /* NEG */ {
1505: /* mask fff8, bits 4440, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1506: int srcreg = (ipc->opcode >> 0) & 7;
1507: uint16 srcdata = DATAREG(srcreg);
1508: uint16 outdata = 0 - (sint16)srcdata;
1509:
1510: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xffff) | outdata;
1511:
1512: VFLAG = (srcdata == (1u<<15));
1513: XFLAG = CFLAG = srcdata ? 1 : 0;
1514: NFLAG = ((sint16)outdata) < 0;
1515: ZFLAG = !outdata;
1516: PC+= 2;
1517: }
1518:
1519: void cpu_op_591a(t_ipc *ipc) /* NEG */ {
1520: /* mask fff8, bits 4450, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1521: int srcreg = (ipc->opcode >> 0) & 7;
1522: uint32 srcaddr = ADDRREG(srcreg);
1523: uint16 srcdata = fetchword(srcaddr);
1524: uint16 outdata = 0 - (sint16)srcdata;
1525:
1526: storeword(srcaddr, outdata);
1527: PC+= 2;
1528: }
1529:
1530: void cpu_op_591b(t_ipc *ipc) /* NEG */ {
1531: /* mask fff8, bits 4450, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1532: int srcreg = (ipc->opcode >> 0) & 7;
1533: uint32 srcaddr = ADDRREG(srcreg);
1534: uint16 srcdata = fetchword(srcaddr);
1535: uint16 outdata = 0 - (sint16)srcdata;
1536:
1537: storeword(srcaddr, outdata);
1538:
1539: VFLAG = (srcdata == (1u<<15));
1540: XFLAG = CFLAG = srcdata ? 1 : 0;
1541: NFLAG = ((sint16)outdata) < 0;
1542: ZFLAG = !outdata;
1543: PC+= 2;
1544: }
1545:
1546: void cpu_op_592a(t_ipc *ipc) /* NEG */ {
1547: /* mask fff8, bits 4458, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1548: int srcreg = (ipc->opcode >> 0) & 7;
1549: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
1550: uint16 srcdata = fetchword(srcaddr);
1551: uint16 outdata = 0 - (sint16)srcdata;
1552:
1553: storeword(srcaddr, outdata);
1554: PC+= 2;
1555: }
1556:
1557: void cpu_op_592b(t_ipc *ipc) /* NEG */ {
1558: /* mask fff8, bits 4458, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1559: int srcreg = (ipc->opcode >> 0) & 7;
1560: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
1561: uint16 srcdata = fetchword(srcaddr);
1562: uint16 outdata = 0 - (sint16)srcdata;
1563:
1564: storeword(srcaddr, outdata);
1565:
1566: VFLAG = (srcdata == (1u<<15));
1567: XFLAG = CFLAG = srcdata ? 1 : 0;
1568: NFLAG = ((sint16)outdata) < 0;
1569: ZFLAG = !outdata;
1570: PC+= 2;
1571: }
1572:
1573: void cpu_op_593a(t_ipc *ipc) /* NEG */ {
1574: /* mask fff8, bits 4460, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1575: int srcreg = (ipc->opcode >> 0) & 7;
1576: uint32 srcaddr = ADDRREG(srcreg)-=2;
1577: uint16 srcdata = fetchword(srcaddr);
1578: uint16 outdata = 0 - (sint16)srcdata;
1579:
1580: storeword(srcaddr, outdata);
1581: PC+= 2;
1582: }
1583:
1584: void cpu_op_593b(t_ipc *ipc) /* NEG */ {
1585: /* mask fff8, bits 4460, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1586: int srcreg = (ipc->opcode >> 0) & 7;
1587: uint32 srcaddr = ADDRREG(srcreg)-=2;
1588: uint16 srcdata = fetchword(srcaddr);
1589: uint16 outdata = 0 - (sint16)srcdata;
1590:
1591: storeword(srcaddr, outdata);
1592:
1593: VFLAG = (srcdata == (1u<<15));
1594: XFLAG = CFLAG = srcdata ? 1 : 0;
1595: NFLAG = ((sint16)outdata) < 0;
1596: ZFLAG = !outdata;
1597: PC+= 2;
1598: }
1599:
1600: void cpu_op_594a(t_ipc *ipc) /* NEG */ {
1601: /* mask fff8, bits 4468, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1602: int srcreg = (ipc->opcode >> 0) & 7;
1603: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1604: uint16 srcdata = fetchword(srcaddr);
1605: uint16 outdata = 0 - (sint16)srcdata;
1606:
1607: storeword(srcaddr, outdata);
1608: PC+= 4;
1609: }
1610:
1611: void cpu_op_594b(t_ipc *ipc) /* NEG */ {
1612: /* mask fff8, bits 4468, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1613: int srcreg = (ipc->opcode >> 0) & 7;
1614: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1615: uint16 srcdata = fetchword(srcaddr);
1616: uint16 outdata = 0 - (sint16)srcdata;
1617:
1618: storeword(srcaddr, outdata);
1619:
1620: VFLAG = (srcdata == (1u<<15));
1621: XFLAG = CFLAG = srcdata ? 1 : 0;
1622: NFLAG = ((sint16)outdata) < 0;
1623: ZFLAG = !outdata;
1624: PC+= 4;
1625: }
1626:
1627: void cpu_op_595a(t_ipc *ipc) /* NEG */ {
1628: /* mask fff8, bits 4470, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1629: int srcreg = (ipc->opcode >> 0) & 7;
1630: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1631: uint16 srcdata = fetchword(srcaddr);
1632: uint16 outdata = 0 - (sint16)srcdata;
1633:
1634: storeword(srcaddr, outdata);
1635: PC+= 4;
1636: }
1637:
1638: void cpu_op_595b(t_ipc *ipc) /* NEG */ {
1639: /* mask fff8, bits 4470, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1640: int srcreg = (ipc->opcode >> 0) & 7;
1641: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1642: uint16 srcdata = fetchword(srcaddr);
1643: uint16 outdata = 0 - (sint16)srcdata;
1644:
1645: storeword(srcaddr, outdata);
1646:
1647: VFLAG = (srcdata == (1u<<15));
1648: XFLAG = CFLAG = srcdata ? 1 : 0;
1649: NFLAG = ((sint16)outdata) < 0;
1650: ZFLAG = !outdata;
1651: PC+= 4;
1652: }
1653:
1654: void cpu_op_596a(t_ipc *ipc) /* NEG */ {
1655: /* mask ffff, bits 4478, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1656: uint32 srcaddr = ipc->src;
1657: uint16 srcdata = fetchword(srcaddr);
1658: uint16 outdata = 0 - (sint16)srcdata;
1659:
1660: storeword(srcaddr, outdata);
1661: PC+= 4;
1662: }
1663:
1664: void cpu_op_596b(t_ipc *ipc) /* NEG */ {
1665: /* mask ffff, bits 4478, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1666: uint32 srcaddr = ipc->src;
1667: uint16 srcdata = fetchword(srcaddr);
1668: uint16 outdata = 0 - (sint16)srcdata;
1669:
1670: storeword(srcaddr, outdata);
1671:
1672: VFLAG = (srcdata == (1u<<15));
1673: XFLAG = CFLAG = srcdata ? 1 : 0;
1674: NFLAG = ((sint16)outdata) < 0;
1675: ZFLAG = !outdata;
1676: PC+= 4;
1677: }
1678:
1679: void cpu_op_597a(t_ipc *ipc) /* NEG */ {
1680: /* mask ffff, bits 4479, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1681: uint32 srcaddr = ipc->src;
1682: uint16 srcdata = fetchword(srcaddr);
1683: uint16 outdata = 0 - (sint16)srcdata;
1684:
1685: storeword(srcaddr, outdata);
1686: PC+= 6;
1687: }
1688:
1689: void cpu_op_597b(t_ipc *ipc) /* NEG */ {
1690: /* mask ffff, bits 4479, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1691: uint32 srcaddr = ipc->src;
1692: uint16 srcdata = fetchword(srcaddr);
1693: uint16 outdata = 0 - (sint16)srcdata;
1694:
1695: storeword(srcaddr, outdata);
1696:
1697: VFLAG = (srcdata == (1u<<15));
1698: XFLAG = CFLAG = srcdata ? 1 : 0;
1699: NFLAG = ((sint16)outdata) < 0;
1700: ZFLAG = !outdata;
1701: PC+= 6;
1702: }
1703:
1704: void cpu_op_598a(t_ipc *ipc) /* NEG */ {
1705: /* mask fff8, bits 4480, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1706: int srcreg = (ipc->opcode >> 0) & 7;
1707: uint32 srcdata = DATAREG(srcreg);
1708: uint32 outdata = 0 - (sint32)srcdata;
1709:
1710: DATAREG(srcreg) = outdata;
1711: PC+= 2;
1712: }
1713:
1714: void cpu_op_598b(t_ipc *ipc) /* NEG */ {
1715: /* mask fff8, bits 4480, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1716: int srcreg = (ipc->opcode >> 0) & 7;
1717: uint32 srcdata = DATAREG(srcreg);
1718: uint32 outdata = 0 - (sint32)srcdata;
1719:
1720: DATAREG(srcreg) = outdata;
1721:
1722: VFLAG = (srcdata == (1u<<31));
1723: XFLAG = CFLAG = srcdata ? 1 : 0;
1724: NFLAG = ((sint32)outdata) < 0;
1725: ZFLAG = !outdata;
1726: PC+= 2;
1727: }
1728:
1729: void cpu_op_599a(t_ipc *ipc) /* NEG */ {
1730: /* mask fff8, bits 4490, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1731: int srcreg = (ipc->opcode >> 0) & 7;
1732: uint32 srcaddr = ADDRREG(srcreg);
1733: uint32 srcdata = fetchlong(srcaddr);
1734: uint32 outdata = 0 - (sint32)srcdata;
1735:
1736: storelong(srcaddr, outdata);
1737: PC+= 2;
1738: }
1739:
1740: void cpu_op_599b(t_ipc *ipc) /* NEG */ {
1741: /* mask fff8, bits 4490, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1742: int srcreg = (ipc->opcode >> 0) & 7;
1743: uint32 srcaddr = ADDRREG(srcreg);
1744: uint32 srcdata = fetchlong(srcaddr);
1745: uint32 outdata = 0 - (sint32)srcdata;
1746:
1747: storelong(srcaddr, outdata);
1748:
1749: VFLAG = (srcdata == (1u<<31));
1750: XFLAG = CFLAG = srcdata ? 1 : 0;
1751: NFLAG = ((sint32)outdata) < 0;
1752: ZFLAG = !outdata;
1753: PC+= 2;
1754: }
1755:
1756: void cpu_op_600a(t_ipc *ipc) /* NEG */ {
1757: /* mask fff8, bits 4498, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1758: int srcreg = (ipc->opcode >> 0) & 7;
1759: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4);
1760: uint32 srcdata = fetchlong(srcaddr);
1761: uint32 outdata = 0 - (sint32)srcdata;
1762:
1763: storelong(srcaddr, outdata);
1764: PC+= 2;
1765: }
1766:
1767: void cpu_op_600b(t_ipc *ipc) /* NEG */ {
1768: /* mask fff8, bits 4498, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1769: int srcreg = (ipc->opcode >> 0) & 7;
1770: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4);
1771: uint32 srcdata = fetchlong(srcaddr);
1772: uint32 outdata = 0 - (sint32)srcdata;
1773:
1774: storelong(srcaddr, outdata);
1775:
1776: VFLAG = (srcdata == (1u<<31));
1777: XFLAG = CFLAG = srcdata ? 1 : 0;
1778: NFLAG = ((sint32)outdata) < 0;
1779: ZFLAG = !outdata;
1780: PC+= 2;
1781: }
1782:
1783: void cpu_op_601a(t_ipc *ipc) /* NEG */ {
1784: /* mask fff8, bits 44a0, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1785: int srcreg = (ipc->opcode >> 0) & 7;
1786: uint32 srcaddr = ADDRREG(srcreg)-=4;
1787: uint32 srcdata = fetchlong(srcaddr);
1788: uint32 outdata = 0 - (sint32)srcdata;
1789:
1790: storelong(srcaddr, outdata);
1791: PC+= 2;
1792: }
1793:
1794: void cpu_op_601b(t_ipc *ipc) /* NEG */ {
1795: /* mask fff8, bits 44a0, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1796: int srcreg = (ipc->opcode >> 0) & 7;
1797: uint32 srcaddr = ADDRREG(srcreg)-=4;
1798: uint32 srcdata = fetchlong(srcaddr);
1799: uint32 outdata = 0 - (sint32)srcdata;
1800:
1801: storelong(srcaddr, outdata);
1802:
1803: VFLAG = (srcdata == (1u<<31));
1804: XFLAG = CFLAG = srcdata ? 1 : 0;
1805: NFLAG = ((sint32)outdata) < 0;
1806: ZFLAG = !outdata;
1807: PC+= 2;
1808: }
1809:
1810: void cpu_op_602a(t_ipc *ipc) /* NEG */ {
1811: /* mask fff8, bits 44a8, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1812: int srcreg = (ipc->opcode >> 0) & 7;
1813: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1814: uint32 srcdata = fetchlong(srcaddr);
1815: uint32 outdata = 0 - (sint32)srcdata;
1816:
1817: storelong(srcaddr, outdata);
1818: PC+= 4;
1819: }
1820:
1821: void cpu_op_602b(t_ipc *ipc) /* NEG */ {
1822: /* mask fff8, bits 44a8, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1823: int srcreg = (ipc->opcode >> 0) & 7;
1824: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
1825: uint32 srcdata = fetchlong(srcaddr);
1826: uint32 outdata = 0 - (sint32)srcdata;
1827:
1828: storelong(srcaddr, outdata);
1829:
1830: VFLAG = (srcdata == (1u<<31));
1831: XFLAG = CFLAG = srcdata ? 1 : 0;
1832: NFLAG = ((sint32)outdata) < 0;
1833: ZFLAG = !outdata;
1834: PC+= 4;
1835: }
1836:
1837: void cpu_op_603a(t_ipc *ipc) /* NEG */ {
1838: /* mask fff8, bits 44b0, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1839: int srcreg = (ipc->opcode >> 0) & 7;
1840: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1841: uint32 srcdata = fetchlong(srcaddr);
1842: uint32 outdata = 0 - (sint32)srcdata;
1843:
1844: storelong(srcaddr, outdata);
1845: PC+= 4;
1846: }
1847:
1848: void cpu_op_603b(t_ipc *ipc) /* NEG */ {
1849: /* mask fff8, bits 44b0, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1850: int srcreg = (ipc->opcode >> 0) & 7;
1851: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
1852: uint32 srcdata = fetchlong(srcaddr);
1853: uint32 outdata = 0 - (sint32)srcdata;
1854:
1855: storelong(srcaddr, outdata);
1856:
1857: VFLAG = (srcdata == (1u<<31));
1858: XFLAG = CFLAG = srcdata ? 1 : 0;
1859: NFLAG = ((sint32)outdata) < 0;
1860: ZFLAG = !outdata;
1861: PC+= 4;
1862: }
1863:
1864: void cpu_op_604a(t_ipc *ipc) /* NEG */ {
1865: /* mask ffff, bits 44b8, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1866: uint32 srcaddr = ipc->src;
1867: uint32 srcdata = fetchlong(srcaddr);
1868: uint32 outdata = 0 - (sint32)srcdata;
1869:
1870: storelong(srcaddr, outdata);
1871: PC+= 4;
1872: }
1873:
1874: void cpu_op_604b(t_ipc *ipc) /* NEG */ {
1875: /* mask ffff, bits 44b8, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1876: uint32 srcaddr = ipc->src;
1877: uint32 srcdata = fetchlong(srcaddr);
1878: uint32 outdata = 0 - (sint32)srcdata;
1879:
1880: storelong(srcaddr, outdata);
1881:
1882: VFLAG = (srcdata == (1u<<31));
1883: XFLAG = CFLAG = srcdata ? 1 : 0;
1884: NFLAG = ((sint32)outdata) < 0;
1885: ZFLAG = !outdata;
1886: PC+= 4;
1887: }
1888:
1889: void cpu_op_605a(t_ipc *ipc) /* NEG */ {
1890: /* mask ffff, bits 44b9, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1891: uint32 srcaddr = ipc->src;
1892: uint32 srcdata = fetchlong(srcaddr);
1893: uint32 outdata = 0 - (sint32)srcdata;
1894:
1895: storelong(srcaddr, outdata);
1896: PC+= 6;
1897: }
1898:
1899: void cpu_op_605b(t_ipc *ipc) /* NEG */ {
1900: /* mask ffff, bits 44b9, mnemonic 31, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1901: uint32 srcaddr = ipc->src;
1902: uint32 srcdata = fetchlong(srcaddr);
1903: uint32 outdata = 0 - (sint32)srcdata;
1904:
1905: storelong(srcaddr, outdata);
1906:
1907: VFLAG = (srcdata == (1u<<31));
1908: XFLAG = CFLAG = srcdata ? 1 : 0;
1909: NFLAG = ((sint32)outdata) < 0;
1910: ZFLAG = !outdata;
1911: PC+= 6;
1912: }
1913:
1914: void cpu_op_606a(t_ipc *ipc) /* NOT */ {
1915: /* mask fff8, bits 4600, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1916: int srcreg = (ipc->opcode >> 0) & 7;
1917: uint8 srcdata = DATAREG(srcreg);
1918: uint8 outdata = ~srcdata;
1919:
1920: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
1921: PC+= 2;
1922: }
1923:
1924: void cpu_op_606b(t_ipc *ipc) /* NOT */ {
1925: /* mask fff8, bits 4600, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1926: int srcreg = (ipc->opcode >> 0) & 7;
1927: uint8 srcdata = DATAREG(srcreg);
1928: uint8 outdata = ~srcdata;
1929:
1930: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
1931:
1932: VFLAG = 0;
1933: CFLAG = 0;
1934: NFLAG = ((sint8)outdata) < 0;
1935: ZFLAG = !outdata;
1936: PC+= 2;
1937: }
1938:
1939: void cpu_op_607a(t_ipc *ipc) /* NOT */ {
1940: /* mask fff8, bits 4610, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1941: int srcreg = (ipc->opcode >> 0) & 7;
1942: uint32 srcaddr = ADDRREG(srcreg);
1943: uint8 srcdata = fetchbyte(srcaddr);
1944: uint8 outdata = ~srcdata;
1945:
1946: storebyte(srcaddr, outdata);
1947: PC+= 2;
1948: }
1949:
1950: void cpu_op_607b(t_ipc *ipc) /* NOT */ {
1951: /* mask fff8, bits 4610, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1952: int srcreg = (ipc->opcode >> 0) & 7;
1953: uint32 srcaddr = ADDRREG(srcreg);
1954: uint8 srcdata = fetchbyte(srcaddr);
1955: uint8 outdata = ~srcdata;
1956:
1957: storebyte(srcaddr, outdata);
1958:
1959: VFLAG = 0;
1960: CFLAG = 0;
1961: NFLAG = ((sint8)outdata) < 0;
1962: ZFLAG = !outdata;
1963: PC+= 2;
1964: }
1965:
1966: void cpu_op_608a(t_ipc *ipc) /* NOT */ {
1967: /* mask fff8, bits 4618, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1968: int srcreg = (ipc->opcode >> 0) & 7;
1969: uint32 srcaddr = ADDRREG(srcreg);
1970: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
1971: uint8 srcdata = fetchbyte(srcaddr);
1972: uint8 outdata = ~srcdata;
1973:
1974: storebyte(srcaddr, outdata);
1975: PC+= 2;
1976: }
1977:
1978: void cpu_op_608b(t_ipc *ipc) /* NOT */ {
1979: /* mask fff8, bits 4618, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1980: int srcreg = (ipc->opcode >> 0) & 7;
1981: uint32 srcaddr = ADDRREG(srcreg);
1982: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
1983: uint8 srcdata = fetchbyte(srcaddr);
1984: uint8 outdata = ~srcdata;
1985:
1986: storebyte(srcaddr, outdata);
1987:
1988: VFLAG = 0;
1989: CFLAG = 0;
1990: NFLAG = ((sint8)outdata) < 0;
1991: ZFLAG = !outdata;
1992: PC+= 2;
1993: }
1994:
1995: void cpu_op_609a(t_ipc *ipc) /* NOT */ {
1996: /* mask fff8, bits 4620, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
1997: int srcreg = (ipc->opcode >> 0) & 7;
1998: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
1999: uint8 srcdata = fetchbyte(srcaddr);
2000: uint8 outdata = ~srcdata;
2001:
2002: storebyte(srcaddr, outdata);
2003: PC+= 2;
2004: }
2005:
2006: void cpu_op_609b(t_ipc *ipc) /* NOT */ {
2007: /* mask fff8, bits 4620, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2008: int srcreg = (ipc->opcode >> 0) & 7;
2009: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
2010: uint8 srcdata = fetchbyte(srcaddr);
2011: uint8 outdata = ~srcdata;
2012:
2013: storebyte(srcaddr, outdata);
2014:
2015: VFLAG = 0;
2016: CFLAG = 0;
2017: NFLAG = ((sint8)outdata) < 0;
2018: ZFLAG = !outdata;
2019: PC+= 2;
2020: }
2021:
2022: void cpu_op_610a(t_ipc *ipc) /* NOT */ {
2023: /* mask fff8, bits 4628, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2024: int srcreg = (ipc->opcode >> 0) & 7;
2025: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
2026: uint8 srcdata = fetchbyte(srcaddr);
2027: uint8 outdata = ~srcdata;
2028:
2029: storebyte(srcaddr, outdata);
2030: PC+= 4;
2031: }
2032:
2033: void cpu_op_610b(t_ipc *ipc) /* NOT */ {
2034: /* mask fff8, bits 4628, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2035: int srcreg = (ipc->opcode >> 0) & 7;
2036: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
2037: uint8 srcdata = fetchbyte(srcaddr);
2038: uint8 outdata = ~srcdata;
2039:
2040: storebyte(srcaddr, outdata);
2041:
2042: VFLAG = 0;
2043: CFLAG = 0;
2044: NFLAG = ((sint8)outdata) < 0;
2045: ZFLAG = !outdata;
2046: PC+= 4;
2047: }
2048:
2049: void cpu_op_611a(t_ipc *ipc) /* NOT */ {
2050: /* mask fff8, bits 4630, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2051: int srcreg = (ipc->opcode >> 0) & 7;
2052: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
2053: uint8 srcdata = fetchbyte(srcaddr);
2054: uint8 outdata = ~srcdata;
2055:
2056: storebyte(srcaddr, outdata);
2057: PC+= 4;
2058: }
2059:
2060: void cpu_op_611b(t_ipc *ipc) /* NOT */ {
2061: /* mask fff8, bits 4630, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2062: int srcreg = (ipc->opcode >> 0) & 7;
2063: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
2064: uint8 srcdata = fetchbyte(srcaddr);
2065: uint8 outdata = ~srcdata;
2066:
2067: storebyte(srcaddr, outdata);
2068:
2069: VFLAG = 0;
2070: CFLAG = 0;
2071: NFLAG = ((sint8)outdata) < 0;
2072: ZFLAG = !outdata;
2073: PC+= 4;
2074: }
2075:
2076: void cpu_op_612a(t_ipc *ipc) /* NOT */ {
2077: /* mask ffff, bits 4638, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2078: uint32 srcaddr = ipc->src;
2079: uint8 srcdata = fetchbyte(srcaddr);
2080: uint8 outdata = ~srcdata;
2081:
2082: storebyte(srcaddr, outdata);
2083: PC+= 4;
2084: }
2085:
2086: void cpu_op_612b(t_ipc *ipc) /* NOT */ {
2087: /* mask ffff, bits 4638, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2088: uint32 srcaddr = ipc->src;
2089: uint8 srcdata = fetchbyte(srcaddr);
2090: uint8 outdata = ~srcdata;
2091:
2092: storebyte(srcaddr, outdata);
2093:
2094: VFLAG = 0;
2095: CFLAG = 0;
2096: NFLAG = ((sint8)outdata) < 0;
2097: ZFLAG = !outdata;
2098: PC+= 4;
2099: }
2100:
2101: void cpu_op_613a(t_ipc *ipc) /* NOT */ {
2102: /* mask ffff, bits 4639, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2103: uint32 srcaddr = ipc->src;
2104: uint8 srcdata = fetchbyte(srcaddr);
2105: uint8 outdata = ~srcdata;
2106:
2107: storebyte(srcaddr, outdata);
2108: PC+= 6;
2109: }
2110:
2111: void cpu_op_613b(t_ipc *ipc) /* NOT */ {
2112: /* mask ffff, bits 4639, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2113: uint32 srcaddr = ipc->src;
2114: uint8 srcdata = fetchbyte(srcaddr);
2115: uint8 outdata = ~srcdata;
2116:
2117: storebyte(srcaddr, outdata);
2118:
2119: VFLAG = 0;
2120: CFLAG = 0;
2121: NFLAG = ((sint8)outdata) < 0;
2122: ZFLAG = !outdata;
2123: PC+= 6;
2124: }
2125:
2126: void cpu_op_614a(t_ipc *ipc) /* NOT */ {
2127: /* mask fff8, bits 4640, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2128: int srcreg = (ipc->opcode >> 0) & 7;
2129: uint16 srcdata = DATAREG(srcreg);
2130: uint16 outdata = ~srcdata;
2131:
2132: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xffff) | outdata;
2133: PC+= 2;
2134: }
2135:
2136: void cpu_op_614b(t_ipc *ipc) /* NOT */ {
2137: /* mask fff8, bits 4640, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2138: int srcreg = (ipc->opcode >> 0) & 7;
2139: uint16 srcdata = DATAREG(srcreg);
2140: uint16 outdata = ~srcdata;
2141:
2142: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xffff) | outdata;
2143:
2144: VFLAG = 0;
2145: CFLAG = 0;
2146: NFLAG = ((sint16)outdata) < 0;
2147: ZFLAG = !outdata;
2148: PC+= 2;
2149: }
2150:
2151: void cpu_op_615a(t_ipc *ipc) /* NOT */ {
2152: /* mask fff8, bits 4650, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2153: int srcreg = (ipc->opcode >> 0) & 7;
2154: uint32 srcaddr = ADDRREG(srcreg);
2155: uint16 srcdata = fetchword(srcaddr);
2156: uint16 outdata = ~srcdata;
2157:
2158: storeword(srcaddr, outdata);
2159: PC+= 2;
2160: }
2161:
2162: void cpu_op_615b(t_ipc *ipc) /* NOT */ {
2163: /* mask fff8, bits 4650, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2164: int srcreg = (ipc->opcode >> 0) & 7;
2165: uint32 srcaddr = ADDRREG(srcreg);
2166: uint16 srcdata = fetchword(srcaddr);
2167: uint16 outdata = ~srcdata;
2168:
2169: storeword(srcaddr, outdata);
2170:
2171: VFLAG = 0;
2172: CFLAG = 0;
2173: NFLAG = ((sint16)outdata) < 0;
2174: ZFLAG = !outdata;
2175: PC+= 2;
2176: }
2177:
2178: void cpu_op_616a(t_ipc *ipc) /* NOT */ {
2179: /* mask fff8, bits 4658, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2180: int srcreg = (ipc->opcode >> 0) & 7;
2181: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
2182: uint16 srcdata = fetchword(srcaddr);
2183: uint16 outdata = ~srcdata;
2184:
2185: storeword(srcaddr, outdata);
2186: PC+= 2;
2187: }
2188:
2189: void cpu_op_616b(t_ipc *ipc) /* NOT */ {
2190: /* mask fff8, bits 4658, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2191: int srcreg = (ipc->opcode >> 0) & 7;
2192: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
2193: uint16 srcdata = fetchword(srcaddr);
2194: uint16 outdata = ~srcdata;
2195:
2196: storeword(srcaddr, outdata);
2197:
2198: VFLAG = 0;
2199: CFLAG = 0;
2200: NFLAG = ((sint16)outdata) < 0;
2201: ZFLAG = !outdata;
2202: PC+= 2;
2203: }
2204:
2205: void cpu_op_617a(t_ipc *ipc) /* NOT */ {
2206: /* mask fff8, bits 4660, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2207: int srcreg = (ipc->opcode >> 0) & 7;
2208: uint32 srcaddr = ADDRREG(srcreg)-=2;
2209: uint16 srcdata = fetchword(srcaddr);
2210: uint16 outdata = ~srcdata;
2211:
2212: storeword(srcaddr, outdata);
2213: PC+= 2;
2214: }
2215:
2216: void cpu_op_617b(t_ipc *ipc) /* NOT */ {
2217: /* mask fff8, bits 4660, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2218: int srcreg = (ipc->opcode >> 0) & 7;
2219: uint32 srcaddr = ADDRREG(srcreg)-=2;
2220: uint16 srcdata = fetchword(srcaddr);
2221: uint16 outdata = ~srcdata;
2222:
2223: storeword(srcaddr, outdata);
2224:
2225: VFLAG = 0;
2226: CFLAG = 0;
2227: NFLAG = ((sint16)outdata) < 0;
2228: ZFLAG = !outdata;
2229: PC+= 2;
2230: }
2231:
2232: void cpu_op_618a(t_ipc *ipc) /* NOT */ {
2233: /* mask fff8, bits 4668, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2234: int srcreg = (ipc->opcode >> 0) & 7;
2235: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
2236: uint16 srcdata = fetchword(srcaddr);
2237: uint16 outdata = ~srcdata;
2238:
2239: storeword(srcaddr, outdata);
2240: PC+= 4;
2241: }
2242:
2243: void cpu_op_618b(t_ipc *ipc) /* NOT */ {
2244: /* mask fff8, bits 4668, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2245: int srcreg = (ipc->opcode >> 0) & 7;
2246: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
2247: uint16 srcdata = fetchword(srcaddr);
2248: uint16 outdata = ~srcdata;
2249:
2250: storeword(srcaddr, outdata);
2251:
2252: VFLAG = 0;
2253: CFLAG = 0;
2254: NFLAG = ((sint16)outdata) < 0;
2255: ZFLAG = !outdata;
2256: PC+= 4;
2257: }
2258:
2259: void cpu_op_619a(t_ipc *ipc) /* NOT */ {
2260: /* mask fff8, bits 4670, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2261: int srcreg = (ipc->opcode >> 0) & 7;
2262: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
2263: uint16 srcdata = fetchword(srcaddr);
2264: uint16 outdata = ~srcdata;
2265:
2266: storeword(srcaddr, outdata);
2267: PC+= 4;
2268: }
2269:
2270: void cpu_op_619b(t_ipc *ipc) /* NOT */ {
2271: /* mask fff8, bits 4670, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2272: int srcreg = (ipc->opcode >> 0) & 7;
2273: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
2274: uint16 srcdata = fetchword(srcaddr);
2275: uint16 outdata = ~srcdata;
2276:
2277: storeword(srcaddr, outdata);
2278:
2279: VFLAG = 0;
2280: CFLAG = 0;
2281: NFLAG = ((sint16)outdata) < 0;
2282: ZFLAG = !outdata;
2283: PC+= 4;
2284: }
2285:
2286: void cpu_op_620a(t_ipc *ipc) /* NOT */ {
2287: /* mask ffff, bits 4678, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2288: uint32 srcaddr = ipc->src;
2289: uint16 srcdata = fetchword(srcaddr);
2290: uint16 outdata = ~srcdata;
2291:
2292: storeword(srcaddr, outdata);
2293: PC+= 4;
2294: }
2295:
2296: void cpu_op_620b(t_ipc *ipc) /* NOT */ {
2297: /* mask ffff, bits 4678, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2298: uint32 srcaddr = ipc->src;
2299: uint16 srcdata = fetchword(srcaddr);
2300: uint16 outdata = ~srcdata;
2301:
2302: storeword(srcaddr, outdata);
2303:
2304: VFLAG = 0;
2305: CFLAG = 0;
2306: NFLAG = ((sint16)outdata) < 0;
2307: ZFLAG = !outdata;
2308: PC+= 4;
2309: }
2310:
2311: void cpu_op_621a(t_ipc *ipc) /* NOT */ {
2312: /* mask ffff, bits 4679, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2313: uint32 srcaddr = ipc->src;
2314: uint16 srcdata = fetchword(srcaddr);
2315: uint16 outdata = ~srcdata;
2316:
2317: storeword(srcaddr, outdata);
2318: PC+= 6;
2319: }
2320:
2321: void cpu_op_621b(t_ipc *ipc) /* NOT */ {
2322: /* mask ffff, bits 4679, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2323: uint32 srcaddr = ipc->src;
2324: uint16 srcdata = fetchword(srcaddr);
2325: uint16 outdata = ~srcdata;
2326:
2327: storeword(srcaddr, outdata);
2328:
2329: VFLAG = 0;
2330: CFLAG = 0;
2331: NFLAG = ((sint16)outdata) < 0;
2332: ZFLAG = !outdata;
2333: PC+= 6;
2334: }
2335:
2336: void cpu_op_622a(t_ipc *ipc) /* NOT */ {
2337: /* mask fff8, bits 4680, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2338: int srcreg = (ipc->opcode >> 0) & 7;
2339: uint32 srcdata = DATAREG(srcreg);
2340: uint32 outdata = ~srcdata;
2341:
2342: DATAREG(srcreg) = outdata;
2343: PC+= 2;
2344: }
2345:
2346: void cpu_op_622b(t_ipc *ipc) /* NOT */ {
2347: /* mask fff8, bits 4680, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2348: int srcreg = (ipc->opcode >> 0) & 7;
2349: uint32 srcdata = DATAREG(srcreg);
2350: uint32 outdata = ~srcdata;
2351:
2352: DATAREG(srcreg) = outdata;
2353:
2354: VFLAG = 0;
2355: CFLAG = 0;
2356: NFLAG = ((sint32)outdata) < 0;
2357: ZFLAG = !outdata;
2358: PC+= 2;
2359: }
2360:
2361: void cpu_op_623a(t_ipc *ipc) /* NOT */ {
2362: /* mask fff8, bits 4690, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2363: int srcreg = (ipc->opcode >> 0) & 7;
2364: uint32 srcaddr = ADDRREG(srcreg);
2365: uint32 srcdata = fetchlong(srcaddr);
2366: uint32 outdata = ~srcdata;
2367:
2368: storelong(srcaddr, outdata);
2369: PC+= 2;
2370: }
2371:
2372: void cpu_op_623b(t_ipc *ipc) /* NOT */ {
2373: /* mask fff8, bits 4690, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2374: int srcreg = (ipc->opcode >> 0) & 7;
2375: uint32 srcaddr = ADDRREG(srcreg);
2376: uint32 srcdata = fetchlong(srcaddr);
2377: uint32 outdata = ~srcdata;
2378:
2379: storelong(srcaddr, outdata);
2380:
2381: VFLAG = 0;
2382: CFLAG = 0;
2383: NFLAG = ((sint32)outdata) < 0;
2384: ZFLAG = !outdata;
2385: PC+= 2;
2386: }
2387:
2388: void cpu_op_624a(t_ipc *ipc) /* NOT */ {
2389: /* mask fff8, bits 4698, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2390: int srcreg = (ipc->opcode >> 0) & 7;
2391: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4);
2392: uint32 srcdata = fetchlong(srcaddr);
2393: uint32 outdata = ~srcdata;
2394:
2395: storelong(srcaddr, outdata);
2396: PC+= 2;
2397: }
2398:
2399: void cpu_op_624b(t_ipc *ipc) /* NOT */ {
2400: /* mask fff8, bits 4698, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2401: int srcreg = (ipc->opcode >> 0) & 7;
2402: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4);
2403: uint32 srcdata = fetchlong(srcaddr);
2404: uint32 outdata = ~srcdata;
2405:
2406: storelong(srcaddr, outdata);
2407:
2408: VFLAG = 0;
2409: CFLAG = 0;
2410: NFLAG = ((sint32)outdata) < 0;
2411: ZFLAG = !outdata;
2412: PC+= 2;
2413: }
2414:
2415: void cpu_op_625a(t_ipc *ipc) /* NOT */ {
2416: /* mask fff8, bits 46a0, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2417: int srcreg = (ipc->opcode >> 0) & 7;
2418: uint32 srcaddr = ADDRREG(srcreg)-=4;
2419: uint32 srcdata = fetchlong(srcaddr);
2420: uint32 outdata = ~srcdata;
2421:
2422: storelong(srcaddr, outdata);
2423: PC+= 2;
2424: }
2425:
2426: void cpu_op_625b(t_ipc *ipc) /* NOT */ {
2427: /* mask fff8, bits 46a0, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2428: int srcreg = (ipc->opcode >> 0) & 7;
2429: uint32 srcaddr = ADDRREG(srcreg)-=4;
2430: uint32 srcdata = fetchlong(srcaddr);
2431: uint32 outdata = ~srcdata;
2432:
2433: storelong(srcaddr, outdata);
2434:
2435: VFLAG = 0;
2436: CFLAG = 0;
2437: NFLAG = ((sint32)outdata) < 0;
2438: ZFLAG = !outdata;
2439: PC+= 2;
2440: }
2441:
2442: void cpu_op_626a(t_ipc *ipc) /* NOT */ {
2443: /* mask fff8, bits 46a8, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2444: int srcreg = (ipc->opcode >> 0) & 7;
2445: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
2446: uint32 srcdata = fetchlong(srcaddr);
2447: uint32 outdata = ~srcdata;
2448:
2449: storelong(srcaddr, outdata);
2450: PC+= 4;
2451: }
2452:
2453: void cpu_op_626b(t_ipc *ipc) /* NOT */ {
2454: /* mask fff8, bits 46a8, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2455: int srcreg = (ipc->opcode >> 0) & 7;
2456: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
2457: uint32 srcdata = fetchlong(srcaddr);
2458: uint32 outdata = ~srcdata;
2459:
2460: storelong(srcaddr, outdata);
2461:
2462: VFLAG = 0;
2463: CFLAG = 0;
2464: NFLAG = ((sint32)outdata) < 0;
2465: ZFLAG = !outdata;
2466: PC+= 4;
2467: }
2468:
2469: void cpu_op_627a(t_ipc *ipc) /* NOT */ {
2470: /* mask fff8, bits 46b0, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2471: int srcreg = (ipc->opcode >> 0) & 7;
2472: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
2473: uint32 srcdata = fetchlong(srcaddr);
2474: uint32 outdata = ~srcdata;
2475:
2476: storelong(srcaddr, outdata);
2477: PC+= 4;
2478: }
2479:
2480: void cpu_op_627b(t_ipc *ipc) /* NOT */ {
2481: /* mask fff8, bits 46b0, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2482: int srcreg = (ipc->opcode >> 0) & 7;
2483: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
2484: uint32 srcdata = fetchlong(srcaddr);
2485: uint32 outdata = ~srcdata;
2486:
2487: storelong(srcaddr, outdata);
2488:
2489: VFLAG = 0;
2490: CFLAG = 0;
2491: NFLAG = ((sint32)outdata) < 0;
2492: ZFLAG = !outdata;
2493: PC+= 4;
2494: }
2495:
2496: void cpu_op_628a(t_ipc *ipc) /* NOT */ {
2497: /* mask ffff, bits 46b8, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2498: uint32 srcaddr = ipc->src;
2499: uint32 srcdata = fetchlong(srcaddr);
2500: uint32 outdata = ~srcdata;
2501:
2502: storelong(srcaddr, outdata);
2503: PC+= 4;
2504: }
2505:
2506: void cpu_op_628b(t_ipc *ipc) /* NOT */ {
2507: /* mask ffff, bits 46b8, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2508: uint32 srcaddr = ipc->src;
2509: uint32 srcdata = fetchlong(srcaddr);
2510: uint32 outdata = ~srcdata;
2511:
2512: storelong(srcaddr, outdata);
2513:
2514: VFLAG = 0;
2515: CFLAG = 0;
2516: NFLAG = ((sint32)outdata) < 0;
2517: ZFLAG = !outdata;
2518: PC+= 4;
2519: }
2520:
2521: void cpu_op_629a(t_ipc *ipc) /* NOT */ {
2522: /* mask ffff, bits 46b9, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2523: uint32 srcaddr = ipc->src;
2524: uint32 srcdata = fetchlong(srcaddr);
2525: uint32 outdata = ~srcdata;
2526:
2527: storelong(srcaddr, outdata);
2528: PC+= 6;
2529: }
2530:
2531: void cpu_op_629b(t_ipc *ipc) /* NOT */ {
2532: /* mask ffff, bits 46b9, mnemonic 34, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2533: uint32 srcaddr = ipc->src;
2534: uint32 srcdata = fetchlong(srcaddr);
2535: uint32 outdata = ~srcdata;
2536:
2537: storelong(srcaddr, outdata);
2538:
2539: VFLAG = 0;
2540: CFLAG = 0;
2541: NFLAG = ((sint32)outdata) < 0;
2542: ZFLAG = !outdata;
2543: PC+= 6;
2544: }
2545:
2546: void cpu_op_630a(t_ipc *ipc) /* MOVEFSR */ {
2547: /* mask fff8, bits 40c0, mnemonic 25, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2548: int srcreg = (ipc->opcode >> 0) & 7;
2549: uint16 outdata;
2550:
2551: outdata = SR;
2552: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xffff) | outdata;
2553: PC+= 2;
2554: }
2555:
2556: void cpu_op_631a(t_ipc *ipc) /* MOVEFSR */ {
2557: /* mask fff8, bits 40d0, mnemonic 25, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2558: int srcreg = (ipc->opcode >> 0) & 7;
2559: uint32 srcaddr = ADDRREG(srcreg);
2560: uint16 outdata;
2561:
2562: outdata = SR;
2563: storeword(srcaddr, outdata);
2564: PC+= 2;
2565: }
2566:
2567: void cpu_op_632a(t_ipc *ipc) /* MOVEFSR */ {
2568: /* mask fff8, bits 40d8, mnemonic 25, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2569: int srcreg = (ipc->opcode >> 0) & 7;
2570: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
2571: uint16 outdata;
2572:
2573: outdata = SR;
2574: storeword(srcaddr, outdata);
2575: PC+= 2;
2576: }
2577:
2578: void cpu_op_633a(t_ipc *ipc) /* MOVEFSR */ {
2579: /* mask fff8, bits 40e0, mnemonic 25, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2580: int srcreg = (ipc->opcode >> 0) & 7;
2581: uint32 srcaddr = ADDRREG(srcreg)-=2;
2582: uint16 outdata;
2583:
2584: outdata = SR;
2585: storeword(srcaddr, outdata);
2586: PC+= 2;
2587: }
2588:
2589: void cpu_op_634a(t_ipc *ipc) /* MOVEFSR */ {
2590: /* mask fff8, bits 40e8, mnemonic 25, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2591: int srcreg = (ipc->opcode >> 0) & 7;
2592: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
2593: uint16 outdata;
2594:
2595: outdata = SR;
2596: storeword(srcaddr, outdata);
2597: PC+= 4;
2598: }
2599:
2600: void cpu_op_635a(t_ipc *ipc) /* MOVEFSR */ {
2601: /* mask fff8, bits 40f0, mnemonic 25, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2602: int srcreg = (ipc->opcode >> 0) & 7;
2603: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
2604: uint16 outdata;
2605:
2606: outdata = SR;
2607: storeword(srcaddr, outdata);
2608: PC+= 4;
2609: }
2610:
2611: void cpu_op_636a(t_ipc *ipc) /* MOVEFSR */ {
2612: /* mask ffff, bits 40f8, mnemonic 25, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2613: uint32 srcaddr = ipc->src;
2614: uint16 outdata;
2615:
2616: outdata = SR;
2617: storeword(srcaddr, outdata);
2618: PC+= 4;
2619: }
2620:
2621: void cpu_op_637a(t_ipc *ipc) /* MOVEFSR */ {
2622: /* mask ffff, bits 40f9, mnemonic 25, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2623: uint32 srcaddr = ipc->src;
2624: uint16 outdata;
2625:
2626: outdata = SR;
2627: storeword(srcaddr, outdata);
2628: PC+= 6;
2629: }
2630:
2631: void cpu_op_638a(t_ipc *ipc) /* MOVETSR */ {
2632: /* mask fff8, bits 44c0, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2633: int srcreg = (ipc->opcode >> 0) & 7;
2634: uint8 srcdata = DATAREG(srcreg);
2635: unsigned int sr = reg68k_sr.sr_struct.s;
2636:
2637: SR = (SR & ~0xFF) | srcdata;
2638: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2639: /* mode change, swap SP and A7 */
2640: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2641: }
2642: PC+= 2;
2643: }
2644:
2645: void cpu_op_638b(t_ipc *ipc) /* MOVETSR */ {
2646: /* mask fff8, bits 44c0, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2647: int srcreg = (ipc->opcode >> 0) & 7;
2648: uint8 srcdata = DATAREG(srcreg);
2649: unsigned int sr = reg68k_sr.sr_struct.s;
2650:
2651: SR = (SR & ~0xFF) | srcdata;
2652: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2653: /* mode change, swap SP and A7 */
2654: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2655: }
2656: PC+= 2;
2657: }
2658:
2659: void cpu_op_639a(t_ipc *ipc) /* MOVETSR */ {
2660: /* mask fff8, bits 44d0, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2661: int srcreg = (ipc->opcode >> 0) & 7;
2662: uint32 srcaddr = ADDRREG(srcreg);
2663: uint8 srcdata = fetchbyte(srcaddr);
2664: unsigned int sr = reg68k_sr.sr_struct.s;
2665:
2666: SR = (SR & ~0xFF) | srcdata;
2667: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2668: /* mode change, swap SP and A7 */
2669: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2670: }
2671: PC+= 2;
2672: }
2673:
2674: void cpu_op_639b(t_ipc *ipc) /* MOVETSR */ {
2675: /* mask fff8, bits 44d0, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2676: int srcreg = (ipc->opcode >> 0) & 7;
2677: uint32 srcaddr = ADDRREG(srcreg);
2678: uint8 srcdata = fetchbyte(srcaddr);
2679: unsigned int sr = reg68k_sr.sr_struct.s;
2680:
2681: SR = (SR & ~0xFF) | srcdata;
2682: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2683: /* mode change, swap SP and A7 */
2684: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2685: }
2686: PC+= 2;
2687: }
2688:
2689: void cpu_op_640a(t_ipc *ipc) /* MOVETSR */ {
2690: /* mask fff8, bits 44d8, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2691: int srcreg = (ipc->opcode >> 0) & 7;
2692: uint32 srcaddr = ADDRREG(srcreg);
2693: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
2694: uint8 srcdata = fetchbyte(srcaddr);
2695: unsigned int sr = reg68k_sr.sr_struct.s;
2696:
2697: SR = (SR & ~0xFF) | srcdata;
2698: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2699: /* mode change, swap SP and A7 */
2700: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2701: }
2702: PC+= 2;
2703: }
2704:
2705: void cpu_op_640b(t_ipc *ipc) /* MOVETSR */ {
2706: /* mask fff8, bits 44d8, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2707: int srcreg = (ipc->opcode >> 0) & 7;
2708: uint32 srcaddr = ADDRREG(srcreg);
2709: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
2710: uint8 srcdata = fetchbyte(srcaddr);
2711: unsigned int sr = reg68k_sr.sr_struct.s;
2712:
2713: SR = (SR & ~0xFF) | srcdata;
2714: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2715: /* mode change, swap SP and A7 */
2716: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2717: }
2718: PC+= 2;
2719: }
2720:
2721: void cpu_op_641a(t_ipc *ipc) /* MOVETSR */ {
2722: /* mask fff8, bits 44e0, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2723: int srcreg = (ipc->opcode >> 0) & 7;
2724: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
2725: uint8 srcdata = fetchbyte(srcaddr);
2726: unsigned int sr = reg68k_sr.sr_struct.s;
2727:
2728: SR = (SR & ~0xFF) | srcdata;
2729: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2730: /* mode change, swap SP and A7 */
2731: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2732: }
2733: PC+= 2;
2734: }
2735:
2736: void cpu_op_641b(t_ipc *ipc) /* MOVETSR */ {
2737: /* mask fff8, bits 44e0, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2738: int srcreg = (ipc->opcode >> 0) & 7;
2739: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
2740: uint8 srcdata = fetchbyte(srcaddr);
2741: unsigned int sr = reg68k_sr.sr_struct.s;
2742:
2743: SR = (SR & ~0xFF) | srcdata;
2744: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2745: /* mode change, swap SP and A7 */
2746: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2747: }
2748: PC+= 2;
2749: }
2750:
2751: void cpu_op_642a(t_ipc *ipc) /* MOVETSR */ {
2752: /* mask fff8, bits 44e8, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2753: int srcreg = (ipc->opcode >> 0) & 7;
2754: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
2755: uint8 srcdata = fetchbyte(srcaddr);
2756: unsigned int sr = reg68k_sr.sr_struct.s;
2757:
2758: SR = (SR & ~0xFF) | srcdata;
2759: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2760: /* mode change, swap SP and A7 */
2761: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2762: }
2763: PC+= 4;
2764: }
2765:
2766: void cpu_op_642b(t_ipc *ipc) /* MOVETSR */ {
2767: /* mask fff8, bits 44e8, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2768: int srcreg = (ipc->opcode >> 0) & 7;
2769: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
2770: uint8 srcdata = fetchbyte(srcaddr);
2771: unsigned int sr = reg68k_sr.sr_struct.s;
2772:
2773: SR = (SR & ~0xFF) | srcdata;
2774: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2775: /* mode change, swap SP and A7 */
2776: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2777: }
2778: PC+= 4;
2779: }
2780:
2781: void cpu_op_643a(t_ipc *ipc) /* MOVETSR */ {
2782: /* mask fff8, bits 44f0, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2783: int srcreg = (ipc->opcode >> 0) & 7;
2784: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
2785: uint8 srcdata = fetchbyte(srcaddr);
2786: unsigned int sr = reg68k_sr.sr_struct.s;
2787:
2788: SR = (SR & ~0xFF) | srcdata;
2789: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2790: /* mode change, swap SP and A7 */
2791: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2792: }
2793: PC+= 4;
2794: }
2795:
2796: void cpu_op_643b(t_ipc *ipc) /* MOVETSR */ {
2797: /* mask fff8, bits 44f0, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2798: int srcreg = (ipc->opcode >> 0) & 7;
2799: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
2800: uint8 srcdata = fetchbyte(srcaddr);
2801: unsigned int sr = reg68k_sr.sr_struct.s;
2802:
2803: SR = (SR & ~0xFF) | srcdata;
2804: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2805: /* mode change, swap SP and A7 */
2806: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2807: }
2808: PC+= 4;
2809: }
2810:
2811: void cpu_op_644a(t_ipc *ipc) /* MOVETSR */ {
2812: /* mask ffff, bits 44f8, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2813: uint32 srcaddr = ipc->src;
2814: uint8 srcdata = fetchbyte(srcaddr);
2815: unsigned int sr = reg68k_sr.sr_struct.s;
2816:
2817: SR = (SR & ~0xFF) | srcdata;
2818: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2819: /* mode change, swap SP and A7 */
2820: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2821: }
2822: PC+= 4;
2823: }
2824:
2825: void cpu_op_644b(t_ipc *ipc) /* MOVETSR */ {
2826: /* mask ffff, bits 44f8, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2827: uint32 srcaddr = ipc->src;
2828: uint8 srcdata = fetchbyte(srcaddr);
2829: unsigned int sr = reg68k_sr.sr_struct.s;
2830:
2831: SR = (SR & ~0xFF) | srcdata;
2832: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2833: /* mode change, swap SP and A7 */
2834: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2835: }
2836: PC+= 4;
2837: }
2838:
2839: void cpu_op_645a(t_ipc *ipc) /* MOVETSR */ {
2840: /* mask ffff, bits 44f9, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2841: uint32 srcaddr = ipc->src;
2842: uint8 srcdata = fetchbyte(srcaddr);
2843: unsigned int sr = reg68k_sr.sr_struct.s;
2844:
2845: SR = (SR & ~0xFF) | srcdata;
2846: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2847: /* mode change, swap SP and A7 */
2848: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2849: }
2850: PC+= 6;
2851: }
2852:
2853: void cpu_op_645b(t_ipc *ipc) /* MOVETSR */ {
2854: /* mask ffff, bits 44f9, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2855: uint32 srcaddr = ipc->src;
2856: uint8 srcdata = fetchbyte(srcaddr);
2857: unsigned int sr = reg68k_sr.sr_struct.s;
2858:
2859: SR = (SR & ~0xFF) | srcdata;
2860: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2861: /* mode change, swap SP and A7 */
2862: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2863: }
2864: PC+= 6;
2865: }
2866:
2867: void cpu_op_646a(t_ipc *ipc) /* MOVETSR */ {
2868: /* mask ffff, bits 44fa, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 9, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2869: uint32 srcaddr = ipc->src;
2870: uint8 srcdata = fetchbyte(srcaddr);
2871: unsigned int sr = reg68k_sr.sr_struct.s;
2872:
2873: SR = (SR & ~0xFF) | srcdata;
2874: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2875: /* mode change, swap SP and A7 */
2876: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2877: }
2878: PC+= 4;
2879: }
2880:
2881: void cpu_op_646b(t_ipc *ipc) /* MOVETSR */ {
2882: /* mask ffff, bits 44fa, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 9, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2883: uint32 srcaddr = ipc->src;
2884: uint8 srcdata = fetchbyte(srcaddr);
2885: unsigned int sr = reg68k_sr.sr_struct.s;
2886:
2887: SR = (SR & ~0xFF) | srcdata;
2888: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2889: /* mode change, swap SP and A7 */
2890: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2891: }
2892: PC+= 4;
2893: }
2894:
2895: void cpu_op_647a(t_ipc *ipc) /* MOVETSR */ {
2896: /* mask ffff, bits 44fb, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 10, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2897: uint32 srcaddr = idxval_src(ipc);
2898: uint8 srcdata = fetchbyte(srcaddr);
2899: unsigned int sr = reg68k_sr.sr_struct.s;
2900:
2901: SR = (SR & ~0xFF) | srcdata;
2902: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2903: /* mode change, swap SP and A7 */
2904: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2905: }
2906: PC+= 4;
2907: }
2908:
2909: void cpu_op_647b(t_ipc *ipc) /* MOVETSR */ {
2910: /* mask ffff, bits 44fb, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 10, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2911: uint32 srcaddr = idxval_src(ipc);
2912: uint8 srcdata = fetchbyte(srcaddr);
2913: unsigned int sr = reg68k_sr.sr_struct.s;
2914:
2915: SR = (SR & ~0xFF) | srcdata;
2916: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2917: /* mode change, swap SP and A7 */
2918: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2919: }
2920: PC+= 4;
2921: }
2922:
2923: void cpu_op_648a(t_ipc *ipc) /* MOVETSR */ {
2924: /* mask ffff, bits 44fc, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2925: uint8 srcdata = ipc->src;
2926: unsigned int sr = reg68k_sr.sr_struct.s;
2927:
2928: SR = (SR & ~0xFF) | srcdata;
2929: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2930: /* mode change, swap SP and A7 */
2931: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2932: }
2933: PC+= 4;
2934: }
2935:
2936: void cpu_op_648b(t_ipc *ipc) /* MOVETSR */ {
2937: /* mask ffff, bits 44fc, mnemonic 26, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2938: uint8 srcdata = ipc->src;
2939: unsigned int sr = reg68k_sr.sr_struct.s;
2940:
2941: SR = (SR & ~0xFF) | srcdata;
2942: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2943: /* mode change, swap SP and A7 */
2944: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2945: }
2946: PC+= 4;
2947: }
2948:
2949: void cpu_op_649a(t_ipc *ipc) /* MOVETSR */ {
2950: /* mask fff8, bits 46c0, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2951: int srcreg = (ipc->opcode >> 0) & 7;
2952: uint16 srcdata = DATAREG(srcreg);
2953: unsigned int sr = reg68k_sr.sr_struct.s;
2954:
2955: if (!SFLAG)
2956: reg68k_vector(V_PRIVILEGE, PC+2);
2957:
2958: SR = srcdata;
2959: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2960: /* mode change, swap SP and A7 */
2961: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2962: }
2963: PC+= 2;
2964: }
2965:
2966: void cpu_op_649b(t_ipc *ipc) /* MOVETSR */ {
2967: /* mask fff8, bits 46c0, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2968: int srcreg = (ipc->opcode >> 0) & 7;
2969: uint16 srcdata = DATAREG(srcreg);
2970: unsigned int sr = reg68k_sr.sr_struct.s;
2971:
2972: if (!SFLAG)
2973: reg68k_vector(V_PRIVILEGE, PC+2);
2974:
2975: SR = srcdata;
2976: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2977: /* mode change, swap SP and A7 */
2978: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2979: }
2980: PC+= 2;
2981: }
2982:
2983: void cpu_op_650a(t_ipc *ipc) /* MOVETSR */ {
2984: /* mask fff8, bits 46d0, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2985: int srcreg = (ipc->opcode >> 0) & 7;
2986: uint32 srcaddr = ADDRREG(srcreg);
2987: uint16 srcdata = fetchword(srcaddr);
2988: unsigned int sr = reg68k_sr.sr_struct.s;
2989:
2990: if (!SFLAG)
2991: reg68k_vector(V_PRIVILEGE, PC+2);
2992:
2993: SR = srcdata;
2994: if (sr != (uint8)reg68k_sr.sr_struct.s) {
2995: /* mode change, swap SP and A7 */
2996: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
2997: }
2998: PC+= 2;
2999: }
3000:
3001: void cpu_op_650b(t_ipc *ipc) /* MOVETSR */ {
3002: /* mask fff8, bits 46d0, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3003: int srcreg = (ipc->opcode >> 0) & 7;
3004: uint32 srcaddr = ADDRREG(srcreg);
3005: uint16 srcdata = fetchword(srcaddr);
3006: unsigned int sr = reg68k_sr.sr_struct.s;
3007:
3008: if (!SFLAG)
3009: reg68k_vector(V_PRIVILEGE, PC+2);
3010:
3011: SR = srcdata;
3012: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3013: /* mode change, swap SP and A7 */
3014: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3015: }
3016: PC+= 2;
3017: }
3018:
3019: void cpu_op_651a(t_ipc *ipc) /* MOVETSR */ {
3020: /* mask fff8, bits 46d8, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3021: int srcreg = (ipc->opcode >> 0) & 7;
3022: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
3023: uint16 srcdata = fetchword(srcaddr);
3024: unsigned int sr = reg68k_sr.sr_struct.s;
3025:
3026: if (!SFLAG)
3027: reg68k_vector(V_PRIVILEGE, PC+2);
3028:
3029: SR = srcdata;
3030: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3031: /* mode change, swap SP and A7 */
3032: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3033: }
3034: PC+= 2;
3035: }
3036:
3037: void cpu_op_651b(t_ipc *ipc) /* MOVETSR */ {
3038: /* mask fff8, bits 46d8, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3039: int srcreg = (ipc->opcode >> 0) & 7;
3040: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
3041: uint16 srcdata = fetchword(srcaddr);
3042: unsigned int sr = reg68k_sr.sr_struct.s;
3043:
3044: if (!SFLAG)
3045: reg68k_vector(V_PRIVILEGE, PC+2);
3046:
3047: SR = srcdata;
3048: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3049: /* mode change, swap SP and A7 */
3050: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3051: }
3052: PC+= 2;
3053: }
3054:
3055: void cpu_op_652a(t_ipc *ipc) /* MOVETSR */ {
3056: /* mask fff8, bits 46e0, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3057: int srcreg = (ipc->opcode >> 0) & 7;
3058: uint32 srcaddr = ADDRREG(srcreg)-=2;
3059: uint16 srcdata = fetchword(srcaddr);
3060: unsigned int sr = reg68k_sr.sr_struct.s;
3061:
3062: if (!SFLAG)
3063: reg68k_vector(V_PRIVILEGE, PC+2);
3064:
3065: SR = srcdata;
3066: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3067: /* mode change, swap SP and A7 */
3068: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3069: }
3070: PC+= 2;
3071: }
3072:
3073: void cpu_op_652b(t_ipc *ipc) /* MOVETSR */ {
3074: /* mask fff8, bits 46e0, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3075: int srcreg = (ipc->opcode >> 0) & 7;
3076: uint32 srcaddr = ADDRREG(srcreg)-=2;
3077: uint16 srcdata = fetchword(srcaddr);
3078: unsigned int sr = reg68k_sr.sr_struct.s;
3079:
3080: if (!SFLAG)
3081: reg68k_vector(V_PRIVILEGE, PC+2);
3082:
3083: SR = srcdata;
3084: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3085: /* mode change, swap SP and A7 */
3086: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3087: }
3088: PC+= 2;
3089: }
3090:
3091: void cpu_op_653a(t_ipc *ipc) /* MOVETSR */ {
3092: /* mask fff8, bits 46e8, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3093: int srcreg = (ipc->opcode >> 0) & 7;
3094: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3095: uint16 srcdata = fetchword(srcaddr);
3096: unsigned int sr = reg68k_sr.sr_struct.s;
3097:
3098: if (!SFLAG)
3099: reg68k_vector(V_PRIVILEGE, PC+4);
3100:
3101: SR = srcdata;
3102: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3103: /* mode change, swap SP and A7 */
3104: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3105: }
3106: PC+= 4;
3107: }
3108:
3109: void cpu_op_653b(t_ipc *ipc) /* MOVETSR */ {
3110: /* mask fff8, bits 46e8, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3111: int srcreg = (ipc->opcode >> 0) & 7;
3112: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3113: uint16 srcdata = fetchword(srcaddr);
3114: unsigned int sr = reg68k_sr.sr_struct.s;
3115:
3116: if (!SFLAG)
3117: reg68k_vector(V_PRIVILEGE, PC+4);
3118:
3119: SR = srcdata;
3120: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3121: /* mode change, swap SP and A7 */
3122: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3123: }
3124: PC+= 4;
3125: }
3126:
3127: void cpu_op_654a(t_ipc *ipc) /* MOVETSR */ {
3128: /* mask fff8, bits 46f0, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3129: int srcreg = (ipc->opcode >> 0) & 7;
3130: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3131: uint16 srcdata = fetchword(srcaddr);
3132: unsigned int sr = reg68k_sr.sr_struct.s;
3133:
3134: if (!SFLAG)
3135: reg68k_vector(V_PRIVILEGE, PC+4);
3136:
3137: SR = srcdata;
3138: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3139: /* mode change, swap SP and A7 */
3140: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3141: }
3142: PC+= 4;
3143: }
3144:
3145: void cpu_op_654b(t_ipc *ipc) /* MOVETSR */ {
3146: /* mask fff8, bits 46f0, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3147: int srcreg = (ipc->opcode >> 0) & 7;
3148: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3149: uint16 srcdata = fetchword(srcaddr);
3150: unsigned int sr = reg68k_sr.sr_struct.s;
3151:
3152: if (!SFLAG)
3153: reg68k_vector(V_PRIVILEGE, PC+4);
3154:
3155: SR = srcdata;
3156: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3157: /* mode change, swap SP and A7 */
3158: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3159: }
3160: PC+= 4;
3161: }
3162:
3163: void cpu_op_655a(t_ipc *ipc) /* MOVETSR */ {
3164: /* mask ffff, bits 46f8, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3165: uint32 srcaddr = ipc->src;
3166: uint16 srcdata = fetchword(srcaddr);
3167: unsigned int sr = reg68k_sr.sr_struct.s;
3168:
3169: if (!SFLAG)
3170: reg68k_vector(V_PRIVILEGE, PC+4);
3171:
3172: SR = srcdata;
3173: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3174: /* mode change, swap SP and A7 */
3175: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3176: }
3177: PC+= 4;
3178: }
3179:
3180: void cpu_op_655b(t_ipc *ipc) /* MOVETSR */ {
3181: /* mask ffff, bits 46f8, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3182: uint32 srcaddr = ipc->src;
3183: uint16 srcdata = fetchword(srcaddr);
3184: unsigned int sr = reg68k_sr.sr_struct.s;
3185:
3186: if (!SFLAG)
3187: reg68k_vector(V_PRIVILEGE, PC+4);
3188:
3189: SR = srcdata;
3190: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3191: /* mode change, swap SP and A7 */
3192: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3193: }
3194: PC+= 4;
3195: }
3196:
3197: void cpu_op_656a(t_ipc *ipc) /* MOVETSR */ {
3198: /* mask ffff, bits 46f9, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3199: uint32 srcaddr = ipc->src;
3200: uint16 srcdata = fetchword(srcaddr);
3201: unsigned int sr = reg68k_sr.sr_struct.s;
3202:
3203: if (!SFLAG)
3204: reg68k_vector(V_PRIVILEGE, PC+6);
3205:
3206: SR = srcdata;
3207: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3208: /* mode change, swap SP and A7 */
3209: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3210: }
3211: PC+= 6;
3212: }
3213:
3214: void cpu_op_656b(t_ipc *ipc) /* MOVETSR */ {
3215: /* mask ffff, bits 46f9, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3216: uint32 srcaddr = ipc->src;
3217: uint16 srcdata = fetchword(srcaddr);
3218: unsigned int sr = reg68k_sr.sr_struct.s;
3219:
3220: if (!SFLAG)
3221: reg68k_vector(V_PRIVILEGE, PC+6);
3222:
3223: SR = srcdata;
3224: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3225: /* mode change, swap SP and A7 */
3226: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3227: }
3228: PC+= 6;
3229: }
3230:
3231: void cpu_op_657a(t_ipc *ipc) /* MOVETSR */ {
3232: /* mask ffff, bits 46fa, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 9, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3233: uint32 srcaddr = ipc->src;
3234: uint16 srcdata = fetchword(srcaddr);
3235: unsigned int sr = reg68k_sr.sr_struct.s;
3236:
3237: if (!SFLAG)
3238: reg68k_vector(V_PRIVILEGE, PC+4);
3239:
3240: SR = srcdata;
3241: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3242: /* mode change, swap SP and A7 */
3243: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3244: }
3245: PC+= 4;
3246: }
3247:
3248: void cpu_op_657b(t_ipc *ipc) /* MOVETSR */ {
3249: /* mask ffff, bits 46fa, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 9, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3250: uint32 srcaddr = ipc->src;
3251: uint16 srcdata = fetchword(srcaddr);
3252: unsigned int sr = reg68k_sr.sr_struct.s;
3253:
3254: if (!SFLAG)
3255: reg68k_vector(V_PRIVILEGE, PC+4);
3256:
3257: SR = srcdata;
3258: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3259: /* mode change, swap SP and A7 */
3260: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3261: }
3262: PC+= 4;
3263: }
3264:
3265: void cpu_op_658a(t_ipc *ipc) /* MOVETSR */ {
3266: /* mask ffff, bits 46fb, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 10, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3267: uint32 srcaddr = idxval_src(ipc);
3268: uint16 srcdata = fetchword(srcaddr);
3269: unsigned int sr = reg68k_sr.sr_struct.s;
3270:
3271: if (!SFLAG)
3272: reg68k_vector(V_PRIVILEGE, PC+4);
3273:
3274: SR = srcdata;
3275: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3276: /* mode change, swap SP and A7 */
3277: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3278: }
3279: PC+= 4;
3280: }
3281:
3282: void cpu_op_658b(t_ipc *ipc) /* MOVETSR */ {
3283: /* mask ffff, bits 46fb, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 10, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3284: uint32 srcaddr = idxval_src(ipc);
3285: uint16 srcdata = fetchword(srcaddr);
3286: unsigned int sr = reg68k_sr.sr_struct.s;
3287:
3288: if (!SFLAG)
3289: reg68k_vector(V_PRIVILEGE, PC+4);
3290:
3291: SR = srcdata;
3292: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3293: /* mode change, swap SP and A7 */
3294: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3295: }
3296: PC+= 4;
3297: }
3298:
3299: void cpu_op_659a(t_ipc *ipc) /* MOVETSR */ {
3300: /* mask ffff, bits 46fc, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3301: uint16 srcdata = ipc->src;
3302: unsigned int sr = reg68k_sr.sr_struct.s;
3303:
3304: if (!SFLAG)
3305: reg68k_vector(V_PRIVILEGE, PC+4);
3306:
3307: SR = srcdata;
3308: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3309: /* mode change, swap SP and A7 */
3310: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3311: }
3312: PC+= 4;
3313: }
3314:
3315: void cpu_op_659b(t_ipc *ipc) /* MOVETSR */ {
3316: /* mask ffff, bits 46fc, mnemonic 26, priv -1, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3317: uint16 srcdata = ipc->src;
3318: unsigned int sr = reg68k_sr.sr_struct.s;
3319:
3320: if (!SFLAG)
3321: reg68k_vector(V_PRIVILEGE, PC+4);
3322:
3323: SR = srcdata;
3324: if (sr != (uint8)reg68k_sr.sr_struct.s) {
3325: /* mode change, swap SP and A7 */
3326: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
3327: }
3328: PC+= 4;
3329: }
3330:
3331: void cpu_op_660a(t_ipc *ipc) /* NBCD */ {
3332: /* mask fff8, bits 4800, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3333: int srcreg = (ipc->opcode >> 0) & 7;
3334: uint8 srcdata = DATAREG(srcreg);
3335: uint8 outdata;
3336:
3337: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3338: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3339:
3340: if ((sint8)outdata_low < 0) {
3341: outdata_low+=10; outdata_high--;
3342: }
3343: if ((sint8)outdata_high < 0) {
3344: outdata_high+=10;
3345: } else {
3346: }
3347: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3348: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
3349: PC+= 2;
3350: }
3351:
3352: void cpu_op_660b(t_ipc *ipc) /* NBCD */ {
3353: /* mask fff8, bits 4800, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3354: int srcreg = (ipc->opcode >> 0) & 7;
3355: uint8 srcdata = DATAREG(srcreg);
3356: uint8 outdata;
3357:
3358: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3359: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3360:
3361: if ((sint8)outdata_low < 0) {
3362: outdata_low+=10; outdata_high--;
3363: }
3364: if ((sint8)outdata_high < 0) {
3365: outdata_high+=10;
3366: CFLAG = 1;
3367: XFLAG = 1;
3368: } else {
3369: CFLAG = 0;
3370: XFLAG = 0;
3371: }
3372: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3373: if (outdata) ZFLAG = 0;
3374: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
3375: PC+= 2;
3376: }
3377:
3378: void cpu_op_661a(t_ipc *ipc) /* NBCD */ {
3379: /* mask fff8, bits 4810, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3380: int srcreg = (ipc->opcode >> 0) & 7;
3381: uint32 srcaddr = ADDRREG(srcreg);
3382: uint8 srcdata = fetchbyte(srcaddr);
3383: uint8 outdata;
3384:
3385: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3386: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3387:
3388: if ((sint8)outdata_low < 0) {
3389: outdata_low+=10; outdata_high--;
3390: }
3391: if ((sint8)outdata_high < 0) {
3392: outdata_high+=10;
3393: } else {
3394: }
3395: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3396: storebyte(srcaddr, outdata);
3397: PC+= 2;
3398: }
3399:
3400: void cpu_op_661b(t_ipc *ipc) /* NBCD */ {
3401: /* mask fff8, bits 4810, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3402: int srcreg = (ipc->opcode >> 0) & 7;
3403: uint32 srcaddr = ADDRREG(srcreg);
3404: uint8 srcdata = fetchbyte(srcaddr);
3405: uint8 outdata;
3406:
3407: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3408: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3409:
3410: if ((sint8)outdata_low < 0) {
3411: outdata_low+=10; outdata_high--;
3412: }
3413: if ((sint8)outdata_high < 0) {
3414: outdata_high+=10;
3415: CFLAG = 1;
3416: XFLAG = 1;
3417: } else {
3418: CFLAG = 0;
3419: XFLAG = 0;
3420: }
3421: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3422: if (outdata) ZFLAG = 0;
3423: storebyte(srcaddr, outdata);
3424: PC+= 2;
3425: }
3426:
3427: void cpu_op_662a(t_ipc *ipc) /* NBCD */ {
3428: /* mask fff8, bits 4818, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3429: int srcreg = (ipc->opcode >> 0) & 7;
3430: uint32 srcaddr = ADDRREG(srcreg);
3431: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3432: uint8 srcdata = fetchbyte(srcaddr);
3433: uint8 outdata;
3434:
3435: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3436: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3437:
3438: if ((sint8)outdata_low < 0) {
3439: outdata_low+=10; outdata_high--;
3440: }
3441: if ((sint8)outdata_high < 0) {
3442: outdata_high+=10;
3443: } else {
3444: }
3445: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3446: storebyte(srcaddr, outdata);
3447: PC+= 2;
3448: }
3449:
3450: void cpu_op_662b(t_ipc *ipc) /* NBCD */ {
3451: /* mask fff8, bits 4818, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3452: int srcreg = (ipc->opcode >> 0) & 7;
3453: uint32 srcaddr = ADDRREG(srcreg);
3454: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3455: uint8 srcdata = fetchbyte(srcaddr);
3456: uint8 outdata;
3457:
3458: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3459: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3460:
3461: if ((sint8)outdata_low < 0) {
3462: outdata_low+=10; outdata_high--;
3463: }
3464: if ((sint8)outdata_high < 0) {
3465: outdata_high+=10;
3466: CFLAG = 1;
3467: XFLAG = 1;
3468: } else {
3469: CFLAG = 0;
3470: XFLAG = 0;
3471: }
3472: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3473: if (outdata) ZFLAG = 0;
3474: storebyte(srcaddr, outdata);
3475: PC+= 2;
3476: }
3477:
3478: void cpu_op_663a(t_ipc *ipc) /* NBCD */ {
3479: /* mask fff8, bits 4820, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3480: int srcreg = (ipc->opcode >> 0) & 7;
3481: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3482: uint8 srcdata = fetchbyte(srcaddr);
3483: uint8 outdata;
3484:
3485: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3486: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3487:
3488: if ((sint8)outdata_low < 0) {
3489: outdata_low+=10; outdata_high--;
3490: }
3491: if ((sint8)outdata_high < 0) {
3492: outdata_high+=10;
3493: } else {
3494: }
3495: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3496: storebyte(srcaddr, outdata);
3497: PC+= 2;
3498: }
3499:
3500: void cpu_op_663b(t_ipc *ipc) /* NBCD */ {
3501: /* mask fff8, bits 4820, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3502: int srcreg = (ipc->opcode >> 0) & 7;
3503: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3504: uint8 srcdata = fetchbyte(srcaddr);
3505: uint8 outdata;
3506:
3507: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3508: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3509:
3510: if ((sint8)outdata_low < 0) {
3511: outdata_low+=10; outdata_high--;
3512: }
3513: if ((sint8)outdata_high < 0) {
3514: outdata_high+=10;
3515: CFLAG = 1;
3516: XFLAG = 1;
3517: } else {
3518: CFLAG = 0;
3519: XFLAG = 0;
3520: }
3521: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3522: if (outdata) ZFLAG = 0;
3523: storebyte(srcaddr, outdata);
3524: PC+= 2;
3525: }
3526:
3527: void cpu_op_664a(t_ipc *ipc) /* NBCD */ {
3528: /* mask fff8, bits 4828, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3529: int srcreg = (ipc->opcode >> 0) & 7;
3530: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3531: uint8 srcdata = fetchbyte(srcaddr);
3532: uint8 outdata;
3533:
3534: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3535: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3536:
3537: if ((sint8)outdata_low < 0) {
3538: outdata_low+=10; outdata_high--;
3539: }
3540: if ((sint8)outdata_high < 0) {
3541: outdata_high+=10;
3542: } else {
3543: }
3544: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3545: storebyte(srcaddr, outdata);
3546: PC+= 4;
3547: }
3548:
3549: void cpu_op_664b(t_ipc *ipc) /* NBCD */ {
3550: /* mask fff8, bits 4828, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3551: int srcreg = (ipc->opcode >> 0) & 7;
3552: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3553: uint8 srcdata = fetchbyte(srcaddr);
3554: uint8 outdata;
3555:
3556: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3557: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3558:
3559: if ((sint8)outdata_low < 0) {
3560: outdata_low+=10; outdata_high--;
3561: }
3562: if ((sint8)outdata_high < 0) {
3563: outdata_high+=10;
3564: CFLAG = 1;
3565: XFLAG = 1;
3566: } else {
3567: CFLAG = 0;
3568: XFLAG = 0;
3569: }
3570: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3571: if (outdata) ZFLAG = 0;
3572: storebyte(srcaddr, outdata);
3573: PC+= 4;
3574: }
3575:
3576: void cpu_op_665a(t_ipc *ipc) /* NBCD */ {
3577: /* mask fff8, bits 4830, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3578: int srcreg = (ipc->opcode >> 0) & 7;
3579: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3580: uint8 srcdata = fetchbyte(srcaddr);
3581: uint8 outdata;
3582:
3583: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3584: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3585:
3586: if ((sint8)outdata_low < 0) {
3587: outdata_low+=10; outdata_high--;
3588: }
3589: if ((sint8)outdata_high < 0) {
3590: outdata_high+=10;
3591: } else {
3592: }
3593: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3594: storebyte(srcaddr, outdata);
3595: PC+= 4;
3596: }
3597:
3598: void cpu_op_665b(t_ipc *ipc) /* NBCD */ {
3599: /* mask fff8, bits 4830, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3600: int srcreg = (ipc->opcode >> 0) & 7;
3601: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3602: uint8 srcdata = fetchbyte(srcaddr);
3603: uint8 outdata;
3604:
3605: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3606: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3607:
3608: if ((sint8)outdata_low < 0) {
3609: outdata_low+=10; outdata_high--;
3610: }
3611: if ((sint8)outdata_high < 0) {
3612: outdata_high+=10;
3613: CFLAG = 1;
3614: XFLAG = 1;
3615: } else {
3616: CFLAG = 0;
3617: XFLAG = 0;
3618: }
3619: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3620: if (outdata) ZFLAG = 0;
3621: storebyte(srcaddr, outdata);
3622: PC+= 4;
3623: }
3624:
3625: void cpu_op_666a(t_ipc *ipc) /* NBCD */ {
3626: /* mask ffff, bits 4838, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3627: uint32 srcaddr = ipc->src;
3628: uint8 srcdata = fetchbyte(srcaddr);
3629: uint8 outdata;
3630:
3631: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3632: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3633:
3634: if ((sint8)outdata_low < 0) {
3635: outdata_low+=10; outdata_high--;
3636: }
3637: if ((sint8)outdata_high < 0) {
3638: outdata_high+=10;
3639: } else {
3640: }
3641: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3642: storebyte(srcaddr, outdata);
3643: PC+= 4;
3644: }
3645:
3646: void cpu_op_666b(t_ipc *ipc) /* NBCD */ {
3647: /* mask ffff, bits 4838, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3648: uint32 srcaddr = ipc->src;
3649: uint8 srcdata = fetchbyte(srcaddr);
3650: uint8 outdata;
3651:
3652: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3653: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3654:
3655: if ((sint8)outdata_low < 0) {
3656: outdata_low+=10; outdata_high--;
3657: }
3658: if ((sint8)outdata_high < 0) {
3659: outdata_high+=10;
3660: CFLAG = 1;
3661: XFLAG = 1;
3662: } else {
3663: CFLAG = 0;
3664: XFLAG = 0;
3665: }
3666: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3667: if (outdata) ZFLAG = 0;
3668: storebyte(srcaddr, outdata);
3669: PC+= 4;
3670: }
3671:
3672: void cpu_op_667a(t_ipc *ipc) /* NBCD */ {
3673: /* mask ffff, bits 4839, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3674: uint32 srcaddr = ipc->src;
3675: uint8 srcdata = fetchbyte(srcaddr);
3676: uint8 outdata;
3677:
3678: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3679: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3680:
3681: if ((sint8)outdata_low < 0) {
3682: outdata_low+=10; outdata_high--;
3683: }
3684: if ((sint8)outdata_high < 0) {
3685: outdata_high+=10;
3686: } else {
3687: }
3688: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3689: storebyte(srcaddr, outdata);
3690: PC+= 6;
3691: }
3692:
3693: void cpu_op_667b(t_ipc *ipc) /* NBCD */ {
3694: /* mask ffff, bits 4839, mnemonic 37, priv 0, endblk 0, imm_notzero 0, used 1 set -11, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3695: uint32 srcaddr = ipc->src;
3696: uint8 srcdata = fetchbyte(srcaddr);
3697: uint8 outdata;
3698:
3699: sint8 outdata_low = 0 - (sint8)(srcdata & 0xF) - XFLAG;
3700: sint8 outdata_high = 0 - (sint8)(srcdata>>4);
3701:
3702: if ((sint8)outdata_low < 0) {
3703: outdata_low+=10; outdata_high--;
3704: }
3705: if ((sint8)outdata_high < 0) {
3706: outdata_high+=10;
3707: CFLAG = 1;
3708: XFLAG = 1;
3709: } else {
3710: CFLAG = 0;
3711: XFLAG = 0;
3712: }
3713: outdata = (uint8)outdata_low |((uint8)outdata_high << 4);
3714: if (outdata) ZFLAG = 0;
3715: storebyte(srcaddr, outdata);
3716: PC+= 6;
3717: }
3718:
3719: void cpu_op_668a(t_ipc *ipc) /* SWAP */ {
3720: /* mask fff8, bits 4840, mnemonic 38, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3721: int srcreg = (ipc->opcode >> 0) & 7;
3722: uint32 srcdata = DATAREG(srcreg);
3723: uint32 outdata = (srcdata>>16) | (srcdata<<16);
3724:
3725: DATAREG(srcreg) = outdata;
3726: PC+= 2;
3727: }
3728:
3729: void cpu_op_668b(t_ipc *ipc) /* SWAP */ {
3730: /* mask fff8, bits 4840, mnemonic 38, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3731: int srcreg = (ipc->opcode >> 0) & 7;
3732: uint32 srcdata = DATAREG(srcreg);
3733: uint32 outdata = (srcdata>>16) | (srcdata<<16);
3734:
3735: DATAREG(srcreg) = outdata;
3736:
3737: VFLAG = 0;
3738: CFLAG = 0;
3739: NFLAG = ((sint32)outdata) < 0;
3740: ZFLAG = !outdata;
3741: PC+= 2;
3742: }
3743:
3744: void cpu_op_669a(t_ipc *ipc) /* PEA */ {
3745: /* mask fff8, bits 4850, mnemonic 39, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3746: int srcreg = (ipc->opcode >> 0) & 7;
3747: uint32 srcaddr = ADDRREG(srcreg);
3748:
3749: ADDRREG(7)-= 4;
3750: storelong(ADDRREG(7), srcaddr);
3751: PC+= 2;
3752: }
3753:
3754: void cpu_op_670a(t_ipc *ipc) /* PEA */ {
3755: /* mask fff8, bits 4868, mnemonic 39, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3756: int srcreg = (ipc->opcode >> 0) & 7;
3757: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3758:
3759: ADDRREG(7)-= 4;
3760: storelong(ADDRREG(7), srcaddr);
3761: PC+= 4;
3762: }
3763:
3764: void cpu_op_671a(t_ipc *ipc) /* PEA */ {
3765: /* mask fff8, bits 4870, mnemonic 39, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3766: int srcreg = (ipc->opcode >> 0) & 7;
3767: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3768:
3769: ADDRREG(7)-= 4;
3770: storelong(ADDRREG(7), srcaddr);
3771: PC+= 4;
3772: }
3773:
3774: void cpu_op_672a(t_ipc *ipc) /* PEA */ {
3775: /* mask ffff, bits 4878, mnemonic 39, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3776: uint32 srcaddr = ipc->src;
3777:
3778: ADDRREG(7)-= 4;
3779: storelong(ADDRREG(7), srcaddr);
3780: PC+= 4;
3781: }
3782:
3783: void cpu_op_673a(t_ipc *ipc) /* PEA */ {
3784: /* mask ffff, bits 4879, mnemonic 39, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3785: uint32 srcaddr = ipc->src;
3786:
3787: ADDRREG(7)-= 4;
3788: storelong(ADDRREG(7), srcaddr);
3789: PC+= 6;
3790: }
3791:
3792: void cpu_op_674a(t_ipc *ipc) /* PEA */ {
3793: /* mask ffff, bits 487a, mnemonic 39, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 9, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3794: uint32 srcaddr = ipc->src;
3795:
3796: ADDRREG(7)-= 4;
3797: storelong(ADDRREG(7), srcaddr);
3798: PC+= 4;
3799: }
3800:
3801: void cpu_op_675a(t_ipc *ipc) /* PEA */ {
3802: /* mask ffff, bits 487b, mnemonic 39, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 10, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3803: uint32 srcaddr = idxval_src(ipc);
3804:
3805: ADDRREG(7)-= 4;
3806: storelong(ADDRREG(7), srcaddr);
3807: PC+= 4;
3808: }
3809:
3810: void cpu_op_676a(t_ipc *ipc) /* EXT */ {
3811: /* mask fff8, bits 4880, mnemonic 41, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3812: int srcreg = (ipc->opcode >> 0) & 7;
3813: uint16 srcdata = DATAREG(srcreg);
3814:
3815: uint16 outdata = (sint16)(sint8)(srcdata);
3816: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xffff) | outdata;
3817: PC+= 2;
3818: }
3819:
3820: void cpu_op_676b(t_ipc *ipc) /* EXT */ {
3821: /* mask fff8, bits 4880, mnemonic 41, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3822: int srcreg = (ipc->opcode >> 0) & 7;
3823: uint16 srcdata = DATAREG(srcreg);
3824:
3825: uint16 outdata = (sint16)(sint8)(srcdata);
3826: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xffff) | outdata;
3827:
3828: VFLAG = 0;
3829: CFLAG = 0;
3830: NFLAG = ((sint16)outdata) < 0;
3831: ZFLAG = !outdata;
3832: PC+= 2;
3833: }
3834:
3835: void cpu_op_677a(t_ipc *ipc) /* MOVEMRM */ {
3836: /* mask fff8, bits 4890, mnemonic 27, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
3837: uint16 srcdata = ipc->src;
3838: int dstreg = (ipc->opcode >> 0) & 7;
3839: uint32 dstaddr = ADDRREG(dstreg);
3840: uint8 addrmask = (srcdata & 0xFF00) >> 8;
3841: uint8 datamask = srcdata & 0xFF;
3842: while (datamask) {
3843: storeword(dstaddr, DATAREG(movem_bit[datamask]));
3844: datamask&= ~(1<<movem_bit[datamask]);
3845: dstaddr+= 2;
3846: }
3847: while (addrmask) {
3848: storeword(dstaddr, ADDRREG(movem_bit[addrmask]));
3849: addrmask&= ~(1<<movem_bit[addrmask]);
3850: dstaddr+= 2;
3851: }
3852: PC+= 4;
3853: }
3854:
3855: void cpu_op_678a(t_ipc *ipc) /* MOVEMRM */ {
3856: /* mask fff8, bits 48a0, mnemonic 27, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
3857: uint16 srcdata = ipc->src;
3858: int dstreg = (ipc->opcode >> 0) & 7;
3859: uint32 dstaddr = ADDRREG(dstreg);
3860: uint8 datamask = (srcdata & 0xFF00) >> 8;
3861: uint8 addrmask = srcdata & 0xFF;
3862: while (addrmask) {
3863: dstaddr-= 2;
3864: storeword(dstaddr, ADDRREG((7-movem_bit[addrmask])));
3865: addrmask&= ~(1<<movem_bit[addrmask]);
3866: }
3867: while (datamask) {
3868: dstaddr-= 2;
3869: storeword(dstaddr, DATAREG((7-movem_bit[datamask])));
3870: datamask&= ~(1<<movem_bit[datamask]);
3871: }
3872: ADDRREG(dstreg) = dstaddr; PC+= 4;
3873: }
3874:
3875: void cpu_op_679a(t_ipc *ipc) /* MOVEMRM */ {
3876: /* mask fff8, bits 48a8, mnemonic 27, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
3877: uint16 srcdata = ipc->src;
3878: int dstreg = (ipc->opcode >> 0) & 7;
3879: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
3880: uint8 addrmask = (srcdata & 0xFF00) >> 8;
3881: uint8 datamask = srcdata & 0xFF;
3882: while (datamask) {
3883: storeword(dstaddr, DATAREG(movem_bit[datamask]));
3884: datamask&= ~(1<<movem_bit[datamask]);
3885: dstaddr+= 2;
3886: }
3887: while (addrmask) {
3888: storeword(dstaddr, ADDRREG(movem_bit[addrmask]));
3889: addrmask&= ~(1<<movem_bit[addrmask]);
3890: dstaddr+= 2;
3891: }
3892: PC+= 6;
3893: }
3894:
3895: void cpu_op_680a(t_ipc *ipc) /* MOVEMRM */ {
3896: /* mask fff8, bits 48b0, mnemonic 27, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
3897: uint16 srcdata = ipc->src;
3898: int dstreg = (ipc->opcode >> 0) & 7;
3899: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
3900: uint8 addrmask = (srcdata & 0xFF00) >> 8;
3901: uint8 datamask = srcdata & 0xFF;
3902: while (datamask) {
3903: storeword(dstaddr, DATAREG(movem_bit[datamask]));
3904: datamask&= ~(1<<movem_bit[datamask]);
3905: dstaddr+= 2;
3906: }
3907: while (addrmask) {
3908: storeword(dstaddr, ADDRREG(movem_bit[addrmask]));
3909: addrmask&= ~(1<<movem_bit[addrmask]);
3910: dstaddr+= 2;
3911: }
3912: PC+= 6;
3913: }
3914:
3915: void cpu_op_681a(t_ipc *ipc) /* MOVEMRM */ {
3916: /* mask ffff, bits 48b8, mnemonic 27, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
3917: uint16 srcdata = ipc->src;
3918: uint32 dstaddr = ipc->dst;
3919: uint8 addrmask = (srcdata & 0xFF00) >> 8;
3920: uint8 datamask = srcdata & 0xFF;
3921: while (datamask) {
3922: storeword(dstaddr, DATAREG(movem_bit[datamask]));
3923: datamask&= ~(1<<movem_bit[datamask]);
3924: dstaddr+= 2;
3925: }
3926: while (addrmask) {
3927: storeword(dstaddr, ADDRREG(movem_bit[addrmask]));
3928: addrmask&= ~(1<<movem_bit[addrmask]);
3929: dstaddr+= 2;
3930: }
3931: PC+= 6;
3932: }
3933:
3934: void cpu_op_682a(t_ipc *ipc) /* MOVEMRM */ {
3935: /* mask ffff, bits 48b9, mnemonic 27, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
3936: uint16 srcdata = ipc->src;
3937: uint32 dstaddr = ipc->dst;
3938: uint8 addrmask = (srcdata & 0xFF00) >> 8;
3939: uint8 datamask = srcdata & 0xFF;
3940: while (datamask) {
3941: storeword(dstaddr, DATAREG(movem_bit[datamask]));
3942: datamask&= ~(1<<movem_bit[datamask]);
3943: dstaddr+= 2;
3944: }
3945: while (addrmask) {
3946: storeword(dstaddr, ADDRREG(movem_bit[addrmask]));
3947: addrmask&= ~(1<<movem_bit[addrmask]);
3948: dstaddr+= 2;
3949: }
3950: PC+= 8;
3951: }
3952:
3953: void cpu_op_683a(t_ipc *ipc) /* EXT */ {
3954: /* mask fff8, bits 48c0, mnemonic 41, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3955: int srcreg = (ipc->opcode >> 0) & 7;
3956: uint32 srcdata = DATAREG(srcreg);
3957:
3958: uint32 outdata = (sint32)(sint16)(srcdata);
3959: DATAREG(srcreg) = outdata;
3960: PC+= 2;
3961: }
3962:
3963: void cpu_op_683b(t_ipc *ipc) /* EXT */ {
3964: /* mask fff8, bits 48c0, mnemonic 41, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3965: int srcreg = (ipc->opcode >> 0) & 7;
3966: uint32 srcdata = DATAREG(srcreg);
3967:
3968: uint32 outdata = (sint32)(sint16)(srcdata);
3969: DATAREG(srcreg) = outdata;
3970:
3971: VFLAG = 0;
3972: CFLAG = 0;
3973: NFLAG = ((sint32)outdata) < 0;
3974: ZFLAG = !outdata;
3975: PC+= 2;
3976: }
3977:
3978: void cpu_op_684a(t_ipc *ipc) /* MOVEMRM */ {
3979: /* mask fff8, bits 48d0, mnemonic 27, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
3980: uint16 srcdata = ipc->src;
3981: int dstreg = (ipc->opcode >> 0) & 7;
3982: uint32 dstaddr = ADDRREG(dstreg);
3983: uint8 addrmask = (srcdata & 0xFF00) >> 8;
3984: uint8 datamask = srcdata & 0xFF;
3985: while (datamask) {
3986: storelong(dstaddr, DATAREG(movem_bit[datamask]));
3987: datamask&= ~(1<<movem_bit[datamask]);
3988: dstaddr+= 4;
3989: }
3990: while (addrmask) {
3991: storelong(dstaddr, ADDRREG(movem_bit[addrmask]));
3992: addrmask&= ~(1<<movem_bit[addrmask]);
3993: dstaddr+= 4;
3994: }
3995: PC+= 4;
3996: }
3997:
3998: void cpu_op_685a(t_ipc *ipc) /* MOVEMRM */ {
3999: /* mask fff8, bits 48e0, mnemonic 27, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 4, sbitpos 0, dbitpos 0, immvalue 0 */
4000: uint16 srcdata = ipc->src;
4001: int dstreg = (ipc->opcode >> 0) & 7;
4002: uint32 dstaddr = ADDRREG(dstreg);
4003: uint8 datamask = (srcdata & 0xFF00) >> 8;
4004: uint8 addrmask = srcdata & 0xFF;
4005: while (addrmask) {
4006: dstaddr-= 4;
4007: storelong(dstaddr, ADDRREG((7-movem_bit[addrmask])));
4008: addrmask&= ~(1<<movem_bit[addrmask]);
4009: }
4010: while (datamask) {
4011: dstaddr-= 4;
4012: storelong(dstaddr, DATAREG((7-movem_bit[datamask])));
4013: datamask&= ~(1<<movem_bit[datamask]);
4014: }
4015: ADDRREG(dstreg) = dstaddr; PC+= 4;
4016: }
4017:
4018: void cpu_op_686a(t_ipc *ipc) /* MOVEMRM */ {
4019: /* mask fff8, bits 48e8, mnemonic 27, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
4020: uint16 srcdata = ipc->src;
4021: int dstreg = (ipc->opcode >> 0) & 7;
4022: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
4023: uint8 addrmask = (srcdata & 0xFF00) >> 8;
4024: uint8 datamask = srcdata & 0xFF;
4025: while (datamask) {
4026: storelong(dstaddr, DATAREG(movem_bit[datamask]));
4027: datamask&= ~(1<<movem_bit[datamask]);
4028: dstaddr+= 4;
4029: }
4030: while (addrmask) {
4031: storelong(dstaddr, ADDRREG(movem_bit[addrmask]));
4032: addrmask&= ~(1<<movem_bit[addrmask]);
4033: dstaddr+= 4;
4034: }
4035: PC+= 6;
4036: }
4037:
4038: void cpu_op_687a(t_ipc *ipc) /* MOVEMRM */ {
4039: /* mask fff8, bits 48f0, mnemonic 27, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
4040: uint16 srcdata = ipc->src;
4041: int dstreg = (ipc->opcode >> 0) & 7;
4042: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
4043: uint8 addrmask = (srcdata & 0xFF00) >> 8;
4044: uint8 datamask = srcdata & 0xFF;
4045: while (datamask) {
4046: storelong(dstaddr, DATAREG(movem_bit[datamask]));
4047: datamask&= ~(1<<movem_bit[datamask]);
4048: dstaddr+= 4;
4049: }
4050: while (addrmask) {
4051: storelong(dstaddr, ADDRREG(movem_bit[addrmask]));
4052: addrmask&= ~(1<<movem_bit[addrmask]);
4053: dstaddr+= 4;
4054: }
4055: PC+= 6;
4056: }
4057:
4058: void cpu_op_688a(t_ipc *ipc) /* MOVEMRM */ {
4059: /* mask ffff, bits 48f8, mnemonic 27, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
4060: uint16 srcdata = ipc->src;
4061: uint32 dstaddr = ipc->dst;
4062: uint8 addrmask = (srcdata & 0xFF00) >> 8;
4063: uint8 datamask = srcdata & 0xFF;
4064: while (datamask) {
4065: storelong(dstaddr, DATAREG(movem_bit[datamask]));
4066: datamask&= ~(1<<movem_bit[datamask]);
4067: dstaddr+= 4;
4068: }
4069: while (addrmask) {
4070: storelong(dstaddr, ADDRREG(movem_bit[addrmask]));
4071: addrmask&= ~(1<<movem_bit[addrmask]);
4072: dstaddr+= 4;
4073: }
4074: PC+= 6;
4075: }
4076:
4077: void cpu_op_689a(t_ipc *ipc) /* MOVEMRM */ {
4078: /* mask ffff, bits 48f9, mnemonic 27, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
4079: uint16 srcdata = ipc->src;
4080: uint32 dstaddr = ipc->dst;
4081: uint8 addrmask = (srcdata & 0xFF00) >> 8;
4082: uint8 datamask = srcdata & 0xFF;
4083: while (datamask) {
4084: storelong(dstaddr, DATAREG(movem_bit[datamask]));
4085: datamask&= ~(1<<movem_bit[datamask]);
4086: dstaddr+= 4;
4087: }
4088: while (addrmask) {
4089: storelong(dstaddr, ADDRREG(movem_bit[addrmask]));
4090: addrmask&= ~(1<<movem_bit[addrmask]);
4091: dstaddr+= 4;
4092: }
4093: PC+= 8;
4094: }
4095:
4096: void cpu_op_690a(t_ipc *ipc) /* TST */ {
4097: /* mask fff8, bits 4a00, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4098: int srcreg = (ipc->opcode >> 0) & 7;
4099: uint8 srcdata = DATAREG(srcreg);
4100: uint8 outdata = srcdata;
4101: PC+= 2;
4102: }
4103:
4104: void cpu_op_690b(t_ipc *ipc) /* TST */ {
4105: /* mask fff8, bits 4a00, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4106: int srcreg = (ipc->opcode >> 0) & 7;
4107: uint8 srcdata = DATAREG(srcreg);
4108: uint8 outdata = srcdata;
4109:
4110: VFLAG = 0;
4111: CFLAG = 0;
4112: NFLAG = ((sint8)outdata) < 0;
4113: ZFLAG = !outdata;
4114: PC+= 2;
4115: }
4116:
4117: void cpu_op_691a(t_ipc *ipc) /* TST */ {
4118: /* mask fff8, bits 4a10, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4119: int srcreg = (ipc->opcode >> 0) & 7;
4120: uint32 srcaddr = ADDRREG(srcreg);
4121: uint8 srcdata = fetchbyte(srcaddr);
4122: uint8 outdata = srcdata;
4123: PC+= 2;
4124: }
4125:
4126: void cpu_op_691b(t_ipc *ipc) /* TST */ {
4127: /* mask fff8, bits 4a10, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4128: int srcreg = (ipc->opcode >> 0) & 7;
4129: uint32 srcaddr = ADDRREG(srcreg);
4130: uint8 srcdata = fetchbyte(srcaddr);
4131: uint8 outdata = srcdata;
4132:
4133: VFLAG = 0;
4134: CFLAG = 0;
4135: NFLAG = ((sint8)outdata) < 0;
4136: ZFLAG = !outdata;
4137: PC+= 2;
4138: }
4139:
4140: void cpu_op_692a(t_ipc *ipc) /* TST */ {
4141: /* mask fff8, bits 4a18, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4142: int srcreg = (ipc->opcode >> 0) & 7;
4143: uint32 srcaddr = ADDRREG(srcreg);
4144: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
4145: uint8 srcdata = fetchbyte(srcaddr);
4146: uint8 outdata = srcdata;
4147: PC+= 2;
4148: }
4149:
4150: void cpu_op_692b(t_ipc *ipc) /* TST */ {
4151: /* mask fff8, bits 4a18, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4152: int srcreg = (ipc->opcode >> 0) & 7;
4153: uint32 srcaddr = ADDRREG(srcreg);
4154: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
4155: uint8 srcdata = fetchbyte(srcaddr);
4156: uint8 outdata = srcdata;
4157:
4158: VFLAG = 0;
4159: CFLAG = 0;
4160: NFLAG = ((sint8)outdata) < 0;
4161: ZFLAG = !outdata;
4162: PC+= 2;
4163: }
4164:
4165: void cpu_op_693a(t_ipc *ipc) /* TST */ {
4166: /* mask fff8, bits 4a20, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4167: int srcreg = (ipc->opcode >> 0) & 7;
4168: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
4169: uint8 srcdata = fetchbyte(srcaddr);
4170: uint8 outdata = srcdata;
4171: PC+= 2;
4172: }
4173:
4174: void cpu_op_693b(t_ipc *ipc) /* TST */ {
4175: /* mask fff8, bits 4a20, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4176: int srcreg = (ipc->opcode >> 0) & 7;
4177: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
4178: uint8 srcdata = fetchbyte(srcaddr);
4179: uint8 outdata = srcdata;
4180:
4181: VFLAG = 0;
4182: CFLAG = 0;
4183: NFLAG = ((sint8)outdata) < 0;
4184: ZFLAG = !outdata;
4185: PC+= 2;
4186: }
4187:
4188: void cpu_op_694a(t_ipc *ipc) /* TST */ {
4189: /* mask fff8, bits 4a28, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4190: int srcreg = (ipc->opcode >> 0) & 7;
4191: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
4192: uint8 srcdata = fetchbyte(srcaddr);
4193: uint8 outdata = srcdata;
4194: PC+= 4;
4195: }
4196:
4197: void cpu_op_694b(t_ipc *ipc) /* TST */ {
4198: /* mask fff8, bits 4a28, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4199: int srcreg = (ipc->opcode >> 0) & 7;
4200: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
4201: uint8 srcdata = fetchbyte(srcaddr);
4202: uint8 outdata = srcdata;
4203:
4204: VFLAG = 0;
4205: CFLAG = 0;
4206: NFLAG = ((sint8)outdata) < 0;
4207: ZFLAG = !outdata;
4208: PC+= 4;
4209: }
4210:
4211: void cpu_op_695a(t_ipc *ipc) /* TST */ {
4212: /* mask fff8, bits 4a30, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4213: int srcreg = (ipc->opcode >> 0) & 7;
4214: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
4215: uint8 srcdata = fetchbyte(srcaddr);
4216: uint8 outdata = srcdata;
4217: PC+= 4;
4218: }
4219:
4220: void cpu_op_695b(t_ipc *ipc) /* TST */ {
4221: /* mask fff8, bits 4a30, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4222: int srcreg = (ipc->opcode >> 0) & 7;
4223: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
4224: uint8 srcdata = fetchbyte(srcaddr);
4225: uint8 outdata = srcdata;
4226:
4227: VFLAG = 0;
4228: CFLAG = 0;
4229: NFLAG = ((sint8)outdata) < 0;
4230: ZFLAG = !outdata;
4231: PC+= 4;
4232: }
4233:
4234: void cpu_op_696a(t_ipc *ipc) /* TST */ {
4235: /* mask ffff, bits 4a38, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4236: uint32 srcaddr = ipc->src;
4237: uint8 srcdata = fetchbyte(srcaddr);
4238: uint8 outdata = srcdata;
4239: PC+= 4;
4240: }
4241:
4242: void cpu_op_696b(t_ipc *ipc) /* TST */ {
4243: /* mask ffff, bits 4a38, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4244: uint32 srcaddr = ipc->src;
4245: uint8 srcdata = fetchbyte(srcaddr);
4246: uint8 outdata = srcdata;
4247:
4248: VFLAG = 0;
4249: CFLAG = 0;
4250: NFLAG = ((sint8)outdata) < 0;
4251: ZFLAG = !outdata;
4252: PC+= 4;
4253: }
4254:
4255: void cpu_op_697a(t_ipc *ipc) /* TST */ {
4256: /* mask ffff, bits 4a39, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4257: uint32 srcaddr = ipc->src;
4258: uint8 srcdata = fetchbyte(srcaddr);
4259: uint8 outdata = srcdata;
4260: PC+= 6;
4261: }
4262:
4263: void cpu_op_697b(t_ipc *ipc) /* TST */ {
4264: /* mask ffff, bits 4a39, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4265: uint32 srcaddr = ipc->src;
4266: uint8 srcdata = fetchbyte(srcaddr);
4267: uint8 outdata = srcdata;
4268:
4269: VFLAG = 0;
4270: CFLAG = 0;
4271: NFLAG = ((sint8)outdata) < 0;
4272: ZFLAG = !outdata;
4273: PC+= 6;
4274: }
4275:
4276: void cpu_op_698a(t_ipc *ipc) /* TST */ {
4277: /* mask fff8, bits 4a40, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4278: int srcreg = (ipc->opcode >> 0) & 7;
4279: uint16 srcdata = DATAREG(srcreg);
4280: uint16 outdata = srcdata;
4281: PC+= 2;
4282: }
4283:
4284: void cpu_op_698b(t_ipc *ipc) /* TST */ {
4285: /* mask fff8, bits 4a40, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4286: int srcreg = (ipc->opcode >> 0) & 7;
4287: uint16 srcdata = DATAREG(srcreg);
4288: uint16 outdata = srcdata;
4289:
4290: VFLAG = 0;
4291: CFLAG = 0;
4292: NFLAG = ((sint16)outdata) < 0;
4293: ZFLAG = !outdata;
4294: PC+= 2;
4295: }
4296:
4297: void cpu_op_699a(t_ipc *ipc) /* TST */ {
4298: /* mask fff8, bits 4a50, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4299: int srcreg = (ipc->opcode >> 0) & 7;
4300: uint32 srcaddr = ADDRREG(srcreg);
4301: uint16 srcdata = fetchword(srcaddr);
4302: uint16 outdata = srcdata;
4303: PC+= 2;
4304: }
4305:
4306: void cpu_op_699b(t_ipc *ipc) /* TST */ {
4307: /* mask fff8, bits 4a50, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4308: int srcreg = (ipc->opcode >> 0) & 7;
4309: uint32 srcaddr = ADDRREG(srcreg);
4310: uint16 srcdata = fetchword(srcaddr);
4311: uint16 outdata = srcdata;
4312:
4313: VFLAG = 0;
4314: CFLAG = 0;
4315: NFLAG = ((sint16)outdata) < 0;
4316: ZFLAG = !outdata;
4317: PC+= 2;
4318: }
4319:
4320: void cpu_op_700a(t_ipc *ipc) /* TST */ {
4321: /* mask fff8, bits 4a58, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4322: int srcreg = (ipc->opcode >> 0) & 7;
4323: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
4324: uint16 srcdata = fetchword(srcaddr);
4325: uint16 outdata = srcdata;
4326: PC+= 2;
4327: }
4328:
4329: void cpu_op_700b(t_ipc *ipc) /* TST */ {
4330: /* mask fff8, bits 4a58, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4331: int srcreg = (ipc->opcode >> 0) & 7;
4332: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
4333: uint16 srcdata = fetchword(srcaddr);
4334: uint16 outdata = srcdata;
4335:
4336: VFLAG = 0;
4337: CFLAG = 0;
4338: NFLAG = ((sint16)outdata) < 0;
4339: ZFLAG = !outdata;
4340: PC+= 2;
4341: }
4342:
4343: void cpu_op_701a(t_ipc *ipc) /* TST */ {
4344: /* mask fff8, bits 4a60, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4345: int srcreg = (ipc->opcode >> 0) & 7;
4346: uint32 srcaddr = ADDRREG(srcreg)-=2;
4347: uint16 srcdata = fetchword(srcaddr);
4348: uint16 outdata = srcdata;
4349: PC+= 2;
4350: }
4351:
4352: void cpu_op_701b(t_ipc *ipc) /* TST */ {
4353: /* mask fff8, bits 4a60, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4354: int srcreg = (ipc->opcode >> 0) & 7;
4355: uint32 srcaddr = ADDRREG(srcreg)-=2;
4356: uint16 srcdata = fetchword(srcaddr);
4357: uint16 outdata = srcdata;
4358:
4359: VFLAG = 0;
4360: CFLAG = 0;
4361: NFLAG = ((sint16)outdata) < 0;
4362: ZFLAG = !outdata;
4363: PC+= 2;
4364: }
4365:
4366: void cpu_op_702a(t_ipc *ipc) /* TST */ {
4367: /* mask fff8, bits 4a68, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4368: int srcreg = (ipc->opcode >> 0) & 7;
4369: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
4370: uint16 srcdata = fetchword(srcaddr);
4371: uint16 outdata = srcdata;
4372: PC+= 4;
4373: }
4374:
4375: void cpu_op_702b(t_ipc *ipc) /* TST */ {
4376: /* mask fff8, bits 4a68, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4377: int srcreg = (ipc->opcode >> 0) & 7;
4378: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
4379: uint16 srcdata = fetchword(srcaddr);
4380: uint16 outdata = srcdata;
4381:
4382: VFLAG = 0;
4383: CFLAG = 0;
4384: NFLAG = ((sint16)outdata) < 0;
4385: ZFLAG = !outdata;
4386: PC+= 4;
4387: }
4388:
4389: void cpu_op_703a(t_ipc *ipc) /* TST */ {
4390: /* mask fff8, bits 4a70, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4391: int srcreg = (ipc->opcode >> 0) & 7;
4392: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
4393: uint16 srcdata = fetchword(srcaddr);
4394: uint16 outdata = srcdata;
4395: PC+= 4;
4396: }
4397:
4398: void cpu_op_703b(t_ipc *ipc) /* TST */ {
4399: /* mask fff8, bits 4a70, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4400: int srcreg = (ipc->opcode >> 0) & 7;
4401: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
4402: uint16 srcdata = fetchword(srcaddr);
4403: uint16 outdata = srcdata;
4404:
4405: VFLAG = 0;
4406: CFLAG = 0;
4407: NFLAG = ((sint16)outdata) < 0;
4408: ZFLAG = !outdata;
4409: PC+= 4;
4410: }
4411:
4412: void cpu_op_704a(t_ipc *ipc) /* TST */ {
4413: /* mask ffff, bits 4a78, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4414: uint32 srcaddr = ipc->src;
4415: uint16 srcdata = fetchword(srcaddr);
4416: uint16 outdata = srcdata;
4417: PC+= 4;
4418: }
4419:
4420: void cpu_op_704b(t_ipc *ipc) /* TST */ {
4421: /* mask ffff, bits 4a78, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4422: uint32 srcaddr = ipc->src;
4423: uint16 srcdata = fetchword(srcaddr);
4424: uint16 outdata = srcdata;
4425:
4426: VFLAG = 0;
4427: CFLAG = 0;
4428: NFLAG = ((sint16)outdata) < 0;
4429: ZFLAG = !outdata;
4430: PC+= 4;
4431: }
4432:
4433: void cpu_op_705a(t_ipc *ipc) /* TST */ {
4434: /* mask ffff, bits 4a79, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4435: uint32 srcaddr = ipc->src;
4436: uint16 srcdata = fetchword(srcaddr);
4437: uint16 outdata = srcdata;
4438: PC+= 6;
4439: }
4440:
4441: void cpu_op_705b(t_ipc *ipc) /* TST */ {
4442: /* mask ffff, bits 4a79, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4443: uint32 srcaddr = ipc->src;
4444: uint16 srcdata = fetchword(srcaddr);
4445: uint16 outdata = srcdata;
4446:
4447: VFLAG = 0;
4448: CFLAG = 0;
4449: NFLAG = ((sint16)outdata) < 0;
4450: ZFLAG = !outdata;
4451: PC+= 6;
4452: }
4453:
4454: void cpu_op_706a(t_ipc *ipc) /* TST */ {
4455: /* mask fff8, bits 4a80, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4456: int srcreg = (ipc->opcode >> 0) & 7;
4457: uint32 srcdata = DATAREG(srcreg);
4458: uint32 outdata = srcdata;
4459: PC+= 2;
4460: }
4461:
4462: void cpu_op_706b(t_ipc *ipc) /* TST */ {
4463: /* mask fff8, bits 4a80, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4464: int srcreg = (ipc->opcode >> 0) & 7;
4465: uint32 srcdata = DATAREG(srcreg);
4466: uint32 outdata = srcdata;
4467:
4468: VFLAG = 0;
4469: CFLAG = 0;
4470: NFLAG = ((sint32)outdata) < 0;
4471: ZFLAG = !outdata;
4472: PC+= 2;
4473: }
4474:
4475: void cpu_op_707a(t_ipc *ipc) /* TST */ {
4476: /* mask fff8, bits 4a90, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4477: int srcreg = (ipc->opcode >> 0) & 7;
4478: uint32 srcaddr = ADDRREG(srcreg);
4479: uint32 srcdata = fetchlong(srcaddr);
4480: uint32 outdata = srcdata;
4481: PC+= 2;
4482: }
4483:
4484: void cpu_op_707b(t_ipc *ipc) /* TST */ {
4485: /* mask fff8, bits 4a90, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4486: int srcreg = (ipc->opcode >> 0) & 7;
4487: uint32 srcaddr = ADDRREG(srcreg);
4488: uint32 srcdata = fetchlong(srcaddr);
4489: uint32 outdata = srcdata;
4490:
4491: VFLAG = 0;
4492: CFLAG = 0;
4493: NFLAG = ((sint32)outdata) < 0;
4494: ZFLAG = !outdata;
4495: PC+= 2;
4496: }
4497:
4498: void cpu_op_708a(t_ipc *ipc) /* TST */ {
4499: /* mask fff8, bits 4a98, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4500: int srcreg = (ipc->opcode >> 0) & 7;
4501: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4);
4502: uint32 srcdata = fetchlong(srcaddr);
4503: uint32 outdata = srcdata;
4504: PC+= 2;
4505: }
4506:
4507: void cpu_op_708b(t_ipc *ipc) /* TST */ {
4508: /* mask fff8, bits 4a98, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4509: int srcreg = (ipc->opcode >> 0) & 7;
4510: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4);
4511: uint32 srcdata = fetchlong(srcaddr);
4512: uint32 outdata = srcdata;
4513:
4514: VFLAG = 0;
4515: CFLAG = 0;
4516: NFLAG = ((sint32)outdata) < 0;
4517: ZFLAG = !outdata;
4518: PC+= 2;
4519: }
4520:
4521: void cpu_op_709a(t_ipc *ipc) /* TST */ {
4522: /* mask fff8, bits 4aa0, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4523: int srcreg = (ipc->opcode >> 0) & 7;
4524: uint32 srcaddr = ADDRREG(srcreg)-=4;
4525: uint32 srcdata = fetchlong(srcaddr);
4526: uint32 outdata = srcdata;
4527: PC+= 2;
4528: }
4529:
4530: void cpu_op_709b(t_ipc *ipc) /* TST */ {
4531: /* mask fff8, bits 4aa0, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4532: int srcreg = (ipc->opcode >> 0) & 7;
4533: uint32 srcaddr = ADDRREG(srcreg)-=4;
4534: uint32 srcdata = fetchlong(srcaddr);
4535: uint32 outdata = srcdata;
4536:
4537: VFLAG = 0;
4538: CFLAG = 0;
4539: NFLAG = ((sint32)outdata) < 0;
4540: ZFLAG = !outdata;
4541: PC+= 2;
4542: }
4543:
4544: void cpu_op_710a(t_ipc *ipc) /* TST */ {
4545: /* mask fff8, bits 4aa8, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4546: int srcreg = (ipc->opcode >> 0) & 7;
4547: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
4548: uint32 srcdata = fetchlong(srcaddr);
4549: uint32 outdata = srcdata;
4550: PC+= 4;
4551: }
4552:
4553: void cpu_op_710b(t_ipc *ipc) /* TST */ {
4554: /* mask fff8, bits 4aa8, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4555: int srcreg = (ipc->opcode >> 0) & 7;
4556: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
4557: uint32 srcdata = fetchlong(srcaddr);
4558: uint32 outdata = srcdata;
4559:
4560: VFLAG = 0;
4561: CFLAG = 0;
4562: NFLAG = ((sint32)outdata) < 0;
4563: ZFLAG = !outdata;
4564: PC+= 4;
4565: }
4566:
4567: void cpu_op_711a(t_ipc *ipc) /* TST */ {
4568: /* mask fff8, bits 4ab0, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4569: int srcreg = (ipc->opcode >> 0) & 7;
4570: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
4571: uint32 srcdata = fetchlong(srcaddr);
4572: uint32 outdata = srcdata;
4573: PC+= 4;
4574: }
4575:
4576: void cpu_op_711b(t_ipc *ipc) /* TST */ {
4577: /* mask fff8, bits 4ab0, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4578: int srcreg = (ipc->opcode >> 0) & 7;
4579: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
4580: uint32 srcdata = fetchlong(srcaddr);
4581: uint32 outdata = srcdata;
4582:
4583: VFLAG = 0;
4584: CFLAG = 0;
4585: NFLAG = ((sint32)outdata) < 0;
4586: ZFLAG = !outdata;
4587: PC+= 4;
4588: }
4589:
4590: void cpu_op_712a(t_ipc *ipc) /* TST */ {
4591: /* mask ffff, bits 4ab8, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4592: uint32 srcaddr = ipc->src;
4593: uint32 srcdata = fetchlong(srcaddr);
4594: uint32 outdata = srcdata;
4595: PC+= 4;
4596: }
4597:
4598: void cpu_op_712b(t_ipc *ipc) /* TST */ {
4599: /* mask ffff, bits 4ab8, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4600: uint32 srcaddr = ipc->src;
4601: uint32 srcdata = fetchlong(srcaddr);
4602: uint32 outdata = srcdata;
4603:
4604: VFLAG = 0;
4605: CFLAG = 0;
4606: NFLAG = ((sint32)outdata) < 0;
4607: ZFLAG = !outdata;
4608: PC+= 4;
4609: }
4610:
4611: void cpu_op_713a(t_ipc *ipc) /* TST */ {
4612: /* mask ffff, bits 4ab9, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4613: uint32 srcaddr = ipc->src;
4614: uint32 srcdata = fetchlong(srcaddr);
4615: uint32 outdata = srcdata;
4616: PC+= 6;
4617: }
4618:
4619: void cpu_op_713b(t_ipc *ipc) /* TST */ {
4620: /* mask ffff, bits 4ab9, mnemonic 43, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4621: uint32 srcaddr = ipc->src;
4622: uint32 srcdata = fetchlong(srcaddr);
4623: uint32 outdata = srcdata;
4624:
4625: VFLAG = 0;
4626: CFLAG = 0;
4627: NFLAG = ((sint32)outdata) < 0;
4628: ZFLAG = !outdata;
4629: PC+= 6;
4630: }
4631:
4632: void cpu_op_714a(t_ipc *ipc) /* TAS */ {
4633: /* mask fff8, bits 4ac0, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4634: int srcreg = (ipc->opcode >> 0) & 7;
4635: uint8 srcdata = DATAREG(srcreg);
4636: uint8 outdata = srcdata;
4637: outdata|= 1<<7;
4638: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
4639: PC+= 2;
4640: }
4641:
4642: void cpu_op_714b(t_ipc *ipc) /* TAS */ {
4643: /* mask fff8, bits 4ac0, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4644: int srcreg = (ipc->opcode >> 0) & 7;
4645: uint8 srcdata = DATAREG(srcreg);
4646: uint8 outdata = srcdata;
4647:
4648: VFLAG = 0;
4649: CFLAG = 0;
4650: NFLAG = ((sint8)outdata) < 0;
4651: ZFLAG = !outdata;
4652: outdata|= 1<<7;
4653: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
4654: PC+= 2;
4655: }
4656:
4657: void cpu_op_715a(t_ipc *ipc) /* TAS */ {
4658: /* mask fff8, bits 4ad0, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4659: int srcreg = (ipc->opcode >> 0) & 7;
4660: uint32 srcaddr = ADDRREG(srcreg);
4661: uint8 srcdata = fetchbyte(srcaddr);
4662: uint8 outdata = srcdata;
4663: outdata|= 1<<7;
4664: storebyte(srcaddr, outdata);
4665: PC+= 2;
4666: }
4667:
4668: void cpu_op_715b(t_ipc *ipc) /* TAS */ {
4669: /* mask fff8, bits 4ad0, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4670: int srcreg = (ipc->opcode >> 0) & 7;
4671: uint32 srcaddr = ADDRREG(srcreg);
4672: uint8 srcdata = fetchbyte(srcaddr);
4673: uint8 outdata = srcdata;
4674:
4675: VFLAG = 0;
4676: CFLAG = 0;
4677: NFLAG = ((sint8)outdata) < 0;
4678: ZFLAG = !outdata;
4679: outdata|= 1<<7;
4680: storebyte(srcaddr, outdata);
4681: PC+= 2;
4682: }
4683:
4684: void cpu_op_716a(t_ipc *ipc) /* TAS */ {
4685: /* mask fff8, bits 4ad8, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4686: int srcreg = (ipc->opcode >> 0) & 7;
4687: uint32 srcaddr = ADDRREG(srcreg);
4688: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
4689: uint8 srcdata = fetchbyte(srcaddr);
4690: uint8 outdata = srcdata;
4691: outdata|= 1<<7;
4692: storebyte(srcaddr, outdata);
4693: PC+= 2;
4694: }
4695:
4696: void cpu_op_716b(t_ipc *ipc) /* TAS */ {
4697: /* mask fff8, bits 4ad8, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4698: int srcreg = (ipc->opcode >> 0) & 7;
4699: uint32 srcaddr = ADDRREG(srcreg);
4700: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
4701: uint8 srcdata = fetchbyte(srcaddr);
4702: uint8 outdata = srcdata;
4703:
4704: VFLAG = 0;
4705: CFLAG = 0;
4706: NFLAG = ((sint8)outdata) < 0;
4707: ZFLAG = !outdata;
4708: outdata|= 1<<7;
4709: storebyte(srcaddr, outdata);
4710: PC+= 2;
4711: }
4712:
4713: void cpu_op_717a(t_ipc *ipc) /* TAS */ {
4714: /* mask fff8, bits 4ae0, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4715: int srcreg = (ipc->opcode >> 0) & 7;
4716: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
4717: uint8 srcdata = fetchbyte(srcaddr);
4718: uint8 outdata = srcdata;
4719: outdata|= 1<<7;
4720: storebyte(srcaddr, outdata);
4721: PC+= 2;
4722: }
4723:
4724: void cpu_op_717b(t_ipc *ipc) /* TAS */ {
4725: /* mask fff8, bits 4ae0, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4726: int srcreg = (ipc->opcode >> 0) & 7;
4727: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
4728: uint8 srcdata = fetchbyte(srcaddr);
4729: uint8 outdata = srcdata;
4730:
4731: VFLAG = 0;
4732: CFLAG = 0;
4733: NFLAG = ((sint8)outdata) < 0;
4734: ZFLAG = !outdata;
4735: outdata|= 1<<7;
4736: storebyte(srcaddr, outdata);
4737: PC+= 2;
4738: }
4739:
4740: void cpu_op_718a(t_ipc *ipc) /* TAS */ {
4741: /* mask fff8, bits 4ae8, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4742: int srcreg = (ipc->opcode >> 0) & 7;
4743: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
4744: uint8 srcdata = fetchbyte(srcaddr);
4745: uint8 outdata = srcdata;
4746: outdata|= 1<<7;
4747: storebyte(srcaddr, outdata);
4748: PC+= 4;
4749: }
4750:
4751: void cpu_op_718b(t_ipc *ipc) /* TAS */ {
4752: /* mask fff8, bits 4ae8, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4753: int srcreg = (ipc->opcode >> 0) & 7;
4754: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
4755: uint8 srcdata = fetchbyte(srcaddr);
4756: uint8 outdata = srcdata;
4757:
4758: VFLAG = 0;
4759: CFLAG = 0;
4760: NFLAG = ((sint8)outdata) < 0;
4761: ZFLAG = !outdata;
4762: outdata|= 1<<7;
4763: storebyte(srcaddr, outdata);
4764: PC+= 4;
4765: }
4766:
4767: void cpu_op_719a(t_ipc *ipc) /* TAS */ {
4768: /* mask fff8, bits 4af0, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4769: int srcreg = (ipc->opcode >> 0) & 7;
4770: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
4771: uint8 srcdata = fetchbyte(srcaddr);
4772: uint8 outdata = srcdata;
4773: outdata|= 1<<7;
4774: storebyte(srcaddr, outdata);
4775: PC+= 4;
4776: }
4777:
4778: void cpu_op_719b(t_ipc *ipc) /* TAS */ {
4779: /* mask fff8, bits 4af0, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4780: int srcreg = (ipc->opcode >> 0) & 7;
4781: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
4782: uint8 srcdata = fetchbyte(srcaddr);
4783: uint8 outdata = srcdata;
4784:
4785: VFLAG = 0;
4786: CFLAG = 0;
4787: NFLAG = ((sint8)outdata) < 0;
4788: ZFLAG = !outdata;
4789: outdata|= 1<<7;
4790: storebyte(srcaddr, outdata);
4791: PC+= 4;
4792: }
4793:
4794: void cpu_op_720a(t_ipc *ipc) /* TAS */ {
4795: /* mask ffff, bits 4af8, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4796: uint32 srcaddr = ipc->src;
4797: uint8 srcdata = fetchbyte(srcaddr);
4798: uint8 outdata = srcdata;
4799: outdata|= 1<<7;
4800: storebyte(srcaddr, outdata);
4801: PC+= 4;
4802: }
4803:
4804: void cpu_op_720b(t_ipc *ipc) /* TAS */ {
4805: /* mask ffff, bits 4af8, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4806: uint32 srcaddr = ipc->src;
4807: uint8 srcdata = fetchbyte(srcaddr);
4808: uint8 outdata = srcdata;
4809:
4810: VFLAG = 0;
4811: CFLAG = 0;
4812: NFLAG = ((sint8)outdata) < 0;
4813: ZFLAG = !outdata;
4814: outdata|= 1<<7;
4815: storebyte(srcaddr, outdata);
4816: PC+= 4;
4817: }
4818:
4819: void cpu_op_721a(t_ipc *ipc) /* TAS */ {
4820: /* mask ffff, bits 4af9, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4821: uint32 srcaddr = ipc->src;
4822: uint8 srcdata = fetchbyte(srcaddr);
4823: uint8 outdata = srcdata;
4824: outdata|= 1<<7;
4825: storebyte(srcaddr, outdata);
4826: PC+= 6;
4827: }
4828:
4829: void cpu_op_721b(t_ipc *ipc) /* TAS */ {
4830: /* mask ffff, bits 4af9, mnemonic 44, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4831: uint32 srcaddr = ipc->src;
4832: uint8 srcdata = fetchbyte(srcaddr);
4833: uint8 outdata = srcdata;
4834:
4835: VFLAG = 0;
4836: CFLAG = 0;
4837: NFLAG = ((sint8)outdata) < 0;
4838: ZFLAG = !outdata;
4839: outdata|= 1<<7;
4840: storebyte(srcaddr, outdata);
4841: PC+= 6;
4842: }
4843:
4844: void cpu_op_722a(t_ipc *ipc) /* ILLEGAL */ {
4845: /* mask ffff, bits 4afc, mnemonic 0, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 0, stype 20, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4846: printf("Illegal instruction @ %x\n", PC);
4847: exit(1);
4848: PC+= 2;
4849: }
4850:
4851: void cpu_op_723a(t_ipc *ipc) /* MOVEMMR */ {
4852: /* mask fff8, bits 4c90, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
4853: uint16 srcdata = ipc->src;
4854: int dstreg = (ipc->opcode >> 0) & 7;
4855: uint32 dstaddr = ADDRREG(dstreg);
4856: uint8 addrmask = (srcdata & 0xFF00) >> 8;
4857: uint8 datamask = srcdata & 0xFF;
4858: while (datamask) {
4859: DATAREG(movem_bit[datamask]) = (sint32)(sint16)fetchword(dstaddr);
4860: datamask&= ~(1<<movem_bit[datamask]);
4861: dstaddr+= 2;
4862: }
4863: while (addrmask) {
4864: ADDRREG(movem_bit[addrmask]) = (sint32)(sint16)fetchword(dstaddr);
4865: addrmask&= ~(1<<movem_bit[addrmask]);
4866: dstaddr+= 2;
4867: }
4868: PC+= 4;
4869: }
4870:
4871: void cpu_op_724a(t_ipc *ipc) /* MOVEMMR */ {
4872: /* mask fff8, bits 4c98, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
4873: uint16 srcdata = ipc->src;
4874: int dstreg = (ipc->opcode >> 0) & 7;
4875: uint32 dstaddr = ADDRREG(dstreg);
4876: uint8 addrmask = (srcdata & 0xFF00) >> 8;
4877: uint8 datamask = srcdata & 0xFF;
4878: while (datamask) {
4879: DATAREG(movem_bit[datamask]) = (sint32)(sint16)fetchword(dstaddr);
4880: datamask&= ~(1<<movem_bit[datamask]);
4881: dstaddr+= 2;
4882: }
4883: while (addrmask) {
4884: ADDRREG(movem_bit[addrmask]) = (sint32)(sint16)fetchword(dstaddr);
4885: addrmask&= ~(1<<movem_bit[addrmask]);
4886: dstaddr+= 2;
4887: }
4888: ADDRREG(dstreg) = dstaddr;
4889: PC+= 4;
4890: }
4891:
4892: void cpu_op_725a(t_ipc *ipc) /* MOVEMMR */ {
4893: /* mask fff8, bits 4ca8, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
4894: uint16 srcdata = ipc->src;
4895: int dstreg = (ipc->opcode >> 0) & 7;
4896: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
4897: uint8 addrmask = (srcdata & 0xFF00) >> 8;
4898: uint8 datamask = srcdata & 0xFF;
4899: while (datamask) {
4900: DATAREG(movem_bit[datamask]) = (sint32)(sint16)fetchword(dstaddr);
4901: datamask&= ~(1<<movem_bit[datamask]);
4902: dstaddr+= 2;
4903: }
4904: while (addrmask) {
4905: ADDRREG(movem_bit[addrmask]) = (sint32)(sint16)fetchword(dstaddr);
4906: addrmask&= ~(1<<movem_bit[addrmask]);
4907: dstaddr+= 2;
4908: }
4909: PC+= 6;
4910: }
4911:
4912: void cpu_op_726a(t_ipc *ipc) /* MOVEMMR */ {
4913: /* mask fff8, bits 4cb0, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
4914: uint16 srcdata = ipc->src;
4915: int dstreg = (ipc->opcode >> 0) & 7;
4916: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
4917: uint8 addrmask = (srcdata & 0xFF00) >> 8;
4918: uint8 datamask = srcdata & 0xFF;
4919: while (datamask) {
4920: DATAREG(movem_bit[datamask]) = (sint32)(sint16)fetchword(dstaddr);
4921: datamask&= ~(1<<movem_bit[datamask]);
4922: dstaddr+= 2;
4923: }
4924: while (addrmask) {
4925: ADDRREG(movem_bit[addrmask]) = (sint32)(sint16)fetchword(dstaddr);
4926: addrmask&= ~(1<<movem_bit[addrmask]);
4927: dstaddr+= 2;
4928: }
4929: PC+= 6;
4930: }
4931:
4932: void cpu_op_727a(t_ipc *ipc) /* MOVEMMR */ {
4933: /* mask ffff, bits 4cb8, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
4934: uint16 srcdata = ipc->src;
4935: uint32 dstaddr = ipc->dst;
4936: uint8 addrmask = (srcdata & 0xFF00) >> 8;
4937: uint8 datamask = srcdata & 0xFF;
4938: while (datamask) {
4939: DATAREG(movem_bit[datamask]) = (sint32)(sint16)fetchword(dstaddr);
4940: datamask&= ~(1<<movem_bit[datamask]);
4941: dstaddr+= 2;
4942: }
4943: while (addrmask) {
4944: ADDRREG(movem_bit[addrmask]) = (sint32)(sint16)fetchword(dstaddr);
4945: addrmask&= ~(1<<movem_bit[addrmask]);
4946: dstaddr+= 2;
4947: }
4948: PC+= 6;
4949: }
4950:
4951: void cpu_op_728a(t_ipc *ipc) /* MOVEMMR */ {
4952: /* mask ffff, bits 4cb9, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
4953: uint16 srcdata = ipc->src;
4954: uint32 dstaddr = ipc->dst;
4955: uint8 addrmask = (srcdata & 0xFF00) >> 8;
4956: uint8 datamask = srcdata & 0xFF;
4957: while (datamask) {
4958: DATAREG(movem_bit[datamask]) = (sint32)(sint16)fetchword(dstaddr);
4959: datamask&= ~(1<<movem_bit[datamask]);
4960: dstaddr+= 2;
4961: }
4962: while (addrmask) {
4963: ADDRREG(movem_bit[addrmask]) = (sint32)(sint16)fetchword(dstaddr);
4964: addrmask&= ~(1<<movem_bit[addrmask]);
4965: dstaddr+= 2;
4966: }
4967: PC+= 8;
4968: }
4969:
4970: void cpu_op_729a(t_ipc *ipc) /* MOVEMMR */ {
4971: /* mask ffff, bits 4cba, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 9, sbitpos 0, dbitpos 0, immvalue 0 */
4972: uint16 srcdata = ipc->src;
4973: uint32 dstaddr = ipc->dst;
4974: uint8 addrmask = (srcdata & 0xFF00) >> 8;
4975: uint8 datamask = srcdata & 0xFF;
4976: while (datamask) {
4977: DATAREG(movem_bit[datamask]) = (sint32)(sint16)fetchword(dstaddr);
4978: datamask&= ~(1<<movem_bit[datamask]);
4979: dstaddr+= 2;
4980: }
4981: while (addrmask) {
4982: ADDRREG(movem_bit[addrmask]) = (sint32)(sint16)fetchword(dstaddr);
4983: addrmask&= ~(1<<movem_bit[addrmask]);
4984: dstaddr+= 2;
4985: }
4986: PC+= 6;
4987: }
4988:
4989: void cpu_op_730a(t_ipc *ipc) /* MOVEMMR */ {
4990: /* mask ffff, bits 4cbb, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 10, sbitpos 0, dbitpos 0, immvalue 0 */
4991: uint16 srcdata = ipc->src;
4992: uint32 dstaddr = idxval_dst(ipc);
4993: uint8 addrmask = (srcdata & 0xFF00) >> 8;
4994: uint8 datamask = srcdata & 0xFF;
4995: while (datamask) {
4996: DATAREG(movem_bit[datamask]) = (sint32)(sint16)fetchword(dstaddr);
4997: datamask&= ~(1<<movem_bit[datamask]);
4998: dstaddr+= 2;
4999: }
5000: while (addrmask) {
5001: ADDRREG(movem_bit[addrmask]) = (sint32)(sint16)fetchword(dstaddr);
5002: addrmask&= ~(1<<movem_bit[addrmask]);
5003: dstaddr+= 2;
5004: }
5005: PC+= 6;
5006: }
5007:
5008: void cpu_op_731a(t_ipc *ipc) /* MOVEMMR */ {
5009: /* mask fff8, bits 4cd0, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 2, sbitpos 0, dbitpos 0, immvalue 0 */
5010: uint16 srcdata = ipc->src;
5011: int dstreg = (ipc->opcode >> 0) & 7;
5012: uint32 dstaddr = ADDRREG(dstreg);
5013: uint8 addrmask = (srcdata & 0xFF00) >> 8;
5014: uint8 datamask = srcdata & 0xFF;
5015: while (datamask) {
5016: DATAREG(movem_bit[datamask]) = fetchlong(dstaddr);
5017: datamask&= ~(1<<movem_bit[datamask]);
5018: dstaddr+= 4;
5019: }
5020: while (addrmask) {
5021: ADDRREG(movem_bit[addrmask]) = fetchlong(dstaddr);
5022: addrmask&= ~(1<<movem_bit[addrmask]);
5023: dstaddr+= 4;
5024: }
5025: PC+= 4;
5026: }
5027:
5028: void cpu_op_732a(t_ipc *ipc) /* MOVEMMR */ {
5029: /* mask fff8, bits 4cd8, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 3, sbitpos 0, dbitpos 0, immvalue 0 */
5030: uint16 srcdata = ipc->src;
5031: int dstreg = (ipc->opcode >> 0) & 7;
5032: uint32 dstaddr = ADDRREG(dstreg);
5033: uint8 addrmask = (srcdata & 0xFF00) >> 8;
5034: uint8 datamask = srcdata & 0xFF;
5035: while (datamask) {
5036: DATAREG(movem_bit[datamask]) = fetchlong(dstaddr);
5037: datamask&= ~(1<<movem_bit[datamask]);
5038: dstaddr+= 4;
5039: }
5040: while (addrmask) {
5041: ADDRREG(movem_bit[addrmask]) = fetchlong(dstaddr);
5042: addrmask&= ~(1<<movem_bit[addrmask]);
5043: dstaddr+= 4;
5044: }
5045: ADDRREG(dstreg) = dstaddr;
5046: PC+= 4;
5047: }
5048:
5049: void cpu_op_733a(t_ipc *ipc) /* MOVEMMR */ {
5050: /* mask fff8, bits 4ce8, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 5, sbitpos 0, dbitpos 0, immvalue 0 */
5051: uint16 srcdata = ipc->src;
5052: int dstreg = (ipc->opcode >> 0) & 7;
5053: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
5054: uint8 addrmask = (srcdata & 0xFF00) >> 8;
5055: uint8 datamask = srcdata & 0xFF;
5056: while (datamask) {
5057: DATAREG(movem_bit[datamask]) = fetchlong(dstaddr);
5058: datamask&= ~(1<<movem_bit[datamask]);
5059: dstaddr+= 4;
5060: }
5061: while (addrmask) {
5062: ADDRREG(movem_bit[addrmask]) = fetchlong(dstaddr);
5063: addrmask&= ~(1<<movem_bit[addrmask]);
5064: dstaddr+= 4;
5065: }
5066: PC+= 6;
5067: }
5068:
5069: void cpu_op_734a(t_ipc *ipc) /* MOVEMMR */ {
5070: /* mask fff8, bits 4cf0, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 6, sbitpos 0, dbitpos 0, immvalue 0 */
5071: uint16 srcdata = ipc->src;
5072: int dstreg = (ipc->opcode >> 0) & 7;
5073: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
5074: uint8 addrmask = (srcdata & 0xFF00) >> 8;
5075: uint8 datamask = srcdata & 0xFF;
5076: while (datamask) {
5077: DATAREG(movem_bit[datamask]) = fetchlong(dstaddr);
5078: datamask&= ~(1<<movem_bit[datamask]);
5079: dstaddr+= 4;
5080: }
5081: while (addrmask) {
5082: ADDRREG(movem_bit[addrmask]) = fetchlong(dstaddr);
5083: addrmask&= ~(1<<movem_bit[addrmask]);
5084: dstaddr+= 4;
5085: }
5086: PC+= 6;
5087: }
5088:
5089: void cpu_op_735a(t_ipc *ipc) /* MOVEMMR */ {
5090: /* mask ffff, bits 4cf8, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 7, sbitpos 0, dbitpos 0, immvalue 0 */
5091: uint16 srcdata = ipc->src;
5092: uint32 dstaddr = ipc->dst;
5093: uint8 addrmask = (srcdata & 0xFF00) >> 8;
5094: uint8 datamask = srcdata & 0xFF;
5095: while (datamask) {
5096: DATAREG(movem_bit[datamask]) = fetchlong(dstaddr);
5097: datamask&= ~(1<<movem_bit[datamask]);
5098: dstaddr+= 4;
5099: }
5100: while (addrmask) {
5101: ADDRREG(movem_bit[addrmask]) = fetchlong(dstaddr);
5102: addrmask&= ~(1<<movem_bit[addrmask]);
5103: dstaddr+= 4;
5104: }
5105: PC+= 6;
5106: }
5107:
5108: void cpu_op_736a(t_ipc *ipc) /* MOVEMMR */ {
5109: /* mask ffff, bits 4cf9, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 8, sbitpos 0, dbitpos 0, immvalue 0 */
5110: uint16 srcdata = ipc->src;
5111: uint32 dstaddr = ipc->dst;
5112: uint8 addrmask = (srcdata & 0xFF00) >> 8;
5113: uint8 datamask = srcdata & 0xFF;
5114: while (datamask) {
5115: DATAREG(movem_bit[datamask]) = fetchlong(dstaddr);
5116: datamask&= ~(1<<movem_bit[datamask]);
5117: dstaddr+= 4;
5118: }
5119: while (addrmask) {
5120: ADDRREG(movem_bit[addrmask]) = fetchlong(dstaddr);
5121: addrmask&= ~(1<<movem_bit[addrmask]);
5122: dstaddr+= 4;
5123: }
5124: PC+= 8;
5125: }
5126:
5127: void cpu_op_737a(t_ipc *ipc) /* MOVEMMR */ {
5128: /* mask ffff, bits 4cfa, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 9, sbitpos 0, dbitpos 0, immvalue 0 */
5129: uint16 srcdata = ipc->src;
5130: uint32 dstaddr = ipc->dst;
5131: uint8 addrmask = (srcdata & 0xFF00) >> 8;
5132: uint8 datamask = srcdata & 0xFF;
5133: while (datamask) {
5134: DATAREG(movem_bit[datamask]) = fetchlong(dstaddr);
5135: datamask&= ~(1<<movem_bit[datamask]);
5136: dstaddr+= 4;
5137: }
5138: while (addrmask) {
5139: ADDRREG(movem_bit[addrmask]) = fetchlong(dstaddr);
5140: addrmask&= ~(1<<movem_bit[addrmask]);
5141: dstaddr+= 4;
5142: }
5143: PC+= 6;
5144: }
5145:
5146: void cpu_op_738a(t_ipc *ipc) /* MOVEMMR */ {
5147: /* mask ffff, bits 4cfb, mnemonic 28, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 10, sbitpos 0, dbitpos 0, immvalue 0 */
5148: uint16 srcdata = ipc->src;
5149: uint32 dstaddr = idxval_dst(ipc);
5150: uint8 addrmask = (srcdata & 0xFF00) >> 8;
5151: uint8 datamask = srcdata & 0xFF;
5152: while (datamask) {
5153: DATAREG(movem_bit[datamask]) = fetchlong(dstaddr);
5154: datamask&= ~(1<<movem_bit[datamask]);
5155: dstaddr+= 4;
5156: }
5157: while (addrmask) {
5158: ADDRREG(movem_bit[addrmask]) = fetchlong(dstaddr);
5159: addrmask&= ~(1<<movem_bit[addrmask]);
5160: dstaddr+= 4;
5161: }
5162: PC+= 6;
5163: }
5164:
5165: void cpu_op_739a(t_ipc *ipc) /* TRAP */ {
5166: /* mask fff0, bits 4e40, mnemonic 47, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 0, stype 16, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5167: unsigned int srcdata = ipc->src;
5168:
5169: reg68k_vector(V_TRAP+srcdata, PC+2);
5170: }
5171:
5172: void cpu_op_740a(t_ipc *ipc) /* LINK */ {
5173: /* mask fff8, bits 4e50, mnemonic 51, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 12, dtype 1, sbitpos 0, dbitpos 0, immvalue 0 */
5174: uint16 srcdata = ipc->src;
5175: int dstreg = (ipc->opcode >> 0) & 7;
5176: uint32 dstdata = ADDRREG(dstreg);
5177:
5178: ADDRREG(7)-= 4;
5179: storelong(ADDRREG(7), dstdata);
5180: ADDRREG(dstreg) = ADDRREG(7);
5181: ADDRREG(7)+= (sint16)srcdata;
5182: PC+= 4;
5183: }
5184:
5185: void cpu_op_741a(t_ipc *ipc) /* UNLK */ {
5186: /* mask fff8, bits 4e58, mnemonic 52, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 1, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5187: int srcreg = (ipc->opcode >> 0) & 7;
5188: uint32 srcdata = ADDRREG(srcreg);
5189:
5190: ADDRREG(srcreg) = fetchlong(srcdata);
5191: ADDRREG(7) = srcdata+4;
5192: PC+= 2;
5193: }
5194:
5195: void cpu_op_742a(t_ipc *ipc) /* MOVETUSP */ {
5196: /* mask fff8, bits 4e60, mnemonic 29, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 1, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5197: int srcreg = (ipc->opcode >> 0) & 7;
5198: uint32 srcdata = ADDRREG(srcreg);
5199:
5200: if (!SFLAG)
5201: reg68k_vector(V_PRIVILEGE, PC+2);
5202:
5203: SP = srcdata;
5204: PC+= 2;
5205: }
5206:
5207: void cpu_op_743a(t_ipc *ipc) /* MOVEFUSP */ {
5208: /* mask fff8, bits 4e68, mnemonic 30, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 1, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5209: int srcreg = (ipc->opcode >> 0) & 7;
5210: uint32 outdata;
5211:
5212: if (!SFLAG)
5213: reg68k_vector(V_PRIVILEGE, PC+2);
5214:
5215: outdata = SP;
5216: ADDRREG(srcreg) = outdata;
5217: PC+= 2;
5218: }
5219:
5220: void cpu_op_744a(t_ipc *ipc) /* RESET */ {
5221: /* mask ffff, bits 4e70, mnemonic 48, priv -1, endblk -1, imm_notzero 0, used 0 set 0, size 0, stype 20, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5222: printf("RESET @ %x\n", PC);
5223: exit(1);
5224: PC+= 2;
5225: }
5226:
5227: void cpu_op_745a(t_ipc *ipc) /* NOP */ {
5228: /* mask ffff, bits 4e71, mnemonic 49, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 0, stype 20, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5229: PC+= 2;
5230: }
5231:
5232: void cpu_op_746a(t_ipc *ipc) /* STOP */ {
5233: /* mask ffff, bits 4e72, mnemonic 50, priv -1, endblk -1, imm_notzero 0, used 0 set -1, size 0, stype 12, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5234: uint16 srcdata = ipc->src;
5235:
5236: switch(regs.stop) {
5237: case 1:
5238: break;
5239: case 2:
5240: PC+= 2;
5241: break;
5242: default:
5243: if (!(SFLAG && (srcdata & 1<<13)))
5244: reg68k_vector(V_PRIVILEGE, PC+4);
5245: SR = srcdata;
5246: STOP = 1;
5247: printf("STOP @ %%x\n", PC);
5248: exit(1);
5249: }
5250: PC+= 4;
5251: }
5252:
5253: void cpu_op_746b(t_ipc *ipc) /* STOP */ {
5254: /* mask ffff, bits 4e72, mnemonic 50, priv -1, endblk -1, imm_notzero 0, used 0 set -1, size 0, stype 12, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5255: uint16 srcdata = ipc->src;
5256:
5257: switch(regs.stop) {
5258: case 1:
5259: break;
5260: case 2:
5261: PC+= 2;
5262: break;
5263: default:
5264: if (!(SFLAG && (srcdata & 1<<13)))
5265: reg68k_vector(V_PRIVILEGE, PC+4);
5266: SR = srcdata;
5267: STOP = 1;
5268: printf("STOP @ %%x\n", PC);
5269: exit(1);
5270: }
5271: PC+= 4;
5272: }
5273:
5274: void cpu_op_747a(t_ipc *ipc) /* RTE */ {
5275: /* mask ffff, bits 4e73, mnemonic 53, priv -1, endblk -1, imm_notzero 0, used 0 set -1, size 0, stype 20, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5276: if (!SFLAG)
5277: reg68k_vector(V_PRIVILEGE, PC+2);
5278:
5279: SR = fetchword(ADDRREG(7));
5280: PC = fetchlong(ADDRREG(7)+2);
5281: ADDRREG(7)+= 6;
5282: if (!reg68k_sr.sr_struct.s) {
5283: /* mode change, swap SP and A7 */
5284: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
5285: }
5286: }
5287:
5288: void cpu_op_747b(t_ipc *ipc) /* RTE */ {
5289: /* mask ffff, bits 4e73, mnemonic 53, priv -1, endblk -1, imm_notzero 0, used 0 set -1, size 0, stype 20, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5290: if (!SFLAG)
5291: reg68k_vector(V_PRIVILEGE, PC+2);
5292:
5293: SR = fetchword(ADDRREG(7));
5294: PC = fetchlong(ADDRREG(7)+2);
5295: ADDRREG(7)+= 6;
5296: if (!reg68k_sr.sr_struct.s) {
5297: /* mode change, swap SP and A7 */
5298: ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP;
5299: }
5300: }
5301:
5302: void cpu_op_748a(t_ipc *ipc) /* RTS */ {
5303: /* mask ffff, bits 4e75, mnemonic 54, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 0, stype 20, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5304: PC = fetchlong(ADDRREG(7));
5305: ADDRREG(7)+= 4;
5306: }
5307:
5308: void cpu_op_749a(t_ipc *ipc) /* TRAPV */ {
5309: /* mask ffff, bits 4e76, mnemonic 46, priv 0, endblk -1, imm_notzero 0, used 8 set 0, size 0, stype 20, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5310: if (VFLAG) {
5311: reg68k_vector(V_TRAPV, PC+2);
5312: }
5313: PC+= 2;
5314: }
5315:
5316: void cpu_op_750a(t_ipc *ipc) /* RTR */ {
5317: /* mask ffff, bits 4e77, mnemonic 55, priv 0, endblk -1, imm_notzero 0, used 0 set -1, size 0, stype 20, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5318: SR = (SR & ~0xFF) | (fetchword(ADDRREG(7)) & 0xFF);
5319: PC = fetchlong(ADDRREG(7)+2);
5320: ADDRREG(7)+= 6;
5321: }
5322:
5323: void cpu_op_750b(t_ipc *ipc) /* RTR */ {
5324: /* mask ffff, bits 4e77, mnemonic 55, priv 0, endblk -1, imm_notzero 0, used 0 set -1, size 0, stype 20, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5325: SR = (SR & ~0xFF) | (fetchword(ADDRREG(7)) & 0xFF);
5326: PC = fetchlong(ADDRREG(7)+2);
5327: ADDRREG(7)+= 6;
5328: }
5329:
5330: void cpu_op_751a(t_ipc *ipc) /* JSR */ {
5331: /* mask fff8, bits 4e90, mnemonic 56, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5332: int srcreg = (ipc->opcode >> 0) & 7;
5333: uint32 srcaddr = ADDRREG(srcreg);
5334:
5335: ADDRREG(7)-= 4;
5336: storelong(ADDRREG(7), PC+2);
5337: PC = srcaddr;
5338: }
5339:
5340: void cpu_op_752a(t_ipc *ipc) /* JSR */ {
5341: /* mask fff8, bits 4ea8, mnemonic 56, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5342: int srcreg = (ipc->opcode >> 0) & 7;
5343: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
5344:
5345: ADDRREG(7)-= 4;
5346: storelong(ADDRREG(7), PC+4);
5347: PC = srcaddr;
5348: }
5349:
5350: void cpu_op_753a(t_ipc *ipc) /* JSR */ {
5351: /* mask fff8, bits 4eb0, mnemonic 56, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5352: int srcreg = (ipc->opcode >> 0) & 7;
5353: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
5354:
5355: ADDRREG(7)-= 4;
5356: storelong(ADDRREG(7), PC+4);
5357: PC = srcaddr;
5358: }
5359:
5360: void cpu_op_754a(t_ipc *ipc) /* JSR */ {
5361: /* mask ffff, bits 4eb8, mnemonic 56, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5362: uint32 srcaddr = ipc->src;
5363:
5364: ADDRREG(7)-= 4;
5365: storelong(ADDRREG(7), PC+4);
5366: PC = srcaddr;
5367: }
5368:
5369: void cpu_op_755a(t_ipc *ipc) /* JSR */ {
5370: /* mask ffff, bits 4eb9, mnemonic 56, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5371: uint32 srcaddr = ipc->src;
5372:
5373: ADDRREG(7)-= 4;
5374: storelong(ADDRREG(7), PC+6);
5375: PC = srcaddr;
5376: }
5377:
5378: void cpu_op_756a(t_ipc *ipc) /* JSR */ {
5379: /* mask ffff, bits 4eba, mnemonic 56, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 9, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5380: uint32 srcaddr = ipc->src;
5381:
5382: ADDRREG(7)-= 4;
5383: storelong(ADDRREG(7), PC+4);
5384: PC = srcaddr;
5385: }
5386:
5387: void cpu_op_757a(t_ipc *ipc) /* JSR */ {
5388: /* mask ffff, bits 4ebb, mnemonic 56, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 10, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5389: uint32 srcaddr = idxval_src(ipc);
5390:
5391: ADDRREG(7)-= 4;
5392: storelong(ADDRREG(7), PC+4);
5393: PC = srcaddr;
5394: }
5395:
5396: void cpu_op_758a(t_ipc *ipc) /* JMP */ {
5397: /* mask fff8, bits 4ed0, mnemonic 57, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5398: int srcreg = (ipc->opcode >> 0) & 7;
5399: uint32 srcaddr = ADDRREG(srcreg);
5400:
5401: PC = srcaddr;
5402: }
5403:
5404: void cpu_op_759a(t_ipc *ipc) /* JMP */ {
5405: /* mask fff8, bits 4ee8, mnemonic 57, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5406: int srcreg = (ipc->opcode >> 0) & 7;
5407: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
5408:
5409: PC = srcaddr;
5410: }
5411:
5412: void cpu_op_760a(t_ipc *ipc) /* JMP */ {
5413: /* mask fff8, bits 4ef0, mnemonic 57, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5414: int srcreg = (ipc->opcode >> 0) & 7;
5415: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
5416:
5417: PC = srcaddr;
5418: }
5419:
5420: void cpu_op_761a(t_ipc *ipc) /* JMP */ {
5421: /* mask ffff, bits 4ef8, mnemonic 57, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5422: uint32 srcaddr = ipc->src;
5423:
5424: PC = srcaddr;
5425: }
5426:
5427: void cpu_op_762a(t_ipc *ipc) /* JMP */ {
5428: /* mask ffff, bits 4ef9, mnemonic 57, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5429: uint32 srcaddr = ipc->src;
5430:
5431: PC = srcaddr;
5432: }
5433:
5434: void cpu_op_763a(t_ipc *ipc) /* JMP */ {
5435: /* mask ffff, bits 4efa, mnemonic 57, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 9, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5436: uint32 srcaddr = ipc->src;
5437:
5438: PC = srcaddr;
5439: }
5440:
5441: void cpu_op_764a(t_ipc *ipc) /* JMP */ {
5442: /* mask ffff, bits 4efb, mnemonic 57, priv 0, endblk -1, imm_notzero 0, used 0 set 0, size 3, stype 10, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
5443: uint32 srcaddr = idxval_src(ipc);
5444:
5445: PC = srcaddr;
5446: }
5447:
5448: void cpu_op_765a(t_ipc *ipc) /* CHK */ {
5449: /* mask f1f8, bits 4180, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5450: int srcreg = (ipc->opcode >> 0) & 7;
5451: uint16 srcdata = DATAREG(srcreg);
5452: int dstreg = (ipc->opcode >> 9) & 7;
5453: uint16 dstdata = DATAREG(dstreg);
5454:
5455: if ((sint16)srcdata < 0) {
5456: reg68k_vector(V_CHK, PC+2);
5457: } else if (dstdata > srcdata) {
5458: reg68k_vector(V_CHK, PC+2);
5459: }
5460: PC+= 2;
5461: }
5462:
5463: void cpu_op_765b(t_ipc *ipc) /* CHK */ {
5464: /* mask f1f8, bits 4180, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5465: int srcreg = (ipc->opcode >> 0) & 7;
5466: uint16 srcdata = DATAREG(srcreg);
5467: int dstreg = (ipc->opcode >> 9) & 7;
5468: uint16 dstdata = DATAREG(dstreg);
5469:
5470: if ((sint16)srcdata < 0) {
5471: NFLAG = 1;
5472: reg68k_vector(V_CHK, PC+2);
5473: } else if (dstdata > srcdata) {
5474: NFLAG = 0;
5475: reg68k_vector(V_CHK, PC+2);
5476: }
5477: PC+= 2;
5478: }
5479:
5480: void cpu_op_766a(t_ipc *ipc) /* CHK */ {
5481: /* mask f1f8, bits 4190, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5482: int srcreg = (ipc->opcode >> 0) & 7;
5483: uint32 srcaddr = ADDRREG(srcreg);
5484: uint16 srcdata = fetchword(srcaddr);
5485: int dstreg = (ipc->opcode >> 9) & 7;
5486: uint16 dstdata = DATAREG(dstreg);
5487:
5488: if ((sint16)srcdata < 0) {
5489: reg68k_vector(V_CHK, PC+2);
5490: } else if (dstdata > srcdata) {
5491: reg68k_vector(V_CHK, PC+2);
5492: }
5493: PC+= 2;
5494: }
5495:
5496: void cpu_op_766b(t_ipc *ipc) /* CHK */ {
5497: /* mask f1f8, bits 4190, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5498: int srcreg = (ipc->opcode >> 0) & 7;
5499: uint32 srcaddr = ADDRREG(srcreg);
5500: uint16 srcdata = fetchword(srcaddr);
5501: int dstreg = (ipc->opcode >> 9) & 7;
5502: uint16 dstdata = DATAREG(dstreg);
5503:
5504: if ((sint16)srcdata < 0) {
5505: NFLAG = 1;
5506: reg68k_vector(V_CHK, PC+2);
5507: } else if (dstdata > srcdata) {
5508: NFLAG = 0;
5509: reg68k_vector(V_CHK, PC+2);
5510: }
5511: PC+= 2;
5512: }
5513:
5514: void cpu_op_767a(t_ipc *ipc) /* CHK */ {
5515: /* mask f1f8, bits 4198, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5516: int srcreg = (ipc->opcode >> 0) & 7;
5517: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
5518: uint16 srcdata = fetchword(srcaddr);
5519: int dstreg = (ipc->opcode >> 9) & 7;
5520: uint16 dstdata = DATAREG(dstreg);
5521:
5522: if ((sint16)srcdata < 0) {
5523: reg68k_vector(V_CHK, PC+2);
5524: } else if (dstdata > srcdata) {
5525: reg68k_vector(V_CHK, PC+2);
5526: }
5527: PC+= 2;
5528: }
5529:
5530: void cpu_op_767b(t_ipc *ipc) /* CHK */ {
5531: /* mask f1f8, bits 4198, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5532: int srcreg = (ipc->opcode >> 0) & 7;
5533: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2);
5534: uint16 srcdata = fetchword(srcaddr);
5535: int dstreg = (ipc->opcode >> 9) & 7;
5536: uint16 dstdata = DATAREG(dstreg);
5537:
5538: if ((sint16)srcdata < 0) {
5539: NFLAG = 1;
5540: reg68k_vector(V_CHK, PC+2);
5541: } else if (dstdata > srcdata) {
5542: NFLAG = 0;
5543: reg68k_vector(V_CHK, PC+2);
5544: }
5545: PC+= 2;
5546: }
5547:
5548: void cpu_op_768a(t_ipc *ipc) /* CHK */ {
5549: /* mask f1f8, bits 41a0, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5550: int srcreg = (ipc->opcode >> 0) & 7;
5551: uint32 srcaddr = ADDRREG(srcreg)-=2;
5552: uint16 srcdata = fetchword(srcaddr);
5553: int dstreg = (ipc->opcode >> 9) & 7;
5554: uint16 dstdata = DATAREG(dstreg);
5555:
5556: if ((sint16)srcdata < 0) {
5557: reg68k_vector(V_CHK, PC+2);
5558: } else if (dstdata > srcdata) {
5559: reg68k_vector(V_CHK, PC+2);
5560: }
5561: PC+= 2;
5562: }
5563:
5564: void cpu_op_768b(t_ipc *ipc) /* CHK */ {
5565: /* mask f1f8, bits 41a0, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5566: int srcreg = (ipc->opcode >> 0) & 7;
5567: uint32 srcaddr = ADDRREG(srcreg)-=2;
5568: uint16 srcdata = fetchword(srcaddr);
5569: int dstreg = (ipc->opcode >> 9) & 7;
5570: uint16 dstdata = DATAREG(dstreg);
5571:
5572: if ((sint16)srcdata < 0) {
5573: NFLAG = 1;
5574: reg68k_vector(V_CHK, PC+2);
5575: } else if (dstdata > srcdata) {
5576: NFLAG = 0;
5577: reg68k_vector(V_CHK, PC+2);
5578: }
5579: PC+= 2;
5580: }
5581:
5582: void cpu_op_769a(t_ipc *ipc) /* CHK */ {
5583: /* mask f1f8, bits 41a8, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5584: int srcreg = (ipc->opcode >> 0) & 7;
5585: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
5586: uint16 srcdata = fetchword(srcaddr);
5587: int dstreg = (ipc->opcode >> 9) & 7;
5588: uint16 dstdata = DATAREG(dstreg);
5589:
5590: if ((sint16)srcdata < 0) {
5591: reg68k_vector(V_CHK, PC+4);
5592: } else if (dstdata > srcdata) {
5593: reg68k_vector(V_CHK, PC+4);
5594: }
5595: PC+= 4;
5596: }
5597:
5598: void cpu_op_769b(t_ipc *ipc) /* CHK */ {
5599: /* mask f1f8, bits 41a8, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5600: int srcreg = (ipc->opcode >> 0) & 7;
5601: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
5602: uint16 srcdata = fetchword(srcaddr);
5603: int dstreg = (ipc->opcode >> 9) & 7;
5604: uint16 dstdata = DATAREG(dstreg);
5605:
5606: if ((sint16)srcdata < 0) {
5607: NFLAG = 1;
5608: reg68k_vector(V_CHK, PC+4);
5609: } else if (dstdata > srcdata) {
5610: NFLAG = 0;
5611: reg68k_vector(V_CHK, PC+4);
5612: }
5613: PC+= 4;
5614: }
5615:
5616: void cpu_op_770a(t_ipc *ipc) /* CHK */ {
5617: /* mask f1f8, bits 41b0, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5618: int srcreg = (ipc->opcode >> 0) & 7;
5619: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
5620: uint16 srcdata = fetchword(srcaddr);
5621: int dstreg = (ipc->opcode >> 9) & 7;
5622: uint16 dstdata = DATAREG(dstreg);
5623:
5624: if ((sint16)srcdata < 0) {
5625: reg68k_vector(V_CHK, PC+4);
5626: } else if (dstdata > srcdata) {
5627: reg68k_vector(V_CHK, PC+4);
5628: }
5629: PC+= 4;
5630: }
5631:
5632: void cpu_op_770b(t_ipc *ipc) /* CHK */ {
5633: /* mask f1f8, bits 41b0, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5634: int srcreg = (ipc->opcode >> 0) & 7;
5635: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
5636: uint16 srcdata = fetchword(srcaddr);
5637: int dstreg = (ipc->opcode >> 9) & 7;
5638: uint16 dstdata = DATAREG(dstreg);
5639:
5640: if ((sint16)srcdata < 0) {
5641: NFLAG = 1;
5642: reg68k_vector(V_CHK, PC+4);
5643: } else if (dstdata > srcdata) {
5644: NFLAG = 0;
5645: reg68k_vector(V_CHK, PC+4);
5646: }
5647: PC+= 4;
5648: }
5649:
5650: void cpu_op_771a(t_ipc *ipc) /* CHK */ {
5651: /* mask f1ff, bits 41b8, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5652: uint32 srcaddr = ipc->src;
5653: uint16 srcdata = fetchword(srcaddr);
5654: int dstreg = (ipc->opcode >> 9) & 7;
5655: uint16 dstdata = DATAREG(dstreg);
5656:
5657: if ((sint16)srcdata < 0) {
5658: reg68k_vector(V_CHK, PC+4);
5659: } else if (dstdata > srcdata) {
5660: reg68k_vector(V_CHK, PC+4);
5661: }
5662: PC+= 4;
5663: }
5664:
5665: void cpu_op_771b(t_ipc *ipc) /* CHK */ {
5666: /* mask f1ff, bits 41b8, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5667: uint32 srcaddr = ipc->src;
5668: uint16 srcdata = fetchword(srcaddr);
5669: int dstreg = (ipc->opcode >> 9) & 7;
5670: uint16 dstdata = DATAREG(dstreg);
5671:
5672: if ((sint16)srcdata < 0) {
5673: NFLAG = 1;
5674: reg68k_vector(V_CHK, PC+4);
5675: } else if (dstdata > srcdata) {
5676: NFLAG = 0;
5677: reg68k_vector(V_CHK, PC+4);
5678: }
5679: PC+= 4;
5680: }
5681:
5682: void cpu_op_772a(t_ipc *ipc) /* CHK */ {
5683: /* mask f1ff, bits 41b9, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5684: uint32 srcaddr = ipc->src;
5685: uint16 srcdata = fetchword(srcaddr);
5686: int dstreg = (ipc->opcode >> 9) & 7;
5687: uint16 dstdata = DATAREG(dstreg);
5688:
5689: if ((sint16)srcdata < 0) {
5690: reg68k_vector(V_CHK, PC+6);
5691: } else if (dstdata > srcdata) {
5692: reg68k_vector(V_CHK, PC+6);
5693: }
5694: PC+= 6;
5695: }
5696:
5697: void cpu_op_772b(t_ipc *ipc) /* CHK */ {
5698: /* mask f1ff, bits 41b9, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5699: uint32 srcaddr = ipc->src;
5700: uint16 srcdata = fetchword(srcaddr);
5701: int dstreg = (ipc->opcode >> 9) & 7;
5702: uint16 dstdata = DATAREG(dstreg);
5703:
5704: if ((sint16)srcdata < 0) {
5705: NFLAG = 1;
5706: reg68k_vector(V_CHK, PC+6);
5707: } else if (dstdata > srcdata) {
5708: NFLAG = 0;
5709: reg68k_vector(V_CHK, PC+6);
5710: }
5711: PC+= 6;
5712: }
5713:
5714: void cpu_op_773a(t_ipc *ipc) /* CHK */ {
5715: /* mask f1ff, bits 41ba, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5716: uint32 srcaddr = ipc->src;
5717: uint16 srcdata = fetchword(srcaddr);
5718: int dstreg = (ipc->opcode >> 9) & 7;
5719: uint16 dstdata = DATAREG(dstreg);
5720:
5721: if ((sint16)srcdata < 0) {
5722: reg68k_vector(V_CHK, PC+4);
5723: } else if (dstdata > srcdata) {
5724: reg68k_vector(V_CHK, PC+4);
5725: }
5726: PC+= 4;
5727: }
5728:
5729: void cpu_op_773b(t_ipc *ipc) /* CHK */ {
5730: /* mask f1ff, bits 41ba, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5731: uint32 srcaddr = ipc->src;
5732: uint16 srcdata = fetchword(srcaddr);
5733: int dstreg = (ipc->opcode >> 9) & 7;
5734: uint16 dstdata = DATAREG(dstreg);
5735:
5736: if ((sint16)srcdata < 0) {
5737: NFLAG = 1;
5738: reg68k_vector(V_CHK, PC+4);
5739: } else if (dstdata > srcdata) {
5740: NFLAG = 0;
5741: reg68k_vector(V_CHK, PC+4);
5742: }
5743: PC+= 4;
5744: }
5745:
5746: void cpu_op_774a(t_ipc *ipc) /* CHK */ {
5747: /* mask f1ff, bits 41bb, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5748: uint32 srcaddr = idxval_src(ipc);
5749: uint16 srcdata = fetchword(srcaddr);
5750: int dstreg = (ipc->opcode >> 9) & 7;
5751: uint16 dstdata = DATAREG(dstreg);
5752:
5753: if ((sint16)srcdata < 0) {
5754: reg68k_vector(V_CHK, PC+4);
5755: } else if (dstdata > srcdata) {
5756: reg68k_vector(V_CHK, PC+4);
5757: }
5758: PC+= 4;
5759: }
5760:
5761: void cpu_op_774b(t_ipc *ipc) /* CHK */ {
5762: /* mask f1ff, bits 41bb, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5763: uint32 srcaddr = idxval_src(ipc);
5764: uint16 srcdata = fetchword(srcaddr);
5765: int dstreg = (ipc->opcode >> 9) & 7;
5766: uint16 dstdata = DATAREG(dstreg);
5767:
5768: if ((sint16)srcdata < 0) {
5769: NFLAG = 1;
5770: reg68k_vector(V_CHK, PC+4);
5771: } else if (dstdata > srcdata) {
5772: NFLAG = 0;
5773: reg68k_vector(V_CHK, PC+4);
5774: }
5775: PC+= 4;
5776: }
5777:
5778: void cpu_op_775a(t_ipc *ipc) /* CHK */ {
5779: /* mask f1ff, bits 41bc, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5780: uint16 srcdata = ipc->src;
5781: int dstreg = (ipc->opcode >> 9) & 7;
5782: uint16 dstdata = DATAREG(dstreg);
5783:
5784: if ((sint16)srcdata < 0) {
5785: reg68k_vector(V_CHK, PC+4);
5786: } else if (dstdata > srcdata) {
5787: reg68k_vector(V_CHK, PC+4);
5788: }
5789: PC+= 4;
5790: }
5791:
5792: void cpu_op_775b(t_ipc *ipc) /* CHK */ {
5793: /* mask f1ff, bits 41bc, mnemonic 45, priv 0, endblk 0, imm_notzero 0, used 0 set 2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */
5794: uint16 srcdata = ipc->src;
5795: int dstreg = (ipc->opcode >> 9) & 7;
5796: uint16 dstdata = DATAREG(dstreg);
5797:
5798: if ((sint16)srcdata < 0) {
5799: NFLAG = 1;
5800: reg68k_vector(V_CHK, PC+4);
5801: } else if (dstdata > srcdata) {
5802: NFLAG = 0;
5803: reg68k_vector(V_CHK, PC+4);
5804: }
5805: PC+= 4;
5806: }
5807:
5808: void cpu_op_776a(t_ipc *ipc) /* LEA */ {
5809: /* mask f1f8, bits 41d0, mnemonic 40, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 2, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */
5810: int srcreg = (ipc->opcode >> 0) & 7;
5811: uint32 srcaddr = ADDRREG(srcreg);
5812: int dstreg = (ipc->opcode >> 9) & 7;
5813: uint32 outdata = srcaddr;
5814:
5815: ADDRREG(dstreg) = outdata;
5816: PC+= 2;
5817: }
5818:
5819: void cpu_op_777a(t_ipc *ipc) /* LEA */ {
5820: /* mask f1f8, bits 41e8, mnemonic 40, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 5, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */
5821: int srcreg = (ipc->opcode >> 0) & 7;
5822: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
5823: int dstreg = (ipc->opcode >> 9) & 7;
5824: uint32 outdata = srcaddr;
5825:
5826: ADDRREG(dstreg) = outdata;
5827: PC+= 4;
5828: }
5829:
5830: void cpu_op_778a(t_ipc *ipc) /* LEA */ {
5831: /* mask f1f8, bits 41f0, mnemonic 40, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 6, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */
5832: int srcreg = (ipc->opcode >> 0) & 7;
5833: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
5834: int dstreg = (ipc->opcode >> 9) & 7;
5835: uint32 outdata = srcaddr;
5836:
5837: ADDRREG(dstreg) = outdata;
5838: PC+= 4;
5839: }
5840:
5841: void cpu_op_779a(t_ipc *ipc) /* LEA */ {
5842: /* mask f1ff, bits 41f8, mnemonic 40, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 7, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */
5843: uint32 srcaddr = ipc->src;
5844: int dstreg = (ipc->opcode >> 9) & 7;
5845: uint32 outdata = srcaddr;
5846:
5847: ADDRREG(dstreg) = outdata;
5848: PC+= 4;
5849: }
5850:
5851: void cpu_op_780a(t_ipc *ipc) /* LEA */ {
5852: /* mask f1ff, bits 41f9, mnemonic 40, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 8, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */
5853: uint32 srcaddr = ipc->src;
5854: int dstreg = (ipc->opcode >> 9) & 7;
5855: uint32 outdata = srcaddr;
5856:
5857: ADDRREG(dstreg) = outdata;
5858: PC+= 6;
5859: }
5860:
5861: void cpu_op_781a(t_ipc *ipc) /* LEA */ {
5862: /* mask f1ff, bits 41fa, mnemonic 40, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 9, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */
5863: uint32 srcaddr = ipc->src;
5864: int dstreg = (ipc->opcode >> 9) & 7;
5865: uint32 outdata = srcaddr;
5866:
5867: ADDRREG(dstreg) = outdata;
5868: PC+= 4;
5869: }
5870:
5871: void cpu_op_782a(t_ipc *ipc) /* LEA */ {
5872: /* mask f1ff, bits 41fb, mnemonic 40, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 10, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */
5873: uint32 srcaddr = idxval_src(ipc);
5874: int dstreg = (ipc->opcode >> 9) & 7;
5875: uint32 outdata = srcaddr;
5876:
5877: ADDRREG(dstreg) = outdata;
5878: PC+= 4;
5879: }
5880:
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.