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1.1 root 1: /*****************************************************************************/
2: /* Generator - Sega Genesis emulation - (c) James Ponder 1997-1998 */
3: /*****************************************************************************/
4: /* */
5: /* cpu68k-5.c */
6: /* */
7: /*****************************************************************************/
8:
9: #include "generator.h"
10: #include "cpu68k.h"
11: #include "mem68k.h"
12: #include "reg68k.h"
13:
14: #include "cpu68k-inline.h"
15:
16: #include <stdio.h>
17:
18: void cpu_op_783a(t_ipc *ipc) /* ADD */ {
19: /* mask f1f8, bits 5000, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
20: unsigned int srcdata = ipc->src;
21: int dstreg = (ipc->opcode >> 0) & 7;
22: uint8 dstdata = DATAREG(dstreg);
23: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
24:
25: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
26: PC+= 2;
27: }
28:
29: void cpu_op_783b(t_ipc *ipc) /* ADD */ {
30: /* mask f1f8, bits 5000, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
31: unsigned int srcdata = ipc->src;
32: int dstreg = (ipc->opcode >> 0) & 7;
33: uint8 dstdata = DATAREG(dstreg);
34: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
35:
36: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
37:
38: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
39: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
40: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
41: NFLAG = ((sint8)outdata) < 0;
42: ZFLAG = !outdata;
43: PC+= 2;
44: }
45:
46: void cpu_op_784a(t_ipc *ipc) /* ADD */ {
47: /* mask f1f8, bits 5010, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
48: unsigned int srcdata = ipc->src;
49: int dstreg = (ipc->opcode >> 0) & 7;
50: uint32 dstaddr = ADDRREG(dstreg);
51: uint8 dstdata = fetchbyte(dstaddr);
52: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
53:
54: storebyte(dstaddr, outdata);
55: PC+= 2;
56: }
57:
58: void cpu_op_784b(t_ipc *ipc) /* ADD */ {
59: /* mask f1f8, bits 5010, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
60: unsigned int srcdata = ipc->src;
61: int dstreg = (ipc->opcode >> 0) & 7;
62: uint32 dstaddr = ADDRREG(dstreg);
63: uint8 dstdata = fetchbyte(dstaddr);
64: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
65:
66: storebyte(dstaddr, outdata);
67:
68: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
69: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
70: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
71: NFLAG = ((sint8)outdata) < 0;
72: ZFLAG = !outdata;
73: PC+= 2;
74: }
75:
76: void cpu_op_785a(t_ipc *ipc) /* ADD */ {
77: /* mask f1f8, bits 5018, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
78: unsigned int srcdata = ipc->src;
79: int dstreg = (ipc->opcode >> 0) & 7;
80: uint32 dstaddr = ADDRREG(dstreg);
81: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
82: uint8 dstdata = fetchbyte(dstaddr);
83: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
84:
85: storebyte(dstaddr, outdata);
86: PC+= 2;
87: }
88:
89: void cpu_op_785b(t_ipc *ipc) /* ADD */ {
90: /* mask f1f8, bits 5018, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
91: unsigned int srcdata = ipc->src;
92: int dstreg = (ipc->opcode >> 0) & 7;
93: uint32 dstaddr = ADDRREG(dstreg);
94: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
95: uint8 dstdata = fetchbyte(dstaddr);
96: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
97:
98: storebyte(dstaddr, outdata);
99:
100: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
101: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
102: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
103: NFLAG = ((sint8)outdata) < 0;
104: ZFLAG = !outdata;
105: PC+= 2;
106: }
107:
108: void cpu_op_786a(t_ipc *ipc) /* ADD */ {
109: /* mask f1f8, bits 5020, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
110: unsigned int srcdata = ipc->src;
111: int dstreg = (ipc->opcode >> 0) & 7;
112: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
113: uint8 dstdata = fetchbyte(dstaddr);
114: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
115:
116: storebyte(dstaddr, outdata);
117: PC+= 2;
118: }
119:
120: void cpu_op_786b(t_ipc *ipc) /* ADD */ {
121: /* mask f1f8, bits 5020, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
122: unsigned int srcdata = ipc->src;
123: int dstreg = (ipc->opcode >> 0) & 7;
124: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
125: uint8 dstdata = fetchbyte(dstaddr);
126: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
127:
128: storebyte(dstaddr, outdata);
129:
130: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
131: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
132: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
133: NFLAG = ((sint8)outdata) < 0;
134: ZFLAG = !outdata;
135: PC+= 2;
136: }
137:
138: void cpu_op_787a(t_ipc *ipc) /* ADD */ {
139: /* mask f1f8, bits 5028, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
140: unsigned int srcdata = ipc->src;
141: int dstreg = (ipc->opcode >> 0) & 7;
142: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
143: uint8 dstdata = fetchbyte(dstaddr);
144: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
145:
146: storebyte(dstaddr, outdata);
147: PC+= 4;
148: }
149:
150: void cpu_op_787b(t_ipc *ipc) /* ADD */ {
151: /* mask f1f8, bits 5028, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
152: unsigned int srcdata = ipc->src;
153: int dstreg = (ipc->opcode >> 0) & 7;
154: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
155: uint8 dstdata = fetchbyte(dstaddr);
156: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
157:
158: storebyte(dstaddr, outdata);
159:
160: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
161: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
162: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
163: NFLAG = ((sint8)outdata) < 0;
164: ZFLAG = !outdata;
165: PC+= 4;
166: }
167:
168: void cpu_op_788a(t_ipc *ipc) /* ADD */ {
169: /* mask f1f8, bits 5030, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
170: unsigned int srcdata = ipc->src;
171: int dstreg = (ipc->opcode >> 0) & 7;
172: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
173: uint8 dstdata = fetchbyte(dstaddr);
174: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
175:
176: storebyte(dstaddr, outdata);
177: PC+= 4;
178: }
179:
180: void cpu_op_788b(t_ipc *ipc) /* ADD */ {
181: /* mask f1f8, bits 5030, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
182: unsigned int srcdata = ipc->src;
183: int dstreg = (ipc->opcode >> 0) & 7;
184: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
185: uint8 dstdata = fetchbyte(dstaddr);
186: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
187:
188: storebyte(dstaddr, outdata);
189:
190: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
191: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
192: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
193: NFLAG = ((sint8)outdata) < 0;
194: ZFLAG = !outdata;
195: PC+= 4;
196: }
197:
198: void cpu_op_789a(t_ipc *ipc) /* ADD */ {
199: /* mask f1ff, bits 5038, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
200: unsigned int srcdata = ipc->src;
201: uint32 dstaddr = ipc->dst;
202: uint8 dstdata = fetchbyte(dstaddr);
203: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
204:
205: storebyte(dstaddr, outdata);
206: PC+= 4;
207: }
208:
209: void cpu_op_789b(t_ipc *ipc) /* ADD */ {
210: /* mask f1ff, bits 5038, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
211: unsigned int srcdata = ipc->src;
212: uint32 dstaddr = ipc->dst;
213: uint8 dstdata = fetchbyte(dstaddr);
214: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
215:
216: storebyte(dstaddr, outdata);
217:
218: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
219: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
220: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
221: NFLAG = ((sint8)outdata) < 0;
222: ZFLAG = !outdata;
223: PC+= 4;
224: }
225:
226: void cpu_op_790a(t_ipc *ipc) /* ADD */ {
227: /* mask f1ff, bits 5039, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
228: unsigned int srcdata = ipc->src;
229: uint32 dstaddr = ipc->dst;
230: uint8 dstdata = fetchbyte(dstaddr);
231: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
232:
233: storebyte(dstaddr, outdata);
234: PC+= 6;
235: }
236:
237: void cpu_op_790b(t_ipc *ipc) /* ADD */ {
238: /* mask f1ff, bits 5039, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
239: unsigned int srcdata = ipc->src;
240: uint32 dstaddr = ipc->dst;
241: uint8 dstdata = fetchbyte(dstaddr);
242: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
243:
244: storebyte(dstaddr, outdata);
245:
246: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
247: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
248: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
249: NFLAG = ((sint8)outdata) < 0;
250: ZFLAG = !outdata;
251: PC+= 6;
252: }
253:
254: void cpu_op_791a(t_ipc *ipc) /* ADD */ {
255: /* mask f1f8, bits 5040, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
256: unsigned int srcdata = ipc->src;
257: int dstreg = (ipc->opcode >> 0) & 7;
258: uint16 dstdata = DATAREG(dstreg);
259: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
260:
261: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
262: PC+= 2;
263: }
264:
265: void cpu_op_791b(t_ipc *ipc) /* ADD */ {
266: /* mask f1f8, bits 5040, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
267: unsigned int srcdata = ipc->src;
268: int dstreg = (ipc->opcode >> 0) & 7;
269: uint16 dstdata = DATAREG(dstreg);
270: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
271:
272: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
273:
274: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
275: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
276: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
277: NFLAG = ((sint16)outdata) < 0;
278: ZFLAG = !outdata;
279: PC+= 2;
280: }
281:
282: void cpu_op_792a(t_ipc *ipc) /* ADD */ {
283: /* mask f1f8, bits 5050, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
284: unsigned int srcdata = ipc->src;
285: int dstreg = (ipc->opcode >> 0) & 7;
286: uint32 dstaddr = ADDRREG(dstreg);
287: uint16 dstdata = fetchword(dstaddr);
288: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
289:
290: storeword(dstaddr, outdata);
291: PC+= 2;
292: }
293:
294: void cpu_op_792b(t_ipc *ipc) /* ADD */ {
295: /* mask f1f8, bits 5050, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
296: unsigned int srcdata = ipc->src;
297: int dstreg = (ipc->opcode >> 0) & 7;
298: uint32 dstaddr = ADDRREG(dstreg);
299: uint16 dstdata = fetchword(dstaddr);
300: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
301:
302: storeword(dstaddr, outdata);
303:
304: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
305: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
306: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
307: NFLAG = ((sint16)outdata) < 0;
308: ZFLAG = !outdata;
309: PC+= 2;
310: }
311:
312: void cpu_op_793a(t_ipc *ipc) /* ADD */ {
313: /* mask f1f8, bits 5058, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
314: unsigned int srcdata = ipc->src;
315: int dstreg = (ipc->opcode >> 0) & 7;
316: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
317: uint16 dstdata = fetchword(dstaddr);
318: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
319:
320: storeword(dstaddr, outdata);
321: PC+= 2;
322: }
323:
324: void cpu_op_793b(t_ipc *ipc) /* ADD */ {
325: /* mask f1f8, bits 5058, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
326: unsigned int srcdata = ipc->src;
327: int dstreg = (ipc->opcode >> 0) & 7;
328: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
329: uint16 dstdata = fetchword(dstaddr);
330: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
331:
332: storeword(dstaddr, outdata);
333:
334: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
335: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
336: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
337: NFLAG = ((sint16)outdata) < 0;
338: ZFLAG = !outdata;
339: PC+= 2;
340: }
341:
342: void cpu_op_794a(t_ipc *ipc) /* ADD */ {
343: /* mask f1f8, bits 5060, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
344: unsigned int srcdata = ipc->src;
345: int dstreg = (ipc->opcode >> 0) & 7;
346: uint32 dstaddr = ADDRREG(dstreg)-=2;
347: uint16 dstdata = fetchword(dstaddr);
348: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
349:
350: storeword(dstaddr, outdata);
351: PC+= 2;
352: }
353:
354: void cpu_op_794b(t_ipc *ipc) /* ADD */ {
355: /* mask f1f8, bits 5060, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
356: unsigned int srcdata = ipc->src;
357: int dstreg = (ipc->opcode >> 0) & 7;
358: uint32 dstaddr = ADDRREG(dstreg)-=2;
359: uint16 dstdata = fetchword(dstaddr);
360: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
361:
362: storeword(dstaddr, outdata);
363:
364: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
365: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
366: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
367: NFLAG = ((sint16)outdata) < 0;
368: ZFLAG = !outdata;
369: PC+= 2;
370: }
371:
372: void cpu_op_795a(t_ipc *ipc) /* ADD */ {
373: /* mask f1f8, bits 5068, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
374: unsigned int srcdata = ipc->src;
375: int dstreg = (ipc->opcode >> 0) & 7;
376: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
377: uint16 dstdata = fetchword(dstaddr);
378: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
379:
380: storeword(dstaddr, outdata);
381: PC+= 4;
382: }
383:
384: void cpu_op_795b(t_ipc *ipc) /* ADD */ {
385: /* mask f1f8, bits 5068, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
386: unsigned int srcdata = ipc->src;
387: int dstreg = (ipc->opcode >> 0) & 7;
388: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
389: uint16 dstdata = fetchword(dstaddr);
390: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
391:
392: storeword(dstaddr, outdata);
393:
394: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
395: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
396: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
397: NFLAG = ((sint16)outdata) < 0;
398: ZFLAG = !outdata;
399: PC+= 4;
400: }
401:
402: void cpu_op_796a(t_ipc *ipc) /* ADD */ {
403: /* mask f1f8, bits 5070, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
404: unsigned int srcdata = ipc->src;
405: int dstreg = (ipc->opcode >> 0) & 7;
406: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
407: uint16 dstdata = fetchword(dstaddr);
408: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
409:
410: storeword(dstaddr, outdata);
411: PC+= 4;
412: }
413:
414: void cpu_op_796b(t_ipc *ipc) /* ADD */ {
415: /* mask f1f8, bits 5070, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
416: unsigned int srcdata = ipc->src;
417: int dstreg = (ipc->opcode >> 0) & 7;
418: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
419: uint16 dstdata = fetchword(dstaddr);
420: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
421:
422: storeword(dstaddr, outdata);
423:
424: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
425: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
426: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
427: NFLAG = ((sint16)outdata) < 0;
428: ZFLAG = !outdata;
429: PC+= 4;
430: }
431:
432: void cpu_op_797a(t_ipc *ipc) /* ADD */ {
433: /* mask f1ff, bits 5078, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
434: unsigned int srcdata = ipc->src;
435: uint32 dstaddr = ipc->dst;
436: uint16 dstdata = fetchword(dstaddr);
437: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
438:
439: storeword(dstaddr, outdata);
440: PC+= 4;
441: }
442:
443: void cpu_op_797b(t_ipc *ipc) /* ADD */ {
444: /* mask f1ff, bits 5078, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
445: unsigned int srcdata = ipc->src;
446: uint32 dstaddr = ipc->dst;
447: uint16 dstdata = fetchword(dstaddr);
448: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
449:
450: storeword(dstaddr, outdata);
451:
452: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
453: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
454: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
455: NFLAG = ((sint16)outdata) < 0;
456: ZFLAG = !outdata;
457: PC+= 4;
458: }
459:
460: void cpu_op_798a(t_ipc *ipc) /* ADD */ {
461: /* mask f1ff, bits 5079, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
462: unsigned int srcdata = ipc->src;
463: uint32 dstaddr = ipc->dst;
464: uint16 dstdata = fetchword(dstaddr);
465: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
466:
467: storeword(dstaddr, outdata);
468: PC+= 6;
469: }
470:
471: void cpu_op_798b(t_ipc *ipc) /* ADD */ {
472: /* mask f1ff, bits 5079, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
473: unsigned int srcdata = ipc->src;
474: uint32 dstaddr = ipc->dst;
475: uint16 dstdata = fetchword(dstaddr);
476: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
477:
478: storeword(dstaddr, outdata);
479:
480: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
481: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
482: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
483: NFLAG = ((sint16)outdata) < 0;
484: ZFLAG = !outdata;
485: PC+= 6;
486: }
487:
488: void cpu_op_799a(t_ipc *ipc) /* ADD */ {
489: /* mask f1f8, bits 5080, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
490: unsigned int srcdata = ipc->src;
491: int dstreg = (ipc->opcode >> 0) & 7;
492: uint32 dstdata = DATAREG(dstreg);
493: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
494:
495: DATAREG(dstreg) = outdata;
496: PC+= 2;
497: }
498:
499: void cpu_op_799b(t_ipc *ipc) /* ADD */ {
500: /* mask f1f8, bits 5080, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
501: unsigned int srcdata = ipc->src;
502: int dstreg = (ipc->opcode >> 0) & 7;
503: uint32 dstdata = DATAREG(dstreg);
504: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
505:
506: DATAREG(dstreg) = outdata;
507:
508: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
509: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
510: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
511: NFLAG = ((sint32)outdata) < 0;
512: ZFLAG = !outdata;
513: PC+= 2;
514: }
515:
516: void cpu_op_800a(t_ipc *ipc) /* ADD */ {
517: /* mask f1f8, bits 5090, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
518: unsigned int srcdata = ipc->src;
519: int dstreg = (ipc->opcode >> 0) & 7;
520: uint32 dstaddr = ADDRREG(dstreg);
521: uint32 dstdata = fetchlong(dstaddr);
522: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
523:
524: storelong(dstaddr, outdata);
525: PC+= 2;
526: }
527:
528: void cpu_op_800b(t_ipc *ipc) /* ADD */ {
529: /* mask f1f8, bits 5090, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
530: unsigned int srcdata = ipc->src;
531: int dstreg = (ipc->opcode >> 0) & 7;
532: uint32 dstaddr = ADDRREG(dstreg);
533: uint32 dstdata = fetchlong(dstaddr);
534: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
535:
536: storelong(dstaddr, outdata);
537:
538: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
539: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
540: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
541: NFLAG = ((sint32)outdata) < 0;
542: ZFLAG = !outdata;
543: PC+= 2;
544: }
545:
546: void cpu_op_801a(t_ipc *ipc) /* ADD */ {
547: /* mask f1f8, bits 5098, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
548: unsigned int srcdata = ipc->src;
549: int dstreg = (ipc->opcode >> 0) & 7;
550: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
551: uint32 dstdata = fetchlong(dstaddr);
552: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
553:
554: storelong(dstaddr, outdata);
555: PC+= 2;
556: }
557:
558: void cpu_op_801b(t_ipc *ipc) /* ADD */ {
559: /* mask f1f8, bits 5098, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
560: unsigned int srcdata = ipc->src;
561: int dstreg = (ipc->opcode >> 0) & 7;
562: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
563: uint32 dstdata = fetchlong(dstaddr);
564: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
565:
566: storelong(dstaddr, outdata);
567:
568: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
569: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
570: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
571: NFLAG = ((sint32)outdata) < 0;
572: ZFLAG = !outdata;
573: PC+= 2;
574: }
575:
576: void cpu_op_802a(t_ipc *ipc) /* ADD */ {
577: /* mask f1f8, bits 50a0, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
578: unsigned int srcdata = ipc->src;
579: int dstreg = (ipc->opcode >> 0) & 7;
580: uint32 dstaddr = ADDRREG(dstreg)-=4;
581: uint32 dstdata = fetchlong(dstaddr);
582: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
583:
584: storelong(dstaddr, outdata);
585: PC+= 2;
586: }
587:
588: void cpu_op_802b(t_ipc *ipc) /* ADD */ {
589: /* mask f1f8, bits 50a0, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
590: unsigned int srcdata = ipc->src;
591: int dstreg = (ipc->opcode >> 0) & 7;
592: uint32 dstaddr = ADDRREG(dstreg)-=4;
593: uint32 dstdata = fetchlong(dstaddr);
594: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
595:
596: storelong(dstaddr, outdata);
597:
598: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
599: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
600: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
601: NFLAG = ((sint32)outdata) < 0;
602: ZFLAG = !outdata;
603: PC+= 2;
604: }
605:
606: void cpu_op_803a(t_ipc *ipc) /* ADD */ {
607: /* mask f1f8, bits 50a8, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
608: unsigned int srcdata = ipc->src;
609: int dstreg = (ipc->opcode >> 0) & 7;
610: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
611: uint32 dstdata = fetchlong(dstaddr);
612: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
613:
614: storelong(dstaddr, outdata);
615: PC+= 4;
616: }
617:
618: void cpu_op_803b(t_ipc *ipc) /* ADD */ {
619: /* mask f1f8, bits 50a8, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
620: unsigned int srcdata = ipc->src;
621: int dstreg = (ipc->opcode >> 0) & 7;
622: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
623: uint32 dstdata = fetchlong(dstaddr);
624: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
625:
626: storelong(dstaddr, outdata);
627:
628: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
629: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
630: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
631: NFLAG = ((sint32)outdata) < 0;
632: ZFLAG = !outdata;
633: PC+= 4;
634: }
635:
636: void cpu_op_804a(t_ipc *ipc) /* ADD */ {
637: /* mask f1f8, bits 50b0, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
638: unsigned int srcdata = ipc->src;
639: int dstreg = (ipc->opcode >> 0) & 7;
640: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
641: uint32 dstdata = fetchlong(dstaddr);
642: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
643:
644: storelong(dstaddr, outdata);
645: PC+= 4;
646: }
647:
648: void cpu_op_804b(t_ipc *ipc) /* ADD */ {
649: /* mask f1f8, bits 50b0, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
650: unsigned int srcdata = ipc->src;
651: int dstreg = (ipc->opcode >> 0) & 7;
652: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
653: uint32 dstdata = fetchlong(dstaddr);
654: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
655:
656: storelong(dstaddr, outdata);
657:
658: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
659: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
660: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
661: NFLAG = ((sint32)outdata) < 0;
662: ZFLAG = !outdata;
663: PC+= 4;
664: }
665:
666: void cpu_op_805a(t_ipc *ipc) /* ADD */ {
667: /* mask f1ff, bits 50b8, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
668: unsigned int srcdata = ipc->src;
669: uint32 dstaddr = ipc->dst;
670: uint32 dstdata = fetchlong(dstaddr);
671: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
672:
673: storelong(dstaddr, outdata);
674: PC+= 4;
675: }
676:
677: void cpu_op_805b(t_ipc *ipc) /* ADD */ {
678: /* mask f1ff, bits 50b8, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
679: unsigned int srcdata = ipc->src;
680: uint32 dstaddr = ipc->dst;
681: uint32 dstdata = fetchlong(dstaddr);
682: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
683:
684: storelong(dstaddr, outdata);
685:
686: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
687: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
688: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
689: NFLAG = ((sint32)outdata) < 0;
690: ZFLAG = !outdata;
691: PC+= 4;
692: }
693:
694: void cpu_op_806a(t_ipc *ipc) /* ADD */ {
695: /* mask f1ff, bits 50b9, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
696: unsigned int srcdata = ipc->src;
697: uint32 dstaddr = ipc->dst;
698: uint32 dstdata = fetchlong(dstaddr);
699: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
700:
701: storelong(dstaddr, outdata);
702: PC+= 6;
703: }
704:
705: void cpu_op_806b(t_ipc *ipc) /* ADD */ {
706: /* mask f1ff, bits 50b9, mnemonic 10, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
707: unsigned int srcdata = ipc->src;
708: uint32 dstaddr = ipc->dst;
709: uint32 dstdata = fetchlong(dstaddr);
710: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
711:
712: storelong(dstaddr, outdata);
713:
714: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
715: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
716: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
717: NFLAG = ((sint32)outdata) < 0;
718: ZFLAG = !outdata;
719: PC+= 6;
720: }
721:
722: void cpu_op_807a(t_ipc *ipc) /* ADDA */ {
723: /* mask f1f8, bits 5048, mnemonic 11, priv 0, endblk 0, imm_notzero -1, used 0 set 0, size 2, stype 15, dtype 1, sbitpos 9, dbitpos 0, immvalue 0 */
724: unsigned int srcdata = ipc->src;
725: int dstreg = (ipc->opcode >> 0) & 7;
726: uint32 dstdata = ADDRREG(dstreg);
727: uint32 outdata = (sint32)dstdata + (sint16)srcdata;
728:
729: ADDRREG(dstreg) = outdata;
730: PC+= 2;
731: }
732:
733: void cpu_op_808a(t_ipc *ipc) /* ADDA */ {
734: /* mask f1f8, bits 5088, mnemonic 11, priv 0, endblk 0, imm_notzero -1, used 0 set 0, size 3, stype 15, dtype 1, sbitpos 9, dbitpos 0, immvalue 0 */
735: unsigned int srcdata = ipc->src;
736: int dstreg = (ipc->opcode >> 0) & 7;
737: uint32 dstdata = ADDRREG(dstreg);
738: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
739:
740: ADDRREG(dstreg) = outdata;
741: PC+= 2;
742: }
743:
744: void cpu_op_809a(t_ipc *ipc) /* SUB */ {
745: /* mask f1f8, bits 5100, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
746: unsigned int srcdata = ipc->src;
747: int dstreg = (ipc->opcode >> 0) & 7;
748: uint8 dstdata = DATAREG(dstreg);
749: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
750:
751: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
752: PC+= 2;
753: }
754:
755: void cpu_op_809b(t_ipc *ipc) /* SUB */ {
756: /* mask f1f8, bits 5100, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
757: unsigned int srcdata = ipc->src;
758: int dstreg = (ipc->opcode >> 0) & 7;
759: uint8 dstdata = DATAREG(dstreg);
760: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
761:
762: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
763:
764: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
765: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
766: XFLAG = CFLAG = srcdata > dstdata;
767: NFLAG = ((sint8)outdata) < 0;
768: ZFLAG = !outdata;
769: PC+= 2;
770: }
771:
772: void cpu_op_810a(t_ipc *ipc) /* SUB */ {
773: /* mask f1f8, bits 5110, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
774: unsigned int srcdata = ipc->src;
775: int dstreg = (ipc->opcode >> 0) & 7;
776: uint32 dstaddr = ADDRREG(dstreg);
777: uint8 dstdata = fetchbyte(dstaddr);
778: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
779:
780: storebyte(dstaddr, outdata);
781: PC+= 2;
782: }
783:
784: void cpu_op_810b(t_ipc *ipc) /* SUB */ {
785: /* mask f1f8, bits 5110, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
786: unsigned int srcdata = ipc->src;
787: int dstreg = (ipc->opcode >> 0) & 7;
788: uint32 dstaddr = ADDRREG(dstreg);
789: uint8 dstdata = fetchbyte(dstaddr);
790: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
791:
792: storebyte(dstaddr, outdata);
793:
794: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
795: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
796: XFLAG = CFLAG = srcdata > dstdata;
797: NFLAG = ((sint8)outdata) < 0;
798: ZFLAG = !outdata;
799: PC+= 2;
800: }
801:
802: void cpu_op_811a(t_ipc *ipc) /* SUB */ {
803: /* mask f1f8, bits 5118, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
804: unsigned int srcdata = ipc->src;
805: int dstreg = (ipc->opcode >> 0) & 7;
806: uint32 dstaddr = ADDRREG(dstreg);
807: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
808: uint8 dstdata = fetchbyte(dstaddr);
809: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
810:
811: storebyte(dstaddr, outdata);
812: PC+= 2;
813: }
814:
815: void cpu_op_811b(t_ipc *ipc) /* SUB */ {
816: /* mask f1f8, bits 5118, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
817: unsigned int srcdata = ipc->src;
818: int dstreg = (ipc->opcode >> 0) & 7;
819: uint32 dstaddr = ADDRREG(dstreg);
820: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
821: uint8 dstdata = fetchbyte(dstaddr);
822: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
823:
824: storebyte(dstaddr, outdata);
825:
826: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
827: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
828: XFLAG = CFLAG = srcdata > dstdata;
829: NFLAG = ((sint8)outdata) < 0;
830: ZFLAG = !outdata;
831: PC+= 2;
832: }
833:
834: void cpu_op_812a(t_ipc *ipc) /* SUB */ {
835: /* mask f1f8, bits 5120, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
836: unsigned int srcdata = ipc->src;
837: int dstreg = (ipc->opcode >> 0) & 7;
838: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
839: uint8 dstdata = fetchbyte(dstaddr);
840: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
841:
842: storebyte(dstaddr, outdata);
843: PC+= 2;
844: }
845:
846: void cpu_op_812b(t_ipc *ipc) /* SUB */ {
847: /* mask f1f8, bits 5120, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
848: unsigned int srcdata = ipc->src;
849: int dstreg = (ipc->opcode >> 0) & 7;
850: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
851: uint8 dstdata = fetchbyte(dstaddr);
852: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
853:
854: storebyte(dstaddr, outdata);
855:
856: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
857: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
858: XFLAG = CFLAG = srcdata > dstdata;
859: NFLAG = ((sint8)outdata) < 0;
860: ZFLAG = !outdata;
861: PC+= 2;
862: }
863:
864: void cpu_op_813a(t_ipc *ipc) /* SUB */ {
865: /* mask f1f8, bits 5128, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
866: unsigned int srcdata = ipc->src;
867: int dstreg = (ipc->opcode >> 0) & 7;
868: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
869: uint8 dstdata = fetchbyte(dstaddr);
870: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
871:
872: storebyte(dstaddr, outdata);
873: PC+= 4;
874: }
875:
876: void cpu_op_813b(t_ipc *ipc) /* SUB */ {
877: /* mask f1f8, bits 5128, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
878: unsigned int srcdata = ipc->src;
879: int dstreg = (ipc->opcode >> 0) & 7;
880: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
881: uint8 dstdata = fetchbyte(dstaddr);
882: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
883:
884: storebyte(dstaddr, outdata);
885:
886: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
887: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
888: XFLAG = CFLAG = srcdata > dstdata;
889: NFLAG = ((sint8)outdata) < 0;
890: ZFLAG = !outdata;
891: PC+= 4;
892: }
893:
894: void cpu_op_814a(t_ipc *ipc) /* SUB */ {
895: /* mask f1f8, bits 5130, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
896: unsigned int srcdata = ipc->src;
897: int dstreg = (ipc->opcode >> 0) & 7;
898: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
899: uint8 dstdata = fetchbyte(dstaddr);
900: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
901:
902: storebyte(dstaddr, outdata);
903: PC+= 4;
904: }
905:
906: void cpu_op_814b(t_ipc *ipc) /* SUB */ {
907: /* mask f1f8, bits 5130, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
908: unsigned int srcdata = ipc->src;
909: int dstreg = (ipc->opcode >> 0) & 7;
910: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
911: uint8 dstdata = fetchbyte(dstaddr);
912: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
913:
914: storebyte(dstaddr, outdata);
915:
916: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
917: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
918: XFLAG = CFLAG = srcdata > dstdata;
919: NFLAG = ((sint8)outdata) < 0;
920: ZFLAG = !outdata;
921: PC+= 4;
922: }
923:
924: void cpu_op_815a(t_ipc *ipc) /* SUB */ {
925: /* mask f1ff, bits 5138, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
926: unsigned int srcdata = ipc->src;
927: uint32 dstaddr = ipc->dst;
928: uint8 dstdata = fetchbyte(dstaddr);
929: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
930:
931: storebyte(dstaddr, outdata);
932: PC+= 4;
933: }
934:
935: void cpu_op_815b(t_ipc *ipc) /* SUB */ {
936: /* mask f1ff, bits 5138, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
937: unsigned int srcdata = ipc->src;
938: uint32 dstaddr = ipc->dst;
939: uint8 dstdata = fetchbyte(dstaddr);
940: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
941:
942: storebyte(dstaddr, outdata);
943:
944: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
945: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
946: XFLAG = CFLAG = srcdata > dstdata;
947: NFLAG = ((sint8)outdata) < 0;
948: ZFLAG = !outdata;
949: PC+= 4;
950: }
951:
952: void cpu_op_816a(t_ipc *ipc) /* SUB */ {
953: /* mask f1ff, bits 5139, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
954: unsigned int srcdata = ipc->src;
955: uint32 dstaddr = ipc->dst;
956: uint8 dstdata = fetchbyte(dstaddr);
957: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
958:
959: storebyte(dstaddr, outdata);
960: PC+= 6;
961: }
962:
963: void cpu_op_816b(t_ipc *ipc) /* SUB */ {
964: /* mask f1ff, bits 5139, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 1, stype 15, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
965: unsigned int srcdata = ipc->src;
966: uint32 dstaddr = ipc->dst;
967: uint8 dstdata = fetchbyte(dstaddr);
968: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
969:
970: storebyte(dstaddr, outdata);
971:
972: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
973: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
974: XFLAG = CFLAG = srcdata > dstdata;
975: NFLAG = ((sint8)outdata) < 0;
976: ZFLAG = !outdata;
977: PC+= 6;
978: }
979:
980: void cpu_op_817a(t_ipc *ipc) /* SUB */ {
981: /* mask f1f8, bits 5140, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
982: unsigned int srcdata = ipc->src;
983: int dstreg = (ipc->opcode >> 0) & 7;
984: uint16 dstdata = DATAREG(dstreg);
985: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
986:
987: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
988: PC+= 2;
989: }
990:
991: void cpu_op_817b(t_ipc *ipc) /* SUB */ {
992: /* mask f1f8, bits 5140, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
993: unsigned int srcdata = ipc->src;
994: int dstreg = (ipc->opcode >> 0) & 7;
995: uint16 dstdata = DATAREG(dstreg);
996: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
997:
998: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
999:
1000: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1001: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1002: XFLAG = CFLAG = srcdata > dstdata;
1003: NFLAG = ((sint16)outdata) < 0;
1004: ZFLAG = !outdata;
1005: PC+= 2;
1006: }
1007:
1008: void cpu_op_818a(t_ipc *ipc) /* SUB */ {
1009: /* mask f1f8, bits 5150, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
1010: unsigned int srcdata = ipc->src;
1011: int dstreg = (ipc->opcode >> 0) & 7;
1012: uint32 dstaddr = ADDRREG(dstreg);
1013: uint16 dstdata = fetchword(dstaddr);
1014: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1015:
1016: storeword(dstaddr, outdata);
1017: PC+= 2;
1018: }
1019:
1020: void cpu_op_818b(t_ipc *ipc) /* SUB */ {
1021: /* mask f1f8, bits 5150, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
1022: unsigned int srcdata = ipc->src;
1023: int dstreg = (ipc->opcode >> 0) & 7;
1024: uint32 dstaddr = ADDRREG(dstreg);
1025: uint16 dstdata = fetchword(dstaddr);
1026: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1027:
1028: storeword(dstaddr, outdata);
1029:
1030: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1031: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1032: XFLAG = CFLAG = srcdata > dstdata;
1033: NFLAG = ((sint16)outdata) < 0;
1034: ZFLAG = !outdata;
1035: PC+= 2;
1036: }
1037:
1038: void cpu_op_819a(t_ipc *ipc) /* SUB */ {
1039: /* mask f1f8, bits 5158, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
1040: unsigned int srcdata = ipc->src;
1041: int dstreg = (ipc->opcode >> 0) & 7;
1042: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
1043: uint16 dstdata = fetchword(dstaddr);
1044: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1045:
1046: storeword(dstaddr, outdata);
1047: PC+= 2;
1048: }
1049:
1050: void cpu_op_819b(t_ipc *ipc) /* SUB */ {
1051: /* mask f1f8, bits 5158, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
1052: unsigned int srcdata = ipc->src;
1053: int dstreg = (ipc->opcode >> 0) & 7;
1054: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
1055: uint16 dstdata = fetchword(dstaddr);
1056: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1057:
1058: storeword(dstaddr, outdata);
1059:
1060: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1061: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1062: XFLAG = CFLAG = srcdata > dstdata;
1063: NFLAG = ((sint16)outdata) < 0;
1064: ZFLAG = !outdata;
1065: PC+= 2;
1066: }
1067:
1068: void cpu_op_820a(t_ipc *ipc) /* SUB */ {
1069: /* mask f1f8, bits 5160, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
1070: unsigned int srcdata = ipc->src;
1071: int dstreg = (ipc->opcode >> 0) & 7;
1072: uint32 dstaddr = ADDRREG(dstreg)-=2;
1073: uint16 dstdata = fetchword(dstaddr);
1074: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1075:
1076: storeword(dstaddr, outdata);
1077: PC+= 2;
1078: }
1079:
1080: void cpu_op_820b(t_ipc *ipc) /* SUB */ {
1081: /* mask f1f8, bits 5160, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
1082: unsigned int srcdata = ipc->src;
1083: int dstreg = (ipc->opcode >> 0) & 7;
1084: uint32 dstaddr = ADDRREG(dstreg)-=2;
1085: uint16 dstdata = fetchword(dstaddr);
1086: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1087:
1088: storeword(dstaddr, outdata);
1089:
1090: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1091: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1092: XFLAG = CFLAG = srcdata > dstdata;
1093: NFLAG = ((sint16)outdata) < 0;
1094: ZFLAG = !outdata;
1095: PC+= 2;
1096: }
1097:
1098: void cpu_op_821a(t_ipc *ipc) /* SUB */ {
1099: /* mask f1f8, bits 5168, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
1100: unsigned int srcdata = ipc->src;
1101: int dstreg = (ipc->opcode >> 0) & 7;
1102: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1103: uint16 dstdata = fetchword(dstaddr);
1104: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1105:
1106: storeword(dstaddr, outdata);
1107: PC+= 4;
1108: }
1109:
1110: void cpu_op_821b(t_ipc *ipc) /* SUB */ {
1111: /* mask f1f8, bits 5168, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
1112: unsigned int srcdata = ipc->src;
1113: int dstreg = (ipc->opcode >> 0) & 7;
1114: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1115: uint16 dstdata = fetchword(dstaddr);
1116: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1117:
1118: storeword(dstaddr, outdata);
1119:
1120: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1121: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1122: XFLAG = CFLAG = srcdata > dstdata;
1123: NFLAG = ((sint16)outdata) < 0;
1124: ZFLAG = !outdata;
1125: PC+= 4;
1126: }
1127:
1128: void cpu_op_822a(t_ipc *ipc) /* SUB */ {
1129: /* mask f1f8, bits 5170, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
1130: unsigned int srcdata = ipc->src;
1131: int dstreg = (ipc->opcode >> 0) & 7;
1132: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1133: uint16 dstdata = fetchword(dstaddr);
1134: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1135:
1136: storeword(dstaddr, outdata);
1137: PC+= 4;
1138: }
1139:
1140: void cpu_op_822b(t_ipc *ipc) /* SUB */ {
1141: /* mask f1f8, bits 5170, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
1142: unsigned int srcdata = ipc->src;
1143: int dstreg = (ipc->opcode >> 0) & 7;
1144: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1145: uint16 dstdata = fetchword(dstaddr);
1146: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1147:
1148: storeword(dstaddr, outdata);
1149:
1150: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1151: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1152: XFLAG = CFLAG = srcdata > dstdata;
1153: NFLAG = ((sint16)outdata) < 0;
1154: ZFLAG = !outdata;
1155: PC+= 4;
1156: }
1157:
1158: void cpu_op_823a(t_ipc *ipc) /* SUB */ {
1159: /* mask f1ff, bits 5178, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
1160: unsigned int srcdata = ipc->src;
1161: uint32 dstaddr = ipc->dst;
1162: uint16 dstdata = fetchword(dstaddr);
1163: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1164:
1165: storeword(dstaddr, outdata);
1166: PC+= 4;
1167: }
1168:
1169: void cpu_op_823b(t_ipc *ipc) /* SUB */ {
1170: /* mask f1ff, bits 5178, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
1171: unsigned int srcdata = ipc->src;
1172: uint32 dstaddr = ipc->dst;
1173: uint16 dstdata = fetchword(dstaddr);
1174: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1175:
1176: storeword(dstaddr, outdata);
1177:
1178: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1179: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1180: XFLAG = CFLAG = srcdata > dstdata;
1181: NFLAG = ((sint16)outdata) < 0;
1182: ZFLAG = !outdata;
1183: PC+= 4;
1184: }
1185:
1186: void cpu_op_824a(t_ipc *ipc) /* SUB */ {
1187: /* mask f1ff, bits 5179, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
1188: unsigned int srcdata = ipc->src;
1189: uint32 dstaddr = ipc->dst;
1190: uint16 dstdata = fetchword(dstaddr);
1191: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1192:
1193: storeword(dstaddr, outdata);
1194: PC+= 6;
1195: }
1196:
1197: void cpu_op_824b(t_ipc *ipc) /* SUB */ {
1198: /* mask f1ff, bits 5179, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 2, stype 15, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
1199: unsigned int srcdata = ipc->src;
1200: uint32 dstaddr = ipc->dst;
1201: uint16 dstdata = fetchword(dstaddr);
1202: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
1203:
1204: storeword(dstaddr, outdata);
1205:
1206: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
1207: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1208: XFLAG = CFLAG = srcdata > dstdata;
1209: NFLAG = ((sint16)outdata) < 0;
1210: ZFLAG = !outdata;
1211: PC+= 6;
1212: }
1213:
1214: void cpu_op_825a(t_ipc *ipc) /* SUB */ {
1215: /* mask f1f8, bits 5180, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
1216: unsigned int srcdata = ipc->src;
1217: int dstreg = (ipc->opcode >> 0) & 7;
1218: uint32 dstdata = DATAREG(dstreg);
1219: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1220:
1221: DATAREG(dstreg) = outdata;
1222: PC+= 2;
1223: }
1224:
1225: void cpu_op_825b(t_ipc *ipc) /* SUB */ {
1226: /* mask f1f8, bits 5180, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 0, sbitpos 9, dbitpos 0, immvalue 0 */
1227: unsigned int srcdata = ipc->src;
1228: int dstreg = (ipc->opcode >> 0) & 7;
1229: uint32 dstdata = DATAREG(dstreg);
1230: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1231:
1232: DATAREG(dstreg) = outdata;
1233:
1234: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
1235: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
1236: XFLAG = CFLAG = srcdata > dstdata;
1237: NFLAG = ((sint32)outdata) < 0;
1238: ZFLAG = !outdata;
1239: PC+= 2;
1240: }
1241:
1242: void cpu_op_826a(t_ipc *ipc) /* SUB */ {
1243: /* mask f1f8, bits 5190, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
1244: unsigned int srcdata = ipc->src;
1245: int dstreg = (ipc->opcode >> 0) & 7;
1246: uint32 dstaddr = ADDRREG(dstreg);
1247: uint32 dstdata = fetchlong(dstaddr);
1248: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1249:
1250: storelong(dstaddr, outdata);
1251: PC+= 2;
1252: }
1253:
1254: void cpu_op_826b(t_ipc *ipc) /* SUB */ {
1255: /* mask f1f8, bits 5190, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */
1256: unsigned int srcdata = ipc->src;
1257: int dstreg = (ipc->opcode >> 0) & 7;
1258: uint32 dstaddr = ADDRREG(dstreg);
1259: uint32 dstdata = fetchlong(dstaddr);
1260: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1261:
1262: storelong(dstaddr, outdata);
1263:
1264: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
1265: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
1266: XFLAG = CFLAG = srcdata > dstdata;
1267: NFLAG = ((sint32)outdata) < 0;
1268: ZFLAG = !outdata;
1269: PC+= 2;
1270: }
1271:
1272: void cpu_op_827a(t_ipc *ipc) /* SUB */ {
1273: /* mask f1f8, bits 5198, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
1274: unsigned int srcdata = ipc->src;
1275: int dstreg = (ipc->opcode >> 0) & 7;
1276: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
1277: uint32 dstdata = fetchlong(dstaddr);
1278: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1279:
1280: storelong(dstaddr, outdata);
1281: PC+= 2;
1282: }
1283:
1284: void cpu_op_827b(t_ipc *ipc) /* SUB */ {
1285: /* mask f1f8, bits 5198, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */
1286: unsigned int srcdata = ipc->src;
1287: int dstreg = (ipc->opcode >> 0) & 7;
1288: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
1289: uint32 dstdata = fetchlong(dstaddr);
1290: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1291:
1292: storelong(dstaddr, outdata);
1293:
1294: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
1295: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
1296: XFLAG = CFLAG = srcdata > dstdata;
1297: NFLAG = ((sint32)outdata) < 0;
1298: ZFLAG = !outdata;
1299: PC+= 2;
1300: }
1301:
1302: void cpu_op_828a(t_ipc *ipc) /* SUB */ {
1303: /* mask f1f8, bits 51a0, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
1304: unsigned int srcdata = ipc->src;
1305: int dstreg = (ipc->opcode >> 0) & 7;
1306: uint32 dstaddr = ADDRREG(dstreg)-=4;
1307: uint32 dstdata = fetchlong(dstaddr);
1308: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1309:
1310: storelong(dstaddr, outdata);
1311: PC+= 2;
1312: }
1313:
1314: void cpu_op_828b(t_ipc *ipc) /* SUB */ {
1315: /* mask f1f8, bits 51a0, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */
1316: unsigned int srcdata = ipc->src;
1317: int dstreg = (ipc->opcode >> 0) & 7;
1318: uint32 dstaddr = ADDRREG(dstreg)-=4;
1319: uint32 dstdata = fetchlong(dstaddr);
1320: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1321:
1322: storelong(dstaddr, outdata);
1323:
1324: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
1325: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
1326: XFLAG = CFLAG = srcdata > dstdata;
1327: NFLAG = ((sint32)outdata) < 0;
1328: ZFLAG = !outdata;
1329: PC+= 2;
1330: }
1331:
1332: void cpu_op_829a(t_ipc *ipc) /* SUB */ {
1333: /* mask f1f8, bits 51a8, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
1334: unsigned int srcdata = ipc->src;
1335: int dstreg = (ipc->opcode >> 0) & 7;
1336: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1337: uint32 dstdata = fetchlong(dstaddr);
1338: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1339:
1340: storelong(dstaddr, outdata);
1341: PC+= 4;
1342: }
1343:
1344: void cpu_op_829b(t_ipc *ipc) /* SUB */ {
1345: /* mask f1f8, bits 51a8, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */
1346: unsigned int srcdata = ipc->src;
1347: int dstreg = (ipc->opcode >> 0) & 7;
1348: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1349: uint32 dstdata = fetchlong(dstaddr);
1350: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1351:
1352: storelong(dstaddr, outdata);
1353:
1354: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
1355: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
1356: XFLAG = CFLAG = srcdata > dstdata;
1357: NFLAG = ((sint32)outdata) < 0;
1358: ZFLAG = !outdata;
1359: PC+= 4;
1360: }
1361:
1362: void cpu_op_830a(t_ipc *ipc) /* SUB */ {
1363: /* mask f1f8, bits 51b0, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
1364: unsigned int srcdata = ipc->src;
1365: int dstreg = (ipc->opcode >> 0) & 7;
1366: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1367: uint32 dstdata = fetchlong(dstaddr);
1368: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1369:
1370: storelong(dstaddr, outdata);
1371: PC+= 4;
1372: }
1373:
1374: void cpu_op_830b(t_ipc *ipc) /* SUB */ {
1375: /* mask f1f8, bits 51b0, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */
1376: unsigned int srcdata = ipc->src;
1377: int dstreg = (ipc->opcode >> 0) & 7;
1378: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1379: uint32 dstdata = fetchlong(dstaddr);
1380: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1381:
1382: storelong(dstaddr, outdata);
1383:
1384: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
1385: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
1386: XFLAG = CFLAG = srcdata > dstdata;
1387: NFLAG = ((sint32)outdata) < 0;
1388: ZFLAG = !outdata;
1389: PC+= 4;
1390: }
1391:
1392: void cpu_op_831a(t_ipc *ipc) /* SUB */ {
1393: /* mask f1ff, bits 51b8, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
1394: unsigned int srcdata = ipc->src;
1395: uint32 dstaddr = ipc->dst;
1396: uint32 dstdata = fetchlong(dstaddr);
1397: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1398:
1399: storelong(dstaddr, outdata);
1400: PC+= 4;
1401: }
1402:
1403: void cpu_op_831b(t_ipc *ipc) /* SUB */ {
1404: /* mask f1ff, bits 51b8, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */
1405: unsigned int srcdata = ipc->src;
1406: uint32 dstaddr = ipc->dst;
1407: uint32 dstdata = fetchlong(dstaddr);
1408: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1409:
1410: storelong(dstaddr, outdata);
1411:
1412: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
1413: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
1414: XFLAG = CFLAG = srcdata > dstdata;
1415: NFLAG = ((sint32)outdata) < 0;
1416: ZFLAG = !outdata;
1417: PC+= 4;
1418: }
1419:
1420: void cpu_op_832a(t_ipc *ipc) /* SUB */ {
1421: /* mask f1ff, bits 51b9, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
1422: unsigned int srcdata = ipc->src;
1423: uint32 dstaddr = ipc->dst;
1424: uint32 dstdata = fetchlong(dstaddr);
1425: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1426:
1427: storelong(dstaddr, outdata);
1428: PC+= 6;
1429: }
1430:
1431: void cpu_op_832b(t_ipc *ipc) /* SUB */ {
1432: /* mask f1ff, bits 51b9, mnemonic 7, priv 0, endblk 0, imm_notzero -1, used 0 set -1, size 3, stype 15, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */
1433: unsigned int srcdata = ipc->src;
1434: uint32 dstaddr = ipc->dst;
1435: uint32 dstdata = fetchlong(dstaddr);
1436: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1437:
1438: storelong(dstaddr, outdata);
1439:
1440: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
1441: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
1442: XFLAG = CFLAG = srcdata > dstdata;
1443: NFLAG = ((sint32)outdata) < 0;
1444: ZFLAG = !outdata;
1445: PC+= 6;
1446: }
1447:
1448: void cpu_op_833a(t_ipc *ipc) /* SUBA */ {
1449: /* mask f1f8, bits 5148, mnemonic 8, priv 0, endblk 0, imm_notzero -1, used 0 set 0, size 3, stype 15, dtype 1, sbitpos 9, dbitpos 0, immvalue 0 */
1450: unsigned int srcdata = ipc->src;
1451: int dstreg = (ipc->opcode >> 0) & 7;
1452: uint32 dstdata = ADDRREG(dstreg);
1453: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1454:
1455: ADDRREG(dstreg) = outdata;
1456: PC+= 2;
1457: }
1458:
1459: void cpu_op_834a(t_ipc *ipc) /* SUBA */ {
1460: /* mask f1f8, bits 5188, mnemonic 8, priv 0, endblk 0, imm_notzero -1, used 0 set 0, size 3, stype 15, dtype 1, sbitpos 9, dbitpos 0, immvalue 0 */
1461: unsigned int srcdata = ipc->src;
1462: int dstreg = (ipc->opcode >> 0) & 7;
1463: uint32 dstdata = ADDRREG(dstreg);
1464: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
1465:
1466: ADDRREG(dstreg) = outdata;
1467: PC+= 2;
1468: }
1469:
1470: void cpu_op_835a(t_ipc *ipc) /* ADD */ {
1471: /* mask fff8, bits 5000, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 0, sbitpos 0, dbitpos 0, immvalue 8 */
1472: unsigned int srcdata = 8;
1473: int dstreg = (ipc->opcode >> 0) & 7;
1474: uint8 dstdata = DATAREG(dstreg);
1475: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1476:
1477: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
1478: PC+= 2;
1479: }
1480:
1481: void cpu_op_835b(t_ipc *ipc) /* ADD */ {
1482: /* mask fff8, bits 5000, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 0, sbitpos 0, dbitpos 0, immvalue 8 */
1483: unsigned int srcdata = 8;
1484: int dstreg = (ipc->opcode >> 0) & 7;
1485: uint8 dstdata = DATAREG(dstreg);
1486: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1487:
1488: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
1489:
1490: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
1491: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1492: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
1493: NFLAG = ((sint8)outdata) < 0;
1494: ZFLAG = !outdata;
1495: PC+= 2;
1496: }
1497:
1498: void cpu_op_836a(t_ipc *ipc) /* ADD */ {
1499: /* mask fff8, bits 5010, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 2, sbitpos 0, dbitpos 0, immvalue 8 */
1500: unsigned int srcdata = 8;
1501: int dstreg = (ipc->opcode >> 0) & 7;
1502: uint32 dstaddr = ADDRREG(dstreg);
1503: uint8 dstdata = fetchbyte(dstaddr);
1504: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1505:
1506: storebyte(dstaddr, outdata);
1507: PC+= 2;
1508: }
1509:
1510: void cpu_op_836b(t_ipc *ipc) /* ADD */ {
1511: /* mask fff8, bits 5010, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 2, sbitpos 0, dbitpos 0, immvalue 8 */
1512: unsigned int srcdata = 8;
1513: int dstreg = (ipc->opcode >> 0) & 7;
1514: uint32 dstaddr = ADDRREG(dstreg);
1515: uint8 dstdata = fetchbyte(dstaddr);
1516: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1517:
1518: storebyte(dstaddr, outdata);
1519:
1520: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
1521: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1522: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
1523: NFLAG = ((sint8)outdata) < 0;
1524: ZFLAG = !outdata;
1525: PC+= 2;
1526: }
1527:
1528: void cpu_op_837a(t_ipc *ipc) /* ADD */ {
1529: /* mask fff8, bits 5018, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 3, sbitpos 0, dbitpos 0, immvalue 8 */
1530: unsigned int srcdata = 8;
1531: int dstreg = (ipc->opcode >> 0) & 7;
1532: uint32 dstaddr = ADDRREG(dstreg);
1533: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
1534: uint8 dstdata = fetchbyte(dstaddr);
1535: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1536:
1537: storebyte(dstaddr, outdata);
1538: PC+= 2;
1539: }
1540:
1541: void cpu_op_837b(t_ipc *ipc) /* ADD */ {
1542: /* mask fff8, bits 5018, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 3, sbitpos 0, dbitpos 0, immvalue 8 */
1543: unsigned int srcdata = 8;
1544: int dstreg = (ipc->opcode >> 0) & 7;
1545: uint32 dstaddr = ADDRREG(dstreg);
1546: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
1547: uint8 dstdata = fetchbyte(dstaddr);
1548: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1549:
1550: storebyte(dstaddr, outdata);
1551:
1552: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
1553: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1554: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
1555: NFLAG = ((sint8)outdata) < 0;
1556: ZFLAG = !outdata;
1557: PC+= 2;
1558: }
1559:
1560: void cpu_op_838a(t_ipc *ipc) /* ADD */ {
1561: /* mask fff8, bits 5020, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 4, sbitpos 0, dbitpos 0, immvalue 8 */
1562: unsigned int srcdata = 8;
1563: int dstreg = (ipc->opcode >> 0) & 7;
1564: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
1565: uint8 dstdata = fetchbyte(dstaddr);
1566: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1567:
1568: storebyte(dstaddr, outdata);
1569: PC+= 2;
1570: }
1571:
1572: void cpu_op_838b(t_ipc *ipc) /* ADD */ {
1573: /* mask fff8, bits 5020, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 4, sbitpos 0, dbitpos 0, immvalue 8 */
1574: unsigned int srcdata = 8;
1575: int dstreg = (ipc->opcode >> 0) & 7;
1576: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
1577: uint8 dstdata = fetchbyte(dstaddr);
1578: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1579:
1580: storebyte(dstaddr, outdata);
1581:
1582: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
1583: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1584: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
1585: NFLAG = ((sint8)outdata) < 0;
1586: ZFLAG = !outdata;
1587: PC+= 2;
1588: }
1589:
1590: void cpu_op_839a(t_ipc *ipc) /* ADD */ {
1591: /* mask fff8, bits 5028, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 5, sbitpos 0, dbitpos 0, immvalue 8 */
1592: unsigned int srcdata = 8;
1593: int dstreg = (ipc->opcode >> 0) & 7;
1594: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1595: uint8 dstdata = fetchbyte(dstaddr);
1596: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1597:
1598: storebyte(dstaddr, outdata);
1599: PC+= 4;
1600: }
1601:
1602: void cpu_op_839b(t_ipc *ipc) /* ADD */ {
1603: /* mask fff8, bits 5028, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 5, sbitpos 0, dbitpos 0, immvalue 8 */
1604: unsigned int srcdata = 8;
1605: int dstreg = (ipc->opcode >> 0) & 7;
1606: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1607: uint8 dstdata = fetchbyte(dstaddr);
1608: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1609:
1610: storebyte(dstaddr, outdata);
1611:
1612: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
1613: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1614: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
1615: NFLAG = ((sint8)outdata) < 0;
1616: ZFLAG = !outdata;
1617: PC+= 4;
1618: }
1619:
1620: void cpu_op_840a(t_ipc *ipc) /* ADD */ {
1621: /* mask fff8, bits 5030, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 6, sbitpos 0, dbitpos 0, immvalue 8 */
1622: unsigned int srcdata = 8;
1623: int dstreg = (ipc->opcode >> 0) & 7;
1624: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1625: uint8 dstdata = fetchbyte(dstaddr);
1626: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1627:
1628: storebyte(dstaddr, outdata);
1629: PC+= 4;
1630: }
1631:
1632: void cpu_op_840b(t_ipc *ipc) /* ADD */ {
1633: /* mask fff8, bits 5030, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 6, sbitpos 0, dbitpos 0, immvalue 8 */
1634: unsigned int srcdata = 8;
1635: int dstreg = (ipc->opcode >> 0) & 7;
1636: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1637: uint8 dstdata = fetchbyte(dstaddr);
1638: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1639:
1640: storebyte(dstaddr, outdata);
1641:
1642: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
1643: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1644: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
1645: NFLAG = ((sint8)outdata) < 0;
1646: ZFLAG = !outdata;
1647: PC+= 4;
1648: }
1649:
1650: void cpu_op_841a(t_ipc *ipc) /* ADD */ {
1651: /* mask ffff, bits 5038, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 7, sbitpos 0, dbitpos 0, immvalue 8 */
1652: unsigned int srcdata = 8;
1653: uint32 dstaddr = ipc->dst;
1654: uint8 dstdata = fetchbyte(dstaddr);
1655: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1656:
1657: storebyte(dstaddr, outdata);
1658: PC+= 4;
1659: }
1660:
1661: void cpu_op_841b(t_ipc *ipc) /* ADD */ {
1662: /* mask ffff, bits 5038, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 7, sbitpos 0, dbitpos 0, immvalue 8 */
1663: unsigned int srcdata = 8;
1664: uint32 dstaddr = ipc->dst;
1665: uint8 dstdata = fetchbyte(dstaddr);
1666: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1667:
1668: storebyte(dstaddr, outdata);
1669:
1670: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
1671: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1672: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
1673: NFLAG = ((sint8)outdata) < 0;
1674: ZFLAG = !outdata;
1675: PC+= 4;
1676: }
1677:
1678: void cpu_op_842a(t_ipc *ipc) /* ADD */ {
1679: /* mask ffff, bits 5039, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 8, sbitpos 0, dbitpos 0, immvalue 8 */
1680: unsigned int srcdata = 8;
1681: uint32 dstaddr = ipc->dst;
1682: uint8 dstdata = fetchbyte(dstaddr);
1683: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1684:
1685: storebyte(dstaddr, outdata);
1686: PC+= 6;
1687: }
1688:
1689: void cpu_op_842b(t_ipc *ipc) /* ADD */ {
1690: /* mask ffff, bits 5039, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 8, sbitpos 0, dbitpos 0, immvalue 8 */
1691: unsigned int srcdata = 8;
1692: uint32 dstaddr = ipc->dst;
1693: uint8 dstdata = fetchbyte(dstaddr);
1694: uint8 outdata = (sint8)dstdata + (sint8)srcdata;
1695:
1696: storebyte(dstaddr, outdata);
1697:
1698: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) &&
1699: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
1700: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata);
1701: NFLAG = ((sint8)outdata) < 0;
1702: ZFLAG = !outdata;
1703: PC+= 6;
1704: }
1705:
1706: void cpu_op_843a(t_ipc *ipc) /* ADD */ {
1707: /* mask fff8, bits 5040, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 0, sbitpos 0, dbitpos 0, immvalue 8 */
1708: unsigned int srcdata = 8;
1709: int dstreg = (ipc->opcode >> 0) & 7;
1710: uint16 dstdata = DATAREG(dstreg);
1711: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1712:
1713: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
1714: PC+= 2;
1715: }
1716:
1717: void cpu_op_843b(t_ipc *ipc) /* ADD */ {
1718: /* mask fff8, bits 5040, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 0, sbitpos 0, dbitpos 0, immvalue 8 */
1719: unsigned int srcdata = 8;
1720: int dstreg = (ipc->opcode >> 0) & 7;
1721: uint16 dstdata = DATAREG(dstreg);
1722: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1723:
1724: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
1725:
1726: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
1727: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1728: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
1729: NFLAG = ((sint16)outdata) < 0;
1730: ZFLAG = !outdata;
1731: PC+= 2;
1732: }
1733:
1734: void cpu_op_844a(t_ipc *ipc) /* ADD */ {
1735: /* mask fff8, bits 5050, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 2, sbitpos 0, dbitpos 0, immvalue 8 */
1736: unsigned int srcdata = 8;
1737: int dstreg = (ipc->opcode >> 0) & 7;
1738: uint32 dstaddr = ADDRREG(dstreg);
1739: uint16 dstdata = fetchword(dstaddr);
1740: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1741:
1742: storeword(dstaddr, outdata);
1743: PC+= 2;
1744: }
1745:
1746: void cpu_op_844b(t_ipc *ipc) /* ADD */ {
1747: /* mask fff8, bits 5050, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 2, sbitpos 0, dbitpos 0, immvalue 8 */
1748: unsigned int srcdata = 8;
1749: int dstreg = (ipc->opcode >> 0) & 7;
1750: uint32 dstaddr = ADDRREG(dstreg);
1751: uint16 dstdata = fetchword(dstaddr);
1752: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1753:
1754: storeword(dstaddr, outdata);
1755:
1756: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
1757: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1758: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
1759: NFLAG = ((sint16)outdata) < 0;
1760: ZFLAG = !outdata;
1761: PC+= 2;
1762: }
1763:
1764: void cpu_op_845a(t_ipc *ipc) /* ADD */ {
1765: /* mask fff8, bits 5058, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 3, sbitpos 0, dbitpos 0, immvalue 8 */
1766: unsigned int srcdata = 8;
1767: int dstreg = (ipc->opcode >> 0) & 7;
1768: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
1769: uint16 dstdata = fetchword(dstaddr);
1770: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1771:
1772: storeword(dstaddr, outdata);
1773: PC+= 2;
1774: }
1775:
1776: void cpu_op_845b(t_ipc *ipc) /* ADD */ {
1777: /* mask fff8, bits 5058, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 3, sbitpos 0, dbitpos 0, immvalue 8 */
1778: unsigned int srcdata = 8;
1779: int dstreg = (ipc->opcode >> 0) & 7;
1780: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
1781: uint16 dstdata = fetchword(dstaddr);
1782: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1783:
1784: storeword(dstaddr, outdata);
1785:
1786: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
1787: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1788: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
1789: NFLAG = ((sint16)outdata) < 0;
1790: ZFLAG = !outdata;
1791: PC+= 2;
1792: }
1793:
1794: void cpu_op_846a(t_ipc *ipc) /* ADD */ {
1795: /* mask fff8, bits 5060, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 4, sbitpos 0, dbitpos 0, immvalue 8 */
1796: unsigned int srcdata = 8;
1797: int dstreg = (ipc->opcode >> 0) & 7;
1798: uint32 dstaddr = ADDRREG(dstreg)-=2;
1799: uint16 dstdata = fetchword(dstaddr);
1800: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1801:
1802: storeword(dstaddr, outdata);
1803: PC+= 2;
1804: }
1805:
1806: void cpu_op_846b(t_ipc *ipc) /* ADD */ {
1807: /* mask fff8, bits 5060, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 4, sbitpos 0, dbitpos 0, immvalue 8 */
1808: unsigned int srcdata = 8;
1809: int dstreg = (ipc->opcode >> 0) & 7;
1810: uint32 dstaddr = ADDRREG(dstreg)-=2;
1811: uint16 dstdata = fetchword(dstaddr);
1812: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1813:
1814: storeword(dstaddr, outdata);
1815:
1816: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
1817: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1818: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
1819: NFLAG = ((sint16)outdata) < 0;
1820: ZFLAG = !outdata;
1821: PC+= 2;
1822: }
1823:
1824: void cpu_op_847a(t_ipc *ipc) /* ADD */ {
1825: /* mask fff8, bits 5068, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 5, sbitpos 0, dbitpos 0, immvalue 8 */
1826: unsigned int srcdata = 8;
1827: int dstreg = (ipc->opcode >> 0) & 7;
1828: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1829: uint16 dstdata = fetchword(dstaddr);
1830: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1831:
1832: storeword(dstaddr, outdata);
1833: PC+= 4;
1834: }
1835:
1836: void cpu_op_847b(t_ipc *ipc) /* ADD */ {
1837: /* mask fff8, bits 5068, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 5, sbitpos 0, dbitpos 0, immvalue 8 */
1838: unsigned int srcdata = 8;
1839: int dstreg = (ipc->opcode >> 0) & 7;
1840: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
1841: uint16 dstdata = fetchword(dstaddr);
1842: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1843:
1844: storeword(dstaddr, outdata);
1845:
1846: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
1847: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1848: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
1849: NFLAG = ((sint16)outdata) < 0;
1850: ZFLAG = !outdata;
1851: PC+= 4;
1852: }
1853:
1854: void cpu_op_848a(t_ipc *ipc) /* ADD */ {
1855: /* mask fff8, bits 5070, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 6, sbitpos 0, dbitpos 0, immvalue 8 */
1856: unsigned int srcdata = 8;
1857: int dstreg = (ipc->opcode >> 0) & 7;
1858: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1859: uint16 dstdata = fetchword(dstaddr);
1860: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1861:
1862: storeword(dstaddr, outdata);
1863: PC+= 4;
1864: }
1865:
1866: void cpu_op_848b(t_ipc *ipc) /* ADD */ {
1867: /* mask fff8, bits 5070, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 6, sbitpos 0, dbitpos 0, immvalue 8 */
1868: unsigned int srcdata = 8;
1869: int dstreg = (ipc->opcode >> 0) & 7;
1870: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
1871: uint16 dstdata = fetchword(dstaddr);
1872: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1873:
1874: storeword(dstaddr, outdata);
1875:
1876: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
1877: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1878: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
1879: NFLAG = ((sint16)outdata) < 0;
1880: ZFLAG = !outdata;
1881: PC+= 4;
1882: }
1883:
1884: void cpu_op_849a(t_ipc *ipc) /* ADD */ {
1885: /* mask ffff, bits 5078, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 7, sbitpos 0, dbitpos 0, immvalue 8 */
1886: unsigned int srcdata = 8;
1887: uint32 dstaddr = ipc->dst;
1888: uint16 dstdata = fetchword(dstaddr);
1889: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1890:
1891: storeword(dstaddr, outdata);
1892: PC+= 4;
1893: }
1894:
1895: void cpu_op_849b(t_ipc *ipc) /* ADD */ {
1896: /* mask ffff, bits 5078, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 7, sbitpos 0, dbitpos 0, immvalue 8 */
1897: unsigned int srcdata = 8;
1898: uint32 dstaddr = ipc->dst;
1899: uint16 dstdata = fetchword(dstaddr);
1900: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1901:
1902: storeword(dstaddr, outdata);
1903:
1904: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
1905: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1906: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
1907: NFLAG = ((sint16)outdata) < 0;
1908: ZFLAG = !outdata;
1909: PC+= 4;
1910: }
1911:
1912: void cpu_op_850a(t_ipc *ipc) /* ADD */ {
1913: /* mask ffff, bits 5079, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 8, sbitpos 0, dbitpos 0, immvalue 8 */
1914: unsigned int srcdata = 8;
1915: uint32 dstaddr = ipc->dst;
1916: uint16 dstdata = fetchword(dstaddr);
1917: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1918:
1919: storeword(dstaddr, outdata);
1920: PC+= 6;
1921: }
1922:
1923: void cpu_op_850b(t_ipc *ipc) /* ADD */ {
1924: /* mask ffff, bits 5079, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 8, sbitpos 0, dbitpos 0, immvalue 8 */
1925: unsigned int srcdata = 8;
1926: uint32 dstaddr = ipc->dst;
1927: uint16 dstdata = fetchword(dstaddr);
1928: uint16 outdata = (sint16)dstdata + (sint16)srcdata;
1929:
1930: storeword(dstaddr, outdata);
1931:
1932: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) &&
1933: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
1934: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata);
1935: NFLAG = ((sint16)outdata) < 0;
1936: ZFLAG = !outdata;
1937: PC+= 6;
1938: }
1939:
1940: void cpu_op_851a(t_ipc *ipc) /* ADD */ {
1941: /* mask fff8, bits 5080, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 0, sbitpos 0, dbitpos 0, immvalue 8 */
1942: unsigned int srcdata = 8;
1943: int dstreg = (ipc->opcode >> 0) & 7;
1944: uint32 dstdata = DATAREG(dstreg);
1945: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
1946:
1947: DATAREG(dstreg) = outdata;
1948: PC+= 2;
1949: }
1950:
1951: void cpu_op_851b(t_ipc *ipc) /* ADD */ {
1952: /* mask fff8, bits 5080, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 0, sbitpos 0, dbitpos 0, immvalue 8 */
1953: unsigned int srcdata = 8;
1954: int dstreg = (ipc->opcode >> 0) & 7;
1955: uint32 dstdata = DATAREG(dstreg);
1956: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
1957:
1958: DATAREG(dstreg) = outdata;
1959:
1960: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
1961: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
1962: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
1963: NFLAG = ((sint32)outdata) < 0;
1964: ZFLAG = !outdata;
1965: PC+= 2;
1966: }
1967:
1968: void cpu_op_852a(t_ipc *ipc) /* ADD */ {
1969: /* mask fff8, bits 5090, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 2, sbitpos 0, dbitpos 0, immvalue 8 */
1970: unsigned int srcdata = 8;
1971: int dstreg = (ipc->opcode >> 0) & 7;
1972: uint32 dstaddr = ADDRREG(dstreg);
1973: uint32 dstdata = fetchlong(dstaddr);
1974: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
1975:
1976: storelong(dstaddr, outdata);
1977: PC+= 2;
1978: }
1979:
1980: void cpu_op_852b(t_ipc *ipc) /* ADD */ {
1981: /* mask fff8, bits 5090, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 2, sbitpos 0, dbitpos 0, immvalue 8 */
1982: unsigned int srcdata = 8;
1983: int dstreg = (ipc->opcode >> 0) & 7;
1984: uint32 dstaddr = ADDRREG(dstreg);
1985: uint32 dstdata = fetchlong(dstaddr);
1986: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
1987:
1988: storelong(dstaddr, outdata);
1989:
1990: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
1991: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
1992: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
1993: NFLAG = ((sint32)outdata) < 0;
1994: ZFLAG = !outdata;
1995: PC+= 2;
1996: }
1997:
1998: void cpu_op_853a(t_ipc *ipc) /* ADD */ {
1999: /* mask fff8, bits 5098, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 3, sbitpos 0, dbitpos 0, immvalue 8 */
2000: unsigned int srcdata = 8;
2001: int dstreg = (ipc->opcode >> 0) & 7;
2002: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
2003: uint32 dstdata = fetchlong(dstaddr);
2004: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2005:
2006: storelong(dstaddr, outdata);
2007: PC+= 2;
2008: }
2009:
2010: void cpu_op_853b(t_ipc *ipc) /* ADD */ {
2011: /* mask fff8, bits 5098, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 3, sbitpos 0, dbitpos 0, immvalue 8 */
2012: unsigned int srcdata = 8;
2013: int dstreg = (ipc->opcode >> 0) & 7;
2014: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
2015: uint32 dstdata = fetchlong(dstaddr);
2016: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2017:
2018: storelong(dstaddr, outdata);
2019:
2020: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2021: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2022: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2023: NFLAG = ((sint32)outdata) < 0;
2024: ZFLAG = !outdata;
2025: PC+= 2;
2026: }
2027:
2028: void cpu_op_854a(t_ipc *ipc) /* ADD */ {
2029: /* mask fff8, bits 50a0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 4, sbitpos 0, dbitpos 0, immvalue 8 */
2030: unsigned int srcdata = 8;
2031: int dstreg = (ipc->opcode >> 0) & 7;
2032: uint32 dstaddr = ADDRREG(dstreg)-=4;
2033: uint32 dstdata = fetchlong(dstaddr);
2034: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2035:
2036: storelong(dstaddr, outdata);
2037: PC+= 2;
2038: }
2039:
2040: void cpu_op_854b(t_ipc *ipc) /* ADD */ {
2041: /* mask fff8, bits 50a0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 4, sbitpos 0, dbitpos 0, immvalue 8 */
2042: unsigned int srcdata = 8;
2043: int dstreg = (ipc->opcode >> 0) & 7;
2044: uint32 dstaddr = ADDRREG(dstreg)-=4;
2045: uint32 dstdata = fetchlong(dstaddr);
2046: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2047:
2048: storelong(dstaddr, outdata);
2049:
2050: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2051: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2052: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2053: NFLAG = ((sint32)outdata) < 0;
2054: ZFLAG = !outdata;
2055: PC+= 2;
2056: }
2057:
2058: void cpu_op_855a(t_ipc *ipc) /* ADD */ {
2059: /* mask fff8, bits 50a8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 5, sbitpos 0, dbitpos 0, immvalue 8 */
2060: unsigned int srcdata = 8;
2061: int dstreg = (ipc->opcode >> 0) & 7;
2062: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2063: uint32 dstdata = fetchlong(dstaddr);
2064: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2065:
2066: storelong(dstaddr, outdata);
2067: PC+= 4;
2068: }
2069:
2070: void cpu_op_855b(t_ipc *ipc) /* ADD */ {
2071: /* mask fff8, bits 50a8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 5, sbitpos 0, dbitpos 0, immvalue 8 */
2072: unsigned int srcdata = 8;
2073: int dstreg = (ipc->opcode >> 0) & 7;
2074: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2075: uint32 dstdata = fetchlong(dstaddr);
2076: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2077:
2078: storelong(dstaddr, outdata);
2079:
2080: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2081: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2082: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2083: NFLAG = ((sint32)outdata) < 0;
2084: ZFLAG = !outdata;
2085: PC+= 4;
2086: }
2087:
2088: void cpu_op_856a(t_ipc *ipc) /* ADD */ {
2089: /* mask fff8, bits 50b0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 6, sbitpos 0, dbitpos 0, immvalue 8 */
2090: unsigned int srcdata = 8;
2091: int dstreg = (ipc->opcode >> 0) & 7;
2092: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2093: uint32 dstdata = fetchlong(dstaddr);
2094: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2095:
2096: storelong(dstaddr, outdata);
2097: PC+= 4;
2098: }
2099:
2100: void cpu_op_856b(t_ipc *ipc) /* ADD */ {
2101: /* mask fff8, bits 50b0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 6, sbitpos 0, dbitpos 0, immvalue 8 */
2102: unsigned int srcdata = 8;
2103: int dstreg = (ipc->opcode >> 0) & 7;
2104: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2105: uint32 dstdata = fetchlong(dstaddr);
2106: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2107:
2108: storelong(dstaddr, outdata);
2109:
2110: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2111: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2112: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2113: NFLAG = ((sint32)outdata) < 0;
2114: ZFLAG = !outdata;
2115: PC+= 4;
2116: }
2117:
2118: void cpu_op_857a(t_ipc *ipc) /* ADD */ {
2119: /* mask ffff, bits 50b8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 7, sbitpos 0, dbitpos 0, immvalue 8 */
2120: unsigned int srcdata = 8;
2121: uint32 dstaddr = ipc->dst;
2122: uint32 dstdata = fetchlong(dstaddr);
2123: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2124:
2125: storelong(dstaddr, outdata);
2126: PC+= 4;
2127: }
2128:
2129: void cpu_op_857b(t_ipc *ipc) /* ADD */ {
2130: /* mask ffff, bits 50b8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 7, sbitpos 0, dbitpos 0, immvalue 8 */
2131: unsigned int srcdata = 8;
2132: uint32 dstaddr = ipc->dst;
2133: uint32 dstdata = fetchlong(dstaddr);
2134: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2135:
2136: storelong(dstaddr, outdata);
2137:
2138: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2139: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2140: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2141: NFLAG = ((sint32)outdata) < 0;
2142: ZFLAG = !outdata;
2143: PC+= 4;
2144: }
2145:
2146: void cpu_op_858a(t_ipc *ipc) /* ADD */ {
2147: /* mask ffff, bits 50b9, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 8, sbitpos 0, dbitpos 0, immvalue 8 */
2148: unsigned int srcdata = 8;
2149: uint32 dstaddr = ipc->dst;
2150: uint32 dstdata = fetchlong(dstaddr);
2151: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2152:
2153: storelong(dstaddr, outdata);
2154: PC+= 6;
2155: }
2156:
2157: void cpu_op_858b(t_ipc *ipc) /* ADD */ {
2158: /* mask ffff, bits 50b9, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 8, sbitpos 0, dbitpos 0, immvalue 8 */
2159: unsigned int srcdata = 8;
2160: uint32 dstaddr = ipc->dst;
2161: uint32 dstdata = fetchlong(dstaddr);
2162: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2163:
2164: storelong(dstaddr, outdata);
2165:
2166: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) &&
2167: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2168: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata;
2169: NFLAG = ((sint32)outdata) < 0;
2170: ZFLAG = !outdata;
2171: PC+= 6;
2172: }
2173:
2174: void cpu_op_859a(t_ipc *ipc) /* ADDA */ {
2175: /* mask fff8, bits 5048, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 14, dtype 1, sbitpos 0, dbitpos 0, immvalue 8 */
2176: unsigned int srcdata = 8;
2177: int dstreg = (ipc->opcode >> 0) & 7;
2178: uint32 dstdata = ADDRREG(dstreg);
2179: uint32 outdata = (sint32)dstdata + (sint16)srcdata;
2180:
2181: ADDRREG(dstreg) = outdata;
2182: PC+= 2;
2183: }
2184:
2185: void cpu_op_860a(t_ipc *ipc) /* ADDA */ {
2186: /* mask fff8, bits 5088, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 14, dtype 1, sbitpos 0, dbitpos 0, immvalue 8 */
2187: unsigned int srcdata = 8;
2188: int dstreg = (ipc->opcode >> 0) & 7;
2189: uint32 dstdata = ADDRREG(dstreg);
2190: uint32 outdata = (sint32)dstdata + (sint32)srcdata;
2191:
2192: ADDRREG(dstreg) = outdata;
2193: PC+= 2;
2194: }
2195:
2196: void cpu_op_861a(t_ipc *ipc) /* SUB */ {
2197: /* mask fff8, bits 5100, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 0, sbitpos 0, dbitpos 0, immvalue 8 */
2198: unsigned int srcdata = 8;
2199: int dstreg = (ipc->opcode >> 0) & 7;
2200: uint8 dstdata = DATAREG(dstreg);
2201: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2202:
2203: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
2204: PC+= 2;
2205: }
2206:
2207: void cpu_op_861b(t_ipc *ipc) /* SUB */ {
2208: /* mask fff8, bits 5100, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 0, sbitpos 0, dbitpos 0, immvalue 8 */
2209: unsigned int srcdata = 8;
2210: int dstreg = (ipc->opcode >> 0) & 7;
2211: uint8 dstdata = DATAREG(dstreg);
2212: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2213:
2214: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata;
2215:
2216: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
2217: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2218: XFLAG = CFLAG = srcdata > dstdata;
2219: NFLAG = ((sint8)outdata) < 0;
2220: ZFLAG = !outdata;
2221: PC+= 2;
2222: }
2223:
2224: void cpu_op_862a(t_ipc *ipc) /* SUB */ {
2225: /* mask fff8, bits 5110, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 2, sbitpos 0, dbitpos 0, immvalue 8 */
2226: unsigned int srcdata = 8;
2227: int dstreg = (ipc->opcode >> 0) & 7;
2228: uint32 dstaddr = ADDRREG(dstreg);
2229: uint8 dstdata = fetchbyte(dstaddr);
2230: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2231:
2232: storebyte(dstaddr, outdata);
2233: PC+= 2;
2234: }
2235:
2236: void cpu_op_862b(t_ipc *ipc) /* SUB */ {
2237: /* mask fff8, bits 5110, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 2, sbitpos 0, dbitpos 0, immvalue 8 */
2238: unsigned int srcdata = 8;
2239: int dstreg = (ipc->opcode >> 0) & 7;
2240: uint32 dstaddr = ADDRREG(dstreg);
2241: uint8 dstdata = fetchbyte(dstaddr);
2242: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2243:
2244: storebyte(dstaddr, outdata);
2245:
2246: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
2247: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2248: XFLAG = CFLAG = srcdata > dstdata;
2249: NFLAG = ((sint8)outdata) < 0;
2250: ZFLAG = !outdata;
2251: PC+= 2;
2252: }
2253:
2254: void cpu_op_863a(t_ipc *ipc) /* SUB */ {
2255: /* mask fff8, bits 5118, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 3, sbitpos 0, dbitpos 0, immvalue 8 */
2256: unsigned int srcdata = 8;
2257: int dstreg = (ipc->opcode >> 0) & 7;
2258: uint32 dstaddr = ADDRREG(dstreg);
2259: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2260: uint8 dstdata = fetchbyte(dstaddr);
2261: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2262:
2263: storebyte(dstaddr, outdata);
2264: PC+= 2;
2265: }
2266:
2267: void cpu_op_863b(t_ipc *ipc) /* SUB */ {
2268: /* mask fff8, bits 5118, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 3, sbitpos 0, dbitpos 0, immvalue 8 */
2269: unsigned int srcdata = 8;
2270: int dstreg = (ipc->opcode >> 0) & 7;
2271: uint32 dstaddr = ADDRREG(dstreg);
2272: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0);
2273: uint8 dstdata = fetchbyte(dstaddr);
2274: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2275:
2276: storebyte(dstaddr, outdata);
2277:
2278: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
2279: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2280: XFLAG = CFLAG = srcdata > dstdata;
2281: NFLAG = ((sint8)outdata) < 0;
2282: ZFLAG = !outdata;
2283: PC+= 2;
2284: }
2285:
2286: void cpu_op_864a(t_ipc *ipc) /* SUB */ {
2287: /* mask fff8, bits 5120, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 4, sbitpos 0, dbitpos 0, immvalue 8 */
2288: unsigned int srcdata = 8;
2289: int dstreg = (ipc->opcode >> 0) & 7;
2290: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2291: uint8 dstdata = fetchbyte(dstaddr);
2292: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2293:
2294: storebyte(dstaddr, outdata);
2295: PC+= 2;
2296: }
2297:
2298: void cpu_op_864b(t_ipc *ipc) /* SUB */ {
2299: /* mask fff8, bits 5120, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 4, sbitpos 0, dbitpos 0, immvalue 8 */
2300: unsigned int srcdata = 8;
2301: int dstreg = (ipc->opcode >> 0) & 7;
2302: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1));
2303: uint8 dstdata = fetchbyte(dstaddr);
2304: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2305:
2306: storebyte(dstaddr, outdata);
2307:
2308: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
2309: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2310: XFLAG = CFLAG = srcdata > dstdata;
2311: NFLAG = ((sint8)outdata) < 0;
2312: ZFLAG = !outdata;
2313: PC+= 2;
2314: }
2315:
2316: void cpu_op_865a(t_ipc *ipc) /* SUB */ {
2317: /* mask fff8, bits 5128, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 5, sbitpos 0, dbitpos 0, immvalue 8 */
2318: unsigned int srcdata = 8;
2319: int dstreg = (ipc->opcode >> 0) & 7;
2320: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2321: uint8 dstdata = fetchbyte(dstaddr);
2322: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2323:
2324: storebyte(dstaddr, outdata);
2325: PC+= 4;
2326: }
2327:
2328: void cpu_op_865b(t_ipc *ipc) /* SUB */ {
2329: /* mask fff8, bits 5128, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 5, sbitpos 0, dbitpos 0, immvalue 8 */
2330: unsigned int srcdata = 8;
2331: int dstreg = (ipc->opcode >> 0) & 7;
2332: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2333: uint8 dstdata = fetchbyte(dstaddr);
2334: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2335:
2336: storebyte(dstaddr, outdata);
2337:
2338: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
2339: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2340: XFLAG = CFLAG = srcdata > dstdata;
2341: NFLAG = ((sint8)outdata) < 0;
2342: ZFLAG = !outdata;
2343: PC+= 4;
2344: }
2345:
2346: void cpu_op_866a(t_ipc *ipc) /* SUB */ {
2347: /* mask fff8, bits 5130, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 6, sbitpos 0, dbitpos 0, immvalue 8 */
2348: unsigned int srcdata = 8;
2349: int dstreg = (ipc->opcode >> 0) & 7;
2350: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2351: uint8 dstdata = fetchbyte(dstaddr);
2352: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2353:
2354: storebyte(dstaddr, outdata);
2355: PC+= 4;
2356: }
2357:
2358: void cpu_op_866b(t_ipc *ipc) /* SUB */ {
2359: /* mask fff8, bits 5130, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 6, sbitpos 0, dbitpos 0, immvalue 8 */
2360: unsigned int srcdata = 8;
2361: int dstreg = (ipc->opcode >> 0) & 7;
2362: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2363: uint8 dstdata = fetchbyte(dstaddr);
2364: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2365:
2366: storebyte(dstaddr, outdata);
2367:
2368: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
2369: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2370: XFLAG = CFLAG = srcdata > dstdata;
2371: NFLAG = ((sint8)outdata) < 0;
2372: ZFLAG = !outdata;
2373: PC+= 4;
2374: }
2375:
2376: void cpu_op_867a(t_ipc *ipc) /* SUB */ {
2377: /* mask ffff, bits 5138, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 7, sbitpos 0, dbitpos 0, immvalue 8 */
2378: unsigned int srcdata = 8;
2379: uint32 dstaddr = ipc->dst;
2380: uint8 dstdata = fetchbyte(dstaddr);
2381: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2382:
2383: storebyte(dstaddr, outdata);
2384: PC+= 4;
2385: }
2386:
2387: void cpu_op_867b(t_ipc *ipc) /* SUB */ {
2388: /* mask ffff, bits 5138, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 7, sbitpos 0, dbitpos 0, immvalue 8 */
2389: unsigned int srcdata = 8;
2390: uint32 dstaddr = ipc->dst;
2391: uint8 dstdata = fetchbyte(dstaddr);
2392: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2393:
2394: storebyte(dstaddr, outdata);
2395:
2396: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
2397: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2398: XFLAG = CFLAG = srcdata > dstdata;
2399: NFLAG = ((sint8)outdata) < 0;
2400: ZFLAG = !outdata;
2401: PC+= 4;
2402: }
2403:
2404: void cpu_op_868a(t_ipc *ipc) /* SUB */ {
2405: /* mask ffff, bits 5139, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 8, sbitpos 0, dbitpos 0, immvalue 8 */
2406: unsigned int srcdata = 8;
2407: uint32 dstaddr = ipc->dst;
2408: uint8 dstdata = fetchbyte(dstaddr);
2409: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2410:
2411: storebyte(dstaddr, outdata);
2412: PC+= 6;
2413: }
2414:
2415: void cpu_op_868b(t_ipc *ipc) /* SUB */ {
2416: /* mask ffff, bits 5139, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 14, dtype 8, sbitpos 0, dbitpos 0, immvalue 8 */
2417: unsigned int srcdata = 8;
2418: uint32 dstaddr = ipc->dst;
2419: uint8 dstdata = fetchbyte(dstaddr);
2420: uint8 outdata = (sint8)dstdata - (sint8)srcdata;
2421:
2422: storebyte(dstaddr, outdata);
2423:
2424: VFLAG = (((sint8)srcdata < 0) != ((sint8)dstdata < 0)) &&
2425: (((sint8)dstdata < 0) != ((sint8)outdata < 0));
2426: XFLAG = CFLAG = srcdata > dstdata;
2427: NFLAG = ((sint8)outdata) < 0;
2428: ZFLAG = !outdata;
2429: PC+= 6;
2430: }
2431:
2432: void cpu_op_869a(t_ipc *ipc) /* SUB */ {
2433: /* mask fff8, bits 5140, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 0, sbitpos 0, dbitpos 0, immvalue 8 */
2434: unsigned int srcdata = 8;
2435: int dstreg = (ipc->opcode >> 0) & 7;
2436: uint16 dstdata = DATAREG(dstreg);
2437: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2438:
2439: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
2440: PC+= 2;
2441: }
2442:
2443: void cpu_op_869b(t_ipc *ipc) /* SUB */ {
2444: /* mask fff8, bits 5140, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 0, sbitpos 0, dbitpos 0, immvalue 8 */
2445: unsigned int srcdata = 8;
2446: int dstreg = (ipc->opcode >> 0) & 7;
2447: uint16 dstdata = DATAREG(dstreg);
2448: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2449:
2450: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata;
2451:
2452: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
2453: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2454: XFLAG = CFLAG = srcdata > dstdata;
2455: NFLAG = ((sint16)outdata) < 0;
2456: ZFLAG = !outdata;
2457: PC+= 2;
2458: }
2459:
2460: void cpu_op_870a(t_ipc *ipc) /* SUB */ {
2461: /* mask fff8, bits 5150, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 2, sbitpos 0, dbitpos 0, immvalue 8 */
2462: unsigned int srcdata = 8;
2463: int dstreg = (ipc->opcode >> 0) & 7;
2464: uint32 dstaddr = ADDRREG(dstreg);
2465: uint16 dstdata = fetchword(dstaddr);
2466: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2467:
2468: storeword(dstaddr, outdata);
2469: PC+= 2;
2470: }
2471:
2472: void cpu_op_870b(t_ipc *ipc) /* SUB */ {
2473: /* mask fff8, bits 5150, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 2, sbitpos 0, dbitpos 0, immvalue 8 */
2474: unsigned int srcdata = 8;
2475: int dstreg = (ipc->opcode >> 0) & 7;
2476: uint32 dstaddr = ADDRREG(dstreg);
2477: uint16 dstdata = fetchword(dstaddr);
2478: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2479:
2480: storeword(dstaddr, outdata);
2481:
2482: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
2483: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2484: XFLAG = CFLAG = srcdata > dstdata;
2485: NFLAG = ((sint16)outdata) < 0;
2486: ZFLAG = !outdata;
2487: PC+= 2;
2488: }
2489:
2490: void cpu_op_871a(t_ipc *ipc) /* SUB */ {
2491: /* mask fff8, bits 5158, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 3, sbitpos 0, dbitpos 0, immvalue 8 */
2492: unsigned int srcdata = 8;
2493: int dstreg = (ipc->opcode >> 0) & 7;
2494: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
2495: uint16 dstdata = fetchword(dstaddr);
2496: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2497:
2498: storeword(dstaddr, outdata);
2499: PC+= 2;
2500: }
2501:
2502: void cpu_op_871b(t_ipc *ipc) /* SUB */ {
2503: /* mask fff8, bits 5158, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 3, sbitpos 0, dbitpos 0, immvalue 8 */
2504: unsigned int srcdata = 8;
2505: int dstreg = (ipc->opcode >> 0) & 7;
2506: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2);
2507: uint16 dstdata = fetchword(dstaddr);
2508: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2509:
2510: storeword(dstaddr, outdata);
2511:
2512: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
2513: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2514: XFLAG = CFLAG = srcdata > dstdata;
2515: NFLAG = ((sint16)outdata) < 0;
2516: ZFLAG = !outdata;
2517: PC+= 2;
2518: }
2519:
2520: void cpu_op_872a(t_ipc *ipc) /* SUB */ {
2521: /* mask fff8, bits 5160, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 4, sbitpos 0, dbitpos 0, immvalue 8 */
2522: unsigned int srcdata = 8;
2523: int dstreg = (ipc->opcode >> 0) & 7;
2524: uint32 dstaddr = ADDRREG(dstreg)-=2;
2525: uint16 dstdata = fetchword(dstaddr);
2526: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2527:
2528: storeword(dstaddr, outdata);
2529: PC+= 2;
2530: }
2531:
2532: void cpu_op_872b(t_ipc *ipc) /* SUB */ {
2533: /* mask fff8, bits 5160, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 4, sbitpos 0, dbitpos 0, immvalue 8 */
2534: unsigned int srcdata = 8;
2535: int dstreg = (ipc->opcode >> 0) & 7;
2536: uint32 dstaddr = ADDRREG(dstreg)-=2;
2537: uint16 dstdata = fetchword(dstaddr);
2538: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2539:
2540: storeword(dstaddr, outdata);
2541:
2542: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
2543: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2544: XFLAG = CFLAG = srcdata > dstdata;
2545: NFLAG = ((sint16)outdata) < 0;
2546: ZFLAG = !outdata;
2547: PC+= 2;
2548: }
2549:
2550: void cpu_op_873a(t_ipc *ipc) /* SUB */ {
2551: /* mask fff8, bits 5168, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 5, sbitpos 0, dbitpos 0, immvalue 8 */
2552: unsigned int srcdata = 8;
2553: int dstreg = (ipc->opcode >> 0) & 7;
2554: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2555: uint16 dstdata = fetchword(dstaddr);
2556: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2557:
2558: storeword(dstaddr, outdata);
2559: PC+= 4;
2560: }
2561:
2562: void cpu_op_873b(t_ipc *ipc) /* SUB */ {
2563: /* mask fff8, bits 5168, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 5, sbitpos 0, dbitpos 0, immvalue 8 */
2564: unsigned int srcdata = 8;
2565: int dstreg = (ipc->opcode >> 0) & 7;
2566: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2567: uint16 dstdata = fetchword(dstaddr);
2568: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2569:
2570: storeword(dstaddr, outdata);
2571:
2572: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
2573: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2574: XFLAG = CFLAG = srcdata > dstdata;
2575: NFLAG = ((sint16)outdata) < 0;
2576: ZFLAG = !outdata;
2577: PC+= 4;
2578: }
2579:
2580: void cpu_op_874a(t_ipc *ipc) /* SUB */ {
2581: /* mask fff8, bits 5170, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 6, sbitpos 0, dbitpos 0, immvalue 8 */
2582: unsigned int srcdata = 8;
2583: int dstreg = (ipc->opcode >> 0) & 7;
2584: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2585: uint16 dstdata = fetchword(dstaddr);
2586: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2587:
2588: storeword(dstaddr, outdata);
2589: PC+= 4;
2590: }
2591:
2592: void cpu_op_874b(t_ipc *ipc) /* SUB */ {
2593: /* mask fff8, bits 5170, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 6, sbitpos 0, dbitpos 0, immvalue 8 */
2594: unsigned int srcdata = 8;
2595: int dstreg = (ipc->opcode >> 0) & 7;
2596: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2597: uint16 dstdata = fetchword(dstaddr);
2598: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2599:
2600: storeword(dstaddr, outdata);
2601:
2602: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
2603: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2604: XFLAG = CFLAG = srcdata > dstdata;
2605: NFLAG = ((sint16)outdata) < 0;
2606: ZFLAG = !outdata;
2607: PC+= 4;
2608: }
2609:
2610: void cpu_op_875a(t_ipc *ipc) /* SUB */ {
2611: /* mask ffff, bits 5178, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 7, sbitpos 0, dbitpos 0, immvalue 8 */
2612: unsigned int srcdata = 8;
2613: uint32 dstaddr = ipc->dst;
2614: uint16 dstdata = fetchword(dstaddr);
2615: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2616:
2617: storeword(dstaddr, outdata);
2618: PC+= 4;
2619: }
2620:
2621: void cpu_op_875b(t_ipc *ipc) /* SUB */ {
2622: /* mask ffff, bits 5178, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 7, sbitpos 0, dbitpos 0, immvalue 8 */
2623: unsigned int srcdata = 8;
2624: uint32 dstaddr = ipc->dst;
2625: uint16 dstdata = fetchword(dstaddr);
2626: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2627:
2628: storeword(dstaddr, outdata);
2629:
2630: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
2631: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2632: XFLAG = CFLAG = srcdata > dstdata;
2633: NFLAG = ((sint16)outdata) < 0;
2634: ZFLAG = !outdata;
2635: PC+= 4;
2636: }
2637:
2638: void cpu_op_876a(t_ipc *ipc) /* SUB */ {
2639: /* mask ffff, bits 5179, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 8, sbitpos 0, dbitpos 0, immvalue 8 */
2640: unsigned int srcdata = 8;
2641: uint32 dstaddr = ipc->dst;
2642: uint16 dstdata = fetchword(dstaddr);
2643: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2644:
2645: storeword(dstaddr, outdata);
2646: PC+= 6;
2647: }
2648:
2649: void cpu_op_876b(t_ipc *ipc) /* SUB */ {
2650: /* mask ffff, bits 5179, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 14, dtype 8, sbitpos 0, dbitpos 0, immvalue 8 */
2651: unsigned int srcdata = 8;
2652: uint32 dstaddr = ipc->dst;
2653: uint16 dstdata = fetchword(dstaddr);
2654: uint16 outdata = (sint16)dstdata - (sint16)srcdata;
2655:
2656: storeword(dstaddr, outdata);
2657:
2658: VFLAG = (((sint16)srcdata < 0) != ((sint16)dstdata < 0)) &&
2659: (((sint16)dstdata < 0) != ((sint16)outdata < 0));
2660: XFLAG = CFLAG = srcdata > dstdata;
2661: NFLAG = ((sint16)outdata) < 0;
2662: ZFLAG = !outdata;
2663: PC+= 6;
2664: }
2665:
2666: void cpu_op_877a(t_ipc *ipc) /* SUB */ {
2667: /* mask fff8, bits 5180, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 0, sbitpos 0, dbitpos 0, immvalue 8 */
2668: unsigned int srcdata = 8;
2669: int dstreg = (ipc->opcode >> 0) & 7;
2670: uint32 dstdata = DATAREG(dstreg);
2671: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2672:
2673: DATAREG(dstreg) = outdata;
2674: PC+= 2;
2675: }
2676:
2677: void cpu_op_877b(t_ipc *ipc) /* SUB */ {
2678: /* mask fff8, bits 5180, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 0, sbitpos 0, dbitpos 0, immvalue 8 */
2679: unsigned int srcdata = 8;
2680: int dstreg = (ipc->opcode >> 0) & 7;
2681: uint32 dstdata = DATAREG(dstreg);
2682: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2683:
2684: DATAREG(dstreg) = outdata;
2685:
2686: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2687: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2688: XFLAG = CFLAG = srcdata > dstdata;
2689: NFLAG = ((sint32)outdata) < 0;
2690: ZFLAG = !outdata;
2691: PC+= 2;
2692: }
2693:
2694: void cpu_op_878a(t_ipc *ipc) /* SUB */ {
2695: /* mask fff8, bits 5190, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 2, sbitpos 0, dbitpos 0, immvalue 8 */
2696: unsigned int srcdata = 8;
2697: int dstreg = (ipc->opcode >> 0) & 7;
2698: uint32 dstaddr = ADDRREG(dstreg);
2699: uint32 dstdata = fetchlong(dstaddr);
2700: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2701:
2702: storelong(dstaddr, outdata);
2703: PC+= 2;
2704: }
2705:
2706: void cpu_op_878b(t_ipc *ipc) /* SUB */ {
2707: /* mask fff8, bits 5190, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 2, sbitpos 0, dbitpos 0, immvalue 8 */
2708: unsigned int srcdata = 8;
2709: int dstreg = (ipc->opcode >> 0) & 7;
2710: uint32 dstaddr = ADDRREG(dstreg);
2711: uint32 dstdata = fetchlong(dstaddr);
2712: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2713:
2714: storelong(dstaddr, outdata);
2715:
2716: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2717: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2718: XFLAG = CFLAG = srcdata > dstdata;
2719: NFLAG = ((sint32)outdata) < 0;
2720: ZFLAG = !outdata;
2721: PC+= 2;
2722: }
2723:
2724: void cpu_op_879a(t_ipc *ipc) /* SUB */ {
2725: /* mask fff8, bits 5198, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 3, sbitpos 0, dbitpos 0, immvalue 8 */
2726: unsigned int srcdata = 8;
2727: int dstreg = (ipc->opcode >> 0) & 7;
2728: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
2729: uint32 dstdata = fetchlong(dstaddr);
2730: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2731:
2732: storelong(dstaddr, outdata);
2733: PC+= 2;
2734: }
2735:
2736: void cpu_op_879b(t_ipc *ipc) /* SUB */ {
2737: /* mask fff8, bits 5198, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 3, sbitpos 0, dbitpos 0, immvalue 8 */
2738: unsigned int srcdata = 8;
2739: int dstreg = (ipc->opcode >> 0) & 7;
2740: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4);
2741: uint32 dstdata = fetchlong(dstaddr);
2742: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2743:
2744: storelong(dstaddr, outdata);
2745:
2746: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2747: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2748: XFLAG = CFLAG = srcdata > dstdata;
2749: NFLAG = ((sint32)outdata) < 0;
2750: ZFLAG = !outdata;
2751: PC+= 2;
2752: }
2753:
2754: void cpu_op_880a(t_ipc *ipc) /* SUB */ {
2755: /* mask fff8, bits 51a0, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 4, sbitpos 0, dbitpos 0, immvalue 8 */
2756: unsigned int srcdata = 8;
2757: int dstreg = (ipc->opcode >> 0) & 7;
2758: uint32 dstaddr = ADDRREG(dstreg)-=4;
2759: uint32 dstdata = fetchlong(dstaddr);
2760: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2761:
2762: storelong(dstaddr, outdata);
2763: PC+= 2;
2764: }
2765:
2766: void cpu_op_880b(t_ipc *ipc) /* SUB */ {
2767: /* mask fff8, bits 51a0, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 4, sbitpos 0, dbitpos 0, immvalue 8 */
2768: unsigned int srcdata = 8;
2769: int dstreg = (ipc->opcode >> 0) & 7;
2770: uint32 dstaddr = ADDRREG(dstreg)-=4;
2771: uint32 dstdata = fetchlong(dstaddr);
2772: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2773:
2774: storelong(dstaddr, outdata);
2775:
2776: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2777: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2778: XFLAG = CFLAG = srcdata > dstdata;
2779: NFLAG = ((sint32)outdata) < 0;
2780: ZFLAG = !outdata;
2781: PC+= 2;
2782: }
2783:
2784: void cpu_op_881a(t_ipc *ipc) /* SUB */ {
2785: /* mask fff8, bits 51a8, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 5, sbitpos 0, dbitpos 0, immvalue 8 */
2786: unsigned int srcdata = 8;
2787: int dstreg = (ipc->opcode >> 0) & 7;
2788: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2789: uint32 dstdata = fetchlong(dstaddr);
2790: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2791:
2792: storelong(dstaddr, outdata);
2793: PC+= 4;
2794: }
2795:
2796: void cpu_op_881b(t_ipc *ipc) /* SUB */ {
2797: /* mask fff8, bits 51a8, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 5, sbitpos 0, dbitpos 0, immvalue 8 */
2798: unsigned int srcdata = 8;
2799: int dstreg = (ipc->opcode >> 0) & 7;
2800: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst;
2801: uint32 dstdata = fetchlong(dstaddr);
2802: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2803:
2804: storelong(dstaddr, outdata);
2805:
2806: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2807: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2808: XFLAG = CFLAG = srcdata > dstdata;
2809: NFLAG = ((sint32)outdata) < 0;
2810: ZFLAG = !outdata;
2811: PC+= 4;
2812: }
2813:
2814: void cpu_op_882a(t_ipc *ipc) /* SUB */ {
2815: /* mask fff8, bits 51b0, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 6, sbitpos 0, dbitpos 0, immvalue 8 */
2816: unsigned int srcdata = 8;
2817: int dstreg = (ipc->opcode >> 0) & 7;
2818: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2819: uint32 dstdata = fetchlong(dstaddr);
2820: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2821:
2822: storelong(dstaddr, outdata);
2823: PC+= 4;
2824: }
2825:
2826: void cpu_op_882b(t_ipc *ipc) /* SUB */ {
2827: /* mask fff8, bits 51b0, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 6, sbitpos 0, dbitpos 0, immvalue 8 */
2828: unsigned int srcdata = 8;
2829: int dstreg = (ipc->opcode >> 0) & 7;
2830: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc);
2831: uint32 dstdata = fetchlong(dstaddr);
2832: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2833:
2834: storelong(dstaddr, outdata);
2835:
2836: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2837: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2838: XFLAG = CFLAG = srcdata > dstdata;
2839: NFLAG = ((sint32)outdata) < 0;
2840: ZFLAG = !outdata;
2841: PC+= 4;
2842: }
2843:
2844: void cpu_op_883a(t_ipc *ipc) /* SUB */ {
2845: /* mask ffff, bits 51b8, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 7, sbitpos 0, dbitpos 0, immvalue 8 */
2846: unsigned int srcdata = 8;
2847: uint32 dstaddr = ipc->dst;
2848: uint32 dstdata = fetchlong(dstaddr);
2849: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2850:
2851: storelong(dstaddr, outdata);
2852: PC+= 4;
2853: }
2854:
2855: void cpu_op_883b(t_ipc *ipc) /* SUB */ {
2856: /* mask ffff, bits 51b8, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 7, sbitpos 0, dbitpos 0, immvalue 8 */
2857: unsigned int srcdata = 8;
2858: uint32 dstaddr = ipc->dst;
2859: uint32 dstdata = fetchlong(dstaddr);
2860: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2861:
2862: storelong(dstaddr, outdata);
2863:
2864: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2865: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2866: XFLAG = CFLAG = srcdata > dstdata;
2867: NFLAG = ((sint32)outdata) < 0;
2868: ZFLAG = !outdata;
2869: PC+= 4;
2870: }
2871:
2872: void cpu_op_884a(t_ipc *ipc) /* SUB */ {
2873: /* mask ffff, bits 51b9, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 8, sbitpos 0, dbitpos 0, immvalue 8 */
2874: unsigned int srcdata = 8;
2875: uint32 dstaddr = ipc->dst;
2876: uint32 dstdata = fetchlong(dstaddr);
2877: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2878:
2879: storelong(dstaddr, outdata);
2880: PC+= 6;
2881: }
2882:
2883: void cpu_op_884b(t_ipc *ipc) /* SUB */ {
2884: /* mask ffff, bits 51b9, mnemonic 7, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 14, dtype 8, sbitpos 0, dbitpos 0, immvalue 8 */
2885: unsigned int srcdata = 8;
2886: uint32 dstaddr = ipc->dst;
2887: uint32 dstdata = fetchlong(dstaddr);
2888: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2889:
2890: storelong(dstaddr, outdata);
2891:
2892: VFLAG = (((sint32)srcdata < 0) != ((sint32)dstdata < 0)) &&
2893: (((sint32)dstdata < 0) != ((sint32)outdata < 0));
2894: XFLAG = CFLAG = srcdata > dstdata;
2895: NFLAG = ((sint32)outdata) < 0;
2896: ZFLAG = !outdata;
2897: PC+= 6;
2898: }
2899:
2900: void cpu_op_885a(t_ipc *ipc) /* SUBA */ {
2901: /* mask fff8, bits 5148, mnemonic 8, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 14, dtype 1, sbitpos 0, dbitpos 0, immvalue 8 */
2902: unsigned int srcdata = 8;
2903: int dstreg = (ipc->opcode >> 0) & 7;
2904: uint32 dstdata = ADDRREG(dstreg);
2905: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2906:
2907: ADDRREG(dstreg) = outdata;
2908: PC+= 2;
2909: }
2910:
2911: void cpu_op_886a(t_ipc *ipc) /* SUBA */ {
2912: /* mask fff8, bits 5188, mnemonic 8, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 14, dtype 1, sbitpos 0, dbitpos 0, immvalue 8 */
2913: unsigned int srcdata = 8;
2914: int dstreg = (ipc->opcode >> 0) & 7;
2915: uint32 dstdata = ADDRREG(dstreg);
2916: uint32 outdata = (sint32)dstdata - (sint32)srcdata;
2917:
2918: ADDRREG(dstreg) = outdata;
2919: PC+= 2;
2920: }
2921:
2922: void cpu_op_887a(t_ipc *ipc) /* Scc */ {
2923: /* mask fff8, bits 50c0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2924: int srcreg = (ipc->opcode >> 0) & 7;
2925: uint8 cc = 1;
2926: uint8 outdata = cc ? (uint8)(-1) : 0;
2927:
2928: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
2929: PC+= 2;
2930: }
2931:
2932: void cpu_op_888a(t_ipc *ipc) /* Scc */ {
2933: /* mask fff8, bits 52c0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2934: int srcreg = (ipc->opcode >> 0) & 7;
2935: uint8 cc = !(CFLAG || ZFLAG);
2936: uint8 outdata = cc ? (uint8)(-1) : 0;
2937:
2938: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
2939: PC+= 2;
2940: }
2941:
2942: void cpu_op_889a(t_ipc *ipc) /* Scc */ {
2943: /* mask fff8, bits 53c0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2944: int srcreg = (ipc->opcode >> 0) & 7;
2945: uint8 cc = CFLAG || ZFLAG;
2946: uint8 outdata = cc ? (uint8)(-1) : 0;
2947:
2948: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
2949: PC+= 2;
2950: }
2951:
2952: void cpu_op_890a(t_ipc *ipc) /* Scc */ {
2953: /* mask fff8, bits 54c0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2954: int srcreg = (ipc->opcode >> 0) & 7;
2955: uint8 cc = !CFLAG;
2956: uint8 outdata = cc ? (uint8)(-1) : 0;
2957:
2958: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
2959: PC+= 2;
2960: }
2961:
2962: void cpu_op_891a(t_ipc *ipc) /* Scc */ {
2963: /* mask fff8, bits 55c0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2964: int srcreg = (ipc->opcode >> 0) & 7;
2965: uint8 cc = CFLAG;
2966: uint8 outdata = cc ? (uint8)(-1) : 0;
2967:
2968: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
2969: PC+= 2;
2970: }
2971:
2972: void cpu_op_892a(t_ipc *ipc) /* Scc */ {
2973: /* mask fff8, bits 56c0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2974: int srcreg = (ipc->opcode >> 0) & 7;
2975: uint8 cc = !ZFLAG;
2976: uint8 outdata = cc ? (uint8)(-1) : 0;
2977:
2978: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
2979: PC+= 2;
2980: }
2981:
2982: void cpu_op_893a(t_ipc *ipc) /* Scc */ {
2983: /* mask fff8, bits 57c0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2984: int srcreg = (ipc->opcode >> 0) & 7;
2985: uint8 cc = ZFLAG;
2986: uint8 outdata = cc ? (uint8)(-1) : 0;
2987:
2988: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
2989: PC+= 2;
2990: }
2991:
2992: void cpu_op_894a(t_ipc *ipc) /* Scc */ {
2993: /* mask fff8, bits 58c0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
2994: int srcreg = (ipc->opcode >> 0) & 7;
2995: uint8 cc = !VFLAG;
2996: uint8 outdata = cc ? (uint8)(-1) : 0;
2997:
2998: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
2999: PC+= 2;
3000: }
3001:
3002: void cpu_op_895a(t_ipc *ipc) /* Scc */ {
3003: /* mask fff8, bits 59c0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3004: int srcreg = (ipc->opcode >> 0) & 7;
3005: uint8 cc = VFLAG;
3006: uint8 outdata = cc ? (uint8)(-1) : 0;
3007:
3008: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
3009: PC+= 2;
3010: }
3011:
3012: void cpu_op_896a(t_ipc *ipc) /* Scc */ {
3013: /* mask fff8, bits 5ac0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3014: int srcreg = (ipc->opcode >> 0) & 7;
3015: uint8 cc = !NFLAG;
3016: uint8 outdata = cc ? (uint8)(-1) : 0;
3017:
3018: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
3019: PC+= 2;
3020: }
3021:
3022: void cpu_op_897a(t_ipc *ipc) /* Scc */ {
3023: /* mask fff8, bits 5bc0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3024: int srcreg = (ipc->opcode >> 0) & 7;
3025: uint8 cc = NFLAG;
3026: uint8 outdata = cc ? (uint8)(-1) : 0;
3027:
3028: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
3029: PC+= 2;
3030: }
3031:
3032: void cpu_op_898a(t_ipc *ipc) /* Scc */ {
3033: /* mask fff8, bits 5cc0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3034: int srcreg = (ipc->opcode >> 0) & 7;
3035: uint8 cc = (NFLAG == VFLAG);
3036: uint8 outdata = cc ? (uint8)(-1) : 0;
3037:
3038: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
3039: PC+= 2;
3040: }
3041:
3042: void cpu_op_899a(t_ipc *ipc) /* Scc */ {
3043: /* mask fff8, bits 5dc0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3044: int srcreg = (ipc->opcode >> 0) & 7;
3045: uint8 cc = (NFLAG != VFLAG);
3046: uint8 outdata = cc ? (uint8)(-1) : 0;
3047:
3048: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
3049: PC+= 2;
3050: }
3051:
3052: void cpu_op_900a(t_ipc *ipc) /* Scc */ {
3053: /* mask fff8, bits 5ec0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3054: int srcreg = (ipc->opcode >> 0) & 7;
3055: uint8 cc = !ZFLAG && (NFLAG == VFLAG);
3056: uint8 outdata = cc ? (uint8)(-1) : 0;
3057:
3058: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
3059: PC+= 2;
3060: }
3061:
3062: void cpu_op_901a(t_ipc *ipc) /* Scc */ {
3063: /* mask fff8, bits 5fc0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3064: int srcreg = (ipc->opcode >> 0) & 7;
3065: uint8 cc = ZFLAG || (NFLAG != VFLAG);
3066: uint8 outdata = cc ? (uint8)(-1) : 0;
3067:
3068: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
3069: PC+= 2;
3070: }
3071:
3072: void cpu_op_902a(t_ipc *ipc) /* Scc */ {
3073: /* mask fff8, bits 50d0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3074: int srcreg = (ipc->opcode >> 0) & 7;
3075: uint32 srcaddr = ADDRREG(srcreg);
3076: uint8 cc = 1;
3077: uint8 outdata = cc ? (uint8)(-1) : 0;
3078:
3079: storebyte(srcaddr, outdata);
3080: PC+= 2;
3081: }
3082:
3083: void cpu_op_903a(t_ipc *ipc) /* Scc */ {
3084: /* mask fff8, bits 52d0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3085: int srcreg = (ipc->opcode >> 0) & 7;
3086: uint32 srcaddr = ADDRREG(srcreg);
3087: uint8 cc = !(CFLAG || ZFLAG);
3088: uint8 outdata = cc ? (uint8)(-1) : 0;
3089:
3090: storebyte(srcaddr, outdata);
3091: PC+= 2;
3092: }
3093:
3094: void cpu_op_904a(t_ipc *ipc) /* Scc */ {
3095: /* mask fff8, bits 53d0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3096: int srcreg = (ipc->opcode >> 0) & 7;
3097: uint32 srcaddr = ADDRREG(srcreg);
3098: uint8 cc = CFLAG || ZFLAG;
3099: uint8 outdata = cc ? (uint8)(-1) : 0;
3100:
3101: storebyte(srcaddr, outdata);
3102: PC+= 2;
3103: }
3104:
3105: void cpu_op_905a(t_ipc *ipc) /* Scc */ {
3106: /* mask fff8, bits 54d0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3107: int srcreg = (ipc->opcode >> 0) & 7;
3108: uint32 srcaddr = ADDRREG(srcreg);
3109: uint8 cc = !CFLAG;
3110: uint8 outdata = cc ? (uint8)(-1) : 0;
3111:
3112: storebyte(srcaddr, outdata);
3113: PC+= 2;
3114: }
3115:
3116: void cpu_op_906a(t_ipc *ipc) /* Scc */ {
3117: /* mask fff8, bits 55d0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3118: int srcreg = (ipc->opcode >> 0) & 7;
3119: uint32 srcaddr = ADDRREG(srcreg);
3120: uint8 cc = CFLAG;
3121: uint8 outdata = cc ? (uint8)(-1) : 0;
3122:
3123: storebyte(srcaddr, outdata);
3124: PC+= 2;
3125: }
3126:
3127: void cpu_op_907a(t_ipc *ipc) /* Scc */ {
3128: /* mask fff8, bits 56d0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3129: int srcreg = (ipc->opcode >> 0) & 7;
3130: uint32 srcaddr = ADDRREG(srcreg);
3131: uint8 cc = !ZFLAG;
3132: uint8 outdata = cc ? (uint8)(-1) : 0;
3133:
3134: storebyte(srcaddr, outdata);
3135: PC+= 2;
3136: }
3137:
3138: void cpu_op_908a(t_ipc *ipc) /* Scc */ {
3139: /* mask fff8, bits 57d0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3140: int srcreg = (ipc->opcode >> 0) & 7;
3141: uint32 srcaddr = ADDRREG(srcreg);
3142: uint8 cc = ZFLAG;
3143: uint8 outdata = cc ? (uint8)(-1) : 0;
3144:
3145: storebyte(srcaddr, outdata);
3146: PC+= 2;
3147: }
3148:
3149: void cpu_op_909a(t_ipc *ipc) /* Scc */ {
3150: /* mask fff8, bits 58d0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3151: int srcreg = (ipc->opcode >> 0) & 7;
3152: uint32 srcaddr = ADDRREG(srcreg);
3153: uint8 cc = !VFLAG;
3154: uint8 outdata = cc ? (uint8)(-1) : 0;
3155:
3156: storebyte(srcaddr, outdata);
3157: PC+= 2;
3158: }
3159:
3160: void cpu_op_910a(t_ipc *ipc) /* Scc */ {
3161: /* mask fff8, bits 59d0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3162: int srcreg = (ipc->opcode >> 0) & 7;
3163: uint32 srcaddr = ADDRREG(srcreg);
3164: uint8 cc = VFLAG;
3165: uint8 outdata = cc ? (uint8)(-1) : 0;
3166:
3167: storebyte(srcaddr, outdata);
3168: PC+= 2;
3169: }
3170:
3171: void cpu_op_911a(t_ipc *ipc) /* Scc */ {
3172: /* mask fff8, bits 5ad0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3173: int srcreg = (ipc->opcode >> 0) & 7;
3174: uint32 srcaddr = ADDRREG(srcreg);
3175: uint8 cc = !NFLAG;
3176: uint8 outdata = cc ? (uint8)(-1) : 0;
3177:
3178: storebyte(srcaddr, outdata);
3179: PC+= 2;
3180: }
3181:
3182: void cpu_op_912a(t_ipc *ipc) /* Scc */ {
3183: /* mask fff8, bits 5bd0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3184: int srcreg = (ipc->opcode >> 0) & 7;
3185: uint32 srcaddr = ADDRREG(srcreg);
3186: uint8 cc = NFLAG;
3187: uint8 outdata = cc ? (uint8)(-1) : 0;
3188:
3189: storebyte(srcaddr, outdata);
3190: PC+= 2;
3191: }
3192:
3193: void cpu_op_913a(t_ipc *ipc) /* Scc */ {
3194: /* mask fff8, bits 5cd0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3195: int srcreg = (ipc->opcode >> 0) & 7;
3196: uint32 srcaddr = ADDRREG(srcreg);
3197: uint8 cc = (NFLAG == VFLAG);
3198: uint8 outdata = cc ? (uint8)(-1) : 0;
3199:
3200: storebyte(srcaddr, outdata);
3201: PC+= 2;
3202: }
3203:
3204: void cpu_op_914a(t_ipc *ipc) /* Scc */ {
3205: /* mask fff8, bits 5dd0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3206: int srcreg = (ipc->opcode >> 0) & 7;
3207: uint32 srcaddr = ADDRREG(srcreg);
3208: uint8 cc = (NFLAG != VFLAG);
3209: uint8 outdata = cc ? (uint8)(-1) : 0;
3210:
3211: storebyte(srcaddr, outdata);
3212: PC+= 2;
3213: }
3214:
3215: void cpu_op_915a(t_ipc *ipc) /* Scc */ {
3216: /* mask fff8, bits 5ed0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3217: int srcreg = (ipc->opcode >> 0) & 7;
3218: uint32 srcaddr = ADDRREG(srcreg);
3219: uint8 cc = !ZFLAG && (NFLAG == VFLAG);
3220: uint8 outdata = cc ? (uint8)(-1) : 0;
3221:
3222: storebyte(srcaddr, outdata);
3223: PC+= 2;
3224: }
3225:
3226: void cpu_op_916a(t_ipc *ipc) /* Scc */ {
3227: /* mask fff8, bits 5fd0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3228: int srcreg = (ipc->opcode >> 0) & 7;
3229: uint32 srcaddr = ADDRREG(srcreg);
3230: uint8 cc = ZFLAG || (NFLAG != VFLAG);
3231: uint8 outdata = cc ? (uint8)(-1) : 0;
3232:
3233: storebyte(srcaddr, outdata);
3234: PC+= 2;
3235: }
3236:
3237: void cpu_op_917a(t_ipc *ipc) /* Scc */ {
3238: /* mask fff8, bits 50d8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3239: int srcreg = (ipc->opcode >> 0) & 7;
3240: uint32 srcaddr = ADDRREG(srcreg);
3241: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3242: uint8 cc = 1;
3243: uint8 outdata = cc ? (uint8)(-1) : 0;
3244:
3245: storebyte(srcaddr, outdata);
3246: PC+= 2;
3247: }
3248:
3249: void cpu_op_918a(t_ipc *ipc) /* Scc */ {
3250: /* mask fff8, bits 52d8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3251: int srcreg = (ipc->opcode >> 0) & 7;
3252: uint32 srcaddr = ADDRREG(srcreg);
3253: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3254: uint8 cc = !(CFLAG || ZFLAG);
3255: uint8 outdata = cc ? (uint8)(-1) : 0;
3256:
3257: storebyte(srcaddr, outdata);
3258: PC+= 2;
3259: }
3260:
3261: void cpu_op_919a(t_ipc *ipc) /* Scc */ {
3262: /* mask fff8, bits 53d8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3263: int srcreg = (ipc->opcode >> 0) & 7;
3264: uint32 srcaddr = ADDRREG(srcreg);
3265: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3266: uint8 cc = CFLAG || ZFLAG;
3267: uint8 outdata = cc ? (uint8)(-1) : 0;
3268:
3269: storebyte(srcaddr, outdata);
3270: PC+= 2;
3271: }
3272:
3273: void cpu_op_920a(t_ipc *ipc) /* Scc */ {
3274: /* mask fff8, bits 54d8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3275: int srcreg = (ipc->opcode >> 0) & 7;
3276: uint32 srcaddr = ADDRREG(srcreg);
3277: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3278: uint8 cc = !CFLAG;
3279: uint8 outdata = cc ? (uint8)(-1) : 0;
3280:
3281: storebyte(srcaddr, outdata);
3282: PC+= 2;
3283: }
3284:
3285: void cpu_op_921a(t_ipc *ipc) /* Scc */ {
3286: /* mask fff8, bits 55d8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3287: int srcreg = (ipc->opcode >> 0) & 7;
3288: uint32 srcaddr = ADDRREG(srcreg);
3289: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3290: uint8 cc = CFLAG;
3291: uint8 outdata = cc ? (uint8)(-1) : 0;
3292:
3293: storebyte(srcaddr, outdata);
3294: PC+= 2;
3295: }
3296:
3297: void cpu_op_922a(t_ipc *ipc) /* Scc */ {
3298: /* mask fff8, bits 56d8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3299: int srcreg = (ipc->opcode >> 0) & 7;
3300: uint32 srcaddr = ADDRREG(srcreg);
3301: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3302: uint8 cc = !ZFLAG;
3303: uint8 outdata = cc ? (uint8)(-1) : 0;
3304:
3305: storebyte(srcaddr, outdata);
3306: PC+= 2;
3307: }
3308:
3309: void cpu_op_923a(t_ipc *ipc) /* Scc */ {
3310: /* mask fff8, bits 57d8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3311: int srcreg = (ipc->opcode >> 0) & 7;
3312: uint32 srcaddr = ADDRREG(srcreg);
3313: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3314: uint8 cc = ZFLAG;
3315: uint8 outdata = cc ? (uint8)(-1) : 0;
3316:
3317: storebyte(srcaddr, outdata);
3318: PC+= 2;
3319: }
3320:
3321: void cpu_op_924a(t_ipc *ipc) /* Scc */ {
3322: /* mask fff8, bits 58d8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3323: int srcreg = (ipc->opcode >> 0) & 7;
3324: uint32 srcaddr = ADDRREG(srcreg);
3325: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3326: uint8 cc = !VFLAG;
3327: uint8 outdata = cc ? (uint8)(-1) : 0;
3328:
3329: storebyte(srcaddr, outdata);
3330: PC+= 2;
3331: }
3332:
3333: void cpu_op_925a(t_ipc *ipc) /* Scc */ {
3334: /* mask fff8, bits 59d8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3335: int srcreg = (ipc->opcode >> 0) & 7;
3336: uint32 srcaddr = ADDRREG(srcreg);
3337: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3338: uint8 cc = VFLAG;
3339: uint8 outdata = cc ? (uint8)(-1) : 0;
3340:
3341: storebyte(srcaddr, outdata);
3342: PC+= 2;
3343: }
3344:
3345: void cpu_op_926a(t_ipc *ipc) /* Scc */ {
3346: /* mask fff8, bits 5ad8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3347: int srcreg = (ipc->opcode >> 0) & 7;
3348: uint32 srcaddr = ADDRREG(srcreg);
3349: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3350: uint8 cc = !NFLAG;
3351: uint8 outdata = cc ? (uint8)(-1) : 0;
3352:
3353: storebyte(srcaddr, outdata);
3354: PC+= 2;
3355: }
3356:
3357: void cpu_op_927a(t_ipc *ipc) /* Scc */ {
3358: /* mask fff8, bits 5bd8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3359: int srcreg = (ipc->opcode >> 0) & 7;
3360: uint32 srcaddr = ADDRREG(srcreg);
3361: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3362: uint8 cc = NFLAG;
3363: uint8 outdata = cc ? (uint8)(-1) : 0;
3364:
3365: storebyte(srcaddr, outdata);
3366: PC+= 2;
3367: }
3368:
3369: void cpu_op_928a(t_ipc *ipc) /* Scc */ {
3370: /* mask fff8, bits 5cd8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3371: int srcreg = (ipc->opcode >> 0) & 7;
3372: uint32 srcaddr = ADDRREG(srcreg);
3373: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3374: uint8 cc = (NFLAG == VFLAG);
3375: uint8 outdata = cc ? (uint8)(-1) : 0;
3376:
3377: storebyte(srcaddr, outdata);
3378: PC+= 2;
3379: }
3380:
3381: void cpu_op_929a(t_ipc *ipc) /* Scc */ {
3382: /* mask fff8, bits 5dd8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3383: int srcreg = (ipc->opcode >> 0) & 7;
3384: uint32 srcaddr = ADDRREG(srcreg);
3385: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3386: uint8 cc = (NFLAG != VFLAG);
3387: uint8 outdata = cc ? (uint8)(-1) : 0;
3388:
3389: storebyte(srcaddr, outdata);
3390: PC+= 2;
3391: }
3392:
3393: void cpu_op_930a(t_ipc *ipc) /* Scc */ {
3394: /* mask fff8, bits 5ed8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3395: int srcreg = (ipc->opcode >> 0) & 7;
3396: uint32 srcaddr = ADDRREG(srcreg);
3397: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3398: uint8 cc = !ZFLAG && (NFLAG == VFLAG);
3399: uint8 outdata = cc ? (uint8)(-1) : 0;
3400:
3401: storebyte(srcaddr, outdata);
3402: PC+= 2;
3403: }
3404:
3405: void cpu_op_931a(t_ipc *ipc) /* Scc */ {
3406: /* mask fff8, bits 5fd8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3407: int srcreg = (ipc->opcode >> 0) & 7;
3408: uint32 srcaddr = ADDRREG(srcreg);
3409: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
3410: uint8 cc = ZFLAG || (NFLAG != VFLAG);
3411: uint8 outdata = cc ? (uint8)(-1) : 0;
3412:
3413: storebyte(srcaddr, outdata);
3414: PC+= 2;
3415: }
3416:
3417: void cpu_op_932a(t_ipc *ipc) /* Scc */ {
3418: /* mask fff8, bits 50e0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3419: int srcreg = (ipc->opcode >> 0) & 7;
3420: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3421: uint8 cc = 1;
3422: uint8 outdata = cc ? (uint8)(-1) : 0;
3423:
3424: storebyte(srcaddr, outdata);
3425: PC+= 2;
3426: }
3427:
3428: void cpu_op_933a(t_ipc *ipc) /* Scc */ {
3429: /* mask fff8, bits 52e0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3430: int srcreg = (ipc->opcode >> 0) & 7;
3431: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3432: uint8 cc = !(CFLAG || ZFLAG);
3433: uint8 outdata = cc ? (uint8)(-1) : 0;
3434:
3435: storebyte(srcaddr, outdata);
3436: PC+= 2;
3437: }
3438:
3439: void cpu_op_934a(t_ipc *ipc) /* Scc */ {
3440: /* mask fff8, bits 53e0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3441: int srcreg = (ipc->opcode >> 0) & 7;
3442: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3443: uint8 cc = CFLAG || ZFLAG;
3444: uint8 outdata = cc ? (uint8)(-1) : 0;
3445:
3446: storebyte(srcaddr, outdata);
3447: PC+= 2;
3448: }
3449:
3450: void cpu_op_935a(t_ipc *ipc) /* Scc */ {
3451: /* mask fff8, bits 54e0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3452: int srcreg = (ipc->opcode >> 0) & 7;
3453: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3454: uint8 cc = !CFLAG;
3455: uint8 outdata = cc ? (uint8)(-1) : 0;
3456:
3457: storebyte(srcaddr, outdata);
3458: PC+= 2;
3459: }
3460:
3461: void cpu_op_936a(t_ipc *ipc) /* Scc */ {
3462: /* mask fff8, bits 55e0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3463: int srcreg = (ipc->opcode >> 0) & 7;
3464: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3465: uint8 cc = CFLAG;
3466: uint8 outdata = cc ? (uint8)(-1) : 0;
3467:
3468: storebyte(srcaddr, outdata);
3469: PC+= 2;
3470: }
3471:
3472: void cpu_op_937a(t_ipc *ipc) /* Scc */ {
3473: /* mask fff8, bits 56e0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3474: int srcreg = (ipc->opcode >> 0) & 7;
3475: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3476: uint8 cc = !ZFLAG;
3477: uint8 outdata = cc ? (uint8)(-1) : 0;
3478:
3479: storebyte(srcaddr, outdata);
3480: PC+= 2;
3481: }
3482:
3483: void cpu_op_938a(t_ipc *ipc) /* Scc */ {
3484: /* mask fff8, bits 57e0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3485: int srcreg = (ipc->opcode >> 0) & 7;
3486: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3487: uint8 cc = ZFLAG;
3488: uint8 outdata = cc ? (uint8)(-1) : 0;
3489:
3490: storebyte(srcaddr, outdata);
3491: PC+= 2;
3492: }
3493:
3494: void cpu_op_939a(t_ipc *ipc) /* Scc */ {
3495: /* mask fff8, bits 58e0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3496: int srcreg = (ipc->opcode >> 0) & 7;
3497: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3498: uint8 cc = !VFLAG;
3499: uint8 outdata = cc ? (uint8)(-1) : 0;
3500:
3501: storebyte(srcaddr, outdata);
3502: PC+= 2;
3503: }
3504:
3505: void cpu_op_940a(t_ipc *ipc) /* Scc */ {
3506: /* mask fff8, bits 59e0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3507: int srcreg = (ipc->opcode >> 0) & 7;
3508: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3509: uint8 cc = VFLAG;
3510: uint8 outdata = cc ? (uint8)(-1) : 0;
3511:
3512: storebyte(srcaddr, outdata);
3513: PC+= 2;
3514: }
3515:
3516: void cpu_op_941a(t_ipc *ipc) /* Scc */ {
3517: /* mask fff8, bits 5ae0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3518: int srcreg = (ipc->opcode >> 0) & 7;
3519: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3520: uint8 cc = !NFLAG;
3521: uint8 outdata = cc ? (uint8)(-1) : 0;
3522:
3523: storebyte(srcaddr, outdata);
3524: PC+= 2;
3525: }
3526:
3527: void cpu_op_942a(t_ipc *ipc) /* Scc */ {
3528: /* mask fff8, bits 5be0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3529: int srcreg = (ipc->opcode >> 0) & 7;
3530: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3531: uint8 cc = NFLAG;
3532: uint8 outdata = cc ? (uint8)(-1) : 0;
3533:
3534: storebyte(srcaddr, outdata);
3535: PC+= 2;
3536: }
3537:
3538: void cpu_op_943a(t_ipc *ipc) /* Scc */ {
3539: /* mask fff8, bits 5ce0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3540: int srcreg = (ipc->opcode >> 0) & 7;
3541: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3542: uint8 cc = (NFLAG == VFLAG);
3543: uint8 outdata = cc ? (uint8)(-1) : 0;
3544:
3545: storebyte(srcaddr, outdata);
3546: PC+= 2;
3547: }
3548:
3549: void cpu_op_944a(t_ipc *ipc) /* Scc */ {
3550: /* mask fff8, bits 5de0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3551: int srcreg = (ipc->opcode >> 0) & 7;
3552: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3553: uint8 cc = (NFLAG != VFLAG);
3554: uint8 outdata = cc ? (uint8)(-1) : 0;
3555:
3556: storebyte(srcaddr, outdata);
3557: PC+= 2;
3558: }
3559:
3560: void cpu_op_945a(t_ipc *ipc) /* Scc */ {
3561: /* mask fff8, bits 5ee0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3562: int srcreg = (ipc->opcode >> 0) & 7;
3563: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3564: uint8 cc = !ZFLAG && (NFLAG == VFLAG);
3565: uint8 outdata = cc ? (uint8)(-1) : 0;
3566:
3567: storebyte(srcaddr, outdata);
3568: PC+= 2;
3569: }
3570:
3571: void cpu_op_946a(t_ipc *ipc) /* Scc */ {
3572: /* mask fff8, bits 5fe0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3573: int srcreg = (ipc->opcode >> 0) & 7;
3574: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
3575: uint8 cc = ZFLAG || (NFLAG != VFLAG);
3576: uint8 outdata = cc ? (uint8)(-1) : 0;
3577:
3578: storebyte(srcaddr, outdata);
3579: PC+= 2;
3580: }
3581:
3582: void cpu_op_947a(t_ipc *ipc) /* Scc */ {
3583: /* mask fff8, bits 50e8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3584: int srcreg = (ipc->opcode >> 0) & 7;
3585: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3586: uint8 cc = 1;
3587: uint8 outdata = cc ? (uint8)(-1) : 0;
3588:
3589: storebyte(srcaddr, outdata);
3590: PC+= 4;
3591: }
3592:
3593: void cpu_op_948a(t_ipc *ipc) /* Scc */ {
3594: /* mask fff8, bits 52e8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3595: int srcreg = (ipc->opcode >> 0) & 7;
3596: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3597: uint8 cc = !(CFLAG || ZFLAG);
3598: uint8 outdata = cc ? (uint8)(-1) : 0;
3599:
3600: storebyte(srcaddr, outdata);
3601: PC+= 4;
3602: }
3603:
3604: void cpu_op_949a(t_ipc *ipc) /* Scc */ {
3605: /* mask fff8, bits 53e8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3606: int srcreg = (ipc->opcode >> 0) & 7;
3607: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3608: uint8 cc = CFLAG || ZFLAG;
3609: uint8 outdata = cc ? (uint8)(-1) : 0;
3610:
3611: storebyte(srcaddr, outdata);
3612: PC+= 4;
3613: }
3614:
3615: void cpu_op_950a(t_ipc *ipc) /* Scc */ {
3616: /* mask fff8, bits 54e8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3617: int srcreg = (ipc->opcode >> 0) & 7;
3618: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3619: uint8 cc = !CFLAG;
3620: uint8 outdata = cc ? (uint8)(-1) : 0;
3621:
3622: storebyte(srcaddr, outdata);
3623: PC+= 4;
3624: }
3625:
3626: void cpu_op_951a(t_ipc *ipc) /* Scc */ {
3627: /* mask fff8, bits 55e8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3628: int srcreg = (ipc->opcode >> 0) & 7;
3629: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3630: uint8 cc = CFLAG;
3631: uint8 outdata = cc ? (uint8)(-1) : 0;
3632:
3633: storebyte(srcaddr, outdata);
3634: PC+= 4;
3635: }
3636:
3637: void cpu_op_952a(t_ipc *ipc) /* Scc */ {
3638: /* mask fff8, bits 56e8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3639: int srcreg = (ipc->opcode >> 0) & 7;
3640: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3641: uint8 cc = !ZFLAG;
3642: uint8 outdata = cc ? (uint8)(-1) : 0;
3643:
3644: storebyte(srcaddr, outdata);
3645: PC+= 4;
3646: }
3647:
3648: void cpu_op_953a(t_ipc *ipc) /* Scc */ {
3649: /* mask fff8, bits 57e8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3650: int srcreg = (ipc->opcode >> 0) & 7;
3651: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3652: uint8 cc = ZFLAG;
3653: uint8 outdata = cc ? (uint8)(-1) : 0;
3654:
3655: storebyte(srcaddr, outdata);
3656: PC+= 4;
3657: }
3658:
3659: void cpu_op_954a(t_ipc *ipc) /* Scc */ {
3660: /* mask fff8, bits 58e8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3661: int srcreg = (ipc->opcode >> 0) & 7;
3662: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3663: uint8 cc = !VFLAG;
3664: uint8 outdata = cc ? (uint8)(-1) : 0;
3665:
3666: storebyte(srcaddr, outdata);
3667: PC+= 4;
3668: }
3669:
3670: void cpu_op_955a(t_ipc *ipc) /* Scc */ {
3671: /* mask fff8, bits 59e8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3672: int srcreg = (ipc->opcode >> 0) & 7;
3673: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3674: uint8 cc = VFLAG;
3675: uint8 outdata = cc ? (uint8)(-1) : 0;
3676:
3677: storebyte(srcaddr, outdata);
3678: PC+= 4;
3679: }
3680:
3681: void cpu_op_956a(t_ipc *ipc) /* Scc */ {
3682: /* mask fff8, bits 5ae8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3683: int srcreg = (ipc->opcode >> 0) & 7;
3684: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3685: uint8 cc = !NFLAG;
3686: uint8 outdata = cc ? (uint8)(-1) : 0;
3687:
3688: storebyte(srcaddr, outdata);
3689: PC+= 4;
3690: }
3691:
3692: void cpu_op_957a(t_ipc *ipc) /* Scc */ {
3693: /* mask fff8, bits 5be8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3694: int srcreg = (ipc->opcode >> 0) & 7;
3695: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3696: uint8 cc = NFLAG;
3697: uint8 outdata = cc ? (uint8)(-1) : 0;
3698:
3699: storebyte(srcaddr, outdata);
3700: PC+= 4;
3701: }
3702:
3703: void cpu_op_958a(t_ipc *ipc) /* Scc */ {
3704: /* mask fff8, bits 5ce8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3705: int srcreg = (ipc->opcode >> 0) & 7;
3706: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3707: uint8 cc = (NFLAG == VFLAG);
3708: uint8 outdata = cc ? (uint8)(-1) : 0;
3709:
3710: storebyte(srcaddr, outdata);
3711: PC+= 4;
3712: }
3713:
3714: void cpu_op_959a(t_ipc *ipc) /* Scc */ {
3715: /* mask fff8, bits 5de8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3716: int srcreg = (ipc->opcode >> 0) & 7;
3717: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3718: uint8 cc = (NFLAG != VFLAG);
3719: uint8 outdata = cc ? (uint8)(-1) : 0;
3720:
3721: storebyte(srcaddr, outdata);
3722: PC+= 4;
3723: }
3724:
3725: void cpu_op_960a(t_ipc *ipc) /* Scc */ {
3726: /* mask fff8, bits 5ee8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3727: int srcreg = (ipc->opcode >> 0) & 7;
3728: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3729: uint8 cc = !ZFLAG && (NFLAG == VFLAG);
3730: uint8 outdata = cc ? (uint8)(-1) : 0;
3731:
3732: storebyte(srcaddr, outdata);
3733: PC+= 4;
3734: }
3735:
3736: void cpu_op_961a(t_ipc *ipc) /* Scc */ {
3737: /* mask fff8, bits 5fe8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3738: int srcreg = (ipc->opcode >> 0) & 7;
3739: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
3740: uint8 cc = ZFLAG || (NFLAG != VFLAG);
3741: uint8 outdata = cc ? (uint8)(-1) : 0;
3742:
3743: storebyte(srcaddr, outdata);
3744: PC+= 4;
3745: }
3746:
3747: void cpu_op_962a(t_ipc *ipc) /* Scc */ {
3748: /* mask fff8, bits 50f0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3749: int srcreg = (ipc->opcode >> 0) & 7;
3750: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3751: uint8 cc = 1;
3752: uint8 outdata = cc ? (uint8)(-1) : 0;
3753:
3754: storebyte(srcaddr, outdata);
3755: PC+= 4;
3756: }
3757:
3758: void cpu_op_963a(t_ipc *ipc) /* Scc */ {
3759: /* mask fff8, bits 52f0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3760: int srcreg = (ipc->opcode >> 0) & 7;
3761: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3762: uint8 cc = !(CFLAG || ZFLAG);
3763: uint8 outdata = cc ? (uint8)(-1) : 0;
3764:
3765: storebyte(srcaddr, outdata);
3766: PC+= 4;
3767: }
3768:
3769: void cpu_op_964a(t_ipc *ipc) /* Scc */ {
3770: /* mask fff8, bits 53f0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3771: int srcreg = (ipc->opcode >> 0) & 7;
3772: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3773: uint8 cc = CFLAG || ZFLAG;
3774: uint8 outdata = cc ? (uint8)(-1) : 0;
3775:
3776: storebyte(srcaddr, outdata);
3777: PC+= 4;
3778: }
3779:
3780: void cpu_op_965a(t_ipc *ipc) /* Scc */ {
3781: /* mask fff8, bits 54f0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3782: int srcreg = (ipc->opcode >> 0) & 7;
3783: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3784: uint8 cc = !CFLAG;
3785: uint8 outdata = cc ? (uint8)(-1) : 0;
3786:
3787: storebyte(srcaddr, outdata);
3788: PC+= 4;
3789: }
3790:
3791: void cpu_op_966a(t_ipc *ipc) /* Scc */ {
3792: /* mask fff8, bits 55f0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3793: int srcreg = (ipc->opcode >> 0) & 7;
3794: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3795: uint8 cc = CFLAG;
3796: uint8 outdata = cc ? (uint8)(-1) : 0;
3797:
3798: storebyte(srcaddr, outdata);
3799: PC+= 4;
3800: }
3801:
3802: void cpu_op_967a(t_ipc *ipc) /* Scc */ {
3803: /* mask fff8, bits 56f0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3804: int srcreg = (ipc->opcode >> 0) & 7;
3805: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3806: uint8 cc = !ZFLAG;
3807: uint8 outdata = cc ? (uint8)(-1) : 0;
3808:
3809: storebyte(srcaddr, outdata);
3810: PC+= 4;
3811: }
3812:
3813: void cpu_op_968a(t_ipc *ipc) /* Scc */ {
3814: /* mask fff8, bits 57f0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3815: int srcreg = (ipc->opcode >> 0) & 7;
3816: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3817: uint8 cc = ZFLAG;
3818: uint8 outdata = cc ? (uint8)(-1) : 0;
3819:
3820: storebyte(srcaddr, outdata);
3821: PC+= 4;
3822: }
3823:
3824: void cpu_op_969a(t_ipc *ipc) /* Scc */ {
3825: /* mask fff8, bits 58f0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3826: int srcreg = (ipc->opcode >> 0) & 7;
3827: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3828: uint8 cc = !VFLAG;
3829: uint8 outdata = cc ? (uint8)(-1) : 0;
3830:
3831: storebyte(srcaddr, outdata);
3832: PC+= 4;
3833: }
3834:
3835: void cpu_op_970a(t_ipc *ipc) /* Scc */ {
3836: /* mask fff8, bits 59f0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3837: int srcreg = (ipc->opcode >> 0) & 7;
3838: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3839: uint8 cc = VFLAG;
3840: uint8 outdata = cc ? (uint8)(-1) : 0;
3841:
3842: storebyte(srcaddr, outdata);
3843: PC+= 4;
3844: }
3845:
3846: void cpu_op_971a(t_ipc *ipc) /* Scc */ {
3847: /* mask fff8, bits 5af0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3848: int srcreg = (ipc->opcode >> 0) & 7;
3849: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3850: uint8 cc = !NFLAG;
3851: uint8 outdata = cc ? (uint8)(-1) : 0;
3852:
3853: storebyte(srcaddr, outdata);
3854: PC+= 4;
3855: }
3856:
3857: void cpu_op_972a(t_ipc *ipc) /* Scc */ {
3858: /* mask fff8, bits 5bf0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3859: int srcreg = (ipc->opcode >> 0) & 7;
3860: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3861: uint8 cc = NFLAG;
3862: uint8 outdata = cc ? (uint8)(-1) : 0;
3863:
3864: storebyte(srcaddr, outdata);
3865: PC+= 4;
3866: }
3867:
3868: void cpu_op_973a(t_ipc *ipc) /* Scc */ {
3869: /* mask fff8, bits 5cf0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3870: int srcreg = (ipc->opcode >> 0) & 7;
3871: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3872: uint8 cc = (NFLAG == VFLAG);
3873: uint8 outdata = cc ? (uint8)(-1) : 0;
3874:
3875: storebyte(srcaddr, outdata);
3876: PC+= 4;
3877: }
3878:
3879: void cpu_op_974a(t_ipc *ipc) /* Scc */ {
3880: /* mask fff8, bits 5df0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3881: int srcreg = (ipc->opcode >> 0) & 7;
3882: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3883: uint8 cc = (NFLAG != VFLAG);
3884: uint8 outdata = cc ? (uint8)(-1) : 0;
3885:
3886: storebyte(srcaddr, outdata);
3887: PC+= 4;
3888: }
3889:
3890: void cpu_op_975a(t_ipc *ipc) /* Scc */ {
3891: /* mask fff8, bits 5ef0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3892: int srcreg = (ipc->opcode >> 0) & 7;
3893: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3894: uint8 cc = !ZFLAG && (NFLAG == VFLAG);
3895: uint8 outdata = cc ? (uint8)(-1) : 0;
3896:
3897: storebyte(srcaddr, outdata);
3898: PC+= 4;
3899: }
3900:
3901: void cpu_op_976a(t_ipc *ipc) /* Scc */ {
3902: /* mask fff8, bits 5ff0, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3903: int srcreg = (ipc->opcode >> 0) & 7;
3904: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
3905: uint8 cc = ZFLAG || (NFLAG != VFLAG);
3906: uint8 outdata = cc ? (uint8)(-1) : 0;
3907:
3908: storebyte(srcaddr, outdata);
3909: PC+= 4;
3910: }
3911:
3912: void cpu_op_977a(t_ipc *ipc) /* Scc */ {
3913: /* mask ffff, bits 50f8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3914: uint32 srcaddr = ipc->src;
3915: uint8 cc = 1;
3916: uint8 outdata = cc ? (uint8)(-1) : 0;
3917:
3918: storebyte(srcaddr, outdata);
3919: PC+= 4;
3920: }
3921:
3922: void cpu_op_978a(t_ipc *ipc) /* Scc */ {
3923: /* mask ffff, bits 52f8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3924: uint32 srcaddr = ipc->src;
3925: uint8 cc = !(CFLAG || ZFLAG);
3926: uint8 outdata = cc ? (uint8)(-1) : 0;
3927:
3928: storebyte(srcaddr, outdata);
3929: PC+= 4;
3930: }
3931:
3932: void cpu_op_979a(t_ipc *ipc) /* Scc */ {
3933: /* mask ffff, bits 53f8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3934: uint32 srcaddr = ipc->src;
3935: uint8 cc = CFLAG || ZFLAG;
3936: uint8 outdata = cc ? (uint8)(-1) : 0;
3937:
3938: storebyte(srcaddr, outdata);
3939: PC+= 4;
3940: }
3941:
3942: void cpu_op_980a(t_ipc *ipc) /* Scc */ {
3943: /* mask ffff, bits 54f8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3944: uint32 srcaddr = ipc->src;
3945: uint8 cc = !CFLAG;
3946: uint8 outdata = cc ? (uint8)(-1) : 0;
3947:
3948: storebyte(srcaddr, outdata);
3949: PC+= 4;
3950: }
3951:
3952: void cpu_op_981a(t_ipc *ipc) /* Scc */ {
3953: /* mask ffff, bits 55f8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3954: uint32 srcaddr = ipc->src;
3955: uint8 cc = CFLAG;
3956: uint8 outdata = cc ? (uint8)(-1) : 0;
3957:
3958: storebyte(srcaddr, outdata);
3959: PC+= 4;
3960: }
3961:
3962: void cpu_op_982a(t_ipc *ipc) /* Scc */ {
3963: /* mask ffff, bits 56f8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3964: uint32 srcaddr = ipc->src;
3965: uint8 cc = !ZFLAG;
3966: uint8 outdata = cc ? (uint8)(-1) : 0;
3967:
3968: storebyte(srcaddr, outdata);
3969: PC+= 4;
3970: }
3971:
3972: void cpu_op_983a(t_ipc *ipc) /* Scc */ {
3973: /* mask ffff, bits 57f8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3974: uint32 srcaddr = ipc->src;
3975: uint8 cc = ZFLAG;
3976: uint8 outdata = cc ? (uint8)(-1) : 0;
3977:
3978: storebyte(srcaddr, outdata);
3979: PC+= 4;
3980: }
3981:
3982: void cpu_op_984a(t_ipc *ipc) /* Scc */ {
3983: /* mask ffff, bits 58f8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3984: uint32 srcaddr = ipc->src;
3985: uint8 cc = !VFLAG;
3986: uint8 outdata = cc ? (uint8)(-1) : 0;
3987:
3988: storebyte(srcaddr, outdata);
3989: PC+= 4;
3990: }
3991:
3992: void cpu_op_985a(t_ipc *ipc) /* Scc */ {
3993: /* mask ffff, bits 59f8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
3994: uint32 srcaddr = ipc->src;
3995: uint8 cc = VFLAG;
3996: uint8 outdata = cc ? (uint8)(-1) : 0;
3997:
3998: storebyte(srcaddr, outdata);
3999: PC+= 4;
4000: }
4001:
4002: void cpu_op_986a(t_ipc *ipc) /* Scc */ {
4003: /* mask ffff, bits 5af8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4004: uint32 srcaddr = ipc->src;
4005: uint8 cc = !NFLAG;
4006: uint8 outdata = cc ? (uint8)(-1) : 0;
4007:
4008: storebyte(srcaddr, outdata);
4009: PC+= 4;
4010: }
4011:
4012: void cpu_op_987a(t_ipc *ipc) /* Scc */ {
4013: /* mask ffff, bits 5bf8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4014: uint32 srcaddr = ipc->src;
4015: uint8 cc = NFLAG;
4016: uint8 outdata = cc ? (uint8)(-1) : 0;
4017:
4018: storebyte(srcaddr, outdata);
4019: PC+= 4;
4020: }
4021:
4022: void cpu_op_988a(t_ipc *ipc) /* Scc */ {
4023: /* mask ffff, bits 5cf8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4024: uint32 srcaddr = ipc->src;
4025: uint8 cc = (NFLAG == VFLAG);
4026: uint8 outdata = cc ? (uint8)(-1) : 0;
4027:
4028: storebyte(srcaddr, outdata);
4029: PC+= 4;
4030: }
4031:
4032: void cpu_op_989a(t_ipc *ipc) /* Scc */ {
4033: /* mask ffff, bits 5df8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4034: uint32 srcaddr = ipc->src;
4035: uint8 cc = (NFLAG != VFLAG);
4036: uint8 outdata = cc ? (uint8)(-1) : 0;
4037:
4038: storebyte(srcaddr, outdata);
4039: PC+= 4;
4040: }
4041:
4042: void cpu_op_990a(t_ipc *ipc) /* Scc */ {
4043: /* mask ffff, bits 5ef8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4044: uint32 srcaddr = ipc->src;
4045: uint8 cc = !ZFLAG && (NFLAG == VFLAG);
4046: uint8 outdata = cc ? (uint8)(-1) : 0;
4047:
4048: storebyte(srcaddr, outdata);
4049: PC+= 4;
4050: }
4051:
4052: void cpu_op_991a(t_ipc *ipc) /* Scc */ {
4053: /* mask ffff, bits 5ff8, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4054: uint32 srcaddr = ipc->src;
4055: uint8 cc = ZFLAG || (NFLAG != VFLAG);
4056: uint8 outdata = cc ? (uint8)(-1) : 0;
4057:
4058: storebyte(srcaddr, outdata);
4059: PC+= 4;
4060: }
4061:
4062: void cpu_op_992a(t_ipc *ipc) /* Scc */ {
4063: /* mask ffff, bits 50f9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4064: uint32 srcaddr = ipc->src;
4065: uint8 cc = 1;
4066: uint8 outdata = cc ? (uint8)(-1) : 0;
4067:
4068: storebyte(srcaddr, outdata);
4069: PC+= 6;
4070: }
4071:
4072: void cpu_op_993a(t_ipc *ipc) /* Scc */ {
4073: /* mask ffff, bits 52f9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4074: uint32 srcaddr = ipc->src;
4075: uint8 cc = !(CFLAG || ZFLAG);
4076: uint8 outdata = cc ? (uint8)(-1) : 0;
4077:
4078: storebyte(srcaddr, outdata);
4079: PC+= 6;
4080: }
4081:
4082: void cpu_op_994a(t_ipc *ipc) /* Scc */ {
4083: /* mask ffff, bits 53f9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4084: uint32 srcaddr = ipc->src;
4085: uint8 cc = CFLAG || ZFLAG;
4086: uint8 outdata = cc ? (uint8)(-1) : 0;
4087:
4088: storebyte(srcaddr, outdata);
4089: PC+= 6;
4090: }
4091:
4092: void cpu_op_995a(t_ipc *ipc) /* Scc */ {
4093: /* mask ffff, bits 54f9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4094: uint32 srcaddr = ipc->src;
4095: uint8 cc = !CFLAG;
4096: uint8 outdata = cc ? (uint8)(-1) : 0;
4097:
4098: storebyte(srcaddr, outdata);
4099: PC+= 6;
4100: }
4101:
4102: void cpu_op_996a(t_ipc *ipc) /* Scc */ {
4103: /* mask ffff, bits 55f9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4104: uint32 srcaddr = ipc->src;
4105: uint8 cc = CFLAG;
4106: uint8 outdata = cc ? (uint8)(-1) : 0;
4107:
4108: storebyte(srcaddr, outdata);
4109: PC+= 6;
4110: }
4111:
4112: void cpu_op_997a(t_ipc *ipc) /* Scc */ {
4113: /* mask ffff, bits 56f9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4114: uint32 srcaddr = ipc->src;
4115: uint8 cc = !ZFLAG;
4116: uint8 outdata = cc ? (uint8)(-1) : 0;
4117:
4118: storebyte(srcaddr, outdata);
4119: PC+= 6;
4120: }
4121:
4122: void cpu_op_998a(t_ipc *ipc) /* Scc */ {
4123: /* mask ffff, bits 57f9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4124: uint32 srcaddr = ipc->src;
4125: uint8 cc = ZFLAG;
4126: uint8 outdata = cc ? (uint8)(-1) : 0;
4127:
4128: storebyte(srcaddr, outdata);
4129: PC+= 6;
4130: }
4131:
4132: void cpu_op_999a(t_ipc *ipc) /* Scc */ {
4133: /* mask ffff, bits 58f9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4134: uint32 srcaddr = ipc->src;
4135: uint8 cc = !VFLAG;
4136: uint8 outdata = cc ? (uint8)(-1) : 0;
4137:
4138: storebyte(srcaddr, outdata);
4139: PC+= 6;
4140: }
4141:
4142: void cpu_op_1000a(t_ipc *ipc) /* Scc */ {
4143: /* mask ffff, bits 59f9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4144: uint32 srcaddr = ipc->src;
4145: uint8 cc = VFLAG;
4146: uint8 outdata = cc ? (uint8)(-1) : 0;
4147:
4148: storebyte(srcaddr, outdata);
4149: PC+= 6;
4150: }
4151:
4152: void cpu_op_1001a(t_ipc *ipc) /* Scc */ {
4153: /* mask ffff, bits 5af9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4154: uint32 srcaddr = ipc->src;
4155: uint8 cc = !NFLAG;
4156: uint8 outdata = cc ? (uint8)(-1) : 0;
4157:
4158: storebyte(srcaddr, outdata);
4159: PC+= 6;
4160: }
4161:
4162: void cpu_op_1002a(t_ipc *ipc) /* Scc */ {
4163: /* mask ffff, bits 5bf9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4164: uint32 srcaddr = ipc->src;
4165: uint8 cc = NFLAG;
4166: uint8 outdata = cc ? (uint8)(-1) : 0;
4167:
4168: storebyte(srcaddr, outdata);
4169: PC+= 6;
4170: }
4171:
4172: void cpu_op_1003a(t_ipc *ipc) /* Scc */ {
4173: /* mask ffff, bits 5cf9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4174: uint32 srcaddr = ipc->src;
4175: uint8 cc = (NFLAG == VFLAG);
4176: uint8 outdata = cc ? (uint8)(-1) : 0;
4177:
4178: storebyte(srcaddr, outdata);
4179: PC+= 6;
4180: }
4181:
4182: void cpu_op_1004a(t_ipc *ipc) /* Scc */ {
4183: /* mask ffff, bits 5df9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4184: uint32 srcaddr = ipc->src;
4185: uint8 cc = (NFLAG != VFLAG);
4186: uint8 outdata = cc ? (uint8)(-1) : 0;
4187:
4188: storebyte(srcaddr, outdata);
4189: PC+= 6;
4190: }
4191:
4192: void cpu_op_1005a(t_ipc *ipc) /* Scc */ {
4193: /* mask ffff, bits 5ef9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4194: uint32 srcaddr = ipc->src;
4195: uint8 cc = !ZFLAG && (NFLAG == VFLAG);
4196: uint8 outdata = cc ? (uint8)(-1) : 0;
4197:
4198: storebyte(srcaddr, outdata);
4199: PC+= 6;
4200: }
4201:
4202: void cpu_op_1006a(t_ipc *ipc) /* Scc */ {
4203: /* mask ffff, bits 5ff9, mnemonic 58, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4204: uint32 srcaddr = ipc->src;
4205: uint8 cc = ZFLAG || (NFLAG != VFLAG);
4206: uint8 outdata = cc ? (uint8)(-1) : 0;
4207:
4208: storebyte(srcaddr, outdata);
4209: PC+= 6;
4210: }
4211:
4212: void cpu_op_1007a(t_ipc *ipc) /* SF */ {
4213: /* mask fff8, bits 51c0, mnemonic 59, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 0, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4214: int srcreg = (ipc->opcode >> 0) & 7;
4215: uint8 outdata = 0;
4216:
4217: DATAREG(srcreg) = (DATAREG(srcreg) & ~0xff) | outdata;
4218: PC+= 2;
4219: }
4220:
4221: void cpu_op_1008a(t_ipc *ipc) /* SF */ {
4222: /* mask fff8, bits 51d0, mnemonic 59, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 2, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4223: int srcreg = (ipc->opcode >> 0) & 7;
4224: uint32 srcaddr = ADDRREG(srcreg);
4225: uint8 outdata = 0;
4226:
4227: storebyte(srcaddr, outdata);
4228: PC+= 2;
4229: }
4230:
4231: void cpu_op_1009a(t_ipc *ipc) /* SF */ {
4232: /* mask fff8, bits 51d8, mnemonic 59, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 3, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4233: int srcreg = (ipc->opcode >> 0) & 7;
4234: uint32 srcaddr = ADDRREG(srcreg);
4235: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0);
4236: uint8 outdata = 0;
4237:
4238: storebyte(srcaddr, outdata);
4239: PC+= 2;
4240: }
4241:
4242: void cpu_op_1010a(t_ipc *ipc) /* SF */ {
4243: /* mask fff8, bits 51e0, mnemonic 59, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 4, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4244: int srcreg = (ipc->opcode >> 0) & 7;
4245: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1));
4246: uint8 outdata = 0;
4247:
4248: storebyte(srcaddr, outdata);
4249: PC+= 2;
4250: }
4251:
4252: void cpu_op_1011a(t_ipc *ipc) /* SF */ {
4253: /* mask fff8, bits 51e8, mnemonic 59, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 5, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4254: int srcreg = (ipc->opcode >> 0) & 7;
4255: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src;
4256: uint8 outdata = 0;
4257:
4258: storebyte(srcaddr, outdata);
4259: PC+= 4;
4260: }
4261:
4262: void cpu_op_1012a(t_ipc *ipc) /* SF */ {
4263: /* mask fff8, bits 51f0, mnemonic 59, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 6, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4264: int srcreg = (ipc->opcode >> 0) & 7;
4265: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc);
4266: uint8 outdata = 0;
4267:
4268: storebyte(srcaddr, outdata);
4269: PC+= 4;
4270: }
4271:
4272: void cpu_op_1013a(t_ipc *ipc) /* SF */ {
4273: /* mask ffff, bits 51f8, mnemonic 59, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 7, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4274: uint32 srcaddr = ipc->src;
4275: uint8 outdata = 0;
4276:
4277: storebyte(srcaddr, outdata);
4278: PC+= 4;
4279: }
4280:
4281: void cpu_op_1014a(t_ipc *ipc) /* SF */ {
4282: /* mask ffff, bits 51f9, mnemonic 59, priv 0, endblk 0, imm_notzero 0, used -1 set 0, size 1, stype 8, dtype 20, sbitpos 0, dbitpos 0, immvalue 0 */
4283: uint32 srcaddr = ipc->src;
4284: uint8 outdata = 0;
4285:
4286: storebyte(srcaddr, outdata);
4287: PC+= 6;
4288: }
4289:
4290: void cpu_op_1015a(t_ipc *ipc) /* DBcc */ {
4291: /* mask fff8, bits 50c8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4292: uint32 srcdata = ipc->src;
4293: int dstreg = (ipc->opcode >> 0) & 7;
4294: uint16 dstdata = DATAREG(dstreg);
4295: uint8 cc = 1;
4296:
4297: if (!cc) {
4298: dstdata-= 1;
4299: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4300: | (dstdata & 0xFFFF);
4301: if ((sint16)dstdata != -1)
4302: PC = srcdata;
4303: else
4304: PC+= 4;
4305: } else
4306: PC+= 4;
4307: }
4308:
4309: void cpu_op_1016a(t_ipc *ipc) /* DBcc */ {
4310: /* mask fff8, bits 52c8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4311: uint32 srcdata = ipc->src;
4312: int dstreg = (ipc->opcode >> 0) & 7;
4313: uint16 dstdata = DATAREG(dstreg);
4314: uint8 cc = !(CFLAG || ZFLAG);
4315:
4316: if (!cc) {
4317: dstdata-= 1;
4318: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4319: | (dstdata & 0xFFFF);
4320: if ((sint16)dstdata != -1)
4321: PC = srcdata;
4322: else
4323: PC+= 4;
4324: } else
4325: PC+= 4;
4326: }
4327:
4328: void cpu_op_1017a(t_ipc *ipc) /* DBcc */ {
4329: /* mask fff8, bits 53c8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4330: uint32 srcdata = ipc->src;
4331: int dstreg = (ipc->opcode >> 0) & 7;
4332: uint16 dstdata = DATAREG(dstreg);
4333: uint8 cc = CFLAG || ZFLAG;
4334:
4335: if (!cc) {
4336: dstdata-= 1;
4337: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4338: | (dstdata & 0xFFFF);
4339: if ((sint16)dstdata != -1)
4340: PC = srcdata;
4341: else
4342: PC+= 4;
4343: } else
4344: PC+= 4;
4345: }
4346:
4347: void cpu_op_1018a(t_ipc *ipc) /* DBcc */ {
4348: /* mask fff8, bits 54c8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4349: uint32 srcdata = ipc->src;
4350: int dstreg = (ipc->opcode >> 0) & 7;
4351: uint16 dstdata = DATAREG(dstreg);
4352: uint8 cc = !CFLAG;
4353:
4354: if (!cc) {
4355: dstdata-= 1;
4356: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4357: | (dstdata & 0xFFFF);
4358: if ((sint16)dstdata != -1)
4359: PC = srcdata;
4360: else
4361: PC+= 4;
4362: } else
4363: PC+= 4;
4364: }
4365:
4366: void cpu_op_1019a(t_ipc *ipc) /* DBcc */ {
4367: /* mask fff8, bits 55c8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4368: uint32 srcdata = ipc->src;
4369: int dstreg = (ipc->opcode >> 0) & 7;
4370: uint16 dstdata = DATAREG(dstreg);
4371: uint8 cc = CFLAG;
4372:
4373: if (!cc) {
4374: dstdata-= 1;
4375: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4376: | (dstdata & 0xFFFF);
4377: if ((sint16)dstdata != -1)
4378: PC = srcdata;
4379: else
4380: PC+= 4;
4381: } else
4382: PC+= 4;
4383: }
4384:
4385: void cpu_op_1020a(t_ipc *ipc) /* DBcc */ {
4386: /* mask fff8, bits 56c8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4387: uint32 srcdata = ipc->src;
4388: int dstreg = (ipc->opcode >> 0) & 7;
4389: uint16 dstdata = DATAREG(dstreg);
4390: uint8 cc = !ZFLAG;
4391:
4392: if (!cc) {
4393: dstdata-= 1;
4394: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4395: | (dstdata & 0xFFFF);
4396: if ((sint16)dstdata != -1)
4397: PC = srcdata;
4398: else
4399: PC+= 4;
4400: } else
4401: PC+= 4;
4402: }
4403:
4404: void cpu_op_1021a(t_ipc *ipc) /* DBcc */ {
4405: /* mask fff8, bits 57c8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4406: uint32 srcdata = ipc->src;
4407: int dstreg = (ipc->opcode >> 0) & 7;
4408: uint16 dstdata = DATAREG(dstreg);
4409: uint8 cc = ZFLAG;
4410:
4411: if (!cc) {
4412: dstdata-= 1;
4413: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4414: | (dstdata & 0xFFFF);
4415: if ((sint16)dstdata != -1)
4416: PC = srcdata;
4417: else
4418: PC+= 4;
4419: } else
4420: PC+= 4;
4421: }
4422:
4423: void cpu_op_1022a(t_ipc *ipc) /* DBcc */ {
4424: /* mask fff8, bits 58c8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4425: uint32 srcdata = ipc->src;
4426: int dstreg = (ipc->opcode >> 0) & 7;
4427: uint16 dstdata = DATAREG(dstreg);
4428: uint8 cc = !VFLAG;
4429:
4430: if (!cc) {
4431: dstdata-= 1;
4432: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4433: | (dstdata & 0xFFFF);
4434: if ((sint16)dstdata != -1)
4435: PC = srcdata;
4436: else
4437: PC+= 4;
4438: } else
4439: PC+= 4;
4440: }
4441:
4442: void cpu_op_1023a(t_ipc *ipc) /* DBcc */ {
4443: /* mask fff8, bits 59c8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4444: uint32 srcdata = ipc->src;
4445: int dstreg = (ipc->opcode >> 0) & 7;
4446: uint16 dstdata = DATAREG(dstreg);
4447: uint8 cc = VFLAG;
4448:
4449: if (!cc) {
4450: dstdata-= 1;
4451: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4452: | (dstdata & 0xFFFF);
4453: if ((sint16)dstdata != -1)
4454: PC = srcdata;
4455: else
4456: PC+= 4;
4457: } else
4458: PC+= 4;
4459: }
4460:
4461: void cpu_op_1024a(t_ipc *ipc) /* DBcc */ {
4462: /* mask fff8, bits 5ac8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4463: uint32 srcdata = ipc->src;
4464: int dstreg = (ipc->opcode >> 0) & 7;
4465: uint16 dstdata = DATAREG(dstreg);
4466: uint8 cc = !NFLAG;
4467:
4468: if (!cc) {
4469: dstdata-= 1;
4470: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4471: | (dstdata & 0xFFFF);
4472: if ((sint16)dstdata != -1)
4473: PC = srcdata;
4474: else
4475: PC+= 4;
4476: } else
4477: PC+= 4;
4478: }
4479:
4480: void cpu_op_1025a(t_ipc *ipc) /* DBcc */ {
4481: /* mask fff8, bits 5bc8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4482: uint32 srcdata = ipc->src;
4483: int dstreg = (ipc->opcode >> 0) & 7;
4484: uint16 dstdata = DATAREG(dstreg);
4485: uint8 cc = NFLAG;
4486:
4487: if (!cc) {
4488: dstdata-= 1;
4489: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4490: | (dstdata & 0xFFFF);
4491: if ((sint16)dstdata != -1)
4492: PC = srcdata;
4493: else
4494: PC+= 4;
4495: } else
4496: PC+= 4;
4497: }
4498:
4499: void cpu_op_1026a(t_ipc *ipc) /* DBcc */ {
4500: /* mask fff8, bits 5cc8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4501: uint32 srcdata = ipc->src;
4502: int dstreg = (ipc->opcode >> 0) & 7;
4503: uint16 dstdata = DATAREG(dstreg);
4504: uint8 cc = (NFLAG == VFLAG);
4505:
4506: if (!cc) {
4507: dstdata-= 1;
4508: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4509: | (dstdata & 0xFFFF);
4510: if ((sint16)dstdata != -1)
4511: PC = srcdata;
4512: else
4513: PC+= 4;
4514: } else
4515: PC+= 4;
4516: }
4517:
4518: void cpu_op_1027a(t_ipc *ipc) /* DBcc */ {
4519: /* mask fff8, bits 5dc8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4520: uint32 srcdata = ipc->src;
4521: int dstreg = (ipc->opcode >> 0) & 7;
4522: uint16 dstdata = DATAREG(dstreg);
4523: uint8 cc = (NFLAG != VFLAG);
4524:
4525: if (!cc) {
4526: dstdata-= 1;
4527: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4528: | (dstdata & 0xFFFF);
4529: if ((sint16)dstdata != -1)
4530: PC = srcdata;
4531: else
4532: PC+= 4;
4533: } else
4534: PC+= 4;
4535: }
4536:
4537: void cpu_op_1028a(t_ipc *ipc) /* DBcc */ {
4538: /* mask fff8, bits 5ec8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4539: uint32 srcdata = ipc->src;
4540: int dstreg = (ipc->opcode >> 0) & 7;
4541: uint16 dstdata = DATAREG(dstreg);
4542: uint8 cc = !ZFLAG && (NFLAG == VFLAG);
4543:
4544: if (!cc) {
4545: dstdata-= 1;
4546: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4547: | (dstdata & 0xFFFF);
4548: if ((sint16)dstdata != -1)
4549: PC = srcdata;
4550: else
4551: PC+= 4;
4552: } else
4553: PC+= 4;
4554: }
4555:
4556: void cpu_op_1029a(t_ipc *ipc) /* DBcc */ {
4557: /* mask fff8, bits 5fc8, mnemonic 60, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4558: uint32 srcdata = ipc->src;
4559: int dstreg = (ipc->opcode >> 0) & 7;
4560: uint16 dstdata = DATAREG(dstreg);
4561: uint8 cc = ZFLAG || (NFLAG != VFLAG);
4562:
4563: if (!cc) {
4564: dstdata-= 1;
4565: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF)
4566: | (dstdata & 0xFFFF);
4567: if ((sint16)dstdata != -1)
4568: PC = srcdata;
4569: else
4570: PC+= 4;
4571: } else
4572: PC+= 4;
4573: }
4574:
4575: void cpu_op_1030a(t_ipc *ipc) /* DBRA */ {
4576: /* mask fff8, bits 51c8, mnemonic 61, priv 0, endblk -1, imm_notzero 0, used -1 set 0, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 0, immvalue 0 */
4577: uint32 srcdata = ipc->src;
4578: int dstreg = (ipc->opcode >> 0) & 7;
4579: uint16 dstdata = DATAREG(dstreg);
4580:
4581: dstdata-= 1;
4582: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xFFFF) | (dstdata & 0xFFFF);
4583: if ((sint16)dstdata != -1)
4584: PC = srcdata;
4585: else
4586: PC+= 4;
4587: }
4588:
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