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1.1 ! root 1: /*****************************************************************************/ ! 2: /* Generator - Sega Genesis emulation - (c) James Ponder 1997-1998 */ ! 3: /*****************************************************************************/ ! 4: /* */ ! 5: /* cpu68k-c.c */ ! 6: /* */ ! 7: /*****************************************************************************/ ! 8: ! 9: #include "generator.h" ! 10: #include "cpu68k.h" ! 11: #include "mem68k.h" ! 12: #include "reg68k.h" ! 13: ! 14: #include "cpu68k-inline.h" ! 15: ! 16: #include <stdio.h> ! 17: ! 18: void cpu_op_1316a(t_ipc *ipc) /* AND */ { ! 19: /* mask f1f8, bits c000, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 20: int srcreg = (ipc->opcode >> 0) & 7; ! 21: uint8 srcdata = DATAREG(srcreg); ! 22: int dstreg = (ipc->opcode >> 9) & 7; ! 23: uint8 dstdata = DATAREG(dstreg); ! 24: uint8 outdata = dstdata; ! 25: ! 26: outdata&= srcdata; ! 27: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 28: PC+= 2; ! 29: } ! 30: ! 31: void cpu_op_1316b(t_ipc *ipc) /* AND */ { ! 32: /* mask f1f8, bits c000, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 33: int srcreg = (ipc->opcode >> 0) & 7; ! 34: uint8 srcdata = DATAREG(srcreg); ! 35: int dstreg = (ipc->opcode >> 9) & 7; ! 36: uint8 dstdata = DATAREG(dstreg); ! 37: uint8 outdata = dstdata; ! 38: ! 39: outdata&= srcdata; ! 40: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 41: ! 42: NFLAG = ((sint8)outdata) < 0; ! 43: ZFLAG = !outdata; ! 44: VFLAG = 0; ! 45: CFLAG = 0; ! 46: PC+= 2; ! 47: } ! 48: ! 49: void cpu_op_1317a(t_ipc *ipc) /* AND */ { ! 50: /* mask f1f8, bits c010, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 51: int srcreg = (ipc->opcode >> 0) & 7; ! 52: uint32 srcaddr = ADDRREG(srcreg); ! 53: uint8 srcdata = fetchbyte(srcaddr); ! 54: int dstreg = (ipc->opcode >> 9) & 7; ! 55: uint8 dstdata = DATAREG(dstreg); ! 56: uint8 outdata = dstdata; ! 57: ! 58: outdata&= srcdata; ! 59: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 60: PC+= 2; ! 61: } ! 62: ! 63: void cpu_op_1317b(t_ipc *ipc) /* AND */ { ! 64: /* mask f1f8, bits c010, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 65: int srcreg = (ipc->opcode >> 0) & 7; ! 66: uint32 srcaddr = ADDRREG(srcreg); ! 67: uint8 srcdata = fetchbyte(srcaddr); ! 68: int dstreg = (ipc->opcode >> 9) & 7; ! 69: uint8 dstdata = DATAREG(dstreg); ! 70: uint8 outdata = dstdata; ! 71: ! 72: outdata&= srcdata; ! 73: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 74: ! 75: NFLAG = ((sint8)outdata) < 0; ! 76: ZFLAG = !outdata; ! 77: VFLAG = 0; ! 78: CFLAG = 0; ! 79: PC+= 2; ! 80: } ! 81: ! 82: void cpu_op_1318a(t_ipc *ipc) /* AND */ { ! 83: /* mask f1f8, bits c018, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 84: int srcreg = (ipc->opcode >> 0) & 7; ! 85: uint32 srcaddr = ADDRREG(srcreg); ! 86: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0); ! 87: uint8 srcdata = fetchbyte(srcaddr); ! 88: int dstreg = (ipc->opcode >> 9) & 7; ! 89: uint8 dstdata = DATAREG(dstreg); ! 90: uint8 outdata = dstdata; ! 91: ! 92: outdata&= srcdata; ! 93: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 94: PC+= 2; ! 95: } ! 96: ! 97: void cpu_op_1318b(t_ipc *ipc) /* AND */ { ! 98: /* mask f1f8, bits c018, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 99: int srcreg = (ipc->opcode >> 0) & 7; ! 100: uint32 srcaddr = ADDRREG(srcreg); ! 101: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0); ! 102: uint8 srcdata = fetchbyte(srcaddr); ! 103: int dstreg = (ipc->opcode >> 9) & 7; ! 104: uint8 dstdata = DATAREG(dstreg); ! 105: uint8 outdata = dstdata; ! 106: ! 107: outdata&= srcdata; ! 108: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 109: ! 110: NFLAG = ((sint8)outdata) < 0; ! 111: ZFLAG = !outdata; ! 112: VFLAG = 0; ! 113: CFLAG = 0; ! 114: PC+= 2; ! 115: } ! 116: ! 117: void cpu_op_1319a(t_ipc *ipc) /* AND */ { ! 118: /* mask f1f8, bits c020, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 119: int srcreg = (ipc->opcode >> 0) & 7; ! 120: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1)); ! 121: uint8 srcdata = fetchbyte(srcaddr); ! 122: int dstreg = (ipc->opcode >> 9) & 7; ! 123: uint8 dstdata = DATAREG(dstreg); ! 124: uint8 outdata = dstdata; ! 125: ! 126: outdata&= srcdata; ! 127: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 128: PC+= 2; ! 129: } ! 130: ! 131: void cpu_op_1319b(t_ipc *ipc) /* AND */ { ! 132: /* mask f1f8, bits c020, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 133: int srcreg = (ipc->opcode >> 0) & 7; ! 134: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1)); ! 135: uint8 srcdata = fetchbyte(srcaddr); ! 136: int dstreg = (ipc->opcode >> 9) & 7; ! 137: uint8 dstdata = DATAREG(dstreg); ! 138: uint8 outdata = dstdata; ! 139: ! 140: outdata&= srcdata; ! 141: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 142: ! 143: NFLAG = ((sint8)outdata) < 0; ! 144: ZFLAG = !outdata; ! 145: VFLAG = 0; ! 146: CFLAG = 0; ! 147: PC+= 2; ! 148: } ! 149: ! 150: void cpu_op_1320a(t_ipc *ipc) /* AND */ { ! 151: /* mask f1f8, bits c028, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 152: int srcreg = (ipc->opcode >> 0) & 7; ! 153: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 154: uint8 srcdata = fetchbyte(srcaddr); ! 155: int dstreg = (ipc->opcode >> 9) & 7; ! 156: uint8 dstdata = DATAREG(dstreg); ! 157: uint8 outdata = dstdata; ! 158: ! 159: outdata&= srcdata; ! 160: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 161: PC+= 4; ! 162: } ! 163: ! 164: void cpu_op_1320b(t_ipc *ipc) /* AND */ { ! 165: /* mask f1f8, bits c028, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 166: int srcreg = (ipc->opcode >> 0) & 7; ! 167: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 168: uint8 srcdata = fetchbyte(srcaddr); ! 169: int dstreg = (ipc->opcode >> 9) & 7; ! 170: uint8 dstdata = DATAREG(dstreg); ! 171: uint8 outdata = dstdata; ! 172: ! 173: outdata&= srcdata; ! 174: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 175: ! 176: NFLAG = ((sint8)outdata) < 0; ! 177: ZFLAG = !outdata; ! 178: VFLAG = 0; ! 179: CFLAG = 0; ! 180: PC+= 4; ! 181: } ! 182: ! 183: void cpu_op_1321a(t_ipc *ipc) /* AND */ { ! 184: /* mask f1f8, bits c030, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 185: int srcreg = (ipc->opcode >> 0) & 7; ! 186: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 187: uint8 srcdata = fetchbyte(srcaddr); ! 188: int dstreg = (ipc->opcode >> 9) & 7; ! 189: uint8 dstdata = DATAREG(dstreg); ! 190: uint8 outdata = dstdata; ! 191: ! 192: outdata&= srcdata; ! 193: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 194: PC+= 4; ! 195: } ! 196: ! 197: void cpu_op_1321b(t_ipc *ipc) /* AND */ { ! 198: /* mask f1f8, bits c030, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 199: int srcreg = (ipc->opcode >> 0) & 7; ! 200: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 201: uint8 srcdata = fetchbyte(srcaddr); ! 202: int dstreg = (ipc->opcode >> 9) & 7; ! 203: uint8 dstdata = DATAREG(dstreg); ! 204: uint8 outdata = dstdata; ! 205: ! 206: outdata&= srcdata; ! 207: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 208: ! 209: NFLAG = ((sint8)outdata) < 0; ! 210: ZFLAG = !outdata; ! 211: VFLAG = 0; ! 212: CFLAG = 0; ! 213: PC+= 4; ! 214: } ! 215: ! 216: void cpu_op_1322a(t_ipc *ipc) /* AND */ { ! 217: /* mask f1ff, bits c038, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 218: uint32 srcaddr = ipc->src; ! 219: uint8 srcdata = fetchbyte(srcaddr); ! 220: int dstreg = (ipc->opcode >> 9) & 7; ! 221: uint8 dstdata = DATAREG(dstreg); ! 222: uint8 outdata = dstdata; ! 223: ! 224: outdata&= srcdata; ! 225: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 226: PC+= 4; ! 227: } ! 228: ! 229: void cpu_op_1322b(t_ipc *ipc) /* AND */ { ! 230: /* mask f1ff, bits c038, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 231: uint32 srcaddr = ipc->src; ! 232: uint8 srcdata = fetchbyte(srcaddr); ! 233: int dstreg = (ipc->opcode >> 9) & 7; ! 234: uint8 dstdata = DATAREG(dstreg); ! 235: uint8 outdata = dstdata; ! 236: ! 237: outdata&= srcdata; ! 238: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 239: ! 240: NFLAG = ((sint8)outdata) < 0; ! 241: ZFLAG = !outdata; ! 242: VFLAG = 0; ! 243: CFLAG = 0; ! 244: PC+= 4; ! 245: } ! 246: ! 247: void cpu_op_1323a(t_ipc *ipc) /* AND */ { ! 248: /* mask f1ff, bits c039, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 249: uint32 srcaddr = ipc->src; ! 250: uint8 srcdata = fetchbyte(srcaddr); ! 251: int dstreg = (ipc->opcode >> 9) & 7; ! 252: uint8 dstdata = DATAREG(dstreg); ! 253: uint8 outdata = dstdata; ! 254: ! 255: outdata&= srcdata; ! 256: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 257: PC+= 6; ! 258: } ! 259: ! 260: void cpu_op_1323b(t_ipc *ipc) /* AND */ { ! 261: /* mask f1ff, bits c039, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 262: uint32 srcaddr = ipc->src; ! 263: uint8 srcdata = fetchbyte(srcaddr); ! 264: int dstreg = (ipc->opcode >> 9) & 7; ! 265: uint8 dstdata = DATAREG(dstreg); ! 266: uint8 outdata = dstdata; ! 267: ! 268: outdata&= srcdata; ! 269: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 270: ! 271: NFLAG = ((sint8)outdata) < 0; ! 272: ZFLAG = !outdata; ! 273: VFLAG = 0; ! 274: CFLAG = 0; ! 275: PC+= 6; ! 276: } ! 277: ! 278: void cpu_op_1324a(t_ipc *ipc) /* AND */ { ! 279: /* mask f1ff, bits c03a, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 280: uint32 srcaddr = ipc->src; ! 281: uint8 srcdata = fetchbyte(srcaddr); ! 282: int dstreg = (ipc->opcode >> 9) & 7; ! 283: uint8 dstdata = DATAREG(dstreg); ! 284: uint8 outdata = dstdata; ! 285: ! 286: outdata&= srcdata; ! 287: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 288: PC+= 4; ! 289: } ! 290: ! 291: void cpu_op_1324b(t_ipc *ipc) /* AND */ { ! 292: /* mask f1ff, bits c03a, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 293: uint32 srcaddr = ipc->src; ! 294: uint8 srcdata = fetchbyte(srcaddr); ! 295: int dstreg = (ipc->opcode >> 9) & 7; ! 296: uint8 dstdata = DATAREG(dstreg); ! 297: uint8 outdata = dstdata; ! 298: ! 299: outdata&= srcdata; ! 300: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 301: ! 302: NFLAG = ((sint8)outdata) < 0; ! 303: ZFLAG = !outdata; ! 304: VFLAG = 0; ! 305: CFLAG = 0; ! 306: PC+= 4; ! 307: } ! 308: ! 309: void cpu_op_1325a(t_ipc *ipc) /* AND */ { ! 310: /* mask f1ff, bits c03b, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 311: uint32 srcaddr = idxval_src(ipc); ! 312: uint8 srcdata = fetchbyte(srcaddr); ! 313: int dstreg = (ipc->opcode >> 9) & 7; ! 314: uint8 dstdata = DATAREG(dstreg); ! 315: uint8 outdata = dstdata; ! 316: ! 317: outdata&= srcdata; ! 318: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 319: PC+= 4; ! 320: } ! 321: ! 322: void cpu_op_1325b(t_ipc *ipc) /* AND */ { ! 323: /* mask f1ff, bits c03b, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 324: uint32 srcaddr = idxval_src(ipc); ! 325: uint8 srcdata = fetchbyte(srcaddr); ! 326: int dstreg = (ipc->opcode >> 9) & 7; ! 327: uint8 dstdata = DATAREG(dstreg); ! 328: uint8 outdata = dstdata; ! 329: ! 330: outdata&= srcdata; ! 331: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 332: ! 333: NFLAG = ((sint8)outdata) < 0; ! 334: ZFLAG = !outdata; ! 335: VFLAG = 0; ! 336: CFLAG = 0; ! 337: PC+= 4; ! 338: } ! 339: ! 340: void cpu_op_1326a(t_ipc *ipc) /* AND */ { ! 341: /* mask f1ff, bits c03c, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 342: uint8 srcdata = ipc->src; ! 343: int dstreg = (ipc->opcode >> 9) & 7; ! 344: uint8 dstdata = DATAREG(dstreg); ! 345: uint8 outdata = dstdata; ! 346: ! 347: outdata&= srcdata; ! 348: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 349: PC+= 4; ! 350: } ! 351: ! 352: void cpu_op_1326b(t_ipc *ipc) /* AND */ { ! 353: /* mask f1ff, bits c03c, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 354: uint8 srcdata = ipc->src; ! 355: int dstreg = (ipc->opcode >> 9) & 7; ! 356: uint8 dstdata = DATAREG(dstreg); ! 357: uint8 outdata = dstdata; ! 358: ! 359: outdata&= srcdata; ! 360: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 361: ! 362: NFLAG = ((sint8)outdata) < 0; ! 363: ZFLAG = !outdata; ! 364: VFLAG = 0; ! 365: CFLAG = 0; ! 366: PC+= 4; ! 367: } ! 368: ! 369: void cpu_op_1327a(t_ipc *ipc) /* AND */ { ! 370: /* mask f1f8, bits c040, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 371: int srcreg = (ipc->opcode >> 0) & 7; ! 372: uint16 srcdata = DATAREG(srcreg); ! 373: int dstreg = (ipc->opcode >> 9) & 7; ! 374: uint16 dstdata = DATAREG(dstreg); ! 375: uint16 outdata = dstdata; ! 376: ! 377: outdata&= srcdata; ! 378: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 379: PC+= 2; ! 380: } ! 381: ! 382: void cpu_op_1327b(t_ipc *ipc) /* AND */ { ! 383: /* mask f1f8, bits c040, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 384: int srcreg = (ipc->opcode >> 0) & 7; ! 385: uint16 srcdata = DATAREG(srcreg); ! 386: int dstreg = (ipc->opcode >> 9) & 7; ! 387: uint16 dstdata = DATAREG(dstreg); ! 388: uint16 outdata = dstdata; ! 389: ! 390: outdata&= srcdata; ! 391: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 392: ! 393: NFLAG = ((sint16)outdata) < 0; ! 394: ZFLAG = !outdata; ! 395: VFLAG = 0; ! 396: CFLAG = 0; ! 397: PC+= 2; ! 398: } ! 399: ! 400: void cpu_op_1328a(t_ipc *ipc) /* AND */ { ! 401: /* mask f1f8, bits c050, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 402: int srcreg = (ipc->opcode >> 0) & 7; ! 403: uint32 srcaddr = ADDRREG(srcreg); ! 404: uint16 srcdata = fetchword(srcaddr); ! 405: int dstreg = (ipc->opcode >> 9) & 7; ! 406: uint16 dstdata = DATAREG(dstreg); ! 407: uint16 outdata = dstdata; ! 408: ! 409: outdata&= srcdata; ! 410: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 411: PC+= 2; ! 412: } ! 413: ! 414: void cpu_op_1328b(t_ipc *ipc) /* AND */ { ! 415: /* mask f1f8, bits c050, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 416: int srcreg = (ipc->opcode >> 0) & 7; ! 417: uint32 srcaddr = ADDRREG(srcreg); ! 418: uint16 srcdata = fetchword(srcaddr); ! 419: int dstreg = (ipc->opcode >> 9) & 7; ! 420: uint16 dstdata = DATAREG(dstreg); ! 421: uint16 outdata = dstdata; ! 422: ! 423: outdata&= srcdata; ! 424: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 425: ! 426: NFLAG = ((sint16)outdata) < 0; ! 427: ZFLAG = !outdata; ! 428: VFLAG = 0; ! 429: CFLAG = 0; ! 430: PC+= 2; ! 431: } ! 432: ! 433: void cpu_op_1329a(t_ipc *ipc) /* AND */ { ! 434: /* mask f1f8, bits c058, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 435: int srcreg = (ipc->opcode >> 0) & 7; ! 436: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2); ! 437: uint16 srcdata = fetchword(srcaddr); ! 438: int dstreg = (ipc->opcode >> 9) & 7; ! 439: uint16 dstdata = DATAREG(dstreg); ! 440: uint16 outdata = dstdata; ! 441: ! 442: outdata&= srcdata; ! 443: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 444: PC+= 2; ! 445: } ! 446: ! 447: void cpu_op_1329b(t_ipc *ipc) /* AND */ { ! 448: /* mask f1f8, bits c058, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 449: int srcreg = (ipc->opcode >> 0) & 7; ! 450: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2); ! 451: uint16 srcdata = fetchword(srcaddr); ! 452: int dstreg = (ipc->opcode >> 9) & 7; ! 453: uint16 dstdata = DATAREG(dstreg); ! 454: uint16 outdata = dstdata; ! 455: ! 456: outdata&= srcdata; ! 457: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 458: ! 459: NFLAG = ((sint16)outdata) < 0; ! 460: ZFLAG = !outdata; ! 461: VFLAG = 0; ! 462: CFLAG = 0; ! 463: PC+= 2; ! 464: } ! 465: ! 466: void cpu_op_1330a(t_ipc *ipc) /* AND */ { ! 467: /* mask f1f8, bits c060, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 468: int srcreg = (ipc->opcode >> 0) & 7; ! 469: uint32 srcaddr = ADDRREG(srcreg)-=2; ! 470: uint16 srcdata = fetchword(srcaddr); ! 471: int dstreg = (ipc->opcode >> 9) & 7; ! 472: uint16 dstdata = DATAREG(dstreg); ! 473: uint16 outdata = dstdata; ! 474: ! 475: outdata&= srcdata; ! 476: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 477: PC+= 2; ! 478: } ! 479: ! 480: void cpu_op_1330b(t_ipc *ipc) /* AND */ { ! 481: /* mask f1f8, bits c060, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 482: int srcreg = (ipc->opcode >> 0) & 7; ! 483: uint32 srcaddr = ADDRREG(srcreg)-=2; ! 484: uint16 srcdata = fetchword(srcaddr); ! 485: int dstreg = (ipc->opcode >> 9) & 7; ! 486: uint16 dstdata = DATAREG(dstreg); ! 487: uint16 outdata = dstdata; ! 488: ! 489: outdata&= srcdata; ! 490: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 491: ! 492: NFLAG = ((sint16)outdata) < 0; ! 493: ZFLAG = !outdata; ! 494: VFLAG = 0; ! 495: CFLAG = 0; ! 496: PC+= 2; ! 497: } ! 498: ! 499: void cpu_op_1331a(t_ipc *ipc) /* AND */ { ! 500: /* mask f1f8, bits c068, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 501: int srcreg = (ipc->opcode >> 0) & 7; ! 502: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 503: uint16 srcdata = fetchword(srcaddr); ! 504: int dstreg = (ipc->opcode >> 9) & 7; ! 505: uint16 dstdata = DATAREG(dstreg); ! 506: uint16 outdata = dstdata; ! 507: ! 508: outdata&= srcdata; ! 509: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 510: PC+= 4; ! 511: } ! 512: ! 513: void cpu_op_1331b(t_ipc *ipc) /* AND */ { ! 514: /* mask f1f8, bits c068, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 515: int srcreg = (ipc->opcode >> 0) & 7; ! 516: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 517: uint16 srcdata = fetchword(srcaddr); ! 518: int dstreg = (ipc->opcode >> 9) & 7; ! 519: uint16 dstdata = DATAREG(dstreg); ! 520: uint16 outdata = dstdata; ! 521: ! 522: outdata&= srcdata; ! 523: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 524: ! 525: NFLAG = ((sint16)outdata) < 0; ! 526: ZFLAG = !outdata; ! 527: VFLAG = 0; ! 528: CFLAG = 0; ! 529: PC+= 4; ! 530: } ! 531: ! 532: void cpu_op_1332a(t_ipc *ipc) /* AND */ { ! 533: /* mask f1f8, bits c070, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 534: int srcreg = (ipc->opcode >> 0) & 7; ! 535: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 536: uint16 srcdata = fetchword(srcaddr); ! 537: int dstreg = (ipc->opcode >> 9) & 7; ! 538: uint16 dstdata = DATAREG(dstreg); ! 539: uint16 outdata = dstdata; ! 540: ! 541: outdata&= srcdata; ! 542: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 543: PC+= 4; ! 544: } ! 545: ! 546: void cpu_op_1332b(t_ipc *ipc) /* AND */ { ! 547: /* mask f1f8, bits c070, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 548: int srcreg = (ipc->opcode >> 0) & 7; ! 549: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 550: uint16 srcdata = fetchword(srcaddr); ! 551: int dstreg = (ipc->opcode >> 9) & 7; ! 552: uint16 dstdata = DATAREG(dstreg); ! 553: uint16 outdata = dstdata; ! 554: ! 555: outdata&= srcdata; ! 556: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 557: ! 558: NFLAG = ((sint16)outdata) < 0; ! 559: ZFLAG = !outdata; ! 560: VFLAG = 0; ! 561: CFLAG = 0; ! 562: PC+= 4; ! 563: } ! 564: ! 565: void cpu_op_1333a(t_ipc *ipc) /* AND */ { ! 566: /* mask f1ff, bits c078, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 567: uint32 srcaddr = ipc->src; ! 568: uint16 srcdata = fetchword(srcaddr); ! 569: int dstreg = (ipc->opcode >> 9) & 7; ! 570: uint16 dstdata = DATAREG(dstreg); ! 571: uint16 outdata = dstdata; ! 572: ! 573: outdata&= srcdata; ! 574: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 575: PC+= 4; ! 576: } ! 577: ! 578: void cpu_op_1333b(t_ipc *ipc) /* AND */ { ! 579: /* mask f1ff, bits c078, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 580: uint32 srcaddr = ipc->src; ! 581: uint16 srcdata = fetchword(srcaddr); ! 582: int dstreg = (ipc->opcode >> 9) & 7; ! 583: uint16 dstdata = DATAREG(dstreg); ! 584: uint16 outdata = dstdata; ! 585: ! 586: outdata&= srcdata; ! 587: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 588: ! 589: NFLAG = ((sint16)outdata) < 0; ! 590: ZFLAG = !outdata; ! 591: VFLAG = 0; ! 592: CFLAG = 0; ! 593: PC+= 4; ! 594: } ! 595: ! 596: void cpu_op_1334a(t_ipc *ipc) /* AND */ { ! 597: /* mask f1ff, bits c079, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 598: uint32 srcaddr = ipc->src; ! 599: uint16 srcdata = fetchword(srcaddr); ! 600: int dstreg = (ipc->opcode >> 9) & 7; ! 601: uint16 dstdata = DATAREG(dstreg); ! 602: uint16 outdata = dstdata; ! 603: ! 604: outdata&= srcdata; ! 605: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 606: PC+= 6; ! 607: } ! 608: ! 609: void cpu_op_1334b(t_ipc *ipc) /* AND */ { ! 610: /* mask f1ff, bits c079, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 611: uint32 srcaddr = ipc->src; ! 612: uint16 srcdata = fetchword(srcaddr); ! 613: int dstreg = (ipc->opcode >> 9) & 7; ! 614: uint16 dstdata = DATAREG(dstreg); ! 615: uint16 outdata = dstdata; ! 616: ! 617: outdata&= srcdata; ! 618: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 619: ! 620: NFLAG = ((sint16)outdata) < 0; ! 621: ZFLAG = !outdata; ! 622: VFLAG = 0; ! 623: CFLAG = 0; ! 624: PC+= 6; ! 625: } ! 626: ! 627: void cpu_op_1335a(t_ipc *ipc) /* AND */ { ! 628: /* mask f1ff, bits c07a, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 629: uint32 srcaddr = ipc->src; ! 630: uint16 srcdata = fetchword(srcaddr); ! 631: int dstreg = (ipc->opcode >> 9) & 7; ! 632: uint16 dstdata = DATAREG(dstreg); ! 633: uint16 outdata = dstdata; ! 634: ! 635: outdata&= srcdata; ! 636: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 637: PC+= 4; ! 638: } ! 639: ! 640: void cpu_op_1335b(t_ipc *ipc) /* AND */ { ! 641: /* mask f1ff, bits c07a, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 642: uint32 srcaddr = ipc->src; ! 643: uint16 srcdata = fetchword(srcaddr); ! 644: int dstreg = (ipc->opcode >> 9) & 7; ! 645: uint16 dstdata = DATAREG(dstreg); ! 646: uint16 outdata = dstdata; ! 647: ! 648: outdata&= srcdata; ! 649: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 650: ! 651: NFLAG = ((sint16)outdata) < 0; ! 652: ZFLAG = !outdata; ! 653: VFLAG = 0; ! 654: CFLAG = 0; ! 655: PC+= 4; ! 656: } ! 657: ! 658: void cpu_op_1336a(t_ipc *ipc) /* AND */ { ! 659: /* mask f1ff, bits c07b, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 660: uint32 srcaddr = idxval_src(ipc); ! 661: uint16 srcdata = fetchword(srcaddr); ! 662: int dstreg = (ipc->opcode >> 9) & 7; ! 663: uint16 dstdata = DATAREG(dstreg); ! 664: uint16 outdata = dstdata; ! 665: ! 666: outdata&= srcdata; ! 667: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 668: PC+= 4; ! 669: } ! 670: ! 671: void cpu_op_1336b(t_ipc *ipc) /* AND */ { ! 672: /* mask f1ff, bits c07b, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 673: uint32 srcaddr = idxval_src(ipc); ! 674: uint16 srcdata = fetchword(srcaddr); ! 675: int dstreg = (ipc->opcode >> 9) & 7; ! 676: uint16 dstdata = DATAREG(dstreg); ! 677: uint16 outdata = dstdata; ! 678: ! 679: outdata&= srcdata; ! 680: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 681: ! 682: NFLAG = ((sint16)outdata) < 0; ! 683: ZFLAG = !outdata; ! 684: VFLAG = 0; ! 685: CFLAG = 0; ! 686: PC+= 4; ! 687: } ! 688: ! 689: void cpu_op_1337a(t_ipc *ipc) /* AND */ { ! 690: /* mask f1ff, bits c07c, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 691: uint16 srcdata = ipc->src; ! 692: int dstreg = (ipc->opcode >> 9) & 7; ! 693: uint16 dstdata = DATAREG(dstreg); ! 694: uint16 outdata = dstdata; ! 695: ! 696: outdata&= srcdata; ! 697: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 698: PC+= 4; ! 699: } ! 700: ! 701: void cpu_op_1337b(t_ipc *ipc) /* AND */ { ! 702: /* mask f1ff, bits c07c, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 703: uint16 srcdata = ipc->src; ! 704: int dstreg = (ipc->opcode >> 9) & 7; ! 705: uint16 dstdata = DATAREG(dstreg); ! 706: uint16 outdata = dstdata; ! 707: ! 708: outdata&= srcdata; ! 709: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 710: ! 711: NFLAG = ((sint16)outdata) < 0; ! 712: ZFLAG = !outdata; ! 713: VFLAG = 0; ! 714: CFLAG = 0; ! 715: PC+= 4; ! 716: } ! 717: ! 718: void cpu_op_1338a(t_ipc *ipc) /* AND */ { ! 719: /* mask f1f8, bits c080, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 720: int srcreg = (ipc->opcode >> 0) & 7; ! 721: uint32 srcdata = DATAREG(srcreg); ! 722: int dstreg = (ipc->opcode >> 9) & 7; ! 723: uint32 dstdata = DATAREG(dstreg); ! 724: uint32 outdata = dstdata; ! 725: ! 726: outdata&= srcdata; ! 727: DATAREG(dstreg) = outdata; ! 728: PC+= 2; ! 729: } ! 730: ! 731: void cpu_op_1338b(t_ipc *ipc) /* AND */ { ! 732: /* mask f1f8, bits c080, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 733: int srcreg = (ipc->opcode >> 0) & 7; ! 734: uint32 srcdata = DATAREG(srcreg); ! 735: int dstreg = (ipc->opcode >> 9) & 7; ! 736: uint32 dstdata = DATAREG(dstreg); ! 737: uint32 outdata = dstdata; ! 738: ! 739: outdata&= srcdata; ! 740: DATAREG(dstreg) = outdata; ! 741: ! 742: NFLAG = ((sint32)outdata) < 0; ! 743: ZFLAG = !outdata; ! 744: VFLAG = 0; ! 745: CFLAG = 0; ! 746: PC+= 2; ! 747: } ! 748: ! 749: void cpu_op_1339a(t_ipc *ipc) /* AND */ { ! 750: /* mask f1f8, bits c090, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 751: int srcreg = (ipc->opcode >> 0) & 7; ! 752: uint32 srcaddr = ADDRREG(srcreg); ! 753: uint32 srcdata = fetchlong(srcaddr); ! 754: int dstreg = (ipc->opcode >> 9) & 7; ! 755: uint32 dstdata = DATAREG(dstreg); ! 756: uint32 outdata = dstdata; ! 757: ! 758: outdata&= srcdata; ! 759: DATAREG(dstreg) = outdata; ! 760: PC+= 2; ! 761: } ! 762: ! 763: void cpu_op_1339b(t_ipc *ipc) /* AND */ { ! 764: /* mask f1f8, bits c090, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 765: int srcreg = (ipc->opcode >> 0) & 7; ! 766: uint32 srcaddr = ADDRREG(srcreg); ! 767: uint32 srcdata = fetchlong(srcaddr); ! 768: int dstreg = (ipc->opcode >> 9) & 7; ! 769: uint32 dstdata = DATAREG(dstreg); ! 770: uint32 outdata = dstdata; ! 771: ! 772: outdata&= srcdata; ! 773: DATAREG(dstreg) = outdata; ! 774: ! 775: NFLAG = ((sint32)outdata) < 0; ! 776: ZFLAG = !outdata; ! 777: VFLAG = 0; ! 778: CFLAG = 0; ! 779: PC+= 2; ! 780: } ! 781: ! 782: void cpu_op_1340a(t_ipc *ipc) /* AND */ { ! 783: /* mask f1f8, bits c098, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 784: int srcreg = (ipc->opcode >> 0) & 7; ! 785: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4); ! 786: uint32 srcdata = fetchlong(srcaddr); ! 787: int dstreg = (ipc->opcode >> 9) & 7; ! 788: uint32 dstdata = DATAREG(dstreg); ! 789: uint32 outdata = dstdata; ! 790: ! 791: outdata&= srcdata; ! 792: DATAREG(dstreg) = outdata; ! 793: PC+= 2; ! 794: } ! 795: ! 796: void cpu_op_1340b(t_ipc *ipc) /* AND */ { ! 797: /* mask f1f8, bits c098, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 798: int srcreg = (ipc->opcode >> 0) & 7; ! 799: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4); ! 800: uint32 srcdata = fetchlong(srcaddr); ! 801: int dstreg = (ipc->opcode >> 9) & 7; ! 802: uint32 dstdata = DATAREG(dstreg); ! 803: uint32 outdata = dstdata; ! 804: ! 805: outdata&= srcdata; ! 806: DATAREG(dstreg) = outdata; ! 807: ! 808: NFLAG = ((sint32)outdata) < 0; ! 809: ZFLAG = !outdata; ! 810: VFLAG = 0; ! 811: CFLAG = 0; ! 812: PC+= 2; ! 813: } ! 814: ! 815: void cpu_op_1341a(t_ipc *ipc) /* AND */ { ! 816: /* mask f1f8, bits c0a0, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 817: int srcreg = (ipc->opcode >> 0) & 7; ! 818: uint32 srcaddr = ADDRREG(srcreg)-=4; ! 819: uint32 srcdata = fetchlong(srcaddr); ! 820: int dstreg = (ipc->opcode >> 9) & 7; ! 821: uint32 dstdata = DATAREG(dstreg); ! 822: uint32 outdata = dstdata; ! 823: ! 824: outdata&= srcdata; ! 825: DATAREG(dstreg) = outdata; ! 826: PC+= 2; ! 827: } ! 828: ! 829: void cpu_op_1341b(t_ipc *ipc) /* AND */ { ! 830: /* mask f1f8, bits c0a0, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 831: int srcreg = (ipc->opcode >> 0) & 7; ! 832: uint32 srcaddr = ADDRREG(srcreg)-=4; ! 833: uint32 srcdata = fetchlong(srcaddr); ! 834: int dstreg = (ipc->opcode >> 9) & 7; ! 835: uint32 dstdata = DATAREG(dstreg); ! 836: uint32 outdata = dstdata; ! 837: ! 838: outdata&= srcdata; ! 839: DATAREG(dstreg) = outdata; ! 840: ! 841: NFLAG = ((sint32)outdata) < 0; ! 842: ZFLAG = !outdata; ! 843: VFLAG = 0; ! 844: CFLAG = 0; ! 845: PC+= 2; ! 846: } ! 847: ! 848: void cpu_op_1342a(t_ipc *ipc) /* AND */ { ! 849: /* mask f1f8, bits c0a8, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 850: int srcreg = (ipc->opcode >> 0) & 7; ! 851: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 852: uint32 srcdata = fetchlong(srcaddr); ! 853: int dstreg = (ipc->opcode >> 9) & 7; ! 854: uint32 dstdata = DATAREG(dstreg); ! 855: uint32 outdata = dstdata; ! 856: ! 857: outdata&= srcdata; ! 858: DATAREG(dstreg) = outdata; ! 859: PC+= 4; ! 860: } ! 861: ! 862: void cpu_op_1342b(t_ipc *ipc) /* AND */ { ! 863: /* mask f1f8, bits c0a8, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 864: int srcreg = (ipc->opcode >> 0) & 7; ! 865: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 866: uint32 srcdata = fetchlong(srcaddr); ! 867: int dstreg = (ipc->opcode >> 9) & 7; ! 868: uint32 dstdata = DATAREG(dstreg); ! 869: uint32 outdata = dstdata; ! 870: ! 871: outdata&= srcdata; ! 872: DATAREG(dstreg) = outdata; ! 873: ! 874: NFLAG = ((sint32)outdata) < 0; ! 875: ZFLAG = !outdata; ! 876: VFLAG = 0; ! 877: CFLAG = 0; ! 878: PC+= 4; ! 879: } ! 880: ! 881: void cpu_op_1343a(t_ipc *ipc) /* AND */ { ! 882: /* mask f1f8, bits c0b0, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 883: int srcreg = (ipc->opcode >> 0) & 7; ! 884: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 885: uint32 srcdata = fetchlong(srcaddr); ! 886: int dstreg = (ipc->opcode >> 9) & 7; ! 887: uint32 dstdata = DATAREG(dstreg); ! 888: uint32 outdata = dstdata; ! 889: ! 890: outdata&= srcdata; ! 891: DATAREG(dstreg) = outdata; ! 892: PC+= 4; ! 893: } ! 894: ! 895: void cpu_op_1343b(t_ipc *ipc) /* AND */ { ! 896: /* mask f1f8, bits c0b0, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 897: int srcreg = (ipc->opcode >> 0) & 7; ! 898: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 899: uint32 srcdata = fetchlong(srcaddr); ! 900: int dstreg = (ipc->opcode >> 9) & 7; ! 901: uint32 dstdata = DATAREG(dstreg); ! 902: uint32 outdata = dstdata; ! 903: ! 904: outdata&= srcdata; ! 905: DATAREG(dstreg) = outdata; ! 906: ! 907: NFLAG = ((sint32)outdata) < 0; ! 908: ZFLAG = !outdata; ! 909: VFLAG = 0; ! 910: CFLAG = 0; ! 911: PC+= 4; ! 912: } ! 913: ! 914: void cpu_op_1344a(t_ipc *ipc) /* AND */ { ! 915: /* mask f1ff, bits c0b8, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 916: uint32 srcaddr = ipc->src; ! 917: uint32 srcdata = fetchlong(srcaddr); ! 918: int dstreg = (ipc->opcode >> 9) & 7; ! 919: uint32 dstdata = DATAREG(dstreg); ! 920: uint32 outdata = dstdata; ! 921: ! 922: outdata&= srcdata; ! 923: DATAREG(dstreg) = outdata; ! 924: PC+= 4; ! 925: } ! 926: ! 927: void cpu_op_1344b(t_ipc *ipc) /* AND */ { ! 928: /* mask f1ff, bits c0b8, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 929: uint32 srcaddr = ipc->src; ! 930: uint32 srcdata = fetchlong(srcaddr); ! 931: int dstreg = (ipc->opcode >> 9) & 7; ! 932: uint32 dstdata = DATAREG(dstreg); ! 933: uint32 outdata = dstdata; ! 934: ! 935: outdata&= srcdata; ! 936: DATAREG(dstreg) = outdata; ! 937: ! 938: NFLAG = ((sint32)outdata) < 0; ! 939: ZFLAG = !outdata; ! 940: VFLAG = 0; ! 941: CFLAG = 0; ! 942: PC+= 4; ! 943: } ! 944: ! 945: void cpu_op_1345a(t_ipc *ipc) /* AND */ { ! 946: /* mask f1ff, bits c0b9, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 947: uint32 srcaddr = ipc->src; ! 948: uint32 srcdata = fetchlong(srcaddr); ! 949: int dstreg = (ipc->opcode >> 9) & 7; ! 950: uint32 dstdata = DATAREG(dstreg); ! 951: uint32 outdata = dstdata; ! 952: ! 953: outdata&= srcdata; ! 954: DATAREG(dstreg) = outdata; ! 955: PC+= 6; ! 956: } ! 957: ! 958: void cpu_op_1345b(t_ipc *ipc) /* AND */ { ! 959: /* mask f1ff, bits c0b9, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 960: uint32 srcaddr = ipc->src; ! 961: uint32 srcdata = fetchlong(srcaddr); ! 962: int dstreg = (ipc->opcode >> 9) & 7; ! 963: uint32 dstdata = DATAREG(dstreg); ! 964: uint32 outdata = dstdata; ! 965: ! 966: outdata&= srcdata; ! 967: DATAREG(dstreg) = outdata; ! 968: ! 969: NFLAG = ((sint32)outdata) < 0; ! 970: ZFLAG = !outdata; ! 971: VFLAG = 0; ! 972: CFLAG = 0; ! 973: PC+= 6; ! 974: } ! 975: ! 976: void cpu_op_1346a(t_ipc *ipc) /* AND */ { ! 977: /* mask f1ff, bits c0ba, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 978: uint32 srcaddr = ipc->src; ! 979: uint32 srcdata = fetchlong(srcaddr); ! 980: int dstreg = (ipc->opcode >> 9) & 7; ! 981: uint32 dstdata = DATAREG(dstreg); ! 982: uint32 outdata = dstdata; ! 983: ! 984: outdata&= srcdata; ! 985: DATAREG(dstreg) = outdata; ! 986: PC+= 4; ! 987: } ! 988: ! 989: void cpu_op_1346b(t_ipc *ipc) /* AND */ { ! 990: /* mask f1ff, bits c0ba, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 991: uint32 srcaddr = ipc->src; ! 992: uint32 srcdata = fetchlong(srcaddr); ! 993: int dstreg = (ipc->opcode >> 9) & 7; ! 994: uint32 dstdata = DATAREG(dstreg); ! 995: uint32 outdata = dstdata; ! 996: ! 997: outdata&= srcdata; ! 998: DATAREG(dstreg) = outdata; ! 999: ! 1000: NFLAG = ((sint32)outdata) < 0; ! 1001: ZFLAG = !outdata; ! 1002: VFLAG = 0; ! 1003: CFLAG = 0; ! 1004: PC+= 4; ! 1005: } ! 1006: ! 1007: void cpu_op_1347a(t_ipc *ipc) /* AND */ { ! 1008: /* mask f1ff, bits c0bb, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1009: uint32 srcaddr = idxval_src(ipc); ! 1010: uint32 srcdata = fetchlong(srcaddr); ! 1011: int dstreg = (ipc->opcode >> 9) & 7; ! 1012: uint32 dstdata = DATAREG(dstreg); ! 1013: uint32 outdata = dstdata; ! 1014: ! 1015: outdata&= srcdata; ! 1016: DATAREG(dstreg) = outdata; ! 1017: PC+= 4; ! 1018: } ! 1019: ! 1020: void cpu_op_1347b(t_ipc *ipc) /* AND */ { ! 1021: /* mask f1ff, bits c0bb, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1022: uint32 srcaddr = idxval_src(ipc); ! 1023: uint32 srcdata = fetchlong(srcaddr); ! 1024: int dstreg = (ipc->opcode >> 9) & 7; ! 1025: uint32 dstdata = DATAREG(dstreg); ! 1026: uint32 outdata = dstdata; ! 1027: ! 1028: outdata&= srcdata; ! 1029: DATAREG(dstreg) = outdata; ! 1030: ! 1031: NFLAG = ((sint32)outdata) < 0; ! 1032: ZFLAG = !outdata; ! 1033: VFLAG = 0; ! 1034: CFLAG = 0; ! 1035: PC+= 4; ! 1036: } ! 1037: ! 1038: void cpu_op_1348a(t_ipc *ipc) /* AND */ { ! 1039: /* mask f1ff, bits c0bc, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1040: uint32 srcdata = ipc->src; ! 1041: int dstreg = (ipc->opcode >> 9) & 7; ! 1042: uint32 dstdata = DATAREG(dstreg); ! 1043: uint32 outdata = dstdata; ! 1044: ! 1045: outdata&= srcdata; ! 1046: DATAREG(dstreg) = outdata; ! 1047: PC+= 6; ! 1048: } ! 1049: ! 1050: void cpu_op_1348b(t_ipc *ipc) /* AND */ { ! 1051: /* mask f1ff, bits c0bc, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1052: uint32 srcdata = ipc->src; ! 1053: int dstreg = (ipc->opcode >> 9) & 7; ! 1054: uint32 dstdata = DATAREG(dstreg); ! 1055: uint32 outdata = dstdata; ! 1056: ! 1057: outdata&= srcdata; ! 1058: DATAREG(dstreg) = outdata; ! 1059: ! 1060: NFLAG = ((sint32)outdata) < 0; ! 1061: ZFLAG = !outdata; ! 1062: VFLAG = 0; ! 1063: CFLAG = 0; ! 1064: PC+= 6; ! 1065: } ! 1066: ! 1067: void cpu_op_1349a(t_ipc *ipc) /* AND */ { ! 1068: /* mask f1f8, bits c110, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1069: int srcreg = (ipc->opcode >> 9) & 7; ! 1070: uint8 srcdata = DATAREG(srcreg); ! 1071: int dstreg = (ipc->opcode >> 0) & 7; ! 1072: uint32 dstaddr = ADDRREG(dstreg); ! 1073: uint8 dstdata = fetchbyte(dstaddr); ! 1074: uint8 outdata = dstdata; ! 1075: ! 1076: outdata&= srcdata; ! 1077: storebyte(dstaddr, outdata); ! 1078: PC+= 2; ! 1079: } ! 1080: ! 1081: void cpu_op_1349b(t_ipc *ipc) /* AND */ { ! 1082: /* mask f1f8, bits c110, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1083: int srcreg = (ipc->opcode >> 9) & 7; ! 1084: uint8 srcdata = DATAREG(srcreg); ! 1085: int dstreg = (ipc->opcode >> 0) & 7; ! 1086: uint32 dstaddr = ADDRREG(dstreg); ! 1087: uint8 dstdata = fetchbyte(dstaddr); ! 1088: uint8 outdata = dstdata; ! 1089: ! 1090: outdata&= srcdata; ! 1091: storebyte(dstaddr, outdata); ! 1092: ! 1093: NFLAG = ((sint8)outdata) < 0; ! 1094: ZFLAG = !outdata; ! 1095: VFLAG = 0; ! 1096: CFLAG = 0; ! 1097: PC+= 2; ! 1098: } ! 1099: ! 1100: void cpu_op_1350a(t_ipc *ipc) /* AND */ { ! 1101: /* mask f1f8, bits c118, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1102: int srcreg = (ipc->opcode >> 9) & 7; ! 1103: uint8 srcdata = DATAREG(srcreg); ! 1104: int dstreg = (ipc->opcode >> 0) & 7; ! 1105: uint32 dstaddr = ADDRREG(dstreg); ! 1106: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0); ! 1107: uint8 dstdata = fetchbyte(dstaddr); ! 1108: uint8 outdata = dstdata; ! 1109: ! 1110: outdata&= srcdata; ! 1111: storebyte(dstaddr, outdata); ! 1112: PC+= 2; ! 1113: } ! 1114: ! 1115: void cpu_op_1350b(t_ipc *ipc) /* AND */ { ! 1116: /* mask f1f8, bits c118, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1117: int srcreg = (ipc->opcode >> 9) & 7; ! 1118: uint8 srcdata = DATAREG(srcreg); ! 1119: int dstreg = (ipc->opcode >> 0) & 7; ! 1120: uint32 dstaddr = ADDRREG(dstreg); ! 1121: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0); ! 1122: uint8 dstdata = fetchbyte(dstaddr); ! 1123: uint8 outdata = dstdata; ! 1124: ! 1125: outdata&= srcdata; ! 1126: storebyte(dstaddr, outdata); ! 1127: ! 1128: NFLAG = ((sint8)outdata) < 0; ! 1129: ZFLAG = !outdata; ! 1130: VFLAG = 0; ! 1131: CFLAG = 0; ! 1132: PC+= 2; ! 1133: } ! 1134: ! 1135: void cpu_op_1351a(t_ipc *ipc) /* AND */ { ! 1136: /* mask f1f8, bits c120, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1137: int srcreg = (ipc->opcode >> 9) & 7; ! 1138: uint8 srcdata = DATAREG(srcreg); ! 1139: int dstreg = (ipc->opcode >> 0) & 7; ! 1140: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1)); ! 1141: uint8 dstdata = fetchbyte(dstaddr); ! 1142: uint8 outdata = dstdata; ! 1143: ! 1144: outdata&= srcdata; ! 1145: storebyte(dstaddr, outdata); ! 1146: PC+= 2; ! 1147: } ! 1148: ! 1149: void cpu_op_1351b(t_ipc *ipc) /* AND */ { ! 1150: /* mask f1f8, bits c120, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1151: int srcreg = (ipc->opcode >> 9) & 7; ! 1152: uint8 srcdata = DATAREG(srcreg); ! 1153: int dstreg = (ipc->opcode >> 0) & 7; ! 1154: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1)); ! 1155: uint8 dstdata = fetchbyte(dstaddr); ! 1156: uint8 outdata = dstdata; ! 1157: ! 1158: outdata&= srcdata; ! 1159: storebyte(dstaddr, outdata); ! 1160: ! 1161: NFLAG = ((sint8)outdata) < 0; ! 1162: ZFLAG = !outdata; ! 1163: VFLAG = 0; ! 1164: CFLAG = 0; ! 1165: PC+= 2; ! 1166: } ! 1167: ! 1168: void cpu_op_1352a(t_ipc *ipc) /* AND */ { ! 1169: /* mask f1f8, bits c128, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1170: int srcreg = (ipc->opcode >> 9) & 7; ! 1171: uint8 srcdata = DATAREG(srcreg); ! 1172: int dstreg = (ipc->opcode >> 0) & 7; ! 1173: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst; ! 1174: uint8 dstdata = fetchbyte(dstaddr); ! 1175: uint8 outdata = dstdata; ! 1176: ! 1177: outdata&= srcdata; ! 1178: storebyte(dstaddr, outdata); ! 1179: PC+= 4; ! 1180: } ! 1181: ! 1182: void cpu_op_1352b(t_ipc *ipc) /* AND */ { ! 1183: /* mask f1f8, bits c128, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1184: int srcreg = (ipc->opcode >> 9) & 7; ! 1185: uint8 srcdata = DATAREG(srcreg); ! 1186: int dstreg = (ipc->opcode >> 0) & 7; ! 1187: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst; ! 1188: uint8 dstdata = fetchbyte(dstaddr); ! 1189: uint8 outdata = dstdata; ! 1190: ! 1191: outdata&= srcdata; ! 1192: storebyte(dstaddr, outdata); ! 1193: ! 1194: NFLAG = ((sint8)outdata) < 0; ! 1195: ZFLAG = !outdata; ! 1196: VFLAG = 0; ! 1197: CFLAG = 0; ! 1198: PC+= 4; ! 1199: } ! 1200: ! 1201: void cpu_op_1353a(t_ipc *ipc) /* AND */ { ! 1202: /* mask f1f8, bits c130, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1203: int srcreg = (ipc->opcode >> 9) & 7; ! 1204: uint8 srcdata = DATAREG(srcreg); ! 1205: int dstreg = (ipc->opcode >> 0) & 7; ! 1206: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc); ! 1207: uint8 dstdata = fetchbyte(dstaddr); ! 1208: uint8 outdata = dstdata; ! 1209: ! 1210: outdata&= srcdata; ! 1211: storebyte(dstaddr, outdata); ! 1212: PC+= 4; ! 1213: } ! 1214: ! 1215: void cpu_op_1353b(t_ipc *ipc) /* AND */ { ! 1216: /* mask f1f8, bits c130, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1217: int srcreg = (ipc->opcode >> 9) & 7; ! 1218: uint8 srcdata = DATAREG(srcreg); ! 1219: int dstreg = (ipc->opcode >> 0) & 7; ! 1220: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc); ! 1221: uint8 dstdata = fetchbyte(dstaddr); ! 1222: uint8 outdata = dstdata; ! 1223: ! 1224: outdata&= srcdata; ! 1225: storebyte(dstaddr, outdata); ! 1226: ! 1227: NFLAG = ((sint8)outdata) < 0; ! 1228: ZFLAG = !outdata; ! 1229: VFLAG = 0; ! 1230: CFLAG = 0; ! 1231: PC+= 4; ! 1232: } ! 1233: ! 1234: void cpu_op_1354a(t_ipc *ipc) /* AND */ { ! 1235: /* mask f1ff, bits c138, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1236: int srcreg = (ipc->opcode >> 9) & 7; ! 1237: uint8 srcdata = DATAREG(srcreg); ! 1238: uint32 dstaddr = ipc->dst; ! 1239: uint8 dstdata = fetchbyte(dstaddr); ! 1240: uint8 outdata = dstdata; ! 1241: ! 1242: outdata&= srcdata; ! 1243: storebyte(dstaddr, outdata); ! 1244: PC+= 4; ! 1245: } ! 1246: ! 1247: void cpu_op_1354b(t_ipc *ipc) /* AND */ { ! 1248: /* mask f1ff, bits c138, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1249: int srcreg = (ipc->opcode >> 9) & 7; ! 1250: uint8 srcdata = DATAREG(srcreg); ! 1251: uint32 dstaddr = ipc->dst; ! 1252: uint8 dstdata = fetchbyte(dstaddr); ! 1253: uint8 outdata = dstdata; ! 1254: ! 1255: outdata&= srcdata; ! 1256: storebyte(dstaddr, outdata); ! 1257: ! 1258: NFLAG = ((sint8)outdata) < 0; ! 1259: ZFLAG = !outdata; ! 1260: VFLAG = 0; ! 1261: CFLAG = 0; ! 1262: PC+= 4; ! 1263: } ! 1264: ! 1265: void cpu_op_1355a(t_ipc *ipc) /* AND */ { ! 1266: /* mask f1ff, bits c139, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1267: int srcreg = (ipc->opcode >> 9) & 7; ! 1268: uint8 srcdata = DATAREG(srcreg); ! 1269: uint32 dstaddr = ipc->dst; ! 1270: uint8 dstdata = fetchbyte(dstaddr); ! 1271: uint8 outdata = dstdata; ! 1272: ! 1273: outdata&= srcdata; ! 1274: storebyte(dstaddr, outdata); ! 1275: PC+= 6; ! 1276: } ! 1277: ! 1278: void cpu_op_1355b(t_ipc *ipc) /* AND */ { ! 1279: /* mask f1ff, bits c139, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 1, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1280: int srcreg = (ipc->opcode >> 9) & 7; ! 1281: uint8 srcdata = DATAREG(srcreg); ! 1282: uint32 dstaddr = ipc->dst; ! 1283: uint8 dstdata = fetchbyte(dstaddr); ! 1284: uint8 outdata = dstdata; ! 1285: ! 1286: outdata&= srcdata; ! 1287: storebyte(dstaddr, outdata); ! 1288: ! 1289: NFLAG = ((sint8)outdata) < 0; ! 1290: ZFLAG = !outdata; ! 1291: VFLAG = 0; ! 1292: CFLAG = 0; ! 1293: PC+= 6; ! 1294: } ! 1295: ! 1296: void cpu_op_1356a(t_ipc *ipc) /* AND */ { ! 1297: /* mask f1f8, bits c150, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1298: int srcreg = (ipc->opcode >> 9) & 7; ! 1299: uint16 srcdata = DATAREG(srcreg); ! 1300: int dstreg = (ipc->opcode >> 0) & 7; ! 1301: uint32 dstaddr = ADDRREG(dstreg); ! 1302: uint16 dstdata = fetchword(dstaddr); ! 1303: uint16 outdata = dstdata; ! 1304: ! 1305: outdata&= srcdata; ! 1306: storeword(dstaddr, outdata); ! 1307: PC+= 2; ! 1308: } ! 1309: ! 1310: void cpu_op_1356b(t_ipc *ipc) /* AND */ { ! 1311: /* mask f1f8, bits c150, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1312: int srcreg = (ipc->opcode >> 9) & 7; ! 1313: uint16 srcdata = DATAREG(srcreg); ! 1314: int dstreg = (ipc->opcode >> 0) & 7; ! 1315: uint32 dstaddr = ADDRREG(dstreg); ! 1316: uint16 dstdata = fetchword(dstaddr); ! 1317: uint16 outdata = dstdata; ! 1318: ! 1319: outdata&= srcdata; ! 1320: storeword(dstaddr, outdata); ! 1321: ! 1322: NFLAG = ((sint16)outdata) < 0; ! 1323: ZFLAG = !outdata; ! 1324: VFLAG = 0; ! 1325: CFLAG = 0; ! 1326: PC+= 2; ! 1327: } ! 1328: ! 1329: void cpu_op_1357a(t_ipc *ipc) /* AND */ { ! 1330: /* mask f1f8, bits c158, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1331: int srcreg = (ipc->opcode >> 9) & 7; ! 1332: uint16 srcdata = DATAREG(srcreg); ! 1333: int dstreg = (ipc->opcode >> 0) & 7; ! 1334: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2); ! 1335: uint16 dstdata = fetchword(dstaddr); ! 1336: uint16 outdata = dstdata; ! 1337: ! 1338: outdata&= srcdata; ! 1339: storeword(dstaddr, outdata); ! 1340: PC+= 2; ! 1341: } ! 1342: ! 1343: void cpu_op_1357b(t_ipc *ipc) /* AND */ { ! 1344: /* mask f1f8, bits c158, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1345: int srcreg = (ipc->opcode >> 9) & 7; ! 1346: uint16 srcdata = DATAREG(srcreg); ! 1347: int dstreg = (ipc->opcode >> 0) & 7; ! 1348: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2); ! 1349: uint16 dstdata = fetchword(dstaddr); ! 1350: uint16 outdata = dstdata; ! 1351: ! 1352: outdata&= srcdata; ! 1353: storeword(dstaddr, outdata); ! 1354: ! 1355: NFLAG = ((sint16)outdata) < 0; ! 1356: ZFLAG = !outdata; ! 1357: VFLAG = 0; ! 1358: CFLAG = 0; ! 1359: PC+= 2; ! 1360: } ! 1361: ! 1362: void cpu_op_1358a(t_ipc *ipc) /* AND */ { ! 1363: /* mask f1f8, bits c160, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1364: int srcreg = (ipc->opcode >> 9) & 7; ! 1365: uint16 srcdata = DATAREG(srcreg); ! 1366: int dstreg = (ipc->opcode >> 0) & 7; ! 1367: uint32 dstaddr = ADDRREG(dstreg)-=2; ! 1368: uint16 dstdata = fetchword(dstaddr); ! 1369: uint16 outdata = dstdata; ! 1370: ! 1371: outdata&= srcdata; ! 1372: storeword(dstaddr, outdata); ! 1373: PC+= 2; ! 1374: } ! 1375: ! 1376: void cpu_op_1358b(t_ipc *ipc) /* AND */ { ! 1377: /* mask f1f8, bits c160, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1378: int srcreg = (ipc->opcode >> 9) & 7; ! 1379: uint16 srcdata = DATAREG(srcreg); ! 1380: int dstreg = (ipc->opcode >> 0) & 7; ! 1381: uint32 dstaddr = ADDRREG(dstreg)-=2; ! 1382: uint16 dstdata = fetchword(dstaddr); ! 1383: uint16 outdata = dstdata; ! 1384: ! 1385: outdata&= srcdata; ! 1386: storeword(dstaddr, outdata); ! 1387: ! 1388: NFLAG = ((sint16)outdata) < 0; ! 1389: ZFLAG = !outdata; ! 1390: VFLAG = 0; ! 1391: CFLAG = 0; ! 1392: PC+= 2; ! 1393: } ! 1394: ! 1395: void cpu_op_1359a(t_ipc *ipc) /* AND */ { ! 1396: /* mask f1f8, bits c168, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1397: int srcreg = (ipc->opcode >> 9) & 7; ! 1398: uint16 srcdata = DATAREG(srcreg); ! 1399: int dstreg = (ipc->opcode >> 0) & 7; ! 1400: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst; ! 1401: uint16 dstdata = fetchword(dstaddr); ! 1402: uint16 outdata = dstdata; ! 1403: ! 1404: outdata&= srcdata; ! 1405: storeword(dstaddr, outdata); ! 1406: PC+= 4; ! 1407: } ! 1408: ! 1409: void cpu_op_1359b(t_ipc *ipc) /* AND */ { ! 1410: /* mask f1f8, bits c168, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1411: int srcreg = (ipc->opcode >> 9) & 7; ! 1412: uint16 srcdata = DATAREG(srcreg); ! 1413: int dstreg = (ipc->opcode >> 0) & 7; ! 1414: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst; ! 1415: uint16 dstdata = fetchword(dstaddr); ! 1416: uint16 outdata = dstdata; ! 1417: ! 1418: outdata&= srcdata; ! 1419: storeword(dstaddr, outdata); ! 1420: ! 1421: NFLAG = ((sint16)outdata) < 0; ! 1422: ZFLAG = !outdata; ! 1423: VFLAG = 0; ! 1424: CFLAG = 0; ! 1425: PC+= 4; ! 1426: } ! 1427: ! 1428: void cpu_op_1360a(t_ipc *ipc) /* AND */ { ! 1429: /* mask f1f8, bits c170, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1430: int srcreg = (ipc->opcode >> 9) & 7; ! 1431: uint16 srcdata = DATAREG(srcreg); ! 1432: int dstreg = (ipc->opcode >> 0) & 7; ! 1433: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc); ! 1434: uint16 dstdata = fetchword(dstaddr); ! 1435: uint16 outdata = dstdata; ! 1436: ! 1437: outdata&= srcdata; ! 1438: storeword(dstaddr, outdata); ! 1439: PC+= 4; ! 1440: } ! 1441: ! 1442: void cpu_op_1360b(t_ipc *ipc) /* AND */ { ! 1443: /* mask f1f8, bits c170, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1444: int srcreg = (ipc->opcode >> 9) & 7; ! 1445: uint16 srcdata = DATAREG(srcreg); ! 1446: int dstreg = (ipc->opcode >> 0) & 7; ! 1447: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc); ! 1448: uint16 dstdata = fetchword(dstaddr); ! 1449: uint16 outdata = dstdata; ! 1450: ! 1451: outdata&= srcdata; ! 1452: storeword(dstaddr, outdata); ! 1453: ! 1454: NFLAG = ((sint16)outdata) < 0; ! 1455: ZFLAG = !outdata; ! 1456: VFLAG = 0; ! 1457: CFLAG = 0; ! 1458: PC+= 4; ! 1459: } ! 1460: ! 1461: void cpu_op_1361a(t_ipc *ipc) /* AND */ { ! 1462: /* mask f1ff, bits c178, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1463: int srcreg = (ipc->opcode >> 9) & 7; ! 1464: uint16 srcdata = DATAREG(srcreg); ! 1465: uint32 dstaddr = ipc->dst; ! 1466: uint16 dstdata = fetchword(dstaddr); ! 1467: uint16 outdata = dstdata; ! 1468: ! 1469: outdata&= srcdata; ! 1470: storeword(dstaddr, outdata); ! 1471: PC+= 4; ! 1472: } ! 1473: ! 1474: void cpu_op_1361b(t_ipc *ipc) /* AND */ { ! 1475: /* mask f1ff, bits c178, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1476: int srcreg = (ipc->opcode >> 9) & 7; ! 1477: uint16 srcdata = DATAREG(srcreg); ! 1478: uint32 dstaddr = ipc->dst; ! 1479: uint16 dstdata = fetchword(dstaddr); ! 1480: uint16 outdata = dstdata; ! 1481: ! 1482: outdata&= srcdata; ! 1483: storeword(dstaddr, outdata); ! 1484: ! 1485: NFLAG = ((sint16)outdata) < 0; ! 1486: ZFLAG = !outdata; ! 1487: VFLAG = 0; ! 1488: CFLAG = 0; ! 1489: PC+= 4; ! 1490: } ! 1491: ! 1492: void cpu_op_1362a(t_ipc *ipc) /* AND */ { ! 1493: /* mask f1ff, bits c179, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1494: int srcreg = (ipc->opcode >> 9) & 7; ! 1495: uint16 srcdata = DATAREG(srcreg); ! 1496: uint32 dstaddr = ipc->dst; ! 1497: uint16 dstdata = fetchword(dstaddr); ! 1498: uint16 outdata = dstdata; ! 1499: ! 1500: outdata&= srcdata; ! 1501: storeword(dstaddr, outdata); ! 1502: PC+= 6; ! 1503: } ! 1504: ! 1505: void cpu_op_1362b(t_ipc *ipc) /* AND */ { ! 1506: /* mask f1ff, bits c179, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1507: int srcreg = (ipc->opcode >> 9) & 7; ! 1508: uint16 srcdata = DATAREG(srcreg); ! 1509: uint32 dstaddr = ipc->dst; ! 1510: uint16 dstdata = fetchword(dstaddr); ! 1511: uint16 outdata = dstdata; ! 1512: ! 1513: outdata&= srcdata; ! 1514: storeword(dstaddr, outdata); ! 1515: ! 1516: NFLAG = ((sint16)outdata) < 0; ! 1517: ZFLAG = !outdata; ! 1518: VFLAG = 0; ! 1519: CFLAG = 0; ! 1520: PC+= 6; ! 1521: } ! 1522: ! 1523: void cpu_op_1363a(t_ipc *ipc) /* AND */ { ! 1524: /* mask f1f8, bits c190, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1525: int srcreg = (ipc->opcode >> 9) & 7; ! 1526: uint32 srcdata = DATAREG(srcreg); ! 1527: int dstreg = (ipc->opcode >> 0) & 7; ! 1528: uint32 dstaddr = ADDRREG(dstreg); ! 1529: uint32 dstdata = fetchlong(dstaddr); ! 1530: uint32 outdata = dstdata; ! 1531: ! 1532: outdata&= srcdata; ! 1533: storelong(dstaddr, outdata); ! 1534: PC+= 2; ! 1535: } ! 1536: ! 1537: void cpu_op_1363b(t_ipc *ipc) /* AND */ { ! 1538: /* mask f1f8, bits c190, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1539: int srcreg = (ipc->opcode >> 9) & 7; ! 1540: uint32 srcdata = DATAREG(srcreg); ! 1541: int dstreg = (ipc->opcode >> 0) & 7; ! 1542: uint32 dstaddr = ADDRREG(dstreg); ! 1543: uint32 dstdata = fetchlong(dstaddr); ! 1544: uint32 outdata = dstdata; ! 1545: ! 1546: outdata&= srcdata; ! 1547: storelong(dstaddr, outdata); ! 1548: ! 1549: NFLAG = ((sint32)outdata) < 0; ! 1550: ZFLAG = !outdata; ! 1551: VFLAG = 0; ! 1552: CFLAG = 0; ! 1553: PC+= 2; ! 1554: } ! 1555: ! 1556: void cpu_op_1364a(t_ipc *ipc) /* AND */ { ! 1557: /* mask f1f8, bits c198, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1558: int srcreg = (ipc->opcode >> 9) & 7; ! 1559: uint32 srcdata = DATAREG(srcreg); ! 1560: int dstreg = (ipc->opcode >> 0) & 7; ! 1561: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4); ! 1562: uint32 dstdata = fetchlong(dstaddr); ! 1563: uint32 outdata = dstdata; ! 1564: ! 1565: outdata&= srcdata; ! 1566: storelong(dstaddr, outdata); ! 1567: PC+= 2; ! 1568: } ! 1569: ! 1570: void cpu_op_1364b(t_ipc *ipc) /* AND */ { ! 1571: /* mask f1f8, bits c198, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1572: int srcreg = (ipc->opcode >> 9) & 7; ! 1573: uint32 srcdata = DATAREG(srcreg); ! 1574: int dstreg = (ipc->opcode >> 0) & 7; ! 1575: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4); ! 1576: uint32 dstdata = fetchlong(dstaddr); ! 1577: uint32 outdata = dstdata; ! 1578: ! 1579: outdata&= srcdata; ! 1580: storelong(dstaddr, outdata); ! 1581: ! 1582: NFLAG = ((sint32)outdata) < 0; ! 1583: ZFLAG = !outdata; ! 1584: VFLAG = 0; ! 1585: CFLAG = 0; ! 1586: PC+= 2; ! 1587: } ! 1588: ! 1589: void cpu_op_1365a(t_ipc *ipc) /* AND */ { ! 1590: /* mask f1f8, bits c1a0, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1591: int srcreg = (ipc->opcode >> 9) & 7; ! 1592: uint32 srcdata = DATAREG(srcreg); ! 1593: int dstreg = (ipc->opcode >> 0) & 7; ! 1594: uint32 dstaddr = ADDRREG(dstreg)-=4; ! 1595: uint32 dstdata = fetchlong(dstaddr); ! 1596: uint32 outdata = dstdata; ! 1597: ! 1598: outdata&= srcdata; ! 1599: storelong(dstaddr, outdata); ! 1600: PC+= 2; ! 1601: } ! 1602: ! 1603: void cpu_op_1365b(t_ipc *ipc) /* AND */ { ! 1604: /* mask f1f8, bits c1a0, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1605: int srcreg = (ipc->opcode >> 9) & 7; ! 1606: uint32 srcdata = DATAREG(srcreg); ! 1607: int dstreg = (ipc->opcode >> 0) & 7; ! 1608: uint32 dstaddr = ADDRREG(dstreg)-=4; ! 1609: uint32 dstdata = fetchlong(dstaddr); ! 1610: uint32 outdata = dstdata; ! 1611: ! 1612: outdata&= srcdata; ! 1613: storelong(dstaddr, outdata); ! 1614: ! 1615: NFLAG = ((sint32)outdata) < 0; ! 1616: ZFLAG = !outdata; ! 1617: VFLAG = 0; ! 1618: CFLAG = 0; ! 1619: PC+= 2; ! 1620: } ! 1621: ! 1622: void cpu_op_1366a(t_ipc *ipc) /* AND */ { ! 1623: /* mask f1f8, bits c1a8, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1624: int srcreg = (ipc->opcode >> 9) & 7; ! 1625: uint32 srcdata = DATAREG(srcreg); ! 1626: int dstreg = (ipc->opcode >> 0) & 7; ! 1627: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst; ! 1628: uint32 dstdata = fetchlong(dstaddr); ! 1629: uint32 outdata = dstdata; ! 1630: ! 1631: outdata&= srcdata; ! 1632: storelong(dstaddr, outdata); ! 1633: PC+= 4; ! 1634: } ! 1635: ! 1636: void cpu_op_1366b(t_ipc *ipc) /* AND */ { ! 1637: /* mask f1f8, bits c1a8, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1638: int srcreg = (ipc->opcode >> 9) & 7; ! 1639: uint32 srcdata = DATAREG(srcreg); ! 1640: int dstreg = (ipc->opcode >> 0) & 7; ! 1641: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst; ! 1642: uint32 dstdata = fetchlong(dstaddr); ! 1643: uint32 outdata = dstdata; ! 1644: ! 1645: outdata&= srcdata; ! 1646: storelong(dstaddr, outdata); ! 1647: ! 1648: NFLAG = ((sint32)outdata) < 0; ! 1649: ZFLAG = !outdata; ! 1650: VFLAG = 0; ! 1651: CFLAG = 0; ! 1652: PC+= 4; ! 1653: } ! 1654: ! 1655: void cpu_op_1367a(t_ipc *ipc) /* AND */ { ! 1656: /* mask f1f8, bits c1b0, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1657: int srcreg = (ipc->opcode >> 9) & 7; ! 1658: uint32 srcdata = DATAREG(srcreg); ! 1659: int dstreg = (ipc->opcode >> 0) & 7; ! 1660: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc); ! 1661: uint32 dstdata = fetchlong(dstaddr); ! 1662: uint32 outdata = dstdata; ! 1663: ! 1664: outdata&= srcdata; ! 1665: storelong(dstaddr, outdata); ! 1666: PC+= 4; ! 1667: } ! 1668: ! 1669: void cpu_op_1367b(t_ipc *ipc) /* AND */ { ! 1670: /* mask f1f8, bits c1b0, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1671: int srcreg = (ipc->opcode >> 9) & 7; ! 1672: uint32 srcdata = DATAREG(srcreg); ! 1673: int dstreg = (ipc->opcode >> 0) & 7; ! 1674: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc); ! 1675: uint32 dstdata = fetchlong(dstaddr); ! 1676: uint32 outdata = dstdata; ! 1677: ! 1678: outdata&= srcdata; ! 1679: storelong(dstaddr, outdata); ! 1680: ! 1681: NFLAG = ((sint32)outdata) < 0; ! 1682: ZFLAG = !outdata; ! 1683: VFLAG = 0; ! 1684: CFLAG = 0; ! 1685: PC+= 4; ! 1686: } ! 1687: ! 1688: void cpu_op_1368a(t_ipc *ipc) /* AND */ { ! 1689: /* mask f1ff, bits c1b8, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1690: int srcreg = (ipc->opcode >> 9) & 7; ! 1691: uint32 srcdata = DATAREG(srcreg); ! 1692: uint32 dstaddr = ipc->dst; ! 1693: uint32 dstdata = fetchlong(dstaddr); ! 1694: uint32 outdata = dstdata; ! 1695: ! 1696: outdata&= srcdata; ! 1697: storelong(dstaddr, outdata); ! 1698: PC+= 4; ! 1699: } ! 1700: ! 1701: void cpu_op_1368b(t_ipc *ipc) /* AND */ { ! 1702: /* mask f1ff, bits c1b8, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1703: int srcreg = (ipc->opcode >> 9) & 7; ! 1704: uint32 srcdata = DATAREG(srcreg); ! 1705: uint32 dstaddr = ipc->dst; ! 1706: uint32 dstdata = fetchlong(dstaddr); ! 1707: uint32 outdata = dstdata; ! 1708: ! 1709: outdata&= srcdata; ! 1710: storelong(dstaddr, outdata); ! 1711: ! 1712: NFLAG = ((sint32)outdata) < 0; ! 1713: ZFLAG = !outdata; ! 1714: VFLAG = 0; ! 1715: CFLAG = 0; ! 1716: PC+= 4; ! 1717: } ! 1718: ! 1719: void cpu_op_1369a(t_ipc *ipc) /* AND */ { ! 1720: /* mask f1ff, bits c1b9, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1721: int srcreg = (ipc->opcode >> 9) & 7; ! 1722: uint32 srcdata = DATAREG(srcreg); ! 1723: uint32 dstaddr = ipc->dst; ! 1724: uint32 dstdata = fetchlong(dstaddr); ! 1725: uint32 outdata = dstdata; ! 1726: ! 1727: outdata&= srcdata; ! 1728: storelong(dstaddr, outdata); ! 1729: PC+= 6; ! 1730: } ! 1731: ! 1732: void cpu_op_1369b(t_ipc *ipc) /* AND */ { ! 1733: /* mask f1ff, bits c1b9, mnemonic 3, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 3, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1734: int srcreg = (ipc->opcode >> 9) & 7; ! 1735: uint32 srcdata = DATAREG(srcreg); ! 1736: uint32 dstaddr = ipc->dst; ! 1737: uint32 dstdata = fetchlong(dstaddr); ! 1738: uint32 outdata = dstdata; ! 1739: ! 1740: outdata&= srcdata; ! 1741: storelong(dstaddr, outdata); ! 1742: ! 1743: NFLAG = ((sint32)outdata) < 0; ! 1744: ZFLAG = !outdata; ! 1745: VFLAG = 0; ! 1746: CFLAG = 0; ! 1747: PC+= 6; ! 1748: } ! 1749: ! 1750: void cpu_op_1370a(t_ipc *ipc) /* MULU */ { ! 1751: /* mask f1f8, bits c0c0, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1752: int srcreg = (ipc->opcode >> 0) & 7; ! 1753: uint16 srcdata = DATAREG(srcreg); ! 1754: int dstreg = (ipc->opcode >> 9) & 7; ! 1755: uint16 dstdata = DATAREG(dstreg); ! 1756: ! 1757: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1758: DATAREG(dstreg) = outdata; ! 1759: PC+= 2; ! 1760: } ! 1761: ! 1762: void cpu_op_1370b(t_ipc *ipc) /* MULU */ { ! 1763: /* mask f1f8, bits c0c0, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1764: int srcreg = (ipc->opcode >> 0) & 7; ! 1765: uint16 srcdata = DATAREG(srcreg); ! 1766: int dstreg = (ipc->opcode >> 9) & 7; ! 1767: uint16 dstdata = DATAREG(dstreg); ! 1768: ! 1769: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1770: DATAREG(dstreg) = outdata; ! 1771: ! 1772: NFLAG = ((sint32)outdata) < 0; ! 1773: ZFLAG = !outdata; ! 1774: VFLAG = 0; ! 1775: CFLAG = 0; ! 1776: PC+= 2; ! 1777: } ! 1778: ! 1779: void cpu_op_1371a(t_ipc *ipc) /* MULU */ { ! 1780: /* mask f1f8, bits c0d0, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1781: int srcreg = (ipc->opcode >> 0) & 7; ! 1782: uint32 srcaddr = ADDRREG(srcreg); ! 1783: uint16 srcdata = fetchword(srcaddr); ! 1784: int dstreg = (ipc->opcode >> 9) & 7; ! 1785: uint16 dstdata = DATAREG(dstreg); ! 1786: ! 1787: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1788: DATAREG(dstreg) = outdata; ! 1789: PC+= 2; ! 1790: } ! 1791: ! 1792: void cpu_op_1371b(t_ipc *ipc) /* MULU */ { ! 1793: /* mask f1f8, bits c0d0, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1794: int srcreg = (ipc->opcode >> 0) & 7; ! 1795: uint32 srcaddr = ADDRREG(srcreg); ! 1796: uint16 srcdata = fetchword(srcaddr); ! 1797: int dstreg = (ipc->opcode >> 9) & 7; ! 1798: uint16 dstdata = DATAREG(dstreg); ! 1799: ! 1800: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1801: DATAREG(dstreg) = outdata; ! 1802: ! 1803: NFLAG = ((sint32)outdata) < 0; ! 1804: ZFLAG = !outdata; ! 1805: VFLAG = 0; ! 1806: CFLAG = 0; ! 1807: PC+= 2; ! 1808: } ! 1809: ! 1810: void cpu_op_1372a(t_ipc *ipc) /* MULU */ { ! 1811: /* mask f1f8, bits c0d8, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1812: int srcreg = (ipc->opcode >> 0) & 7; ! 1813: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2); ! 1814: uint16 srcdata = fetchword(srcaddr); ! 1815: int dstreg = (ipc->opcode >> 9) & 7; ! 1816: uint16 dstdata = DATAREG(dstreg); ! 1817: ! 1818: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1819: DATAREG(dstreg) = outdata; ! 1820: PC+= 2; ! 1821: } ! 1822: ! 1823: void cpu_op_1372b(t_ipc *ipc) /* MULU */ { ! 1824: /* mask f1f8, bits c0d8, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1825: int srcreg = (ipc->opcode >> 0) & 7; ! 1826: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2); ! 1827: uint16 srcdata = fetchword(srcaddr); ! 1828: int dstreg = (ipc->opcode >> 9) & 7; ! 1829: uint16 dstdata = DATAREG(dstreg); ! 1830: ! 1831: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1832: DATAREG(dstreg) = outdata; ! 1833: ! 1834: NFLAG = ((sint32)outdata) < 0; ! 1835: ZFLAG = !outdata; ! 1836: VFLAG = 0; ! 1837: CFLAG = 0; ! 1838: PC+= 2; ! 1839: } ! 1840: ! 1841: void cpu_op_1373a(t_ipc *ipc) /* MULU */ { ! 1842: /* mask f1f8, bits c0e0, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1843: int srcreg = (ipc->opcode >> 0) & 7; ! 1844: uint32 srcaddr = ADDRREG(srcreg)-=2; ! 1845: uint16 srcdata = fetchword(srcaddr); ! 1846: int dstreg = (ipc->opcode >> 9) & 7; ! 1847: uint16 dstdata = DATAREG(dstreg); ! 1848: ! 1849: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1850: DATAREG(dstreg) = outdata; ! 1851: PC+= 2; ! 1852: } ! 1853: ! 1854: void cpu_op_1373b(t_ipc *ipc) /* MULU */ { ! 1855: /* mask f1f8, bits c0e0, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1856: int srcreg = (ipc->opcode >> 0) & 7; ! 1857: uint32 srcaddr = ADDRREG(srcreg)-=2; ! 1858: uint16 srcdata = fetchword(srcaddr); ! 1859: int dstreg = (ipc->opcode >> 9) & 7; ! 1860: uint16 dstdata = DATAREG(dstreg); ! 1861: ! 1862: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1863: DATAREG(dstreg) = outdata; ! 1864: ! 1865: NFLAG = ((sint32)outdata) < 0; ! 1866: ZFLAG = !outdata; ! 1867: VFLAG = 0; ! 1868: CFLAG = 0; ! 1869: PC+= 2; ! 1870: } ! 1871: ! 1872: void cpu_op_1374a(t_ipc *ipc) /* MULU */ { ! 1873: /* mask f1f8, bits c0e8, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1874: int srcreg = (ipc->opcode >> 0) & 7; ! 1875: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 1876: uint16 srcdata = fetchword(srcaddr); ! 1877: int dstreg = (ipc->opcode >> 9) & 7; ! 1878: uint16 dstdata = DATAREG(dstreg); ! 1879: ! 1880: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1881: DATAREG(dstreg) = outdata; ! 1882: PC+= 4; ! 1883: } ! 1884: ! 1885: void cpu_op_1374b(t_ipc *ipc) /* MULU */ { ! 1886: /* mask f1f8, bits c0e8, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1887: int srcreg = (ipc->opcode >> 0) & 7; ! 1888: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 1889: uint16 srcdata = fetchword(srcaddr); ! 1890: int dstreg = (ipc->opcode >> 9) & 7; ! 1891: uint16 dstdata = DATAREG(dstreg); ! 1892: ! 1893: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1894: DATAREG(dstreg) = outdata; ! 1895: ! 1896: NFLAG = ((sint32)outdata) < 0; ! 1897: ZFLAG = !outdata; ! 1898: VFLAG = 0; ! 1899: CFLAG = 0; ! 1900: PC+= 4; ! 1901: } ! 1902: ! 1903: void cpu_op_1375a(t_ipc *ipc) /* MULU */ { ! 1904: /* mask f1f8, bits c0f0, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1905: int srcreg = (ipc->opcode >> 0) & 7; ! 1906: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 1907: uint16 srcdata = fetchword(srcaddr); ! 1908: int dstreg = (ipc->opcode >> 9) & 7; ! 1909: uint16 dstdata = DATAREG(dstreg); ! 1910: ! 1911: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1912: DATAREG(dstreg) = outdata; ! 1913: PC+= 4; ! 1914: } ! 1915: ! 1916: void cpu_op_1375b(t_ipc *ipc) /* MULU */ { ! 1917: /* mask f1f8, bits c0f0, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1918: int srcreg = (ipc->opcode >> 0) & 7; ! 1919: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 1920: uint16 srcdata = fetchword(srcaddr); ! 1921: int dstreg = (ipc->opcode >> 9) & 7; ! 1922: uint16 dstdata = DATAREG(dstreg); ! 1923: ! 1924: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1925: DATAREG(dstreg) = outdata; ! 1926: ! 1927: NFLAG = ((sint32)outdata) < 0; ! 1928: ZFLAG = !outdata; ! 1929: VFLAG = 0; ! 1930: CFLAG = 0; ! 1931: PC+= 4; ! 1932: } ! 1933: ! 1934: void cpu_op_1376a(t_ipc *ipc) /* MULU */ { ! 1935: /* mask f1ff, bits c0f8, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1936: uint32 srcaddr = ipc->src; ! 1937: uint16 srcdata = fetchword(srcaddr); ! 1938: int dstreg = (ipc->opcode >> 9) & 7; ! 1939: uint16 dstdata = DATAREG(dstreg); ! 1940: ! 1941: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1942: DATAREG(dstreg) = outdata; ! 1943: PC+= 4; ! 1944: } ! 1945: ! 1946: void cpu_op_1376b(t_ipc *ipc) /* MULU */ { ! 1947: /* mask f1ff, bits c0f8, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1948: uint32 srcaddr = ipc->src; ! 1949: uint16 srcdata = fetchword(srcaddr); ! 1950: int dstreg = (ipc->opcode >> 9) & 7; ! 1951: uint16 dstdata = DATAREG(dstreg); ! 1952: ! 1953: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1954: DATAREG(dstreg) = outdata; ! 1955: ! 1956: NFLAG = ((sint32)outdata) < 0; ! 1957: ZFLAG = !outdata; ! 1958: VFLAG = 0; ! 1959: CFLAG = 0; ! 1960: PC+= 4; ! 1961: } ! 1962: ! 1963: void cpu_op_1377a(t_ipc *ipc) /* MULU */ { ! 1964: /* mask f1ff, bits c0f9, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1965: uint32 srcaddr = ipc->src; ! 1966: uint16 srcdata = fetchword(srcaddr); ! 1967: int dstreg = (ipc->opcode >> 9) & 7; ! 1968: uint16 dstdata = DATAREG(dstreg); ! 1969: ! 1970: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1971: DATAREG(dstreg) = outdata; ! 1972: PC+= 6; ! 1973: } ! 1974: ! 1975: void cpu_op_1377b(t_ipc *ipc) /* MULU */ { ! 1976: /* mask f1ff, bits c0f9, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1977: uint32 srcaddr = ipc->src; ! 1978: uint16 srcdata = fetchword(srcaddr); ! 1979: int dstreg = (ipc->opcode >> 9) & 7; ! 1980: uint16 dstdata = DATAREG(dstreg); ! 1981: ! 1982: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 1983: DATAREG(dstreg) = outdata; ! 1984: ! 1985: NFLAG = ((sint32)outdata) < 0; ! 1986: ZFLAG = !outdata; ! 1987: VFLAG = 0; ! 1988: CFLAG = 0; ! 1989: PC+= 6; ! 1990: } ! 1991: ! 1992: void cpu_op_1378a(t_ipc *ipc) /* MULU */ { ! 1993: /* mask f1ff, bits c0fa, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1994: uint32 srcaddr = ipc->src; ! 1995: uint16 srcdata = fetchword(srcaddr); ! 1996: int dstreg = (ipc->opcode >> 9) & 7; ! 1997: uint16 dstdata = DATAREG(dstreg); ! 1998: ! 1999: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 2000: DATAREG(dstreg) = outdata; ! 2001: PC+= 4; ! 2002: } ! 2003: ! 2004: void cpu_op_1378b(t_ipc *ipc) /* MULU */ { ! 2005: /* mask f1ff, bits c0fa, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2006: uint32 srcaddr = ipc->src; ! 2007: uint16 srcdata = fetchword(srcaddr); ! 2008: int dstreg = (ipc->opcode >> 9) & 7; ! 2009: uint16 dstdata = DATAREG(dstreg); ! 2010: ! 2011: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 2012: DATAREG(dstreg) = outdata; ! 2013: ! 2014: NFLAG = ((sint32)outdata) < 0; ! 2015: ZFLAG = !outdata; ! 2016: VFLAG = 0; ! 2017: CFLAG = 0; ! 2018: PC+= 4; ! 2019: } ! 2020: ! 2021: void cpu_op_1379a(t_ipc *ipc) /* MULU */ { ! 2022: /* mask f1ff, bits c0fb, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2023: uint32 srcaddr = idxval_src(ipc); ! 2024: uint16 srcdata = fetchword(srcaddr); ! 2025: int dstreg = (ipc->opcode >> 9) & 7; ! 2026: uint16 dstdata = DATAREG(dstreg); ! 2027: ! 2028: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 2029: DATAREG(dstreg) = outdata; ! 2030: PC+= 4; ! 2031: } ! 2032: ! 2033: void cpu_op_1379b(t_ipc *ipc) /* MULU */ { ! 2034: /* mask f1ff, bits c0fb, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2035: uint32 srcaddr = idxval_src(ipc); ! 2036: uint16 srcdata = fetchword(srcaddr); ! 2037: int dstreg = (ipc->opcode >> 9) & 7; ! 2038: uint16 dstdata = DATAREG(dstreg); ! 2039: ! 2040: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 2041: DATAREG(dstreg) = outdata; ! 2042: ! 2043: NFLAG = ((sint32)outdata) < 0; ! 2044: ZFLAG = !outdata; ! 2045: VFLAG = 0; ! 2046: CFLAG = 0; ! 2047: PC+= 4; ! 2048: } ! 2049: ! 2050: void cpu_op_1380a(t_ipc *ipc) /* MULU */ { ! 2051: /* mask f1ff, bits c0fc, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2052: uint16 srcdata = ipc->src; ! 2053: int dstreg = (ipc->opcode >> 9) & 7; ! 2054: uint16 dstdata = DATAREG(dstreg); ! 2055: ! 2056: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 2057: DATAREG(dstreg) = outdata; ! 2058: PC+= 4; ! 2059: } ! 2060: ! 2061: void cpu_op_1380b(t_ipc *ipc) /* MULU */ { ! 2062: /* mask f1ff, bits c0fc, mnemonic 13, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2063: uint16 srcdata = ipc->src; ! 2064: int dstreg = (ipc->opcode >> 9) & 7; ! 2065: uint16 dstdata = DATAREG(dstreg); ! 2066: ! 2067: uint32 outdata = (uint32)srcdata * (uint32)dstdata; ! 2068: DATAREG(dstreg) = outdata; ! 2069: ! 2070: NFLAG = ((sint32)outdata) < 0; ! 2071: ZFLAG = !outdata; ! 2072: VFLAG = 0; ! 2073: CFLAG = 0; ! 2074: PC+= 4; ! 2075: } ! 2076: ! 2077: void cpu_op_1381a(t_ipc *ipc) /* MULS */ { ! 2078: /* mask f1f8, bits c1c0, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2079: int srcreg = (ipc->opcode >> 0) & 7; ! 2080: uint16 srcdata = DATAREG(srcreg); ! 2081: int dstreg = (ipc->opcode >> 9) & 7; ! 2082: uint16 dstdata = DATAREG(dstreg); ! 2083: ! 2084: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2085: DATAREG(dstreg) = outdata; ! 2086: PC+= 2; ! 2087: } ! 2088: ! 2089: void cpu_op_1381b(t_ipc *ipc) /* MULS */ { ! 2090: /* mask f1f8, bits c1c0, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2091: int srcreg = (ipc->opcode >> 0) & 7; ! 2092: uint16 srcdata = DATAREG(srcreg); ! 2093: int dstreg = (ipc->opcode >> 9) & 7; ! 2094: uint16 dstdata = DATAREG(dstreg); ! 2095: ! 2096: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2097: DATAREG(dstreg) = outdata; ! 2098: ! 2099: NFLAG = ((sint32)outdata) < 0; ! 2100: ZFLAG = !outdata; ! 2101: VFLAG = 0; ! 2102: CFLAG = 0; ! 2103: PC+= 2; ! 2104: } ! 2105: ! 2106: void cpu_op_1382a(t_ipc *ipc) /* MULS */ { ! 2107: /* mask f1f8, bits c1d0, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2108: int srcreg = (ipc->opcode >> 0) & 7; ! 2109: uint32 srcaddr = ADDRREG(srcreg); ! 2110: uint16 srcdata = fetchword(srcaddr); ! 2111: int dstreg = (ipc->opcode >> 9) & 7; ! 2112: uint16 dstdata = DATAREG(dstreg); ! 2113: ! 2114: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2115: DATAREG(dstreg) = outdata; ! 2116: PC+= 2; ! 2117: } ! 2118: ! 2119: void cpu_op_1382b(t_ipc *ipc) /* MULS */ { ! 2120: /* mask f1f8, bits c1d0, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2121: int srcreg = (ipc->opcode >> 0) & 7; ! 2122: uint32 srcaddr = ADDRREG(srcreg); ! 2123: uint16 srcdata = fetchword(srcaddr); ! 2124: int dstreg = (ipc->opcode >> 9) & 7; ! 2125: uint16 dstdata = DATAREG(dstreg); ! 2126: ! 2127: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2128: DATAREG(dstreg) = outdata; ! 2129: ! 2130: NFLAG = ((sint32)outdata) < 0; ! 2131: ZFLAG = !outdata; ! 2132: VFLAG = 0; ! 2133: CFLAG = 0; ! 2134: PC+= 2; ! 2135: } ! 2136: ! 2137: void cpu_op_1383a(t_ipc *ipc) /* MULS */ { ! 2138: /* mask f1f8, bits c1d8, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2139: int srcreg = (ipc->opcode >> 0) & 7; ! 2140: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2); ! 2141: uint16 srcdata = fetchword(srcaddr); ! 2142: int dstreg = (ipc->opcode >> 9) & 7; ! 2143: uint16 dstdata = DATAREG(dstreg); ! 2144: ! 2145: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2146: DATAREG(dstreg) = outdata; ! 2147: PC+= 2; ! 2148: } ! 2149: ! 2150: void cpu_op_1383b(t_ipc *ipc) /* MULS */ { ! 2151: /* mask f1f8, bits c1d8, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2152: int srcreg = (ipc->opcode >> 0) & 7; ! 2153: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2); ! 2154: uint16 srcdata = fetchword(srcaddr); ! 2155: int dstreg = (ipc->opcode >> 9) & 7; ! 2156: uint16 dstdata = DATAREG(dstreg); ! 2157: ! 2158: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2159: DATAREG(dstreg) = outdata; ! 2160: ! 2161: NFLAG = ((sint32)outdata) < 0; ! 2162: ZFLAG = !outdata; ! 2163: VFLAG = 0; ! 2164: CFLAG = 0; ! 2165: PC+= 2; ! 2166: } ! 2167: ! 2168: void cpu_op_1384a(t_ipc *ipc) /* MULS */ { ! 2169: /* mask f1f8, bits c1e0, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2170: int srcreg = (ipc->opcode >> 0) & 7; ! 2171: uint32 srcaddr = ADDRREG(srcreg)-=2; ! 2172: uint16 srcdata = fetchword(srcaddr); ! 2173: int dstreg = (ipc->opcode >> 9) & 7; ! 2174: uint16 dstdata = DATAREG(dstreg); ! 2175: ! 2176: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2177: DATAREG(dstreg) = outdata; ! 2178: PC+= 2; ! 2179: } ! 2180: ! 2181: void cpu_op_1384b(t_ipc *ipc) /* MULS */ { ! 2182: /* mask f1f8, bits c1e0, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2183: int srcreg = (ipc->opcode >> 0) & 7; ! 2184: uint32 srcaddr = ADDRREG(srcreg)-=2; ! 2185: uint16 srcdata = fetchword(srcaddr); ! 2186: int dstreg = (ipc->opcode >> 9) & 7; ! 2187: uint16 dstdata = DATAREG(dstreg); ! 2188: ! 2189: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2190: DATAREG(dstreg) = outdata; ! 2191: ! 2192: NFLAG = ((sint32)outdata) < 0; ! 2193: ZFLAG = !outdata; ! 2194: VFLAG = 0; ! 2195: CFLAG = 0; ! 2196: PC+= 2; ! 2197: } ! 2198: ! 2199: void cpu_op_1385a(t_ipc *ipc) /* MULS */ { ! 2200: /* mask f1f8, bits c1e8, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2201: int srcreg = (ipc->opcode >> 0) & 7; ! 2202: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 2203: uint16 srcdata = fetchword(srcaddr); ! 2204: int dstreg = (ipc->opcode >> 9) & 7; ! 2205: uint16 dstdata = DATAREG(dstreg); ! 2206: ! 2207: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2208: DATAREG(dstreg) = outdata; ! 2209: PC+= 4; ! 2210: } ! 2211: ! 2212: void cpu_op_1385b(t_ipc *ipc) /* MULS */ { ! 2213: /* mask f1f8, bits c1e8, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2214: int srcreg = (ipc->opcode >> 0) & 7; ! 2215: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 2216: uint16 srcdata = fetchword(srcaddr); ! 2217: int dstreg = (ipc->opcode >> 9) & 7; ! 2218: uint16 dstdata = DATAREG(dstreg); ! 2219: ! 2220: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2221: DATAREG(dstreg) = outdata; ! 2222: ! 2223: NFLAG = ((sint32)outdata) < 0; ! 2224: ZFLAG = !outdata; ! 2225: VFLAG = 0; ! 2226: CFLAG = 0; ! 2227: PC+= 4; ! 2228: } ! 2229: ! 2230: void cpu_op_1386a(t_ipc *ipc) /* MULS */ { ! 2231: /* mask f1f8, bits c1f0, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2232: int srcreg = (ipc->opcode >> 0) & 7; ! 2233: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 2234: uint16 srcdata = fetchword(srcaddr); ! 2235: int dstreg = (ipc->opcode >> 9) & 7; ! 2236: uint16 dstdata = DATAREG(dstreg); ! 2237: ! 2238: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2239: DATAREG(dstreg) = outdata; ! 2240: PC+= 4; ! 2241: } ! 2242: ! 2243: void cpu_op_1386b(t_ipc *ipc) /* MULS */ { ! 2244: /* mask f1f8, bits c1f0, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2245: int srcreg = (ipc->opcode >> 0) & 7; ! 2246: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 2247: uint16 srcdata = fetchword(srcaddr); ! 2248: int dstreg = (ipc->opcode >> 9) & 7; ! 2249: uint16 dstdata = DATAREG(dstreg); ! 2250: ! 2251: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2252: DATAREG(dstreg) = outdata; ! 2253: ! 2254: NFLAG = ((sint32)outdata) < 0; ! 2255: ZFLAG = !outdata; ! 2256: VFLAG = 0; ! 2257: CFLAG = 0; ! 2258: PC+= 4; ! 2259: } ! 2260: ! 2261: void cpu_op_1387a(t_ipc *ipc) /* MULS */ { ! 2262: /* mask f1ff, bits c1f8, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2263: uint32 srcaddr = ipc->src; ! 2264: uint16 srcdata = fetchword(srcaddr); ! 2265: int dstreg = (ipc->opcode >> 9) & 7; ! 2266: uint16 dstdata = DATAREG(dstreg); ! 2267: ! 2268: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2269: DATAREG(dstreg) = outdata; ! 2270: PC+= 4; ! 2271: } ! 2272: ! 2273: void cpu_op_1387b(t_ipc *ipc) /* MULS */ { ! 2274: /* mask f1ff, bits c1f8, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2275: uint32 srcaddr = ipc->src; ! 2276: uint16 srcdata = fetchword(srcaddr); ! 2277: int dstreg = (ipc->opcode >> 9) & 7; ! 2278: uint16 dstdata = DATAREG(dstreg); ! 2279: ! 2280: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2281: DATAREG(dstreg) = outdata; ! 2282: ! 2283: NFLAG = ((sint32)outdata) < 0; ! 2284: ZFLAG = !outdata; ! 2285: VFLAG = 0; ! 2286: CFLAG = 0; ! 2287: PC+= 4; ! 2288: } ! 2289: ! 2290: void cpu_op_1388a(t_ipc *ipc) /* MULS */ { ! 2291: /* mask f1ff, bits c1f9, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2292: uint32 srcaddr = ipc->src; ! 2293: uint16 srcdata = fetchword(srcaddr); ! 2294: int dstreg = (ipc->opcode >> 9) & 7; ! 2295: uint16 dstdata = DATAREG(dstreg); ! 2296: ! 2297: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2298: DATAREG(dstreg) = outdata; ! 2299: PC+= 6; ! 2300: } ! 2301: ! 2302: void cpu_op_1388b(t_ipc *ipc) /* MULS */ { ! 2303: /* mask f1ff, bits c1f9, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2304: uint32 srcaddr = ipc->src; ! 2305: uint16 srcdata = fetchword(srcaddr); ! 2306: int dstreg = (ipc->opcode >> 9) & 7; ! 2307: uint16 dstdata = DATAREG(dstreg); ! 2308: ! 2309: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2310: DATAREG(dstreg) = outdata; ! 2311: ! 2312: NFLAG = ((sint32)outdata) < 0; ! 2313: ZFLAG = !outdata; ! 2314: VFLAG = 0; ! 2315: CFLAG = 0; ! 2316: PC+= 6; ! 2317: } ! 2318: ! 2319: void cpu_op_1389a(t_ipc *ipc) /* MULS */ { ! 2320: /* mask f1ff, bits c1fa, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2321: uint32 srcaddr = ipc->src; ! 2322: uint16 srcdata = fetchword(srcaddr); ! 2323: int dstreg = (ipc->opcode >> 9) & 7; ! 2324: uint16 dstdata = DATAREG(dstreg); ! 2325: ! 2326: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2327: DATAREG(dstreg) = outdata; ! 2328: PC+= 4; ! 2329: } ! 2330: ! 2331: void cpu_op_1389b(t_ipc *ipc) /* MULS */ { ! 2332: /* mask f1ff, bits c1fa, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2333: uint32 srcaddr = ipc->src; ! 2334: uint16 srcdata = fetchword(srcaddr); ! 2335: int dstreg = (ipc->opcode >> 9) & 7; ! 2336: uint16 dstdata = DATAREG(dstreg); ! 2337: ! 2338: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2339: DATAREG(dstreg) = outdata; ! 2340: ! 2341: NFLAG = ((sint32)outdata) < 0; ! 2342: ZFLAG = !outdata; ! 2343: VFLAG = 0; ! 2344: CFLAG = 0; ! 2345: PC+= 4; ! 2346: } ! 2347: ! 2348: void cpu_op_1390a(t_ipc *ipc) /* MULS */ { ! 2349: /* mask f1ff, bits c1fb, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2350: uint32 srcaddr = idxval_src(ipc); ! 2351: uint16 srcdata = fetchword(srcaddr); ! 2352: int dstreg = (ipc->opcode >> 9) & 7; ! 2353: uint16 dstdata = DATAREG(dstreg); ! 2354: ! 2355: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2356: DATAREG(dstreg) = outdata; ! 2357: PC+= 4; ! 2358: } ! 2359: ! 2360: void cpu_op_1390b(t_ipc *ipc) /* MULS */ { ! 2361: /* mask f1ff, bits c1fb, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2362: uint32 srcaddr = idxval_src(ipc); ! 2363: uint16 srcdata = fetchword(srcaddr); ! 2364: int dstreg = (ipc->opcode >> 9) & 7; ! 2365: uint16 dstdata = DATAREG(dstreg); ! 2366: ! 2367: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2368: DATAREG(dstreg) = outdata; ! 2369: ! 2370: NFLAG = ((sint32)outdata) < 0; ! 2371: ZFLAG = !outdata; ! 2372: VFLAG = 0; ! 2373: CFLAG = 0; ! 2374: PC+= 4; ! 2375: } ! 2376: ! 2377: void cpu_op_1391a(t_ipc *ipc) /* MULS */ { ! 2378: /* mask f1ff, bits c1fc, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2379: uint16 srcdata = ipc->src; ! 2380: int dstreg = (ipc->opcode >> 9) & 7; ! 2381: uint16 dstdata = DATAREG(dstreg); ! 2382: ! 2383: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2384: DATAREG(dstreg) = outdata; ! 2385: PC+= 4; ! 2386: } ! 2387: ! 2388: void cpu_op_1391b(t_ipc *ipc) /* MULS */ { ! 2389: /* mask f1ff, bits c1fc, mnemonic 14, priv 0, endblk 0, imm_notzero 0, used 0 set -2, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2390: uint16 srcdata = ipc->src; ! 2391: int dstreg = (ipc->opcode >> 9) & 7; ! 2392: uint16 dstdata = DATAREG(dstreg); ! 2393: ! 2394: uint32 outdata = (sint32)(sint16)srcdata * (sint32)(sint16)dstdata; ! 2395: DATAREG(dstreg) = outdata; ! 2396: ! 2397: NFLAG = ((sint32)outdata) < 0; ! 2398: ZFLAG = !outdata; ! 2399: VFLAG = 0; ! 2400: CFLAG = 0; ! 2401: PC+= 4; ! 2402: } ! 2403: ! 2404: void cpu_op_1392a(t_ipc *ipc) /* ABCD */ { ! 2405: /* mask f1f8, bits c100, mnemonic 35, priv 0, endblk 0, imm_notzero 0, used 5 set -11, size 1, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2406: int srcreg = (ipc->opcode >> 0) & 7; ! 2407: uint8 srcdata = DATAREG(srcreg); ! 2408: int dstreg = (ipc->opcode >> 9) & 7; ! 2409: uint8 dstdata = DATAREG(dstreg); ! 2410: uint8 outdata; ! 2411: ! 2412: uint8 outdata_low = (dstdata & 0xF) + (srcdata & 0xF) + XFLAG; ! 2413: uint8 outdata_high = (dstdata>>4) + (srcdata>>4); ! 2414: ! 2415: if (outdata_low > 9) { ! 2416: outdata_low-=10; outdata_high++; ! 2417: } ! 2418: if (outdata_high > 9) { ! 2419: outdata_high-=10; ! 2420: } else { ! 2421: } ! 2422: outdata = outdata_low | (outdata_high << 4); ! 2423: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 2424: PC+= 2; ! 2425: } ! 2426: ! 2427: void cpu_op_1392b(t_ipc *ipc) /* ABCD */ { ! 2428: /* mask f1f8, bits c100, mnemonic 35, priv 0, endblk 0, imm_notzero 0, used 5 set -11, size 1, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2429: int srcreg = (ipc->opcode >> 0) & 7; ! 2430: uint8 srcdata = DATAREG(srcreg); ! 2431: int dstreg = (ipc->opcode >> 9) & 7; ! 2432: uint8 dstdata = DATAREG(dstreg); ! 2433: uint8 outdata; ! 2434: ! 2435: uint8 outdata_low = (dstdata & 0xF) + (srcdata & 0xF) + XFLAG; ! 2436: uint8 outdata_high = (dstdata>>4) + (srcdata>>4); ! 2437: ! 2438: if (outdata_low > 9) { ! 2439: outdata_low-=10; outdata_high++; ! 2440: } ! 2441: if (outdata_high > 9) { ! 2442: outdata_high-=10; ! 2443: CFLAG = 1; ! 2444: XFLAG = 1; ! 2445: } else { ! 2446: CFLAG = 0; ! 2447: XFLAG = 0; ! 2448: } ! 2449: outdata = outdata_low | (outdata_high << 4); ! 2450: if (outdata) ZFLAG = 0; ! 2451: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 2452: PC+= 2; ! 2453: } ! 2454: ! 2455: void cpu_op_1393a(t_ipc *ipc) /* ABCD */ { ! 2456: /* mask f1f8, bits c108, mnemonic 35, priv 0, endblk 0, imm_notzero 0, used 5 set -11, size 1, stype 4, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2457: int srcreg = (ipc->opcode >> 0) & 7; ! 2458: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1)); ! 2459: uint8 srcdata = fetchbyte(srcaddr); ! 2460: int dstreg = (ipc->opcode >> 9) & 7; ! 2461: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1)); ! 2462: uint8 dstdata = fetchbyte(dstaddr); ! 2463: uint8 outdata; ! 2464: ! 2465: uint8 outdata_low = (dstdata & 0xF) + (srcdata & 0xF) + XFLAG; ! 2466: uint8 outdata_high = (dstdata>>4) + (srcdata>>4); ! 2467: ! 2468: if (outdata_low > 9) { ! 2469: outdata_low-=10; outdata_high++; ! 2470: } ! 2471: if (outdata_high > 9) { ! 2472: outdata_high-=10; ! 2473: } else { ! 2474: } ! 2475: outdata = outdata_low | (outdata_high << 4); ! 2476: storebyte(dstaddr, outdata); ! 2477: PC+= 2; ! 2478: } ! 2479: ! 2480: void cpu_op_1393b(t_ipc *ipc) /* ABCD */ { ! 2481: /* mask f1f8, bits c108, mnemonic 35, priv 0, endblk 0, imm_notzero 0, used 5 set -11, size 1, stype 4, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2482: int srcreg = (ipc->opcode >> 0) & 7; ! 2483: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1)); ! 2484: uint8 srcdata = fetchbyte(srcaddr); ! 2485: int dstreg = (ipc->opcode >> 9) & 7; ! 2486: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1)); ! 2487: uint8 dstdata = fetchbyte(dstaddr); ! 2488: uint8 outdata; ! 2489: ! 2490: uint8 outdata_low = (dstdata & 0xF) + (srcdata & 0xF) + XFLAG; ! 2491: uint8 outdata_high = (dstdata>>4) + (srcdata>>4); ! 2492: ! 2493: if (outdata_low > 9) { ! 2494: outdata_low-=10; outdata_high++; ! 2495: } ! 2496: if (outdata_high > 9) { ! 2497: outdata_high-=10; ! 2498: CFLAG = 1; ! 2499: XFLAG = 1; ! 2500: } else { ! 2501: CFLAG = 0; ! 2502: XFLAG = 0; ! 2503: } ! 2504: outdata = outdata_low | (outdata_high << 4); ! 2505: if (outdata) ZFLAG = 0; ! 2506: storebyte(dstaddr, outdata); ! 2507: PC+= 2; ! 2508: } ! 2509: ! 2510: void cpu_op_1394a(t_ipc *ipc) /* EXG */ { ! 2511: /* mask f1f8, bits c140, mnemonic 42, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2512: int srcreg = (ipc->opcode >> 0) & 7; ! 2513: uint32 srcdata = DATAREG(srcreg); ! 2514: int dstreg = (ipc->opcode >> 9) & 7; ! 2515: uint32 dstdata = DATAREG(dstreg); ! 2516: ! 2517: DATAREG(dstreg) = srcdata; ! 2518: DATAREG(srcreg) = dstdata; ! 2519: PC+= 2; ! 2520: } ! 2521: ! 2522: void cpu_op_1395a(t_ipc *ipc) /* EXG */ { ! 2523: /* mask f1f8, bits c148, mnemonic 42, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 1, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2524: int srcreg = (ipc->opcode >> 0) & 7; ! 2525: uint32 srcdata = ADDRREG(srcreg); ! 2526: int dstreg = (ipc->opcode >> 9) & 7; ! 2527: uint32 dstdata = ADDRREG(dstreg); ! 2528: ! 2529: ADDRREG(dstreg) = srcdata; ! 2530: ADDRREG(srcreg) = dstdata; ! 2531: PC+= 2; ! 2532: } ! 2533: ! 2534: void cpu_op_1396a(t_ipc *ipc) /* EXG */ { ! 2535: /* mask f1f8, bits c188, mnemonic 42, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 0, dtype 1, sbitpos 9, dbitpos 0, immvalue 0 */ ! 2536: int srcreg = (ipc->opcode >> 9) & 7; ! 2537: uint32 srcdata = DATAREG(srcreg); ! 2538: int dstreg = (ipc->opcode >> 0) & 7; ! 2539: uint32 dstdata = ADDRREG(dstreg); ! 2540: ! 2541: ADDRREG(dstreg) = srcdata; ! 2542: DATAREG(srcreg) = dstdata; ! 2543: PC+= 2; ! 2544: } ! 2545:
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