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1.1 ! root 1: /*****************************************************************************/ ! 2: /* Generator - Sega Genesis emulation - (c) James Ponder 1997-1998 */ ! 3: /*****************************************************************************/ ! 4: /* */ ! 5: /* cpu68k-d.c */ ! 6: /* */ ! 7: /*****************************************************************************/ ! 8: ! 9: #include "generator.h" ! 10: #include "cpu68k.h" ! 11: #include "mem68k.h" ! 12: #include "reg68k.h" ! 13: ! 14: #include "cpu68k-inline.h" ! 15: ! 16: #include <stdio.h> ! 17: ! 18: void cpu_op_1397a(t_ipc *ipc) /* ADD */ { ! 19: /* mask f1f8, bits d000, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 20: int srcreg = (ipc->opcode >> 0) & 7; ! 21: uint8 srcdata = DATAREG(srcreg); ! 22: int dstreg = (ipc->opcode >> 9) & 7; ! 23: uint8 dstdata = DATAREG(dstreg); ! 24: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 25: ! 26: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 27: PC+= 2; ! 28: } ! 29: ! 30: void cpu_op_1397b(t_ipc *ipc) /* ADD */ { ! 31: /* mask f1f8, bits d000, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 32: int srcreg = (ipc->opcode >> 0) & 7; ! 33: uint8 srcdata = DATAREG(srcreg); ! 34: int dstreg = (ipc->opcode >> 9) & 7; ! 35: uint8 dstdata = DATAREG(dstreg); ! 36: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 37: ! 38: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 39: ! 40: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 41: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 42: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 43: NFLAG = ((sint8)outdata) < 0; ! 44: ZFLAG = !outdata; ! 45: PC+= 2; ! 46: } ! 47: ! 48: void cpu_op_1398a(t_ipc *ipc) /* ADD */ { ! 49: /* mask f1f8, bits d008, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 1, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 50: int srcreg = (ipc->opcode >> 0) & 7; ! 51: uint8 srcdata = ADDRREG(srcreg); ! 52: int dstreg = (ipc->opcode >> 9) & 7; ! 53: uint8 dstdata = DATAREG(dstreg); ! 54: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 55: ! 56: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 57: PC+= 2; ! 58: } ! 59: ! 60: void cpu_op_1398b(t_ipc *ipc) /* ADD */ { ! 61: /* mask f1f8, bits d008, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 1, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 62: int srcreg = (ipc->opcode >> 0) & 7; ! 63: uint8 srcdata = ADDRREG(srcreg); ! 64: int dstreg = (ipc->opcode >> 9) & 7; ! 65: uint8 dstdata = DATAREG(dstreg); ! 66: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 67: ! 68: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 69: ! 70: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 71: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 72: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 73: NFLAG = ((sint8)outdata) < 0; ! 74: ZFLAG = !outdata; ! 75: PC+= 2; ! 76: } ! 77: ! 78: void cpu_op_1399a(t_ipc *ipc) /* ADD */ { ! 79: /* mask f1f8, bits d010, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 80: int srcreg = (ipc->opcode >> 0) & 7; ! 81: uint32 srcaddr = ADDRREG(srcreg); ! 82: uint8 srcdata = fetchbyte(srcaddr); ! 83: int dstreg = (ipc->opcode >> 9) & 7; ! 84: uint8 dstdata = DATAREG(dstreg); ! 85: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 86: ! 87: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 88: PC+= 2; ! 89: } ! 90: ! 91: void cpu_op_1399b(t_ipc *ipc) /* ADD */ { ! 92: /* mask f1f8, bits d010, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 93: int srcreg = (ipc->opcode >> 0) & 7; ! 94: uint32 srcaddr = ADDRREG(srcreg); ! 95: uint8 srcdata = fetchbyte(srcaddr); ! 96: int dstreg = (ipc->opcode >> 9) & 7; ! 97: uint8 dstdata = DATAREG(dstreg); ! 98: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 99: ! 100: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 101: ! 102: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 103: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 104: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 105: NFLAG = ((sint8)outdata) < 0; ! 106: ZFLAG = !outdata; ! 107: PC+= 2; ! 108: } ! 109: ! 110: void cpu_op_1400a(t_ipc *ipc) /* ADD */ { ! 111: /* mask f1f8, bits d018, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 112: int srcreg = (ipc->opcode >> 0) & 7; ! 113: uint32 srcaddr = ADDRREG(srcreg); ! 114: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0); ! 115: uint8 srcdata = fetchbyte(srcaddr); ! 116: int dstreg = (ipc->opcode >> 9) & 7; ! 117: uint8 dstdata = DATAREG(dstreg); ! 118: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 119: ! 120: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 121: PC+= 2; ! 122: } ! 123: ! 124: void cpu_op_1400b(t_ipc *ipc) /* ADD */ { ! 125: /* mask f1f8, bits d018, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 126: int srcreg = (ipc->opcode >> 0) & 7; ! 127: uint32 srcaddr = ADDRREG(srcreg); ! 128: uint32 srcaddr_tmp = (ADDRREG(srcreg)+= (srcreg == 7 ? 2 : 1), 0); ! 129: uint8 srcdata = fetchbyte(srcaddr); ! 130: int dstreg = (ipc->opcode >> 9) & 7; ! 131: uint8 dstdata = DATAREG(dstreg); ! 132: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 133: ! 134: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 135: ! 136: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 137: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 138: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 139: NFLAG = ((sint8)outdata) < 0; ! 140: ZFLAG = !outdata; ! 141: PC+= 2; ! 142: } ! 143: ! 144: void cpu_op_1401a(t_ipc *ipc) /* ADD */ { ! 145: /* mask f1f8, bits d020, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 146: int srcreg = (ipc->opcode >> 0) & 7; ! 147: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1)); ! 148: uint8 srcdata = fetchbyte(srcaddr); ! 149: int dstreg = (ipc->opcode >> 9) & 7; ! 150: uint8 dstdata = DATAREG(dstreg); ! 151: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 152: ! 153: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 154: PC+= 2; ! 155: } ! 156: ! 157: void cpu_op_1401b(t_ipc *ipc) /* ADD */ { ! 158: /* mask f1f8, bits d020, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 159: int srcreg = (ipc->opcode >> 0) & 7; ! 160: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1)); ! 161: uint8 srcdata = fetchbyte(srcaddr); ! 162: int dstreg = (ipc->opcode >> 9) & 7; ! 163: uint8 dstdata = DATAREG(dstreg); ! 164: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 165: ! 166: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 167: ! 168: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 169: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 170: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 171: NFLAG = ((sint8)outdata) < 0; ! 172: ZFLAG = !outdata; ! 173: PC+= 2; ! 174: } ! 175: ! 176: void cpu_op_1402a(t_ipc *ipc) /* ADD */ { ! 177: /* mask f1f8, bits d028, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 178: int srcreg = (ipc->opcode >> 0) & 7; ! 179: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 180: uint8 srcdata = fetchbyte(srcaddr); ! 181: int dstreg = (ipc->opcode >> 9) & 7; ! 182: uint8 dstdata = DATAREG(dstreg); ! 183: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 184: ! 185: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 186: PC+= 4; ! 187: } ! 188: ! 189: void cpu_op_1402b(t_ipc *ipc) /* ADD */ { ! 190: /* mask f1f8, bits d028, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 191: int srcreg = (ipc->opcode >> 0) & 7; ! 192: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 193: uint8 srcdata = fetchbyte(srcaddr); ! 194: int dstreg = (ipc->opcode >> 9) & 7; ! 195: uint8 dstdata = DATAREG(dstreg); ! 196: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 197: ! 198: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 199: ! 200: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 201: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 202: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 203: NFLAG = ((sint8)outdata) < 0; ! 204: ZFLAG = !outdata; ! 205: PC+= 4; ! 206: } ! 207: ! 208: void cpu_op_1403a(t_ipc *ipc) /* ADD */ { ! 209: /* mask f1f8, bits d030, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 210: int srcreg = (ipc->opcode >> 0) & 7; ! 211: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 212: uint8 srcdata = fetchbyte(srcaddr); ! 213: int dstreg = (ipc->opcode >> 9) & 7; ! 214: uint8 dstdata = DATAREG(dstreg); ! 215: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 216: ! 217: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 218: PC+= 4; ! 219: } ! 220: ! 221: void cpu_op_1403b(t_ipc *ipc) /* ADD */ { ! 222: /* mask f1f8, bits d030, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 223: int srcreg = (ipc->opcode >> 0) & 7; ! 224: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 225: uint8 srcdata = fetchbyte(srcaddr); ! 226: int dstreg = (ipc->opcode >> 9) & 7; ! 227: uint8 dstdata = DATAREG(dstreg); ! 228: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 229: ! 230: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 231: ! 232: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 233: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 234: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 235: NFLAG = ((sint8)outdata) < 0; ! 236: ZFLAG = !outdata; ! 237: PC+= 4; ! 238: } ! 239: ! 240: void cpu_op_1404a(t_ipc *ipc) /* ADD */ { ! 241: /* mask f1ff, bits d038, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 242: uint32 srcaddr = ipc->src; ! 243: uint8 srcdata = fetchbyte(srcaddr); ! 244: int dstreg = (ipc->opcode >> 9) & 7; ! 245: uint8 dstdata = DATAREG(dstreg); ! 246: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 247: ! 248: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 249: PC+= 4; ! 250: } ! 251: ! 252: void cpu_op_1404b(t_ipc *ipc) /* ADD */ { ! 253: /* mask f1ff, bits d038, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 254: uint32 srcaddr = ipc->src; ! 255: uint8 srcdata = fetchbyte(srcaddr); ! 256: int dstreg = (ipc->opcode >> 9) & 7; ! 257: uint8 dstdata = DATAREG(dstreg); ! 258: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 259: ! 260: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 261: ! 262: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 263: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 264: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 265: NFLAG = ((sint8)outdata) < 0; ! 266: ZFLAG = !outdata; ! 267: PC+= 4; ! 268: } ! 269: ! 270: void cpu_op_1405a(t_ipc *ipc) /* ADD */ { ! 271: /* mask f1ff, bits d039, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 272: uint32 srcaddr = ipc->src; ! 273: uint8 srcdata = fetchbyte(srcaddr); ! 274: int dstreg = (ipc->opcode >> 9) & 7; ! 275: uint8 dstdata = DATAREG(dstreg); ! 276: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 277: ! 278: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 279: PC+= 6; ! 280: } ! 281: ! 282: void cpu_op_1405b(t_ipc *ipc) /* ADD */ { ! 283: /* mask f1ff, bits d039, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 284: uint32 srcaddr = ipc->src; ! 285: uint8 srcdata = fetchbyte(srcaddr); ! 286: int dstreg = (ipc->opcode >> 9) & 7; ! 287: uint8 dstdata = DATAREG(dstreg); ! 288: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 289: ! 290: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 291: ! 292: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 293: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 294: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 295: NFLAG = ((sint8)outdata) < 0; ! 296: ZFLAG = !outdata; ! 297: PC+= 6; ! 298: } ! 299: ! 300: void cpu_op_1406a(t_ipc *ipc) /* ADD */ { ! 301: /* mask f1ff, bits d03a, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 302: uint32 srcaddr = ipc->src; ! 303: uint8 srcdata = fetchbyte(srcaddr); ! 304: int dstreg = (ipc->opcode >> 9) & 7; ! 305: uint8 dstdata = DATAREG(dstreg); ! 306: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 307: ! 308: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 309: PC+= 4; ! 310: } ! 311: ! 312: void cpu_op_1406b(t_ipc *ipc) /* ADD */ { ! 313: /* mask f1ff, bits d03a, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 314: uint32 srcaddr = ipc->src; ! 315: uint8 srcdata = fetchbyte(srcaddr); ! 316: int dstreg = (ipc->opcode >> 9) & 7; ! 317: uint8 dstdata = DATAREG(dstreg); ! 318: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 319: ! 320: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 321: ! 322: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 323: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 324: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 325: NFLAG = ((sint8)outdata) < 0; ! 326: ZFLAG = !outdata; ! 327: PC+= 4; ! 328: } ! 329: ! 330: void cpu_op_1407a(t_ipc *ipc) /* ADD */ { ! 331: /* mask f1ff, bits d03b, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 332: uint32 srcaddr = idxval_src(ipc); ! 333: uint8 srcdata = fetchbyte(srcaddr); ! 334: int dstreg = (ipc->opcode >> 9) & 7; ! 335: uint8 dstdata = DATAREG(dstreg); ! 336: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 337: ! 338: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 339: PC+= 4; ! 340: } ! 341: ! 342: void cpu_op_1407b(t_ipc *ipc) /* ADD */ { ! 343: /* mask f1ff, bits d03b, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 344: uint32 srcaddr = idxval_src(ipc); ! 345: uint8 srcdata = fetchbyte(srcaddr); ! 346: int dstreg = (ipc->opcode >> 9) & 7; ! 347: uint8 dstdata = DATAREG(dstreg); ! 348: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 349: ! 350: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 351: ! 352: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 353: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 354: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 355: NFLAG = ((sint8)outdata) < 0; ! 356: ZFLAG = !outdata; ! 357: PC+= 4; ! 358: } ! 359: ! 360: void cpu_op_1408a(t_ipc *ipc) /* ADD */ { ! 361: /* mask f1ff, bits d03c, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 362: uint8 srcdata = ipc->src; ! 363: int dstreg = (ipc->opcode >> 9) & 7; ! 364: uint8 dstdata = DATAREG(dstreg); ! 365: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 366: ! 367: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 368: PC+= 4; ! 369: } ! 370: ! 371: void cpu_op_1408b(t_ipc *ipc) /* ADD */ { ! 372: /* mask f1ff, bits d03c, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 11, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 373: uint8 srcdata = ipc->src; ! 374: int dstreg = (ipc->opcode >> 9) & 7; ! 375: uint8 dstdata = DATAREG(dstreg); ! 376: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 377: ! 378: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 379: ! 380: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 381: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 382: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 383: NFLAG = ((sint8)outdata) < 0; ! 384: ZFLAG = !outdata; ! 385: PC+= 4; ! 386: } ! 387: ! 388: void cpu_op_1409a(t_ipc *ipc) /* ADD */ { ! 389: /* mask f1f8, bits d040, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 390: int srcreg = (ipc->opcode >> 0) & 7; ! 391: uint16 srcdata = DATAREG(srcreg); ! 392: int dstreg = (ipc->opcode >> 9) & 7; ! 393: uint16 dstdata = DATAREG(dstreg); ! 394: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 395: ! 396: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 397: PC+= 2; ! 398: } ! 399: ! 400: void cpu_op_1409b(t_ipc *ipc) /* ADD */ { ! 401: /* mask f1f8, bits d040, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 402: int srcreg = (ipc->opcode >> 0) & 7; ! 403: uint16 srcdata = DATAREG(srcreg); ! 404: int dstreg = (ipc->opcode >> 9) & 7; ! 405: uint16 dstdata = DATAREG(dstreg); ! 406: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 407: ! 408: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 409: ! 410: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 411: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 412: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 413: NFLAG = ((sint16)outdata) < 0; ! 414: ZFLAG = !outdata; ! 415: PC+= 2; ! 416: } ! 417: ! 418: void cpu_op_1410a(t_ipc *ipc) /* ADD */ { ! 419: /* mask f1f8, bits d048, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 1, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 420: int srcreg = (ipc->opcode >> 0) & 7; ! 421: uint16 srcdata = ADDRREG(srcreg); ! 422: int dstreg = (ipc->opcode >> 9) & 7; ! 423: uint16 dstdata = DATAREG(dstreg); ! 424: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 425: ! 426: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 427: PC+= 2; ! 428: } ! 429: ! 430: void cpu_op_1410b(t_ipc *ipc) /* ADD */ { ! 431: /* mask f1f8, bits d048, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 1, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 432: int srcreg = (ipc->opcode >> 0) & 7; ! 433: uint16 srcdata = ADDRREG(srcreg); ! 434: int dstreg = (ipc->opcode >> 9) & 7; ! 435: uint16 dstdata = DATAREG(dstreg); ! 436: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 437: ! 438: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 439: ! 440: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 441: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 442: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 443: NFLAG = ((sint16)outdata) < 0; ! 444: ZFLAG = !outdata; ! 445: PC+= 2; ! 446: } ! 447: ! 448: void cpu_op_1411a(t_ipc *ipc) /* ADD */ { ! 449: /* mask f1f8, bits d050, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 450: int srcreg = (ipc->opcode >> 0) & 7; ! 451: uint32 srcaddr = ADDRREG(srcreg); ! 452: uint16 srcdata = fetchword(srcaddr); ! 453: int dstreg = (ipc->opcode >> 9) & 7; ! 454: uint16 dstdata = DATAREG(dstreg); ! 455: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 456: ! 457: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 458: PC+= 2; ! 459: } ! 460: ! 461: void cpu_op_1411b(t_ipc *ipc) /* ADD */ { ! 462: /* mask f1f8, bits d050, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 463: int srcreg = (ipc->opcode >> 0) & 7; ! 464: uint32 srcaddr = ADDRREG(srcreg); ! 465: uint16 srcdata = fetchword(srcaddr); ! 466: int dstreg = (ipc->opcode >> 9) & 7; ! 467: uint16 dstdata = DATAREG(dstreg); ! 468: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 469: ! 470: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 471: ! 472: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 473: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 474: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 475: NFLAG = ((sint16)outdata) < 0; ! 476: ZFLAG = !outdata; ! 477: PC+= 2; ! 478: } ! 479: ! 480: void cpu_op_1412a(t_ipc *ipc) /* ADD */ { ! 481: /* mask f1f8, bits d058, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 482: int srcreg = (ipc->opcode >> 0) & 7; ! 483: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2); ! 484: uint16 srcdata = fetchword(srcaddr); ! 485: int dstreg = (ipc->opcode >> 9) & 7; ! 486: uint16 dstdata = DATAREG(dstreg); ! 487: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 488: ! 489: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 490: PC+= 2; ! 491: } ! 492: ! 493: void cpu_op_1412b(t_ipc *ipc) /* ADD */ { ! 494: /* mask f1f8, bits d058, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 495: int srcreg = (ipc->opcode >> 0) & 7; ! 496: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2); ! 497: uint16 srcdata = fetchword(srcaddr); ! 498: int dstreg = (ipc->opcode >> 9) & 7; ! 499: uint16 dstdata = DATAREG(dstreg); ! 500: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 501: ! 502: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 503: ! 504: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 505: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 506: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 507: NFLAG = ((sint16)outdata) < 0; ! 508: ZFLAG = !outdata; ! 509: PC+= 2; ! 510: } ! 511: ! 512: void cpu_op_1413a(t_ipc *ipc) /* ADD */ { ! 513: /* mask f1f8, bits d060, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 514: int srcreg = (ipc->opcode >> 0) & 7; ! 515: uint32 srcaddr = ADDRREG(srcreg)-=2; ! 516: uint16 srcdata = fetchword(srcaddr); ! 517: int dstreg = (ipc->opcode >> 9) & 7; ! 518: uint16 dstdata = DATAREG(dstreg); ! 519: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 520: ! 521: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 522: PC+= 2; ! 523: } ! 524: ! 525: void cpu_op_1413b(t_ipc *ipc) /* ADD */ { ! 526: /* mask f1f8, bits d060, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 527: int srcreg = (ipc->opcode >> 0) & 7; ! 528: uint32 srcaddr = ADDRREG(srcreg)-=2; ! 529: uint16 srcdata = fetchword(srcaddr); ! 530: int dstreg = (ipc->opcode >> 9) & 7; ! 531: uint16 dstdata = DATAREG(dstreg); ! 532: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 533: ! 534: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 535: ! 536: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 537: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 538: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 539: NFLAG = ((sint16)outdata) < 0; ! 540: ZFLAG = !outdata; ! 541: PC+= 2; ! 542: } ! 543: ! 544: void cpu_op_1414a(t_ipc *ipc) /* ADD */ { ! 545: /* mask f1f8, bits d068, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 546: int srcreg = (ipc->opcode >> 0) & 7; ! 547: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 548: uint16 srcdata = fetchword(srcaddr); ! 549: int dstreg = (ipc->opcode >> 9) & 7; ! 550: uint16 dstdata = DATAREG(dstreg); ! 551: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 552: ! 553: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 554: PC+= 4; ! 555: } ! 556: ! 557: void cpu_op_1414b(t_ipc *ipc) /* ADD */ { ! 558: /* mask f1f8, bits d068, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 559: int srcreg = (ipc->opcode >> 0) & 7; ! 560: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 561: uint16 srcdata = fetchword(srcaddr); ! 562: int dstreg = (ipc->opcode >> 9) & 7; ! 563: uint16 dstdata = DATAREG(dstreg); ! 564: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 565: ! 566: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 567: ! 568: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 569: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 570: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 571: NFLAG = ((sint16)outdata) < 0; ! 572: ZFLAG = !outdata; ! 573: PC+= 4; ! 574: } ! 575: ! 576: void cpu_op_1415a(t_ipc *ipc) /* ADD */ { ! 577: /* mask f1f8, bits d070, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 578: int srcreg = (ipc->opcode >> 0) & 7; ! 579: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 580: uint16 srcdata = fetchword(srcaddr); ! 581: int dstreg = (ipc->opcode >> 9) & 7; ! 582: uint16 dstdata = DATAREG(dstreg); ! 583: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 584: ! 585: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 586: PC+= 4; ! 587: } ! 588: ! 589: void cpu_op_1415b(t_ipc *ipc) /* ADD */ { ! 590: /* mask f1f8, bits d070, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 591: int srcreg = (ipc->opcode >> 0) & 7; ! 592: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 593: uint16 srcdata = fetchword(srcaddr); ! 594: int dstreg = (ipc->opcode >> 9) & 7; ! 595: uint16 dstdata = DATAREG(dstreg); ! 596: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 597: ! 598: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 599: ! 600: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 601: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 602: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 603: NFLAG = ((sint16)outdata) < 0; ! 604: ZFLAG = !outdata; ! 605: PC+= 4; ! 606: } ! 607: ! 608: void cpu_op_1416a(t_ipc *ipc) /* ADD */ { ! 609: /* mask f1ff, bits d078, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 610: uint32 srcaddr = ipc->src; ! 611: uint16 srcdata = fetchword(srcaddr); ! 612: int dstreg = (ipc->opcode >> 9) & 7; ! 613: uint16 dstdata = DATAREG(dstreg); ! 614: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 615: ! 616: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 617: PC+= 4; ! 618: } ! 619: ! 620: void cpu_op_1416b(t_ipc *ipc) /* ADD */ { ! 621: /* mask f1ff, bits d078, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 622: uint32 srcaddr = ipc->src; ! 623: uint16 srcdata = fetchword(srcaddr); ! 624: int dstreg = (ipc->opcode >> 9) & 7; ! 625: uint16 dstdata = DATAREG(dstreg); ! 626: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 627: ! 628: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 629: ! 630: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 631: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 632: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 633: NFLAG = ((sint16)outdata) < 0; ! 634: ZFLAG = !outdata; ! 635: PC+= 4; ! 636: } ! 637: ! 638: void cpu_op_1417a(t_ipc *ipc) /* ADD */ { ! 639: /* mask f1ff, bits d079, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 640: uint32 srcaddr = ipc->src; ! 641: uint16 srcdata = fetchword(srcaddr); ! 642: int dstreg = (ipc->opcode >> 9) & 7; ! 643: uint16 dstdata = DATAREG(dstreg); ! 644: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 645: ! 646: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 647: PC+= 6; ! 648: } ! 649: ! 650: void cpu_op_1417b(t_ipc *ipc) /* ADD */ { ! 651: /* mask f1ff, bits d079, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 652: uint32 srcaddr = ipc->src; ! 653: uint16 srcdata = fetchword(srcaddr); ! 654: int dstreg = (ipc->opcode >> 9) & 7; ! 655: uint16 dstdata = DATAREG(dstreg); ! 656: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 657: ! 658: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 659: ! 660: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 661: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 662: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 663: NFLAG = ((sint16)outdata) < 0; ! 664: ZFLAG = !outdata; ! 665: PC+= 6; ! 666: } ! 667: ! 668: void cpu_op_1418a(t_ipc *ipc) /* ADD */ { ! 669: /* mask f1ff, bits d07a, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 670: uint32 srcaddr = ipc->src; ! 671: uint16 srcdata = fetchword(srcaddr); ! 672: int dstreg = (ipc->opcode >> 9) & 7; ! 673: uint16 dstdata = DATAREG(dstreg); ! 674: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 675: ! 676: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 677: PC+= 4; ! 678: } ! 679: ! 680: void cpu_op_1418b(t_ipc *ipc) /* ADD */ { ! 681: /* mask f1ff, bits d07a, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 682: uint32 srcaddr = ipc->src; ! 683: uint16 srcdata = fetchword(srcaddr); ! 684: int dstreg = (ipc->opcode >> 9) & 7; ! 685: uint16 dstdata = DATAREG(dstreg); ! 686: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 687: ! 688: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 689: ! 690: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 691: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 692: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 693: NFLAG = ((sint16)outdata) < 0; ! 694: ZFLAG = !outdata; ! 695: PC+= 4; ! 696: } ! 697: ! 698: void cpu_op_1419a(t_ipc *ipc) /* ADD */ { ! 699: /* mask f1ff, bits d07b, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 700: uint32 srcaddr = idxval_src(ipc); ! 701: uint16 srcdata = fetchword(srcaddr); ! 702: int dstreg = (ipc->opcode >> 9) & 7; ! 703: uint16 dstdata = DATAREG(dstreg); ! 704: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 705: ! 706: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 707: PC+= 4; ! 708: } ! 709: ! 710: void cpu_op_1419b(t_ipc *ipc) /* ADD */ { ! 711: /* mask f1ff, bits d07b, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 712: uint32 srcaddr = idxval_src(ipc); ! 713: uint16 srcdata = fetchword(srcaddr); ! 714: int dstreg = (ipc->opcode >> 9) & 7; ! 715: uint16 dstdata = DATAREG(dstreg); ! 716: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 717: ! 718: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 719: ! 720: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 721: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 722: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 723: NFLAG = ((sint16)outdata) < 0; ! 724: ZFLAG = !outdata; ! 725: PC+= 4; ! 726: } ! 727: ! 728: void cpu_op_1420a(t_ipc *ipc) /* ADD */ { ! 729: /* mask f1ff, bits d07c, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 730: uint16 srcdata = ipc->src; ! 731: int dstreg = (ipc->opcode >> 9) & 7; ! 732: uint16 dstdata = DATAREG(dstreg); ! 733: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 734: ! 735: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 736: PC+= 4; ! 737: } ! 738: ! 739: void cpu_op_1420b(t_ipc *ipc) /* ADD */ { ! 740: /* mask f1ff, bits d07c, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 12, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 741: uint16 srcdata = ipc->src; ! 742: int dstreg = (ipc->opcode >> 9) & 7; ! 743: uint16 dstdata = DATAREG(dstreg); ! 744: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 745: ! 746: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 747: ! 748: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 749: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 750: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 751: NFLAG = ((sint16)outdata) < 0; ! 752: ZFLAG = !outdata; ! 753: PC+= 4; ! 754: } ! 755: ! 756: void cpu_op_1421a(t_ipc *ipc) /* ADD */ { ! 757: /* mask f1f8, bits d080, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 758: int srcreg = (ipc->opcode >> 0) & 7; ! 759: uint32 srcdata = DATAREG(srcreg); ! 760: int dstreg = (ipc->opcode >> 9) & 7; ! 761: uint32 dstdata = DATAREG(dstreg); ! 762: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 763: ! 764: DATAREG(dstreg) = outdata; ! 765: PC+= 2; ! 766: } ! 767: ! 768: void cpu_op_1421b(t_ipc *ipc) /* ADD */ { ! 769: /* mask f1f8, bits d080, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 770: int srcreg = (ipc->opcode >> 0) & 7; ! 771: uint32 srcdata = DATAREG(srcreg); ! 772: int dstreg = (ipc->opcode >> 9) & 7; ! 773: uint32 dstdata = DATAREG(dstreg); ! 774: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 775: ! 776: DATAREG(dstreg) = outdata; ! 777: ! 778: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 779: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 780: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 781: NFLAG = ((sint32)outdata) < 0; ! 782: ZFLAG = !outdata; ! 783: PC+= 2; ! 784: } ! 785: ! 786: void cpu_op_1422a(t_ipc *ipc) /* ADD */ { ! 787: /* mask f1f8, bits d088, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 1, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 788: int srcreg = (ipc->opcode >> 0) & 7; ! 789: uint32 srcdata = ADDRREG(srcreg); ! 790: int dstreg = (ipc->opcode >> 9) & 7; ! 791: uint32 dstdata = DATAREG(dstreg); ! 792: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 793: ! 794: DATAREG(dstreg) = outdata; ! 795: PC+= 2; ! 796: } ! 797: ! 798: void cpu_op_1422b(t_ipc *ipc) /* ADD */ { ! 799: /* mask f1f8, bits d088, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 1, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 800: int srcreg = (ipc->opcode >> 0) & 7; ! 801: uint32 srcdata = ADDRREG(srcreg); ! 802: int dstreg = (ipc->opcode >> 9) & 7; ! 803: uint32 dstdata = DATAREG(dstreg); ! 804: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 805: ! 806: DATAREG(dstreg) = outdata; ! 807: ! 808: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 809: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 810: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 811: NFLAG = ((sint32)outdata) < 0; ! 812: ZFLAG = !outdata; ! 813: PC+= 2; ! 814: } ! 815: ! 816: void cpu_op_1423a(t_ipc *ipc) /* ADD */ { ! 817: /* mask f1f8, bits d090, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 818: int srcreg = (ipc->opcode >> 0) & 7; ! 819: uint32 srcaddr = ADDRREG(srcreg); ! 820: uint32 srcdata = fetchlong(srcaddr); ! 821: int dstreg = (ipc->opcode >> 9) & 7; ! 822: uint32 dstdata = DATAREG(dstreg); ! 823: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 824: ! 825: DATAREG(dstreg) = outdata; ! 826: PC+= 2; ! 827: } ! 828: ! 829: void cpu_op_1423b(t_ipc *ipc) /* ADD */ { ! 830: /* mask f1f8, bits d090, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 2, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 831: int srcreg = (ipc->opcode >> 0) & 7; ! 832: uint32 srcaddr = ADDRREG(srcreg); ! 833: uint32 srcdata = fetchlong(srcaddr); ! 834: int dstreg = (ipc->opcode >> 9) & 7; ! 835: uint32 dstdata = DATAREG(dstreg); ! 836: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 837: ! 838: DATAREG(dstreg) = outdata; ! 839: ! 840: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 841: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 842: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 843: NFLAG = ((sint32)outdata) < 0; ! 844: ZFLAG = !outdata; ! 845: PC+= 2; ! 846: } ! 847: ! 848: void cpu_op_1424a(t_ipc *ipc) /* ADD */ { ! 849: /* mask f1f8, bits d098, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 850: int srcreg = (ipc->opcode >> 0) & 7; ! 851: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4); ! 852: uint32 srcdata = fetchlong(srcaddr); ! 853: int dstreg = (ipc->opcode >> 9) & 7; ! 854: uint32 dstdata = DATAREG(dstreg); ! 855: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 856: ! 857: DATAREG(dstreg) = outdata; ! 858: PC+= 2; ! 859: } ! 860: ! 861: void cpu_op_1424b(t_ipc *ipc) /* ADD */ { ! 862: /* mask f1f8, bits d098, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 3, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 863: int srcreg = (ipc->opcode >> 0) & 7; ! 864: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4); ! 865: uint32 srcdata = fetchlong(srcaddr); ! 866: int dstreg = (ipc->opcode >> 9) & 7; ! 867: uint32 dstdata = DATAREG(dstreg); ! 868: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 869: ! 870: DATAREG(dstreg) = outdata; ! 871: ! 872: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 873: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 874: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 875: NFLAG = ((sint32)outdata) < 0; ! 876: ZFLAG = !outdata; ! 877: PC+= 2; ! 878: } ! 879: ! 880: void cpu_op_1425a(t_ipc *ipc) /* ADD */ { ! 881: /* mask f1f8, bits d0a0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 882: int srcreg = (ipc->opcode >> 0) & 7; ! 883: uint32 srcaddr = ADDRREG(srcreg)-=4; ! 884: uint32 srcdata = fetchlong(srcaddr); ! 885: int dstreg = (ipc->opcode >> 9) & 7; ! 886: uint32 dstdata = DATAREG(dstreg); ! 887: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 888: ! 889: DATAREG(dstreg) = outdata; ! 890: PC+= 2; ! 891: } ! 892: ! 893: void cpu_op_1425b(t_ipc *ipc) /* ADD */ { ! 894: /* mask f1f8, bits d0a0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 4, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 895: int srcreg = (ipc->opcode >> 0) & 7; ! 896: uint32 srcaddr = ADDRREG(srcreg)-=4; ! 897: uint32 srcdata = fetchlong(srcaddr); ! 898: int dstreg = (ipc->opcode >> 9) & 7; ! 899: uint32 dstdata = DATAREG(dstreg); ! 900: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 901: ! 902: DATAREG(dstreg) = outdata; ! 903: ! 904: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 905: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 906: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 907: NFLAG = ((sint32)outdata) < 0; ! 908: ZFLAG = !outdata; ! 909: PC+= 2; ! 910: } ! 911: ! 912: void cpu_op_1426a(t_ipc *ipc) /* ADD */ { ! 913: /* mask f1f8, bits d0a8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 914: int srcreg = (ipc->opcode >> 0) & 7; ! 915: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 916: uint32 srcdata = fetchlong(srcaddr); ! 917: int dstreg = (ipc->opcode >> 9) & 7; ! 918: uint32 dstdata = DATAREG(dstreg); ! 919: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 920: ! 921: DATAREG(dstreg) = outdata; ! 922: PC+= 4; ! 923: } ! 924: ! 925: void cpu_op_1426b(t_ipc *ipc) /* ADD */ { ! 926: /* mask f1f8, bits d0a8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 5, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 927: int srcreg = (ipc->opcode >> 0) & 7; ! 928: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 929: uint32 srcdata = fetchlong(srcaddr); ! 930: int dstreg = (ipc->opcode >> 9) & 7; ! 931: uint32 dstdata = DATAREG(dstreg); ! 932: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 933: ! 934: DATAREG(dstreg) = outdata; ! 935: ! 936: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 937: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 938: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 939: NFLAG = ((sint32)outdata) < 0; ! 940: ZFLAG = !outdata; ! 941: PC+= 4; ! 942: } ! 943: ! 944: void cpu_op_1427a(t_ipc *ipc) /* ADD */ { ! 945: /* mask f1f8, bits d0b0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 946: int srcreg = (ipc->opcode >> 0) & 7; ! 947: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 948: uint32 srcdata = fetchlong(srcaddr); ! 949: int dstreg = (ipc->opcode >> 9) & 7; ! 950: uint32 dstdata = DATAREG(dstreg); ! 951: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 952: ! 953: DATAREG(dstreg) = outdata; ! 954: PC+= 4; ! 955: } ! 956: ! 957: void cpu_op_1427b(t_ipc *ipc) /* ADD */ { ! 958: /* mask f1f8, bits d0b0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 6, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 959: int srcreg = (ipc->opcode >> 0) & 7; ! 960: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 961: uint32 srcdata = fetchlong(srcaddr); ! 962: int dstreg = (ipc->opcode >> 9) & 7; ! 963: uint32 dstdata = DATAREG(dstreg); ! 964: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 965: ! 966: DATAREG(dstreg) = outdata; ! 967: ! 968: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 969: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 970: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 971: NFLAG = ((sint32)outdata) < 0; ! 972: ZFLAG = !outdata; ! 973: PC+= 4; ! 974: } ! 975: ! 976: void cpu_op_1428a(t_ipc *ipc) /* ADD */ { ! 977: /* mask f1ff, bits d0b8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 978: uint32 srcaddr = ipc->src; ! 979: uint32 srcdata = fetchlong(srcaddr); ! 980: int dstreg = (ipc->opcode >> 9) & 7; ! 981: uint32 dstdata = DATAREG(dstreg); ! 982: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 983: ! 984: DATAREG(dstreg) = outdata; ! 985: PC+= 4; ! 986: } ! 987: ! 988: void cpu_op_1428b(t_ipc *ipc) /* ADD */ { ! 989: /* mask f1ff, bits d0b8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 7, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 990: uint32 srcaddr = ipc->src; ! 991: uint32 srcdata = fetchlong(srcaddr); ! 992: int dstreg = (ipc->opcode >> 9) & 7; ! 993: uint32 dstdata = DATAREG(dstreg); ! 994: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 995: ! 996: DATAREG(dstreg) = outdata; ! 997: ! 998: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 999: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 1000: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 1001: NFLAG = ((sint32)outdata) < 0; ! 1002: ZFLAG = !outdata; ! 1003: PC+= 4; ! 1004: } ! 1005: ! 1006: void cpu_op_1429a(t_ipc *ipc) /* ADD */ { ! 1007: /* mask f1ff, bits d0b9, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1008: uint32 srcaddr = ipc->src; ! 1009: uint32 srcdata = fetchlong(srcaddr); ! 1010: int dstreg = (ipc->opcode >> 9) & 7; ! 1011: uint32 dstdata = DATAREG(dstreg); ! 1012: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1013: ! 1014: DATAREG(dstreg) = outdata; ! 1015: PC+= 6; ! 1016: } ! 1017: ! 1018: void cpu_op_1429b(t_ipc *ipc) /* ADD */ { ! 1019: /* mask f1ff, bits d0b9, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 8, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1020: uint32 srcaddr = ipc->src; ! 1021: uint32 srcdata = fetchlong(srcaddr); ! 1022: int dstreg = (ipc->opcode >> 9) & 7; ! 1023: uint32 dstdata = DATAREG(dstreg); ! 1024: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1025: ! 1026: DATAREG(dstreg) = outdata; ! 1027: ! 1028: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 1029: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 1030: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 1031: NFLAG = ((sint32)outdata) < 0; ! 1032: ZFLAG = !outdata; ! 1033: PC+= 6; ! 1034: } ! 1035: ! 1036: void cpu_op_1430a(t_ipc *ipc) /* ADD */ { ! 1037: /* mask f1ff, bits d0ba, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1038: uint32 srcaddr = ipc->src; ! 1039: uint32 srcdata = fetchlong(srcaddr); ! 1040: int dstreg = (ipc->opcode >> 9) & 7; ! 1041: uint32 dstdata = DATAREG(dstreg); ! 1042: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1043: ! 1044: DATAREG(dstreg) = outdata; ! 1045: PC+= 4; ! 1046: } ! 1047: ! 1048: void cpu_op_1430b(t_ipc *ipc) /* ADD */ { ! 1049: /* mask f1ff, bits d0ba, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 9, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1050: uint32 srcaddr = ipc->src; ! 1051: uint32 srcdata = fetchlong(srcaddr); ! 1052: int dstreg = (ipc->opcode >> 9) & 7; ! 1053: uint32 dstdata = DATAREG(dstreg); ! 1054: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1055: ! 1056: DATAREG(dstreg) = outdata; ! 1057: ! 1058: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 1059: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 1060: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 1061: NFLAG = ((sint32)outdata) < 0; ! 1062: ZFLAG = !outdata; ! 1063: PC+= 4; ! 1064: } ! 1065: ! 1066: void cpu_op_1431a(t_ipc *ipc) /* ADD */ { ! 1067: /* mask f1ff, bits d0bb, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1068: uint32 srcaddr = idxval_src(ipc); ! 1069: uint32 srcdata = fetchlong(srcaddr); ! 1070: int dstreg = (ipc->opcode >> 9) & 7; ! 1071: uint32 dstdata = DATAREG(dstreg); ! 1072: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1073: ! 1074: DATAREG(dstreg) = outdata; ! 1075: PC+= 4; ! 1076: } ! 1077: ! 1078: void cpu_op_1431b(t_ipc *ipc) /* ADD */ { ! 1079: /* mask f1ff, bits d0bb, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 10, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1080: uint32 srcaddr = idxval_src(ipc); ! 1081: uint32 srcdata = fetchlong(srcaddr); ! 1082: int dstreg = (ipc->opcode >> 9) & 7; ! 1083: uint32 dstdata = DATAREG(dstreg); ! 1084: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1085: ! 1086: DATAREG(dstreg) = outdata; ! 1087: ! 1088: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 1089: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 1090: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 1091: NFLAG = ((sint32)outdata) < 0; ! 1092: ZFLAG = !outdata; ! 1093: PC+= 4; ! 1094: } ! 1095: ! 1096: void cpu_op_1432a(t_ipc *ipc) /* ADD */ { ! 1097: /* mask f1ff, bits d0bc, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1098: uint32 srcdata = ipc->src; ! 1099: int dstreg = (ipc->opcode >> 9) & 7; ! 1100: uint32 dstdata = DATAREG(dstreg); ! 1101: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1102: ! 1103: DATAREG(dstreg) = outdata; ! 1104: PC+= 6; ! 1105: } ! 1106: ! 1107: void cpu_op_1432b(t_ipc *ipc) /* ADD */ { ! 1108: /* mask f1ff, bits d0bc, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 13, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1109: uint32 srcdata = ipc->src; ! 1110: int dstreg = (ipc->opcode >> 9) & 7; ! 1111: uint32 dstdata = DATAREG(dstreg); ! 1112: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1113: ! 1114: DATAREG(dstreg) = outdata; ! 1115: ! 1116: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 1117: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 1118: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 1119: NFLAG = ((sint32)outdata) < 0; ! 1120: ZFLAG = !outdata; ! 1121: PC+= 6; ! 1122: } ! 1123: ! 1124: void cpu_op_1433a(t_ipc *ipc) /* ADD */ { ! 1125: /* mask f1f8, bits d110, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1126: int srcreg = (ipc->opcode >> 9) & 7; ! 1127: uint8 srcdata = DATAREG(srcreg); ! 1128: int dstreg = (ipc->opcode >> 0) & 7; ! 1129: uint32 dstaddr = ADDRREG(dstreg); ! 1130: uint8 dstdata = fetchbyte(dstaddr); ! 1131: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1132: ! 1133: storebyte(dstaddr, outdata); ! 1134: PC+= 2; ! 1135: } ! 1136: ! 1137: void cpu_op_1433b(t_ipc *ipc) /* ADD */ { ! 1138: /* mask f1f8, bits d110, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1139: int srcreg = (ipc->opcode >> 9) & 7; ! 1140: uint8 srcdata = DATAREG(srcreg); ! 1141: int dstreg = (ipc->opcode >> 0) & 7; ! 1142: uint32 dstaddr = ADDRREG(dstreg); ! 1143: uint8 dstdata = fetchbyte(dstaddr); ! 1144: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1145: ! 1146: storebyte(dstaddr, outdata); ! 1147: ! 1148: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 1149: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 1150: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 1151: NFLAG = ((sint8)outdata) < 0; ! 1152: ZFLAG = !outdata; ! 1153: PC+= 2; ! 1154: } ! 1155: ! 1156: void cpu_op_1434a(t_ipc *ipc) /* ADD */ { ! 1157: /* mask f1f8, bits d118, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1158: int srcreg = (ipc->opcode >> 9) & 7; ! 1159: uint8 srcdata = DATAREG(srcreg); ! 1160: int dstreg = (ipc->opcode >> 0) & 7; ! 1161: uint32 dstaddr = ADDRREG(dstreg); ! 1162: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0); ! 1163: uint8 dstdata = fetchbyte(dstaddr); ! 1164: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1165: ! 1166: storebyte(dstaddr, outdata); ! 1167: PC+= 2; ! 1168: } ! 1169: ! 1170: void cpu_op_1434b(t_ipc *ipc) /* ADD */ { ! 1171: /* mask f1f8, bits d118, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1172: int srcreg = (ipc->opcode >> 9) & 7; ! 1173: uint8 srcdata = DATAREG(srcreg); ! 1174: int dstreg = (ipc->opcode >> 0) & 7; ! 1175: uint32 dstaddr = ADDRREG(dstreg); ! 1176: uint32 dstaddr_tmp = (ADDRREG(dstreg)+= (dstreg == 7 ? 2 : 1), 0); ! 1177: uint8 dstdata = fetchbyte(dstaddr); ! 1178: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1179: ! 1180: storebyte(dstaddr, outdata); ! 1181: ! 1182: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 1183: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 1184: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 1185: NFLAG = ((sint8)outdata) < 0; ! 1186: ZFLAG = !outdata; ! 1187: PC+= 2; ! 1188: } ! 1189: ! 1190: void cpu_op_1435a(t_ipc *ipc) /* ADD */ { ! 1191: /* mask f1f8, bits d120, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1192: int srcreg = (ipc->opcode >> 9) & 7; ! 1193: uint8 srcdata = DATAREG(srcreg); ! 1194: int dstreg = (ipc->opcode >> 0) & 7; ! 1195: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1)); ! 1196: uint8 dstdata = fetchbyte(dstaddr); ! 1197: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1198: ! 1199: storebyte(dstaddr, outdata); ! 1200: PC+= 2; ! 1201: } ! 1202: ! 1203: void cpu_op_1435b(t_ipc *ipc) /* ADD */ { ! 1204: /* mask f1f8, bits d120, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1205: int srcreg = (ipc->opcode >> 9) & 7; ! 1206: uint8 srcdata = DATAREG(srcreg); ! 1207: int dstreg = (ipc->opcode >> 0) & 7; ! 1208: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1)); ! 1209: uint8 dstdata = fetchbyte(dstaddr); ! 1210: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1211: ! 1212: storebyte(dstaddr, outdata); ! 1213: ! 1214: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 1215: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 1216: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 1217: NFLAG = ((sint8)outdata) < 0; ! 1218: ZFLAG = !outdata; ! 1219: PC+= 2; ! 1220: } ! 1221: ! 1222: void cpu_op_1436a(t_ipc *ipc) /* ADD */ { ! 1223: /* mask f1f8, bits d128, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1224: int srcreg = (ipc->opcode >> 9) & 7; ! 1225: uint8 srcdata = DATAREG(srcreg); ! 1226: int dstreg = (ipc->opcode >> 0) & 7; ! 1227: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst; ! 1228: uint8 dstdata = fetchbyte(dstaddr); ! 1229: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1230: ! 1231: storebyte(dstaddr, outdata); ! 1232: PC+= 4; ! 1233: } ! 1234: ! 1235: void cpu_op_1436b(t_ipc *ipc) /* ADD */ { ! 1236: /* mask f1f8, bits d128, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1237: int srcreg = (ipc->opcode >> 9) & 7; ! 1238: uint8 srcdata = DATAREG(srcreg); ! 1239: int dstreg = (ipc->opcode >> 0) & 7; ! 1240: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst; ! 1241: uint8 dstdata = fetchbyte(dstaddr); ! 1242: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1243: ! 1244: storebyte(dstaddr, outdata); ! 1245: ! 1246: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 1247: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 1248: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 1249: NFLAG = ((sint8)outdata) < 0; ! 1250: ZFLAG = !outdata; ! 1251: PC+= 4; ! 1252: } ! 1253: ! 1254: void cpu_op_1437a(t_ipc *ipc) /* ADD */ { ! 1255: /* mask f1f8, bits d130, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1256: int srcreg = (ipc->opcode >> 9) & 7; ! 1257: uint8 srcdata = DATAREG(srcreg); ! 1258: int dstreg = (ipc->opcode >> 0) & 7; ! 1259: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc); ! 1260: uint8 dstdata = fetchbyte(dstaddr); ! 1261: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1262: ! 1263: storebyte(dstaddr, outdata); ! 1264: PC+= 4; ! 1265: } ! 1266: ! 1267: void cpu_op_1437b(t_ipc *ipc) /* ADD */ { ! 1268: /* mask f1f8, bits d130, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1269: int srcreg = (ipc->opcode >> 9) & 7; ! 1270: uint8 srcdata = DATAREG(srcreg); ! 1271: int dstreg = (ipc->opcode >> 0) & 7; ! 1272: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc); ! 1273: uint8 dstdata = fetchbyte(dstaddr); ! 1274: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1275: ! 1276: storebyte(dstaddr, outdata); ! 1277: ! 1278: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 1279: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 1280: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 1281: NFLAG = ((sint8)outdata) < 0; ! 1282: ZFLAG = !outdata; ! 1283: PC+= 4; ! 1284: } ! 1285: ! 1286: void cpu_op_1438a(t_ipc *ipc) /* ADD */ { ! 1287: /* mask f1ff, bits d138, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1288: int srcreg = (ipc->opcode >> 9) & 7; ! 1289: uint8 srcdata = DATAREG(srcreg); ! 1290: uint32 dstaddr = ipc->dst; ! 1291: uint8 dstdata = fetchbyte(dstaddr); ! 1292: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1293: ! 1294: storebyte(dstaddr, outdata); ! 1295: PC+= 4; ! 1296: } ! 1297: ! 1298: void cpu_op_1438b(t_ipc *ipc) /* ADD */ { ! 1299: /* mask f1ff, bits d138, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1300: int srcreg = (ipc->opcode >> 9) & 7; ! 1301: uint8 srcdata = DATAREG(srcreg); ! 1302: uint32 dstaddr = ipc->dst; ! 1303: uint8 dstdata = fetchbyte(dstaddr); ! 1304: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1305: ! 1306: storebyte(dstaddr, outdata); ! 1307: ! 1308: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 1309: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 1310: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 1311: NFLAG = ((sint8)outdata) < 0; ! 1312: ZFLAG = !outdata; ! 1313: PC+= 4; ! 1314: } ! 1315: ! 1316: void cpu_op_1439a(t_ipc *ipc) /* ADD */ { ! 1317: /* mask f1ff, bits d139, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1318: int srcreg = (ipc->opcode >> 9) & 7; ! 1319: uint8 srcdata = DATAREG(srcreg); ! 1320: uint32 dstaddr = ipc->dst; ! 1321: uint8 dstdata = fetchbyte(dstaddr); ! 1322: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1323: ! 1324: storebyte(dstaddr, outdata); ! 1325: PC+= 6; ! 1326: } ! 1327: ! 1328: void cpu_op_1439b(t_ipc *ipc) /* ADD */ { ! 1329: /* mask f1ff, bits d139, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 1, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1330: int srcreg = (ipc->opcode >> 9) & 7; ! 1331: uint8 srcdata = DATAREG(srcreg); ! 1332: uint32 dstaddr = ipc->dst; ! 1333: uint8 dstdata = fetchbyte(dstaddr); ! 1334: uint8 outdata = (sint8)dstdata + (sint8)srcdata; ! 1335: ! 1336: storebyte(dstaddr, outdata); ! 1337: ! 1338: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 1339: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 1340: XFLAG = CFLAG = srcdata > (0xFFu - (uint8)dstdata); ! 1341: NFLAG = ((sint8)outdata) < 0; ! 1342: ZFLAG = !outdata; ! 1343: PC+= 6; ! 1344: } ! 1345: ! 1346: void cpu_op_1440a(t_ipc *ipc) /* ADD */ { ! 1347: /* mask f1f8, bits d150, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1348: int srcreg = (ipc->opcode >> 9) & 7; ! 1349: uint16 srcdata = DATAREG(srcreg); ! 1350: int dstreg = (ipc->opcode >> 0) & 7; ! 1351: uint32 dstaddr = ADDRREG(dstreg); ! 1352: uint16 dstdata = fetchword(dstaddr); ! 1353: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1354: ! 1355: storeword(dstaddr, outdata); ! 1356: PC+= 2; ! 1357: } ! 1358: ! 1359: void cpu_op_1440b(t_ipc *ipc) /* ADD */ { ! 1360: /* mask f1f8, bits d150, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1361: int srcreg = (ipc->opcode >> 9) & 7; ! 1362: uint16 srcdata = DATAREG(srcreg); ! 1363: int dstreg = (ipc->opcode >> 0) & 7; ! 1364: uint32 dstaddr = ADDRREG(dstreg); ! 1365: uint16 dstdata = fetchword(dstaddr); ! 1366: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1367: ! 1368: storeword(dstaddr, outdata); ! 1369: ! 1370: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 1371: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 1372: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 1373: NFLAG = ((sint16)outdata) < 0; ! 1374: ZFLAG = !outdata; ! 1375: PC+= 2; ! 1376: } ! 1377: ! 1378: void cpu_op_1441a(t_ipc *ipc) /* ADD */ { ! 1379: /* mask f1f8, bits d158, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1380: int srcreg = (ipc->opcode >> 9) & 7; ! 1381: uint16 srcdata = DATAREG(srcreg); ! 1382: int dstreg = (ipc->opcode >> 0) & 7; ! 1383: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2); ! 1384: uint16 dstdata = fetchword(dstaddr); ! 1385: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1386: ! 1387: storeword(dstaddr, outdata); ! 1388: PC+= 2; ! 1389: } ! 1390: ! 1391: void cpu_op_1441b(t_ipc *ipc) /* ADD */ { ! 1392: /* mask f1f8, bits d158, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1393: int srcreg = (ipc->opcode >> 9) & 7; ! 1394: uint16 srcdata = DATAREG(srcreg); ! 1395: int dstreg = (ipc->opcode >> 0) & 7; ! 1396: uint32 dstaddr = (ADDRREG(dstreg)+=2, ADDRREG(dstreg)-2); ! 1397: uint16 dstdata = fetchword(dstaddr); ! 1398: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1399: ! 1400: storeword(dstaddr, outdata); ! 1401: ! 1402: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 1403: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 1404: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 1405: NFLAG = ((sint16)outdata) < 0; ! 1406: ZFLAG = !outdata; ! 1407: PC+= 2; ! 1408: } ! 1409: ! 1410: void cpu_op_1442a(t_ipc *ipc) /* ADD */ { ! 1411: /* mask f1f8, bits d160, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1412: int srcreg = (ipc->opcode >> 9) & 7; ! 1413: uint16 srcdata = DATAREG(srcreg); ! 1414: int dstreg = (ipc->opcode >> 0) & 7; ! 1415: uint32 dstaddr = ADDRREG(dstreg)-=2; ! 1416: uint16 dstdata = fetchword(dstaddr); ! 1417: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1418: ! 1419: storeword(dstaddr, outdata); ! 1420: PC+= 2; ! 1421: } ! 1422: ! 1423: void cpu_op_1442b(t_ipc *ipc) /* ADD */ { ! 1424: /* mask f1f8, bits d160, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1425: int srcreg = (ipc->opcode >> 9) & 7; ! 1426: uint16 srcdata = DATAREG(srcreg); ! 1427: int dstreg = (ipc->opcode >> 0) & 7; ! 1428: uint32 dstaddr = ADDRREG(dstreg)-=2; ! 1429: uint16 dstdata = fetchword(dstaddr); ! 1430: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1431: ! 1432: storeword(dstaddr, outdata); ! 1433: ! 1434: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 1435: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 1436: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 1437: NFLAG = ((sint16)outdata) < 0; ! 1438: ZFLAG = !outdata; ! 1439: PC+= 2; ! 1440: } ! 1441: ! 1442: void cpu_op_1443a(t_ipc *ipc) /* ADD */ { ! 1443: /* mask f1f8, bits d168, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1444: int srcreg = (ipc->opcode >> 9) & 7; ! 1445: uint16 srcdata = DATAREG(srcreg); ! 1446: int dstreg = (ipc->opcode >> 0) & 7; ! 1447: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst; ! 1448: uint16 dstdata = fetchword(dstaddr); ! 1449: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1450: ! 1451: storeword(dstaddr, outdata); ! 1452: PC+= 4; ! 1453: } ! 1454: ! 1455: void cpu_op_1443b(t_ipc *ipc) /* ADD */ { ! 1456: /* mask f1f8, bits d168, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1457: int srcreg = (ipc->opcode >> 9) & 7; ! 1458: uint16 srcdata = DATAREG(srcreg); ! 1459: int dstreg = (ipc->opcode >> 0) & 7; ! 1460: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst; ! 1461: uint16 dstdata = fetchword(dstaddr); ! 1462: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1463: ! 1464: storeword(dstaddr, outdata); ! 1465: ! 1466: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 1467: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 1468: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 1469: NFLAG = ((sint16)outdata) < 0; ! 1470: ZFLAG = !outdata; ! 1471: PC+= 4; ! 1472: } ! 1473: ! 1474: void cpu_op_1444a(t_ipc *ipc) /* ADD */ { ! 1475: /* mask f1f8, bits d170, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1476: int srcreg = (ipc->opcode >> 9) & 7; ! 1477: uint16 srcdata = DATAREG(srcreg); ! 1478: int dstreg = (ipc->opcode >> 0) & 7; ! 1479: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc); ! 1480: uint16 dstdata = fetchword(dstaddr); ! 1481: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1482: ! 1483: storeword(dstaddr, outdata); ! 1484: PC+= 4; ! 1485: } ! 1486: ! 1487: void cpu_op_1444b(t_ipc *ipc) /* ADD */ { ! 1488: /* mask f1f8, bits d170, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1489: int srcreg = (ipc->opcode >> 9) & 7; ! 1490: uint16 srcdata = DATAREG(srcreg); ! 1491: int dstreg = (ipc->opcode >> 0) & 7; ! 1492: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc); ! 1493: uint16 dstdata = fetchword(dstaddr); ! 1494: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1495: ! 1496: storeword(dstaddr, outdata); ! 1497: ! 1498: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 1499: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 1500: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 1501: NFLAG = ((sint16)outdata) < 0; ! 1502: ZFLAG = !outdata; ! 1503: PC+= 4; ! 1504: } ! 1505: ! 1506: void cpu_op_1445a(t_ipc *ipc) /* ADD */ { ! 1507: /* mask f1ff, bits d178, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1508: int srcreg = (ipc->opcode >> 9) & 7; ! 1509: uint16 srcdata = DATAREG(srcreg); ! 1510: uint32 dstaddr = ipc->dst; ! 1511: uint16 dstdata = fetchword(dstaddr); ! 1512: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1513: ! 1514: storeword(dstaddr, outdata); ! 1515: PC+= 4; ! 1516: } ! 1517: ! 1518: void cpu_op_1445b(t_ipc *ipc) /* ADD */ { ! 1519: /* mask f1ff, bits d178, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1520: int srcreg = (ipc->opcode >> 9) & 7; ! 1521: uint16 srcdata = DATAREG(srcreg); ! 1522: uint32 dstaddr = ipc->dst; ! 1523: uint16 dstdata = fetchword(dstaddr); ! 1524: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1525: ! 1526: storeword(dstaddr, outdata); ! 1527: ! 1528: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 1529: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 1530: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 1531: NFLAG = ((sint16)outdata) < 0; ! 1532: ZFLAG = !outdata; ! 1533: PC+= 4; ! 1534: } ! 1535: ! 1536: void cpu_op_1446a(t_ipc *ipc) /* ADD */ { ! 1537: /* mask f1ff, bits d179, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1538: int srcreg = (ipc->opcode >> 9) & 7; ! 1539: uint16 srcdata = DATAREG(srcreg); ! 1540: uint32 dstaddr = ipc->dst; ! 1541: uint16 dstdata = fetchword(dstaddr); ! 1542: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1543: ! 1544: storeword(dstaddr, outdata); ! 1545: PC+= 6; ! 1546: } ! 1547: ! 1548: void cpu_op_1446b(t_ipc *ipc) /* ADD */ { ! 1549: /* mask f1ff, bits d179, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 2, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1550: int srcreg = (ipc->opcode >> 9) & 7; ! 1551: uint16 srcdata = DATAREG(srcreg); ! 1552: uint32 dstaddr = ipc->dst; ! 1553: uint16 dstdata = fetchword(dstaddr); ! 1554: uint16 outdata = (sint16)dstdata + (sint16)srcdata; ! 1555: ! 1556: storeword(dstaddr, outdata); ! 1557: ! 1558: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 1559: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 1560: XFLAG = CFLAG = srcdata > (0xFFFFu - (uint16)dstdata); ! 1561: NFLAG = ((sint16)outdata) < 0; ! 1562: ZFLAG = !outdata; ! 1563: PC+= 6; ! 1564: } ! 1565: ! 1566: void cpu_op_1447a(t_ipc *ipc) /* ADD */ { ! 1567: /* mask f1f8, bits d190, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1568: int srcreg = (ipc->opcode >> 9) & 7; ! 1569: uint32 srcdata = DATAREG(srcreg); ! 1570: int dstreg = (ipc->opcode >> 0) & 7; ! 1571: uint32 dstaddr = ADDRREG(dstreg); ! 1572: uint32 dstdata = fetchlong(dstaddr); ! 1573: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1574: ! 1575: storelong(dstaddr, outdata); ! 1576: PC+= 2; ! 1577: } ! 1578: ! 1579: void cpu_op_1447b(t_ipc *ipc) /* ADD */ { ! 1580: /* mask f1f8, bits d190, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 2, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1581: int srcreg = (ipc->opcode >> 9) & 7; ! 1582: uint32 srcdata = DATAREG(srcreg); ! 1583: int dstreg = (ipc->opcode >> 0) & 7; ! 1584: uint32 dstaddr = ADDRREG(dstreg); ! 1585: uint32 dstdata = fetchlong(dstaddr); ! 1586: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1587: ! 1588: storelong(dstaddr, outdata); ! 1589: ! 1590: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 1591: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 1592: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 1593: NFLAG = ((sint32)outdata) < 0; ! 1594: ZFLAG = !outdata; ! 1595: PC+= 2; ! 1596: } ! 1597: ! 1598: void cpu_op_1448a(t_ipc *ipc) /* ADD */ { ! 1599: /* mask f1f8, bits d198, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1600: int srcreg = (ipc->opcode >> 9) & 7; ! 1601: uint32 srcdata = DATAREG(srcreg); ! 1602: int dstreg = (ipc->opcode >> 0) & 7; ! 1603: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4); ! 1604: uint32 dstdata = fetchlong(dstaddr); ! 1605: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1606: ! 1607: storelong(dstaddr, outdata); ! 1608: PC+= 2; ! 1609: } ! 1610: ! 1611: void cpu_op_1448b(t_ipc *ipc) /* ADD */ { ! 1612: /* mask f1f8, bits d198, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 3, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1613: int srcreg = (ipc->opcode >> 9) & 7; ! 1614: uint32 srcdata = DATAREG(srcreg); ! 1615: int dstreg = (ipc->opcode >> 0) & 7; ! 1616: uint32 dstaddr = (ADDRREG(dstreg)+=4, ADDRREG(dstreg)-4); ! 1617: uint32 dstdata = fetchlong(dstaddr); ! 1618: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1619: ! 1620: storelong(dstaddr, outdata); ! 1621: ! 1622: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 1623: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 1624: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 1625: NFLAG = ((sint32)outdata) < 0; ! 1626: ZFLAG = !outdata; ! 1627: PC+= 2; ! 1628: } ! 1629: ! 1630: void cpu_op_1449a(t_ipc *ipc) /* ADD */ { ! 1631: /* mask f1f8, bits d1a0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1632: int srcreg = (ipc->opcode >> 9) & 7; ! 1633: uint32 srcdata = DATAREG(srcreg); ! 1634: int dstreg = (ipc->opcode >> 0) & 7; ! 1635: uint32 dstaddr = ADDRREG(dstreg)-=4; ! 1636: uint32 dstdata = fetchlong(dstaddr); ! 1637: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1638: ! 1639: storelong(dstaddr, outdata); ! 1640: PC+= 2; ! 1641: } ! 1642: ! 1643: void cpu_op_1449b(t_ipc *ipc) /* ADD */ { ! 1644: /* mask f1f8, bits d1a0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 4, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1645: int srcreg = (ipc->opcode >> 9) & 7; ! 1646: uint32 srcdata = DATAREG(srcreg); ! 1647: int dstreg = (ipc->opcode >> 0) & 7; ! 1648: uint32 dstaddr = ADDRREG(dstreg)-=4; ! 1649: uint32 dstdata = fetchlong(dstaddr); ! 1650: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1651: ! 1652: storelong(dstaddr, outdata); ! 1653: ! 1654: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 1655: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 1656: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 1657: NFLAG = ((sint32)outdata) < 0; ! 1658: ZFLAG = !outdata; ! 1659: PC+= 2; ! 1660: } ! 1661: ! 1662: void cpu_op_1450a(t_ipc *ipc) /* ADD */ { ! 1663: /* mask f1f8, bits d1a8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1664: int srcreg = (ipc->opcode >> 9) & 7; ! 1665: uint32 srcdata = DATAREG(srcreg); ! 1666: int dstreg = (ipc->opcode >> 0) & 7; ! 1667: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst; ! 1668: uint32 dstdata = fetchlong(dstaddr); ! 1669: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1670: ! 1671: storelong(dstaddr, outdata); ! 1672: PC+= 4; ! 1673: } ! 1674: ! 1675: void cpu_op_1450b(t_ipc *ipc) /* ADD */ { ! 1676: /* mask f1f8, bits d1a8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 5, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1677: int srcreg = (ipc->opcode >> 9) & 7; ! 1678: uint32 srcdata = DATAREG(srcreg); ! 1679: int dstreg = (ipc->opcode >> 0) & 7; ! 1680: uint32 dstaddr = (sint32)ADDRREG(dstreg) + (sint32)(sint16)ipc->dst; ! 1681: uint32 dstdata = fetchlong(dstaddr); ! 1682: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1683: ! 1684: storelong(dstaddr, outdata); ! 1685: ! 1686: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 1687: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 1688: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 1689: NFLAG = ((sint32)outdata) < 0; ! 1690: ZFLAG = !outdata; ! 1691: PC+= 4; ! 1692: } ! 1693: ! 1694: void cpu_op_1451a(t_ipc *ipc) /* ADD */ { ! 1695: /* mask f1f8, bits d1b0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1696: int srcreg = (ipc->opcode >> 9) & 7; ! 1697: uint32 srcdata = DATAREG(srcreg); ! 1698: int dstreg = (ipc->opcode >> 0) & 7; ! 1699: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc); ! 1700: uint32 dstdata = fetchlong(dstaddr); ! 1701: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1702: ! 1703: storelong(dstaddr, outdata); ! 1704: PC+= 4; ! 1705: } ! 1706: ! 1707: void cpu_op_1451b(t_ipc *ipc) /* ADD */ { ! 1708: /* mask f1f8, bits d1b0, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 6, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1709: int srcreg = (ipc->opcode >> 9) & 7; ! 1710: uint32 srcdata = DATAREG(srcreg); ! 1711: int dstreg = (ipc->opcode >> 0) & 7; ! 1712: uint32 dstaddr = (sint32)ADDRREG(dstreg) + idxval_dst(ipc); ! 1713: uint32 dstdata = fetchlong(dstaddr); ! 1714: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1715: ! 1716: storelong(dstaddr, outdata); ! 1717: ! 1718: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 1719: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 1720: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 1721: NFLAG = ((sint32)outdata) < 0; ! 1722: ZFLAG = !outdata; ! 1723: PC+= 4; ! 1724: } ! 1725: ! 1726: void cpu_op_1452a(t_ipc *ipc) /* ADD */ { ! 1727: /* mask f1ff, bits d1b8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1728: int srcreg = (ipc->opcode >> 9) & 7; ! 1729: uint32 srcdata = DATAREG(srcreg); ! 1730: uint32 dstaddr = ipc->dst; ! 1731: uint32 dstdata = fetchlong(dstaddr); ! 1732: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1733: ! 1734: storelong(dstaddr, outdata); ! 1735: PC+= 4; ! 1736: } ! 1737: ! 1738: void cpu_op_1452b(t_ipc *ipc) /* ADD */ { ! 1739: /* mask f1ff, bits d1b8, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 7, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1740: int srcreg = (ipc->opcode >> 9) & 7; ! 1741: uint32 srcdata = DATAREG(srcreg); ! 1742: uint32 dstaddr = ipc->dst; ! 1743: uint32 dstdata = fetchlong(dstaddr); ! 1744: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1745: ! 1746: storelong(dstaddr, outdata); ! 1747: ! 1748: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 1749: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 1750: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 1751: NFLAG = ((sint32)outdata) < 0; ! 1752: ZFLAG = !outdata; ! 1753: PC+= 4; ! 1754: } ! 1755: ! 1756: void cpu_op_1453a(t_ipc *ipc) /* ADD */ { ! 1757: /* mask f1ff, bits d1b9, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1758: int srcreg = (ipc->opcode >> 9) & 7; ! 1759: uint32 srcdata = DATAREG(srcreg); ! 1760: uint32 dstaddr = ipc->dst; ! 1761: uint32 dstdata = fetchlong(dstaddr); ! 1762: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1763: ! 1764: storelong(dstaddr, outdata); ! 1765: PC+= 6; ! 1766: } ! 1767: ! 1768: void cpu_op_1453b(t_ipc *ipc) /* ADD */ { ! 1769: /* mask f1ff, bits d1b9, mnemonic 10, priv 0, endblk 0, imm_notzero 0, used 0 set -1, size 3, stype 0, dtype 8, sbitpos 9, dbitpos 0, immvalue 0 */ ! 1770: int srcreg = (ipc->opcode >> 9) & 7; ! 1771: uint32 srcdata = DATAREG(srcreg); ! 1772: uint32 dstaddr = ipc->dst; ! 1773: uint32 dstdata = fetchlong(dstaddr); ! 1774: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1775: ! 1776: storelong(dstaddr, outdata); ! 1777: ! 1778: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 1779: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 1780: XFLAG = CFLAG = srcdata > (uint32)~(uint32)dstdata; ! 1781: NFLAG = ((sint32)outdata) < 0; ! 1782: ZFLAG = !outdata; ! 1783: PC+= 6; ! 1784: } ! 1785: ! 1786: void cpu_op_1454a(t_ipc *ipc) /* ADDA */ { ! 1787: /* mask f1f8, bits d0c0, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 0, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1788: int srcreg = (ipc->opcode >> 0) & 7; ! 1789: uint16 srcdata = DATAREG(srcreg); ! 1790: int dstreg = (ipc->opcode >> 9) & 7; ! 1791: uint32 dstdata = ADDRREG(dstreg); ! 1792: uint32 outdata = (sint32)dstdata + (sint16)srcdata; ! 1793: ! 1794: ADDRREG(dstreg) = outdata; ! 1795: PC+= 2; ! 1796: } ! 1797: ! 1798: void cpu_op_1455a(t_ipc *ipc) /* ADDA */ { ! 1799: /* mask f1f8, bits d0c8, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 1, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1800: int srcreg = (ipc->opcode >> 0) & 7; ! 1801: uint16 srcdata = ADDRREG(srcreg); ! 1802: int dstreg = (ipc->opcode >> 9) & 7; ! 1803: uint32 dstdata = ADDRREG(dstreg); ! 1804: uint32 outdata = (sint32)dstdata + (sint16)srcdata; ! 1805: ! 1806: ADDRREG(dstreg) = outdata; ! 1807: PC+= 2; ! 1808: } ! 1809: ! 1810: void cpu_op_1456a(t_ipc *ipc) /* ADDA */ { ! 1811: /* mask f1f8, bits d0d0, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 2, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1812: int srcreg = (ipc->opcode >> 0) & 7; ! 1813: uint32 srcaddr = ADDRREG(srcreg); ! 1814: uint16 srcdata = fetchword(srcaddr); ! 1815: int dstreg = (ipc->opcode >> 9) & 7; ! 1816: uint32 dstdata = ADDRREG(dstreg); ! 1817: uint32 outdata = (sint32)dstdata + (sint16)srcdata; ! 1818: ! 1819: ADDRREG(dstreg) = outdata; ! 1820: PC+= 2; ! 1821: } ! 1822: ! 1823: void cpu_op_1457a(t_ipc *ipc) /* ADDA */ { ! 1824: /* mask f1f8, bits d0d8, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 3, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1825: int srcreg = (ipc->opcode >> 0) & 7; ! 1826: uint32 srcaddr = (ADDRREG(srcreg)+=2, ADDRREG(srcreg)-2); ! 1827: uint16 srcdata = fetchword(srcaddr); ! 1828: int dstreg = (ipc->opcode >> 9) & 7; ! 1829: uint32 dstdata = ADDRREG(dstreg); ! 1830: uint32 outdata = (sint32)dstdata + (sint16)srcdata; ! 1831: ! 1832: ADDRREG(dstreg) = outdata; ! 1833: PC+= 2; ! 1834: } ! 1835: ! 1836: void cpu_op_1458a(t_ipc *ipc) /* ADDA */ { ! 1837: /* mask f1f8, bits d0e0, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 4, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1838: int srcreg = (ipc->opcode >> 0) & 7; ! 1839: uint32 srcaddr = ADDRREG(srcreg)-=2; ! 1840: uint16 srcdata = fetchword(srcaddr); ! 1841: int dstreg = (ipc->opcode >> 9) & 7; ! 1842: uint32 dstdata = ADDRREG(dstreg); ! 1843: uint32 outdata = (sint32)dstdata + (sint16)srcdata; ! 1844: ! 1845: ADDRREG(dstreg) = outdata; ! 1846: PC+= 2; ! 1847: } ! 1848: ! 1849: void cpu_op_1459a(t_ipc *ipc) /* ADDA */ { ! 1850: /* mask f1f8, bits d0e8, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 5, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1851: int srcreg = (ipc->opcode >> 0) & 7; ! 1852: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 1853: uint16 srcdata = fetchword(srcaddr); ! 1854: int dstreg = (ipc->opcode >> 9) & 7; ! 1855: uint32 dstdata = ADDRREG(dstreg); ! 1856: uint32 outdata = (sint32)dstdata + (sint16)srcdata; ! 1857: ! 1858: ADDRREG(dstreg) = outdata; ! 1859: PC+= 4; ! 1860: } ! 1861: ! 1862: void cpu_op_1460a(t_ipc *ipc) /* ADDA */ { ! 1863: /* mask f1f8, bits d0f0, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 6, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1864: int srcreg = (ipc->opcode >> 0) & 7; ! 1865: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 1866: uint16 srcdata = fetchword(srcaddr); ! 1867: int dstreg = (ipc->opcode >> 9) & 7; ! 1868: uint32 dstdata = ADDRREG(dstreg); ! 1869: uint32 outdata = (sint32)dstdata + (sint16)srcdata; ! 1870: ! 1871: ADDRREG(dstreg) = outdata; ! 1872: PC+= 4; ! 1873: } ! 1874: ! 1875: void cpu_op_1461a(t_ipc *ipc) /* ADDA */ { ! 1876: /* mask f1ff, bits d0f8, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 7, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1877: uint32 srcaddr = ipc->src; ! 1878: uint16 srcdata = fetchword(srcaddr); ! 1879: int dstreg = (ipc->opcode >> 9) & 7; ! 1880: uint32 dstdata = ADDRREG(dstreg); ! 1881: uint32 outdata = (sint32)dstdata + (sint16)srcdata; ! 1882: ! 1883: ADDRREG(dstreg) = outdata; ! 1884: PC+= 4; ! 1885: } ! 1886: ! 1887: void cpu_op_1462a(t_ipc *ipc) /* ADDA */ { ! 1888: /* mask f1ff, bits d0f9, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 8, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1889: uint32 srcaddr = ipc->src; ! 1890: uint16 srcdata = fetchword(srcaddr); ! 1891: int dstreg = (ipc->opcode >> 9) & 7; ! 1892: uint32 dstdata = ADDRREG(dstreg); ! 1893: uint32 outdata = (sint32)dstdata + (sint16)srcdata; ! 1894: ! 1895: ADDRREG(dstreg) = outdata; ! 1896: PC+= 6; ! 1897: } ! 1898: ! 1899: void cpu_op_1463a(t_ipc *ipc) /* ADDA */ { ! 1900: /* mask f1ff, bits d0fa, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 9, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1901: uint32 srcaddr = ipc->src; ! 1902: uint16 srcdata = fetchword(srcaddr); ! 1903: int dstreg = (ipc->opcode >> 9) & 7; ! 1904: uint32 dstdata = ADDRREG(dstreg); ! 1905: uint32 outdata = (sint32)dstdata + (sint16)srcdata; ! 1906: ! 1907: ADDRREG(dstreg) = outdata; ! 1908: PC+= 4; ! 1909: } ! 1910: ! 1911: void cpu_op_1464a(t_ipc *ipc) /* ADDA */ { ! 1912: /* mask f1ff, bits d0fb, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 10, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1913: uint32 srcaddr = idxval_src(ipc); ! 1914: uint16 srcdata = fetchword(srcaddr); ! 1915: int dstreg = (ipc->opcode >> 9) & 7; ! 1916: uint32 dstdata = ADDRREG(dstreg); ! 1917: uint32 outdata = (sint32)dstdata + (sint16)srcdata; ! 1918: ! 1919: ADDRREG(dstreg) = outdata; ! 1920: PC+= 4; ! 1921: } ! 1922: ! 1923: void cpu_op_1465a(t_ipc *ipc) /* ADDA */ { ! 1924: /* mask f1ff, bits d0fc, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 2, stype 12, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1925: uint16 srcdata = ipc->src; ! 1926: int dstreg = (ipc->opcode >> 9) & 7; ! 1927: uint32 dstdata = ADDRREG(dstreg); ! 1928: uint32 outdata = (sint32)dstdata + (sint16)srcdata; ! 1929: ! 1930: ADDRREG(dstreg) = outdata; ! 1931: PC+= 4; ! 1932: } ! 1933: ! 1934: void cpu_op_1466a(t_ipc *ipc) /* ADDA */ { ! 1935: /* mask f1f8, bits d1c0, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 0, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1936: int srcreg = (ipc->opcode >> 0) & 7; ! 1937: uint32 srcdata = DATAREG(srcreg); ! 1938: int dstreg = (ipc->opcode >> 9) & 7; ! 1939: uint32 dstdata = ADDRREG(dstreg); ! 1940: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1941: ! 1942: ADDRREG(dstreg) = outdata; ! 1943: PC+= 2; ! 1944: } ! 1945: ! 1946: void cpu_op_1467a(t_ipc *ipc) /* ADDA */ { ! 1947: /* mask f1f8, bits d1c8, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 1, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1948: int srcreg = (ipc->opcode >> 0) & 7; ! 1949: uint32 srcdata = ADDRREG(srcreg); ! 1950: int dstreg = (ipc->opcode >> 9) & 7; ! 1951: uint32 dstdata = ADDRREG(dstreg); ! 1952: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1953: ! 1954: ADDRREG(dstreg) = outdata; ! 1955: PC+= 2; ! 1956: } ! 1957: ! 1958: void cpu_op_1468a(t_ipc *ipc) /* ADDA */ { ! 1959: /* mask f1f8, bits d1d0, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 2, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1960: int srcreg = (ipc->opcode >> 0) & 7; ! 1961: uint32 srcaddr = ADDRREG(srcreg); ! 1962: uint32 srcdata = fetchlong(srcaddr); ! 1963: int dstreg = (ipc->opcode >> 9) & 7; ! 1964: uint32 dstdata = ADDRREG(dstreg); ! 1965: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1966: ! 1967: ADDRREG(dstreg) = outdata; ! 1968: PC+= 2; ! 1969: } ! 1970: ! 1971: void cpu_op_1469a(t_ipc *ipc) /* ADDA */ { ! 1972: /* mask f1f8, bits d1d8, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 3, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1973: int srcreg = (ipc->opcode >> 0) & 7; ! 1974: uint32 srcaddr = (ADDRREG(srcreg)+=4, ADDRREG(srcreg)-4); ! 1975: uint32 srcdata = fetchlong(srcaddr); ! 1976: int dstreg = (ipc->opcode >> 9) & 7; ! 1977: uint32 dstdata = ADDRREG(dstreg); ! 1978: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1979: ! 1980: ADDRREG(dstreg) = outdata; ! 1981: PC+= 2; ! 1982: } ! 1983: ! 1984: void cpu_op_1470a(t_ipc *ipc) /* ADDA */ { ! 1985: /* mask f1f8, bits d1e0, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 4, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1986: int srcreg = (ipc->opcode >> 0) & 7; ! 1987: uint32 srcaddr = ADDRREG(srcreg)-=4; ! 1988: uint32 srcdata = fetchlong(srcaddr); ! 1989: int dstreg = (ipc->opcode >> 9) & 7; ! 1990: uint32 dstdata = ADDRREG(dstreg); ! 1991: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 1992: ! 1993: ADDRREG(dstreg) = outdata; ! 1994: PC+= 2; ! 1995: } ! 1996: ! 1997: void cpu_op_1471a(t_ipc *ipc) /* ADDA */ { ! 1998: /* mask f1f8, bits d1e8, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 5, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 1999: int srcreg = (ipc->opcode >> 0) & 7; ! 2000: uint32 srcaddr = (sint32)ADDRREG(srcreg) + (sint32)(sint16)ipc->src; ! 2001: uint32 srcdata = fetchlong(srcaddr); ! 2002: int dstreg = (ipc->opcode >> 9) & 7; ! 2003: uint32 dstdata = ADDRREG(dstreg); ! 2004: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 2005: ! 2006: ADDRREG(dstreg) = outdata; ! 2007: PC+= 4; ! 2008: } ! 2009: ! 2010: void cpu_op_1472a(t_ipc *ipc) /* ADDA */ { ! 2011: /* mask f1f8, bits d1f0, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 6, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2012: int srcreg = (ipc->opcode >> 0) & 7; ! 2013: uint32 srcaddr = (sint32)ADDRREG(srcreg) + idxval_src(ipc); ! 2014: uint32 srcdata = fetchlong(srcaddr); ! 2015: int dstreg = (ipc->opcode >> 9) & 7; ! 2016: uint32 dstdata = ADDRREG(dstreg); ! 2017: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 2018: ! 2019: ADDRREG(dstreg) = outdata; ! 2020: PC+= 4; ! 2021: } ! 2022: ! 2023: void cpu_op_1473a(t_ipc *ipc) /* ADDA */ { ! 2024: /* mask f1ff, bits d1f8, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 7, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2025: uint32 srcaddr = ipc->src; ! 2026: uint32 srcdata = fetchlong(srcaddr); ! 2027: int dstreg = (ipc->opcode >> 9) & 7; ! 2028: uint32 dstdata = ADDRREG(dstreg); ! 2029: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 2030: ! 2031: ADDRREG(dstreg) = outdata; ! 2032: PC+= 4; ! 2033: } ! 2034: ! 2035: void cpu_op_1474a(t_ipc *ipc) /* ADDA */ { ! 2036: /* mask f1ff, bits d1f9, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 8, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2037: uint32 srcaddr = ipc->src; ! 2038: uint32 srcdata = fetchlong(srcaddr); ! 2039: int dstreg = (ipc->opcode >> 9) & 7; ! 2040: uint32 dstdata = ADDRREG(dstreg); ! 2041: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 2042: ! 2043: ADDRREG(dstreg) = outdata; ! 2044: PC+= 6; ! 2045: } ! 2046: ! 2047: void cpu_op_1475a(t_ipc *ipc) /* ADDA */ { ! 2048: /* mask f1ff, bits d1fa, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 9, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2049: uint32 srcaddr = ipc->src; ! 2050: uint32 srcdata = fetchlong(srcaddr); ! 2051: int dstreg = (ipc->opcode >> 9) & 7; ! 2052: uint32 dstdata = ADDRREG(dstreg); ! 2053: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 2054: ! 2055: ADDRREG(dstreg) = outdata; ! 2056: PC+= 4; ! 2057: } ! 2058: ! 2059: void cpu_op_1476a(t_ipc *ipc) /* ADDA */ { ! 2060: /* mask f1ff, bits d1fb, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 10, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2061: uint32 srcaddr = idxval_src(ipc); ! 2062: uint32 srcdata = fetchlong(srcaddr); ! 2063: int dstreg = (ipc->opcode >> 9) & 7; ! 2064: uint32 dstdata = ADDRREG(dstreg); ! 2065: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 2066: ! 2067: ADDRREG(dstreg) = outdata; ! 2068: PC+= 4; ! 2069: } ! 2070: ! 2071: void cpu_op_1477a(t_ipc *ipc) /* ADDA */ { ! 2072: /* mask f1ff, bits d1fc, mnemonic 11, priv 0, endblk 0, imm_notzero 0, used 0 set 0, size 3, stype 13, dtype 1, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2073: uint32 srcdata = ipc->src; ! 2074: int dstreg = (ipc->opcode >> 9) & 7; ! 2075: uint32 dstdata = ADDRREG(dstreg); ! 2076: uint32 outdata = (sint32)dstdata + (sint32)srcdata; ! 2077: ! 2078: ADDRREG(dstreg) = outdata; ! 2079: PC+= 6; ! 2080: } ! 2081: ! 2082: void cpu_op_1478a(t_ipc *ipc) /* ADDX */ { ! 2083: /* mask f1f8, bits d100, mnemonic 12, priv 0, endblk 0, imm_notzero 0, used 5 set -1, size 1, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2084: int srcreg = (ipc->opcode >> 0) & 7; ! 2085: uint8 srcdata = DATAREG(srcreg); ! 2086: int dstreg = (ipc->opcode >> 9) & 7; ! 2087: uint8 dstdata = DATAREG(dstreg); ! 2088: uint8 outdata = (sint8)dstdata + (sint8)srcdata + XFLAG; ! 2089: ! 2090: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 2091: PC+= 2; ! 2092: } ! 2093: ! 2094: void cpu_op_1478b(t_ipc *ipc) /* ADDX */ { ! 2095: /* mask f1f8, bits d100, mnemonic 12, priv 0, endblk 0, imm_notzero 0, used 5 set -1, size 1, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2096: int srcreg = (ipc->opcode >> 0) & 7; ! 2097: uint8 srcdata = DATAREG(srcreg); ! 2098: int dstreg = (ipc->opcode >> 9) & 7; ! 2099: uint8 dstdata = DATAREG(dstreg); ! 2100: uint8 outdata = (sint8)dstdata + (sint8)srcdata + XFLAG; ! 2101: ! 2102: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xff) | outdata; ! 2103: ! 2104: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 2105: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 2106: { ! 2107: int Sm = (sint8)srcdata < 0; ! 2108: int Dm = (sint8)dstdata < 0; ! 2109: int Rm = (sint8)outdata < 0; ! 2110: XFLAG = CFLAG = (Sm && Dm) || (!Rm && (Dm || Sm)); ! 2111: } ! 2112: NFLAG = ((sint8)outdata) < 0; ! 2113: if (outdata) ZFLAG = 0; ! 2114: PC+= 2; ! 2115: } ! 2116: ! 2117: void cpu_op_1479a(t_ipc *ipc) /* ADDX */ { ! 2118: /* mask f1f8, bits d140, mnemonic 12, priv 0, endblk 0, imm_notzero 0, used 5 set -1, size 2, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2119: int srcreg = (ipc->opcode >> 0) & 7; ! 2120: uint16 srcdata = DATAREG(srcreg); ! 2121: int dstreg = (ipc->opcode >> 9) & 7; ! 2122: uint16 dstdata = DATAREG(dstreg); ! 2123: uint16 outdata = (sint16)dstdata + (sint16)srcdata+ XFLAG; ! 2124: ! 2125: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 2126: PC+= 2; ! 2127: } ! 2128: ! 2129: void cpu_op_1479b(t_ipc *ipc) /* ADDX */ { ! 2130: /* mask f1f8, bits d140, mnemonic 12, priv 0, endblk 0, imm_notzero 0, used 5 set -1, size 2, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2131: int srcreg = (ipc->opcode >> 0) & 7; ! 2132: uint16 srcdata = DATAREG(srcreg); ! 2133: int dstreg = (ipc->opcode >> 9) & 7; ! 2134: uint16 dstdata = DATAREG(dstreg); ! 2135: uint16 outdata = (sint16)dstdata + (sint16)srcdata+ XFLAG; ! 2136: ! 2137: DATAREG(dstreg) = (DATAREG(dstreg) & ~0xffff) | outdata; ! 2138: ! 2139: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 2140: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 2141: { ! 2142: int Sm = (sint16)srcdata < 0; ! 2143: int Dm = (sint16)dstdata < 0; ! 2144: int Rm = (sint16)outdata < 0; ! 2145: XFLAG = CFLAG = (Sm && Dm) || (!Rm && (Dm || Sm)); ! 2146: } ! 2147: NFLAG = ((sint16)outdata) < 0; ! 2148: if (outdata) ZFLAG = 0; ! 2149: PC+= 2; ! 2150: } ! 2151: ! 2152: void cpu_op_1480a(t_ipc *ipc) /* ADDX */ { ! 2153: /* mask f1f8, bits d180, mnemonic 12, priv 0, endblk 0, imm_notzero 0, used 5 set -1, size 3, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2154: int srcreg = (ipc->opcode >> 0) & 7; ! 2155: uint32 srcdata = DATAREG(srcreg); ! 2156: int dstreg = (ipc->opcode >> 9) & 7; ! 2157: uint32 dstdata = DATAREG(dstreg); ! 2158: uint32 outdata = (sint32)dstdata + (sint32)srcdata+ XFLAG; ! 2159: ! 2160: DATAREG(dstreg) = outdata; ! 2161: PC+= 2; ! 2162: } ! 2163: ! 2164: void cpu_op_1480b(t_ipc *ipc) /* ADDX */ { ! 2165: /* mask f1f8, bits d180, mnemonic 12, priv 0, endblk 0, imm_notzero 0, used 5 set -1, size 3, stype 0, dtype 0, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2166: int srcreg = (ipc->opcode >> 0) & 7; ! 2167: uint32 srcdata = DATAREG(srcreg); ! 2168: int dstreg = (ipc->opcode >> 9) & 7; ! 2169: uint32 dstdata = DATAREG(dstreg); ! 2170: uint32 outdata = (sint32)dstdata + (sint32)srcdata+ XFLAG; ! 2171: ! 2172: DATAREG(dstreg) = outdata; ! 2173: ! 2174: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 2175: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 2176: { ! 2177: int Sm = (sint32)srcdata < 0; ! 2178: int Dm = (sint32)dstdata < 0; ! 2179: int Rm = (sint32)outdata < 0; ! 2180: XFLAG = CFLAG = (Sm && Dm) || (!Rm && (Dm || Sm)); ! 2181: } ! 2182: NFLAG = ((sint32)outdata) < 0; ! 2183: if (outdata) ZFLAG = 0; ! 2184: PC+= 2; ! 2185: } ! 2186: ! 2187: void cpu_op_1481a(t_ipc *ipc) /* ADDX */ { ! 2188: /* mask f1f8, bits d108, mnemonic 12, priv 0, endblk 0, imm_notzero 0, used 5 set -1, size 1, stype 4, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2189: int srcreg = (ipc->opcode >> 0) & 7; ! 2190: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1)); ! 2191: uint8 srcdata = fetchbyte(srcaddr); ! 2192: int dstreg = (ipc->opcode >> 9) & 7; ! 2193: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1)); ! 2194: uint8 dstdata = fetchbyte(dstaddr); ! 2195: uint8 outdata = (sint8)dstdata + (sint8)srcdata + XFLAG; ! 2196: ! 2197: storebyte(dstaddr, outdata); ! 2198: PC+= 2; ! 2199: } ! 2200: ! 2201: void cpu_op_1481b(t_ipc *ipc) /* ADDX */ { ! 2202: /* mask f1f8, bits d108, mnemonic 12, priv 0, endblk 0, imm_notzero 0, used 5 set -1, size 1, stype 4, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2203: int srcreg = (ipc->opcode >> 0) & 7; ! 2204: uint32 srcaddr = (ADDRREG(srcreg)-= (srcreg == 7 ? 2 : 1)); ! 2205: uint8 srcdata = fetchbyte(srcaddr); ! 2206: int dstreg = (ipc->opcode >> 9) & 7; ! 2207: uint32 dstaddr = (ADDRREG(dstreg)-= (dstreg == 7 ? 2 : 1)); ! 2208: uint8 dstdata = fetchbyte(dstaddr); ! 2209: uint8 outdata = (sint8)dstdata + (sint8)srcdata + XFLAG; ! 2210: ! 2211: storebyte(dstaddr, outdata); ! 2212: ! 2213: VFLAG = (((sint8)srcdata < 0) == ((sint8)dstdata < 0)) && ! 2214: (((sint8)dstdata < 0) != ((sint8)outdata < 0)); ! 2215: { ! 2216: int Sm = (sint8)srcdata < 0; ! 2217: int Dm = (sint8)dstdata < 0; ! 2218: int Rm = (sint8)outdata < 0; ! 2219: XFLAG = CFLAG = (Sm && Dm) || (!Rm && (Dm || Sm)); ! 2220: } ! 2221: NFLAG = ((sint8)outdata) < 0; ! 2222: if (outdata) ZFLAG = 0; ! 2223: PC+= 2; ! 2224: } ! 2225: ! 2226: void cpu_op_1482a(t_ipc *ipc) /* ADDX */ { ! 2227: /* mask f1f8, bits d148, mnemonic 12, priv 0, endblk 0, imm_notzero 0, used 5 set -1, size 2, stype 4, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2228: int srcreg = (ipc->opcode >> 0) & 7; ! 2229: uint32 srcaddr = ADDRREG(srcreg)-=2; ! 2230: uint16 srcdata = fetchword(srcaddr); ! 2231: int dstreg = (ipc->opcode >> 9) & 7; ! 2232: uint32 dstaddr = ADDRREG(dstreg)-=2; ! 2233: uint16 dstdata = fetchword(dstaddr); ! 2234: uint16 outdata = (sint16)dstdata + (sint16)srcdata+ XFLAG; ! 2235: ! 2236: storeword(dstaddr, outdata); ! 2237: PC+= 2; ! 2238: } ! 2239: ! 2240: void cpu_op_1482b(t_ipc *ipc) /* ADDX */ { ! 2241: /* mask f1f8, bits d148, mnemonic 12, priv 0, endblk 0, imm_notzero 0, used 5 set -1, size 2, stype 4, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2242: int srcreg = (ipc->opcode >> 0) & 7; ! 2243: uint32 srcaddr = ADDRREG(srcreg)-=2; ! 2244: uint16 srcdata = fetchword(srcaddr); ! 2245: int dstreg = (ipc->opcode >> 9) & 7; ! 2246: uint32 dstaddr = ADDRREG(dstreg)-=2; ! 2247: uint16 dstdata = fetchword(dstaddr); ! 2248: uint16 outdata = (sint16)dstdata + (sint16)srcdata+ XFLAG; ! 2249: ! 2250: storeword(dstaddr, outdata); ! 2251: ! 2252: VFLAG = (((sint16)srcdata < 0) == ((sint16)dstdata < 0)) && ! 2253: (((sint16)dstdata < 0) != ((sint16)outdata < 0)); ! 2254: { ! 2255: int Sm = (sint16)srcdata < 0; ! 2256: int Dm = (sint16)dstdata < 0; ! 2257: int Rm = (sint16)outdata < 0; ! 2258: XFLAG = CFLAG = (Sm && Dm) || (!Rm && (Dm || Sm)); ! 2259: } ! 2260: NFLAG = ((sint16)outdata) < 0; ! 2261: if (outdata) ZFLAG = 0; ! 2262: PC+= 2; ! 2263: } ! 2264: ! 2265: void cpu_op_1483a(t_ipc *ipc) /* ADDX */ { ! 2266: /* mask f1f8, bits d188, mnemonic 12, priv 0, endblk 0, imm_notzero 0, used 5 set -1, size 3, stype 4, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2267: int srcreg = (ipc->opcode >> 0) & 7; ! 2268: uint32 srcaddr = ADDRREG(srcreg)-=4; ! 2269: uint32 srcdata = fetchlong(srcaddr); ! 2270: int dstreg = (ipc->opcode >> 9) & 7; ! 2271: uint32 dstaddr = ADDRREG(dstreg)-=4; ! 2272: uint32 dstdata = fetchlong(dstaddr); ! 2273: uint32 outdata = (sint32)dstdata + (sint32)srcdata+ XFLAG; ! 2274: ! 2275: storelong(dstaddr, outdata); ! 2276: PC+= 2; ! 2277: } ! 2278: ! 2279: void cpu_op_1483b(t_ipc *ipc) /* ADDX */ { ! 2280: /* mask f1f8, bits d188, mnemonic 12, priv 0, endblk 0, imm_notzero 0, used 5 set -1, size 3, stype 4, dtype 4, sbitpos 0, dbitpos 9, immvalue 0 */ ! 2281: int srcreg = (ipc->opcode >> 0) & 7; ! 2282: uint32 srcaddr = ADDRREG(srcreg)-=4; ! 2283: uint32 srcdata = fetchlong(srcaddr); ! 2284: int dstreg = (ipc->opcode >> 9) & 7; ! 2285: uint32 dstaddr = ADDRREG(dstreg)-=4; ! 2286: uint32 dstdata = fetchlong(dstaddr); ! 2287: uint32 outdata = (sint32)dstdata + (sint32)srcdata+ XFLAG; ! 2288: ! 2289: storelong(dstaddr, outdata); ! 2290: ! 2291: VFLAG = (((sint32)srcdata < 0) == ((sint32)dstdata < 0)) && ! 2292: (((sint32)dstdata < 0) != ((sint32)outdata < 0)); ! 2293: { ! 2294: int Sm = (sint32)srcdata < 0; ! 2295: int Dm = (sint32)dstdata < 0; ! 2296: int Rm = (sint32)outdata < 0; ! 2297: XFLAG = CFLAG = (Sm && Dm) || (!Rm && (Dm || Sm)); ! 2298: } ! 2299: NFLAG = ((sint32)outdata) < 0; ! 2300: if (outdata) ZFLAG = 0; ! 2301: PC+= 2; ! 2302: } ! 2303:
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