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1.1.1.2 root 1: /*
1.1.1.3 root 2: * Hatari - blitter.c
1.1.1.2 root 3: *
4: * This file is distributed under the GNU Public License, version 2 or at
5: * your option any later version. Read the file gpl.txt for details.
6: *
1.1.1.3 root 7: * Blitter emulation.
8: * This file has originally been taken from STonX.
1.1.1.4 root 9: *
10: * Changes 2005-10-21:
11: * - Convert types and helper functions to SDL and Hatari ones
12: * - LineNum -> Control (line number is just low nibble of control register)
13: * - Add defines for register addresses
14: * - Fix bug with Smudge mode
15: * - Add documentation
1.1 root 16: *
17: * Original information text follows:
18: *
19: *
20: * This file is part of STonX, the Atari ST Emulator for Unix/X
21: * ============================================================
22: * STonX is free software and comes with NO WARRANTY - read the file
23: * COPYING for details
24: *
25: * Blitter Emulator,
26: * Martin Griffiths, 1995/96.
27: *
28: * Here lies the Atari Blitter Emulator - The 'Blitter' chip is found in
29: * the STE/MegaSTE and provides a very fast BitBlit in hardware.
30: *
1.1.1.3 root 31: * The hardware registers for this chip lie at addresses $ff8a00 - $ff8a3c.
1.1 root 32: */
1.1.1.5 ! root 33: const char Blitter_rcsid[] = "Hatari $Id: blitter.c,v 1.15 2007/01/16 18:42:59 thothy Exp $";
1.1 root 34:
35: #include <SDL_types.h>
36: #include <stdio.h>
37: #include <stdlib.h>
38:
1.1.1.2 root 39: #include "main.h"
1.1 root 40: #include "blitter.h"
41: #include "hatari-glue.h"
1.1.1.3 root 42: #include "ioMem.h"
43: #include "m68000.h"
1.1.1.2 root 44: #include "memorySnapShot.h"
1.1 root 45: #include "stMemory.h"
46:
1.1.1.4 root 47: #define DEBUG 0
1.1 root 48:
1.1.1.4 root 49: /* BLiTTER registers, counts and incs are signed, others unsigned */
50: #define REG_HT_RAM 0xff8a00 /* - 0xff8a1e */
1.1 root 51:
1.1.1.4 root 52: #define REG_SRC_X_INC 0xff8a20
53: #define REG_SRC_Y_INC 0xff8a22
54: #define REG_SRC_ADDR 0xff8a24
55:
56: #define REG_END_MASK1 0xff8a28
57: #define REG_END_MASK2 0xff8a2a
58: #define REG_END_MASK3 0xff8a2c
59:
60: #define REG_DST_X_INC 0xff8a2e
61: #define REG_DST_Y_INC 0xff8a30
62: #define REG_DST_ADDR 0xff8a32
63:
64: #define REG_X_COUNT 0xff8a36
65: #define REG_Y_COUNT 0xff8a38
66:
67: #define REG_BLIT_HOP 0xff8a3a /* halftone blit operation byte */
68: #define REG_BLIT_LOP 0xff8a3b /* logical blit operation byte */
69: #define REG_CONTROL 0xff8a3c
70: #define REG_SKEW 0xff8a3d
71:
72:
73: static Uint16 halftone_ram[16];
74: static Uint16 end_mask_1, end_mask_2, end_mask_3;
75: static Uint16 x_count, y_count;
76: static Uint8 hop, op, blit_control, skewreg;
77: static Uint8 NFSR, FXSR;
78: static Uint32 dest_addr_reg = 0;
79: static int halftone_curroffset, halftone_direction;
1.1 root 80: static int source_x_inc, source_y_inc, dest_x_inc, dest_y_inc;
81:
82:
1.1.1.4 root 83: #if DEBUG
84: static void show_params(Uint32 source_addr)
1.1 root 85: {
1.1.1.4 root 86: fprintf(stderr, "Source Address:%X\n", source_addr);
87: fprintf(stderr, " Dest Address:%X\n", dest_addr_reg);
88: fprintf(stderr, " X count:%X\n", x_count);
89: fprintf(stderr, " Y count:%X\n", y_count);
90: fprintf(stderr, " Source X inc:%X\n", source_x_inc);
91: fprintf(stderr, " Dest X inc:%X\n", dest_x_inc);
92: fprintf(stderr, " Source Y inc:%X\n", source_y_inc);
93: fprintf(stderr, " Dest Y inc:%X\n", dest_y_inc);
94: fprintf(stderr, "HOP:%2X OP:%X\n", hop, op);
95: fprintf(stderr, " source SKEW:%X\n", skewreg);
96: fprintf(stderr, " endmask 1:%X\n", end_mask_1);
97: fprintf(stderr, " endmask 2:%X\n", end_mask_2);
98: fprintf(stderr, " endmask 3:%X\n", end_mask_3);
99: fprintf(stderr, " blit control:%X\n", blit_control);
100: if (NFSR) fprintf(stderr, "NFSR is Set!\n");
101: if (FXSR) fprintf(stderr, "FXSR is Set!\n");
102: }
103:
104: static void show_halftones(void)
105: {
106: int i, j;
107: fprintf(stderr, "Halftone registers:\n");
108: for (i = 0; i < 2; i++) {
109: for (j = 0; j < 8; j++) {
110: fprintf(stderr,"%4X, ", halftone_ram[i*8+j]);
111: }
112: fprintf(stderr, "\n");
113: }
114: }
115: #endif
1.1.1.3 root 116:
117:
1.1.1.4 root 118: /* called only before halftone operations, for HOP modes 01 and 11 */
119: static void load_halftone_ram(Uint32 source_addr)
120: {
121: halftone_ram[0] = STMemory_ReadWord(REG_HT_RAM);
122: halftone_ram[1] = STMemory_ReadWord(REG_HT_RAM+2);
123: halftone_ram[2] = STMemory_ReadWord(REG_HT_RAM+4);
124: halftone_ram[3] = STMemory_ReadWord(REG_HT_RAM+6);
125: halftone_ram[4] = STMemory_ReadWord(REG_HT_RAM+8);
126: halftone_ram[5] = STMemory_ReadWord(REG_HT_RAM+10);
127: halftone_ram[6] = STMemory_ReadWord(REG_HT_RAM+12);
128: halftone_ram[7] = STMemory_ReadWord(REG_HT_RAM+14);
129: halftone_ram[8] = STMemory_ReadWord(REG_HT_RAM+16);
130: halftone_ram[9] = STMemory_ReadWord(REG_HT_RAM+18);
131: halftone_ram[10] = STMemory_ReadWord(REG_HT_RAM+20);
132: halftone_ram[11] = STMemory_ReadWord(REG_HT_RAM+22);
133: halftone_ram[12] = STMemory_ReadWord(REG_HT_RAM+24);
134: halftone_ram[13] = STMemory_ReadWord(REG_HT_RAM+26);
135: halftone_ram[14] = STMemory_ReadWord(REG_HT_RAM+28);
136: halftone_ram[15] = STMemory_ReadWord(REG_HT_RAM+30);
137:
138: if (!(blit_control & 0x20)) {
139: /* No smudge mode: Get halftone offset from control register */
140: halftone_curroffset = blit_control & 15;
141: }
142:
143: if (dest_y_inc >= 0) {
1.1.1.3 root 144: halftone_direction = 1;
1.1.1.4 root 145: } else {
1.1.1.3 root 146: halftone_direction = -1;
1.1.1.4 root 147: }
148: #if DEBUG
149: show_params(source_addr);
150: show_halftones();
151: #endif
1.1 root 152: }
153:
154:
155: #define HOP_OPS(_fn_name,_op,_do_source_shift,_get_source_data,_shifted_hopd_data, _do_halftone_inc) \
156: static void _fn_name (void) \
157: { \
1.1.1.4 root 158: Uint32 source_addr = STMemory_ReadLong(REG_SRC_ADDR); \
159: Uint32 dest_addr = dest_addr_reg; \
160: Uint32 source_buffer = 0; \
161: Uint8 skew = skewreg & 15; \
1.1.1.3 root 162: /*if(address_space_24)*/ \
1.1.1.4 root 163: { source_addr &= 0x0fffffe; dest_addr &= 0x0fffffe; } \
164: source_x_inc = (short) STMemory_ReadWord(REG_SRC_X_INC); \
165: source_y_inc = (short) STMemory_ReadWord(REG_SRC_Y_INC); \
166: dest_x_inc = (short) STMemory_ReadWord(REG_DST_X_INC); \
167: dest_y_inc = (short) STMemory_ReadWord(REG_DST_Y_INC); \
168: if (hop & 1) load_halftone_ram(source_addr); \
1.1.1.3 root 169: do \
170: { \
1.1.1.4 root 171: Uint16 x, dst_data, opd_data; \
1.1.1.3 root 172: if (FXSR) \
173: { \
174: _do_source_shift; \
175: _get_source_data; \
176: source_addr += source_x_inc; \
177: } \
178: _do_source_shift; \
179: _get_source_data; \
1.1.1.4 root 180: dst_data = STMemory_ReadWord(dest_addr); \
1.1.1.3 root 181: opd_data = _shifted_hopd_data; \
1.1.1.4 root 182: STMemory_WriteWord(dest_addr,(dst_data & ~end_mask_1) | (_op & end_mask_1)); \
1.1.1.3 root 183: for(x=0 ; x<x_count-2 ; x++) \
184: { \
185: source_addr += source_x_inc; \
186: dest_addr += dest_x_inc; \
187: _do_source_shift; \
188: _get_source_data; \
1.1.1.4 root 189: dst_data = STMemory_ReadWord(dest_addr); \
1.1.1.3 root 190: opd_data = _shifted_hopd_data; \
1.1.1.4 root 191: STMemory_WriteWord(dest_addr,(dst_data & ~end_mask_2) | (_op & end_mask_2)); \
1.1.1.3 root 192: } \
193: if (x_count >= 2) \
194: { \
195: dest_addr += dest_x_inc; \
196: _do_source_shift; \
197: if ( (!NFSR) || ((~(0xffff>>skew)) > end_mask_3) ) \
198: { \
199: source_addr += source_x_inc; \
200: _get_source_data; \
201: } \
1.1.1.4 root 202: dst_data = STMemory_ReadWord(dest_addr); \
1.1.1.3 root 203: opd_data = _shifted_hopd_data; \
1.1.1.4 root 204: STMemory_WriteWord(dest_addr,(((Uint16)dst_data) & ~end_mask_3) | (_op & end_mask_3)); \
1.1.1.3 root 205: } \
206: source_addr += source_y_inc; \
207: dest_addr += dest_y_inc; \
208: _do_halftone_inc; \
209: } while (--y_count > 0); \
1.1.1.4 root 210: STMemory_WriteLong(REG_SRC_ADDR, source_addr); \
1.1.1.3 root 211: dest_addr_reg = dest_addr; \
1.1 root 212: }
213:
214:
1.1.1.4 root 215: /* In smudge mode, the halftone offset is determined by the lowest 4 bits of
216: * the first source word, after it has been skewed */
217: #define HALFTONE_OFFSET ((blit_control & 0x20) ? \
218: ((STMemory_ReadWord(source_addr) >> skew) & 15) : halftone_curroffset)
219:
220:
1.1 root 221: HOP_OPS(_HOP_0_OP_00_N,(0), source_buffer >>=16,;, 0xffff, ;)
222: HOP_OPS(_HOP_0_OP_01_N,(opd_data & dst_data) ,source_buffer >>=16,; , 0xffff, ;)
223: HOP_OPS(_HOP_0_OP_02_N,(opd_data & ~dst_data) ,source_buffer >>=16,; , 0xffff,;)
224: HOP_OPS(_HOP_0_OP_03_N,(opd_data) ,source_buffer >>=16,; , 0xffff,;)
225: HOP_OPS(_HOP_0_OP_04_N,(~opd_data & dst_data) ,source_buffer >>=16,;, 0xffff,;)
226: HOP_OPS(_HOP_0_OP_05_N,(dst_data) ,source_buffer >>=16,;, 0xffff, ;)
227: HOP_OPS(_HOP_0_OP_06_N,(opd_data ^ dst_data) ,source_buffer >>=16,;, 0xffff, ;)
228: HOP_OPS(_HOP_0_OP_07_N,(opd_data | dst_data) ,source_buffer >>=16,; , 0xffff, ;)
229: HOP_OPS(_HOP_0_OP_08_N,(~opd_data & ~dst_data) ,source_buffer >>=16,;, 0xffff, ;)
230: HOP_OPS(_HOP_0_OP_09_N,(~opd_data ^ dst_data) ,source_buffer >>=16,;, 0xffff, ;)
231: HOP_OPS(_HOP_0_OP_10_N,(~dst_data) ,source_buffer >>=16,;, 0xffff, ;)
232: HOP_OPS(_HOP_0_OP_11_N,(opd_data | ~dst_data) ,source_buffer >>=16,;, 0xffff, ;)
233: HOP_OPS(_HOP_0_OP_12_N,(~opd_data) ,source_buffer >>=16,;, 0xffff, ;)
234: HOP_OPS(_HOP_0_OP_13_N,(~opd_data | dst_data) ,source_buffer >>=16,;, 0xffff, ;)
235: HOP_OPS(_HOP_0_OP_14_N,(~opd_data | ~dst_data) ,source_buffer >>=16,;, 0xffff, ;)
236: HOP_OPS(_HOP_0_OP_15_N,(0xffff) ,source_buffer >>=16,;, 0xffff, ;)
237:
1.1.1.4 root 238: HOP_OPS(_HOP_1_OP_00_N,(0) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
239: HOP_OPS(_HOP_1_OP_01_N,(opd_data & dst_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
240: HOP_OPS(_HOP_1_OP_02_N,(opd_data & ~dst_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
241: HOP_OPS(_HOP_1_OP_03_N,(opd_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
242: HOP_OPS(_HOP_1_OP_04_N,(~opd_data & dst_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
243: HOP_OPS(_HOP_1_OP_05_N,(dst_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
244: HOP_OPS(_HOP_1_OP_06_N,(opd_data ^ dst_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
245: HOP_OPS(_HOP_1_OP_07_N,(opd_data | dst_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
246: HOP_OPS(_HOP_1_OP_08_N,(~opd_data & ~dst_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
247: HOP_OPS(_HOP_1_OP_09_N,(~opd_data ^ dst_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
248: HOP_OPS(_HOP_1_OP_10_N,(~dst_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
249: HOP_OPS(_HOP_1_OP_11_N,(opd_data | ~dst_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
250: HOP_OPS(_HOP_1_OP_12_N,(~opd_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
251: HOP_OPS(_HOP_1_OP_13_N,(~opd_data | dst_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
252: HOP_OPS(_HOP_1_OP_14_N,(~opd_data | ~dst_data) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
253: HOP_OPS(_HOP_1_OP_15_N,(0xffff) ,source_buffer >>=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
254:
255: HOP_OPS(_HOP_2_OP_00_N,(0) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
256: HOP_OPS(_HOP_2_OP_01_N,(opd_data & dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
257: HOP_OPS(_HOP_2_OP_02_N,(opd_data & ~dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
258: HOP_OPS(_HOP_2_OP_03_N,(opd_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
259: HOP_OPS(_HOP_2_OP_04_N,(~opd_data & dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
260: HOP_OPS(_HOP_2_OP_05_N,(dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
261: HOP_OPS(_HOP_2_OP_06_N,(opd_data ^ dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
262: HOP_OPS(_HOP_2_OP_07_N,(opd_data | dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
263: HOP_OPS(_HOP_2_OP_08_N,(~opd_data & ~dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
264: HOP_OPS(_HOP_2_OP_09_N,(~opd_data ^ dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
265: HOP_OPS(_HOP_2_OP_10_N,(~dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
266: HOP_OPS(_HOP_2_OP_11_N,(opd_data | ~dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
267: HOP_OPS(_HOP_2_OP_12_N,(~opd_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
268: HOP_OPS(_HOP_2_OP_13_N,(~opd_data | dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
269: HOP_OPS(_HOP_2_OP_14_N,(~opd_data | ~dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
270: HOP_OPS(_HOP_2_OP_15_N,(0xffff) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew),;)
271:
272: HOP_OPS(_HOP_3_OP_00_N,(0) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
273: HOP_OPS(_HOP_3_OP_01_N,(opd_data & dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
274: HOP_OPS(_HOP_3_OP_02_N,(opd_data & ~dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
275: HOP_OPS(_HOP_3_OP_03_N,(opd_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
276: HOP_OPS(_HOP_3_OP_04_N,(~opd_data & dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
277: HOP_OPS(_HOP_3_OP_05_N,(dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
278: HOP_OPS(_HOP_3_OP_06_N,(opd_data ^ dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
279: HOP_OPS(_HOP_3_OP_07_N,(opd_data | dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
280: HOP_OPS(_HOP_3_OP_08_N,(~opd_data & ~dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
281: HOP_OPS(_HOP_3_OP_09_N,(~opd_data ^ dst_data) , source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
282: HOP_OPS(_HOP_3_OP_10_N,(~dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
283: HOP_OPS(_HOP_3_OP_11_N,(opd_data | ~dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
284: HOP_OPS(_HOP_3_OP_12_N,(~opd_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
285: HOP_OPS(_HOP_3_OP_13_N,(~opd_data | dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
286: HOP_OPS(_HOP_3_OP_14_N,(~opd_data | ~dst_data) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
287: HOP_OPS(_HOP_3_OP_15_N,(0xffff) ,source_buffer >>=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) << 16) ,(source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15)
1.1 root 288:
289:
290: HOP_OPS(_HOP_0_OP_00_P,(0) ,source_buffer <<=16,;, 0xffff,;)
291: HOP_OPS(_HOP_0_OP_01_P,(opd_data & dst_data) ,source_buffer <<=16,;, 0xffff,;)
292: HOP_OPS(_HOP_0_OP_02_P,(opd_data & ~dst_data) ,source_buffer <<=16,;, 0xffff,;)
293: HOP_OPS(_HOP_0_OP_03_P,(opd_data) ,source_buffer <<=16,;, 0xffff,;)
294: HOP_OPS(_HOP_0_OP_04_P,(~opd_data & dst_data) ,source_buffer <<=16,;, 0xffff,;)
295: HOP_OPS(_HOP_0_OP_05_P,(dst_data) ,source_buffer <<=16,;, 0xffff,;)
296: HOP_OPS(_HOP_0_OP_06_P,(opd_data ^ dst_data) ,source_buffer <<=16,;, 0xffff,;)
297: HOP_OPS(_HOP_0_OP_07_P,(opd_data | dst_data) ,source_buffer <<=16,;, 0xffff,;)
298: HOP_OPS(_HOP_0_OP_08_P,(~opd_data & ~dst_data) ,source_buffer <<=16,;, 0xffff,;)
299: HOP_OPS(_HOP_0_OP_09_P,(~opd_data ^ dst_data) ,source_buffer <<=16,;, 0xffff,;)
300: HOP_OPS(_HOP_0_OP_10_P,(~dst_data) ,source_buffer <<=16,;, 0xffff,;)
301: HOP_OPS(_HOP_0_OP_11_P,(opd_data | ~dst_data) ,source_buffer <<=16,;, 0xffff,;)
302: HOP_OPS(_HOP_0_OP_12_P,(~opd_data) ,source_buffer <<=16,;, 0xffff,;)
303: HOP_OPS(_HOP_0_OP_13_P,(~opd_data | dst_data) ,source_buffer <<=16,;, 0xffff,;)
304: HOP_OPS(_HOP_0_OP_14_P,(~opd_data | ~dst_data) ,source_buffer <<=16,;, 0xffff,;)
305: HOP_OPS(_HOP_0_OP_15_P,(0xffff) ,source_buffer <<=16,;, 0xffff,;)
306:
1.1.1.4 root 307: HOP_OPS(_HOP_1_OP_00_P,(0) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
308: HOP_OPS(_HOP_1_OP_01_P,(opd_data & dst_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
309: HOP_OPS(_HOP_1_OP_02_P,(opd_data & ~dst_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
310: HOP_OPS(_HOP_1_OP_03_P,(opd_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
311: HOP_OPS(_HOP_1_OP_04_P,(~opd_data & dst_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
312: HOP_OPS(_HOP_1_OP_05_P,(dst_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
313: HOP_OPS(_HOP_1_OP_06_P,(opd_data ^ dst_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
314: HOP_OPS(_HOP_1_OP_07_P,(opd_data | dst_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
315: HOP_OPS(_HOP_1_OP_08_P,(~opd_data & ~dst_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )\
316: HOP_OPS(_HOP_1_OP_09_P,(~opd_data ^ dst_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
317: HOP_OPS(_HOP_1_OP_10_P,(~dst_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
318: HOP_OPS(_HOP_1_OP_11_P,(opd_data | ~dst_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
319: HOP_OPS(_HOP_1_OP_12_P,(~opd_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
320: HOP_OPS(_HOP_1_OP_13_P,(~opd_data | dst_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
321: HOP_OPS(_HOP_1_OP_14_P,(~opd_data | ~dst_data) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
322: HOP_OPS(_HOP_1_OP_15_P,(0xffff) ,source_buffer <<=16,;,halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
323:
324: HOP_OPS(_HOP_2_OP_00_P,(0) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
325: HOP_OPS(_HOP_2_OP_01_P,(opd_data & dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
326: HOP_OPS(_HOP_2_OP_02_P,(opd_data & ~dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
327: HOP_OPS(_HOP_2_OP_03_P,(opd_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
328: HOP_OPS(_HOP_2_OP_04_P,(~opd_data & dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
329: HOP_OPS(_HOP_2_OP_05_P,(dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
330: HOP_OPS(_HOP_2_OP_06_P,(opd_data ^ dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
331: HOP_OPS(_HOP_2_OP_07_P,(opd_data | dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
332: HOP_OPS(_HOP_2_OP_08_P,(~opd_data & ~dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
333: HOP_OPS(_HOP_2_OP_09_P,(~opd_data ^ dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
334: HOP_OPS(_HOP_2_OP_10_P,(~dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
335: HOP_OPS(_HOP_2_OP_11_P,(opd_data | ~dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
336:
337: HOP_OPS(_HOP_2_OP_12_P,(~opd_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
338: HOP_OPS(_HOP_2_OP_13_P,(~opd_data | dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
339: HOP_OPS(_HOP_2_OP_14_P,(~opd_data | ~dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
340: HOP_OPS(_HOP_2_OP_15_P,(0xffff) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ) , (source_buffer >> skew),;)
341:
342: HOP_OPS(_HOP_3_OP_00_P,(0) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
343: HOP_OPS(_HOP_3_OP_01_P,(opd_data & dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
344: HOP_OPS(_HOP_3_OP_02_P,(opd_data & ~dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
345: HOP_OPS(_HOP_3_OP_03_P,(opd_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
346: HOP_OPS(_HOP_3_OP_04_P,(~opd_data & dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
347: HOP_OPS(_HOP_3_OP_05_P,(dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
348: HOP_OPS(_HOP_3_OP_06_P,(opd_data ^ dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
349: HOP_OPS(_HOP_3_OP_07_P,(opd_data | dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
350: HOP_OPS(_HOP_3_OP_08_P,(~opd_data & ~dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
351: HOP_OPS(_HOP_3_OP_09_P,(~opd_data ^ dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
352: HOP_OPS(_HOP_3_OP_10_P,(~dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
353: HOP_OPS(_HOP_3_OP_11_P,(opd_data | ~dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
354: HOP_OPS(_HOP_3_OP_12_P,(~opd_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
355: HOP_OPS(_HOP_3_OP_13_P,(~opd_data | dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
356: HOP_OPS(_HOP_3_OP_14_P,(~opd_data | ~dst_data) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
357: HOP_OPS(_HOP_3_OP_15_P,(0xffff) ,source_buffer <<=16,source_buffer |= ((Uint32) STMemory_ReadWord(source_addr) ), (source_buffer >> skew) & halftone_ram[HALFTONE_OFFSET],halftone_curroffset=(halftone_curroffset+halftone_direction) & 15 )
1.1 root 358:
1.1.1.4 root 359: static void (* const do_hop_op_N[4][16])(void) =
1.1 root 360: {
361: { _HOP_0_OP_00_N, _HOP_0_OP_01_N, _HOP_0_OP_02_N, _HOP_0_OP_03_N, _HOP_0_OP_04_N, _HOP_0_OP_05_N, _HOP_0_OP_06_N, _HOP_0_OP_07_N, _HOP_0_OP_08_N, _HOP_0_OP_09_N, _HOP_0_OP_10_N, _HOP_0_OP_11_N, _HOP_0_OP_12_N, _HOP_0_OP_13_N, _HOP_0_OP_14_N, _HOP_0_OP_15_N,},
362: { _HOP_1_OP_00_N, _HOP_1_OP_01_N, _HOP_1_OP_02_N, _HOP_1_OP_03_N, _HOP_1_OP_04_N, _HOP_1_OP_05_N, _HOP_1_OP_06_N, _HOP_1_OP_07_N, _HOP_1_OP_08_N, _HOP_1_OP_09_N, _HOP_1_OP_10_N, _HOP_1_OP_11_N, _HOP_1_OP_12_N, _HOP_1_OP_13_N, _HOP_1_OP_14_N, _HOP_1_OP_15_N,},
363: { _HOP_2_OP_00_N, _HOP_2_OP_01_N, _HOP_2_OP_02_N, _HOP_2_OP_03_N, _HOP_2_OP_04_N, _HOP_2_OP_05_N, _HOP_2_OP_06_N, _HOP_2_OP_07_N, _HOP_2_OP_08_N, _HOP_2_OP_09_N, _HOP_2_OP_10_N, _HOP_2_OP_11_N, _HOP_2_OP_12_N, _HOP_2_OP_13_N, _HOP_2_OP_14_N, _HOP_2_OP_15_N,},
364: { _HOP_3_OP_00_N, _HOP_3_OP_01_N, _HOP_3_OP_02_N, _HOP_3_OP_03_N, _HOP_3_OP_04_N, _HOP_3_OP_05_N, _HOP_3_OP_06_N, _HOP_3_OP_07_N, _HOP_3_OP_08_N, _HOP_3_OP_09_N, _HOP_3_OP_10_N, _HOP_3_OP_11_N, _HOP_3_OP_12_N, _HOP_3_OP_13_N, _HOP_3_OP_14_N, _HOP_3_OP_15_N,}
365: };
366:
1.1.1.4 root 367: static void (* const do_hop_op_P[4][16])(void) =
1.1 root 368: {
369: { _HOP_0_OP_00_P, _HOP_0_OP_01_P, _HOP_0_OP_02_P, _HOP_0_OP_03_P, _HOP_0_OP_04_P, _HOP_0_OP_05_P, _HOP_0_OP_06_P, _HOP_0_OP_07_P, _HOP_0_OP_08_P, _HOP_0_OP_09_P, _HOP_0_OP_10_P, _HOP_0_OP_11_P, _HOP_0_OP_12_P, _HOP_0_OP_13_P, _HOP_0_OP_14_P, _HOP_0_OP_15_P,},
370: { _HOP_1_OP_00_P, _HOP_1_OP_01_P, _HOP_1_OP_02_P, _HOP_1_OP_03_P, _HOP_1_OP_04_P, _HOP_1_OP_05_P, _HOP_1_OP_06_P, _HOP_1_OP_07_P, _HOP_1_OP_08_P, _HOP_1_OP_09_P, _HOP_1_OP_10_P, _HOP_1_OP_11_P, _HOP_1_OP_12_P, _HOP_1_OP_13_P, _HOP_1_OP_14_P, _HOP_1_OP_15_P,},
371: { _HOP_2_OP_00_P, _HOP_2_OP_01_P, _HOP_2_OP_02_P, _HOP_2_OP_03_P, _HOP_2_OP_04_P, _HOP_2_OP_05_P, _HOP_2_OP_06_P, _HOP_2_OP_07_P, _HOP_2_OP_08_P, _HOP_2_OP_09_P, _HOP_2_OP_10_P, _HOP_2_OP_11_P, _HOP_2_OP_12_P, _HOP_2_OP_13_P, _HOP_2_OP_14_P, _HOP_2_OP_15_P,},
372: { _HOP_3_OP_00_P, _HOP_3_OP_01_P, _HOP_3_OP_02_P, _HOP_3_OP_03_P, _HOP_3_OP_04_P, _HOP_3_OP_05_P, _HOP_3_OP_06_P, _HOP_3_OP_07_P, _HOP_3_OP_08_P, _HOP_3_OP_09_P, _HOP_3_OP_10_P, _HOP_3_OP_11_P, _HOP_3_OP_12_P, _HOP_3_OP_13_P, _HOP_3_OP_14_P, _HOP_3_OP_15_P,}
373: };
374:
375:
376:
1.1.1.3 root 377: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 378: /**
! 379: * Do the blit.
! 380: */
1.1.1.4 root 381: static void Do_Blit(void)
382: {
383: if (((short)STMemory_ReadWord(REG_SRC_X_INC)) < 0)
384: do_hop_op_N[hop][op]();
385: else
386: do_hop_op_P[hop][op]();
387: }
388:
389: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 390: /**
! 391: * Read blitter endmask 1.
! 392: */
1.1.1.3 root 393: void Blitter_Endmask1_ReadWord(void)
1.1 root 394: {
1.1.1.4 root 395: IoMem_WriteWord(REG_END_MASK1, end_mask_1);
1.1 root 396: }
397:
1.1.1.3 root 398: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 399: /**
! 400: * Read blitter endmask 2.
! 401: */
1.1.1.3 root 402: void Blitter_Endmask2_ReadWord(void)
1.1 root 403: {
1.1.1.4 root 404: IoMem_WriteWord(REG_END_MASK2, end_mask_2);
1.1 root 405: }
406:
1.1.1.3 root 407: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 408: /**
! 409: * Read blitter endmask 3.
! 410: */
1.1.1.3 root 411: void Blitter_Endmask3_ReadWord(void)
1.1 root 412: {
1.1.1.4 root 413: IoMem_WriteWord(REG_END_MASK3, end_mask_3);
1.1 root 414: }
415:
1.1.1.3 root 416: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 417: /**
! 418: * Read blitter destination address.
! 419: */
1.1.1.3 root 420: void Blitter_DestAddr_ReadLong(void)
1.1 root 421: {
1.1.1.4 root 422: IoMem_WriteLong(REG_DST_ADDR, dest_addr_reg);
1.1 root 423: }
424:
1.1.1.3 root 425: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 426: /**
! 427: * Read blitter words-per-line register.
! 428: */
1.1.1.3 root 429: void Blitter_WordsPerLine_ReadWord(void)
1.1 root 430: {
1.1.1.4 root 431: IoMem_WriteWord(REG_X_COUNT, x_count);
1.1 root 432: }
433:
1.1.1.3 root 434: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 435: /**
! 436: * Read blitter lines-per-bitblock register.
! 437: */
1.1.1.3 root 438: void Blitter_LinesPerBitblock_ReadWord(void)
1.1 root 439: {
1.1.1.4 root 440: IoMem_WriteWord(REG_Y_COUNT, y_count);
1.1 root 441: }
442:
1.1.1.3 root 443: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 444: /**
! 445: * Read blitter halftone operation register.
! 446: */
1.1.1.3 root 447: void Blitter_HalftoneOp_ReadByte(void)
1.1 root 448: {
1.1.1.4 root 449: IoMem_WriteByte(REG_BLIT_HOP, hop);
1.1 root 450: }
451:
1.1.1.3 root 452: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 453: /**
! 454: * Read blitter logical operation register.
! 455: */
1.1.1.3 root 456: void Blitter_LogOp_ReadByte(void)
1.1 root 457: {
1.1.1.4 root 458: IoMem_WriteByte(REG_BLIT_LOP, op);
1.1 root 459: }
460:
1.1.1.3 root 461: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 462: /**
! 463: * Read blitter control register.
! 464: */
1.1.1.4 root 465: void Blitter_Control_ReadByte(void)
1.1 root 466: {
1.1.1.4 root 467: /* we don't implement Blit mode so this can never be
468: * busy when application gets the return value
469: * %11101111
470: * busy, hog/blit, smudge, n/a, 4bits for line number
471: */
472: //IoMem_WriteByte(REG_CONTROL, (blit_control & 0x6f));
473: IoMem_WriteByte(REG_CONTROL, (blit_control & 0x3f));
1.1 root 474: }
475:
1.1.1.3 root 476: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 477: /**
! 478: * Read blitter skew register.
! 479: */
1.1.1.3 root 480: void Blitter_Skew_ReadByte(void)
1.1 root 481: {
1.1.1.4 root 482: IoMem_WriteByte(REG_SKEW, skewreg);
1.1 root 483: }
484:
485:
1.1.1.3 root 486: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 487: /**
! 488: * Write to blitter endmask 1.
! 489: */
1.1.1.3 root 490: void Blitter_Endmask1_WriteWord(void)
1.1 root 491: {
1.1.1.4 root 492: end_mask_1 = IoMem_ReadWord(REG_END_MASK1);
1.1 root 493: }
494:
1.1.1.3 root 495: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 496: /**
! 497: * Write to blitter endmask 2.
! 498: */
1.1.1.3 root 499: void Blitter_Endmask2_WriteWord(void)
1.1 root 500: {
1.1.1.4 root 501: end_mask_2 = IoMem_ReadWord(REG_END_MASK2);
1.1 root 502: }
503:
1.1.1.3 root 504: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 505: /**
! 506: * Write to blitter endmask 3.
! 507: */
1.1.1.3 root 508: void Blitter_Endmask3_WriteWord(void)
1.1 root 509: {
1.1.1.4 root 510: end_mask_3 = IoMem_ReadWord(REG_END_MASK3);
1.1 root 511: }
512:
1.1.1.3 root 513: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 514: /**
! 515: * Write to blitter destination address register.
! 516: */
1.1.1.3 root 517: void Blitter_DestAddr_WriteLong(void)
518: {
1.1.1.4 root 519: dest_addr_reg = IoMem_ReadLong(REG_DST_ADDR) & 0x0fffffe;
1.1 root 520: }
521:
1.1.1.3 root 522: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 523: /**
! 524: * Write to blitter words-per-line register.
! 525: */
1.1.1.3 root 526: void Blitter_WordsPerLine_WriteWord(void)
1.1 root 527: {
1.1.1.4 root 528: x_count = IoMem_ReadWord(REG_X_COUNT);
1.1 root 529: }
530:
1.1.1.3 root 531: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 532: /**
! 533: * Write to blitter words-per-bitblock register.
! 534: */
1.1.1.3 root 535: void Blitter_LinesPerBitblock_WriteWord(void)
1.1 root 536: {
1.1.1.4 root 537: y_count = IoMem_ReadWord(REG_Y_COUNT);
1.1 root 538: }
539:
1.1.1.3 root 540: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 541: /**
! 542: * Write to blitter halftone operation register.
! 543: */
1.1.1.3 root 544: void Blitter_HalftoneOp_WriteByte(void)
1.1 root 545: {
1.1.1.4 root 546: /* h/ware reg masks out the top 6 bits! */
547: hop = IoMem_ReadByte(REG_BLIT_HOP) & 3;
1.1 root 548: }
549:
1.1.1.3 root 550: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 551: /**
! 552: * Write to blitter logical operation register.
! 553: */
1.1.1.3 root 554: void Blitter_LogOp_WriteByte(void)
1.1.1.4 root 555: {
556: /* h/ware reg masks out the top 4 bits! */
557: op = IoMem_ReadByte(REG_BLIT_LOP) & 15;
1.1 root 558: }
559:
1.1.1.3 root 560: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 561: /**
! 562: * Write to blitter control register.
! 563: */
1.1.1.4 root 564: void Blitter_Control_WriteByte(void)
565: {
566: /* Control register bits:
567: * 0x80: busy bit
568: * - Turn on Blitter activity and stay "1" until copy finished
569: * 0x40: Blit-mode bit
570: * - 0: Blit mode, CPU and Blitter get 64 clockcycles in turns
571: * - 1: HOG Mode, Blitter reserves and hogs the bus for as long
572: * as the copy takes, CPU and DMA get no Bus access
573: * 0x20: Smudge mode
574: * - Which line of the halftone pattern to start with is
575: * read from the first source word when the copy starts
576: * 0x10: not used
577: * 0x0f
578: *
579: * The lowest 4 bits contain the Halftone pattern line number
580: */
581: blit_control = IoMem_ReadByte(REG_CONTROL) & 0xef;
582:
583: /* Lines to blit and busy bit set? */
584: if((y_count !=0) && (blit_control & 0x80))
1.1.1.3 root 585: {
1.1.1.4 root 586: /* Needed if a program executes for example
587: * move.W #xxxx,$ff8a3c
588: */
589: Blitter_Skew_WriteByte();
590:
591: /* TODO:
592: * - Emulate the shared bus mode when HOG flag is cleared
593: * - Add proper blitter timings
594: */
1.1.1.3 root 595: M68000_AddCycles(y_count);
596:
597: Do_Blit();
598: }
1.1 root 599: }
600:
1.1.1.3 root 601: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 602: /**
! 603: * Write to blitter skew register.
! 604: */
1.1.1.3 root 605: void Blitter_Skew_WriteByte(void)
606: {
1.1.1.4 root 607: Uint8 v = IoMem_ReadByte(REG_SKEW);
1.1.1.3 root 608: NFSR = (v & 0x40) != 0;
609: FXSR = (v & 0x80) != 0;
1.1.1.4 root 610: skewreg = v & 0xcf; /* h/ware reg mask %11001111 !*/
1.1 root 611: }
1.1.1.2 root 612:
613:
614: /*-----------------------------------------------------------------------*/
1.1.1.5 ! root 615: /**
! 616: * Save/Restore snapshot of Blitter variables.
! 617: */
1.1.1.2 root 618: void Blitter_MemorySnapShot_Capture(BOOL bSave)
619: {
1.1.1.3 root 620: /* Save/Restore details */
621: MemorySnapShot_Store(halftone_ram, sizeof(halftone_ram));
622: MemorySnapShot_Store(&end_mask_1, sizeof(end_mask_1));
623: MemorySnapShot_Store(&end_mask_2, sizeof(end_mask_2));
624: MemorySnapShot_Store(&end_mask_3, sizeof(end_mask_3));
625: MemorySnapShot_Store(&NFSR, sizeof(NFSR));
626: MemorySnapShot_Store(&FXSR, sizeof(FXSR));
627: MemorySnapShot_Store(&x_count, sizeof(y_count));
628: MemorySnapShot_Store(&hop, sizeof(hop));
629: MemorySnapShot_Store(&op, sizeof(op));
1.1.1.4 root 630: MemorySnapShot_Store(&blit_control, sizeof(blit_control));
1.1.1.3 root 631: MemorySnapShot_Store(&skewreg, sizeof(skewreg));
632: MemorySnapShot_Store(&dest_addr_reg, sizeof(dest_addr_reg));
633: MemorySnapShot_Store(&halftone_curroffset, sizeof(halftone_curroffset));
634: MemorySnapShot_Store(&halftone_direction, sizeof(halftone_direction));
635: MemorySnapShot_Store(&source_x_inc, sizeof(source_x_inc));
636: MemorySnapShot_Store(&source_y_inc, sizeof(source_y_inc));
637: MemorySnapShot_Store(&dest_x_inc, sizeof(dest_x_inc));
638: MemorySnapShot_Store(&dest_y_inc, sizeof(dest_y_inc));
1.1.1.2 root 639: }
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