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1.1 root 1: /*
2: Hatari - clocks_timings.c
3:
1.1.1.2 ! root 4: This file is distributed under the GNU General Public License, version 2
! 5: or at your option any later version. Read the file gpl.txt for details.
1.1 root 6:
7: Clocks Timings for the hardware components in each supported machine type,
8: as well as functions taking into account the exact length of a VBL to
9: precisely emulate video/audio parts (number of VBL per sec, number of
10: audio samples per VBL, ...)
11:
12: The video freq is not exactly 50 or 60 Hz because the number of cpu cycles
13: per second is not a multiple of the number of cpu cycles per VBL.
14: This can cause synchronisation errors between audio and video effects
15: when both components use different clocks (eg in STE where audio DMA clock
16: is not the same as the cpu clock).
17:
18: To get the best results, it's recommanded to set RoundVBLPerSec=false.
19:
20: Note that if you do so, the number of VBL won't be exactly 50 or 60 per sec
21: but 50.05 or 60.04 ; if this does not work with your display, set RoundVBLPerSec=true
22: to get an integer number of VBL per sec (but this should not be needed).
23:
24:
25:
26: ST :
27: MCLK = 32 MHz
28: SHIFTER IN = 32 MHz OUT = 16 MHz
29: MMU IN = 16 MHz OUT = 8 MHz, 4 MHz
30: GLUE IN = 8 MHz OUT = 2 MHz, 500 kHz
31: BUS = 8 MHz
32:
33: CPU 68000 IN = 8 MHz
34: DMA IN = 8 MHz
35: MFP 68901 IN = 4 MHz, 2.4576 MHz (external clock)
36: FDC WD1772 IN = 8 MHz
37: BLITTER IN = 8 MHz
38: YM2149 IN = 2 MHz
39: ACIA MC6850 IN = 500 kHz
40: IKBD HD6301 IN = 1 MHZ (local clock)
41:
42:
43: STE :
44: MCLK = 32 MHz
45: EXT OSC = 8 MHZ OUT = 8 MHz (SCLK), 2 MHz (CLK2)
46: GST SHIFTER IN = 32 MHz, 8 MHz (external clock SCLK) OUT = 16 MHz, 8 MHz (FCLK=SCLK)
47: GST MCU IN = 16 MHz OUT = 8 MHz (CLK8), 4 MHz (CLK4), 500 kHz (KHZ500)
48: BUS = 8 MHz
49:
50: CPU 68000 IN = 8 MHz (CLK8)
51: DMA IN = 8 MHz (CLK8)
52: DMA AUDIO IN = 8 MHz (SCLK)
53: MFP 68901 IN = 4 MHz (CLK4), 2.4576 MHz (external clock)
54: FDC WD1772 IN = 8 MHz (SCLK)
55: BLITTER IN = 8 MHz (CLK8)
56: YM2149 IN = 2 MHz (CLK2)
57: ACIA MC6850 IN = 500 kHz (KHZ500)
58: IKBD HD6301 IN = 1 MHZ (local clock)
59:
60:
61: MEGA STE :
62: MCLK = 32 MHz
63: SCLK = 8 MHz
64: GST SHIFTER IN = 32 MHz, 8 MHz (external clock SCLK) OUT = 16 MHz (CLK16), 8 MHz (FCLK=SCLK)
65: GST MCU IN = 16 MHz (CLK16) OUT = 8 MHz (CLK8), 4 MHz (CLK4), 500 kHz (KHZ500)
66: BUS = 8 MHz
67:
68: CPU 68000 IN = 16 MHz (CLK16)
69: FPU 68881 IN = 16 MHz (CLK16)
70: DMA IN = 8 MHz (CLK8)
71: DMA AUDIO IN = 8 MHz (SCLK)
72: MFP 68901 IN = 4 MHz (CLK4), 2.4576 MHz (external clock)
73: FDC WD1772 IN = 8 MHz (SCLK)
74: BLITTER IN = 8 MHz (CLK8)
75: YM2149 IN = 2 MHz (CLK2 = SCLK / 4)
76: ACIA MC6850 IN = 500 kHz (KHZ500)
77: IKBD HD6301 IN = 1 MHZ (local clock)
78:
79:
80: TT :
81: MCLK = 32 MHz (CLK32)
82: TT VIDEO IN = 32 MHz (CLK32) OUT = 16 MHz (CLK16), 4 MHz (CLK4), 2 MHz (CLK2)
83: GST MCU IN = 16 MHz (CLK16A), 2 MHz (CLK2) OUT = 8 MHz (CLK8), 8 MHz (FCCLK), 1 MHz (CLKE), 500 kHz (CLKX5)
84: BUS = 16 MHz
85:
86: CPU 68030 IN = 32 MHz (CLK32)
87: FPU 68882 IN = 32 MHz (CLK32)
88: DMA IN = 8 MHz (CLK8)
89: SND SHIFTER IN = 16 MHz (CLK16F), 2 MHz (CLK2) OUT = ? MHz (FCLK)
90: MFP 68901 IN = 4 MHz (CLK4), 2.4576 MHz (external clock) NOTE : TT has 2 MFPs 68901
91: FDC WD1772 IN = 8 MHz (FCCLK)
92: BLITTER NOT AVAILABLE
93: YM2149 IN = 2 MHz (CLK2)
94: ACIA MC6850 IN = 500 kHz (CLKX5)
95: IKBD HD6301 IN = 1 MHZ (local clock)
96:
97:
98: FALCON :
99: MCLK = 32 MHz (CLK32)
100: VIDEL IN = 32 MHz (VID32MHZ), 25 MHz (25K)
101: COMBEL IN = 32 MHz (CLK32) OUT = 4 MHz (CLK4), 500 kHz (KHZ500)
102: BUS = 16 MHz
103:
104: CPU 68030 IN = 16 MHz (CPUCLKB)
105: FPU 68882 IN = 16 MHz (CPUCLKA)
106: DMA IN = 8 MHz (CLK8)
107: CODEC IN = 25 MHz (25K)
108: MFP 68901 IN = 4 MHz (CLK4), 2.4576 MHz (external clock)
109: FDC AJAX IN = 16 MHz (FCCLK)
110: BLITTER IN = 16 MHz
111: YM3439 IN = 2 MHz (CLK2)
112: ACIA MC6850 IN = 500 kHz (KHZ500)
113: IKBD HD6301 IN = 1 MHZ (local clock)
114:
115: DSP 56001 IN = 32 MHz (DSP_32M)
116:
117: */
118:
119:
120: const char ClocksTimings_fileid[] = "Hatari clocks_timings.c : " __DATE__ " " __TIME__;
121:
122: #include <SDL.h>
123: #include <SDL_endian.h>
124:
125: #include "main.h"
126: #include "configuration.h"
127: #include "log.h"
128: #include "clocks_timings.h"
129:
130:
131:
132: /* The possible master frequencies used in the different machines */
133: /* depending on PAL/NTSC version. */
134:
135: #define ATARI_STF_PAL_MCLK 32084988 /* CPU_Freq = 8.021247 MHz */
136: #define ATARI_STF_NTSC_MCLK 32042400 /* CPU_Freq = 8.010600 MHz */
137: #define ATARI_STF_CYCLES_PER_VBL_PAL 160256 /* 512 cycles * 313 lines */
138: #define ATARI_STF_CYCLES_PER_VBL_NTSC 133604 /* 508 cycles * 263 lines */
139: #define ATARI_STF_CYCLES_PER_VBL_HI 112224 /* 224 cycles * 501 lines */
140:
141: #define ATARI_STE_PAL_MCLK 32084988 /* CPU_Freq = 8.021247 MHz */
142: #define ATARI_STE_NTSC_MCLK 32215905 /* CPU_Freq = 8.05397625 MHz */
143: #define ATARI_STE_EXT_OSC 8010613 /* OSC U303 */
144: #define ATARI_STE_CYCLES_PER_VBL_PAL 160256 /* 512 cycles * 313 lines */
145: #define ATARI_STE_CYCLES_PER_VBL_NTSC 133604 /* 508 cycles * 263 lines */
146: #define ATARI_STE_CYCLES_PER_VBL_HI 112224 /* 224 cycles * 501 lines */
147:
148: #define ATARI_MEGA_STE_PAL_MCLK 32084988 /* CPU_Freq = 16.042494 MHz */
149: #define ATARI_MEGA_STE_NTSC_MCLK 32215905 /* CPU_Freq = 16.1079525 MHz */
150: #define ATARI_MEGA_STE_EXT_OSC 16021226 /* OSC U408 */
151:
152: #define ATARI_TT_PAL_MCLK 32084988 /* CPU_Freq = 32.084988 MHz */
153: #define ATARI_TT_NTSC_MCLK 32215905 /* CPU_Freq = 32.215905 MHz */
154:
155: #define ATARI_FALCON_PAL_MCLK 32084988 /* CPU_Freq = 16.042494 MHz */
156: #define ATARI_FALCON_NTSC_MCLK 32215905 /* CPU_Freq = 16.1079525 MHz */
157: #define ATARI_FALCON_25M_CLK 25175000
158:
159: #define ATARI_MFP_XTAL 2457600 /* external clock for the MFP */
160: #define ATARI_IKBD_CLK 1000000 /* clock of the HD6301 ikbd cpu */
161:
162:
163:
164: CLOCKS_STRUCT MachineClocks;
165:
166:
167: bool RoundVBLPerSec = false; /* if false, don't round number of VBL to 50/60 Hz */
168: /* but compute the exact value based on cpu/video clocks */
169:
170:
171:
172:
173: /*--------------------------------------------------------------------------*/
174: /**
175: * Initialize all the clocks informations related to a specific machine type.
176: * We consider the machine is running with PAL clocks.
177: */
178:
179: void ClocksTimings_InitMachine ( MACHINETYPE MachineType )
180: {
181: memset ( (void *)&MachineClocks , 0 , sizeof ( MachineClocks ) );
182:
183: if ( MachineType == MACHINE_ST )
184: {
185: int CLK16, CLK8, CLK4, CLK2, CLK500;
186:
187: MachineClocks.MCLK_Freq = ATARI_STF_PAL_MCLK; /* 32.084988 MHz */
188:
189: MachineClocks.SHIFTER_Freq = MachineClocks.MCLK_Freq; /* 32 MHz */
190: CLK16 = MachineClocks.SHIFTER_Freq / 2;
191:
192: MachineClocks.MMU_Freq = CLK16; /* 16 MHz */
193: CLK8 = MachineClocks.MMU_Freq / 2;
194: CLK4 = MachineClocks.MMU_Freq / 4;
195:
196: MachineClocks.GLUE_Freq = CLK8; /* 8 MHz */
197: CLK2 = MachineClocks.GLUE_Freq / 4;
198: CLK500 = MachineClocks.GLUE_Freq / 16;
199:
200: MachineClocks.BUS_Freq = CLK8; /* 8 MHz */
201:
202: MachineClocks.CPU_Freq = CLK8; /* 8 MHz */
203: MachineClocks.DMA_Freq = CLK8; /* 8 MHz */
204: MachineClocks.MFP_Freq = CLK4; /* 4 MHz */
205: MachineClocks.MFP_Timer_Freq = ATARI_MFP_XTAL; /* 2.4576 MHz (XTAL)*/
206: MachineClocks.FDC_Freq = CLK8; /* 8 MHz */
207: MachineClocks.BLITTER_Freq = CLK8; /* 8 MHz */
208: MachineClocks.YM_Freq = CLK2; /* 2 MHz */;
209: MachineClocks.ACIA_Freq = CLK500; /* 500 kHz */
210: MachineClocks.IKBD_Freq = ATARI_IKBD_CLK; /* 1 MHz */
211: }
212:
213: else if ( MachineType == MACHINE_STE )
214: {
215: int SCLK, CLK16, CLK8, CLK4, CLK2, KHZ500;
216: //int FCLK; /* not used (audio filters) */
217:
218: MachineClocks.MCLK_Freq = ATARI_STE_PAL_MCLK; /* 32.084988 MHz */
219: SCLK = ATARI_STE_EXT_OSC; /* 8.010613 MHz (SCLK) */
220: CLK2 = SCLK / 4;
221:
222: MachineClocks.SHIFTER_Freq = MachineClocks.MCLK_Freq; /* 32 MHz */
223: CLK16 = MachineClocks.SHIFTER_Freq / 2;
224: //FCLK = SCLK;
225:
226: MachineClocks.MCU_Freq = CLK16; /* 16 MHz */
227: CLK8 = MachineClocks.MCU_Freq / 2;
228: CLK4 = MachineClocks.MCU_Freq / 4;
229: KHZ500 = MachineClocks.MCU_Freq / 32;
230:
231: MachineClocks.BUS_Freq = CLK8; /* 8 MHz (CLK8) */
232:
233: MachineClocks.CPU_Freq = CLK8; /* 8 MHz (CLK8) */
234: MachineClocks.DMA_Freq = CLK8; /* 8 MHz (CLK8) */
235: MachineClocks.DMA_Audio_Freq = SCLK; /* 8 MHz (SCLK) */
236: MachineClocks.MFP_Freq = CLK4; /* 4 MHz (CLK4) */
237: MachineClocks.MFP_Timer_Freq = ATARI_MFP_XTAL; /* 2.4576 MHz (XTAL)*/
238: MachineClocks.FDC_Freq = SCLK; /* 8 MHz (SCLK) */
239: MachineClocks.BLITTER_Freq = CLK8; /* 8 MHz (CLK8) */
240: MachineClocks.YM_Freq = CLK2; /* 2 MHz (CLK2) */
241: MachineClocks.ACIA_Freq = KHZ500; /* 500 kHz (KHZ500) */
242: MachineClocks.IKBD_Freq = ATARI_IKBD_CLK; /* 1 MHz */
243: }
244:
245: else if ( MachineType == MACHINE_MEGA_STE )
246: {
247: int SCLK, CLK16, CLK8, CLK4, CLK2, KHZ500;
248: //int FCLK; /* not used (audio filters) */
249:
250: MachineClocks.MCLK_Freq = ATARI_MEGA_STE_PAL_MCLK; /* 32.084988 MHz */
251: SCLK = ATARI_MEGA_STE_EXT_OSC / 2; /* 16.021226 MHz / 2 = 8.010613 MHz */
252: CLK2 = SCLK / 4;
253:
254: MachineClocks.SHIFTER_Freq = MachineClocks.MCLK_Freq; /* 32 MHz */
255: CLK16 = MachineClocks.SHIFTER_Freq / 2;
256: //FCLK = SCLK;
257:
258: MachineClocks.MCU_Freq = CLK16; /* 16 MHz (CLK16) */
259: CLK8 = MachineClocks.MCU_Freq / 2;
260: CLK4 = MachineClocks.MCU_Freq / 4;
261: KHZ500 = MachineClocks.MCU_Freq / 32;
262:
263: MachineClocks.BUS_Freq = CLK8; /* 8 MHz (CLK8) */
264:
265: MachineClocks.CPU_Freq = CLK16; /* 16 MHz (CLK16) */
266: MachineClocks.FPU_Freq = CLK16; /* 16 MHz (CLK16) */
267: MachineClocks.DMA_Freq = CLK8; /* 8 MHz (CLK8) */
268: MachineClocks.DMA_Audio_Freq = SCLK; /* 8 MHz (SCLK) */
269: MachineClocks.MFP_Freq = CLK4; /* 4 MHz (CLK4) */
270: MachineClocks.MFP_Timer_Freq = ATARI_MFP_XTAL; /* 2.4576 MHz (XTAL)*/
271: MachineClocks.FDC_Freq = SCLK; /* 8 MHz (SCLK) */
272: MachineClocks.BLITTER_Freq = CLK8; /* 8 MHz (CLK8) */
273: MachineClocks.YM_Freq = CLK2; /* 2 MHz (CLK2) */
274: MachineClocks.ACIA_Freq = KHZ500; /* 500 kHz (KHZ500) */
275: MachineClocks.IKBD_Freq = ATARI_IKBD_CLK; /* 1 MHz */
276: }
277:
278: else if ( MachineType == MACHINE_TT )
279: {
280: int CLK32, CLK16, CLK8, FCCLK, CLK4, CLK2, CLKX5;
281:
282: MachineClocks.MCLK_Freq = ATARI_TT_PAL_MCLK; /* 32.084988 MHz */
283: CLK32 = MachineClocks.MCLK_Freq;
284:
285: MachineClocks.TTVIDEO_Freq = MachineClocks.MCLK_Freq; /* 32 MHz */
286: CLK16 = MachineClocks.TTVIDEO_Freq / 2;
287: CLK4 = MachineClocks.TTVIDEO_Freq / 8;
288: CLK2 = MachineClocks.TTVIDEO_Freq / 16;
289:
290: MachineClocks.MCU_Freq = CLK16; /* 16 MHz (CLK16A) */
291: CLK8 = MachineClocks.MCU_Freq / 2;
292: FCCLK = MachineClocks.MCU_Freq / 2;
293: CLKX5 = MachineClocks.MCU_Freq / 32;
294:
295: MachineClocks.BUS_Freq = CLK16; /* 16 MHz (CLK16) */
296:
297: MachineClocks.CPU_Freq = CLK32; /* 32 MHz (CLK32) */
298: MachineClocks.FPU_Freq = CLK32; /* 32 MHz (CLK32) */
299: MachineClocks.DMA_Freq = CLK8; /* 8 MHz (CLK8) */
300: MachineClocks.DMA_Audio_Freq = CLK16; /* 16 MHz (CLK16) SND SHIFTER */
301: MachineClocks.MFP_Freq = CLK4; /* 4 MHz (CLK4) */
302: MachineClocks.MFP_Timer_Freq = ATARI_MFP_XTAL; /* 2.4576 MHz (XTAL)*/
303: MachineClocks.FDC_Freq = FCCLK; /* 8 MHz (FCCLK) */
304: MachineClocks.BLITTER_Freq = 0; /* No blitter in TT */
305: MachineClocks.YM_Freq = CLK2; /* 2 MHz (CLK2) */
306: MachineClocks.ACIA_Freq = CLKX5; /* 500 kHz (CLKX5) */
307: MachineClocks.IKBD_Freq = ATARI_IKBD_CLK; /* 1 MHz */
308: }
309:
310: else if ( MachineType == MACHINE_FALCON )
311: {
312: /* TODO : need more docs for Falcon's clocks */
313: int CLK32, CLK25, CLK16, FCCLK, CLK4, CLK2, KHZ500;
314:
315: MachineClocks.MCLK_Freq = ATARI_FALCON_PAL_MCLK; /* 32.084988 MHz */
316: CLK32 = MachineClocks.MCLK_Freq;
317: CLK25 = ATARI_FALCON_25M_CLK;
318: CLK16 = CLK32 / 2;
319: CLK2 = CLK32 / 16;
320: FCCLK = CLK16;
321:
322: MachineClocks.VIDEL_Freq = CLK32; /* 32 MHz */
323:
324: MachineClocks.COMBEL_Freq = CLK32; /* 16 MHz (CLK16A) */
325: CLK4 = MachineClocks.COMBEL_Freq / 8;
326: KHZ500 = MachineClocks.COMBEL_Freq / 64;
327:
328: MachineClocks.BUS_Freq = CLK16; /* 16 MHz (CPUCLK16A) */
329: MachineClocks.CPU_Freq = CLK16; /* 16 MHz (CPUCLK16B) */
330: MachineClocks.FPU_Freq = CLK16; /* 16 MHz (CLK32) */
331: MachineClocks.DSP_Freq = CLK32; /* 32 MHz */
332: MachineClocks.DMA_Freq = CLK16; /* 16 MHz (CLK16) ? */
333: MachineClocks.CODEC_Freq = CLK25; /* 25 MHz (CLK25) */
334: MachineClocks.MFP_Freq = CLK4; /* 4 MHz (CLK4) */
335: MachineClocks.MFP_Timer_Freq = ATARI_MFP_XTAL; /* 2.4576 MHz (XTAL)*/
336: MachineClocks.FDC_Freq = FCCLK; /* 16 MHz (FCCLK) ? */
337: MachineClocks.BLITTER_Freq = CLK16; /* 16 MHz */
338: MachineClocks.YM_Freq = CLK2; /* 2 MHz (CLK2) */
339: MachineClocks.ACIA_Freq = KHZ500; /* 500 kHz (KHZ500) */
340: MachineClocks.IKBD_Freq = ATARI_IKBD_CLK; /* 1 MHz */
341: }
342:
343:
344: }
345:
346:
347:
348:
349:
350: /*-----------------------------------------------------------------------------------------*/
351: /**
352: * Return the number of VBL per second, depending on the video settings and the cpu freq.
353: * This value is only known for STF/STE running at 50, 60 or 71 Hz.
354: * For the other machines, we return CPU_Freq / ScreenRefreshRate
355: */
356:
357: Uint32 ClocksTimings_GetCyclesPerVBL ( MACHINETYPE MachineType , int ScreenRefreshRate )
358: {
359: Uint32 CyclesPerVBL;
360:
361:
362: CyclesPerVBL = MachineClocks.CPU_Freq / ScreenRefreshRate; /* default value */
363:
364: /* STF and STE have the same numbers of cycles per VBL */
365: if ( ( MachineType == MACHINE_ST ) || ( MachineType == MACHINE_STE ) )
366: {
367: if ( ScreenRefreshRate == 50 )
368: CyclesPerVBL = ATARI_STF_CYCLES_PER_VBL_PAL;
369: else if ( ScreenRefreshRate == 60 )
370: CyclesPerVBL = ATARI_STF_CYCLES_PER_VBL_NTSC;
371: else if ( ScreenRefreshRate == 71 )
372: CyclesPerVBL = ATARI_STF_CYCLES_PER_VBL_HI;
373: else
374: CyclesPerVBL = MachineClocks.CPU_Freq / ScreenRefreshRate; /* should not happen */
375: }
376:
377: /* For machines where cpu freq can be changed, we don't know the number of cycles per VBL */
378: /* -> TODO, for now comment code to keep the default value from above */
379: //else if ( ( MachineType == MACHINE_MEGA_STE ) || ( MachineType == MACHINE_TT ) || ( MachineType == MACHINE_FALCON ) )
380: // CyclesPerVBL = MachineClocks.CPU_Freq / ScreenRefreshRate;
381:
382:
383: return CyclesPerVBL;
384: }
385:
386:
387:
388:
389: /*-----------------------------------------------------------------------------------------*/
390: /**
391: * Return the number of VBL per second, depending on the video settings and the cpu freq.
392: * Since the cpu freq is not an exact multiple of the number of cycles per VBL, the real
393: * value slightly differs from the usual 50/60 Hz.
394: * Precise values are needed in STE mode to synchronize cpu and dma sound (as they both use
395: * 2 different clocks).
396: * example for STF/STE :
397: * PAL STF/STE video PAL : 50.053 VBL/sec
398: * PAL STF/STE video NTSC : 60.037 VBL/sec
399: * NTSC STF/STE video PAL : 49.986 VBL/sec
400: * NTSC STF/STE video NTSC : 59.958 VBL/sec
401: *
402: * The returned number of VBL per sec is << 24 (=CLOCKS_TIMINGS_SHIFT_VBL) to simulate floating point using Uint32.
403: */
404:
405: Uint32 ClocksTimings_GetVBLPerSec ( MACHINETYPE MachineType , int ScreenRefreshRate )
406: {
407: Uint32 VBLPerSec; /* Upper 8 bits are for int part, 24 lower bits for float part */
408:
409:
410: VBLPerSec = ScreenRefreshRate << CLOCKS_TIMINGS_SHIFT_VBL; /* default rounded value */
411:
412: if ( RoundVBLPerSec == false )
413: {
414: /* STF and STE have the same numbers of cycles per VBL */
415: if ( ( MachineType == MACHINE_ST ) || ( MachineType == MACHINE_STE ) )
416: VBLPerSec = ( (Sint64)MachineClocks.CPU_Freq << CLOCKS_TIMINGS_SHIFT_VBL ) / ClocksTimings_GetCyclesPerVBL ( MachineType , ScreenRefreshRate );
417:
418: /* For machines where cpu freq can be changed, we don't know the number of cycles per VBL */
419: /* -> TODO, for now comment code to keep the default value from above */
420: //else if ( ( MachineType == MACHINE_MEGA_STE ) || ( MachineType == MACHINE_TT ) || ( MachineType == MACHINE_FALCON ) )
421: // VBLPerSec = ScreenRefreshRate << CLOCKS_TIMINGS_SHIFT_VBL;
422: }
423:
424:
425: return VBLPerSec;
426: }
427:
428:
429:
430:
431: /*-----------------------------------------------------------------------------------------*/
432: /**
433: * Return the length in microsec of a VBL (opposite function of ClocksTimings_GetVBLPerSec)
434: * We use precise values only in STF/STE mode, else we use 1000000 / ScreenRefreshRate.
435: * example for STF/STE :
436: * PAL STF/STE video PAL : 19979 micro sec (instead of 20000 for 50 Hz)
437: * PAL STF/STE video NTSC : 16656 micro sec (instead of 16667 for 60 Hz)
438: */
439:
440: Uint32 ClocksTimings_GetVBLDuration_micro ( MACHINETYPE MachineType , int ScreenRefreshRate )
441: {
442: Uint32 VBLDuration_micro;
443:
444:
445: VBLDuration_micro = (Uint32) (1000000.0 / ScreenRefreshRate + 0.5); /* default rounded value, round to closest integer */
446:
447: if ( RoundVBLPerSec == false )
448: {
449: /* STF and STE have the same numbers of cycles per VBL */
450: if ( ( MachineType == MACHINE_ST ) || ( MachineType == MACHINE_STE ) )
451: VBLDuration_micro = (Uint32) (1000000.0 * ClocksTimings_GetCyclesPerVBL ( MachineType , ScreenRefreshRate ) / MachineClocks.CPU_Freq + 0.5);
452:
453: /* For machines where cpu freq can be changed, we don't know the number of cycles per VBL */
454: /* -> TODO, for now comment code to keep the default value from above */
455: //else if ( ( MachineType == MACHINE_MEGA_STE ) || ( MachineType == MACHINE_TT ) || ( MachineType == MACHINE_FALCON ) )
456: // VBLDuration_micro = (Uint32) (1000000.0 / ScreenRefreshRate + 0.5);
457: }
458:
459:
460: return VBLDuration_micro;
461: }
462:
463:
464:
465:
466: /*-----------------------------------------------------------------------------------------*/
467: /**
468: * Return the number of samples needed to emulate the sound that was produced during one VBL.
469: * This depends on the chosen audio output frequency, as well as the VBL's duration,
470: *
471: * We use precise values only in STF/STE mode, else we use AudioFreq/ScreenRefreshRate.
472: *
473: * The returned number of samples per VBL is << 28 to simulate maximum precision using
474: * 64 bits integers (lower 28 bits are for the floating point part).
475: * example for STF/STE with emulation's audio freq = 44100 :
476: * PAL STF/STE video PAL : 881.07 samples per VBL (instead of 882 for 50 Hz)
477: * 44053.56 samples for 50 VBLs (instead of 44100 for 1 sec at 50 Hz)
478: */
479:
480: Sint64 ClocksTimings_GetSamplesPerVBL ( MACHINETYPE MachineType , int ScreenRefreshRate , int AudioFreq )
481: {
482: Sint64 SamplesPerVBL;
483:
484:
485: SamplesPerVBL = ( ((Sint64)AudioFreq) << 28 ) / ScreenRefreshRate; /* default value */
486:
487: if ( RoundVBLPerSec == false )
488: {
489: /* STF and STE have the same numbers of cycles per VBL */
490: if ( ( MachineType == MACHINE_ST ) || ( MachineType == MACHINE_STE ) )
491: SamplesPerVBL = ( ((Sint64)AudioFreq * ClocksTimings_GetCyclesPerVBL ( MachineType , ScreenRefreshRate ) ) << 28 ) / MachineClocks.CPU_Freq;
492:
493: /* For machines where cpu freq can be changed, we don't know the number of cycles per VBL */
494: /* -> TODO, for now comment code to keep the default value from above */
495: //else if ( ( MachineType == MACHINE_MEGA_STE ) || ( MachineType == MACHINE_TT ) || ( MachineType == MACHINE_FALCON ) )
496: // SamplesPerVBL = ( ((Sint64)AudioFreq) << 28 ) / ScreenRefreshRate;
497: }
498:
499:
500: return SamplesPerVBL;
501: }
502:
503:
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