--- hatari/src/cpu/cpu_prefetch.h	2019/04/09 08:55:30	1.1.1.3
+++ hatari/src/cpu/cpu_prefetch.h	2019/04/09 08:57:58	1.1.1.5
@@ -1,3 +1,7 @@
+#ifndef UAE_CPU_PREFETCH_H
+#define UAE_CPU_PREFETCH_H
+
+#include "uae/types.h"
 
 #ifdef CPUEMU_20
 
@@ -28,22 +32,44 @@ STATIC_INLINE uae_u32 get_long_020_prefe
 
 #ifdef CPUEMU_21
 
-#define CE020_INITCYCLES() \
-	int head = 0, tail = 0, cycles = 0; \
-	unsigned int cu = get_cycles ();
-#define CE020_SAVECYCLES(h,t,c) \
-	head = h; tail = t; cycles = c;
-#define CE020_COUNTCYCLES()
+STATIC_INLINE void limit_cycles_ce020(int clocks)
+{
+#if 0
+	int cycs = clocks * cpucycleunit;
+	int diff = regs.ce020endcycle - regs.ce020startcycle;
+	if (diff <= cycs)
+		return;
+	regs.ce020startcycle = regs.ce020endcycle - cycs;
+#endif
+}
+
+STATIC_INLINE void limit_all_cycles_ce020(void)
+{
+#if 0
+	regs.ce020startcycle = regs.ce020endcycle;
+#endif
+}
 
 // only for CPU internal cycles
 STATIC_INLINE void do_cycles_ce020_internal(int clocks)
 {
+//fprintf ( stderr , "do_cycles_ce020_internal %d sp=%d" , clocks , currprefs.m68k_speed );
 	if (currprefs.m68k_speed < 0) {
 		regs.ce020extracycles += clocks;
 		return;
 	}
 	int cycs = clocks * cpucycleunit;
 //fprintf ( stderr , "do_cycles_ce020_internal %d %d" , cycs , regs.ce020memcycles );
+	int diff = regs.ce020endcycle - regs.ce020startcycle;
+	if (diff > 0) {
+		if (diff >= cycs) {
+			regs.ce020startcycle += cycs;
+			return;
+		}
+		regs.ce020startcycle = regs.ce020endcycle;
+		cycs -= diff;
+	}
+#if 0
 	if (regs.ce020memcycles > 0) {
 		if (regs.ce020memcycles >= cycs) {
 			regs.ce020memcycles -= cycs;
@@ -53,6 +79,7 @@ STATIC_INLINE void do_cycles_ce020_inter
 	}
 //fprintf ( stderr , " -> %d\n" , cycs );
 	regs.ce020memcycles = 0;
+#endif
 	x_do_cycles (cycs);
 }
 
@@ -77,14 +104,6 @@ STATIC_INLINE void do_head_cycles_ce020
 }
 #endif
 
-void mem_access_delay_long_write_ce020 (uaecptr addr, uae_u32 v);
-void mem_access_delay_word_write_ce020 (uaecptr addr, uae_u32 v);
-void mem_access_delay_byte_write_ce020 (uaecptr addr, uae_u32 v);
-uae_u32 mem_access_delay_byte_read_ce020 (uaecptr addr);
-uae_u32 mem_access_delay_word_read_ce020 (uaecptr addr);
-uae_u32 mem_access_delay_longi_read_ce020 (uaecptr addr);
-uae_u32 mem_access_delay_long_read_ce020 (uaecptr addr);
-
 STATIC_INLINE uae_u32 get_long_ce020 (uaecptr addr)
 {
 	return mem_access_delay_long_read_ce020 (addr);
@@ -113,6 +132,7 @@ STATIC_INLINE void put_byte_ce020 (uaecp
 
 extern void continue_ce020_prefetch(void);
 extern uae_u32 get_word_ce020_prefetch(int);
+extern uae_u32 get_word_ce020_prefetch_opcode(int);
 
 STATIC_INLINE uae_u32 get_long_ce020_prefetch (int o)
 {
@@ -155,31 +175,32 @@ STATIC_INLINE void m68k_do_rts_ce020 (vo
 
 #ifdef CPUEMU_22
 
+extern void continue_030_prefetch(void);
 extern uae_u32 get_word_030_prefetch(int);
 
 STATIC_INLINE void put_long_030(uaecptr addr, uae_u32 v)
 {
-	write_dcache030(addr, v, 2);
+	write_data_030_lput(addr, v);
 }
 STATIC_INLINE void put_word_030(uaecptr addr, uae_u32 v)
 {
-	write_dcache030(addr, v, 1);
+	write_data_030_wput(addr, v);
 }
 STATIC_INLINE void put_byte_030(uaecptr addr, uae_u32 v)
 {
-	write_dcache030(addr, v, 0);
+	write_data_030_bput(addr, v);
 }
 STATIC_INLINE uae_u32 get_long_030(uaecptr addr)
 {
-	return read_dcache030(addr, 2);
+	return read_data_030_lget(addr);
 }
 STATIC_INLINE uae_u32 get_word_030(uaecptr addr)
 {
-	return read_dcache030(addr, 1);
+	return read_data_030_wget(addr);
 }
 STATIC_INLINE uae_u32 get_byte_030(uaecptr addr)
 {
-	return read_dcache030(addr, 0);
+	return read_data_030_bget(addr);
 }
 
 STATIC_INLINE uae_u32 get_long_030_prefetch(int o)
@@ -219,31 +240,60 @@ STATIC_INLINE void m68k_do_rts_030(void)
 
 #ifdef CPUEMU_23
 
+extern void continue_ce030_prefetch(void);
 extern uae_u32 get_word_ce030_prefetch(int);
+extern uae_u32 get_word_ce030_prefetch_opcode(int);
+
+STATIC_INLINE uae_u32 get_long_ce030 (uaecptr addr)
+{
+	return mem_access_delay_long_read_ce020 (addr);
+}
+STATIC_INLINE uae_u32 get_word_ce030 (uaecptr addr)
+{
+	return mem_access_delay_word_read_ce020 (addr);
+}
+STATIC_INLINE uae_u32 get_byte_ce030 (uaecptr addr)
+{
+	return mem_access_delay_byte_read_ce020 (addr);
+}
 
 STATIC_INLINE void put_long_ce030 (uaecptr addr, uae_u32 v)
 {
-	write_dcache030 (addr, v, 2);
+	mem_access_delay_long_write_ce020 (addr, v);
 }
 STATIC_INLINE void put_word_ce030 (uaecptr addr, uae_u32 v)
 {
-	write_dcache030 (addr, v, 1);
+	mem_access_delay_word_write_ce020 (addr, v);
 }
 STATIC_INLINE void put_byte_ce030 (uaecptr addr, uae_u32 v)
 {
-	write_dcache030 (addr, v, 0);
+	mem_access_delay_byte_write_ce020 (addr, v);
 }
-STATIC_INLINE uae_u32 get_long_ce030 (uaecptr addr)
+
+
+STATIC_INLINE void put_long_dc030 (uaecptr addr, uae_u32 v)
 {
-	return read_dcache030 (addr, 2);
+	write_dcache030_lput(addr, v, (regs.s ? 4 : 0) | 1);
 }
-STATIC_INLINE uae_u32 get_word_ce030 (uaecptr addr)
+STATIC_INLINE void put_word_dc030 (uaecptr addr, uae_u32 v)
 {
-	return read_dcache030 (addr, 1);
+	write_dcache030_wput(addr, v, (regs.s ? 4 : 0) | 1);
 }
-STATIC_INLINE uae_u32 get_byte_ce030 (uaecptr addr)
+STATIC_INLINE void put_byte_dc030 (uaecptr addr, uae_u32 v)
+{
+	write_dcache030_bput(addr, v, (regs.s ? 4 : 0) | 1);
+}
+STATIC_INLINE uae_u32 get_long_dc030 (uaecptr addr)
+{
+	return read_dcache030_lget(addr, (regs.s ? 4 : 0) | 1);
+}
+STATIC_INLINE uae_u32 get_word_dc030 (uaecptr addr)
+{
+	return read_dcache030_wget(addr, (regs.s ? 4 : 0) | 1);
+}
+STATIC_INLINE uae_u32 get_byte_dc030 (uaecptr addr)
 {
-	return read_dcache030 (addr, 0);
+	return read_dcache030_bget(addr, (regs.s ? 4 : 0) | 1);
 }
 
 STATIC_INLINE uae_u32 get_long_ce030_prefetch (int o)
@@ -270,12 +320,12 @@ STATIC_INLINE uae_u32 next_ilong_030ce (
 STATIC_INLINE void m68k_do_bsr_ce030 (uaecptr oldpc, uae_s32 offset)
 {
 	m68k_areg (regs, 7) -= 4;
-	put_long_ce030 (m68k_areg (regs, 7), oldpc);
+	x_put_long (m68k_areg (regs, 7), oldpc);
 	m68k_incpci (offset);
 }
 STATIC_INLINE void m68k_do_rts_ce030 (void)
 {
-	m68k_setpc (get_long_ce030 (m68k_areg (regs, 7)));
+	m68k_setpc (x_get_long (m68k_areg (regs, 7)));
 	m68k_areg (regs, 7) += 4;
 }
 
@@ -283,30 +333,30 @@ STATIC_INLINE void m68k_do_rts_ce030 (vo
 
 #ifdef CPUEMU_11
 
-STATIC_INLINE uae_u32 get_word_prefetch (int o)
+STATIC_INLINE uae_u32 get_word_000_prefetch(int o)
 {
 	uae_u32 v = regs.irc;
 	regs.irc = regs.db = get_wordi (m68k_getpci () + o);
 	return v;
 }
-STATIC_INLINE uae_u32 get_byte_prefetch (uaecptr addr)
+STATIC_INLINE uae_u32 get_byte_000(uaecptr addr)
 {
 	uae_u32 v = get_byte (addr);
 	regs.db = (v << 8) | v;
 	return v;
 }
-STATIC_INLINE uae_u32 get_word_prefetch_addr (uaecptr addr)
+STATIC_INLINE uae_u32 get_word_000(uaecptr addr)
 {
 	uae_u32 v = get_word (addr);
 	regs.db = v;
 	return v;
 }
-STATIC_INLINE void put_byte_prefetch (uaecptr addr, uae_u32 v)
+STATIC_INLINE void put_byte_000(uaecptr addr, uae_u32 v)
 {
 	regs.db = (v << 8) | v;
 	put_byte (addr, v);
 }
-STATIC_INLINE void put_word_prefetch (uaecptr addr, uae_u32 v)
+STATIC_INLINE void put_word_000(uaecptr addr, uae_u32 v)
 {
 	regs.db = v;
 	put_word (addr, v);
@@ -331,128 +381,11 @@ STATIC_INLINE void ipl_fetch (void)
 	regs.ipl = regs.ipl_pin;
 }
 
-STATIC_INLINE uae_u32 mem_access_delay_word_read (uaecptr addr)
-{
-	uae_u32 v;
-#ifndef WINUAE_FOR_HATARI
-	switch (ce_banktype[addr >> 16])
-	{
-	case CE_MEMBANK_CHIP16:
-	case CE_MEMBANK_CHIP32:
-		v = wait_cpu_cycle_read (addr, 1);
-		break;
-	case CE_MEMBANK_FAST16:
-	case CE_MEMBANK_FAST32:
-		v = get_word (addr);
-		x_do_cycles_post (4 * cpucycleunit, v);
-		break;
-	default:
-		v = get_word (addr);
-		break;
-	}
-#else
-	v = get_word (addr);
-	x_do_cycles_post (4 * cpucycleunit, v);
-#endif
-	regs.db = v;
-	return v;
-}
-STATIC_INLINE uae_u32 mem_access_delay_wordi_read (uaecptr addr)
-{
-	uae_u32 v;
-#ifndef WINUAE_FOR_HATARI
-	switch (ce_banktype[addr >> 16])
-	{
-	case CE_MEMBANK_CHIP16:
-	case CE_MEMBANK_CHIP32:
-		v = wait_cpu_cycle_read (addr, 1);
-		break;
-	case CE_MEMBANK_FAST16:
-	case CE_MEMBANK_FAST32:
-		v = get_wordi (addr);
-		x_do_cycles_post (4 * cpucycleunit, v);
-		break;
-	default:
-		v = get_wordi (addr);
-		break;
-	}
-#else
-	v = get_wordi (addr);
-	x_do_cycles_post (4 * cpucycleunit, v);
-#endif
-	regs.db = v;
-	return v;
-}
-
-STATIC_INLINE uae_u32 mem_access_delay_byte_read (uaecptr addr)
-{
-	uae_u32  v;
-#ifndef WINUAE_FOR_HATARI
-	switch (ce_banktype[addr >> 16])
-	{
-	case CE_MEMBANK_CHIP16:
-	case CE_MEMBANK_CHIP32:
-		v = wait_cpu_cycle_read (addr, 0);
-		break;
-	case CE_MEMBANK_FAST16:
-	case CE_MEMBANK_FAST32:
-		v = get_byte (addr);
-		x_do_cycles_post (4 * cpucycleunit, v);
-		break;
-	default:
-		v = get_byte (addr);
-		break;
-	}
-#else
-	v = get_byte (addr);
-	x_do_cycles_post (4 * cpucycleunit, v);
-#endif
-	regs.db = (v << 8) | v;
-	return v;
-}
-STATIC_INLINE void mem_access_delay_byte_write (uaecptr addr, uae_u32 v)
-{
-	regs.db = (v << 8)  | v;
-#ifndef WINUAE_FOR_HATARI
-	switch (ce_banktype[addr >> 16])
-	{
-	case CE_MEMBANK_CHIP16:
-	case CE_MEMBANK_CHIP32:
-		wait_cpu_cycle_write (addr, 0, v);
-		return;
-	case CE_MEMBANK_FAST16:
-	case CE_MEMBANK_FAST32:
-		put_byte (addr, v);
-		x_do_cycles_post (4 * cpucycleunit, v);
-		return;
-	}
-#else
-	put_byte (addr, v);
-	x_do_cycles_post (4 * cpucycleunit, v);
-#endif
-}
-STATIC_INLINE void mem_access_delay_word_write (uaecptr addr, uae_u32 v)
-{
-#ifndef WINUAE_FOR_HATARI
-	regs.db = v;
-	switch (ce_banktype[addr >> 16])
-	{
-	case CE_MEMBANK_CHIP16:
-	case CE_MEMBANK_CHIP32:
-		wait_cpu_cycle_write (addr, 1, v);
-		return;
-	case CE_MEMBANK_FAST16:
-	case CE_MEMBANK_FAST32:
-		put_word (addr, v);
-		x_do_cycles_post (4 * cpucycleunit, v);
-		return;
-	}
-	put_word (addr, v);
-#else
-	put_word (addr, v);
-	x_do_cycles_post (4 * cpucycleunit, v);
-#endif
-}
+uae_u32 mem_access_delay_word_read (uaecptr addr);
+uae_u32 mem_access_delay_wordi_read (uaecptr addr);
+uae_u32 mem_access_delay_byte_read (uaecptr addr);
+void mem_access_delay_byte_write (uaecptr addr, uae_u32 v);
+void mem_access_delay_word_write (uaecptr addr, uae_u32 v);
 
 STATIC_INLINE uae_u32 get_long_ce000 (uaecptr addr)
 {
@@ -528,3 +461,5 @@ STATIC_INLINE uae_u32 get_disp_ea_000 (u
 		regd = (uae_s32)(uae_s16)regd;
 	return base + (uae_s8)dp + regd;
 }
+
+#endif /* UAE_CPU_PREFETCH_H */