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1.1.1.2 root 1: /*
2: * cpummu.h - MMU emulation
3: *
4: * Copyright (c) 2001-2004 Milan Jurik of ARAnyM dev team (see AUTHORS)
1.1.1.4 root 5: *
1.1.1.2 root 6: * Inspired by UAE MMU patch
7: *
8: * This file is part of the ARAnyM project which builds a new and powerful
9: * TOS/FreeMiNT compatible virtual machine running on almost any hardware.
10: *
11: * ARAnyM is free software; you can redistribute it and/or modify
12: * it under the terms of the GNU General Public License as published by
13: * the Free Software Foundation; either version 2 of the License, or
14: * (at your option) any later version.
15: *
16: * ARAnyM is distributed in the hope that it will be useful,
17: * but WITHOUT ANY WARRANTY; without even the implied warranty of
18: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19: * GNU General Public License for more details.
20: *
21: * You should have received a copy of the GNU General Public License
1.1.1.6 root 22: * along with ARAnyM; if not, write to the Free Software Foundation,
23: * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335 USA
1.1.1.2 root 24: */
25:
1.1.1.4 root 26:
1.1.1.5 root 27: #ifndef UAE_CPUMMU_H
28: #define UAE_CPUMMU_H
29:
30: #include "uae/types.h"
1.1.1.2 root 31:
1.1.1.6 root 32: #define MMU_ICACHE 0
33: #define MMU_IPAGECACHE 1
34: #define MMU_DPAGECACHE 1
35:
36: #define CACHE_HIT_COUNT 0
37:
1.1.1.3 root 38: #include "mmu_common.h"
1.1.1.2 root 39:
40: #ifndef FULLMMU
41: #define FULLMMU
42: #endif
43:
44: #define DUNUSED(x)
45: #define D
46: #if DEBUG
47: #define bug write_log
48: #else
49: #define bug
50: #endif
51:
52: static __inline void flush_internals (void) { }
53:
1.1.1.4 root 54: extern int mmu060_state;
55:
56: extern int mmu040_movem;
57: extern uaecptr mmu040_movem_ea;
58: extern uae_u32 mmu040_move16[4];
59:
60: extern bool mmu_pagesize_8k;
1.1.1.6 root 61: extern int mmu_pageshift, mmu_pageshift1m;
1.1.1.4 root 62: extern uae_u16 mmu_opcode;
63: extern bool mmu_restart;
1.1.1.6 root 64: extern bool mmu_ttr_enabled, mmu_ttr_enabled_ins, mmu_ttr_enabled_data;
65: extern bool rmw_cycle;
66: extern uae_u8 mmu_cache_state;
67: extern uae_u8 cache_default_ins, cache_default_data;
1.1.1.2 root 68:
69: extern void mmu_dump_tables(void);
70:
71: #define MMU_TTR_LOGICAL_BASE 0xff000000
72: #define MMU_TTR_LOGICAL_MASK 0x00ff0000
73: #define MMU_TTR_BIT_ENABLED (1 << 15)
74: #define MMU_TTR_BIT_SFIELD_ENABLED (1 << 14)
75: #define MMU_TTR_BIT_SFIELD_SUPER (1 << 13)
76: #define MMU_TTR_SFIELD_SHIFT 13
77: #define MMU_TTR_UX_MASK ((1 << 9) | (1 << 8))
78: #define MMU_TTR_UX_SHIFT 8
79: #define MMU_TTR_CACHE_MASK ((1 << 6) | (1 << 5))
80: #define MMU_TTR_CACHE_SHIFT 5
1.1.1.6 root 81: #define MMU_TTR_CACHE_DISABLE (1 << 6)
82: #define MMU_TTR_CACHE_MODE (1 << 5)
1.1.1.2 root 83: #define MMU_TTR_BIT_WRITE_PROTECT (1 << 2)
84:
85: #define MMU_UDT_MASK 3
86: #define MMU_PDT_MASK 3
87:
88: #define MMU_DES_WP 4
89: #define MMU_DES_USED 8
90:
91: /* page descriptors only */
92: #define MMU_DES_MODIFIED 16
93: #define MMU_DES_SUPER (1 << 7)
94: #define MMU_DES_GLOBAL (1 << 10)
95:
96: #define MMU_ROOT_PTR_ADDR_MASK 0xfffffe00
97: #define MMU_PTR_PAGE_ADDR_MASK_8 0xffffff80
98: #define MMU_PTR_PAGE_ADDR_MASK_4 0xffffff00
99:
100: #define MMU_PAGE_INDIRECT_MASK 0xfffffffc
101: #define MMU_PAGE_ADDR_MASK_8 0xffffe000
102: #define MMU_PAGE_ADDR_MASK_4 0xfffff000
103: #define MMU_PAGE_UR_MASK_8 ((1 << 12) | (1 << 11))
104: #define MMU_PAGE_UR_MASK_4 (1 << 11)
105: #define MMU_PAGE_UR_SHIFT 11
106:
107: #define MMU_MMUSR_ADDR_MASK 0xfffff000
108: #define MMU_MMUSR_B (1 << 11)
109: #define MMU_MMUSR_G (1 << 10)
110: #define MMU_MMUSR_U1 (1 << 9)
111: #define MMU_MMUSR_U0 (1 << 8)
112: #define MMU_MMUSR_Ux (MMU_MMUSR_U1 | MMU_MMUSR_U0)
113: #define MMU_MMUSR_S (1 << 7)
114: #define MMU_MMUSR_CM ((1 << 6) | ( 1 << 5))
1.1.1.6 root 115: #define MMU_MMUSR_CM_DISABLE (1 << 6)
116: #define MMU_MMUSR_CM_MODE (1 << 5)
1.1.1.2 root 117: #define MMU_MMUSR_M (1 << 4)
118: #define MMU_MMUSR_W (1 << 2)
119: #define MMU_MMUSR_T (1 << 1)
120: #define MMU_MMUSR_R (1 << 0)
121:
1.1.1.6 root 122: // 68040 and 68060
123: #define MMU_TCR_E 0x8000
124: #define MMU_TCR_P 0x4000
125: // 68060 only
126: #define MMU_TCR_NAD 0x2000
127: #define MMU_TCR_NAI 0x1000
128: #define MMU_TCR_FOTC 0x0800
129: #define MMU_TCR_FITC 0x0400
130: #define MMU_TCR_DCO1 0x0200
131: #define MMU_TCR_DCO0 0x0100
132: #define MMU_TCR_DUO1 0x0080
133: #define MMU_TCR_DUO0 0x0040
134: #define MMU_TCR_DWO 0x0020
135: #define MMU_TCR_DCI1 0x0010
136: #define MMU_TCR_DCI0 0x0008
137: #define MMU_TCR_DUI1 0x0004
138: #define MMU_TCR_DUI0 0x0002
139:
1.1.1.2 root 140: #define TTR_I0 4
141: #define TTR_I1 5
142: #define TTR_D0 6
143: #define TTR_D1 7
144:
145: #define TTR_NO_MATCH 0
146: #define TTR_NO_WRITE 1
147: #define TTR_OK_MATCH 2
148:
149: struct mmu_atc_line {
1.1.1.4 root 150: uaecptr tag; // tag is 16 or 17 bits S+logical
1.1.1.6 root 151: uae_u32 valid;
152: uae_u32 status;
1.1.1.4 root 153: uaecptr phys; // phys base address
1.1.1.2 root 154: };
155:
156: /*
1.1.1.4 root 157: * 68040 ATC is a 4 way 16 slot associative address translation cache
158: * the 68040 has a DATA and an INSTRUCTION ATC.
159: * an ATC lookup may result in : a hit, a miss and a modified state.
160: * the 68060 can disable ATC allocation
161: * we must take care of 8k and 4k page size, index position is relative to page size
1.1.1.2 root 162: */
163:
1.1.1.4 root 164: #define ATC_WAYS 4
165: #define ATC_SLOTS 16
166: #define ATC_TYPE 2
167:
168: extern uae_u32 mmu_is_super;
1.1.1.6 root 169: extern uae_u32 mmu_tagmask, mmu_pagemask, mmu_pagemaski;
170: extern struct mmu_atc_line mmu_atc_array[ATC_TYPE][ATC_SLOTS][ATC_WAYS];
1.1.1.4 root 171:
1.1.1.6 root 172: extern void mmu_tt_modified(void);
173: extern int mmu_match_ttr_ins(uaecptr addr, bool super);
174: extern int mmu_match_ttr(uaecptr addr, bool super, bool data);
175: extern void mmu_bus_error_ttr_write_fault(uaecptr addr, bool super, bool data, uae_u32 val, int size);
176: extern int mmu_match_ttr_write(uaecptr addr, bool super, bool data, uae_u32 val, int size);
177: extern int mmu_match_ttr_maybe_write(uaecptr addr, bool super, bool data, int size, bool write);
178: extern uaecptr mmu_translate(uaecptr addr, uae_u32 val, bool super, bool data, bool write, int size);
1.1.1.4 root 179:
180: extern uae_u32 REGPARAM3 mmu060_get_rmw_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
181: extern void REGPARAM3 mmu060_put_rmw_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;
182:
1.1.1.6 root 183: extern uae_u16 REGPARAM3 mmu_get_word_unaligned(uaecptr addr, bool data) REGPARAM;
184: extern uae_u32 REGPARAM3 mmu_get_long_unaligned(uaecptr addr, bool data) REGPARAM;
1.1.1.2 root 185:
1.1.1.4 root 186: extern uae_u32 REGPARAM3 mmu_get_ilong_unaligned(uaecptr addr) REGPARAM;
1.1.1.2 root 187:
1.1.1.6 root 188: extern void REGPARAM3 mmu_put_word_unaligned(uaecptr addr, uae_u16 val, bool data) REGPARAM;
189: extern void REGPARAM3 mmu_put_long_unaligned(uaecptr addr, uae_u32 val, bool data) REGPARAM;
1.1.1.2 root 190:
191: extern void mmu_make_transparent_region(uaecptr baseaddr, uae_u32 size, int datamode);
192:
193: #define FC_DATA (regs.s ? 5 : 1)
194: #define FC_INST (regs.s ? 6 : 2)
195:
1.1.1.6 root 196: extern void mmu_bus_error(uaecptr addr, uae_u32 val, int fc, bool write, int size, uae_u32 status, bool nonmmu);
1.1.1.2 root 197:
198: extern uae_u32 REGPARAM3 sfc_get_long(uaecptr addr) REGPARAM;
199: extern uae_u16 REGPARAM3 sfc_get_word(uaecptr addr) REGPARAM;
200: extern uae_u8 REGPARAM3 sfc_get_byte(uaecptr addr) REGPARAM;
201: extern void REGPARAM3 dfc_put_long(uaecptr addr, uae_u32 val) REGPARAM;
202: extern void REGPARAM3 dfc_put_word(uaecptr addr, uae_u16 val) REGPARAM;
203: extern void REGPARAM3 dfc_put_byte(uaecptr addr, uae_u8 val) REGPARAM;
204:
1.1.1.4 root 205: #define sfc040_get_long sfc_get_long
206: #define sfc040_get_word sfc_get_word
207: #define sfc040_get_byte sfc_get_byte
208: #define dfc040_put_long dfc_put_long
209: #define dfc040_put_word dfc_put_word
210: #define dfc040_put_byte dfc_put_byte
211:
212: #define sfc060_get_long sfc_get_long
213: #define sfc060_get_word sfc_get_word
214: #define sfc060_get_byte sfc_get_byte
215: #define dfc060_put_long dfc_put_long
216: #define dfc060_put_word dfc_put_word
217: #define dfc060_put_byte dfc_put_byte
218:
219: extern void uae_mmu_put_lrmw (uaecptr addr, uae_u32 v, int size, int type);
220: extern uae_u32 uae_mmu_get_lrmw (uaecptr addr, int size, int type);
1.1.1.2 root 221:
222: extern void REGPARAM3 mmu_flush_atc(uaecptr addr, bool super, bool global) REGPARAM;
223: extern void REGPARAM3 mmu_flush_atc_all(bool global) REGPARAM;
224: extern void REGPARAM3 mmu_op_real(uae_u32 opcode, uae_u16 extra) REGPARAM;
225:
226: extern void REGPARAM3 mmu_reset(void) REGPARAM;
1.1.1.4 root 227: extern void REGPARAM3 mmu_set_funcs(void) REGPARAM;
1.1.1.6 root 228: extern uae_u16 REGPARAM3 mmu_set_tc(uae_u16 tc) REGPARAM;
1.1.1.2 root 229: extern void REGPARAM3 mmu_set_super(bool super) REGPARAM;
1.1.1.6 root 230: extern void REGPARAM3 mmu_flush_cache(void) REGPARAM;
1.1.1.2 root 231:
232: static ALWAYS_INLINE uaecptr mmu_get_real_address(uaecptr addr, struct mmu_atc_line *cl)
233: {
1.1.1.6 root 234: return cl->phys | (addr & mmu_pagemask);
1.1.1.2 root 235: }
236:
1.1.1.4 root 237: extern void mmu_get_move16(uaecptr addr, uae_u32 *v, bool data, int size);
238: extern void mmu_put_move16(uaecptr addr, uae_u32 *val, bool data, int size);
239:
1.1.1.6 root 240: #if MMU_IPAGECACHE
241: extern uae_u32 atc_last_ins_laddr, atc_last_ins_paddr;
242: extern uae_u8 atc_last_ins_cache;
243: #endif
1.1.1.2 root 244:
1.1.1.6 root 245: #if MMU_DPAGECACHE
246: #define MMUFASTCACHE_ENTRIES 256
247: struct mmufastcache
248: {
249: uae_u32 log;
250: uae_u32 phys;
251: uae_u8 cache_state;
252: };
253: extern struct mmufastcache atc_data_cache_read[MMUFASTCACHE_ENTRIES];
254: extern struct mmufastcache atc_data_cache_write[MMUFASTCACHE_ENTRIES];
255: #endif
256:
257: #if CACHE_HIT_COUNT
258: extern int mmu_ins_hit, mmu_ins_miss;
259: extern int mmu_data_read_hit, mmu_data_read_miss;
260: extern int mmu_data_write_hit, mmu_data_write_miss;
261: #endif
1.1.1.2 root 262:
1.1.1.4 root 263: static ALWAYS_INLINE uae_u32 mmu_get_ilong(uaecptr addr, int size)
1.1.1.2 root 264: {
1.1.1.6 root 265: mmu_cache_state = cache_default_ins;
266: if ((!mmu_ttr_enabled_ins || mmu_match_ttr_ins(addr,regs.s!=0) == TTR_NO_MATCH) && regs.mmu_enabled) {
267: #if MMU_IPAGECACHE
268: if (((addr & mmu_pagemaski) | regs.s) == atc_last_ins_laddr) {
269: #if CACHE_HIT_COUNT
270: mmu_ins_hit++;
271: #endif
272: addr = atc_last_ins_paddr | (addr & mmu_pagemask);
273: mmu_cache_state = atc_last_ins_cache;
274: } else {
275: #if CACHE_HIT_COUNT
276: mmu_ins_miss++;
277: #endif
278: #endif
279: addr = mmu_translate(addr, 0, regs.s!=0, false, false, size);
280: #if MMU_IPAGECACHE
281: }
282: #endif
283: }
284: return x_phys_get_ilong(addr);
1.1.1.2 root 285: }
286:
1.1.1.4 root 287: static ALWAYS_INLINE uae_u16 mmu_get_iword(uaecptr addr, int size)
288: {
1.1.1.6 root 289: mmu_cache_state = cache_default_ins;
290: if ((!mmu_ttr_enabled_ins || mmu_match_ttr_ins(addr,regs.s!=0) == TTR_NO_MATCH) && regs.mmu_enabled) {
291: #if MMU_IPAGECACHE
292: if (((addr & mmu_pagemaski) | regs.s) == atc_last_ins_laddr) {
293: #if CACHE_HIT_COUNT
294: mmu_ins_hit++;
295: #endif
296: addr = atc_last_ins_paddr | (addr & mmu_pagemask);
297: mmu_cache_state = atc_last_ins_cache;
298: } else {
299: #if CACHE_HIT_COUNT
300: mmu_ins_miss++;
301: #endif
302: #endif
303: addr = mmu_translate(addr, 0, regs.s!=0, false, false, size);
304: #if MMU_IPAGECACHE
305: }
306: #endif
1.1.1.4 root 307: }
1.1.1.6 root 308: return x_phys_get_iword(addr);
1.1.1.2 root 309: }
310:
311:
1.1.1.6 root 312: static ALWAYS_INLINE uae_u32 mmu_get_long(uaecptr addr, bool data, int size)
313: {
314: mmu_cache_state = cache_default_data;
315: if ((!mmu_ttr_enabled || mmu_match_ttr(addr,regs.s!=0,data) == TTR_NO_MATCH) && regs.mmu_enabled) {
316: #if MMU_DPAGECACHE
317: uae_u32 idx1 = ((addr & mmu_pagemaski) >> mmu_pageshift1m) | regs.s;
318: uae_u32 idx2 = idx1 & (MMUFASTCACHE_ENTRIES - 1);
319: if (atc_data_cache_read[idx2].log == idx1) {
320: addr = atc_data_cache_read[idx2].phys | (addr & mmu_pagemask);
321: mmu_cache_state = atc_data_cache_read[idx2].cache_state;
322: #if CACHE_HIT_COUNT
323: mmu_data_read_hit++;
324: #endif
325: } else {
326: #if CACHE_HIT_COUNT
327: mmu_data_read_miss++;
328: #endif
329: #endif
330: addr = mmu_translate(addr, 0, regs.s!=0, data, false, size);
331: #if MMU_DPAGECACHE
332: }
333: #endif
1.1.1.4 root 334: }
1.1.1.6 root 335: return x_phys_get_long(addr);
1.1.1.2 root 336: }
337:
1.1.1.6 root 338: static ALWAYS_INLINE uae_u16 mmu_get_word(uaecptr addr, bool data, int size)
1.1.1.2 root 339: {
1.1.1.6 root 340: mmu_cache_state = cache_default_data;
341: if ((!mmu_ttr_enabled || mmu_match_ttr(addr,regs.s!=0,data) == TTR_NO_MATCH) && regs.mmu_enabled) {
342: #if MMU_DPAGECACHE
343: uae_u32 idx1 = ((addr & mmu_pagemaski) >> mmu_pageshift1m) | regs.s;
344: uae_u32 idx2 = idx1 & (MMUFASTCACHE_ENTRIES - 1);
345: if (atc_data_cache_read[idx2].log == idx1) {
346: addr = atc_data_cache_read[idx2].phys | (addr & mmu_pagemask);
347: mmu_cache_state = atc_data_cache_read[idx2].cache_state;
348: #if CACHE_HIT_COUNT
349: mmu_data_read_hit++;
350: #endif
351: } else {
352: #if CACHE_HIT_COUNT
353: mmu_data_read_miss++;
354: #endif
355: #endif
356: addr = mmu_translate(addr, 0, regs.s!=0, data, false, size);
357: #if MMU_DPAGECACHE
358: }
359: #endif
1.1.1.4 root 360: }
1.1.1.6 root 361: return x_phys_get_word(addr);
1.1.1.2 root 362: }
363:
1.1.1.6 root 364: static ALWAYS_INLINE uae_u8 mmu_get_byte(uaecptr addr, bool data, int size)
1.1.1.2 root 365: {
1.1.1.6 root 366: mmu_cache_state = cache_default_data;
367: if ((!mmu_ttr_enabled || mmu_match_ttr(addr,regs.s!=0,data) == TTR_NO_MATCH) && regs.mmu_enabled) {
368: #if MMU_DPAGECACHE
369: uae_u32 idx1 = ((addr & mmu_pagemaski) >> mmu_pageshift1m) | regs.s;
370: uae_u32 idx2 = idx1 & (MMUFASTCACHE_ENTRIES - 1);
371: if (atc_data_cache_read[idx2].log == idx1) {
372: addr = atc_data_cache_read[idx2].phys | (addr & mmu_pagemask);
373: mmu_cache_state = atc_data_cache_read[idx2].cache_state;
374: #if CACHE_HIT_COUNT
375: mmu_data_read_hit++;
376: #endif
377: } else {
378: #if CACHE_HIT_COUNT
379: mmu_data_read_miss++;
380: #endif
381: #endif
382: addr = mmu_translate(addr, 0, regs.s!=0, data, false, size);
383: #if MMU_DPAGECACHE
384: }
385: #endif
1.1.1.2 root 386: }
1.1.1.6 root 387: return x_phys_get_byte(addr);
1.1.1.2 root 388: }
389:
1.1.1.6 root 390: static ALWAYS_INLINE void mmu_put_long(uaecptr addr, uae_u32 val, bool data, int size)
1.1.1.2 root 391: {
1.1.1.6 root 392: mmu_cache_state = cache_default_data;
393: if ((!mmu_ttr_enabled || mmu_match_ttr_write(addr,regs.s!=0,data,val,size) == TTR_NO_MATCH) && regs.mmu_enabled) {
394: #if MMU_DPAGECACHE
395: uae_u32 idx1 = ((addr & mmu_pagemaski) >> mmu_pageshift1m) | regs.s;
396: uae_u32 idx2 = idx1 & (MMUFASTCACHE_ENTRIES - 1);
397: if (atc_data_cache_write[idx2].log == idx1) {
398: addr = atc_data_cache_write[idx2].phys | (addr & mmu_pagemask);
399: mmu_cache_state = atc_data_cache_read[idx2].cache_state;
400: #if CACHE_HIT_COUNT
401: mmu_data_write_hit++;
402: #endif
403: } else {
404: #if CACHE_HIT_COUNT
405: mmu_data_write_miss++;
406: #endif
407: #endif
408: addr = mmu_translate(addr, val, regs.s!=0, data, true, size);
409: #if MMU_DPAGECACHE
410: }
411: #endif
412: }
413: x_phys_put_long(addr, val);
1.1.1.2 root 414: }
415:
1.1.1.6 root 416: static ALWAYS_INLINE void mmu_put_word(uaecptr addr, uae_u16 val, bool data, int size)
1.1.1.2 root 417: {
1.1.1.6 root 418: mmu_cache_state = cache_default_data;
419: if ((!mmu_ttr_enabled || mmu_match_ttr_write(addr,regs.s!=0,data,val,size) == TTR_NO_MATCH) && regs.mmu_enabled) {
420: #if MMU_DPAGECACHE
421: uae_u32 idx1 = ((addr & mmu_pagemaski) >> mmu_pageshift1m) | regs.s;
422: uae_u32 idx2 = idx1 & (MMUFASTCACHE_ENTRIES - 1);
423: if (atc_data_cache_write[idx2].log == idx1) {
424: addr = atc_data_cache_write[idx2].phys | (addr & mmu_pagemask);
425: mmu_cache_state = atc_data_cache_read[idx2].cache_state;
426: #if CACHE_HIT_COUNT
427: mmu_data_write_hit++;
428: #endif
429: } else {
430: #if CACHE_HIT_COUNT
431: mmu_data_write_miss++;
432: #endif
433: #endif
434: addr = mmu_translate(addr, val, regs.s!=0, data, true, size);
435: #if MMU_DPAGECACHE
436: }
437: #endif
1.1.1.4 root 438: }
1.1.1.6 root 439: x_phys_put_word(addr, val);
1.1.1.2 root 440: }
441:
1.1.1.6 root 442: static ALWAYS_INLINE void mmu_put_byte(uaecptr addr, uae_u8 val, bool data, int size)
1.1.1.2 root 443: {
1.1.1.6 root 444: mmu_cache_state = cache_default_data;
445: if ((!mmu_ttr_enabled || mmu_match_ttr_write(addr,regs.s!=0,data,val,size) == TTR_NO_MATCH) && regs.mmu_enabled) {
446: #if MMU_DPAGECACHE
447: uae_u32 idx1 = ((addr & mmu_pagemaski) >> mmu_pageshift1m) | regs.s;
448: uae_u32 idx2 = idx1 & (MMUFASTCACHE_ENTRIES - 1);
449: if (atc_data_cache_write[idx2].log == idx1) {
450: addr = atc_data_cache_write[idx2].phys | (addr & mmu_pagemask);
451: mmu_cache_state = atc_data_cache_read[idx2].cache_state;
452: #if CACHE_HIT_COUNT
453: mmu_data_write_hit++;
454: #endif
455: } else {
456: #if CACHE_HIT_COUNT
457: mmu_data_write_miss++;
458: #endif
459: #endif
460: addr = mmu_translate(addr, val, regs.s!=0, data, true, size);
461: #if MMU_DPAGECACHE
462: }
463: #endif
1.1.1.4 root 464: }
1.1.1.6 root 465: x_phys_put_byte(addr, val);
1.1.1.2 root 466: }
467:
1.1.1.6 root 468: static ALWAYS_INLINE uae_u32 mmu_get_user_long(uaecptr addr, bool super, bool write, int size, bool ci)
1.1.1.2 root 469: {
1.1.1.6 root 470: mmu_cache_state = cache_default_data;
471: if ((!mmu_ttr_enabled || mmu_match_ttr_maybe_write(addr,super,true,size,write) == TTR_NO_MATCH) && regs.mmu_enabled) {
472: #if MMU_DPAGECACHE
473: uae_u32 idx1 = ((addr & mmu_pagemaski) >> mmu_pageshift1m) | (super ? 1 : 0);
474: uae_u32 idx2 = idx1 & (MMUFASTCACHE_ENTRIES - 1);
475: if (atc_data_cache_read[idx2].log == idx1) {
476: addr = atc_data_cache_read[idx2].phys | (addr & mmu_pagemask);
477: mmu_cache_state = atc_data_cache_read[idx2].cache_state;
478: #if CACHE_HIT_COUNT
479: mmu_data_read_hit++;
480: #endif
481: } else {
482: #if CACHE_HIT_COUNT
483: mmu_data_read_miss++;
484: #endif
485: #endif
486: addr = mmu_translate(addr, 0, super, true, write, size);
487: #if MMU_DPAGECACHE
488: }
489: #endif
1.1.1.4 root 490: }
1.1.1.6 root 491: if (ci)
492: mmu_cache_state = CACHE_DISABLE_MMU;
493: return x_phys_get_long(addr);
494: }
495:
496: static ALWAYS_INLINE uae_u16 mmu_get_user_word(uaecptr addr, bool super, bool write, int size, bool ci)
497: {
498: mmu_cache_state = cache_default_data;
499: if ((!mmu_ttr_enabled || mmu_match_ttr_maybe_write(addr,super,true,size,write) == TTR_NO_MATCH) && regs.mmu_enabled) {
500: #if MMU_DPAGECACHE
501: uae_u32 idx1 = ((addr & mmu_pagemaski) >> mmu_pageshift1m) | (super ? 1 : 0);
502: uae_u32 idx2 = idx1 & (MMUFASTCACHE_ENTRIES - 1);
503: if (atc_data_cache_read[idx2].log == idx1) {
504: addr = atc_data_cache_read[idx2].phys | (addr & mmu_pagemask);
505: mmu_cache_state = atc_data_cache_read[idx2].cache_state;
506: #if CACHE_HIT_COUNT
507: mmu_data_read_hit++;
508: #endif
509: } else {
510: #if CACHE_HIT_COUNT
511: mmu_data_read_miss++;
512: #endif
513: #endif
514: addr = mmu_translate(addr, 0, super, true, write, size);
515: #if MMU_DPAGECACHE
516: }
517: #endif
518: }
519: if (ci)
520: mmu_cache_state = CACHE_DISABLE_MMU;
521: return x_phys_get_word(addr);
522: }
523:
524: static ALWAYS_INLINE uae_u8 mmu_get_user_byte(uaecptr addr, bool super, bool write, int size, bool ci)
525: {
526: mmu_cache_state = cache_default_data;
527: if ((!mmu_ttr_enabled || mmu_match_ttr_maybe_write(addr,super,true,size,write) == TTR_NO_MATCH) && regs.mmu_enabled) {
528: #if MMU_DPAGECACHE
529: uae_u32 idx1 = ((addr & mmu_pagemaski) >> mmu_pageshift1m) | (super ? 1 : 0);
530: uae_u32 idx2 = idx1 & (MMUFASTCACHE_ENTRIES - 1);
531: if (atc_data_cache_read[idx2].log == idx1) {
532: addr = atc_data_cache_read[idx2].phys | (addr & mmu_pagemask);
533: mmu_cache_state = atc_data_cache_read[idx2].cache_state;
534: #if CACHE_HIT_COUNT
535: mmu_data_read_hit++;
536: #endif
537: } else {
538: #if CACHE_HIT_COUNT
539: mmu_data_read_miss++;
540: #endif
541: #endif
542: addr = mmu_translate(addr, 0, super, true, write, size);
543: #if MMU_DPAGECACHE
544: }
545: #endif
546: }
547: if (ci)
548: mmu_cache_state = CACHE_DISABLE_MMU;
549: return x_phys_get_byte(addr);
550: }
551:
552: static ALWAYS_INLINE void mmu_put_user_long(uaecptr addr, uae_u32 val, bool super, int size, bool ci)
553: {
554: mmu_cache_state = cache_default_data;
555: if ((!mmu_ttr_enabled || mmu_match_ttr_write(addr,super,true,val,size) == TTR_NO_MATCH) && regs.mmu_enabled) {
556: #if MMU_DPAGECACHE
557: uae_u32 idx1 = ((addr & mmu_pagemaski) >> mmu_pageshift1m) | (super ? 1 : 0);
558: uae_u32 idx2 = idx1 & (MMUFASTCACHE_ENTRIES - 1);
559: if (atc_data_cache_write[idx2].log == idx1) {
560: addr = atc_data_cache_write[idx2].phys | (addr & mmu_pagemask);
561: mmu_cache_state = atc_data_cache_read[idx2].cache_state;
562: #if CACHE_HIT_COUNT
563: mmu_data_write_hit++;
564: #endif
565: } else {
566: #if CACHE_HIT_COUNT
567: mmu_data_write_miss++;
568: #endif
569: #endif
570: addr = mmu_translate(addr, val, super, true, true, size);
571: #if MMU_DPAGECACHE
572: }
573: #endif
574: }
575: if (ci)
576: mmu_cache_state = CACHE_DISABLE_MMU;
577: x_phys_put_long(addr, val);
578: }
579:
580: static ALWAYS_INLINE void mmu_put_user_word(uaecptr addr, uae_u16 val, bool super, int size, bool ci)
581: {
582: mmu_cache_state = cache_default_data;
583: if ((!mmu_ttr_enabled || mmu_match_ttr_write(addr,super,true,val,size) == TTR_NO_MATCH) && regs.mmu_enabled) {
584: #if MMU_DPAGECACHE
585: uae_u32 idx1 = ((addr & mmu_pagemaski) >> mmu_pageshift1m) | (super ? 1 : 0);
586: uae_u32 idx2 = idx1 & (MMUFASTCACHE_ENTRIES - 1);
587: if (atc_data_cache_write[idx2].log == idx1) {
588: addr = atc_data_cache_write[idx2].phys | (addr & mmu_pagemask);
589: mmu_cache_state = atc_data_cache_read[idx2].cache_state;
590: #if CACHE_HIT_COUNT
591: mmu_data_write_hit++;
592: #endif
593: } else {
594: #if CACHE_HIT_COUNT
595: mmu_data_write_miss++;
596: #endif
597: #endif
598: addr = mmu_translate(addr, val, super, true, true, size);
599: #if MMU_DPAGECACHE
600: }
601: #endif
602: }
603: if (ci)
604: mmu_cache_state = CACHE_DISABLE_MMU;
605: x_phys_put_word(addr, val);
606: }
607:
608: static ALWAYS_INLINE void mmu_put_user_byte(uaecptr addr, uae_u8 val, bool super, int size, bool ci)
609: {
610: mmu_cache_state = cache_default_data;
611: if ((!mmu_ttr_enabled || mmu_match_ttr_write(addr,super,true,val,size) == TTR_NO_MATCH) && regs.mmu_enabled) {
612: #if MMU_DPAGECACHE
613: uae_u32 idx1 = ((addr & mmu_pagemaski) >> mmu_pageshift1m) | (super ? 1 : 0);
614: uae_u32 idx2 = idx1 & (MMUFASTCACHE_ENTRIES - 1);
615: if (atc_data_cache_write[idx2].log == idx1) {
616: addr = atc_data_cache_write[idx2].phys | (addr & mmu_pagemask);
617: mmu_cache_state = atc_data_cache_read[idx2].cache_state;
618: #if CACHE_HIT_COUNT
619: mmu_data_write_hit++;
620: #endif
621: } else {
622: #if CACHE_HIT_COUNT
623: mmu_data_write_miss++;
624: #endif
625: #endif
626: addr = mmu_translate(addr, val, super, true, true, size);
627: #if MMU_DPAGECACHE
628: }
629: #endif
630: }
631: if (ci)
632: mmu_cache_state = CACHE_DISABLE_MMU;
633: x_phys_put_byte(addr, val);
1.1.1.2 root 634: }
635:
636:
637: static ALWAYS_INLINE void HWput_l(uaecptr addr, uae_u32 l)
638: {
1.1.1.6 root 639: put_long (addr, l);
1.1.1.2 root 640: }
641: static ALWAYS_INLINE void HWput_w(uaecptr addr, uae_u32 w)
642: {
1.1.1.6 root 643: put_word (addr, w);
1.1.1.2 root 644: }
645: static ALWAYS_INLINE void HWput_b(uaecptr addr, uae_u32 b)
646: {
1.1.1.6 root 647: put_byte (addr, b);
1.1.1.2 root 648: }
649: static ALWAYS_INLINE uae_u32 HWget_l(uaecptr addr)
650: {
1.1.1.6 root 651: return get_long (addr);
1.1.1.2 root 652: }
653: static ALWAYS_INLINE uae_u32 HWget_w(uaecptr addr)
654: {
1.1.1.6 root 655: return get_word (addr);
1.1.1.2 root 656: }
657: static ALWAYS_INLINE uae_u32 HWget_b(uaecptr addr)
658: {
1.1.1.6 root 659: return get_byte (addr);
1.1.1.2 root 660: }
661:
1.1.1.6 root 662: #if MMU_ICACHE
663: #define MMU_ICACHE_SZ 4096
664: struct mmu_icache
1.1.1.2 root 665: {
1.1.1.6 root 666: uae_u16 data;
667: uae_u32 addr;
668: };
669:
670: extern struct mmu_icache mmu_icache_data[MMU_ICACHE_SZ];
671:
672: static ALWAYS_INLINE uae_u16 uae_mmu040_getc_iword(uaecptr addr)
673: {
674: int icidx = (addr & (MMU_ICACHE_SZ - 1)) | regs.s;
675: if (addr != mmu_icache_data[icidx].addr || !(regs.cacr & 0x8000)) {
676: mmu_icache_data[icidx].data = mmu_get_iword(addr, sz_word);
677: mmu_icache_data[icidx].addr = addr;
678: return mmu_icache_data[icidx].data;
679: } else {
680: return mmu_icache_data[icidx].data;
681: }
1.1.1.2 root 682: }
1.1.1.6 root 683: #endif
684:
1.1.1.4 root 685: static ALWAYS_INLINE uae_u16 uae_mmu040_get_iword(uaecptr addr)
686: {
1.1.1.6 root 687: #if MMU_ICACHE
688: return uae_mmu040_getc_iword(addr);
689: #else
1.1.1.4 root 690: return mmu_get_iword(addr, sz_word);
1.1.1.6 root 691: #endif
692: }
693: static ALWAYS_INLINE uae_u32 uae_mmu040_get_ilong(uaecptr addr)
694: {
695: #if MMU_ICACHE
696: uae_u32 result = uae_mmu040_getc_iword(addr);
697: result <<= 16;
698: result |= uae_mmu040_getc_iword(addr + 2);
699: return result;
700: #else
1.1.1.7 ! root 701: if (unlikely(is_unaligned_page(addr, 4)))
1.1.1.6 root 702: return mmu_get_ilong_unaligned(addr);
703: return mmu_get_ilong(addr, sz_long);
704: #endif
1.1.1.4 root 705: }
706: static ALWAYS_INLINE uae_u16 uae_mmu040_get_ibyte(uaecptr addr)
707: {
1.1.1.6 root 708: #if MMU_ICACHE
709: uae_u16 result = uae_mmu040_getc_iword(addr & ~1);
710: return (addr & 1) ? result & 0xFF : result >> 8;
711: #else
712: return mmu_get_byte(addr, false, sz_byte);
713: #endif
1.1.1.4 root 714: }
715: static ALWAYS_INLINE uae_u32 uae_mmu040_get_long(uaecptr addr)
716: {
1.1.1.7 ! root 717: if (unlikely(is_unaligned_page(addr, 4)))
1.1.1.6 root 718: return mmu_get_long_unaligned(addr, true);
719: return mmu_get_long(addr, true, sz_long);
1.1.1.4 root 720: }
721: static ALWAYS_INLINE uae_u16 uae_mmu040_get_word(uaecptr addr)
1.1.1.2 root 722: {
1.1.1.7 ! root 723: if (unlikely(is_unaligned_page(addr, 2)))
1.1.1.6 root 724: return mmu_get_word_unaligned(addr, true);
725: return mmu_get_word(addr, true, sz_word);
1.1.1.2 root 726: }
1.1.1.4 root 727: static ALWAYS_INLINE uae_u8 uae_mmu040_get_byte(uaecptr addr)
1.1.1.2 root 728: {
1.1.1.6 root 729: return mmu_get_byte(addr, true, sz_byte);
1.1.1.2 root 730: }
1.1.1.4 root 731:
732: static ALWAYS_INLINE void uae_mmu040_put_word(uaecptr addr, uae_u16 val)
733: {
1.1.1.7 ! root 734: if (unlikely(is_unaligned_page(addr, 2)))
1.1.1.6 root 735: mmu_put_word_unaligned(addr, val, true);
1.1.1.4 root 736: else
1.1.1.6 root 737: mmu_put_word(addr, val, true, sz_word);
1.1.1.4 root 738: }
739: static ALWAYS_INLINE void uae_mmu040_put_byte(uaecptr addr, uae_u8 val)
740: {
1.1.1.6 root 741: mmu_put_byte(addr, val, true, sz_byte);
1.1.1.4 root 742: }
743: static ALWAYS_INLINE void uae_mmu040_put_long(uaecptr addr, uae_u32 val)
1.1.1.2 root 744: {
1.1.1.7 ! root 745: if (unlikely(is_unaligned_page(addr, 4)))
1.1.1.6 root 746: mmu_put_long_unaligned(addr, val, true);
1.1.1.4 root 747: else
1.1.1.6 root 748: mmu_put_long(addr, val, true, sz_long);
1.1.1.2 root 749: }
1.1.1.4 root 750:
751:
752: static ALWAYS_INLINE uae_u32 uae_mmu060_get_ilong(uaecptr addr)
753: {
1.1.1.7 ! root 754: if (unlikely(is_unaligned_page(addr, 4)))
1.1.1.4 root 755: return mmu_get_ilong_unaligned(addr);
756: return mmu_get_ilong(addr, sz_long);
757: }
758: static ALWAYS_INLINE uae_u16 uae_mmu060_get_iword(uaecptr addr)
759: {
760: return mmu_get_iword(addr, sz_word);
761: }
762: static ALWAYS_INLINE uae_u16 uae_mmu060_get_ibyte(uaecptr addr)
763: {
1.1.1.6 root 764: return mmu_get_byte(addr, false, sz_byte);
1.1.1.4 root 765: }
1.1.1.6 root 766: static ALWAYS_INLINE uae_u32 uae_mmu060_get_long(uaecptr addr)
1.1.1.4 root 767: {
1.1.1.7 ! root 768: if (unlikely(is_unaligned_page(addr, 4)))
1.1.1.6 root 769: return mmu_get_long_unaligned(addr, true);
770: return mmu_get_long(addr, true, sz_long);
1.1.1.4 root 771: }
1.1.1.6 root 772: static ALWAYS_INLINE uae_u16 uae_mmu060_get_word(uaecptr addr)
1.1.1.2 root 773: {
1.1.1.7 ! root 774: if (unlikely(is_unaligned_page(addr, 2)))
1.1.1.6 root 775: return mmu_get_word_unaligned(addr, true);
776: return mmu_get_word(addr, true, sz_word);
1.1.1.4 root 777: }
1.1.1.6 root 778: static ALWAYS_INLINE uae_u8 uae_mmu060_get_byte(uaecptr addr)
1.1.1.4 root 779: {
1.1.1.6 root 780: return mmu_get_byte(addr, true, sz_byte);
1.1.1.2 root 781: }
1.1.1.4 root 782: static ALWAYS_INLINE void uae_mmu_get_move16(uaecptr addr, uae_u32 *val)
1.1.1.2 root 783: {
1.1.1.4 root 784: // move16 is always aligned
785: mmu_get_move16(addr, val, true, 16);
1.1.1.2 root 786: }
1.1.1.4 root 787:
1.1.1.6 root 788: static ALWAYS_INLINE void uae_mmu060_put_long(uaecptr addr, uae_u32 val)
1.1.1.2 root 789: {
1.1.1.7 ! root 790: if (unlikely(is_unaligned_page(addr, 4)))
1.1.1.6 root 791: mmu_put_long_unaligned(addr, val, true);
1.1.1.2 root 792: else
1.1.1.6 root 793: mmu_put_long(addr, val, true, sz_long);
1.1.1.2 root 794: }
1.1.1.6 root 795: static ALWAYS_INLINE void uae_mmu060_put_word(uaecptr addr, uae_u16 val)
1.1.1.2 root 796: {
1.1.1.7 ! root 797: if (unlikely(is_unaligned_page(addr, 2)))
1.1.1.6 root 798: mmu_put_word_unaligned(addr, val, true);
1.1.1.2 root 799: else
1.1.1.6 root 800: mmu_put_word(addr, val, true, sz_word);
1.1.1.4 root 801: }
1.1.1.6 root 802: static ALWAYS_INLINE void uae_mmu060_put_byte(uaecptr addr, uae_u8 val)
1.1.1.4 root 803: {
1.1.1.6 root 804: mmu_put_byte(addr, val, true, sz_byte);
1.1.1.4 root 805: }
806: static ALWAYS_INLINE void uae_mmu_put_move16(uaecptr addr, uae_u32 *val)
807: {
808: // move16 is always aligned
809: mmu_put_move16(addr, val, true, 16);
810: }
811:
812: // normal 040
813: STATIC_INLINE void put_byte_mmu040 (uaecptr addr, uae_u32 v)
814: {
1.1.1.6 root 815: uae_mmu040_put_byte (addr, v);
1.1.1.4 root 816: }
817: STATIC_INLINE void put_word_mmu040 (uaecptr addr, uae_u32 v)
818: {
1.1.1.6 root 819: uae_mmu040_put_word (addr, v);
1.1.1.4 root 820: }
821: STATIC_INLINE void put_long_mmu040 (uaecptr addr, uae_u32 v)
822: {
1.1.1.6 root 823: uae_mmu040_put_long (addr, v);
1.1.1.4 root 824: }
825: STATIC_INLINE uae_u32 get_byte_mmu040 (uaecptr addr)
826: {
1.1.1.6 root 827: return uae_mmu040_get_byte (addr);
1.1.1.4 root 828: }
829: STATIC_INLINE uae_u32 get_word_mmu040 (uaecptr addr)
830: {
1.1.1.6 root 831: return uae_mmu040_get_word (addr);
1.1.1.4 root 832: }
833: STATIC_INLINE uae_u32 get_long_mmu040 (uaecptr addr)
834: {
1.1.1.6 root 835: return uae_mmu040_get_long (addr);
1.1.1.4 root 836: }
837: // normal 060
838: STATIC_INLINE void put_byte_mmu060 (uaecptr addr, uae_u32 v)
839: {
1.1.1.6 root 840: uae_mmu060_put_byte (addr, v);
1.1.1.4 root 841: }
842: STATIC_INLINE void put_word_mmu060 (uaecptr addr, uae_u32 v)
843: {
1.1.1.6 root 844: uae_mmu060_put_word (addr, v);
1.1.1.4 root 845: }
846: STATIC_INLINE void put_long_mmu060 (uaecptr addr, uae_u32 v)
847: {
1.1.1.6 root 848: uae_mmu060_put_long (addr, v);
1.1.1.4 root 849: }
850: STATIC_INLINE uae_u32 get_byte_mmu060 (uaecptr addr)
851: {
1.1.1.6 root 852: return uae_mmu060_get_byte (addr);
1.1.1.2 root 853: }
1.1.1.4 root 854: STATIC_INLINE uae_u32 get_word_mmu060 (uaecptr addr)
1.1.1.2 root 855: {
1.1.1.6 root 856: return uae_mmu060_get_word (addr);
1.1.1.4 root 857: }
858: STATIC_INLINE uae_u32 get_long_mmu060 (uaecptr addr)
859: {
1.1.1.6 root 860: return uae_mmu060_get_long (addr);
1.1.1.2 root 861: }
862:
1.1.1.4 root 863: STATIC_INLINE void get_move16_mmu (uaecptr addr, uae_u32 *v)
1.1.1.2 root 864: {
1.1.1.6 root 865: uae_mmu_get_move16 (addr, v);
1.1.1.2 root 866: }
1.1.1.4 root 867: STATIC_INLINE void put_move16_mmu (uaecptr addr, uae_u32 *v)
1.1.1.2 root 868: {
1.1.1.6 root 869: uae_mmu_put_move16 (addr, v);
1.1.1.2 root 870: }
1.1.1.4 root 871:
872: // locked rmw 060
873: STATIC_INLINE void put_lrmw_byte_mmu060 (uaecptr addr, uae_u32 v)
1.1.1.2 root 874: {
1.1.1.6 root 875: uae_mmu_put_lrmw (addr, v, sz_byte, 1);
1.1.1.2 root 876: }
1.1.1.4 root 877: STATIC_INLINE void put_lrmw_word_mmu060 (uaecptr addr, uae_u32 v)
1.1.1.2 root 878: {
1.1.1.6 root 879: uae_mmu_put_lrmw (addr, v, sz_word, 1);
1.1.1.2 root 880: }
1.1.1.4 root 881: STATIC_INLINE void put_lrmw_long_mmu060 (uaecptr addr, uae_u32 v)
1.1.1.2 root 882: {
1.1.1.6 root 883: uae_mmu_put_lrmw (addr, v, sz_long, 1);
1.1.1.2 root 884: }
1.1.1.4 root 885: STATIC_INLINE uae_u32 get_lrmw_byte_mmu060 (uaecptr addr)
1.1.1.2 root 886: {
1.1.1.6 root 887: return uae_mmu_get_lrmw (addr, sz_byte, 1);
1.1.1.2 root 888: }
1.1.1.4 root 889: STATIC_INLINE uae_u32 get_lrmw_word_mmu060 (uaecptr addr)
890: {
1.1.1.6 root 891: return uae_mmu_get_lrmw (addr, sz_word, 1);
1.1.1.4 root 892: }
893: STATIC_INLINE uae_u32 get_lrmw_long_mmu060 (uaecptr addr)
894: {
1.1.1.6 root 895: return uae_mmu_get_lrmw (addr, sz_long, 1);
1.1.1.4 root 896: }
897: // normal rmw 060
898: STATIC_INLINE void put_rmw_byte_mmu060 (uaecptr addr, uae_u32 v)
899: {
1.1.1.6 root 900: rmw_cycle = true;
901: uae_mmu060_put_byte (addr, v);
902: rmw_cycle = false;
1.1.1.4 root 903: }
904: STATIC_INLINE void put_rmw_word_mmu060 (uaecptr addr, uae_u32 v)
905: {
1.1.1.6 root 906: rmw_cycle = true;
907: uae_mmu060_put_word (addr, v);
908: rmw_cycle = false;
1.1.1.4 root 909: }
910: STATIC_INLINE void put_rmw_long_mmu060 (uaecptr addr, uae_u32 v)
911: {
1.1.1.6 root 912: rmw_cycle = true;
913: uae_mmu060_put_long (addr, v);
914: rmw_cycle = false;
1.1.1.4 root 915: }
916: STATIC_INLINE uae_u32 get_rmw_byte_mmu060 (uaecptr addr)
917: {
1.1.1.6 root 918: rmw_cycle = true;
919: uae_u32 v = uae_mmu060_get_byte (addr);
920: rmw_cycle = false;
921: return v;
1.1.1.4 root 922: }
923: STATIC_INLINE uae_u32 get_rmw_word_mmu060 (uaecptr addr)
924: {
1.1.1.6 root 925: rmw_cycle = true;
926: uae_u32 v = uae_mmu060_get_word (addr);
927: rmw_cycle = false;
928: return v;
1.1.1.4 root 929: }
930: STATIC_INLINE uae_u32 get_rmw_long_mmu060 (uaecptr addr)
931: {
1.1.1.6 root 932: rmw_cycle = true;
933: uae_u32 v = uae_mmu060_get_long (addr);
934: rmw_cycle = false;
935: return v;
1.1.1.4 root 936: }
937: // locked rmw 040
938: STATIC_INLINE void put_lrmw_byte_mmu040 (uaecptr addr, uae_u32 v)
939: {
1.1.1.6 root 940: uae_mmu_put_lrmw (addr, v, sz_byte, 0);
1.1.1.4 root 941: }
942: STATIC_INLINE void put_lrmw_word_mmu040 (uaecptr addr, uae_u32 v)
943: {
1.1.1.6 root 944: uae_mmu_put_lrmw (addr, v, sz_word, 0);
1.1.1.4 root 945: }
946: STATIC_INLINE void put_lrmw_long_mmu040 (uaecptr addr, uae_u32 v)
947: {
1.1.1.6 root 948: uae_mmu_put_lrmw (addr, v, sz_long, 0);
1.1.1.4 root 949: }
950: STATIC_INLINE uae_u32 get_lrmw_byte_mmu040 (uaecptr addr)
951: {
1.1.1.6 root 952: return uae_mmu_get_lrmw (addr, sz_byte, 0);
1.1.1.4 root 953: }
954: STATIC_INLINE uae_u32 get_lrmw_word_mmu040 (uaecptr addr)
955: {
1.1.1.6 root 956: return uae_mmu_get_lrmw (addr, sz_word, 0);
1.1.1.4 root 957: }
958: STATIC_INLINE uae_u32 get_lrmw_long_mmu040 (uaecptr addr)
959: {
1.1.1.6 root 960: return uae_mmu_get_lrmw (addr, sz_long, 0);
1.1.1.4 root 961: }
962:
963: STATIC_INLINE uae_u32 get_ibyte_mmu040 (int o)
964: {
1.1.1.6 root 965: uae_u32 pc = m68k_getpci () + o;
966: return uae_mmu040_get_iword (pc);
1.1.1.4 root 967: }
968: STATIC_INLINE uae_u32 get_iword_mmu040 (int o)
969: {
1.1.1.6 root 970: uae_u32 pc = m68k_getpci () + o;
971: return uae_mmu040_get_iword (pc);
1.1.1.4 root 972: }
973: STATIC_INLINE uae_u32 get_ilong_mmu040 (int o)
974: {
1.1.1.6 root 975: uae_u32 pc = m68k_getpci () + o;
976: return uae_mmu040_get_ilong (pc);
1.1.1.4 root 977: }
978: STATIC_INLINE uae_u32 next_iword_mmu040 (void)
979: {
1.1.1.6 root 980: uae_u32 pc = m68k_getpci ();
981: m68k_incpci (2);
982: return uae_mmu040_get_iword (pc);
1.1.1.4 root 983: }
984: STATIC_INLINE uae_u32 next_ilong_mmu040 (void)
985: {
1.1.1.6 root 986: uae_u32 pc = m68k_getpci ();
987: m68k_incpci (4);
988: return uae_mmu040_get_ilong (pc);
1.1.1.4 root 989: }
990:
991: STATIC_INLINE uae_u32 get_ibyte_mmu060 (int o)
1.1.1.2 root 992: {
1.1.1.6 root 993: uae_u32 pc = m68k_getpci () + o;
994: return uae_mmu060_get_iword (pc);
1.1.1.2 root 995: }
1.1.1.4 root 996: STATIC_INLINE uae_u32 get_iword_mmu060 (int o)
1.1.1.2 root 997: {
1.1.1.6 root 998: uae_u32 pc = m68k_getpci () + o;
999: return uae_mmu060_get_iword (pc);
1.1.1.2 root 1000: }
1.1.1.4 root 1001: STATIC_INLINE uae_u32 get_ilong_mmu060 (int o)
1.1.1.2 root 1002: {
1.1.1.6 root 1003: uae_u32 pc = m68k_getpci () + o;
1004: return uae_mmu060_get_ilong (pc);
1.1.1.2 root 1005: }
1.1.1.4 root 1006: STATIC_INLINE uae_u32 next_iword_mmu060 (void)
1.1.1.2 root 1007: {
1.1.1.6 root 1008: uae_u32 pc = m68k_getpci ();
1009: m68k_incpci (2);
1010: return uae_mmu060_get_iword (pc);
1.1.1.2 root 1011: }
1.1.1.4 root 1012: STATIC_INLINE uae_u32 next_ilong_mmu060 (void)
1.1.1.2 root 1013: {
1.1.1.6 root 1014: uae_u32 pc = m68k_getpci ();
1015: m68k_incpci (4);
1016: return uae_mmu060_get_ilong (pc);
1.1.1.2 root 1017: }
1018:
1.1.1.4 root 1019: extern void flush_mmu040 (uaecptr, int);
1020: extern void m68k_do_rts_mmu040 (void);
1021: extern void m68k_do_rte_mmu040 (uaecptr a7);
1022: extern void m68k_do_bsr_mmu040 (uaecptr oldpc, uae_s32 offset);
1023:
1024: extern void flush_mmu060 (uaecptr, int);
1025: extern void m68k_do_rts_mmu060 (void);
1026: extern void m68k_do_rte_mmu060 (uaecptr a7);
1027: extern void m68k_do_bsr_mmu060 (uaecptr oldpc, uae_s32 offset);
1.1.1.2 root 1028:
1.1.1.5 root 1029: #endif /* UAE_CPUMMU_H */
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