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1.1 root 1: /*
2: * UAE - The Un*x Amiga Emulator
3: *
4: * MC68000 emulation generator
5: *
6: * This is a fairly stupid program that generates a lot of case labels that
7: * can be #included in a switch statement.
8: * As an alternative, it can generate functions that handle specific
9: * MC68000 instructions, plus a prototype header file and a function pointer
10: * array to look up the function for an opcode.
11: * Error checking is bad, an illegal table68k file will cause the program to
12: * call abort().
13: * The generated code is sometimes sub-optimal, an optimizing compiler should
14: * take care of this.
15: *
16: * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
17: *
18: * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
19: */
20:
21: #include "sysconfig.h"
22: #include "sysdeps.h"
23: #include <ctype.h>
24: #include <string.h>
25:
26: #include "readcpu.h"
1.1.1.2 ! root 27: #include "falcon_cycle030.h"
1.1 root 28:
29: #define BOOL_TYPE "int"
30: /* Define the minimal 680x0 where NV flags are not affected by xBCD instructions. */
31: #define xBCD_KEEPS_NV_FLAGS 4
32:
33: static FILE *headerfile;
34: static FILE *stblfile;
35:
36: static int using_prefetch, using_indirect, using_mmu;
37: static int using_ce020;
38: static int using_exception_3;
39: static int using_ce;
40: static int cpu_level;
41: static int count_read, count_write, count_cycles, count_ncycles;
42: static int count_read_ea, count_write_ea, count_cycles_ea;
43:
44: static int optimized_flags;
45:
1.1.1.2 ! root 46: long nCurInstrCycPos; /* Hatari only : Stores where we have to patch in the current cycles value */
! 47:
1.1 root 48: #define GF_APDI 1
49: #define GF_AD8R 2
50: #define GF_PC8R 4
51: #define GF_AA 7
52: #define GF_NOREFILL 8
53: #define GF_PREFETCH 16
54: #define GF_FC 32
55: #define GF_MOVE 64
56:
57: /* For the current opcode, the next lower level that will have different code.
58: * Initialized to -1 for each opcode. If it remains unchanged, indicates we
59: * are done with that opcode. */
60: static int next_cpu_level;
61:
62: static int *opcode_map;
63: static int *opcode_next_clev;
64: static int *opcode_last_postfix;
65: static unsigned long *counts;
66: static int generate_stbl;
67: static int fixupcnt;
68:
1.1.1.2 ! root 69: static int instr_index = 0; /* Hatari: Added to give a unique index to each 68030 cycle exact instruction (CPU_EMU_21) */
! 70: static int instr_table; /* Hatari: Used to know which cycle table to use (CPU_EMU_21) */
! 71: static int instr_table_index; /* Hatari: Used when the cycle table is not the generic one to set the line of the table (CPU_EMU_21) */
! 72:
! 73: /* used to disable the return cycles function call when there are more than one cycle to take into account for an instruction */
! 74: /* Falcon CPU only (CPUEMU_21)) */
! 75: static bool no_return_cycles;
! 76:
! 77: /* All the following indexes are useful to get the correct cycle index in the cycle tables for 68030 cycle exact CPU (CPU_21) */
! 78: /* Hatari only code */
! 79: static int chk_w_index = 0;
! 80: static int chk_l_index = 0;
! 81: static int chk2_b_index = 0;
! 82: static int chk2_w_index = 0;
! 83: static int chk2_l_index = 0;
! 84: static int cas_b_index = 0;
! 85: static int cas_w_index = 0;
! 86: static int cas_l_index = 0;
! 87:
! 88: /* These defines describe the different tables used for 68030 Cycle exact (Hatari only) */
! 89: #define TABLE_FALCON_CYCLES 0
! 90: #define TABLE_FALCON_CYCLES_CHK2_BW 1
! 91: #define TABLE_FALCON_CYCLES_CHK2_L 2
! 92: #define TABLE_FALCON_CYCLES_CHK_L 3
! 93: #define TABLE_FALCON_CYCLES_CHK_W 4
! 94: #define TABLE_FALCON_CYCLES_CAS_BW 5
! 95: #define TABLE_FALCON_CYCLES_CAS_L 6
! 96: #define TABLE_FALCON_CYCLES_CAS2_W 7
! 97: #define TABLE_FALCON_CYCLES_CAS2_L 8
! 98: #define TABLE_FALCON_CYCLES_RTE 9
! 99: #define TABLE_FALCON_CYCLES_BCC 10
! 100: #define TABLE_FALCON_CYCLES_DBCC 11
! 101: #define TABLE_FALCON_CYCLES_TRAPCC 12
! 102: #define TABLE_FALCON_CYCLES_TRAPCC_W 13
! 103: #define TABLE_FALCON_CYCLES_TRAPCC_L 14
! 104: #define TABLE_FALCON_CYCLES_TRAPV 15
! 105: #define TABLE_FALCON_CYCLES_DIVU_L 16
! 106: #define TABLE_FALCON_CYCLES_DIVS_L 17
! 107: #define TABLE_FALCON_CYCLES_BFTST_MEM 18
! 108: #define TABLE_FALCON_CYCLES_BFEXTU_MEM 19
! 109: #define TABLE_FALCON_CYCLES_BFCHG_MEM 20
! 110: #define TABLE_FALCON_CYCLES_BFEXTS_MEM 21
! 111: #define TABLE_FALCON_CYCLES_BFCLR_MEM 22
! 112: #define TABLE_FALCON_CYCLES_BFFFO_MEM 23
! 113: #define TABLE_FALCON_CYCLES_BFSET_MEM 24
! 114: #define TABLE_FALCON_CYCLES_BFINS_MEM 25
! 115: #define TABLE_FALCON_CYCLES_LSD 26
! 116: #define TABLE_FALCON_CYCLES_ASR 27
! 117: #define TABLE_FALCON_CYCLES_MOVEC 28
! 118: #define TABLE_FALCON_CYCLES_MOVES_EA_RN 29
! 119: #define TABLE_FALCON_CYCLES_MOVES_RN_EA 30
! 120: #define TABLE_FALCON_CYCLES_68030_INTERNAL 31
! 121:
! 122:
1.1 root 123: #define GENA_GETV_NO_FETCH 0
124: #define GENA_GETV_FETCH 1
125: #define GENA_GETV_FETCH_ALIGN 2
126: #define GENA_MOVEM_DO_INC 0
127: #define GENA_MOVEM_NO_INC 1
128: #define GENA_MOVEM_MOVE16 2
129:
1.1.1.2 ! root 130: /**
! 131: Table_labels table for all case.
! 132: */
! 133: static const char* falcon_cycles_tables[] = {
! 134: "table_falcon_cycles",
! 135: "table_falcon_cycles_CHK2_BW",
! 136: "table_falcon_cycles_CHK2_L",
! 137: "table_falcon_cycles_CHK_L",
! 138: "table_falcon_cycles_CHK_W",
! 139: "table_falcon_cycles_CAS_BW",
! 140: "table_falcon_cycles_CAS_L",
! 141: "table_falcon_cycles_CAS2_W",
! 142: "table_falcon_cycles_CAS2_L",
! 143: "table_falcon_cycles_RTE",
! 144: "table_falcon_cycles_Bcc",
! 145: "table_falcon_cycles_DBcc",
! 146: "table_falcon_cycles_TRAPcc",
! 147: "table_falcon_cycles_TRAPcc_W",
! 148: "table_falcon_cycles_TRAPcc_L",
! 149: "table_falcon_cycles_TRAPV",
! 150: "table_falcon_cycles_DIVU_L",
! 151: "table_falcon_cycles_DIVS_L",
! 152: "table_falcon_cycles_BFTST_Mem",
! 153: "table_falcon_cycles_BFEXTU_Mem",
! 154: "table_falcon_cycles_BFCHG_Mem",
! 155: "table_falcon_cycles_BFEXTS_Mem",
! 156: "table_falcon_cycles_BFCLR_Mem",
! 157: "table_falcon_cycles_BFFFO_Mem",
! 158: "table_falcon_cycles_BFSET_Mem",
! 159: "table_falcon_cycles_BFINS_Mem",
! 160: "table_falcon_cycles_LSD",
! 161: "table_falcon_cycles_ASR",
! 162: "table_falcon_cycles_MOVEC",
! 163: "table_falcon_cycles_MOVES_EA_RN",
! 164: "table_falcon_cycles_MOVES_RN_EA",
! 165: "table_falcon_cycles_68030_internal"
! 166: };
! 167:
1.1 root 168: static void read_counts (void)
169: {
170: FILE *file;
171: unsigned long opcode, count, total;
172: char name[20];
173: int nr = 0;
174: int ret;
175: memset (counts, 0, 65536 * sizeof *counts);
176:
177: count = 0;
178: file = fopen ("frequent.68k", "r");
179: if (file) {
180: ret = fscanf (file, "Total: %lu\n", &total);
181: while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
182: opcode_next_clev[nr] = 5;
183: opcode_last_postfix[nr] = -1;
184: opcode_map[nr++] = opcode;
185: counts[opcode] = count;
186: }
187: fclose (file);
188: }
189: if (nr == nr_cpuop_funcs)
190: return;
191: for (opcode = 0; opcode < 0x10000; opcode++) {
192: if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
193: && counts[opcode] == 0)
194: {
195: opcode_next_clev[nr] = 5;
196: opcode_last_postfix[nr] = -1;
197: opcode_map[nr++] = opcode;
198: counts[opcode] = count;
199: }
200: }
201: if (nr != nr_cpuop_funcs)
202: abort ();
203: }
204:
205: static char endlabelstr[80];
206: static int endlabelno = 0;
207: static int need_endlabel;
208:
209: static int n_braces, limit_braces;
210: static int m68k_pc_offset;
211: static int insn_n_cycles, insn_n_cycles020;
212:
213: static void fpulimit (void)
214: {
215: if (limit_braces)
216: return;
217: printf ("\n#ifdef FPUEMU\n");
218: limit_braces = n_braces;
219: n_braces = 0;
220: }
221: static void cpulimit (void)
222: {
223: printf ("#ifndef CPUEMU_68000_ONLY\n");
224: }
225:
226: static void returncycles (const char *s, int cycles)
227: {
228: if (using_ce)
229: return;
1.1.1.2 ! root 230:
! 231: if (using_ce020 == 1)
1.1 root 232: printf ("%sreturn;\n", s);
1.1.1.2 ! root 233: else if (using_ce020 == 2) {
! 234: if (no_return_cycles == true)
! 235: return;
! 236: // TODO: This first if statement should be removed when all the cycles are correctly generated for the Falcon 68030 CPU
! 237: // The next "else" should be removed too and only the printf line should be keept.
! 238: if (instr_table == TABLE_FALCON_CYCLES && table_falcon_cycles[instr_index].cache_cycles == 0) {
! 239: // set a temporary false value for this instruction cycles timing.
! 240: printf ("\tregs.ce030_instr_cycles = table_falcon_cycles[0];\n");
! 241: }
! 242: else {
! 243: printf ("%s\tregs.ce030_instr_cycles = %s[%d];\n", s, falcon_cycles_tables[instr_table], instr_table_index);
! 244: }
! 245:
! 246: printf ("%s\treturn;\n", s);
! 247: }
1.1 root 248: else
249: printf ("%sreturn %d * CYCLE_UNIT / 2;\n", s, cycles);
250: }
251:
1.1.1.2 ! root 252: /* Todo : remove this function when all Falcon cycles are coded */
! 253: static void addcycles_ce020 (int head, int tail, int cache_cycles, int noncache_cycles)
1.1 root 254: {
255: if (!using_ce020)
256: return;
1.1.1.2 ! root 257: if (cache_cycles > 0 && noncache_cycles > 0) {
! 258: //not needed anymore
! 259: }
! 260: count_cycles += noncache_cycles;
1.1 root 261: }
1.1.1.2 ! root 262:
1.1 root 263: static void addcycles000 (int cycles)
264: {
265: if (!using_ce)
266: return;
267: printf ("\tdo_cycles_ce000 (%d);\n", cycles);
268: count_cycles += cycles;
269: }
270: static void addcycles000_2 (const char *s, int cycles)
271: {
272: if (!using_ce)
273: return;
274: printf ("%sdo_cycles_ce000 (%d);\n", s, cycles);
275: count_cycles += cycles;
276: }
277:
278: static void addcycles000_3 (const char *s)
279: {
280: if (!using_ce)
281: return;
282: printf ("%sif (cycles > 0) do_cycles_ce000 (cycles);\n", s);
283: count_ncycles++;
284: }
285:
286: static int isreg (amodes mode)
287: {
288: if (mode == Dreg || mode == Areg)
289: return 1;
290: return 0;
291: }
292:
293: static void start_brace (void)
294: {
295: n_braces++;
296: printf ("{");
297: }
298:
299: static void close_brace (void)
300: {
301: assert (n_braces > 0);
302: n_braces--;
303: printf ("}");
304: }
305:
306: static void finish_braces (void)
307: {
308: while (n_braces > 0)
309: close_brace ();
310: }
311:
312: static void pop_braces (int to)
313: {
314: while (n_braces > to)
315: close_brace ();
316: }
317:
318: static int bit_size (int size)
319: {
320: switch (size) {
321: case sz_byte: return 8;
322: case sz_word: return 16;
323: case sz_long: return 32;
324: default: abort ();
325: }
326: return 0;
327: }
328:
329: static const char *bit_mask (int size)
330: {
331: switch (size) {
332: case sz_byte: return "0xff";
333: case sz_word: return "0xffff";
334: case sz_long: return "0xffffffff";
335: default: abort ();
336: }
337: return 0;
338: }
339:
340: static const char *srcl, *dstl;
341: static const char *srcw, *dstw;
342: static const char *srcb, *dstb;
343: static const char *ce020_prefetch_long;
344: static const char *ce020_prefetch_word;
345:
346: static void gen_nextilong (const char *type, const char *name, int flags)
347: {
348: int r = m68k_pc_offset;
349: m68k_pc_offset += 4;
350:
351: if (using_ce020) {
352: printf ("\t%s %s = %s (%d);\n", type, name, ce020_prefetch_long, r);
353: count_read += 2;
354: } else if (using_ce) {
355: printf ("\t%s %s;\n", type, name);
356: /* we must do this because execution order of (something | something2) is not defined */
357: if (flags & GF_NOREFILL) {
358: printf ("\t%s = get_word_ce_prefetch (%d) << 16;\n", name, r + 2);
359: count_read++;
360: printf ("\t%s |= regs.irc;\n", name);
361: } else {
362: printf ("\t%s = get_word_ce_prefetch (%d) << 16;\n", name, r + 2);
363: count_read++;
364: printf ("\t%s |= get_word_ce_prefetch (%d);\n", name, r + 4);
365: count_read++;
366: }
367: } else {
368: if (using_prefetch) {
369: if (flags & GF_NOREFILL) {
370: printf ("\t%s %s;\n", type, name);
371: printf ("\t%s = get_word_prefetch (%d) << 16;\n", name, r + 2);
372: count_read++;
373: printf ("\t%s |= regs.irc;\n", name);
374: insn_n_cycles += 4;
375: } else {
376: printf ("\t%s %s = get_long_prefetch (%d);\n", type, name, r + 2);
377: count_read++;
378: count_read++;
379: insn_n_cycles += 8;
380: }
381: } else if (using_indirect) {
382: insn_n_cycles += 8;
383: printf ("\t%s %s = get_ilongi (%d);\n", type, name, r);
384: } else if (using_mmu) {
385: insn_n_cycles += 8;
386: printf ("\t%s %s = get_ilong_mmu (%d);\n", type, name, r);
387: } else {
388: insn_n_cycles += 8;
389: printf ("\t%s %s = get_ilong (%d);\n", type, name, r);
390: }
391: }
392: }
393:
394: static const char *gen_nextiword (int flags)
395: {
396: static char buffer[80];
397: int r = m68k_pc_offset;
398: m68k_pc_offset += 2;
399:
400: if (using_ce020) {
401: sprintf (buffer, "%s (%d)", ce020_prefetch_word, r);
402: count_read++;
403: } else if (using_ce) {
404: if (flags & GF_NOREFILL) {
405: strcpy (buffer, "regs.irc");
406: } else {
407: sprintf (buffer, "get_word_ce_prefetch (%d)", r + 2);
408: count_read++;
409: }
410: } else {
411: if (using_prefetch) {
412: if (flags & GF_NOREFILL) {
413: sprintf (buffer, "regs.irc"/*, r*/);
414: } else {
415: sprintf (buffer, "get_word_prefetch (%d)", r + 2);
416: count_read++;
417: insn_n_cycles += 4;
418: }
419: } else if (using_indirect) {
420: sprintf (buffer, "get_iwordi(%d)", r);
421: insn_n_cycles += 4;
422: } else if (using_mmu) {
423: sprintf (buffer, "get_iword_mmu (%d)", r);
424: insn_n_cycles += 4;
425: } else {
426: sprintf (buffer, "get_iword (%d)", r);
427: insn_n_cycles += 4;
428: }
429: }
430: return buffer;
431: }
432:
433: static const char *gen_nextibyte (int flags)
434: {
435: static char buffer[80];
436: int r = m68k_pc_offset;
437: m68k_pc_offset += 2;
438:
439: if (using_ce020) {
440: sprintf (buffer, "(uae_u8)%s (%d)", ce020_prefetch_word, r);
441: count_read++;
442: } else if (using_ce) {
443: if (flags & GF_NOREFILL) {
444: strcpy (buffer, "(uae_u8)regs.irc");
445: } else {
446: sprintf (buffer, "(uae_u8)get_word_ce_prefetch (%d)", r + 2);
447: count_read++;
448: }
449: } else {
450: insn_n_cycles += 4;
451: if (using_prefetch) {
452: if (flags & GF_NOREFILL) {
453: sprintf (buffer, "(uae_u8)regs.irc"/*, r*/);
454: } else {
455: sprintf (buffer, "(uae_u8)get_word_prefetch (%d)", r + 2);
456: insn_n_cycles += 4;
457: count_read++;
458: }
459: } else if (using_indirect) {
460: sprintf (buffer, "get_ibytei (%d)", r);
461: insn_n_cycles += 4;
462: } else if (using_mmu) {
463: sprintf (buffer, "get_ibyte_mmu (%d)", r);
464: insn_n_cycles += 4;
465: } else {
466: sprintf (buffer, "get_ibyte (%d)", r);
467: insn_n_cycles += 4;
468: }
469: }
470: return buffer;
471: }
472:
473: static void irc2ir (void)
474: {
475: if (!using_prefetch)
476: return;
477: printf ("\tregs.ir = regs.irc;\n");
478: if (using_ce)
479: printf ("\tipl_fetch ();\n");
480: }
481:
482: static int did_prefetch;
483:
484: static void fill_prefetch_2 (void)
485: {
486: if (!using_prefetch)
487: return;
488: if (using_ce)
489: printf ("\tget_word_ce_prefetch (%d);\n", m68k_pc_offset + 2);
490: else
491: printf ("\tget_word_prefetch (%d);\n", m68k_pc_offset + 2);
492: did_prefetch = 1;
493: count_read++;
494: insn_n_cycles += 4;
495: }
496:
497: static void fill_prefetch_1 (int o)
498: {
499: if (!using_prefetch)
500: return;
501: if (using_ce) {
502: printf ("\tget_word_ce_prefetch (%d);\n", o);
503: } else {
504: printf ("\tget_word_prefetch (%d);\n", o);
505: }
506: did_prefetch = 1;
507: count_read++;
508: insn_n_cycles += 4;
509: }
510:
511: static void fill_prefetch_full (void)
512: {
513: fill_prefetch_1 (0);
514: irc2ir ();
515: fill_prefetch_1 (2);
516: }
517:
518: static void fill_prefetch_0 (void)
519: {
520: if (!using_prefetch)
521: return;
522: if (using_ce)
523: printf ("\tget_word_ce_prefetch (0);\n");
524: else
525: printf ("\tget_word_prefetch (0);\n");
526: did_prefetch = 1;
527: count_read++;
528: insn_n_cycles += 4;
529: }
530:
531: static void dummy_prefetch (void)
532: {
533: int o = m68k_pc_offset + 2;
534: if (!using_prefetch)
535: return;
536: if (using_ce) {
537: printf ("\tget_wordi_ce (m68k_getpc () + %d);\n", o);
538: } else {
539: printf ("\tget_wordi (m68k_getpc () + %d);\n", o);
540: }
541: count_read++;
542: insn_n_cycles += 4;
543: }
544:
545: static void fill_prefetch_next_1 (void)
546: {
547: irc2ir ();
548: fill_prefetch_1 (m68k_pc_offset + 2);
549: }
550:
551: static void fill_prefetch_next (void)
552: {
553: fill_prefetch_next_1 ();
554: }
555:
556: #if 0
557: static void fill_prefetch_next_delay (int extracycles)
558: {
559: if (!using_prefetch)
560: return;
561: if (using_ce) {
562: if (extracycles > 0) {
563: printf("\t{\n");
564: fill_prefetch_next ();
565: printf("\tif (%d > 0) do_cycles(%d * CYCLE_UNIT / 2);\n",
566: extracycles, extracycles);
567: printf("\t}\n");
568: } else {
569: fill_prefetch_next ();
570: }
571: } else {
572: fill_prefetch_next ();
573: }
574: }
575: #endif
576:
577: static void fill_prefetch_finish (void)
578: {
579: if (did_prefetch || !using_prefetch)
580: return;
581: fill_prefetch_1 (m68k_pc_offset);
582: }
583:
584: static void setpc (const char *format, ...)
585: {
586: va_list parms;
587: char buffer[1000];
588:
589: va_start (parms, format);
590: _vsnprintf (buffer, 1000 - 1, format, parms);
591: va_end (parms);
592:
593: if (using_mmu)
594: printf ("\tm68k_setpc_mmu (%s);\n", buffer);
595: else
596: printf ("\tm68k_setpc (%s);\n", buffer);
597: }
598:
599: static void incpc (const char *format, ...)
600: {
601: va_list parms;
602: char buffer[1000];
603:
604: va_start (parms, format);
605: _vsnprintf (buffer, 1000 - 1, format, parms);
606: va_end (parms);
607:
608: if (using_mmu)
609: printf ("\tm68k_incpci (%s);\n", buffer);
610: else
611: printf ("\tm68k_incpc (%s);\n", buffer);
612: }
613:
614: static void sync_m68k_pc (void)
615: {
616: if (m68k_pc_offset == 0)
617: return;
618: incpc ("%d", m68k_pc_offset);
619: m68k_pc_offset = 0;
620: }
621:
622: static void gen_set_fault_pc (void)
623: {
624: if (!using_mmu)
625: return;
626: sync_m68k_pc ();
627: printf ("\tregs.fault_pc = m68k_getpci ();\n");
628: m68k_pc_offset = 0;
629: }
630:
631: static void syncmovepc (int getv, int flags)
632: {
633: #if 0
634: if (!(flags & GF_MOVE))
635: return;
636: if (getv == 1) {
637: sync_m68k_pc ();
638: //fill_prefetch_next ();
639: }
640: #endif
641: }
642:
643: /* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
644: * the calling routine handles Apdi and Aipi modes.
645: * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
646:
647: /* fixup indicates if we want to fix up adress registers in pre decrement
648: * or post increment mode now (0) or later (1). A value of 2 will then be
649: * used to do the actual fix up. This allows to do all memory readings
650: * before any register is modified, and so to rerun operation without
651: * side effect in case a bus fault is generated by any memory access.
652: * XJ - 2006/11/13 */
653:
654: static void genamode2 (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags, int fixup)
655: {
656: char namea[100];
657: int m68k_pc_offset_last = m68k_pc_offset;
658:
659: sprintf (namea, "%sa", name);
660:
661: start_brace ();
662: switch (mode) {
663: case Dreg:
664: if (movem)
665: abort ();
666: if (getv == 1)
667: switch (size) {
668: case sz_byte:
669: #ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
670: /* This causes the target compiler to generate better code on few systems */
671: printf ("\tuae_s8 %s = ((uae_u8*)&m68k_dreg (regs, %s))[3];\n", name, reg);
672: #else
673: printf ("\tuae_s8 %s = m68k_dreg (regs, %s);\n", name, reg);
674: #endif
675: break;
676: case sz_word:
677: #ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
678: printf ("\tuae_s16 %s = ((uae_s16*)&m68k_dreg (regs, %s))[1];\n", name, reg);
679: #else
680: printf ("\tuae_s16 %s = m68k_dreg (regs, %s);\n", name, reg);
681: #endif
682: break;
683: case sz_long:
684: printf ("\tuae_s32 %s = m68k_dreg (regs, %s);\n", name, reg);
685: break;
686: default:
687: abort ();
688: }
689: syncmovepc (getv, flags);
690: return;
691: case Areg:
692: if (movem)
693: abort ();
694: if (getv == 1)
695: switch (size) {
696: case sz_word:
697: printf ("\tuae_s16 %s = m68k_areg (regs, %s);\n", name, reg);
698: break;
699: case sz_long:
700: printf ("\tuae_s32 %s = m68k_areg (regs, %s);\n", name, reg);
701: break;
702: default:
703: abort ();
704: }
705: syncmovepc (getv, flags);
706: return;
707: case Aind: // (An)
708: printf ("\tuaecptr %sa = m68k_areg (regs, %s);\n", name, reg);
709: break;
710: case Aipi: // (An)+
711: printf ("\tuaecptr %sa = m68k_areg (regs, %s);\n", name, reg);
712: break;
713: case Apdi: // -(An)
714: printf ("\tuaecptr %sa;\n", name);
715: switch (size) {
716: case sz_byte:
717: if (movem)
718: printf ("\t%sa = m68k_areg (regs, %s);\n", name, reg);
719: else
720: printf ("\t%sa = m68k_areg (regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
721: break;
722: case sz_word:
723: printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
724: break;
725: case sz_long:
726: printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
727: break;
728: default:
729: abort ();
730: }
731: if (!(flags & GF_APDI)) {
732: addcycles000 (2);
733: insn_n_cycles += 2;
734: count_cycles_ea += 2;
735: }
736: break;
737: case Ad16: // (d16,An)
738: printf ("\tuaecptr %sa = m68k_areg (regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword (flags));
739: count_read_ea++;
740: break;
741: case Ad8r: // (d8,An,Xn)
742: printf ("\tuaecptr %sa;\n", name);
743: if (cpu_level > 1) {
744: if (next_cpu_level < 1)
745: next_cpu_level = 1;
746: sync_m68k_pc ();
747: start_brace ();
748: /* This would ordinarily be done in gen_nextiword, which we bypass. */
749: insn_n_cycles += 4;
750: if (using_ce020 || using_mmu)
751: printf ("\t%sa = x_get_disp_ea_020 (m68k_areg (regs, %s), x_next_iword ());\n", name, reg);
752: else
753: printf ("\t%sa = get_disp_ea_020 (m68k_areg (regs, %s), next_iword ());\n", name, reg);
754: } else {
755: if (!(flags & GF_AD8R)) {
756: addcycles000 (2);
757: insn_n_cycles += 2;
758: count_cycles_ea += 2;
759: }
760: printf ("\t%sa = get_disp_ea_000 (m68k_areg (regs, %s), %s);\n", name, reg, gen_nextiword (flags));
761: count_read_ea++;
762: }
763: break;
764: case PC16: // (d16,PC,Xn)
765: printf ("\tuaecptr %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset);
766: printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
767: break;
768: case PC8r: // (d8,PC,Xn)
769: printf ("\tuaecptr tmppc;\n");
770: printf ("\tuaecptr %sa;\n", name);
771: if (cpu_level > 1) {
772: if (next_cpu_level < 1)
773: next_cpu_level = 1;
774: sync_m68k_pc ();
775: start_brace ();
776: /* This would ordinarily be done in gen_nextiword, which we bypass. */
777: insn_n_cycles += 4;
778: printf ("\ttmppc = m68k_getpc ();\n");
779: if (using_ce020 || using_mmu)
780: printf ("\t%sa = x_get_disp_ea_020 (tmppc, x_next_iword ());\n", name);
781: else
782: printf ("\t%sa = get_disp_ea_020 (tmppc, next_iword ());\n", name);
783: } else {
784: printf ("\ttmppc = m68k_getpc () + %d;\n", m68k_pc_offset);
785: if (!(flags & GF_PC8R)) {
786: addcycles000 (2);
787: insn_n_cycles += 2;
788: count_cycles_ea += 2;
789: }
790: printf ("\t%sa = get_disp_ea_000 (tmppc, %s);\n", name, gen_nextiword (flags));
791: }
792:
793: break;
794: case absw:
795: printf ("\tuaecptr %sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
796: break;
797: case absl:
798: gen_nextilong ("uaecptr", namea, flags);
799: count_read_ea += 2;
800: break;
801: case imm:
802: if (getv != 1)
803: abort ();
804: insn_n_cycles020++;
805: switch (size) {
806: case sz_byte:
807: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
808: count_read_ea++;
809: break;
810: case sz_word:
811: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
812: count_read_ea++;
813: break;
814: case sz_long:
815: gen_nextilong ("uae_s32", name, flags);
816: count_read_ea += 2;
817: break;
818: default:
819: abort ();
820: }
821: syncmovepc (getv, flags);
822: return;
823: case imm0:
824: if (getv != 1)
825: abort ();
826: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
827: count_read_ea++;
828: syncmovepc (getv, flags);
829: return;
830: case imm1:
831: if (getv != 1)
832: abort ();
833: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
834: count_read_ea++;
835: syncmovepc (getv, flags);
836: return;
837: case imm2:
838: if (getv != 1)
839: abort ();
840: gen_nextilong ("uae_s32", name, flags);
841: count_read_ea += 2;
842: syncmovepc (getv, flags);
843: return;
844: case immi:
845: if (getv != 1)
846: abort ();
847: printf ("\tuae_u32 %s = %s;\n", name, reg);
848: syncmovepc (getv, flags);
849: return;
850: default:
851: abort ();
852: }
853:
854: syncmovepc (getv, flags);
855:
856: /* We get here for all non-reg non-immediate addressing modes to
857: * actually fetch the value. */
858:
859: if ((using_prefetch || using_ce) && using_exception_3 && getv != 0 && size != sz_byte) {
860: int offset = 0;
861: if (flags & GF_MOVE) {
862: offset = m68k_pc_offset;
863: if (getv == 2)
864: offset += 2;
865: } else {
866: offset = m68k_pc_offset_last;
867: }
868: printf ("\tif (%sa & 1) {\n", name);
869: printf ("\t\texception3 (opcode, m68k_getpc () + %d, %sa);\n",
870: offset, name);
871: printf ("\t\tgoto %s;\n", endlabelstr);
872: printf ("\t}\n");
873: need_endlabel = 1;
874: start_brace ();
875: }
876:
877: if (flags & GF_PREFETCH)
878: fill_prefetch_next ();
879:
880: if (getv == 1) {
881: start_brace ();
882: if (using_ce020) {
883: switch (size) {
884: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, srcb, name); count_read++; break;
885: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, srcw, name); count_read++; break;
886: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = %s (%sa);\n", name, srcl, name); count_read += 2; break;
887: default: abort ();
888: }
889: } else if (using_ce) {
890: switch (size) {
891: case sz_byte: printf ("\tuae_s8 %s = get_byte_ce (%sa);\n", name, name); count_read++; break;
892: case sz_word: printf ("\tuae_s16 %s = get_word_ce (%sa);\n", name, name); count_read++; break;
893: case sz_long: printf ("\tuae_s32 %s = get_word_ce (%sa) << 16; %s |= get_word_ce (%sa + 2);\n", name, name, name, name); count_read += 2; break;
894: default: abort ();
895: }
896: } else if (using_mmu) {
897: if (flags & GF_FC) {
898: switch (size) {
899: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = sfc_get_byte (%sa);\n", name, name); break;
900: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = sfc_get_word (%sa);\n", name, name); break;
901: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = sfc_get_long (%sa);\n", name, name); break;
902: default: abort ();
903: }
904: } else {
905: switch (size) {
906: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = get_byte_mmu (%sa);\n", name, name); break;
907: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = get_word_mmu (%sa);\n", name, name); break;
908: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = get_long_mmu (%sa);\n", name, name); break;
909: default: abort ();
910: }
911: }
912: } else {
913: switch (size) {
914: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = get_byte (%sa);\n", name, name); count_read++; break;
915: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = get_word (%sa);\n", name, name); count_read++; break;
916: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = get_long (%sa);\n", name, name); count_read += 2; break;
917: default: abort ();
918: }
919: }
920: }
921:
922: /* We now might have to fix up the register for pre-dec or post-inc
923: * addressing modes. */
924: if (!movem)
925: switch (mode) {
926: case Aipi:
927: if (fixup == 1) {
928: printf ("\tmmufixup[%d].reg = %s;\n", fixupcnt, reg);
929: printf ("\tmmufixup[%d].value = m68k_areg (regs, %s);\n", fixupcnt, reg);
930: }
931: switch (size) {
932: case sz_byte:
933: printf ("\tm68k_areg (regs, %s) += areg_byteinc[%s];\n", reg, reg);
934: break;
935: case sz_word:
936: printf ("\tm68k_areg (regs, %s) += 2;\n", reg);
937: break;
938: case sz_long:
939: printf ("\tm68k_areg (regs, %s) += 4;\n", reg);
940: break;
941: default:
942: abort ();
943: }
944: break;
945: case Apdi:
946: if (fixup == 1) {
947: printf ("\tmmufixup[%d].reg = %s;\n", fixupcnt, reg);
948: printf ("\tmmufixup[%d].value = m68k_areg (regs, %s);\n", fixupcnt, reg);
949: }
950: printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
951: break;
952: default:
953: break;
954: }
955: }
956:
957: static void genamode_fixup (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags, int fixup)
958: {
959: if (fixup != 2) {
960: genamode2 (mode, reg, size, name, getv, movem, flags, fixup);
961: } else {
962: if (!movem) {
963: switch ((int)mode)
964: {
965: case Aipi:
966: case Apdi:
967: printf ("\tmmufixup[0].reg = -1;\n"/*, fixupcnt*/);
968: break;
969: }
970: }
971: }
972: }
973:
974: static void genamode (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
975: {
976: genamode2 (mode, reg, size, name, getv, movem, flags, 0);
977: }
978: static void genamode_pre (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
979: {
980: genamode_fixup (mode, reg, size, name, getv, movem, flags, using_mmu ? 1 : 0);
981: }
982: static void genamode_post (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
983: {
984: if (using_mmu)
985: genamode_fixup (mode, reg, size, name, getv, movem, flags, 2);
986: }
987:
988: static void genastore_2 (const char *from, amodes mode, const char *reg, wordsizes size, const char *to, int store_dir, int flags)
989: {
990: switch (mode) {
991: case Dreg:
992: switch (size) {
993: case sz_byte:
994: printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
995: break;
996: case sz_word:
997: printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
998: break;
999: case sz_long:
1000: printf ("\tm68k_dreg (regs, %s) = (%s);\n", reg, from);
1001: break;
1002: default:
1003: abort ();
1004: }
1005: break;
1006: case Areg:
1007: switch (size) {
1008: case sz_word:
1009: printf ("\tm68k_areg (regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
1010: break;
1011: case sz_long:
1012: printf ("\tm68k_areg (regs, %s) = (%s);\n", reg, from);
1013: break;
1014: default:
1015: abort ();
1016: }
1017: break;
1018: case Aind:
1019: case Aipi:
1020: case Apdi:
1021: case Ad16:
1022: case Ad8r:
1023: case absw:
1024: case absl:
1025: case PC16:
1026: case PC8r:
1027: gen_set_fault_pc ();
1028: if (using_ce020) {
1029: switch (size) {
1030: case sz_byte:
1031: printf ("\t%s (%sa, %s);\n", dstb, to, from);
1032: count_write++;
1033: break;
1034: case sz_word:
1035: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1036: abort ();
1037: printf ("\t%s (%sa, %s);\n", dstw, to, from);
1038: count_write++;
1039: break;
1040: case sz_long:
1041: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1042: abort ();
1043: printf ("\t%s (%sa, %s);\n", dstl, to, from);
1044: count_write += 2;
1045: break;
1046: default:
1047: abort ();
1048: }
1049: } else if (using_ce) {
1050: switch (size) {
1051: case sz_byte:
1052: printf ("\tput_byte_ce (%sa, %s);\n", to, from);
1053: count_write++;
1054: break;
1055: case sz_word:
1056: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1057: abort ();
1058: printf ("\tput_word_ce (%sa, %s);\n", to, from);
1059: count_write++;
1060: break;
1061: case sz_long:
1062: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1063: abort ();
1064: if (store_dir)
1065: printf ("\tput_word_ce (%sa + 2, %s); put_word_ce (%sa, %s >> 16);\n", to, from, to, from);
1066: else
1067: printf ("\tput_word_ce (%sa, %s >> 16); put_word_ce (%sa + 2, %s);\n", to, from, to, from);
1068: count_write += 2;
1069: break;
1070: default:
1071: abort ();
1072: }
1073: } else if (using_mmu) {
1074: switch (size) {
1075: case sz_byte:
1076: insn_n_cycles += 4;
1077: if (flags & GF_FC)
1078: printf ("\tdfc_put_byte (%sa, %s);\n", to, from);
1079: else
1080: printf ("\tput_byte_mmu (%sa, %s);\n", to, from);
1081: break;
1082: case sz_word:
1083: insn_n_cycles += 4;
1084: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1085: abort ();
1086: if (flags & GF_FC)
1087: printf ("\tdfc_put_word (%sa, %s);\n", to, from);
1088: else
1089: printf ("\tput_word_mmu (%sa, %s);\n", to, from);
1090: break;
1091: case sz_long:
1092: insn_n_cycles += 8;
1093: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1094: abort ();
1095: if (flags & GF_FC)
1096: printf ("\tdfc_put_long (%sa, %s);\n", to, from);
1097: else
1098: printf ("\tput_long_mmu (%sa, %s);\n", to, from);
1099: break;
1100: default:
1101: abort ();
1102: }
1103: } else {
1104: switch (size) {
1105: case sz_byte:
1106: insn_n_cycles += 4;
1107: printf ("\tput_byte (%sa, %s);\n", to, from);
1108: count_write++;
1109: break;
1110: case sz_word:
1111: insn_n_cycles += 4;
1112: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1113: abort ();
1114: printf ("\tput_word (%sa, %s);\n", to, from);
1115: count_write++;
1116: break;
1117: case sz_long:
1118: insn_n_cycles += 8;
1119: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1120: abort ();
1121: printf ("\tput_long (%sa, %s);\n", to, from);
1122: count_write += 2;
1123: break;
1124: default:
1125: abort ();
1126: }
1127: }
1128: break;
1129: case imm:
1130: case imm0:
1131: case imm1:
1132: case imm2:
1133: case immi:
1134: abort ();
1135: break;
1136: default:
1137: abort ();
1138: }
1139: }
1140:
1141: static void genastore (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1142: {
1143: genastore_2 (from, mode, reg, size, to, 0, 0);
1144: }
1145: static void genastore_rev (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1146: {
1147: genastore_2 (from, mode, reg, size, to, 1, 0);
1148: }
1149: static void genastore_fc (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1150: {
1151: genastore_2 (from, mode, reg, size, to, 1, GF_FC);
1152: }
1153:
1154: static void genmovemel (uae_u16 opcode)
1155: {
1156: char getcode[100];
1157: int size = table68k[opcode].size == sz_long ? 4 : 2;
1158:
1159: if (table68k[opcode].size == sz_long) {
1160: sprintf (getcode, "%s (srca)", srcl);
1161: } else {
1162: sprintf (getcode, "(uae_s32)(uae_s16)%s (srca)", srcw);
1163: }
1164: count_read += table68k[opcode].size == sz_long ? 2 : 1;
1165: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1166: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1.1.1.2 ! root 1167: printf ("\tuae_u16 regs_number = 0;\n");
1.1 root 1168: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, 0);
1169: start_brace ();
1.1.1.2 ! root 1170: printf ("\twhile (dmask) { m68k_dreg (regs, movem_index1[dmask]) = %s; srca += %d; dmask = movem_next[dmask]; regs_number++; }\n",
1.1 root 1171: getcode, size);
1.1.1.2 ! root 1172: printf ("\twhile (amask) { m68k_areg (regs, movem_index1[amask]) = %s; srca += %d; amask = movem_next[amask]; regs_number++; }\n",
1.1 root 1173: getcode, size);
1174:
1175: if (table68k[opcode].dmode == Aipi) {
1176: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1177: count_read++;
1178: }
1179: count_ncycles++;
1.1.1.2 ! root 1180:
! 1181: if (using_ce020 == 2) {
! 1182: if (table68k[opcode].size == sz_long)
! 1183: printf ("\tregs.ce030_instr_addcycles = regs_number * 8;\n");
! 1184: else
! 1185: printf ("\tregs.ce030_instr_addcycles = regs_number * 4;\n");
! 1186: }
! 1187:
1.1 root 1188: fill_prefetch_next ();
1189: }
1190:
1191: static void genmovemel_ce (uae_u16 opcode)
1192: {
1193: int size = table68k[opcode].size == sz_long ? 4 : 2;
1194: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1195: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1196: printf ("\tuae_u32 v;\n");
1197: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA);
1198: if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
1199: addcycles000 (2);
1200: start_brace ();
1201: if (table68k[opcode].size == sz_long) {
1202: printf ("\twhile (dmask) { v = get_word_ce(srca) << 16; v |= get_word_ce(srca + 2); m68k_dreg (regs, movem_index1[dmask]) = v; srca += %d; dmask = movem_next[dmask]; }\n",
1203: size);
1204: printf ("\twhile (amask) { v = get_word_ce(srca) << 16; v |= get_word_ce(srca + 2); m68k_areg (regs, movem_index1[amask]) = v; srca += %d; amask = movem_next[amask]; }\n",
1205: size);
1206: } else {
1207: printf ("\twhile (dmask) { m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_ce(srca); srca += %d; dmask = movem_next[dmask]; }\n",
1208: size);
1209: printf ("\twhile (amask) { m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_ce(srca); srca += %d; amask = movem_next[amask]; }\n",
1210: size);
1211: }
1212: printf ("\tget_word_ce (srca);\n"); // and final extra word fetch that goes nowhere..
1213: count_read++;
1214: if (table68k[opcode].dmode == Aipi)
1215: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1.1.1.2 ! root 1216:
1.1 root 1217: count_ncycles++;
1218: fill_prefetch_next ();
1219: }
1220:
1221: static void genmovemle (uae_u16 opcode)
1222: {
1223: char putcode[100];
1224: int size = table68k[opcode].size == sz_long ? 4 : 2;
1225:
1226: if (table68k[opcode].size == sz_long) {
1227: sprintf (putcode, "%s (srca", dstl);
1228: } else {
1229: sprintf (putcode, "%s (srca", dstw);
1230: }
1231: count_write += table68k[opcode].size == sz_long ? 2 : 1;
1232:
1233: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1234: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, 0);
1235: start_brace ();
1.1.1.2 ! root 1236: printf ("\tuae_u16 regs_number = 0;\n");
1.1 root 1237: if (table68k[opcode].dmode == Apdi) {
1238: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
1239: if (!using_mmu)
1240: printf ("\tint type = get_cpu_model() >= 68020;\n");
1241: printf ("\twhile (amask) {\n");
1242: printf ("\t\tsrca -= %d;\n", size);
1243: if (!using_mmu)
1244: printf ("\t\tif (type) m68k_areg (regs, dstreg) = srca;\n");
1245: printf ("\t\t%s, m68k_areg (regs, movem_index2[amask]));\n", putcode);
1246: printf ("\t\tamask = movem_next[amask];\n");
1.1.1.2 ! root 1247: printf ("\t\tregs_number++;\n");
1.1 root 1248: printf ("\t}\n");
1.1.1.2 ! root 1249: printf ("\twhile (dmask) { srca -= %d; %s, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; regs_number++; }\n",
1.1 root 1250: size, putcode);
1251: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1252: } else {
1253: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1.1.1.2 ! root 1254: printf ("\twhile (dmask) { %s, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; regs_number++; }\n",
1.1 root 1255: putcode, size);
1.1.1.2 ! root 1256: printf ("\twhile (amask) { %s, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; regs_number++; }\n",
1.1 root 1257: putcode, size);
1258: }
1.1.1.2 ! root 1259:
1.1 root 1260: count_ncycles++;
1.1.1.2 ! root 1261: if (using_ce020 == 2) {
! 1262: if (table68k[opcode].size == sz_long)
! 1263: printf ("\tregs.ce030_instr_addcycles = regs_number * 8;\n");
! 1264: else
! 1265: printf ("\tregs.ce030_instr_addcycles = regs_number * 4;\n");
! 1266: }
1.1 root 1267: fill_prefetch_next ();
1268: }
1269:
1270: static void genmovemle_ce (uae_u16 opcode)
1271: {
1272: int size = table68k[opcode].size == sz_long ? 4 : 2;
1273: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1274: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA);
1275:
1276: if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r) {
1277: addcycles000 (2);
1278: }
1279: start_brace ();
1280: if (table68k[opcode].size == sz_long) {
1281: if (table68k[opcode].dmode == Apdi) {
1282: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
1283: printf ("\twhile (amask) { srca -= %d; put_word_ce (srca, m68k_areg (regs, movem_index2[amask]) >> 16); put_word_ce (srca + 2, m68k_areg (regs, movem_index2[amask])); amask = movem_next[amask]; }\n",
1284: size);
1.1.1.2 ! root 1285: printf ("\twhile (dmask) { srca -= %d; put_word_ce (srca, m68k_dreg (regs, movem_index2[dmask]) >> 16); put_word_ce (srca + 2, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask];}\n",
1.1 root 1286: size);
1287: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1288: } else {
1289: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1290: printf ("\twhile (dmask) { put_word_ce (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16); put_word_ce (srca + 2, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
1291: size);
1.1.1.2 ! root 1292: printf ("\twhile (amask) { put_word_ce (srca, m68k_areg (regs, movem_index1[amask]) >> 16); put_word_ce (srca + 2, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask];}\n",
1.1 root 1293: size);
1294: }
1295: } else {
1296: if (table68k[opcode].dmode == Apdi) {
1297: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
1298: printf ("\twhile (amask) { srca -= %d; put_word_ce (srca, m68k_areg (regs, movem_index2[amask])); amask = movem_next[amask]; }\n",
1299: size);
1300: printf ("\twhile (dmask) { srca -= %d; put_word_ce (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }\n",
1301: size);
1302: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1303: } else {
1304: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1305: printf ("\twhile (dmask) { put_word_ce (srca, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
1306: size);
1307: printf ("\twhile (amask) { put_word_ce (srca, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; }\n",
1308: size);
1309: }
1310: }
1.1.1.2 ! root 1311:
1.1 root 1312: count_ncycles++;
1313: fill_prefetch_next ();
1314: }
1315:
1316: static void duplicate_carry (int n)
1317: {
1318: int i;
1319: for (i = 0; i <= n; i++)
1320: printf ("\t");
1321: printf ("COPY_CARRY ();\n");
1322: }
1323:
1324: typedef enum
1325: {
1326: flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_z, flag_zn,
1327: flag_av, flag_sv
1328: }
1329: flagtypes;
1330:
1331: static void genflags_normal (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
1332: {
1333: char vstr[100], sstr[100], dstr[100];
1334: char usstr[100], udstr[100];
1335: char unsstr[100], undstr[100];
1336:
1337: switch (size) {
1338: case sz_byte:
1339: strcpy (vstr, "((uae_s8)(");
1340: strcpy (usstr, "((uae_u8)(");
1341: break;
1342: case sz_word:
1343: strcpy (vstr, "((uae_s16)(");
1344: strcpy (usstr, "((uae_u16)(");
1345: break;
1346: case sz_long:
1347: strcpy (vstr, "((uae_s32)(");
1348: strcpy (usstr, "((uae_u32)(");
1349: break;
1350: default:
1351: abort ();
1352: }
1353: strcpy (unsstr, usstr);
1354:
1355: strcpy (sstr, vstr);
1356: strcpy (dstr, vstr);
1357: strcat (vstr, value);
1358: strcat (vstr, "))");
1359: strcat (dstr, dst);
1360: strcat (dstr, "))");
1361: strcat (sstr, src);
1362: strcat (sstr, "))");
1363:
1364: strcpy (udstr, usstr);
1365: strcat (udstr, dst);
1366: strcat (udstr, "))");
1367: strcat (usstr, src);
1368: strcat (usstr, "))");
1369:
1370: strcpy (undstr, unsstr);
1371: strcat (unsstr, "-");
1372: strcat (undstr, "~");
1373: strcat (undstr, dst);
1374: strcat (undstr, "))");
1375: strcat (unsstr, src);
1376: strcat (unsstr, "))");
1377:
1378: switch (type) {
1379: case flag_logical_noclobber:
1380: case flag_logical:
1381: case flag_z:
1382: case flag_zn:
1383: case flag_av:
1384: case flag_sv:
1385: case flag_addx:
1386: case flag_subx:
1387: break;
1388:
1389: case flag_add:
1390: start_brace ();
1391: printf ("uae_u32 %s = %s + %s;\n", value, dstr, sstr);
1392: break;
1393: case flag_sub:
1394: case flag_cmp:
1395: start_brace ();
1396: printf ("uae_u32 %s = %s - %s;\n", value, dstr, sstr);
1397: break;
1398: }
1399:
1400: switch ((int)type) {
1401: case flag_logical_noclobber:
1402: case flag_logical:
1403: case flag_zn:
1404: break;
1405:
1406: case flag_add:
1407: case flag_sub:
1408: case flag_addx:
1409: case flag_subx:
1410: case flag_cmp:
1411: case flag_av:
1412: case flag_sv:
1413: start_brace ();
1414: printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
1415: printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
1416: printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
1417: break;
1418: }
1419:
1420: switch (type) {
1421: case flag_logical:
1422: printf ("\tCLEAR_CZNV ();\n");
1423: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1424: printf ("\tSET_NFLG (%s < 0);\n", vstr);
1425: break;
1426: case flag_logical_noclobber:
1427: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1428: printf ("\tSET_NFLG (%s < 0);\n", vstr);
1429: break;
1430: case flag_av:
1431: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
1432: break;
1433: case flag_sv:
1434: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
1435: break;
1436: case flag_z:
1437: printf ("\tSET_ZFLG (GET_ZFLG () & (%s == 0));\n", vstr);
1438: break;
1439: case flag_zn:
1440: printf ("\tSET_ZFLG (GET_ZFLG () & (%s == 0));\n", vstr);
1441: printf ("\tSET_NFLG (%s < 0);\n", vstr);
1442: break;
1443: case flag_add:
1444: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1445: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
1446: printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
1447: duplicate_carry (0);
1448: printf ("\tSET_NFLG (flgn != 0);\n");
1449: break;
1450: case flag_sub:
1451: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1452: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
1453: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
1454: duplicate_carry (0);
1455: printf ("\tSET_NFLG (flgn != 0);\n");
1456: break;
1457: case flag_addx:
1458: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
1459: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
1460: duplicate_carry (0);
1461: break;
1462: case flag_subx:
1463: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
1464: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
1465: duplicate_carry (0);
1466: break;
1467: case flag_cmp:
1468: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1469: printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
1470: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
1471: printf ("\tSET_NFLG (flgn != 0);\n");
1472: break;
1473: }
1474: }
1475:
1476: static void genflags (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
1477: {
1478: /* Temporarily deleted 68k/ARM flag optimizations. I'd prefer to have
1479: them in the appropriate m68k.h files and use just one copy of this
1480: code here. The API can be changed if necessary. */
1481: if (optimized_flags) {
1482: switch (type) {
1483: case flag_add:
1484: case flag_sub:
1485: start_brace ();
1486: printf ("\tuae_u32 %s;\n", value);
1487: break;
1488:
1489: default:
1490: break;
1491: }
1492:
1493: /* At least some of those casts are fairly important! */
1494: switch (type) {
1495: case flag_logical_noclobber:
1496: printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
1497: if (strcmp (value, "0") == 0) {
1498: printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
1499: } else {
1500: switch (size) {
1501: case sz_byte: printf ("\toptflag_testb (regs, (uae_s8)(%s));\n", value); break;
1502: case sz_word: printf ("\toptflag_testw (regs, (uae_s16)(%s));\n", value); break;
1503: case sz_long: printf ("\toptflag_testl (regs, (uae_s32)(%s));\n", value); break;
1504: }
1505: printf ("\tIOR_CZNV (oldcznv);\n");
1506: }
1507: printf ("\t}\n");
1508: return;
1509: case flag_logical:
1510: if (strcmp (value, "0") == 0) {
1511: printf ("\tSET_CZNV (FLAGVAL_Z);\n");
1512: } else {
1513: switch (size) {
1514: case sz_byte: printf ("\toptflag_testb (regs, (uae_s8)(%s));\n", value); break;
1515: case sz_word: printf ("\toptflag_testw (regs, (uae_s16)(%s));\n", value); break;
1516: case sz_long: printf ("\toptflag_testl (regs, (uae_s32)(%s));\n", value); break;
1517: }
1518: }
1519: return;
1520:
1521: case flag_add:
1522: switch (size) {
1523: case sz_byte: printf ("\toptflag_addb (regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
1524: case sz_word: printf ("\toptflag_addw (regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
1525: case sz_long: printf ("\toptflag_addl (regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
1526: }
1527: return;
1528:
1529: case flag_sub:
1530: switch (size) {
1531: case sz_byte: printf ("\toptflag_subb (regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
1532: case sz_word: printf ("\toptflag_subw (regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
1533: case sz_long: printf ("\toptflag_subl (regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
1534: }
1535: return;
1536:
1537: case flag_cmp:
1538: switch (size) {
1539: case sz_byte: printf ("\toptflag_cmpb (regs, (uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
1540: case sz_word: printf ("\toptflag_cmpw (regs, (uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
1541: case sz_long: printf ("\toptflag_cmpl (regs, (uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
1542: }
1543: return;
1544:
1545: default:
1546: break;
1547: }
1548: }
1549:
1550: genflags_normal (type, size, value, src, dst);
1551: }
1552:
1553: static void force_range_for_rox (const char *var, wordsizes size)
1554: {
1555: /* Could do a modulo operation here... which one is faster? */
1556: switch (size) {
1557: case sz_long:
1558: printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
1559: break;
1560: case sz_word:
1561: printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
1562: printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
1563: break;
1564: case sz_byte:
1565: printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
1566: printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
1567: printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
1568: break;
1569: }
1570: }
1571:
1572: static const char *cmask (wordsizes size)
1573: {
1574: switch (size) {
1575: case sz_byte: return "0x80";
1576: case sz_word: return "0x8000";
1577: case sz_long: return "0x80000000";
1578: default: abort ();
1579: }
1580: }
1581:
1582: static int source_is_imm1_8 (struct instr *i)
1583: {
1584: return i->stype == 3;
1585: }
1586:
1587: static void shift_ce (amodes dmode, int size)
1588: {
1589: if (using_ce && isreg (dmode)) {
1590: int c = size == sz_long ? 4 : 2;
1591: printf ("\t{\n");
1592: printf ("\t\tint cycles = %d;\n", c);
1593: printf ("\t\tcycles += 2 * ccnt;\n");
1594: addcycles000_3 ("\t\t");
1595: printf ("\t}\n");
1596: count_cycles += c;
1597: }
1598: }
1599:
1600: // BCHG/BSET/BCLR Dx,Dx or #xx,Dx adds 2 cycles if bit number > 15
1601: static void bsetcycles (struct instr *curi)
1602: {
1603: if (curi->size == sz_byte) {
1604: printf ("\tsrc &= 7;\n");
1605: } else {
1606: printf ("\tsrc &= 31;\n");
1607: if (isreg (curi->dmode)) {
1608: addcycles000 (2);
1609: if (curi->mnemo != i_BTST && using_ce) {
1610: printf ("\tif (src > 15) do_cycles_ce000 (2);\n");
1611: count_ncycles++;
1612: }
1613: }
1614: }
1615: }
1616:
1617: static int islongimm (struct instr *curi)
1618: {
1619: return (curi->size == sz_long && (curi->smode == Dreg || curi->smode == imm));
1620: }
1621:
1622: static void gen_opcode (unsigned long int opcode)
1623: {
1624: struct instr *curi = table68k + opcode;
1625:
1626: insn_n_cycles = using_prefetch ? 0 : 4;
1627:
1.1.1.2 ! root 1628: /* Store the family of the instruction (used to check for pairing on ST)
! 1629: * and leave some space for patching in the current cycles later */
! 1630: if (!using_ce020) {
! 1631: printf ("\tOpcodeFamily = %d; CurrentInstrCycles = \n", curi->mnemo);
! 1632: nCurInstrCycPos = ftell(stdout) - 5;
! 1633: }
! 1634: else if (using_ce020 == 2) {
! 1635: /* Initialize the cycle table to the general table by default */
! 1636: instr_table = TABLE_FALCON_CYCLES;
! 1637: instr_table_index = instr_index;
! 1638: no_return_cycles = false;
! 1639: }
1.1 root 1640:
1641: if (using_ce020) {
1642: if (using_ce020 == 2) {
1643: ce020_prefetch_long = "get_long_ce030_prefetch";
1644: ce020_prefetch_word = "get_word_ce030_prefetch";
1645: srcl = "get_long_ce030";
1646: dstl = "put_long_ce030";
1647: srcw = "get_word_ce030";
1648: dstw = "put_word_ce030";
1649: srcb = "get_byte_ce030";
1650: dstb = "put_byte_ce030";
1651: } else {
1652: ce020_prefetch_long = "get_long_ce020_prefetch";
1653: ce020_prefetch_word = "get_word_ce020_prefetch";
1654: srcl = "get_long_ce020";
1655: dstl = "put_long_ce020";
1656: srcw = "get_word_ce020";
1657: dstw = "put_word_ce020";
1658: srcb = "get_byte_ce020";
1659: dstb = "put_byte_ce020";
1660: }
1661: } else if (using_mmu) {
1662: srcl = "get_long_mmu";
1663: dstl = "put_long_mmu";
1664: srcw = "get_word_mmu";
1665: dstw = "put_word_mmu";
1666: srcb = "get_byte_mmu";
1667: dstb = "put_byte_mmu";
1668: } else if (using_ce) {
1669: srcl = "get_long_ce";
1670: dstl = "put_long_ce";
1671: srcw = "get_word_ce";
1672: dstw = "put_word_ce";
1673: srcb = "get_byte_ce";
1674: dstb = "put_byte_ce";
1675: } else {
1676: srcl = "get_long";
1677: dstl = "put_long";
1678: srcw = "get_word";
1679: dstw = "put_word";
1680: srcb = "get_byte";
1681: dstb = "put_byte";
1682: }
1683:
1684: insn_n_cycles020 = 0;
1685:
1686: start_brace ();
1687: m68k_pc_offset = 2;
1688: switch (curi->plev) {
1689: case 0: /* not privileged */
1690: break;
1691: case 1: /* unprivileged only on 68000 */
1692: if (cpu_level == 0)
1693: break;
1694: if (next_cpu_level < 0)
1695: next_cpu_level = 0;
1696:
1697: /* fall through */
1698: case 2: /* priviledged */
1699: printf ("if (!regs.s) { Exception (8, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1700: need_endlabel = 1;
1701: start_brace ();
1702: break;
1703: case 3: /* privileged if size == word */
1704: if (curi->size == sz_byte)
1705: break;
1706: printf ("if (!regs.s) { Exception (8, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1707: need_endlabel = 1;
1708: start_brace ();
1709: break;
1710: }
1711: switch (curi->mnemo) {
1712: case i_OR:
1713: case i_AND:
1714: case i_EOR:
1715: {
1716: int c = 0;
1717: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1718: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
1719: printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
1720: genflags (flag_logical, curi->size, "src", "", "");
1721: if (curi->dmode == Dreg && curi->size == sz_long) {
1722: c += 2;
1723: if (curi->smode == imm || curi->smode == Dreg)
1724: c += 2;
1725: }
1726: fill_prefetch_next ();
1727: if (c > 0)
1728: addcycles000 (c);
1729: genastore_rev ("src", curi->dmode, "dstreg", curi->size, "dst");
1730: break;
1731: }
1732: // all SR/CCR modifications have dummy read access
1733: case i_ORSR:
1734: case i_EORSR:
1735: printf ("\tMakeSR ();\n");
1736: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1737: dummy_prefetch ();
1738: if (curi->size == sz_byte) {
1739: printf ("\tsrc &= 0xFF;\n");
1740: }
1741: addcycles000 (8);
1742: fill_prefetch_next ();
1743: printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
1744: printf ("\tMakeFromSR ();\n");
1745: break;
1746: case i_ANDSR:
1747: printf ("\tMakeSR ();\n");
1748: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1749: dummy_prefetch ();
1750: if (curi->size == sz_byte) {
1751: printf ("\tsrc |= 0xFF00;\n");
1752: }
1753: addcycles000 (8);
1754: fill_prefetch_next ();
1755: printf ("\tregs.sr &= src;\n");
1756: printf ("\tMakeFromSR ();\n");
1757: break;
1758: case i_SUB:
1759: {
1760: int c = 0;
1761: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1762: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
1763: if (curi->dmode == Dreg) {
1764: if (curi->size == sz_long) {
1765: c += 2;
1766: if (curi->smode == imm || curi->smode == immi || curi->smode == Dreg)
1767: c += 2;
1768: }
1769: }
1770: fill_prefetch_next ();
1771: if (c > 0)
1772: addcycles000 (c);
1773: start_brace ();
1774: genflags (flag_sub, curi->size, "newv", "src", "dst");
1775: genastore_rev ("newv", curi->dmode, "dstreg", curi->size, "dst");
1776: break;
1777: }
1778: case i_SUBA:
1779: {
1780: int c = 0;
1781: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1782: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
1783: if (curi->smode == immi) {
1784: // SUBAQ.x is always 8 cycles
1785: c += 4;
1786: } else {
1787: c = curi->size == sz_long ? 2 : 4;
1788: if (islongimm (curi))
1789: c += 2;
1790: }
1791: fill_prefetch_next ();
1792: if (c > 0)
1793: addcycles000 (c);
1794: start_brace ();
1795: printf ("\tuae_u32 newv = dst - src;\n");
1796: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1797: break;
1798: }
1799: case i_SUBX:
1800: if (!isreg (curi->smode))
1801: addcycles000 (2);
1802: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1803: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1804: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1805: fill_prefetch_next ();
1806: if (curi->size == sz_long && isreg (curi->smode))
1807: addcycles000 (4);
1808: start_brace ();
1809: printf ("\tuae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);\n");
1810: genflags (flag_subx, curi->size, "newv", "src", "dst");
1811: genflags (flag_zn, curi->size, "newv", "", "");
1812: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1813: break;
1814: case i_SBCD:
1815: if (!isreg (curi->smode))
1816: addcycles000 (2);
1817: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1818: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1819: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1820: fill_prefetch_next ();
1821: start_brace ();
1822: printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
1823: printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
1824: printf ("\tuae_u16 newv, tmp_newv;\n");
1825: printf ("\tint bcd = 0;\n");
1826: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
1827: printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
1828: printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
1829: printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);\n");
1830: duplicate_carry (0);
1831: /* Manual says bits NV are undefined though a real 68040/060 don't change them */
1832: if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1833: if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1834: next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1835: genflags (flag_z, curi->size, "newv", "", "");
1836: } else {
1837: genflags (flag_zn, curi->size, "newv", "", "");
1838: printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
1839: }
1840: if (isreg (curi->smode))
1841: addcycles000 (2);
1842: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1843: break;
1844: case i_ADD:
1845: {
1846: int c = 0;
1847: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1848: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
1849: if (curi->dmode == Dreg) {
1850: if (curi->size == sz_long) {
1851: c += 2;
1852: if (curi->smode == imm || curi->smode == immi || curi->smode == Dreg)
1853: c += 2;
1854: }
1855: }
1856: fill_prefetch_next ();
1857: if (c > 0)
1858: addcycles000 (c);
1859: start_brace ();
1860: genflags (flag_add, curi->size, "newv", "src", "dst");
1861: genastore_rev ("newv", curi->dmode, "dstreg", curi->size, "dst");
1862: break;
1863: }
1864: case i_ADDA:
1865: {
1866: int c = 0;
1867: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1868: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
1869: if (curi->smode == immi) {
1870: // ADDAQ.x is always 8 cycles
1871: c += 4;
1872: } else {
1873: c = curi->size == sz_long ? 2 : 4;
1874: if (islongimm (curi))
1875: c += 2;
1876: }
1877: fill_prefetch_next ();
1878: if (c > 0)
1879: addcycles000 (c);
1880: start_brace ();
1881: printf ("\tuae_u32 newv = dst + src;\n");
1882: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1883: break;
1884: }
1885: case i_ADDX:
1886: if (!isreg (curi->smode))
1887: addcycles000 (2);
1888: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1889: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1890: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1891: fill_prefetch_next ();
1892: if (curi->size == sz_long && isreg (curi->smode))
1893: addcycles000 (4);
1894: start_brace ();
1895: printf ("\tuae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);\n");
1896: genflags (flag_addx, curi->size, "newv", "src", "dst");
1897: genflags (flag_zn, curi->size, "newv", "", "");
1898: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1899: break;
1900: case i_ABCD:
1901: if (!isreg (curi->smode))
1902: addcycles000 (2);
1903: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1904: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1905: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1906: fill_prefetch_next ();
1907: start_brace ();
1908: printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);\n");
1909: printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
1910: printf ("\tuae_u16 newv, tmp_newv;\n");
1911: printf ("\tint cflg;\n");
1912: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
1913: printf ("\tif (newv_lo > 9) { newv += 6; }\n");
1914: printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
1915: printf ("\tif (cflg) newv += 0x60;\n");
1916: printf ("\tSET_CFLG (cflg);\n");
1917: duplicate_carry (0);
1918: /* Manual says bits NV are undefined though a real 68040 don't change them */
1919: if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1920: if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1921: next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1922: genflags (flag_z, curi->size, "newv", "", "");
1923: }
1924: else {
1925: genflags (flag_zn, curi->size, "newv", "", "");
1926: printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
1927: }
1928: if (isreg (curi->smode))
1929: addcycles000 (2);
1930: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1931: break;
1932: case i_NEG:
1933: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1934: fill_prefetch_next ();
1935: if (isreg (curi->smode) && curi->size == sz_long)
1936: addcycles000 (2);
1937: start_brace ();
1938: genflags (flag_sub, curi->size, "dst", "src", "0");
1939: genastore_rev ("dst", curi->smode, "srcreg", curi->size, "src");
1940: break;
1941: case i_NEGX:
1942: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1943: fill_prefetch_next ();
1944: if (isreg (curi->smode) && curi->size == sz_long)
1945: addcycles000 (2);
1946: start_brace ();
1947: printf ("\tuae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);\n");
1948: genflags (flag_subx, curi->size, "newv", "src", "0");
1949: genflags (flag_zn, curi->size, "newv", "", "");
1950: genastore_rev ("newv", curi->smode, "srcreg", curi->size, "src");
1951: break;
1952: case i_NBCD:
1953: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1954: if (isreg (curi->smode))
1955: addcycles000 (2);
1956: fill_prefetch_next ();
1957: start_brace ();
1958: printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
1959: printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1960: printf ("\tuae_u16 newv;\n");
1961: printf ("\tint cflg;\n");
1962: printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1963: printf ("\tnewv = newv_hi + newv_lo;");
1964: printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1965: printf ("\tif (cflg) newv -= 0x60;\n");
1966: printf ("\tSET_CFLG (cflg);\n");
1967: duplicate_carry(0);
1968: /* Manual says bits NV are undefined though a real 68040 don't change them */
1969: if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1970: if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1971: next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1972: genflags (flag_z, curi->size, "newv", "", "");
1973: }
1974: else {
1975: genflags (flag_zn, curi->size, "newv", "", "");
1976: }
1977: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1978: break;
1979: case i_CLR:
1980: genamode (curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, 0);
1981: fill_prefetch_next ();
1982: if (isreg (curi->smode) && curi->size == sz_long)
1983: addcycles000 (2);
1984: genflags (flag_logical, curi->size, "0", "", "");
1985: genastore_rev ("0", curi->smode, "srcreg", curi->size, "src");
1986: break;
1987: case i_NOT:
1988: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1989: fill_prefetch_next ();
1990: if (isreg (curi->smode) && curi->size == sz_long)
1991: addcycles000 (2);
1992: start_brace ();
1993: printf ("\tuae_u32 dst = ~src;\n");
1994: genflags (flag_logical, curi->size, "dst", "", "");
1995: genastore_rev ("dst", curi->smode, "srcreg", curi->size, "src");
1996: break;
1997: case i_TST:
1998: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1999: fill_prefetch_next ();
2000: genflags (flag_logical, curi->size, "src", "", "");
2001: break;
2002: case i_BTST:
2003: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2004: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2005: fill_prefetch_next ();
2006: bsetcycles (curi);
2007: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
2008: break;
2009: case i_BCHG:
2010: case i_BCLR:
2011: case i_BSET:
2012: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2013: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2014: fill_prefetch_next ();
2015: bsetcycles (curi);
2016: // bclr needs 1 extra cycle
2017: if (curi->mnemo == i_BCLR && curi->dmode == Dreg)
2018: addcycles000 (2);
2019: if (curi->mnemo == i_BCHG) {
2020: printf ("\tdst ^= (1 << src);\n");
2021: printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
2022: } else if (curi->mnemo == i_BCLR) {
2023: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
2024: printf ("\tdst &= ~(1 << src);\n");
2025: } else if (curi->mnemo == i_BSET) {
2026: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
2027: printf ("\tdst |= (1 << src);\n");
2028: }
2029: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
2030: break;
2031: case i_CMPM:
2032: // confirmed
2033: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
2034: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
2035: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
2036: fill_prefetch_next ();
2037: start_brace ();
2038: genflags (flag_cmp, curi->size, "newv", "src", "dst");
2039: break;
2040: case i_CMP:
2041: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2042: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2043: fill_prefetch_next ();
2044: if (curi->dmode == Dreg && curi->size == sz_long)
2045: addcycles000 (2);
2046: start_brace ();
2047: genflags (flag_cmp, curi->size, "newv", "src", "dst");
2048: break;
2049: case i_CMPA:
2050: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2051: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
2052: fill_prefetch_next ();
2053: addcycles000 (2);
2054: start_brace ();
2055: genflags (flag_cmp, sz_long, "newv", "src", "dst");
2056: break;
2057: /* The next two are coded a little unconventional, but they are doing
2058: * weird things... */
2059: case i_MVPRM: // MOVEP R->M
2060: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2061: printf ("\tuaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
2062: if (curi->size == sz_word) {
1.1.1.2 ! root 2063: printf ("\tMovepByteNbr=1; %s (memp, src >> 8); MovepByteNbr=2; %s (memp + 2, src);\n", dstb, dstb);
1.1 root 2064: count_write += 2;
2065: } else {
1.1.1.2 ! root 2066: printf ("\tMovepByteNbr=1; %s (memp, src >> 24); MovepByteNbr=2; %s (memp + 2, src >> 16);\n", dstb, dstb);
! 2067: printf ("\tMovepByteNbr=3; %s (memp + 4, src >> 8); MovepByteNbr=4; %s (memp + 6, src);\n", dstb, dstb);
1.1 root 2068: count_write += 4;
2069: }
2070: fill_prefetch_next ();
2071: break;
2072: case i_MVPMR: // MOVEP M->R
2073: printf ("\tuaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
2074: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
2075: if (curi->size == sz_word) {
2076: printf ("\tuae_u16 val = (%s (memp) << 8) + %s (memp + 2);\n", srcb, srcb);
2077: count_read += 2;
2078: } else {
2079: printf ("\tuae_u32 val = (%s (memp) << 24) + (%s (memp + 2) << 16)\n", srcb, srcb);
2080: printf (" + (%s (memp + 4) << 8) + %s (memp + 6);\n", srcb, srcb);
2081: count_read += 4;
2082: }
2083: fill_prefetch_next ();
2084: genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
2085: break;
2086: case i_MOVE:
2087: case i_MOVEA:
2088: {
2089: /* 2 MOVE instruction variants have special prefetch sequence:
2090: * - MOVE <ea>,-(An) = prefetch is before writes (Apdi)
2091: * - MOVE memory,(xxx).L = 2 prefetches after write
2092: * - all others = prefetch is done after writes
2093: *
2094: * - move.x xxx,[at least 1 extension word here] = fetch 1 extension word before (xxx)
2095: *
2096: */
2097: int prefetch_done = 0, flags;
2098: int dualprefetch = curi->dmode == absl && (curi->smode != Dreg && curi->smode != Areg && curi->smode != imm);
2099: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_MOVE);
2100: flags = 1 | (dualprefetch ? GF_NOREFILL : 0);
2101: genamode2 (curi->dmode, "dstreg", curi->size, "dst", 2, 0, flags | GF_MOVE, 0);
2102: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2103: if (curi->mnemo == i_MOVEA && curi->size == sz_word)
2104: printf ("\tsrc = (uae_s32)(uae_s16)src;\n");
2105: if (curi->dmode == Apdi) {
2106: fill_prefetch_next ();
2107: prefetch_done = 1;
2108: }
2109: if (curi->mnemo == i_MOVE)
2110: genflags (flag_logical, curi->size, "src", "", "");
2111: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2112: sync_m68k_pc ();
2113: if (dualprefetch) {
2114: fill_prefetch_full ();
2115: prefetch_done = 1;
2116: }
2117: if (!prefetch_done)
2118: fill_prefetch_next ();
2119: }
2120: break;
2121: case i_MVSR2: // MOVE FROM SR
2122: genamode (curi->smode, "srcreg", sz_word, "src", 2, 0, 0);
2123: fill_prefetch_next ();
2124: if (isreg (curi->smode))
2125: addcycles000 (2);
2126: printf ("\tMakeSR ();\n");
2127: if (curi->size == sz_byte)
2128: genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
2129: else
2130: genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
2131: break;
2132: case i_MV2SR: // MOVE TO SR
2133: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2134: if (curi->size == sz_byte) {
2135: // MOVE TO CCR
2136: dummy_prefetch ();
2137: addcycles000 (4);
2138: printf ("\tMakeSR ();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
2139: } else {
2140: // MOVE TO SR
2141: dummy_prefetch ();
2142: addcycles000 (4);
2143: printf ("\tregs.sr = src;\n");
2144: }
2145: printf ("\tMakeFromSR ();\n");
2146: fill_prefetch_next ();
2147: break;
2148: case i_SWAP:
2149: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
2150: fill_prefetch_next ();
2151: start_brace ();
2152: printf ("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
2153: genflags (flag_logical, sz_long, "dst", "", "");
2154: genastore ("dst", curi->smode, "srcreg", sz_long, "src");
2155: break;
2156: case i_EXG:
2157: // confirmed
2158: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2159: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2160: fill_prefetch_next ();
2161: addcycles000 (2);
2162: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
2163: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2164: break;
2165: case i_EXT:
2166: // confirmed
2167: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
2168: fill_prefetch_next ();
2169: start_brace ();
2170: switch (curi->size) {
2171: case sz_byte: printf ("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
2172: case sz_word: printf ("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
2173: case sz_long: printf ("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
2174: default: abort ();
2175: }
2176: genflags (flag_logical,
2177: curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
2178: genastore ("dst", curi->smode, "srcreg",
2179: curi->size == sz_word ? sz_word : sz_long, "src");
2180: break;
2181: case i_MVMEL:
2182: // confirmed
2183: if (using_ce)
2184: genmovemel_ce (opcode);
2185: else
2186: genmovemel (opcode);
2187: break;
2188: case i_MVMLE:
2189: // confirmed
2190: if (using_ce)
2191: genmovemle_ce (opcode);
2192: else
2193: genmovemle (opcode);
2194: break;
2195: case i_TRAP:
2196: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2197: gen_set_fault_pc ();
2198: sync_m68k_pc ();
2199: printf ("\tException (src + 32, 0 ,M68000_EXC_SRC_CPU);\n");
2200: did_prefetch = 1;
2201: m68k_pc_offset = 0;
2202: break;
2203: case i_MVR2USP:
2204: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2205: fill_prefetch_next ();
2206: printf ("\tregs.usp = src;\n");
2207: break;
2208: case i_MVUSP2R:
2209: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0, 0);
2210: fill_prefetch_next ();
2211: genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
2212: break;
2213: case i_RESET:
2214: fill_prefetch_next ();
2215: printf ("\tcpureset ();\n");
2216: addcycles000 (128);
2217: if (using_prefetch)
2218: printf ("\tregs.irc = get_iword (4);\n");
2219: break;
2220: case i_NOP:
2221: fill_prefetch_next ();
2222: break;
2223: case i_STOP:
2224: if (using_prefetch) {
2225: printf ("\tregs.sr = regs.irc;\n");
2226: m68k_pc_offset += 2;
2227: } else {
2228: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2229: printf ("\tregs.sr = src;\n");
2230: }
2231: printf ("\tMakeFromSR ();\n");
2232: printf ("\tm68k_setstopped ();\n");
2233: sync_m68k_pc ();
2234: // STOP does not prefetch anything
2235: did_prefetch = -1;
2236: break;
2237: case i_LPSTOP: /* 68060 */
2238: printf ("\tuae_u16 sw = get_iword (2);\n");
2239: printf ("\tuae_u16 sr;\n");
2240: printf ("\tif (sw != (0x100|0x80|0x40)) { Exception (4, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
2241: printf ("\tsr = get_iword (4);\n");
2242: printf ("\tif (!(sr & 0x8000)) { Exception (8, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
2243: printf ("\tregs.sr = sr;\n");
2244: printf ("\tMakeFromSR ();\n");
2245: printf ("\tm68k_setstopped();\n");
2246: m68k_pc_offset += 4;
2247: sync_m68k_pc ();
2248: fill_prefetch_full ();
2249: break;
2250: case i_RTE:
2251: if (cpu_level == 0) {
2252: genamode (Aipi, "7", sz_word, "sr", 1, 0, GF_NOREFILL);
2253: genamode (Aipi, "7", sz_long, "pc", 1, 0, GF_NOREFILL);
2254: printf ("\tregs.sr = sr;\n");
2255: setpc ("pc");
2256: printf ("\tMakeFromSR ();\n");
2257: } else {
2258: int old_brace_level = n_braces;
2259: if (next_cpu_level < 0)
2260: next_cpu_level = 0;
2261: printf ("\tuae_u16 newsr; uae_u32 newpc;\n");
2262: printf ("\tfor (;;) {\n");
2263: printf ("\t\tuaecptr a = m68k_areg (regs, 7);\n");
2264: printf ("\t\tuae_s16 sr = %s (a);\n", srcw);
2265: printf ("\t\tuae_s32 pc = %s (a + 2);\n", srcl);
2266: printf ("\t\tuae_s16 format = %s (a + 2 + 4);\n", srcw);
2267: printf ("\t\tint frame = format >> 12;\n");
2268: printf ("\t\tint offset = 8;\n");
2269: printf ("\t\tnewsr = sr; newpc = pc;\n");
2270: printf ("\t\tif (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }\n");
2271: printf ("\t\telse if (frame == 0x1) { m68k_areg (regs, 7) += offset; }\n");
2272: printf ("\t\telse if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }\n");
2273: printf ("\t\telse if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }\n");
2274: if (using_mmu)
2275: printf ("\t\telse if (frame == 0x7) { m68k_do_rte_mmu (a); m68k_areg (regs, 7) += offset + 52; break; }\n");
2276: printf ("\t\telse if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }\n");
2277: printf ("\t\telse if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }\n");
2278: printf ("\t\telse if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }\n");
2279: printf ("\t\telse if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }\n");
2280: printf ("\t\telse { m68k_areg (regs, 7) += offset; Exception (14, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
2281: printf ("\t\tregs.sr = newsr; MakeFromSR ();\n}\n");
2282: pop_braces (old_brace_level);
2283: printf ("\tregs.sr = newsr; MakeFromSR ();\n");
2284: printf ("\tif (newpc & 1) {\n");
2285: printf ("\t\texception3i (0x%04X, m68k_getpc (), newpc);\n", opcode);
2286: printf ("\t\tgoto %s;\n", endlabelstr);
2287: printf ("\t}\n");
2288: printf ("\t\tm68k_setpc (newpc);\n");
2289: printf ("\tipl_fetch ();\n");
2290: need_endlabel = 1;
2291: }
1.1.1.2 ! root 2292: instr_table = TABLE_FALCON_CYCLES_RTE;
! 2293: instr_table_index = 0;
1.1 root 2294: /* PC is set and prefetch filled. */
2295: m68k_pc_offset = 0;
2296: fill_prefetch_full ();
2297: break;
2298: case i_RTD:
2299: if (using_mmu) {
2300: genamode (curi->smode, "srcreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2301: genamode (Aipi, "7", sz_long, "pc", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2302: printf ("\tm68k_areg(regs, 7) += offs;\n");
2303: } else {
2304: genamode (Aipi, "7", sz_long, "pc", 1, 0, 0);
2305: genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0, 0);
2306: printf ("\tm68k_areg (regs, 7) += offs;\n");
2307: printf ("\tif (pc & 1) {\n");
2308: printf ("\t\texception3i (0x%04X, m68k_getpc (), pc);\n", opcode);
2309: printf ("\t\tgoto %s;\n", endlabelstr);
2310: printf ("\t}\n");
2311: }
2312: printf ("\tif (pc & 1) {\n");
2313: printf ("\t\texception3i (0x%04X, m68k_getpc(), pc);\n", opcode);
2314: printf ("\t\tgoto %s;\n", endlabelstr);
2315: printf ("\t}\n");
2316: setpc ("pc");
2317: /* PC is set and prefetch filled. */
2318: m68k_pc_offset = 0;
2319: fill_prefetch_full ();
2320: need_endlabel = 1;
2321: break;
2322: case i_LINK:
2323: // ce confirmed
2324: if (using_mmu) {
2325: genamode (curi->dmode, "dstreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2326: genamode (Apdi, "7", sz_long, "old", GENA_GETV_FETCH_ALIGN, GENA_MOVEM_DO_INC, 0);
2327: genamode (curi->smode, "srcreg", sz_long, "src", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2328: genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
2329: printf ("\tm68k_areg(regs, 7) += offs;\n");
2330: genastore ("src", Apdi, "7", sz_long, "old");
2331: } else {
2332: genamode (Apdi, "7", sz_long, "old", 2, 0, GF_AA);
2333: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0, GF_AA);
2334: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0, 0);
2335: genastore ("src", Apdi, "7", sz_long, "old");
2336: genastore ("m68k_areg (regs, 7)", curi->smode, "srcreg", sz_long, "src");
2337: printf ("\tm68k_areg (regs, 7) += offs;\n");
2338: fill_prefetch_next ();
2339: }
2340: break;
2341: case i_UNLK:
2342: // ce confirmed
2343: if (using_mmu) {
2344: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2345: printf ("\tuae_s32 old = get_long_mmu (src);\n");
2346: printf ("\tm68k_areg (regs, 7) = src + 4;\n");
2347: printf ("\tm68k_areg (regs, srcreg) = old;\n");
2348: } else {
2349: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2350: printf ("\tm68k_areg (regs, 7) = src;\n");
2351: genamode (Aipi, "7", sz_long, "old", 1, 0, 0);
2352: fill_prefetch_next ();
2353: genastore ("old", curi->smode, "srcreg", curi->size, "src");
2354: }
2355: break;
2356: case i_RTS:
2357: printf ("\tuaecptr pc = m68k_getpc ();\n");
2358: if (using_ce020 == 1)
2359: printf ("\tm68k_do_rts_ce020 ();\n");
2360: else if (using_ce020 == 2)
2361: printf ("\tm68k_do_rts_ce030 ();\n");
2362: else if (using_ce)
2363: printf ("\tm68k_do_rts_ce ();\n");
2364: else if (using_indirect)
2365: printf ("\tm68k_do_rtsi ();\n");
2366: else if (using_mmu)
2367: printf ("\tm68k_do_rts_mmu ();\n");
2368: else
2369: printf ("\tm68k_do_rts ();\n");
2370: printf ("\tif (m68k_getpc () & 1) {\n");
2371: printf ("\t\tuaecptr faultpc = m68k_getpc ();\n");
2372: printf ("\t\tm68k_setpc (pc);\n");
2373: printf ("\t\texception3i (0x%04X, pc, faultpc);\n", opcode);
2374: printf ("\t\tgoto %s;\n", endlabelstr);
2375: printf ("\t}\n");
2376: count_read += 2;
2377: m68k_pc_offset = 0;
2378: fill_prefetch_full ();
2379: need_endlabel = 1;
2380: break;
2381: case i_TRAPV:
2382: sync_m68k_pc ();
2383: fill_prefetch_next ();
2384: printf ("\tif (GET_VFLG ()) {\n");
2385: printf ("\t\tException (7, m68k_getpc () ,M68000_EXC_SRC_CPU);\n");
2386: printf ("\t\tgoto %s;\n", endlabelstr);
2387: printf ("\t}\n");
2388: need_endlabel = 1;
2389: break;
2390: case i_RTR:
2391: printf ("\tMakeSR ();\n");
2392: genamode_pre (Aipi, "7", sz_word, "sr", 1, 0, 0);
2393: genamode (Aipi, "7", sz_long, "pc", 1, 0, 0);
2394: genamode_post (Aipi, "7", sz_word, "sr", 1, 0, 0);
2395: printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
2396: printf ("\tregs.sr |= sr;\n");
2397: setpc ("pc");
2398: printf ("\tMakeFromSR ();\n");
2399: m68k_pc_offset = 0;
2400: fill_prefetch_full ();
2401: break;
2402: case i_JSR: // TODO: check stack write order
2403: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA|GF_NOREFILL);
2404: start_brace ();
2405: printf ("\tuaecptr oldpc = m68k_getpc () + %d;\n", m68k_pc_offset);
2406: if (using_exception_3) {
2407: printf ("\tif (srca & 1) {\n");
2408: printf ("\t\texception3i (opcode, oldpc, srca);\n");
2409: printf ("\t\tgoto %s;\n", endlabelstr);
2410: printf ("\t}\n");
2411: need_endlabel = 1;
2412: }
2413: if (using_mmu) {
2414: printf ("\t%s (m68k_areg (regs, 7) - 4, oldpc);\n", dstl);
2415: printf ("\tm68k_areg (regs, 7) -= 4;\n");
2416: setpc ("srca");
2417: m68k_pc_offset = 0;
2418: } else {
2419: if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16)
2420: addcycles000 (2);
2421: setpc ("srca");
2422: m68k_pc_offset = 0;
2423: fill_prefetch_1 (0);
2424: if (curi->smode == Ad8r || curi->smode == PC8r)
2425: addcycles000 (6);
2426: printf ("\tm68k_areg (regs, 7) -= 4;\n");
2427: if (using_ce) {
2428: printf ("\tput_word_ce (m68k_areg (regs, 7), oldpc >> 16);\n");
2429: printf ("\tput_word_ce (m68k_areg (regs, 7) + 2, oldpc);\n");
2430: } else {
2431: printf ("\t%s (m68k_areg (regs, 7), oldpc);\n", dstl);
2432: }
2433: }
2434: count_write += 2;
2435: fill_prefetch_next ();
2436: break;
2437: case i_JMP:
2438: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA | ((curi->smode == Ad8r || curi->smode == PC8r) ? 0 : GF_NOREFILL));
2439: if (using_exception_3) {
2440: printf ("\tif (srca & 1) {\n");
2441: printf ("\t\texception3i (opcode, m68k_getpc () + 6, srca);\n");
2442: printf ("\t\tgoto %s;\n", endlabelstr);
2443: printf ("\t}\n");
2444: need_endlabel = 1;
2445: }
2446: if (curi->smode == Ad16 || curi->smode == Ad8r || curi->smode == absw || curi->smode == PC16 || curi->smode == PC8r)
2447: addcycles000 (2);
2448: setpc ("srca");
2449: m68k_pc_offset = 0;
2450: fill_prefetch_full ();
2451: break;
2452: case i_BSR:
2453: // .b and .w confirmed
2454: printf ("\tuae_s32 s;\n");
2455: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA|GF_NOREFILL);
2456: printf ("\ts = (uae_s32)src + 2;\n");
2457: if (using_exception_3) {
2458: printf ("\tif (src & 1) {\n");
2459: printf ("\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + s);\n");
2460: printf ("\t\tgoto %s;\n", endlabelstr);
2461: printf ("\t}\n");
2462: need_endlabel = 1;
2463: }
2464: addcycles000 (2);
2465: if (using_ce020 == 1) {
2466: printf ("\tm68k_do_bsr_ce020 (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2467: } else if (using_ce020 == 2) {
2468: printf ("\tm68k_do_bsr_ce030 (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2469: } else if (using_ce) {
2470: printf ("\tm68k_do_bsr_ce (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2471: } else if (using_indirect) {
2472: printf ("\tm68k_do_bsri (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2473: } else if (using_mmu) {
2474: printf ("\tm68k_do_bsr_mmu (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2475: } else {
2476: printf ("\tm68k_do_bsr (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2477: }
2478: count_write += 2;
2479: m68k_pc_offset = 0;
2480: fill_prefetch_full ();
2481: break;
2482: case i_Bcc:
2483: // bcc.b branch: idle cycle, prefetch, prefetch
2484: // bcc.b not branch: 2 idle cycles, prefetch
1.1.1.2 ! root 2485:
! 2486: instr_table = TABLE_FALCON_CYCLES_BCC;
! 2487:
1.1 root 2488: if (curi->size == sz_long) {
2489: if (cpu_level < 2) {
2490: addcycles000 (2);
2491: printf ("\tif (cctrue (%d)) {\n", curi->cc);
2492: printf ("\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + 1);\n");
2493: printf ("\t\tgoto %s;\n", endlabelstr);
2494: printf ("\t}\n");
2495: sync_m68k_pc ();
2496: irc2ir ();
2497: fill_prefetch_2 ();
2498: printf ("\tgoto %s;\n", endlabelstr);
2499: need_endlabel = 1;
2500: } else {
2501: if (next_cpu_level < 1)
2502: next_cpu_level = 1;
2503: }
2504: }
2505: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_NOREFILL);
2506: addcycles000 (2);
2507: printf ("\tif (!cctrue (%d)) goto didnt_jump;\n", curi->cc);
2508: if (using_exception_3) {
2509: printf ("\tif (src & 1) {\n");
2510: printf ("\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + 2 + (uae_s32)src);\n");
2511: printf ("\t\tgoto %s;\n", endlabelstr);
2512: printf ("\t}\n");
2513: need_endlabel = 1;
2514: }
2515: if (using_prefetch) {
2516: incpc ("(uae_s32)src + 2");
2517: fill_prefetch_full ();
2518: if (using_ce)
2519: printf ("\treturn;\n");
2520: else
2521: printf ("\treturn 10 * CYCLE_UNIT / 2;\n");
2522: } else {
2523: incpc ("(uae_s32)src + 2");
1.1.1.2 ! root 2524: instr_table_index = 0;
! 2525: returncycles ("", 10);
1.1 root 2526: }
2527: printf ("didnt_jump:;\n");
2528: need_endlabel = 1;
2529: sync_m68k_pc ();
2530: if (curi->size == sz_byte) {
2531: addcycles000 (2);
2532: irc2ir ();
2533: fill_prefetch_2 ();
2534: } else if (curi->size == sz_word) {
2535: addcycles000 (2);
2536: fill_prefetch_full ();
2537: } else {
2538: fill_prefetch_full ();
2539: }
1.1.1.2 ! root 2540: if (using_ce020 == 2) {
! 2541: if (curi->size == sz_byte)
! 2542: instr_table_index = 1;
! 2543: else if (curi->size == sz_word)
! 2544: instr_table_index = 2;
! 2545: else
! 2546: instr_table_index = 3;
! 2547: }
1.1 root 2548: insn_n_cycles = curi->size == sz_byte ? 8 : 12;
2549: break;
2550: case i_LEA:
2551: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA);
2552: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, GF_AA);
2553: if (curi->smode == Ad8r || curi->smode == PC8r)
2554: addcycles000 (2);
2555: fill_prefetch_next ();
2556: if (curi->smode == Ad8r || curi->smode == PC8r)
2557: addcycles000 (2);
2558: genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
2559: break;
2560: case i_PEA:
2561: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA);
2562: genamode (Apdi, "7", sz_long, "dst", 2, 0, GF_AA);
2563: if (curi->smode == Ad8r || curi->smode == PC8r)
2564: addcycles000 (2);
2565: if (!(curi->smode == absw || curi->smode == absl))
2566: fill_prefetch_next ();
2567: if (curi->smode == Ad8r || curi->smode == PC8r)
2568: addcycles000 (2);
2569: genastore ("srca", Apdi, "7", sz_long, "dst");
2570: if ((curi->smode == absw || curi->smode == absl))
2571: fill_prefetch_next ();
2572: break;
2573: case i_DBcc:
2574: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_NOREFILL);
2575: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0, GF_AA | GF_NOREFILL);
2576: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2577: addcycles000 (2);
2578: printf ("\tif (!cctrue (%d)) {\n", curi->cc);
2579: incpc ("(uae_s32)offs + 2");
2580: printf ("\t"); fill_prefetch_1 (0);
2581: printf ("\t"); genastore ("(src - 1)", curi->smode, "srcreg", curi->size, "src");
2582:
2583: printf ("\t\tif (src) {\n");
1.1.1.2 ! root 2584: addcycles_ce020 (0, 0, 4, 4);
1.1 root 2585: if (using_exception_3) {
2586: printf ("\t\t\tif (offs & 1) {\n");
2587: printf ("\t\t\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + 2 + (uae_s32)offs + 2);\n");
2588: printf ("\t\t\t\tgoto %s;\n", endlabelstr);
2589: printf ("\t\t\t}\n");
2590: need_endlabel = 1;
2591: }
2592: irc2ir ();
2593: fill_prefetch_1 (2);
2594: returncycles ("\t\t\t", 12);
2595: if (using_ce)
2596: printf ("\t\t\treturn;\n");
2597: printf ("\t\t}\n");
1.1.1.2 ! root 2598: addcycles_ce020 (0, 0, 8, 8);
1.1 root 2599: printf ("\t} else {\n");
2600: addcycles000_2 ("\t\t", 2);
1.1.1.2 ! root 2601: addcycles_ce020 (0, 0, 4, 4);
1.1 root 2602: printf ("\t}\n");
2603: setpc ("oldpc + %d", m68k_pc_offset);
2604: m68k_pc_offset = 0;
2605: fill_prefetch_full ();
2606: insn_n_cycles = 12;
2607: need_endlabel = 1;
2608: break;
2609: case i_Scc:
2610: // confirmed
2611: genamode (curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, 0);
2612: start_brace ();
2613: fill_prefetch_next();
2614: start_brace ();
2615: printf ("\tint val = cctrue (%d) ? 0xff : 0;\n", curi->cc);
2616: if (using_ce) {
2617: printf ("\tint cycles = 0;\n");
2618: if (isreg (curi->smode))
2619: printf ("\tif (val) cycles += 2;\n");
2620: addcycles000_3 ("\t");
2621: }
2622: genastore ("val", curi->smode, "srcreg", curi->size, "src");
2623: break;
2624: case i_DIVU:
2625: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2626: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2627: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
2628: printf ("\tCLEAR_CZNV ();\n");
2629: printf ("\tif (src == 0) {\n");
2630: if (cpu_level > 0) {
2631: /* 68020 sets V when dividing by zero and N if dst is negative
2632: * 68000 clears both
2633: */
2634: printf("\t\tSET_VFLG (1);\n");
2635: printf("\t\tif (dst < 0) SET_NFLG (1);\n");
2636: }
2637: incpc ("%d", m68k_pc_offset);
2638: printf ("\t\tException (5, oldpc ,M68000_EXC_SRC_CPU);\n");
2639: printf ("\t\tgoto %s;\n", endlabelstr);
2640: printf ("\t} else {\n");
2641: printf ("\t\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
2642: printf ("\t\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
2643: fill_prefetch_next ();
2644: if (using_ce) {
2645: start_brace ();
2646: printf ("\t\tint cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src));\n");
2647: addcycles000_3 ("\t\t");
2648: } else if (using_ce020) {
1.1.1.2 ! root 2649: addcycles_ce020 (0, 0, 36, 36);
1.1 root 2650: }
2651: /* The N flag appears to be set each time there is an overflow.
2652: * Weird. but 68020 only sets N when dst is negative.. */
2653: printf ("\t\tif (newv > 0xffff) {\n");
2654: printf ("\t\t\tSET_VFLG (1);\n");
2655: #ifdef UNDEF68020
2656: if (cpu_level >= 2)
2657: printf ("\t\t\tif (currprefs.cpu_level == 0 || dst < 0) SET_NFLG (®s, 1);\n");
2658: else /* ??? some 68000 revisions may not set NFLG when overflow happens.. */
2659: #endif
2660: printf ("\t\t\tSET_NFLG (1);\n");
2661: printf ("\t\t} else {\n");
2662: printf ("\t\t"); genflags (flag_logical, sz_word, "newv", "", "");
2663: printf ("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
2664: printf ("\t\t"); genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2665: printf ("\t\t}\n");
2666: sync_m68k_pc ();
2667: printf ("\t}\n");
2668: count_ncycles++;
2669: insn_n_cycles += 136 - (136 - 76) / 2; /* average */
2670: need_endlabel = 1;
2671: break;
2672: case i_DIVS:
2673: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2674: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2675: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
2676: printf ("\tCLEAR_CZNV ();\n");
2677: printf ("\tif (src == 0) {\n");
2678: if (cpu_level > 0) {
2679: /* 68020 sets V when dividing by zero. Z is also set.
2680: * 68000 clears both
2681: */
2682: printf("\t\tSET_VFLG (1);\n");
2683: printf("\t\tSET_ZFLG (1);\n");
2684: }
2685: incpc ("%d", m68k_pc_offset);
2686: printf ("\t\tException (5, oldpc ,M68000_EXC_SRC_CPU);\n");
2687: printf ("\t\tgoto %s;\n", endlabelstr);
2688: printf ("\t} else {\n");
2689: printf ("\t\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
2690: printf ("\t\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
2691: fill_prefetch_next ();
2692: if (using_ce) {
2693: start_brace ();
2694: printf ("\t\tint cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src));\n");
2695: addcycles000_3 ("\t\t");
2696: } else if (using_ce020) {
1.1.1.2 ! root 2697: addcycles_ce020 (0, 0, 46, 46);
1.1 root 2698: }
2699: printf ("\t\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {\n");
2700: printf ("\t\t\tSET_VFLG (1);\n");
2701: #ifdef UNDEF68020
2702: if (cpu_level > 0)
2703: printf ("\t\t\tif (currprefs.cpu_level == 0) SET_NFLG (®s, 1);\n");
2704: else
2705: #endif
2706: printf ("\t\t\tSET_NFLG (1);\n");
2707: printf ("\t\t} else {\n");
2708: printf ("\t\t\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
2709: genflags (flag_logical, sz_word, "newv", "", "");
2710: printf ("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
2711: printf ("\t\t"); genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2712: printf ("\t\t}\n");
2713: sync_m68k_pc ();
2714: printf ("\t}\n");
2715: count_ncycles++;
2716: insn_n_cycles += 156 - (156 - 120) / 2; /* average */
2717: need_endlabel = 1;
2718: break;
2719: case i_MULU:
2720: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2721: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0, 0);
2722: fill_prefetch_next();
2723: start_brace ();
2724: printf ("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
2725: if (using_ce)
2726: printf ("\tint cycles = 38 - 4, bits;\n");
2727: genflags (flag_logical, sz_long, "newv", "", "");
2728: if (using_ce) {
2729: printf ("\tfor(bits = 0; bits < 16 && src; bits++, src >>= 1)\n");
2730: printf ("\t\tif (src & 1) cycles += 2;\n");
2731: addcycles000_3 ("\t");
2732: } else if (using_ce020) {
1.1.1.2 ! root 2733: addcycles_ce020 (0, 0, 20, 20);
1.1 root 2734: }
2735: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2736: sync_m68k_pc ();
2737: count_cycles += 38 - 4;
2738: count_ncycles++;
2739: insn_n_cycles += (70 - 38) / 2 + 38; /* average */
2740: break;
2741: case i_MULS:
2742: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2743: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0, 0);
2744: fill_prefetch_next();
2745: start_brace ();
2746: printf ("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
2747: if (using_ce) {
2748: printf ("\tint cycles = 38 - 4, bits;\n");
2749: printf ("\tuae_u32 usrc;\n");
2750: }
2751: genflags (flag_logical, sz_long, "newv", "", "");
2752: if (using_ce) {
2753: printf ("\tusrc = ((uae_u32)src) << 1;\n");
2754: printf ("\tfor(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)\n");
2755: printf ("\t\tif ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;\n");
2756: addcycles000_3 ("\t");
2757: } else if (using_ce020) {
1.1.1.2 ! root 2758: addcycles_ce020 (0, 0, 20, 20);
1.1 root 2759: }
2760: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2761: count_cycles += 38 - 4;
2762: count_ncycles++;
2763: insn_n_cycles += (70 - 38) / 2 + 38; /* average */
2764: break;
2765: case i_CHK:
2766: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2767: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2768: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2769: sync_m68k_pc ();
2770: addcycles000 (4);
2771: printf ("\tif (dst > src) {\n");
2772: printf ("\t\tSET_NFLG (0);\n");
2773: printf ("\t\tException (6, oldpc ,M68000_EXC_SRC_CPU);\n");
2774: printf ("\t\tgoto %s;\n", endlabelstr);
2775: printf ("\t}\n");
2776: addcycles000 (2);
2777: printf ("\tif ((uae_s32)dst < 0) {\n");
2778: printf ("\t\tSET_NFLG (1);\n");
2779: printf ("\t\tException (6, oldpc ,M68000_EXC_SRC_CPU);\n");
2780: printf ("\t\tgoto %s;\n", endlabelstr);
2781: printf ("\t}\n");
2782: fill_prefetch_next ();
2783: need_endlabel = 1;
2784: break;
2785: case i_CHK2:
2786: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2787: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
2788: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
2789: fill_prefetch_0 ();
2790: printf ("\t{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
2791: switch (curi->size) {
2792: case sz_byte:
2793: printf ("\tlower = (uae_s32)(uae_s8)%s (dsta); upper = (uae_s32)(uae_s8)%s (dsta + 1);\n", srcb, srcb);
2794: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
1.1.1.2 ! root 2795: if (using_ce020 == 2) {
! 2796: instr_table = TABLE_FALCON_CYCLES_CHK2_BW;
! 2797: instr_table_index = chk2_b_index * 2;
! 2798: chk2_b_index ++;
! 2799: }
1.1 root 2800: break;
2801: case sz_word:
2802: printf ("\tlower = (uae_s32)(uae_s16)%s (dsta); upper = (uae_s32)(uae_s16)%s (dsta + 2);\n", srcw, srcw);
2803: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
1.1.1.2 ! root 2804: if (using_ce020 == 2) {
! 2805: instr_table = TABLE_FALCON_CYCLES_CHK2_BW;
! 2806: instr_table_index = chk2_w_index * 2;
! 2807: chk2_w_index ++;
! 2808: }
1.1 root 2809: break;
2810: case sz_long:
2811: printf ("\tlower = %s (dsta); upper = %s (dsta + 4);\n", srcl, srcl);
1.1.1.2 ! root 2812: if (using_ce020 == 2) {
! 2813: instr_table = TABLE_FALCON_CYCLES_CHK2_L;
! 2814: instr_table_index = chk2_l_index * 2;
! 2815: chk2_l_index ++;
! 2816: }
1.1 root 2817: break;
2818: default:
2819: abort ();
2820: }
2821: printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
2822: printf ("\tSET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1.1.1.2 ! root 2823: printf ("\tif ((extra & 0x800) && GET_CFLG ()) {\n");
! 2824: printf ("\t\tException (6, oldpc ,M68000_EXC_SRC_CPU);\n");
! 2825: instr_table_index ++; /* take the Exception cycle value in the CHK2 table */
! 2826: returncycles ("\t", 0);
! 2827: printf ("\t}\n}\n");
! 2828: instr_table_index --; /* take the No Exception cycle value in the CHK2 table */
1.1 root 2829: break;
2830:
2831: case i_ASR:
2832: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2833: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2834: fill_prefetch_next();
2835: start_brace ();
2836: switch (curi->size) {
2837: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2838: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2839: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2840: default: abort ();
2841: }
2842: printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
2843: printf ("\tint ccnt = cnt & 63;\n");
2844: printf ("\tcnt &= 63;\n");
2845: printf ("\tCLEAR_CZNV ();\n");
2846: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2847: printf ("\t\tval = %s & (uae_u32)-sign;\n", bit_mask (curi->size));
2848: printf ("\t\tSET_CFLG (sign);\n");
2849: duplicate_carry (1);
2850: if (source_is_imm1_8 (curi))
2851: printf ("\t} else {\n");
2852: else
2853: printf ("\t} else if (cnt > 0) {\n");
2854: printf ("\t\tval >>= cnt - 1;\n");
2855: printf ("\t\tSET_CFLG (val & 1);\n");
2856: duplicate_carry (1);
2857: printf ("\t\tval >>= 1;\n");
2858: printf ("\t\tval |= (%s << (%d - cnt)) & (uae_u32)-sign;\n",
2859: bit_mask (curi->size),
2860: bit_size (curi->size));
2861: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
2862: printf ("\t}\n");
2863: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2864: shift_ce (curi->dmode, curi->size);
2865: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2866: break;
2867: case i_ASL:
2868: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2869: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2870: fill_prefetch_next();
2871: start_brace ();
2872: switch (curi->size) {
2873: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2874: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2875: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2876: default: abort ();
2877: }
2878: printf ("\tint ccnt = cnt & 63;\n");
2879: printf ("\tcnt &= 63;\n");
2880: printf ("\tCLEAR_CZNV ();\n");
2881: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2882: printf ("\t\tSET_VFLG (val != 0);\n");
2883: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
2884: bit_size (curi->size));
2885: duplicate_carry (1);
2886: printf ("\t\tval = 0;\n");
2887: if (source_is_imm1_8 (curi))
2888: printf ("\t} else {\n");
2889: else
2890: printf ("\t} else if (cnt > 0) {\n");
2891: printf ("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
2892: bit_mask (curi->size),
2893: bit_size (curi->size) - 1,
2894: bit_mask (curi->size));
2895: printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
2896: printf ("\t\tval <<= cnt - 1;\n");
2897: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
2898: duplicate_carry (1);
2899: printf ("\t\tval <<= 1;\n");
2900: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
2901: printf ("\t}\n");
2902: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2903: shift_ce (curi->dmode, curi->size);
2904: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2905: break;
2906: case i_LSR:
2907: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2908: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2909: fill_prefetch_next();
2910: start_brace ();
2911: switch (curi->size) {
2912: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2913: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2914: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2915: default: abort ();
2916: }
2917: printf ("\tint ccnt = cnt & 63;\n");
2918: printf ("\tcnt &= 63;\n");
2919: printf ("\tCLEAR_CZNV ();\n");
2920: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2921: printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
2922: bit_size (curi->size), bit_size (curi->size) - 1);
2923: duplicate_carry (1);
2924: printf ("\t\tval = 0;\n");
2925: if (source_is_imm1_8 (curi))
2926: printf ("\t} else {\n");
2927: else
2928: printf ("\t} else if (cnt > 0) {\n");
2929: printf ("\t\tval >>= cnt - 1;\n");
2930: printf ("\t\tSET_CFLG (val & 1);\n");
2931: duplicate_carry (1);
2932: printf ("\t\tval >>= 1;\n");
2933: printf ("\t}\n");
2934: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2935: shift_ce (curi->dmode, curi->size);
2936: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2937: break;
2938: case i_LSL:
2939: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2940: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2941: fill_prefetch_next();
2942: start_brace ();
2943: switch (curi->size) {
2944: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2945: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2946: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2947: default: abort ();
2948: }
2949: printf ("\tint ccnt = cnt & 63;\n");
2950: printf ("\tcnt &= 63;\n");
2951: printf ("\tCLEAR_CZNV ();\n");
2952: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2953: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n", bit_size (curi->size));
2954: duplicate_carry (1);
2955: printf ("\t\tval = 0;\n");
2956: if (source_is_imm1_8 (curi))
2957: printf ("\t} else {\n");
2958: else
2959: printf ("\t} else if (cnt > 0) {\n");
2960: printf ("\t\tval <<= (cnt - 1);\n");
2961: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
2962: duplicate_carry (1);
2963: printf ("\t\tval <<= 1;\n");
2964: printf ("\tval &= %s;\n", bit_mask (curi->size));
2965: printf ("\t}\n");
2966: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2967: shift_ce (curi->dmode, curi->size);
2968: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2969: break;
2970: case i_ROL:
2971: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2972: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2973: fill_prefetch_next ();
2974: start_brace ();
2975: switch (curi->size) {
2976: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2977: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2978: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2979: default: abort ();
2980: }
2981: printf ("\tint ccnt = cnt & 63;\n");
2982: printf ("\tcnt &= 63;\n");
2983: printf ("\tCLEAR_CZNV ();\n");
2984: if (source_is_imm1_8 (curi))
2985: printf ("{");
2986: else
2987: printf ("\tif (cnt > 0) {\n");
2988: printf ("\tuae_u32 loval;\n");
2989: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
2990: printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
2991: printf ("\tval <<= cnt;\n");
2992: printf ("\tval |= loval;\n");
2993: printf ("\tval &= %s;\n", bit_mask (curi->size));
2994: printf ("\tSET_CFLG (val & 1);\n");
2995: printf ("}\n");
2996: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2997: shift_ce (curi->dmode, curi->size);
2998: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2999: break;
3000: case i_ROR:
3001: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3002: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3003: fill_prefetch_next ();
3004: start_brace ();
3005: switch (curi->size) {
3006: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3007: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3008: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3009: default: abort ();
3010: }
3011: printf ("\tint ccnt = cnt & 63;\n");
3012: printf ("\tcnt &= 63;\n");
3013: printf ("\tCLEAR_CZNV ();\n");
3014: if (source_is_imm1_8 (curi))
3015: printf ("{");
3016: else
3017: printf ("\tif (cnt > 0) {");
3018: printf ("\tuae_u32 hival;\n");
3019: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
3020: printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
3021: printf ("\tval >>= cnt;\n");
3022: printf ("\tval |= hival;\n");
3023: printf ("\tval &= %s;\n", bit_mask (curi->size));
3024: printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
3025: printf ("\t}\n");
3026: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3027: shift_ce (curi->dmode, curi->size);
3028: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3029: break;
3030: case i_ROXL:
3031: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3032: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3033: fill_prefetch_next ();
3034: start_brace ();
3035: switch (curi->size) {
3036: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3037: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3038: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3039: default: abort ();
3040: }
3041: printf ("\tint ccnt = cnt & 63;\n");
3042: printf ("\tcnt &= 63;\n");
3043: printf ("\tCLEAR_CZNV ();\n");
3044: if (source_is_imm1_8 (curi))
3045: printf ("{");
3046: else {
3047: force_range_for_rox ("cnt", curi->size);
3048: printf ("\tif (cnt > 0) {\n");
3049: }
3050: printf ("\tcnt--;\n");
3051: printf ("\t{\n\tuae_u32 carry;\n");
3052: printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
3053: printf ("\tcarry = loval & 1;\n");
3054: printf ("\tval = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);\n");
3055: printf ("\tSET_XFLG (carry);\n");
3056: printf ("\tval &= %s;\n", bit_mask (curi->size));
3057: printf ("\t} }\n");
3058: printf ("\tSET_CFLG (GET_XFLG ());\n");
3059: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3060: shift_ce (curi->dmode, curi->size);
3061: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3062: break;
3063: case i_ROXR:
3064: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3065: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3066: fill_prefetch_next ();
3067: start_brace ();
3068: switch (curi->size) {
3069: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3070: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3071: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3072: default: abort ();
3073: }
3074: printf ("\tint ccnt = cnt & 63;\n");
3075: printf ("\tcnt &= 63;\n");
3076: printf ("\tCLEAR_CZNV ();\n");
3077: if (source_is_imm1_8 (curi))
3078: printf ("{");
3079: else {
3080: force_range_for_rox ("cnt", curi->size);
3081: printf ("\tif (cnt > 0) {\n");
3082: }
3083: printf ("\tcnt--;\n");
3084: printf ("\t{\n\tuae_u32 carry;\n");
3085: printf ("\tuae_u32 hival = (val << 1) | GET_XFLG ();\n");
3086: printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
3087: printf ("\tval >>= cnt;\n");
3088: printf ("\tcarry = val & 1;\n");
3089: printf ("\tval >>= 1;\n");
3090: printf ("\tval |= hival;\n");
3091: printf ("\tSET_XFLG (carry);\n");
3092: printf ("\tval &= %s;\n", bit_mask (curi->size));
3093: printf ("\t} }\n");
3094: printf ("\tSET_CFLG (GET_XFLG ());\n");
3095: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3096: shift_ce (curi->dmode, curi->size);
3097: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3098: break;
3099: case i_ASRW:
3100: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3101: fill_prefetch_next ();
3102: start_brace ();
3103: switch (curi->size) {
3104: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3105: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3106: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3107: default: abort ();
3108: }
3109: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
3110: printf ("\tuae_u32 cflg = val & 1;\n");
3111: printf ("\tval = (val >> 1) | sign;\n");
3112: genflags (flag_logical, curi->size, "val", "", "");
3113: printf ("\tSET_CFLG (cflg);\n");
3114: duplicate_carry (0);
3115: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3116: break;
3117: case i_ASLW:
3118: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3119: fill_prefetch_next ();
3120: start_brace ();
3121: switch (curi->size) {
3122: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3123: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3124: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3125: default: abort ();
3126: }
3127: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
3128: printf ("\tuae_u32 sign2;\n");
3129: printf ("\tval <<= 1;\n");
3130: genflags (flag_logical, curi->size, "val", "", "");
3131: printf ("\tsign2 = %s & val;\n", cmask (curi->size));
3132: printf ("\tSET_CFLG (sign != 0);\n");
3133: duplicate_carry (0);
3134:
3135: printf ("\tSET_VFLG (GET_VFLG () | (sign2 != sign));\n");
3136: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3137: break;
3138: case i_LSRW:
3139: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3140: fill_prefetch_next ();
3141: start_brace ();
3142: switch (curi->size) {
3143: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3144: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3145: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3146: default: abort ();
3147: }
3148: printf ("\tuae_u32 carry = val & 1;\n");
3149: printf ("\tval >>= 1;\n");
3150: genflags (flag_logical, curi->size, "val", "", "");
3151: printf ("\tSET_CFLG (carry);\n");
3152: duplicate_carry (0);
3153: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3154: break;
3155: case i_LSLW:
3156: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3157: fill_prefetch_next ();
3158: start_brace ();
3159: switch (curi->size) {
3160: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3161: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3162: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3163: default: abort ();
3164: }
3165: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
3166: printf ("\tval <<= 1;\n");
3167: genflags (flag_logical, curi->size, "val", "", "");
3168: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
3169: duplicate_carry (0);
3170: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3171: break;
3172: case i_ROLW:
3173: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3174: fill_prefetch_next ();
3175: start_brace ();
3176: switch (curi->size) {
3177: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3178: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3179: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3180: default: abort ();
3181: }
3182: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
3183: printf ("\tval <<= 1;\n");
3184: printf ("\tif (carry) val |= 1;\n");
3185: genflags (flag_logical, curi->size, "val", "", "");
3186: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
3187: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3188: break;
3189: case i_RORW:
3190: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3191: fill_prefetch_next ();
3192: start_brace ();
3193: switch (curi->size) {
3194: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3195: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3196: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3197: default: abort ();
3198: }
3199: printf ("\tuae_u32 carry = val & 1;\n");
3200: printf ("\tval >>= 1;\n");
3201: printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
3202: genflags (flag_logical, curi->size, "val", "", "");
3203: printf ("\tSET_CFLG (carry);\n");
3204: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3205: break;
3206: case i_ROXLW:
3207: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3208: fill_prefetch_next ();
3209: start_brace ();
3210: switch (curi->size) {
3211: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3212: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3213: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3214: default: abort ();
3215: }
3216: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
3217: printf ("\tval <<= 1;\n");
3218: printf ("\tif (GET_XFLG ()) val |= 1;\n");
3219: genflags (flag_logical, curi->size, "val", "", "");
3220: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
3221: duplicate_carry (0);
3222: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3223: break;
3224: case i_ROXRW:
3225: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3226: fill_prefetch_next ();
3227: start_brace ();
3228: switch (curi->size) {
3229: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3230: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3231: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3232: default: abort ();
3233: }
3234: printf ("\tuae_u32 carry = val & 1;\n");
3235: printf ("\tval >>= 1;\n");
3236: printf ("\tif (GET_XFLG ()) val |= %s;\n", cmask (curi->size));
3237: genflags (flag_logical, curi->size, "val", "", "");
3238: printf ("\tSET_CFLG (carry);\n");
3239: duplicate_carry (0);
3240: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3241: break;
3242: case i_MOVEC2:
3243: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3244: fill_prefetch_next ();
3245: start_brace ();
3246: printf ("\tint regno = (src >> 12) & 15;\n");
3247: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
3248: printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
3249: break;
3250: case i_MOVE2C:
3251: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3252: fill_prefetch_next ();
3253: start_brace ();
3254: printf ("\tint regno = (src >> 12) & 15;\n");
3255: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
3256: printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
3257: break;
3258: case i_CAS:
3259: {
1.1.1.2 ! root 3260: if (using_ce020 == 2) {
! 3261: no_return_cycles = true;
! 3262: if (curi->size == sz_byte) {
! 3263: instr_table = TABLE_FALCON_CYCLES_CAS_BW;
! 3264: instr_table_index = cas_b_index * 2;
! 3265: cas_b_index ++;
! 3266: }
! 3267: else if (curi->size == sz_word) {
! 3268: instr_table = TABLE_FALCON_CYCLES_CAS_BW;
! 3269: instr_table_index = cas_w_index * 2;
! 3270: cas_w_index ++;
! 3271: }
! 3272: else {
! 3273: instr_table = TABLE_FALCON_CYCLES_CAS_L;
! 3274: instr_table_index = cas_l_index * 2;
! 3275: cas_l_index ++;
! 3276: }
! 3277: }
1.1 root 3278: int old_brace_level;
3279: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3280: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3281: fill_prefetch_0 ();
3282: start_brace ();
3283: printf ("\tint ru = (src >> 6) & 7;\n");
3284: printf ("\tint rc = src & 7;\n");
3285: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, rc)", "dst");
3286: printf ("\tif (GET_ZFLG ())");
3287: old_brace_level = n_braces;
3288: start_brace ();
3289: genastore ("(m68k_dreg (regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 ! root 3290: if (using_ce020 == 2)
! 3291: printf ("\tregs.ce030_instr_cycles = %s[%d];\n", falcon_cycles_tables[instr_table], instr_table_index);
1.1 root 3292: pop_braces (old_brace_level);
3293: printf ("else");
3294: start_brace ();
3295: printf ("m68k_dreg (regs, rc) = dst;\n");
1.1.1.2 ! root 3296: if (using_ce020 == 2)
! 3297: printf ("\tregs.ce030_instr_cycles = %s[%d];\n", falcon_cycles_tables[instr_table], instr_table_index + 1);
1.1 root 3298: pop_braces (old_brace_level);
3299: }
3300: break;
3301: case i_CAS2:
3302: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3303: printf ("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
3304: printf ("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
3305: if (curi->size == sz_word) {
3306: int old_brace_level = n_braces;
3307: printf ("\tuae_u16 dst1 = %s (rn1), dst2 = %s (rn2);\n", srcw, srcw);
3308: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, (extra >> 16) & 7)", "dst1");
3309: printf ("\tif (GET_ZFLG ()) {\n");
3310: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, extra & 7)", "dst2");
3311: printf ("\tif (GET_ZFLG ()) {\n");
3312: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 22) & 7));\n", dstw);
3313: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 6) & 7));\n", dstw);
3314: printf ("\t}}\n");
3315: pop_braces (old_brace_level);
3316: printf ("\tif (! GET_ZFLG ()) {\n");
3317: printf ("\tm68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
3318: printf ("\tm68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
3319: printf ("\t}\n");
3320: } else {
3321: int old_brace_level = n_braces;
3322: printf ("\tuae_u32 dst1 = %s (rn1), dst2 = %s (rn2);\n", srcl, srcl);
3323: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, (extra >> 16) & 7)", "dst1");
3324: printf ("\tif (GET_ZFLG ()) {\n");
3325: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, extra & 7)", "dst2");
3326: printf ("\tif (GET_ZFLG ()) {\n");
3327: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 22) & 7));\n", dstl);
3328: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 6) & 7));\n", dstl);
3329: printf ("\t}}\n");
3330: pop_braces (old_brace_level);
3331: printf ("\tif (! GET_ZFLG ()) {\n");
3332: printf ("\tm68k_dreg (regs, (extra >> 22) & 7) = dst1;\n");
3333: printf ("\tm68k_dreg (regs, (extra >> 6) & 7) = dst2;\n");
3334: printf ("\t}\n");
3335: }
3336: break;
3337: case i_MOVES: /* ignore DFC and SFC when using_mmu == false */
3338: {
3339: int old_brace_level;
3340: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3341: printf ("\tif (extra & 0x800)\n");
3342: {
3343: int old_m68k_pc_offset = m68k_pc_offset;
3344: old_brace_level = n_braces;
3345: start_brace ();
3346: printf ("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
3347: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
3348: genastore_fc ("src", curi->dmode, "dstreg", curi->size, "dst");
3349: pop_braces (old_brace_level);
3350: m68k_pc_offset = old_m68k_pc_offset;
3351: }
3352: printf ("else");
3353: {
3354: start_brace ();
3355: genamode (curi->dmode, "dstreg", curi->size, "src", 1, 0, GF_FC);
3356: printf ("\tif (extra & 0x8000) {\n");
3357: switch (curi->size) {
3358: case sz_byte: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
3359: case sz_word: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
3360: case sz_long: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = src;\n"); break;
3361: default: abort ();
3362: }
3363: printf ("\t} else {\n");
3364: genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
3365: printf ("\t}\n");
3366: sync_m68k_pc ();
3367: pop_braces (old_brace_level);
3368: }
3369: }
3370: break;
3371: case i_BKPT: /* only needed for hardware emulators */
3372: sync_m68k_pc ();
3373: printf ("\top_illg (opcode);\n");
3374: break;
3375: case i_CALLM: /* not present in 68030 */
3376: sync_m68k_pc ();
3377: printf ("\top_illg (opcode);\n");
3378: break;
3379: case i_RTM: /* not present in 68030 */
3380: sync_m68k_pc ();
3381: printf ("\top_illg (opcode);\n");
3382: break;
3383: case i_TRAPcc:
3384: if (curi->smode != am_unknown && curi->smode != am_illg)
3385: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
3386: fill_prefetch_0 ();
3387: printf ("\tif (cctrue (%d)) { Exception (7, m68k_getpc () ,M68000_EXC_SRC_CPU); goto %s; }\n", curi->cc, endlabelstr);
3388: need_endlabel = 1;
3389: break;
3390: case i_DIVL:
3391: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
3392: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3393: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3394: if (using_ce020) {
1.1.1.2 ! root 3395: addcycles_ce020 (0, 0, 70, 70);
1.1 root 3396: }
3397: sync_m68k_pc ();
3398: printf ("\tm68k_divl(opcode, dst, extra, oldpc);\n");
3399: break;
3400: case i_MULL:
3401: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3402: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3403: if (using_ce020) {
1.1.1.2 ! root 3404: addcycles_ce020 (0, 0, 40, 40);
1.1 root 3405: }
3406: sync_m68k_pc ();
3407: printf ("\tm68k_mull(opcode, dst, extra);\n");
3408: break;
3409: case i_BFTST:
3410: case i_BFEXTU:
3411: case i_BFCHG:
3412: case i_BFEXTS:
3413: case i_BFCLR:
3414: case i_BFFFO:
3415: case i_BFSET:
3416: case i_BFINS:
3417: {
3418: const char *getb, *putb;
3419:
3420: if (using_mmu || using_ce020) {
3421: getb = "x_get_bitfield";
3422: putb = "x_put_bitfield";
3423: } else {
3424: getb = "get_bitfield";
3425: putb = "put_bitfield";
3426: }
3427:
3428: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3429: genamode (curi->dmode, "dstreg", sz_long, "dst", 2, 0, 0);
3430: start_brace ();
3431: printf ("\tuae_u32 bdata[2];\n");
3432: printf ("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
3433: printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
3434: if (curi->dmode == Dreg) {
3435: printf ("\tuae_u32 tmp = m68k_dreg(regs, dstreg);\n");
3436: printf ("\toffset &= 0x1f;\n");
3437: printf ("\ttmp = (tmp << offset) | (tmp >> (32 - offset));\n");
3438: printf ("\tbdata[0] = tmp & ((1 << (32 - width)) - 1);\n");
3439: } else {
3440: printf ("\tuae_u32 tmp;\n");
3441: printf ("\tdsta += offset >> 3;\n");
3442: printf ("\ttmp = %s (dsta, bdata, offset, width);\n", getb);
3443: }
3444: printf ("\tSET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);\n");
3445: if (curi->mnemo == i_BFEXTS)
3446: printf ("\ttmp = (uae_s32)tmp >> (32 - width);\n");
3447: else
3448: printf ("\ttmp >>= (32 - width);\n");
3449: printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
3450: switch (curi->mnemo) {
3451: case i_BFTST:
3452: break;
3453: case i_BFEXTU:
3454: case i_BFEXTS:
3455: printf ("\tm68k_dreg (regs, (extra >> 12) & 7) = tmp;\n");
3456: break;
3457: case i_BFCHG:
3458: printf ("\ttmp = tmp ^ (0xffffffffu >> (32 - width));\n");
3459: break;
3460: case i_BFCLR:
3461: printf ("\ttmp = 0;\n");
3462: break;
3463: case i_BFFFO:
3464: printf ("\t{ uae_u32 mask = 1 << (width - 1);\n");
3465: printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n");
3466: printf ("\tm68k_dreg (regs, (extra >> 12) & 7) = offset;\n");
3467: break;
3468: case i_BFSET:
3469: printf ("\ttmp = 0xffffffffu >> (32 - width);\n");
3470: break;
3471: case i_BFINS:
3472: printf ("\ttmp = m68k_dreg (regs, (extra >> 12) & 7);\n");
3473: printf ("\ttmp = tmp & (0xffffffffu >> (32 - width));\n");
3474: printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
3475: printf ("\tSET_ZFLG (tmp == 0);\n");
3476: break;
3477: default:
3478: break;
3479: }
3480: if (curi->mnemo == i_BFCHG
3481: || curi->mnemo == i_BFCLR
3482: || curi->mnemo == i_BFSET
3483: || curi->mnemo == i_BFINS) {
3484: if (curi->dmode == Dreg) {
3485: printf ("\ttmp = bdata[0] | (tmp << (32 - width));\n");
3486: printf ("\tm68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));\n");
3487: } else {
3488: printf ("\t%s(dsta, bdata, tmp, offset, width);\n", putb);
3489: }
3490: }
3491: }
3492: break;
3493: case i_PACK:
3494: if (curi->smode == Dreg) {
3495: printf ("\tuae_u16 val = m68k_dreg (regs, srcreg) + %s;\n", gen_nextiword (0));
3496: printf ("\tm68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
3497: } else {
3498: printf ("\tuae_u16 val;\n");
3499: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
3500: printf ("\tval = (uae_u16)%s (m68k_areg (regs, srcreg));\n", srcb);
3501: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
3502: printf ("\tval = (val | ((uae_u16)%s (m68k_areg (regs, srcreg)) << 8)) + %s;\n", srcb, gen_nextiword (0));
3503: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
3504: gen_set_fault_pc ();
3505: printf ("\t%s (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n", dstb);
3506: }
3507: break;
3508: case i_UNPK:
3509: if (curi->smode == Dreg) {
3510: printf ("\tuae_u16 val = m68k_dreg (regs, srcreg);\n");
3511: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
3512: printf ("\tm68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
3513: } else {
3514: printf ("\tuae_u16 val;\n");
3515: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
3516: printf ("\tval = (uae_u16)%s (m68k_areg (regs, srcreg));\n", srcb);
3517: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
3518: if (cpu_level >= 2) {
3519: printf ("\tm68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];\n");
3520: printf ("\t%s (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);\n", dstb);
3521: printf ("\t%s (m68k_areg (regs, dstreg), val >> 8);\n", dstb);
3522: } else {
3523: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
3524: printf ("\t%s (m68k_areg (regs, dstreg),val);\n", dstb);
3525: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
3526: gen_set_fault_pc ();
3527: printf ("\t%s (m68k_areg (regs, dstreg),val >> 8);\n", dstb);
3528: }
3529: }
3530: break;
3531: case i_TAS:
3532: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3533: genflags (flag_logical, curi->size, "src", "", "");
3534: if (!isreg (curi->smode))
3535: addcycles000 (2);
3536: fill_prefetch_next ();
3537: printf ("\tsrc |= 0x80;\n");
3538: if (cpu_level >= 2 || curi->smode == Dreg || !using_ce) {
3539: if (next_cpu_level < 2)
3540: next_cpu_level = 2 - 1;
3541: genastore ("src", curi->smode, "srcreg", curi->size, "src");
3542: } else {
3543: printf ("\tif (!is_cycle_ce ()) {\n");
3544: genastore ("src", curi->smode, "srcreg", curi->size, "src");
3545: printf ("\t} else {\n");
3546: printf ("\t\tdo_cycles_ce000 (4);\n");
3547: printf ("\t}\n");
3548: }
3549: break;
3550: case i_FPP:
3551: fpulimit();
3552: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3553: sync_m68k_pc ();
3554: printf ("\tfpuop_arithmetic(opcode, extra);\n");
3555: break;
3556: case i_FDBcc:
3557: fpulimit();
3558: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3559: sync_m68k_pc ();
3560: printf ("\tfpuop_dbcc (opcode, extra);\n");
3561: break;
3562: case i_FScc:
3563: fpulimit();
3564: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3565: sync_m68k_pc ();
3566: printf ("\tfpuop_scc (opcode, extra);\n");
3567: break;
3568: case i_FTRAPcc:
3569: fpulimit();
3570: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
3571: printf ("\tuae_u16 extra = %s;\n", gen_nextiword (0));
3572: if (curi->smode != am_unknown && curi->smode != am_illg)
3573: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
3574: sync_m68k_pc ();
3575: printf ("\tfpuop_trapcc (opcode, oldpc, extra);\n");
3576: break;
3577: case i_FBcc:
3578: fpulimit();
3579: sync_m68k_pc ();
3580: start_brace ();
3581: printf ("\tuaecptr pc = m68k_getpc ();\n");
3582: genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0, 0);
3583: sync_m68k_pc ();
3584: printf ("\tfpuop_bcc (opcode, pc,extra);\n");
3585: break;
3586: case i_FSAVE:
3587: fpulimit();
3588: sync_m68k_pc ();
3589: printf ("\tfpuop_save (opcode);\n");
3590: break;
3591: case i_FRESTORE:
3592: fpulimit();
3593: sync_m68k_pc ();
3594: printf ("\tfpuop_restore (opcode);\n");
3595: break;
3596:
3597: case i_CINVL:
3598: case i_CINVP:
3599: case i_CINVA:
3600: case i_CPUSHL:
3601: case i_CPUSHP:
3602: case i_CPUSHA:
3603: if (using_mmu)
3604: printf ("\tflush_mmu(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);\n");
3605: printf ("\tif (opcode & 0x80)\n");
3606: printf ("\t\tflush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);\n");
3607: break;
3608:
3609: case i_MOVE16:
3610: {
3611: if ((opcode & 0xfff8) == 0xf620) {
3612: /* MOVE16 (Ax)+,(Ay)+ */
3613: printf ("\tuae_u32 v1, v2, v3, v4;\n");
3614: printf ("\tuaecptr mems = m68k_areg (regs, srcreg) & ~15, memd;\n");
3615: printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword (0));
3616: printf ("\tmemd = m68k_areg (regs, dstreg) & ~15;\n");
3617: printf ("\tv1 = %s (mems);\n", srcl);
3618: printf ("\tv2 = %s (mems + 4);\n", srcl);
3619: printf ("\tv3 = %s (mems + 8);\n", srcl);
3620: printf ("\tv4 = %s (mems + 12);\n", srcl);
3621: printf ("\t%s (memd , v1);\n", dstl);
3622: printf ("\t%s (memd + 4, v2);\n", dstl);
3623: printf ("\t%s (memd + 8, v3);\n", dstl);
3624: printf ("\t%s (memd + 12, v4);\n", dstl);
3625: printf ("\tif (srcreg != dstreg)\n");
3626: printf ("\t\tm68k_areg (regs, srcreg) += 16;\n");
3627: printf ("\tm68k_areg (regs, dstreg) += 16;\n");
3628: } else {
3629: /* Other variants */
3630: printf ("\tuae_u32 v1, v2, v3, v4;\n");
3631: genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2, 0);
3632: genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2, 0);
3633: printf ("\tmemsa &= ~15;\n");
3634: printf ("\tmemda &= ~15;\n");
3635: printf ("\tv1 = %s (memsa);\n", srcl);
3636: printf ("\tv2 = %s (memsa + 4);\n", srcl);
3637: printf ("\tv3 = %s (memsa + 8);\n", srcl);
3638: printf ("\tv4 = %s (memsa + 12);\n", srcl);
3639: printf ("\t%s (memda , v1);\n", dstl);
3640: printf ("\t%s (memda + 4, v2);\n", dstl);
3641: printf ("\t%s (memda + 8, v3);\n", dstl);
3642: printf ("\t%s (memda + 12, v4);\n", dstl);
3643: if ((opcode & 0xfff8) == 0xf600)
3644: printf ("\tm68k_areg (regs, srcreg) += 16;\n");
3645: else if ((opcode & 0xfff8) == 0xf608)
3646: printf ("\tm68k_areg (regs, dstreg) += 16;\n");
3647: }
3648: }
3649: break;
3650:
3651: case i_PFLUSHN:
3652: case i_PFLUSH:
3653: case i_PFLUSHAN:
3654: case i_PFLUSHA:
3655: case i_PLPAR:
3656: case i_PLPAW:
3657: case i_PTESTR:
3658: case i_PTESTW:
3659: sync_m68k_pc ();
3660: printf ("\tmmu_op (opcode, 0);\n");
3661: break;
3662: case i_MMUOP030:
3663: printf ("\tuaecptr pc = m68k_getpc ();\n");
3664: printf ("\tuae_u16 extra = x_get_word (pc + 2);\n");
3665: m68k_pc_offset += 2;
3666: sync_m68k_pc ();
3667: if (curi->smode == Areg || curi->smode == Dreg)
3668: printf("\tuae_u16 extraa = 0;\n");
3669: else
3670: genamode (curi->smode, "srcreg", curi->size, "extra", 0, 0, 0);
3671: sync_m68k_pc ();
3672: printf ("\tmmu_op30 (pc, opcode, extra, extraa);\n");
3673: break;
3674: default:
3675: abort ();
3676: break;
3677: }
3678: finish_braces ();
3679: if (limit_braces) {
3680: printf ("\n#endif\n");
3681: n_braces = limit_braces;
3682: limit_braces = 0;
3683: finish_braces ();
3684: }
3685: if (did_prefetch >= 0)
3686: fill_prefetch_finish ();
3687: if (!count_cycles)
1.1.1.2 ! root 3688: addcycles_ce020 (0, 0, 2, 2);
1.1 root 3689: sync_m68k_pc ();
3690: did_prefetch = 0;
3691: }
3692:
3693: static void generate_includes (FILE * f)
3694: {
1.1.1.2 ! root 3695: /* fprintf (f, "#include \"sysconfig.h\"\n");
1.1 root 3696: fprintf (f, "#include \"sysdeps.h\"\n");
3697: fprintf (f, "#include \"options_cpu.h\"\n");
3698: fprintf (f, "#include \"memory.h\"\n");
3699: fprintf (f, "#include \"custom.h\"\n");
3700: fprintf (f, "#include \"events.h\"\n");
3701: fprintf (f, "#include \"newcpu.h\"\n");
3702: fprintf (f, "#include \"cpu_prefetch.h\"\n");
3703: fprintf (f, "#include \"cputbl.h\"\n");
3704: fprintf (f, "#include \"main.h\"\n");
3705: fprintf (f, "#include \"cpummu.h\"\n");
1.1.1.2 ! root 3706: */
! 3707: fprintf (f, "#include \"sysdeps.h\"\n");
! 3708: fprintf (f, "#include \"hatari-glue.h\"\n");
! 3709: fprintf (f, "#include \"maccess.h\"\n");
! 3710: fprintf (f, "#include \"memory.h\"\n");
! 3711: fprintf (f, "#include \"custom.h\"\n");
! 3712: fprintf (f, "#include \"newcpu.h\"\n");
! 3713: fprintf (f, "#include \"cpu_prefetch.h\"\n");
! 3714: fprintf (f, "#include \"cputbl.h\"\n");
! 3715: fprintf (f, "#include \"main.h\"\n");
! 3716: fprintf (f, "#include \"cpummu.h\"\n");
1.1 root 3717:
3718: fprintf (f, "#define CPUFUNC(x) x##_ff\n"
3719: "#define SET_CFLG_ALWAYS(x) SET_CFLG(x)\n"
3720: "#define SET_NFLG_ALWAYS(x) SET_NFLG(x)\n"
3721: "#ifdef NOFLAGS\n"
3722: "#include \"noflags.h\"\n"
3723: "#endif\n");
3724: }
3725:
3726: static int postfix;
3727:
3728:
3729: static char *decodeEA (amodes mode, wordsizes size)
3730: {
3731: static char buffer[80];
3732:
3733: buffer[0] = 0;
3734: switch (mode){
3735: case Dreg:
3736: strcpy (buffer,"Dn");
3737: break;
3738: case Areg:
3739: strcpy (buffer,"An");
3740: break;
3741: case Aind:
3742: strcpy (buffer,"(An)");
3743: break;
3744: case Aipi:
3745: strcpy (buffer,"(An)+");
3746: break;
3747: case Apdi:
3748: strcpy (buffer,"-(An)");
3749: break;
3750: case Ad16:
3751: strcpy (buffer,"(d16,An)");
3752: break;
3753: case Ad8r:
3754: strcpy (buffer,"(d8,An,Xn)");
3755: break;
3756: case PC16:
3757: strcpy (buffer,"(d16,PC)");
3758: break;
3759: case PC8r:
3760: strcpy (buffer,"(d8,PC,Xn)");
3761: break;
3762: case absw:
3763: strcpy (buffer,"(xxx).W");
3764: break;
3765: case absl:
3766: strcpy (buffer,"(xxx).L");
3767: break;
3768: case imm:
3769: switch (size){
3770: case sz_byte:
3771: strcpy (buffer,"#<data>.B");
3772: break;
3773: case sz_word:
3774: strcpy (buffer,"#<data>.W");
3775: break;
3776: case sz_long:
3777: strcpy (buffer,"#<data>.L");
3778: break;
3779: default:
3780: break;
3781: }
3782: break;
3783: case imm0:
3784: strcpy (buffer,"#<data>.B");
3785: break;
3786: case imm1:
3787: strcpy (buffer,"#<data>.W");
3788: break;
3789: case imm2:
3790: strcpy (buffer,"#<data>.L");
3791: break;
3792: case immi:
3793: strcpy (buffer,"#<data>");
3794: break;
3795:
3796: default:
3797: break;
3798: }
3799: return buffer;
3800: }
3801:
3802: static char *outopcode (int opcode)
3803: {
3804: static char out[100];
3805: struct instr *ins;
3806: int i;
3807:
3808: ins = &table68k[opcode];
3809: for (i = 0; lookuptab[i].name[0]; i++) {
3810: if (ins->mnemo == lookuptab[i].mnemo)
3811: break;
3812: }
3813: {
3814: // char *s = ua (lookuptab[i].name);
3815: const char *s = lookuptab[i].name;
3816: strcpy (out, s);
3817: //xfree (s);
3818: }
3819: if (ins->smode == immi)
3820: strcat (out, "Q");
3821: if (ins->size == sz_byte)
3822: strcat (out,".B");
3823: if (ins->size == sz_word)
3824: strcat (out,".W");
3825: if (ins->size == sz_long)
3826: strcat (out,".L");
3827: strcat (out," ");
3828: if (ins->suse)
3829: strcat (out, decodeEA (ins->smode, ins->size));
3830: if (ins->duse) {
3831: if (ins->suse) strcat (out,",");
3832: strcat (out, decodeEA (ins->dmode, ins->size));
3833: }
3834: return out;
3835: }
3836:
3837: static void generate_one_opcode (int rp)
3838: {
3839: int idx;
3840: uae_u16 smsk, dmsk;
3841: long int opcode = opcode_map[rp];
3842: int i68000 = table68k[opcode].clev > 0;
3843:
3844: if (table68k[opcode].mnemo == i_ILLG
3845: || table68k[opcode].clev > cpu_level)
3846: return;
3847:
3848: for (idx = 0; lookuptab[idx].name[0]; idx++) {
3849: if (table68k[opcode].mnemo == lookuptab[idx].mnemo)
3850: break;
3851: }
3852:
3853: if (table68k[opcode].handler != -1)
3854: return;
3855:
3856: if (opcode_next_clev[rp] != cpu_level) {
3857: //char *name = ua (lookuptab[idx].name);
3858: const char *name = lookuptab[idx].name;
3859: if (generate_stbl)
3860: fprintf (stblfile, "{ %sCPUFUNC(op_%04x_%d), %d }, /* %s */\n",
3861: (using_ce || using_ce020) ? "(cpuop_func*)" : "",
3862: opcode, opcode_last_postfix[rp],
3863: opcode, name);
3864: //xfree (name);
3865: return;
3866: }
3867: fprintf (headerfile, "extern %s op_%04lx_%d_nf;\n",
3868: (using_ce || using_ce020) ? "cpuop_func_ce" : "cpuop_func", opcode, postfix);
3869: fprintf (headerfile, "extern %s op_%04lx_%d_ff;\n",
3870: (using_ce || using_ce020) ? "cpuop_func_ce" : "cpuop_func", opcode, postfix);
3871: printf ("/* %s */\n", outopcode (opcode));
3872: if (i68000)
3873: printf("#ifndef CPUEMU_68000_ONLY\n");
3874: printf ("%s REGPARAM2 CPUFUNC(op_%04lx_%d)(uae_u32 opcode)\n{\n", (using_ce || using_ce020) ? "void" : "unsigned long", opcode, postfix);
3875:
3876: switch (table68k[opcode].stype) {
3877: case 0: smsk = 7; break;
3878: case 1: smsk = 255; break;
3879: case 2: smsk = 15; break;
3880: case 3: smsk = 7; break;
3881: case 4: smsk = 7; break;
3882: case 5: smsk = 63; break;
3883: case 7: smsk = 3; break;
3884: default: abort ();
3885: }
3886: dmsk = 7;
3887:
3888: next_cpu_level = -1;
3889: if (table68k[opcode].suse
3890: && table68k[opcode].smode != imm && table68k[opcode].smode != imm0
3891: && table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
3892: && table68k[opcode].smode != absw && table68k[opcode].smode != absl
3893: && table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
3894: {
3895: if (table68k[opcode].spos == -1) {
3896: if (((int) table68k[opcode].sreg) >= 128)
3897: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
3898: else
3899: printf ("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
3900: } else {
3901: char source[100];
3902: int pos = table68k[opcode].spos;
3903:
3904: if (pos)
3905: sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
3906: else
3907: sprintf (source, "(opcode & %d)", smsk);
3908:
3909: if (table68k[opcode].stype == 3)
3910: printf ("\tuae_u32 srcreg = imm8_table[%s];\n", source);
3911: else if (table68k[opcode].stype == 1)
3912: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
3913: else
3914: printf ("\tuae_u32 srcreg = %s;\n", source);
3915: }
3916: }
3917: if (table68k[opcode].duse
3918: /* Yes, the dmode can be imm, in case of LINK or DBcc */
3919: && table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
3920: && table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
3921: && table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
3922: {
3923: if (table68k[opcode].dpos == -1) {
3924: if (((int) table68k[opcode].dreg) >= 128)
3925: printf ("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
3926: else
3927: printf ("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
3928: } else {
3929: int pos = table68k[opcode].dpos;
3930: if (pos)
3931: printf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
3932: pos, dmsk);
3933: else
3934: printf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
3935: }
3936: }
3937: need_endlabel = 0;
3938: endlabelno++;
3939: sprintf (endlabelstr, "endlabel%d", endlabelno);
3940: count_read = count_write = count_ncycles = count_cycles = 0;
3941: count_read_ea = count_write_ea = count_cycles_ea = 0;
3942: gen_opcode (opcode);
3943: if (need_endlabel)
3944: printf ("%s: ;\n", endlabelstr);
1.1.1.2 ! root 3945:
1.1 root 3946: returncycles ("", insn_n_cycles);
1.1.1.2 ! root 3947:
1.1 root 3948: printf ("}");
3949: if (using_ce || using_prefetch) {
3950: if (count_read + count_write + count_cycles == 0)
3951: count_cycles = 4;
3952: printf (" /* %d%s (%d/%d)",
3953: (count_read + count_write) * 4 + count_cycles, count_ncycles ? "+" : "", count_read, count_write);
3954: printf (" */\n");
3955: } else {
3956: printf("\n");
3957: }
3958: printf ("\n");
3959: if (i68000)
3960: printf("#endif\n");
3961: opcode_next_clev[rp] = next_cpu_level;
3962: opcode_last_postfix[rp] = postfix;
3963:
1.1.1.2 ! root 3964: /* Hatari only : Now patch in the instruction cycles at the beginning of the function: */
! 3965: if (!using_ce020) {
! 3966: fseek(stdout, nCurInstrCycPos, SEEK_SET);
! 3967: printf("%d;", insn_n_cycles);
! 3968: fseek(stdout, 0, SEEK_END);
! 3969: }
! 3970:
! 3971: /* Hatari only : inc instruction index for cycle exact 68030 cpu */
! 3972: if (using_ce020 == 2)
! 3973: instr_index += 1;
! 3974:
1.1 root 3975: if (generate_stbl) {
3976: // char *name = ua (lookuptab[idx].name);
3977: const char *name = lookuptab[idx].name;
3978: if (i68000)
3979: fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
3980: fprintf (stblfile, "{ %sCPUFUNC(op_%04x_%d), %d }, /* %s */\n",
3981: (using_ce || using_ce020) ? "(cpuop_func*)" : "",
3982: opcode, postfix, opcode, name);
3983: if (i68000)
3984: fprintf (stblfile, "#endif\n");
3985: //xfree (name);
3986: }
3987: }
3988:
3989: static void generate_func (void)
3990: {
3991: int j, rp;
3992:
3993: /* sam: this is for people with low memory (eg. me :)) */
3994: printf ("\n"
3995: "#if !defined(PART_1) && !defined(PART_2) && "
3996: "!defined(PART_3) && !defined(PART_4) && "
3997: "!defined(PART_5) && !defined(PART_6) && "
3998: "!defined(PART_7) && !defined(PART_8)"
3999: "\n"
4000: "#define PART_1 1\n"
4001: "#define PART_2 1\n"
4002: "#define PART_3 1\n"
4003: "#define PART_4 1\n"
4004: "#define PART_5 1\n"
4005: "#define PART_6 1\n"
4006: "#define PART_7 1\n"
4007: "#define PART_8 1\n"
4008: "#endif\n\n");
4009:
4010: rp = 0;
4011: for(j = 1; j <= 8; ++j) {
4012: int k = (j * nr_cpuop_funcs) / 8;
4013: printf ("#ifdef PART_%d\n",j);
4014: for (; rp < k; rp++)
4015: generate_one_opcode (rp);
4016: printf ("#endif\n\n");
4017: }
4018:
4019: if (generate_stbl)
4020: fprintf (stblfile, "{ 0, 0 }};\n");
4021: }
4022:
4023: int main (int argc, char **argv)
4024: {
4025: int i, rp, postfix2;
4026: char fname[100];
4027:
4028: read_table68k ();
4029: do_merges ();
4030:
4031: opcode_map = xmalloc (int, nr_cpuop_funcs);
4032: opcode_last_postfix = xmalloc (int, nr_cpuop_funcs);
4033: opcode_next_clev = xmalloc (int, nr_cpuop_funcs);
4034: counts = xmalloc (unsigned long, 65536);
4035: read_counts ();
4036:
4037: /* It would be a lot nicer to put all in one file (we'd also get rid of
4038: * cputbl.h that way), but cpuopti can't cope. That could be fixed, but
4039: * I don't dare to touch the 68k version. */
4040:
4041: headerfile = fopen ("cputbl.h", "wb");
4042:
4043: stblfile = fopen ("cpustbl.c", "wb");
4044: generate_includes (stblfile);
4045:
4046: using_prefetch = 0;
4047: using_indirect = 0;
4048: using_exception_3 = 1;
4049: using_ce = 0;
4050:
4051: postfix2 = -1;
4052: for (i = 0; i < 32; i++) {
4053: postfix = i;
4054: if ((i >= 6 && i < 11) || (i > 12 && i < 20) || (i > 23 && i < 31))
4055: continue;
4056: generate_stbl = 1;
4057: if (i == 0 || i == 11 || i == 12 || i == 20 || i == 21 || i == 31) {
4058: if (generate_stbl)
4059: fprintf (stblfile, "#ifdef CPUEMU_%d\n", postfix);
4060: postfix2 = postfix;
4061: sprintf (fname, "cpuemu_%d.c", postfix);
4062: if (freopen (fname, "wb", stdout) == NULL) {
4063: perror(fname);
4064: return -1;
4065: }
4066: generate_includes (stdout);
4067: }
4068: using_mmu = 0;
4069: using_prefetch = 0;
4070: using_ce = 0;
4071: using_ce020 = 0;
4072: using_mmu = 0;
4073: cpu_level = 5 - i;
4074: if (i == 11 || i == 12) {
4075: cpu_level = 0;
4076: using_prefetch = 1;
4077: using_exception_3 = 1;
4078: if (i == 12)
4079: using_ce = 1;
4080: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4081: opcode_next_clev[rp] = 0;
4082: } else if (i == 20) {
4083: cpu_level = 2;
4084: using_ce020 = 1;
4085: read_counts ();
4086: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4087: opcode_next_clev[rp] = cpu_level;
4088: } else if (i == 21 || i == 22 || i == 23) {
4089: cpu_level = 3 + (23 - i);
4090: using_ce020 = 2;
4091: if (i == 21) {
4092: read_counts ();
4093: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4094: opcode_next_clev[rp] = cpu_level;
4095: }
4096: } else if (i >= 31 && i < 40) {
4097: cpu_level = 4;
4098: using_mmu = 1;
4099: if (i == 31)
4100: read_counts ();
4101: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4102: opcode_next_clev[rp] = cpu_level;
4103: }
4104:
4105: if (generate_stbl) {
4106: if ((i > 0 && i < 10) || (i >= 20))
4107: fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
4108: fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
4109: }
4110:
4111: generate_func ();
4112: if (generate_stbl) {
4113: if ((i > 0 && i < 10) || (i >= 20))
4114: fprintf (stblfile, "#endif /* CPUEMU_68000_ONLY */\n");
4115: if (postfix2 >= 0)
4116: fprintf (stblfile, "#endif /* CPUEMU_%d */\n", postfix2);
4117: }
4118: postfix2 = -1;
4119: }
4120:
4121: free (table68k);
4122: return 0;
4123: }
4124:
4125: void write_log (const TCHAR *format,...)
4126: {
4127: }
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