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1.1 root 1: /*
2: * UAE - The Un*x Amiga Emulator
3: *
4: * MC68000 emulation generator
5: *
6: * This is a fairly stupid program that generates a lot of case labels that
7: * can be #included in a switch statement.
8: * As an alternative, it can generate functions that handle specific
9: * MC68000 instructions, plus a prototype header file and a function pointer
10: * array to look up the function for an opcode.
11: * Error checking is bad, an illegal table68k file will cause the program to
12: * call abort().
13: * The generated code is sometimes sub-optimal, an optimizing compiler should
14: * take care of this.
15: *
16: * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
17: *
18: * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
19: */
20:
21: #include "sysconfig.h"
22: #include "sysdeps.h"
23: #include <ctype.h>
24: #include <string.h>
25:
26: #include "readcpu.h"
1.1.1.2 root 27: #include "falcon_cycle030.h"
1.1 root 28:
29: #define BOOL_TYPE "int"
30: /* Define the minimal 680x0 where NV flags are not affected by xBCD instructions. */
31: #define xBCD_KEEPS_NV_FLAGS 4
32:
33: static FILE *headerfile;
34: static FILE *stblfile;
35:
36: static int using_prefetch, using_indirect, using_mmu;
37: static int using_ce020;
38: static int using_exception_3;
39: static int using_ce;
40: static int cpu_level;
41: static int count_read, count_write, count_cycles, count_ncycles;
42: static int count_read_ea, count_write_ea, count_cycles_ea;
43:
44: static int optimized_flags;
45:
1.1.1.2 root 46: long nCurInstrCycPos; /* Hatari only : Stores where we have to patch in the current cycles value */
47:
1.1 root 48: #define GF_APDI 1
49: #define GF_AD8R 2
50: #define GF_PC8R 4
51: #define GF_AA 7
52: #define GF_NOREFILL 8
53: #define GF_PREFETCH 16
54: #define GF_FC 32
55: #define GF_MOVE 64
56:
57: /* For the current opcode, the next lower level that will have different code.
58: * Initialized to -1 for each opcode. If it remains unchanged, indicates we
59: * are done with that opcode. */
60: static int next_cpu_level;
61:
62: static int *opcode_map;
63: static int *opcode_next_clev;
64: static int *opcode_last_postfix;
65: static unsigned long *counts;
66: static int generate_stbl;
67: static int fixupcnt;
68:
1.1.1.3 ! root 69: static int instr_index = 0; /* Hatari: Added to give a unique index to each 68030 cycle exact instruction (CPU_EMU_21) */
! 70: static int instr_table; /* Hatari: Used to know which cycle table to use (CPU_EMU_21) */
! 71: static int instr_table_index; /* Hatari: Used when the cycle table is not the generic one to set the line of the table (CPU_EMU_21) */
1.1.1.2 root 72:
73: /* used to disable the return cycles function call when there are more than one cycle to take into account for an instruction */
74: /* Falcon CPU only (CPUEMU_21)) */
75: static bool no_return_cycles;
76:
77: /* All the following indexes are useful to get the correct cycle index in the cycle tables for 68030 cycle exact CPU (CPU_21) */
78: /* Hatari only code */
79: static int chk_w_index = 0;
80: static int chk_l_index = 0;
81: static int chk2_b_index = 0;
82: static int chk2_w_index = 0;
83: static int chk2_l_index = 0;
84: static int cas_b_index = 0;
85: static int cas_w_index = 0;
86: static int cas_l_index = 0;
1.1.1.3 ! root 87: static int divl_index = 0;
1.1.1.2 root 88:
89: /* These defines describe the different tables used for 68030 Cycle exact (Hatari only) */
90: #define TABLE_FALCON_CYCLES 0
91: #define TABLE_FALCON_CYCLES_CHK2_BW 1
92: #define TABLE_FALCON_CYCLES_CHK2_L 2
93: #define TABLE_FALCON_CYCLES_CHK_L 3
94: #define TABLE_FALCON_CYCLES_CHK_W 4
95: #define TABLE_FALCON_CYCLES_CAS_BW 5
96: #define TABLE_FALCON_CYCLES_CAS_L 6
97: #define TABLE_FALCON_CYCLES_CAS2_W 7
98: #define TABLE_FALCON_CYCLES_CAS2_L 8
99: #define TABLE_FALCON_CYCLES_RTE 9
100: #define TABLE_FALCON_CYCLES_BCC 10
101: #define TABLE_FALCON_CYCLES_DBCC 11
102: #define TABLE_FALCON_CYCLES_TRAPCC 12
103: #define TABLE_FALCON_CYCLES_TRAPCC_W 13
104: #define TABLE_FALCON_CYCLES_TRAPCC_L 14
105: #define TABLE_FALCON_CYCLES_TRAPV 15
106: #define TABLE_FALCON_CYCLES_DIVU_L 16
107: #define TABLE_FALCON_CYCLES_DIVS_L 17
108: #define TABLE_FALCON_CYCLES_BFTST_MEM 18
109: #define TABLE_FALCON_CYCLES_BFEXTU_MEM 19
110: #define TABLE_FALCON_CYCLES_BFCHG_MEM 20
111: #define TABLE_FALCON_CYCLES_BFEXTS_MEM 21
112: #define TABLE_FALCON_CYCLES_BFCLR_MEM 22
113: #define TABLE_FALCON_CYCLES_BFFFO_MEM 23
114: #define TABLE_FALCON_CYCLES_BFSET_MEM 24
115: #define TABLE_FALCON_CYCLES_BFINS_MEM 25
116: #define TABLE_FALCON_CYCLES_LSD 26
117: #define TABLE_FALCON_CYCLES_ASR 27
118: #define TABLE_FALCON_CYCLES_MOVEC 28
119: #define TABLE_FALCON_CYCLES_MOVES_EA_RN 29
120: #define TABLE_FALCON_CYCLES_MOVES_RN_EA 30
121: #define TABLE_FALCON_CYCLES_68030_INTERNAL 31
122:
123:
1.1 root 124: #define GENA_GETV_NO_FETCH 0
125: #define GENA_GETV_FETCH 1
126: #define GENA_GETV_FETCH_ALIGN 2
127: #define GENA_MOVEM_DO_INC 0
128: #define GENA_MOVEM_NO_INC 1
129: #define GENA_MOVEM_MOVE16 2
130:
1.1.1.2 root 131: /**
132: Table_labels table for all case.
133: */
134: static const char* falcon_cycles_tables[] = {
135: "table_falcon_cycles",
136: "table_falcon_cycles_CHK2_BW",
137: "table_falcon_cycles_CHK2_L",
138: "table_falcon_cycles_CHK_L",
139: "table_falcon_cycles_CHK_W",
140: "table_falcon_cycles_CAS_BW",
141: "table_falcon_cycles_CAS_L",
142: "table_falcon_cycles_CAS2_W",
143: "table_falcon_cycles_CAS2_L",
144: "table_falcon_cycles_RTE",
145: "table_falcon_cycles_Bcc",
146: "table_falcon_cycles_DBcc",
147: "table_falcon_cycles_TRAPcc",
148: "table_falcon_cycles_TRAPcc_W",
149: "table_falcon_cycles_TRAPcc_L",
150: "table_falcon_cycles_TRAPV",
151: "table_falcon_cycles_DIVU_L",
152: "table_falcon_cycles_DIVS_L",
153: "table_falcon_cycles_BFTST_Mem",
154: "table_falcon_cycles_BFEXTU_Mem",
155: "table_falcon_cycles_BFCHG_Mem",
156: "table_falcon_cycles_BFEXTS_Mem",
157: "table_falcon_cycles_BFCLR_Mem",
158: "table_falcon_cycles_BFFFO_Mem",
159: "table_falcon_cycles_BFSET_Mem",
160: "table_falcon_cycles_BFINS_Mem",
161: "table_falcon_cycles_LSD",
162: "table_falcon_cycles_ASR",
163: "table_falcon_cycles_MOVEC",
164: "table_falcon_cycles_MOVES_EA_RN",
165: "table_falcon_cycles_MOVES_RN_EA",
166: "table_falcon_cycles_68030_internal"
167: };
168:
1.1 root 169: static void read_counts (void)
170: {
171: FILE *file;
172: unsigned long opcode, count, total;
173: char name[20];
174: int nr = 0;
175: int ret;
176: memset (counts, 0, 65536 * sizeof *counts);
177:
178: count = 0;
179: file = fopen ("frequent.68k", "r");
180: if (file) {
181: ret = fscanf (file, "Total: %lu\n", &total);
182: while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
183: opcode_next_clev[nr] = 5;
184: opcode_last_postfix[nr] = -1;
185: opcode_map[nr++] = opcode;
186: counts[opcode] = count;
187: }
188: fclose (file);
189: }
190: if (nr == nr_cpuop_funcs)
191: return;
192: for (opcode = 0; opcode < 0x10000; opcode++) {
193: if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
194: && counts[opcode] == 0)
195: {
196: opcode_next_clev[nr] = 5;
197: opcode_last_postfix[nr] = -1;
198: opcode_map[nr++] = opcode;
199: counts[opcode] = count;
200: }
201: }
202: if (nr != nr_cpuop_funcs)
203: abort ();
204: }
205:
206: static char endlabelstr[80];
207: static int endlabelno = 0;
208: static int need_endlabel;
209:
210: static int n_braces, limit_braces;
211: static int m68k_pc_offset;
212: static int insn_n_cycles, insn_n_cycles020;
213:
214: static void fpulimit (void)
215: {
216: if (limit_braces)
217: return;
218: printf ("\n#ifdef FPUEMU\n");
219: limit_braces = n_braces;
220: n_braces = 0;
221: }
222: static void cpulimit (void)
223: {
224: printf ("#ifndef CPUEMU_68000_ONLY\n");
225: }
226:
227: static void returncycles (const char *s, int cycles)
228: {
229: if (using_ce)
230: return;
1.1.1.2 root 231:
232: if (using_ce020 == 1)
1.1 root 233: printf ("%sreturn;\n", s);
1.1.1.2 root 234: else if (using_ce020 == 2) {
235: if (no_return_cycles == true)
236: return;
237: // TODO: This first if statement should be removed when all the cycles are correctly generated for the Falcon 68030 CPU
238: // The next "else" should be removed too and only the printf line should be keept.
239: if (instr_table == TABLE_FALCON_CYCLES && table_falcon_cycles[instr_index].cache_cycles == 0) {
240: // set a temporary false value for this instruction cycles timing.
241: printf ("\tregs.ce030_instr_cycles = table_falcon_cycles[0];\n");
242: }
243: else {
244: printf ("%s\tregs.ce030_instr_cycles = %s[%d];\n", s, falcon_cycles_tables[instr_table], instr_table_index);
245: }
246:
247: printf ("%s\treturn;\n", s);
248: }
1.1 root 249: else
250: printf ("%sreturn %d * CYCLE_UNIT / 2;\n", s, cycles);
251: }
252:
1.1.1.2 root 253: /* Todo : remove this function when all Falcon cycles are coded */
254: static void addcycles_ce020 (int head, int tail, int cache_cycles, int noncache_cycles)
1.1 root 255: {
256: if (!using_ce020)
257: return;
1.1.1.2 root 258: if (cache_cycles > 0 && noncache_cycles > 0) {
259: //not needed anymore
260: }
261: count_cycles += noncache_cycles;
1.1 root 262: }
1.1.1.2 root 263:
1.1 root 264: static void addcycles000 (int cycles)
265: {
266: if (!using_ce)
267: return;
268: printf ("\tdo_cycles_ce000 (%d);\n", cycles);
269: count_cycles += cycles;
270: }
271: static void addcycles000_2 (const char *s, int cycles)
272: {
273: if (!using_ce)
274: return;
275: printf ("%sdo_cycles_ce000 (%d);\n", s, cycles);
276: count_cycles += cycles;
277: }
278:
279: static void addcycles000_3 (const char *s)
280: {
281: if (!using_ce)
282: return;
283: printf ("%sif (cycles > 0) do_cycles_ce000 (cycles);\n", s);
284: count_ncycles++;
285: }
286:
287: static int isreg (amodes mode)
288: {
289: if (mode == Dreg || mode == Areg)
290: return 1;
291: return 0;
292: }
293:
294: static void start_brace (void)
295: {
296: n_braces++;
297: printf ("{");
298: }
299:
300: static void close_brace (void)
301: {
302: assert (n_braces > 0);
303: n_braces--;
304: printf ("}");
305: }
306:
307: static void finish_braces (void)
308: {
309: while (n_braces > 0)
310: close_brace ();
311: }
312:
313: static void pop_braces (int to)
314: {
315: while (n_braces > to)
316: close_brace ();
317: }
318:
319: static int bit_size (int size)
320: {
321: switch (size) {
322: case sz_byte: return 8;
323: case sz_word: return 16;
324: case sz_long: return 32;
325: default: abort ();
326: }
327: return 0;
328: }
329:
330: static const char *bit_mask (int size)
331: {
332: switch (size) {
333: case sz_byte: return "0xff";
334: case sz_word: return "0xffff";
335: case sz_long: return "0xffffffff";
336: default: abort ();
337: }
338: return 0;
339: }
340:
341: static const char *srcl, *dstl;
342: static const char *srcw, *dstw;
343: static const char *srcb, *dstb;
344: static const char *ce020_prefetch_long;
345: static const char *ce020_prefetch_word;
346:
347: static void gen_nextilong (const char *type, const char *name, int flags)
348: {
349: int r = m68k_pc_offset;
350: m68k_pc_offset += 4;
351:
352: if (using_ce020) {
353: printf ("\t%s %s = %s (%d);\n", type, name, ce020_prefetch_long, r);
354: count_read += 2;
355: } else if (using_ce) {
356: printf ("\t%s %s;\n", type, name);
357: /* we must do this because execution order of (something | something2) is not defined */
358: if (flags & GF_NOREFILL) {
359: printf ("\t%s = get_word_ce_prefetch (%d) << 16;\n", name, r + 2);
360: count_read++;
361: printf ("\t%s |= regs.irc;\n", name);
362: } else {
363: printf ("\t%s = get_word_ce_prefetch (%d) << 16;\n", name, r + 2);
364: count_read++;
365: printf ("\t%s |= get_word_ce_prefetch (%d);\n", name, r + 4);
366: count_read++;
367: }
368: } else {
369: if (using_prefetch) {
370: if (flags & GF_NOREFILL) {
371: printf ("\t%s %s;\n", type, name);
372: printf ("\t%s = get_word_prefetch (%d) << 16;\n", name, r + 2);
373: count_read++;
374: printf ("\t%s |= regs.irc;\n", name);
375: insn_n_cycles += 4;
376: } else {
377: printf ("\t%s %s = get_long_prefetch (%d);\n", type, name, r + 2);
378: count_read++;
379: count_read++;
380: insn_n_cycles += 8;
381: }
382: } else if (using_indirect) {
383: insn_n_cycles += 8;
384: printf ("\t%s %s = get_ilongi (%d);\n", type, name, r);
385: } else if (using_mmu) {
386: insn_n_cycles += 8;
387: printf ("\t%s %s = get_ilong_mmu (%d);\n", type, name, r);
388: } else {
389: insn_n_cycles += 8;
390: printf ("\t%s %s = get_ilong (%d);\n", type, name, r);
391: }
392: }
393: }
394:
395: static const char *gen_nextiword (int flags)
396: {
397: static char buffer[80];
398: int r = m68k_pc_offset;
399: m68k_pc_offset += 2;
400:
401: if (using_ce020) {
402: sprintf (buffer, "%s (%d)", ce020_prefetch_word, r);
403: count_read++;
404: } else if (using_ce) {
405: if (flags & GF_NOREFILL) {
406: strcpy (buffer, "regs.irc");
407: } else {
408: sprintf (buffer, "get_word_ce_prefetch (%d)", r + 2);
409: count_read++;
410: }
411: } else {
412: if (using_prefetch) {
413: if (flags & GF_NOREFILL) {
414: sprintf (buffer, "regs.irc"/*, r*/);
415: } else {
416: sprintf (buffer, "get_word_prefetch (%d)", r + 2);
417: count_read++;
418: insn_n_cycles += 4;
419: }
420: } else if (using_indirect) {
421: sprintf (buffer, "get_iwordi(%d)", r);
422: insn_n_cycles += 4;
423: } else if (using_mmu) {
424: sprintf (buffer, "get_iword_mmu (%d)", r);
425: insn_n_cycles += 4;
426: } else {
427: sprintf (buffer, "get_iword (%d)", r);
428: insn_n_cycles += 4;
429: }
430: }
431: return buffer;
432: }
433:
434: static const char *gen_nextibyte (int flags)
435: {
436: static char buffer[80];
437: int r = m68k_pc_offset;
438: m68k_pc_offset += 2;
439:
440: if (using_ce020) {
441: sprintf (buffer, "(uae_u8)%s (%d)", ce020_prefetch_word, r);
442: count_read++;
443: } else if (using_ce) {
444: if (flags & GF_NOREFILL) {
445: strcpy (buffer, "(uae_u8)regs.irc");
446: } else {
447: sprintf (buffer, "(uae_u8)get_word_ce_prefetch (%d)", r + 2);
448: count_read++;
449: }
450: } else {
451: insn_n_cycles += 4;
452: if (using_prefetch) {
453: if (flags & GF_NOREFILL) {
454: sprintf (buffer, "(uae_u8)regs.irc"/*, r*/);
455: } else {
456: sprintf (buffer, "(uae_u8)get_word_prefetch (%d)", r + 2);
457: insn_n_cycles += 4;
458: count_read++;
459: }
460: } else if (using_indirect) {
461: sprintf (buffer, "get_ibytei (%d)", r);
462: insn_n_cycles += 4;
463: } else if (using_mmu) {
464: sprintf (buffer, "get_ibyte_mmu (%d)", r);
465: insn_n_cycles += 4;
466: } else {
467: sprintf (buffer, "get_ibyte (%d)", r);
468: insn_n_cycles += 4;
469: }
470: }
471: return buffer;
472: }
473:
474: static void irc2ir (void)
475: {
476: if (!using_prefetch)
477: return;
478: printf ("\tregs.ir = regs.irc;\n");
479: if (using_ce)
480: printf ("\tipl_fetch ();\n");
481: }
482:
483: static int did_prefetch;
484:
485: static void fill_prefetch_2 (void)
486: {
487: if (!using_prefetch)
488: return;
489: if (using_ce)
490: printf ("\tget_word_ce_prefetch (%d);\n", m68k_pc_offset + 2);
491: else
492: printf ("\tget_word_prefetch (%d);\n", m68k_pc_offset + 2);
493: did_prefetch = 1;
494: count_read++;
495: insn_n_cycles += 4;
496: }
497:
498: static void fill_prefetch_1 (int o)
499: {
500: if (!using_prefetch)
501: return;
502: if (using_ce) {
503: printf ("\tget_word_ce_prefetch (%d);\n", o);
504: } else {
505: printf ("\tget_word_prefetch (%d);\n", o);
506: }
507: did_prefetch = 1;
508: count_read++;
509: insn_n_cycles += 4;
510: }
511:
512: static void fill_prefetch_full (void)
513: {
514: fill_prefetch_1 (0);
515: irc2ir ();
516: fill_prefetch_1 (2);
517: }
518:
519: static void fill_prefetch_0 (void)
520: {
521: if (!using_prefetch)
522: return;
523: if (using_ce)
524: printf ("\tget_word_ce_prefetch (0);\n");
525: else
526: printf ("\tget_word_prefetch (0);\n");
527: did_prefetch = 1;
528: count_read++;
529: insn_n_cycles += 4;
530: }
531:
532: static void dummy_prefetch (void)
533: {
534: int o = m68k_pc_offset + 2;
535: if (!using_prefetch)
536: return;
537: if (using_ce) {
538: printf ("\tget_wordi_ce (m68k_getpc () + %d);\n", o);
539: } else {
540: printf ("\tget_wordi (m68k_getpc () + %d);\n", o);
541: }
542: count_read++;
543: insn_n_cycles += 4;
544: }
545:
546: static void fill_prefetch_next_1 (void)
547: {
548: irc2ir ();
549: fill_prefetch_1 (m68k_pc_offset + 2);
550: }
551:
552: static void fill_prefetch_next (void)
553: {
554: fill_prefetch_next_1 ();
555: }
556:
557: #if 0
558: static void fill_prefetch_next_delay (int extracycles)
559: {
560: if (!using_prefetch)
561: return;
562: if (using_ce) {
563: if (extracycles > 0) {
564: printf("\t{\n");
565: fill_prefetch_next ();
566: printf("\tif (%d > 0) do_cycles(%d * CYCLE_UNIT / 2);\n",
567: extracycles, extracycles);
568: printf("\t}\n");
569: } else {
570: fill_prefetch_next ();
571: }
572: } else {
573: fill_prefetch_next ();
574: }
575: }
576: #endif
577:
578: static void fill_prefetch_finish (void)
579: {
580: if (did_prefetch || !using_prefetch)
581: return;
582: fill_prefetch_1 (m68k_pc_offset);
583: }
584:
585: static void setpc (const char *format, ...)
586: {
587: va_list parms;
588: char buffer[1000];
589:
590: va_start (parms, format);
591: _vsnprintf (buffer, 1000 - 1, format, parms);
592: va_end (parms);
593:
594: if (using_mmu)
595: printf ("\tm68k_setpc_mmu (%s);\n", buffer);
596: else
597: printf ("\tm68k_setpc (%s);\n", buffer);
598: }
599:
600: static void incpc (const char *format, ...)
601: {
602: va_list parms;
603: char buffer[1000];
604:
605: va_start (parms, format);
606: _vsnprintf (buffer, 1000 - 1, format, parms);
607: va_end (parms);
608:
609: if (using_mmu)
610: printf ("\tm68k_incpci (%s);\n", buffer);
611: else
612: printf ("\tm68k_incpc (%s);\n", buffer);
613: }
614:
615: static void sync_m68k_pc (void)
616: {
617: if (m68k_pc_offset == 0)
618: return;
619: incpc ("%d", m68k_pc_offset);
620: m68k_pc_offset = 0;
621: }
622:
623: static void gen_set_fault_pc (void)
624: {
625: if (!using_mmu)
626: return;
627: sync_m68k_pc ();
628: printf ("\tregs.fault_pc = m68k_getpci ();\n");
629: m68k_pc_offset = 0;
630: }
631:
632: static void syncmovepc (int getv, int flags)
633: {
634: #if 0
635: if (!(flags & GF_MOVE))
636: return;
637: if (getv == 1) {
638: sync_m68k_pc ();
639: //fill_prefetch_next ();
640: }
641: #endif
642: }
643:
644: /* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
645: * the calling routine handles Apdi and Aipi modes.
646: * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
647:
648: /* fixup indicates if we want to fix up adress registers in pre decrement
649: * or post increment mode now (0) or later (1). A value of 2 will then be
650: * used to do the actual fix up. This allows to do all memory readings
651: * before any register is modified, and so to rerun operation without
652: * side effect in case a bus fault is generated by any memory access.
653: * XJ - 2006/11/13 */
654:
655: static void genamode2 (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags, int fixup)
656: {
657: char namea[100];
658: int m68k_pc_offset_last = m68k_pc_offset;
659:
660: sprintf (namea, "%sa", name);
661:
662: start_brace ();
663: switch (mode) {
664: case Dreg:
665: if (movem)
666: abort ();
667: if (getv == 1)
668: switch (size) {
669: case sz_byte:
670: #ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
671: /* This causes the target compiler to generate better code on few systems */
672: printf ("\tuae_s8 %s = ((uae_u8*)&m68k_dreg (regs, %s))[3];\n", name, reg);
673: #else
674: printf ("\tuae_s8 %s = m68k_dreg (regs, %s);\n", name, reg);
675: #endif
676: break;
677: case sz_word:
678: #ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
679: printf ("\tuae_s16 %s = ((uae_s16*)&m68k_dreg (regs, %s))[1];\n", name, reg);
680: #else
681: printf ("\tuae_s16 %s = m68k_dreg (regs, %s);\n", name, reg);
682: #endif
683: break;
684: case sz_long:
685: printf ("\tuae_s32 %s = m68k_dreg (regs, %s);\n", name, reg);
686: break;
687: default:
688: abort ();
689: }
690: syncmovepc (getv, flags);
691: return;
692: case Areg:
693: if (movem)
694: abort ();
695: if (getv == 1)
696: switch (size) {
697: case sz_word:
698: printf ("\tuae_s16 %s = m68k_areg (regs, %s);\n", name, reg);
699: break;
700: case sz_long:
701: printf ("\tuae_s32 %s = m68k_areg (regs, %s);\n", name, reg);
702: break;
703: default:
704: abort ();
705: }
706: syncmovepc (getv, flags);
707: return;
708: case Aind: // (An)
709: printf ("\tuaecptr %sa = m68k_areg (regs, %s);\n", name, reg);
710: break;
711: case Aipi: // (An)+
712: printf ("\tuaecptr %sa = m68k_areg (regs, %s);\n", name, reg);
713: break;
714: case Apdi: // -(An)
715: printf ("\tuaecptr %sa;\n", name);
716: switch (size) {
717: case sz_byte:
718: if (movem)
719: printf ("\t%sa = m68k_areg (regs, %s);\n", name, reg);
720: else
721: printf ("\t%sa = m68k_areg (regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
722: break;
723: case sz_word:
724: printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
725: break;
726: case sz_long:
727: printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
728: break;
729: default:
730: abort ();
731: }
732: if (!(flags & GF_APDI)) {
733: addcycles000 (2);
734: insn_n_cycles += 2;
735: count_cycles_ea += 2;
736: }
737: break;
738: case Ad16: // (d16,An)
739: printf ("\tuaecptr %sa = m68k_areg (regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword (flags));
740: count_read_ea++;
741: break;
742: case Ad8r: // (d8,An,Xn)
743: printf ("\tuaecptr %sa;\n", name);
744: if (cpu_level > 1) {
745: if (next_cpu_level < 1)
746: next_cpu_level = 1;
747: sync_m68k_pc ();
748: start_brace ();
749: /* This would ordinarily be done in gen_nextiword, which we bypass. */
750: insn_n_cycles += 4;
751: if (using_ce020 || using_mmu)
752: printf ("\t%sa = x_get_disp_ea_020 (m68k_areg (regs, %s), x_next_iword ());\n", name, reg);
753: else
754: printf ("\t%sa = get_disp_ea_020 (m68k_areg (regs, %s), next_iword ());\n", name, reg);
755: } else {
756: if (!(flags & GF_AD8R)) {
757: addcycles000 (2);
758: insn_n_cycles += 2;
759: count_cycles_ea += 2;
760: }
761: printf ("\t%sa = get_disp_ea_000 (m68k_areg (regs, %s), %s);\n", name, reg, gen_nextiword (flags));
762: count_read_ea++;
763: }
764: break;
765: case PC16: // (d16,PC,Xn)
766: printf ("\tuaecptr %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset);
767: printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
768: break;
769: case PC8r: // (d8,PC,Xn)
770: printf ("\tuaecptr tmppc;\n");
771: printf ("\tuaecptr %sa;\n", name);
772: if (cpu_level > 1) {
773: if (next_cpu_level < 1)
774: next_cpu_level = 1;
775: sync_m68k_pc ();
776: start_brace ();
777: /* This would ordinarily be done in gen_nextiword, which we bypass. */
778: insn_n_cycles += 4;
779: printf ("\ttmppc = m68k_getpc ();\n");
780: if (using_ce020 || using_mmu)
781: printf ("\t%sa = x_get_disp_ea_020 (tmppc, x_next_iword ());\n", name);
782: else
783: printf ("\t%sa = get_disp_ea_020 (tmppc, next_iword ());\n", name);
784: } else {
785: printf ("\ttmppc = m68k_getpc () + %d;\n", m68k_pc_offset);
786: if (!(flags & GF_PC8R)) {
787: addcycles000 (2);
788: insn_n_cycles += 2;
789: count_cycles_ea += 2;
790: }
791: printf ("\t%sa = get_disp_ea_000 (tmppc, %s);\n", name, gen_nextiword (flags));
792: }
793:
794: break;
795: case absw:
796: printf ("\tuaecptr %sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
797: break;
798: case absl:
799: gen_nextilong ("uaecptr", namea, flags);
800: count_read_ea += 2;
801: break;
802: case imm:
803: if (getv != 1)
804: abort ();
805: insn_n_cycles020++;
806: switch (size) {
807: case sz_byte:
808: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
809: count_read_ea++;
810: break;
811: case sz_word:
812: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
813: count_read_ea++;
814: break;
815: case sz_long:
816: gen_nextilong ("uae_s32", name, flags);
817: count_read_ea += 2;
818: break;
819: default:
820: abort ();
821: }
822: syncmovepc (getv, flags);
823: return;
824: case imm0:
825: if (getv != 1)
826: abort ();
827: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
828: count_read_ea++;
829: syncmovepc (getv, flags);
830: return;
831: case imm1:
832: if (getv != 1)
833: abort ();
834: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
835: count_read_ea++;
836: syncmovepc (getv, flags);
837: return;
838: case imm2:
839: if (getv != 1)
840: abort ();
841: gen_nextilong ("uae_s32", name, flags);
842: count_read_ea += 2;
843: syncmovepc (getv, flags);
844: return;
845: case immi:
846: if (getv != 1)
847: abort ();
848: printf ("\tuae_u32 %s = %s;\n", name, reg);
849: syncmovepc (getv, flags);
850: return;
851: default:
852: abort ();
853: }
854:
855: syncmovepc (getv, flags);
856:
857: /* We get here for all non-reg non-immediate addressing modes to
858: * actually fetch the value. */
859:
860: if ((using_prefetch || using_ce) && using_exception_3 && getv != 0 && size != sz_byte) {
861: int offset = 0;
862: if (flags & GF_MOVE) {
863: offset = m68k_pc_offset;
864: if (getv == 2)
865: offset += 2;
866: } else {
867: offset = m68k_pc_offset_last;
868: }
869: printf ("\tif (%sa & 1) {\n", name);
870: printf ("\t\texception3 (opcode, m68k_getpc () + %d, %sa);\n",
871: offset, name);
872: printf ("\t\tgoto %s;\n", endlabelstr);
873: printf ("\t}\n");
874: need_endlabel = 1;
875: start_brace ();
876: }
877:
878: if (flags & GF_PREFETCH)
879: fill_prefetch_next ();
880:
881: if (getv == 1) {
882: start_brace ();
883: if (using_ce020) {
884: switch (size) {
885: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, srcb, name); count_read++; break;
886: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, srcw, name); count_read++; break;
887: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = %s (%sa);\n", name, srcl, name); count_read += 2; break;
888: default: abort ();
889: }
890: } else if (using_ce) {
891: switch (size) {
892: case sz_byte: printf ("\tuae_s8 %s = get_byte_ce (%sa);\n", name, name); count_read++; break;
893: case sz_word: printf ("\tuae_s16 %s = get_word_ce (%sa);\n", name, name); count_read++; break;
894: case sz_long: printf ("\tuae_s32 %s = get_word_ce (%sa) << 16; %s |= get_word_ce (%sa + 2);\n", name, name, name, name); count_read += 2; break;
895: default: abort ();
896: }
897: } else if (using_mmu) {
898: if (flags & GF_FC) {
899: switch (size) {
900: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = sfc_get_byte (%sa);\n", name, name); break;
901: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = sfc_get_word (%sa);\n", name, name); break;
902: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = sfc_get_long (%sa);\n", name, name); break;
903: default: abort ();
904: }
905: } else {
906: switch (size) {
907: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = get_byte_mmu (%sa);\n", name, name); break;
908: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = get_word_mmu (%sa);\n", name, name); break;
909: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = get_long_mmu (%sa);\n", name, name); break;
910: default: abort ();
911: }
912: }
913: } else {
914: switch (size) {
915: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = get_byte (%sa);\n", name, name); count_read++; break;
916: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = get_word (%sa);\n", name, name); count_read++; break;
917: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = get_long (%sa);\n", name, name); count_read += 2; break;
918: default: abort ();
919: }
920: }
921: }
922:
923: /* We now might have to fix up the register for pre-dec or post-inc
924: * addressing modes. */
925: if (!movem)
926: switch (mode) {
927: case Aipi:
928: if (fixup == 1) {
929: printf ("\tmmufixup[%d].reg = %s;\n", fixupcnt, reg);
930: printf ("\tmmufixup[%d].value = m68k_areg (regs, %s);\n", fixupcnt, reg);
931: }
932: switch (size) {
933: case sz_byte:
934: printf ("\tm68k_areg (regs, %s) += areg_byteinc[%s];\n", reg, reg);
935: break;
936: case sz_word:
937: printf ("\tm68k_areg (regs, %s) += 2;\n", reg);
938: break;
939: case sz_long:
940: printf ("\tm68k_areg (regs, %s) += 4;\n", reg);
941: break;
942: default:
943: abort ();
944: }
945: break;
946: case Apdi:
947: if (fixup == 1) {
948: printf ("\tmmufixup[%d].reg = %s;\n", fixupcnt, reg);
949: printf ("\tmmufixup[%d].value = m68k_areg (regs, %s);\n", fixupcnt, reg);
950: }
951: printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
952: break;
953: default:
954: break;
955: }
956: }
957:
958: static void genamode_fixup (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags, int fixup)
959: {
960: if (fixup != 2) {
961: genamode2 (mode, reg, size, name, getv, movem, flags, fixup);
962: } else {
963: if (!movem) {
964: switch ((int)mode)
965: {
966: case Aipi:
967: case Apdi:
968: printf ("\tmmufixup[0].reg = -1;\n"/*, fixupcnt*/);
969: break;
970: }
971: }
972: }
973: }
974:
975: static void genamode (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
976: {
977: genamode2 (mode, reg, size, name, getv, movem, flags, 0);
978: }
979: static void genamode_pre (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
980: {
981: genamode_fixup (mode, reg, size, name, getv, movem, flags, using_mmu ? 1 : 0);
982: }
983: static void genamode_post (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
984: {
985: if (using_mmu)
986: genamode_fixup (mode, reg, size, name, getv, movem, flags, 2);
987: }
988:
989: static void genastore_2 (const char *from, amodes mode, const char *reg, wordsizes size, const char *to, int store_dir, int flags)
990: {
991: switch (mode) {
992: case Dreg:
993: switch (size) {
994: case sz_byte:
995: printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
996: break;
997: case sz_word:
998: printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
999: break;
1000: case sz_long:
1001: printf ("\tm68k_dreg (regs, %s) = (%s);\n", reg, from);
1002: break;
1003: default:
1004: abort ();
1005: }
1006: break;
1007: case Areg:
1008: switch (size) {
1009: case sz_word:
1010: printf ("\tm68k_areg (regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
1011: break;
1012: case sz_long:
1013: printf ("\tm68k_areg (regs, %s) = (%s);\n", reg, from);
1014: break;
1015: default:
1016: abort ();
1017: }
1018: break;
1019: case Aind:
1020: case Aipi:
1021: case Apdi:
1022: case Ad16:
1023: case Ad8r:
1024: case absw:
1025: case absl:
1026: case PC16:
1027: case PC8r:
1028: gen_set_fault_pc ();
1029: if (using_ce020) {
1030: switch (size) {
1031: case sz_byte:
1032: printf ("\t%s (%sa, %s);\n", dstb, to, from);
1033: count_write++;
1034: break;
1035: case sz_word:
1036: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1037: abort ();
1038: printf ("\t%s (%sa, %s);\n", dstw, to, from);
1039: count_write++;
1040: break;
1041: case sz_long:
1042: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1043: abort ();
1044: printf ("\t%s (%sa, %s);\n", dstl, to, from);
1045: count_write += 2;
1046: break;
1047: default:
1048: abort ();
1049: }
1050: } else if (using_ce) {
1051: switch (size) {
1052: case sz_byte:
1053: printf ("\tput_byte_ce (%sa, %s);\n", to, from);
1054: count_write++;
1055: break;
1056: case sz_word:
1057: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1058: abort ();
1059: printf ("\tput_word_ce (%sa, %s);\n", to, from);
1060: count_write++;
1061: break;
1062: case sz_long:
1063: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1064: abort ();
1065: if (store_dir)
1066: printf ("\tput_word_ce (%sa + 2, %s); put_word_ce (%sa, %s >> 16);\n", to, from, to, from);
1067: else
1068: printf ("\tput_word_ce (%sa, %s >> 16); put_word_ce (%sa + 2, %s);\n", to, from, to, from);
1069: count_write += 2;
1070: break;
1071: default:
1072: abort ();
1073: }
1074: } else if (using_mmu) {
1075: switch (size) {
1076: case sz_byte:
1077: insn_n_cycles += 4;
1078: if (flags & GF_FC)
1079: printf ("\tdfc_put_byte (%sa, %s);\n", to, from);
1080: else
1081: printf ("\tput_byte_mmu (%sa, %s);\n", to, from);
1082: break;
1083: case sz_word:
1084: insn_n_cycles += 4;
1085: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1086: abort ();
1087: if (flags & GF_FC)
1088: printf ("\tdfc_put_word (%sa, %s);\n", to, from);
1089: else
1090: printf ("\tput_word_mmu (%sa, %s);\n", to, from);
1091: break;
1092: case sz_long:
1093: insn_n_cycles += 8;
1094: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1095: abort ();
1096: if (flags & GF_FC)
1097: printf ("\tdfc_put_long (%sa, %s);\n", to, from);
1098: else
1099: printf ("\tput_long_mmu (%sa, %s);\n", to, from);
1100: break;
1101: default:
1102: abort ();
1103: }
1104: } else {
1105: switch (size) {
1106: case sz_byte:
1107: insn_n_cycles += 4;
1108: printf ("\tput_byte (%sa, %s);\n", to, from);
1109: count_write++;
1110: break;
1111: case sz_word:
1112: insn_n_cycles += 4;
1113: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1114: abort ();
1115: printf ("\tput_word (%sa, %s);\n", to, from);
1116: count_write++;
1117: break;
1118: case sz_long:
1119: insn_n_cycles += 8;
1120: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1121: abort ();
1122: printf ("\tput_long (%sa, %s);\n", to, from);
1123: count_write += 2;
1124: break;
1125: default:
1126: abort ();
1127: }
1128: }
1129: break;
1130: case imm:
1131: case imm0:
1132: case imm1:
1133: case imm2:
1134: case immi:
1135: abort ();
1136: break;
1137: default:
1138: abort ();
1139: }
1140: }
1141:
1142: static void genastore (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1143: {
1144: genastore_2 (from, mode, reg, size, to, 0, 0);
1145: }
1146: static void genastore_rev (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1147: {
1148: genastore_2 (from, mode, reg, size, to, 1, 0);
1149: }
1150: static void genastore_fc (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1151: {
1152: genastore_2 (from, mode, reg, size, to, 1, GF_FC);
1153: }
1154:
1155: static void genmovemel (uae_u16 opcode)
1156: {
1157: char getcode[100];
1158: int size = table68k[opcode].size == sz_long ? 4 : 2;
1159:
1160: if (table68k[opcode].size == sz_long) {
1161: sprintf (getcode, "%s (srca)", srcl);
1162: } else {
1163: sprintf (getcode, "(uae_s32)(uae_s16)%s (srca)", srcw);
1164: }
1165: count_read += table68k[opcode].size == sz_long ? 2 : 1;
1166: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1167: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1.1.1.2 root 1168: printf ("\tuae_u16 regs_number = 0;\n");
1.1 root 1169: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, 0);
1170: start_brace ();
1.1.1.2 root 1171: printf ("\twhile (dmask) { m68k_dreg (regs, movem_index1[dmask]) = %s; srca += %d; dmask = movem_next[dmask]; regs_number++; }\n",
1.1 root 1172: getcode, size);
1.1.1.2 root 1173: printf ("\twhile (amask) { m68k_areg (regs, movem_index1[amask]) = %s; srca += %d; amask = movem_next[amask]; regs_number++; }\n",
1.1 root 1174: getcode, size);
1175:
1176: if (table68k[opcode].dmode == Aipi) {
1177: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1178: count_read++;
1179: }
1180: count_ncycles++;
1.1.1.2 root 1181:
1182: if (using_ce020 == 2) {
1183: if (table68k[opcode].size == sz_long)
1184: printf ("\tregs.ce030_instr_addcycles = regs_number * 8;\n");
1185: else
1186: printf ("\tregs.ce030_instr_addcycles = regs_number * 4;\n");
1187: }
1188:
1.1 root 1189: fill_prefetch_next ();
1190: }
1191:
1192: static void genmovemel_ce (uae_u16 opcode)
1193: {
1194: int size = table68k[opcode].size == sz_long ? 4 : 2;
1195: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1196: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1197: printf ("\tuae_u32 v;\n");
1198: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA);
1199: if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
1200: addcycles000 (2);
1201: start_brace ();
1202: if (table68k[opcode].size == sz_long) {
1203: printf ("\twhile (dmask) { v = get_word_ce(srca) << 16; v |= get_word_ce(srca + 2); m68k_dreg (regs, movem_index1[dmask]) = v; srca += %d; dmask = movem_next[dmask]; }\n",
1204: size);
1205: printf ("\twhile (amask) { v = get_word_ce(srca) << 16; v |= get_word_ce(srca + 2); m68k_areg (regs, movem_index1[amask]) = v; srca += %d; amask = movem_next[amask]; }\n",
1206: size);
1207: } else {
1208: printf ("\twhile (dmask) { m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_ce(srca); srca += %d; dmask = movem_next[dmask]; }\n",
1209: size);
1210: printf ("\twhile (amask) { m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_ce(srca); srca += %d; amask = movem_next[amask]; }\n",
1211: size);
1212: }
1213: printf ("\tget_word_ce (srca);\n"); // and final extra word fetch that goes nowhere..
1214: count_read++;
1215: if (table68k[opcode].dmode == Aipi)
1216: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1.1.1.2 root 1217:
1.1 root 1218: count_ncycles++;
1219: fill_prefetch_next ();
1220: }
1221:
1222: static void genmovemle (uae_u16 opcode)
1223: {
1224: char putcode[100];
1225: int size = table68k[opcode].size == sz_long ? 4 : 2;
1226:
1227: if (table68k[opcode].size == sz_long) {
1228: sprintf (putcode, "%s (srca", dstl);
1229: } else {
1230: sprintf (putcode, "%s (srca", dstw);
1231: }
1232: count_write += table68k[opcode].size == sz_long ? 2 : 1;
1233:
1234: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1235: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, 0);
1236: start_brace ();
1.1.1.2 root 1237: printf ("\tuae_u16 regs_number = 0;\n");
1.1 root 1238: if (table68k[opcode].dmode == Apdi) {
1239: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
1240: if (!using_mmu)
1241: printf ("\tint type = get_cpu_model() >= 68020;\n");
1242: printf ("\twhile (amask) {\n");
1243: printf ("\t\tsrca -= %d;\n", size);
1244: if (!using_mmu)
1245: printf ("\t\tif (type) m68k_areg (regs, dstreg) = srca;\n");
1246: printf ("\t\t%s, m68k_areg (regs, movem_index2[amask]));\n", putcode);
1247: printf ("\t\tamask = movem_next[amask];\n");
1.1.1.2 root 1248: printf ("\t\tregs_number++;\n");
1.1 root 1249: printf ("\t}\n");
1.1.1.2 root 1250: printf ("\twhile (dmask) { srca -= %d; %s, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; regs_number++; }\n",
1.1 root 1251: size, putcode);
1252: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1253: } else {
1254: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1.1.1.2 root 1255: printf ("\twhile (dmask) { %s, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; regs_number++; }\n",
1.1 root 1256: putcode, size);
1.1.1.2 root 1257: printf ("\twhile (amask) { %s, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; regs_number++; }\n",
1.1 root 1258: putcode, size);
1259: }
1.1.1.2 root 1260:
1.1 root 1261: count_ncycles++;
1.1.1.2 root 1262: if (using_ce020 == 2) {
1263: if (table68k[opcode].size == sz_long)
1264: printf ("\tregs.ce030_instr_addcycles = regs_number * 8;\n");
1265: else
1266: printf ("\tregs.ce030_instr_addcycles = regs_number * 4;\n");
1267: }
1.1 root 1268: fill_prefetch_next ();
1269: }
1270:
1271: static void genmovemle_ce (uae_u16 opcode)
1272: {
1273: int size = table68k[opcode].size == sz_long ? 4 : 2;
1274: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1275: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA);
1276:
1277: if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r) {
1278: addcycles000 (2);
1279: }
1280: start_brace ();
1281: if (table68k[opcode].size == sz_long) {
1282: if (table68k[opcode].dmode == Apdi) {
1283: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
1284: printf ("\twhile (amask) { srca -= %d; put_word_ce (srca, m68k_areg (regs, movem_index2[amask]) >> 16); put_word_ce (srca + 2, m68k_areg (regs, movem_index2[amask])); amask = movem_next[amask]; }\n",
1285: size);
1.1.1.2 root 1286: printf ("\twhile (dmask) { srca -= %d; put_word_ce (srca, m68k_dreg (regs, movem_index2[dmask]) >> 16); put_word_ce (srca + 2, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask];}\n",
1.1 root 1287: size);
1288: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1289: } else {
1290: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1291: printf ("\twhile (dmask) { put_word_ce (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16); put_word_ce (srca + 2, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
1292: size);
1.1.1.2 root 1293: printf ("\twhile (amask) { put_word_ce (srca, m68k_areg (regs, movem_index1[amask]) >> 16); put_word_ce (srca + 2, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask];}\n",
1.1 root 1294: size);
1295: }
1296: } else {
1297: if (table68k[opcode].dmode == Apdi) {
1298: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
1299: printf ("\twhile (amask) { srca -= %d; put_word_ce (srca, m68k_areg (regs, movem_index2[amask])); amask = movem_next[amask]; }\n",
1300: size);
1301: printf ("\twhile (dmask) { srca -= %d; put_word_ce (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }\n",
1302: size);
1303: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1304: } else {
1305: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1306: printf ("\twhile (dmask) { put_word_ce (srca, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
1307: size);
1308: printf ("\twhile (amask) { put_word_ce (srca, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; }\n",
1309: size);
1310: }
1311: }
1.1.1.2 root 1312:
1.1 root 1313: count_ncycles++;
1314: fill_prefetch_next ();
1315: }
1316:
1317: static void duplicate_carry (int n)
1318: {
1319: int i;
1320: for (i = 0; i <= n; i++)
1321: printf ("\t");
1322: printf ("COPY_CARRY ();\n");
1323: }
1324:
1325: typedef enum
1326: {
1327: flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_z, flag_zn,
1328: flag_av, flag_sv
1329: }
1330: flagtypes;
1331:
1332: static void genflags_normal (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
1333: {
1334: char vstr[100], sstr[100], dstr[100];
1335: char usstr[100], udstr[100];
1336: char unsstr[100], undstr[100];
1337:
1338: switch (size) {
1339: case sz_byte:
1340: strcpy (vstr, "((uae_s8)(");
1341: strcpy (usstr, "((uae_u8)(");
1342: break;
1343: case sz_word:
1344: strcpy (vstr, "((uae_s16)(");
1345: strcpy (usstr, "((uae_u16)(");
1346: break;
1347: case sz_long:
1348: strcpy (vstr, "((uae_s32)(");
1349: strcpy (usstr, "((uae_u32)(");
1350: break;
1351: default:
1352: abort ();
1353: }
1354: strcpy (unsstr, usstr);
1355:
1356: strcpy (sstr, vstr);
1357: strcpy (dstr, vstr);
1358: strcat (vstr, value);
1359: strcat (vstr, "))");
1360: strcat (dstr, dst);
1361: strcat (dstr, "))");
1362: strcat (sstr, src);
1363: strcat (sstr, "))");
1364:
1365: strcpy (udstr, usstr);
1366: strcat (udstr, dst);
1367: strcat (udstr, "))");
1368: strcat (usstr, src);
1369: strcat (usstr, "))");
1370:
1371: strcpy (undstr, unsstr);
1372: strcat (unsstr, "-");
1373: strcat (undstr, "~");
1374: strcat (undstr, dst);
1375: strcat (undstr, "))");
1376: strcat (unsstr, src);
1377: strcat (unsstr, "))");
1378:
1379: switch (type) {
1380: case flag_logical_noclobber:
1381: case flag_logical:
1382: case flag_z:
1383: case flag_zn:
1384: case flag_av:
1385: case flag_sv:
1386: case flag_addx:
1387: case flag_subx:
1388: break;
1389:
1390: case flag_add:
1391: start_brace ();
1392: printf ("uae_u32 %s = %s + %s;\n", value, dstr, sstr);
1393: break;
1394: case flag_sub:
1395: case flag_cmp:
1396: start_brace ();
1397: printf ("uae_u32 %s = %s - %s;\n", value, dstr, sstr);
1398: break;
1399: }
1400:
1401: switch ((int)type) {
1402: case flag_logical_noclobber:
1403: case flag_logical:
1404: case flag_zn:
1405: break;
1406:
1407: case flag_add:
1408: case flag_sub:
1409: case flag_addx:
1410: case flag_subx:
1411: case flag_cmp:
1412: case flag_av:
1413: case flag_sv:
1414: start_brace ();
1415: printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
1416: printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
1417: printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
1418: break;
1419: }
1420:
1421: switch (type) {
1422: case flag_logical:
1423: printf ("\tCLEAR_CZNV ();\n");
1424: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1425: printf ("\tSET_NFLG (%s < 0);\n", vstr);
1426: break;
1427: case flag_logical_noclobber:
1428: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1429: printf ("\tSET_NFLG (%s < 0);\n", vstr);
1430: break;
1431: case flag_av:
1432: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
1433: break;
1434: case flag_sv:
1435: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
1436: break;
1437: case flag_z:
1438: printf ("\tSET_ZFLG (GET_ZFLG () & (%s == 0));\n", vstr);
1439: break;
1440: case flag_zn:
1441: printf ("\tSET_ZFLG (GET_ZFLG () & (%s == 0));\n", vstr);
1442: printf ("\tSET_NFLG (%s < 0);\n", vstr);
1443: break;
1444: case flag_add:
1445: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1446: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
1447: printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
1448: duplicate_carry (0);
1449: printf ("\tSET_NFLG (flgn != 0);\n");
1450: break;
1451: case flag_sub:
1452: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1453: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
1454: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
1455: duplicate_carry (0);
1456: printf ("\tSET_NFLG (flgn != 0);\n");
1457: break;
1458: case flag_addx:
1459: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
1460: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
1461: duplicate_carry (0);
1462: break;
1463: case flag_subx:
1464: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
1465: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
1466: duplicate_carry (0);
1467: break;
1468: case flag_cmp:
1469: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1470: printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
1471: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
1472: printf ("\tSET_NFLG (flgn != 0);\n");
1473: break;
1474: }
1475: }
1476:
1477: static void genflags (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
1478: {
1479: /* Temporarily deleted 68k/ARM flag optimizations. I'd prefer to have
1480: them in the appropriate m68k.h files and use just one copy of this
1481: code here. The API can be changed if necessary. */
1482: if (optimized_flags) {
1483: switch (type) {
1484: case flag_add:
1485: case flag_sub:
1486: start_brace ();
1487: printf ("\tuae_u32 %s;\n", value);
1488: break;
1489:
1490: default:
1491: break;
1492: }
1493:
1494: /* At least some of those casts are fairly important! */
1495: switch (type) {
1496: case flag_logical_noclobber:
1497: printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
1498: if (strcmp (value, "0") == 0) {
1499: printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
1500: } else {
1501: switch (size) {
1502: case sz_byte: printf ("\toptflag_testb (regs, (uae_s8)(%s));\n", value); break;
1503: case sz_word: printf ("\toptflag_testw (regs, (uae_s16)(%s));\n", value); break;
1504: case sz_long: printf ("\toptflag_testl (regs, (uae_s32)(%s));\n", value); break;
1505: }
1506: printf ("\tIOR_CZNV (oldcznv);\n");
1507: }
1508: printf ("\t}\n");
1509: return;
1510: case flag_logical:
1511: if (strcmp (value, "0") == 0) {
1512: printf ("\tSET_CZNV (FLAGVAL_Z);\n");
1513: } else {
1514: switch (size) {
1515: case sz_byte: printf ("\toptflag_testb (regs, (uae_s8)(%s));\n", value); break;
1516: case sz_word: printf ("\toptflag_testw (regs, (uae_s16)(%s));\n", value); break;
1517: case sz_long: printf ("\toptflag_testl (regs, (uae_s32)(%s));\n", value); break;
1518: }
1519: }
1520: return;
1521:
1522: case flag_add:
1523: switch (size) {
1524: case sz_byte: printf ("\toptflag_addb (regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
1525: case sz_word: printf ("\toptflag_addw (regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
1526: case sz_long: printf ("\toptflag_addl (regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
1527: }
1528: return;
1529:
1530: case flag_sub:
1531: switch (size) {
1532: case sz_byte: printf ("\toptflag_subb (regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
1533: case sz_word: printf ("\toptflag_subw (regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
1534: case sz_long: printf ("\toptflag_subl (regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
1535: }
1536: return;
1537:
1538: case flag_cmp:
1539: switch (size) {
1540: case sz_byte: printf ("\toptflag_cmpb (regs, (uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
1541: case sz_word: printf ("\toptflag_cmpw (regs, (uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
1542: case sz_long: printf ("\toptflag_cmpl (regs, (uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
1543: }
1544: return;
1545:
1546: default:
1547: break;
1548: }
1549: }
1550:
1551: genflags_normal (type, size, value, src, dst);
1552: }
1553:
1554: static void force_range_for_rox (const char *var, wordsizes size)
1555: {
1556: /* Could do a modulo operation here... which one is faster? */
1557: switch (size) {
1558: case sz_long:
1559: printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
1560: break;
1561: case sz_word:
1562: printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
1563: printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
1564: break;
1565: case sz_byte:
1566: printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
1567: printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
1568: printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
1569: break;
1570: }
1571: }
1572:
1573: static const char *cmask (wordsizes size)
1574: {
1575: switch (size) {
1576: case sz_byte: return "0x80";
1577: case sz_word: return "0x8000";
1578: case sz_long: return "0x80000000";
1579: default: abort ();
1580: }
1581: }
1582:
1583: static int source_is_imm1_8 (struct instr *i)
1584: {
1585: return i->stype == 3;
1586: }
1587:
1588: static void shift_ce (amodes dmode, int size)
1589: {
1590: if (using_ce && isreg (dmode)) {
1591: int c = size == sz_long ? 4 : 2;
1592: printf ("\t{\n");
1593: printf ("\t\tint cycles = %d;\n", c);
1594: printf ("\t\tcycles += 2 * ccnt;\n");
1595: addcycles000_3 ("\t\t");
1596: printf ("\t}\n");
1597: count_cycles += c;
1598: }
1599: }
1600:
1601: // BCHG/BSET/BCLR Dx,Dx or #xx,Dx adds 2 cycles if bit number > 15
1602: static void bsetcycles (struct instr *curi)
1603: {
1604: if (curi->size == sz_byte) {
1605: printf ("\tsrc &= 7;\n");
1606: } else {
1607: printf ("\tsrc &= 31;\n");
1608: if (isreg (curi->dmode)) {
1609: addcycles000 (2);
1610: if (curi->mnemo != i_BTST && using_ce) {
1611: printf ("\tif (src > 15) do_cycles_ce000 (2);\n");
1612: count_ncycles++;
1613: }
1614: }
1615: }
1616: }
1617:
1618: static int islongimm (struct instr *curi)
1619: {
1620: return (curi->size == sz_long && (curi->smode == Dreg || curi->smode == imm));
1621: }
1622:
1623: static void gen_opcode (unsigned long int opcode)
1624: {
1625: struct instr *curi = table68k + opcode;
1626:
1627: insn_n_cycles = using_prefetch ? 0 : 4;
1628:
1.1.1.2 root 1629: /* Store the family of the instruction (used to check for pairing on ST)
1630: * and leave some space for patching in the current cycles later */
1631: if (!using_ce020) {
1632: printf ("\tOpcodeFamily = %d; CurrentInstrCycles = \n", curi->mnemo);
1633: nCurInstrCycPos = ftell(stdout) - 5;
1634: }
1635: else if (using_ce020 == 2) {
1636: /* Initialize the cycle table to the general table by default */
1637: instr_table = TABLE_FALCON_CYCLES;
1638: instr_table_index = instr_index;
1639: no_return_cycles = false;
1640: }
1.1 root 1641:
1642: if (using_ce020) {
1643: if (using_ce020 == 2) {
1644: ce020_prefetch_long = "get_long_ce030_prefetch";
1645: ce020_prefetch_word = "get_word_ce030_prefetch";
1646: srcl = "get_long_ce030";
1647: dstl = "put_long_ce030";
1648: srcw = "get_word_ce030";
1649: dstw = "put_word_ce030";
1650: srcb = "get_byte_ce030";
1651: dstb = "put_byte_ce030";
1652: } else {
1653: ce020_prefetch_long = "get_long_ce020_prefetch";
1654: ce020_prefetch_word = "get_word_ce020_prefetch";
1655: srcl = "get_long_ce020";
1656: dstl = "put_long_ce020";
1657: srcw = "get_word_ce020";
1658: dstw = "put_word_ce020";
1659: srcb = "get_byte_ce020";
1660: dstb = "put_byte_ce020";
1661: }
1662: } else if (using_mmu) {
1663: srcl = "get_long_mmu";
1664: dstl = "put_long_mmu";
1665: srcw = "get_word_mmu";
1666: dstw = "put_word_mmu";
1667: srcb = "get_byte_mmu";
1668: dstb = "put_byte_mmu";
1669: } else if (using_ce) {
1670: srcl = "get_long_ce";
1671: dstl = "put_long_ce";
1672: srcw = "get_word_ce";
1673: dstw = "put_word_ce";
1674: srcb = "get_byte_ce";
1675: dstb = "put_byte_ce";
1676: } else {
1677: srcl = "get_long";
1678: dstl = "put_long";
1679: srcw = "get_word";
1680: dstw = "put_word";
1681: srcb = "get_byte";
1682: dstb = "put_byte";
1683: }
1684:
1685: insn_n_cycles020 = 0;
1686:
1687: start_brace ();
1688: m68k_pc_offset = 2;
1689: switch (curi->plev) {
1690: case 0: /* not privileged */
1691: break;
1692: case 1: /* unprivileged only on 68000 */
1693: if (cpu_level == 0)
1694: break;
1695: if (next_cpu_level < 0)
1696: next_cpu_level = 0;
1697:
1698: /* fall through */
1699: case 2: /* priviledged */
1700: printf ("if (!regs.s) { Exception (8, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1701: need_endlabel = 1;
1702: start_brace ();
1703: break;
1704: case 3: /* privileged if size == word */
1705: if (curi->size == sz_byte)
1706: break;
1707: printf ("if (!regs.s) { Exception (8, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1708: need_endlabel = 1;
1709: start_brace ();
1710: break;
1711: }
1712: switch (curi->mnemo) {
1713: case i_OR:
1714: case i_AND:
1715: case i_EOR:
1716: {
1717: int c = 0;
1718: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1719: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
1720: printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
1721: genflags (flag_logical, curi->size, "src", "", "");
1722: if (curi->dmode == Dreg && curi->size == sz_long) {
1723: c += 2;
1724: if (curi->smode == imm || curi->smode == Dreg)
1725: c += 2;
1726: }
1727: fill_prefetch_next ();
1728: if (c > 0)
1729: addcycles000 (c);
1730: genastore_rev ("src", curi->dmode, "dstreg", curi->size, "dst");
1731: break;
1732: }
1733: // all SR/CCR modifications have dummy read access
1734: case i_ORSR:
1735: case i_EORSR:
1736: printf ("\tMakeSR ();\n");
1737: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1738: dummy_prefetch ();
1739: if (curi->size == sz_byte) {
1740: printf ("\tsrc &= 0xFF;\n");
1741: }
1742: addcycles000 (8);
1743: fill_prefetch_next ();
1744: printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
1745: printf ("\tMakeFromSR ();\n");
1746: break;
1747: case i_ANDSR:
1748: printf ("\tMakeSR ();\n");
1749: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1750: dummy_prefetch ();
1751: if (curi->size == sz_byte) {
1752: printf ("\tsrc |= 0xFF00;\n");
1753: }
1754: addcycles000 (8);
1755: fill_prefetch_next ();
1756: printf ("\tregs.sr &= src;\n");
1757: printf ("\tMakeFromSR ();\n");
1758: break;
1759: case i_SUB:
1760: {
1761: int c = 0;
1762: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1763: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
1764: if (curi->dmode == Dreg) {
1765: if (curi->size == sz_long) {
1766: c += 2;
1767: if (curi->smode == imm || curi->smode == immi || curi->smode == Dreg)
1768: c += 2;
1769: }
1770: }
1771: fill_prefetch_next ();
1772: if (c > 0)
1773: addcycles000 (c);
1774: start_brace ();
1775: genflags (flag_sub, curi->size, "newv", "src", "dst");
1776: genastore_rev ("newv", curi->dmode, "dstreg", curi->size, "dst");
1777: break;
1778: }
1779: case i_SUBA:
1780: {
1781: int c = 0;
1782: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1783: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
1784: if (curi->smode == immi) {
1785: // SUBAQ.x is always 8 cycles
1786: c += 4;
1787: } else {
1788: c = curi->size == sz_long ? 2 : 4;
1789: if (islongimm (curi))
1790: c += 2;
1791: }
1792: fill_prefetch_next ();
1793: if (c > 0)
1794: addcycles000 (c);
1795: start_brace ();
1796: printf ("\tuae_u32 newv = dst - src;\n");
1797: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1798: break;
1799: }
1800: case i_SUBX:
1801: if (!isreg (curi->smode))
1802: addcycles000 (2);
1803: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1804: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1805: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1806: fill_prefetch_next ();
1807: if (curi->size == sz_long && isreg (curi->smode))
1808: addcycles000 (4);
1809: start_brace ();
1810: printf ("\tuae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);\n");
1811: genflags (flag_subx, curi->size, "newv", "src", "dst");
1812: genflags (flag_zn, curi->size, "newv", "", "");
1813: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1814: break;
1815: case i_SBCD:
1816: if (!isreg (curi->smode))
1817: addcycles000 (2);
1818: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1819: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1820: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1821: fill_prefetch_next ();
1822: start_brace ();
1823: printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
1824: printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
1825: printf ("\tuae_u16 newv, tmp_newv;\n");
1826: printf ("\tint bcd = 0;\n");
1827: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
1828: printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
1829: printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
1830: printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);\n");
1831: duplicate_carry (0);
1832: /* Manual says bits NV are undefined though a real 68040/060 don't change them */
1833: if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1834: if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1835: next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1836: genflags (flag_z, curi->size, "newv", "", "");
1837: } else {
1838: genflags (flag_zn, curi->size, "newv", "", "");
1839: printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
1840: }
1841: if (isreg (curi->smode))
1842: addcycles000 (2);
1843: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1844: break;
1845: case i_ADD:
1846: {
1847: int c = 0;
1848: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1849: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
1850: if (curi->dmode == Dreg) {
1851: if (curi->size == sz_long) {
1852: c += 2;
1853: if (curi->smode == imm || curi->smode == immi || curi->smode == Dreg)
1854: c += 2;
1855: }
1856: }
1857: fill_prefetch_next ();
1858: if (c > 0)
1859: addcycles000 (c);
1860: start_brace ();
1861: genflags (flag_add, curi->size, "newv", "src", "dst");
1862: genastore_rev ("newv", curi->dmode, "dstreg", curi->size, "dst");
1863: break;
1864: }
1865: case i_ADDA:
1866: {
1867: int c = 0;
1868: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1869: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
1870: if (curi->smode == immi) {
1871: // ADDAQ.x is always 8 cycles
1872: c += 4;
1873: } else {
1874: c = curi->size == sz_long ? 2 : 4;
1875: if (islongimm (curi))
1876: c += 2;
1877: }
1878: fill_prefetch_next ();
1879: if (c > 0)
1880: addcycles000 (c);
1881: start_brace ();
1882: printf ("\tuae_u32 newv = dst + src;\n");
1883: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1884: break;
1885: }
1886: case i_ADDX:
1887: if (!isreg (curi->smode))
1888: addcycles000 (2);
1889: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1890: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1891: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1892: fill_prefetch_next ();
1893: if (curi->size == sz_long && isreg (curi->smode))
1894: addcycles000 (4);
1895: start_brace ();
1896: printf ("\tuae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);\n");
1897: genflags (flag_addx, curi->size, "newv", "src", "dst");
1898: genflags (flag_zn, curi->size, "newv", "", "");
1899: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1900: break;
1901: case i_ABCD:
1902: if (!isreg (curi->smode))
1903: addcycles000 (2);
1904: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1905: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1906: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1907: fill_prefetch_next ();
1908: start_brace ();
1909: printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);\n");
1910: printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
1911: printf ("\tuae_u16 newv, tmp_newv;\n");
1912: printf ("\tint cflg;\n");
1913: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
1914: printf ("\tif (newv_lo > 9) { newv += 6; }\n");
1915: printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
1916: printf ("\tif (cflg) newv += 0x60;\n");
1917: printf ("\tSET_CFLG (cflg);\n");
1918: duplicate_carry (0);
1919: /* Manual says bits NV are undefined though a real 68040 don't change them */
1920: if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1921: if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1922: next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1923: genflags (flag_z, curi->size, "newv", "", "");
1924: }
1925: else {
1926: genflags (flag_zn, curi->size, "newv", "", "");
1927: printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
1928: }
1929: if (isreg (curi->smode))
1930: addcycles000 (2);
1931: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1932: break;
1933: case i_NEG:
1934: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1935: fill_prefetch_next ();
1936: if (isreg (curi->smode) && curi->size == sz_long)
1937: addcycles000 (2);
1938: start_brace ();
1939: genflags (flag_sub, curi->size, "dst", "src", "0");
1940: genastore_rev ("dst", curi->smode, "srcreg", curi->size, "src");
1941: break;
1942: case i_NEGX:
1943: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1944: fill_prefetch_next ();
1945: if (isreg (curi->smode) && curi->size == sz_long)
1946: addcycles000 (2);
1947: start_brace ();
1948: printf ("\tuae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);\n");
1949: genflags (flag_subx, curi->size, "newv", "src", "0");
1950: genflags (flag_zn, curi->size, "newv", "", "");
1951: genastore_rev ("newv", curi->smode, "srcreg", curi->size, "src");
1952: break;
1953: case i_NBCD:
1954: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1955: if (isreg (curi->smode))
1956: addcycles000 (2);
1957: fill_prefetch_next ();
1958: start_brace ();
1959: printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
1960: printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1961: printf ("\tuae_u16 newv;\n");
1962: printf ("\tint cflg;\n");
1963: printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1964: printf ("\tnewv = newv_hi + newv_lo;");
1965: printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1966: printf ("\tif (cflg) newv -= 0x60;\n");
1967: printf ("\tSET_CFLG (cflg);\n");
1968: duplicate_carry(0);
1969: /* Manual says bits NV are undefined though a real 68040 don't change them */
1970: if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1971: if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1972: next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1973: genflags (flag_z, curi->size, "newv", "", "");
1974: }
1975: else {
1976: genflags (flag_zn, curi->size, "newv", "", "");
1977: }
1978: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1979: break;
1980: case i_CLR:
1981: genamode (curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, 0);
1982: fill_prefetch_next ();
1983: if (isreg (curi->smode) && curi->size == sz_long)
1984: addcycles000 (2);
1985: genflags (flag_logical, curi->size, "0", "", "");
1986: genastore_rev ("0", curi->smode, "srcreg", curi->size, "src");
1987: break;
1988: case i_NOT:
1989: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1990: fill_prefetch_next ();
1991: if (isreg (curi->smode) && curi->size == sz_long)
1992: addcycles000 (2);
1993: start_brace ();
1994: printf ("\tuae_u32 dst = ~src;\n");
1995: genflags (flag_logical, curi->size, "dst", "", "");
1996: genastore_rev ("dst", curi->smode, "srcreg", curi->size, "src");
1997: break;
1998: case i_TST:
1999: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2000: fill_prefetch_next ();
2001: genflags (flag_logical, curi->size, "src", "", "");
2002: break;
2003: case i_BTST:
2004: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2005: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2006: fill_prefetch_next ();
2007: bsetcycles (curi);
2008: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
2009: break;
2010: case i_BCHG:
2011: case i_BCLR:
2012: case i_BSET:
2013: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2014: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2015: fill_prefetch_next ();
2016: bsetcycles (curi);
2017: // bclr needs 1 extra cycle
2018: if (curi->mnemo == i_BCLR && curi->dmode == Dreg)
2019: addcycles000 (2);
2020: if (curi->mnemo == i_BCHG) {
2021: printf ("\tdst ^= (1 << src);\n");
2022: printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
2023: } else if (curi->mnemo == i_BCLR) {
2024: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
2025: printf ("\tdst &= ~(1 << src);\n");
2026: } else if (curi->mnemo == i_BSET) {
2027: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
2028: printf ("\tdst |= (1 << src);\n");
2029: }
2030: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
2031: break;
2032: case i_CMPM:
2033: // confirmed
2034: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
2035: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
2036: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
2037: fill_prefetch_next ();
2038: start_brace ();
2039: genflags (flag_cmp, curi->size, "newv", "src", "dst");
2040: break;
2041: case i_CMP:
2042: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2043: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2044: fill_prefetch_next ();
2045: if (curi->dmode == Dreg && curi->size == sz_long)
2046: addcycles000 (2);
2047: start_brace ();
2048: genflags (flag_cmp, curi->size, "newv", "src", "dst");
2049: break;
2050: case i_CMPA:
2051: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2052: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
2053: fill_prefetch_next ();
2054: addcycles000 (2);
2055: start_brace ();
2056: genflags (flag_cmp, sz_long, "newv", "src", "dst");
2057: break;
2058: /* The next two are coded a little unconventional, but they are doing
2059: * weird things... */
2060: case i_MVPRM: // MOVEP R->M
2061: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2062: printf ("\tuaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
2063: if (curi->size == sz_word) {
1.1.1.2 root 2064: printf ("\tMovepByteNbr=1; %s (memp, src >> 8); MovepByteNbr=2; %s (memp + 2, src);\n", dstb, dstb);
1.1 root 2065: count_write += 2;
2066: } else {
1.1.1.2 root 2067: printf ("\tMovepByteNbr=1; %s (memp, src >> 24); MovepByteNbr=2; %s (memp + 2, src >> 16);\n", dstb, dstb);
2068: printf ("\tMovepByteNbr=3; %s (memp + 4, src >> 8); MovepByteNbr=4; %s (memp + 6, src);\n", dstb, dstb);
1.1 root 2069: count_write += 4;
2070: }
2071: fill_prefetch_next ();
2072: break;
2073: case i_MVPMR: // MOVEP M->R
2074: printf ("\tuaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
2075: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
2076: if (curi->size == sz_word) {
2077: printf ("\tuae_u16 val = (%s (memp) << 8) + %s (memp + 2);\n", srcb, srcb);
2078: count_read += 2;
2079: } else {
2080: printf ("\tuae_u32 val = (%s (memp) << 24) + (%s (memp + 2) << 16)\n", srcb, srcb);
2081: printf (" + (%s (memp + 4) << 8) + %s (memp + 6);\n", srcb, srcb);
2082: count_read += 4;
2083: }
2084: fill_prefetch_next ();
2085: genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
2086: break;
2087: case i_MOVE:
2088: case i_MOVEA:
2089: {
2090: /* 2 MOVE instruction variants have special prefetch sequence:
2091: * - MOVE <ea>,-(An) = prefetch is before writes (Apdi)
2092: * - MOVE memory,(xxx).L = 2 prefetches after write
2093: * - all others = prefetch is done after writes
2094: *
2095: * - move.x xxx,[at least 1 extension word here] = fetch 1 extension word before (xxx)
2096: *
2097: */
2098: int prefetch_done = 0, flags;
2099: int dualprefetch = curi->dmode == absl && (curi->smode != Dreg && curi->smode != Areg && curi->smode != imm);
2100: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_MOVE);
2101: flags = 1 | (dualprefetch ? GF_NOREFILL : 0);
2102: genamode2 (curi->dmode, "dstreg", curi->size, "dst", 2, 0, flags | GF_MOVE, 0);
2103: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2104: if (curi->mnemo == i_MOVEA && curi->size == sz_word)
2105: printf ("\tsrc = (uae_s32)(uae_s16)src;\n");
2106: if (curi->dmode == Apdi) {
2107: fill_prefetch_next ();
2108: prefetch_done = 1;
2109: }
2110: if (curi->mnemo == i_MOVE)
2111: genflags (flag_logical, curi->size, "src", "", "");
2112: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2113: sync_m68k_pc ();
2114: if (dualprefetch) {
2115: fill_prefetch_full ();
2116: prefetch_done = 1;
2117: }
2118: if (!prefetch_done)
2119: fill_prefetch_next ();
2120: }
2121: break;
2122: case i_MVSR2: // MOVE FROM SR
2123: genamode (curi->smode, "srcreg", sz_word, "src", 2, 0, 0);
2124: fill_prefetch_next ();
2125: if (isreg (curi->smode))
2126: addcycles000 (2);
2127: printf ("\tMakeSR ();\n");
2128: if (curi->size == sz_byte)
2129: genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
2130: else
2131: genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
2132: break;
2133: case i_MV2SR: // MOVE TO SR
2134: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2135: if (curi->size == sz_byte) {
2136: // MOVE TO CCR
2137: dummy_prefetch ();
2138: addcycles000 (4);
2139: printf ("\tMakeSR ();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
2140: } else {
2141: // MOVE TO SR
2142: dummy_prefetch ();
2143: addcycles000 (4);
2144: printf ("\tregs.sr = src;\n");
2145: }
2146: printf ("\tMakeFromSR ();\n");
2147: fill_prefetch_next ();
2148: break;
2149: case i_SWAP:
2150: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
2151: fill_prefetch_next ();
2152: start_brace ();
2153: printf ("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
2154: genflags (flag_logical, sz_long, "dst", "", "");
2155: genastore ("dst", curi->smode, "srcreg", sz_long, "src");
2156: break;
2157: case i_EXG:
2158: // confirmed
2159: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2160: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2161: fill_prefetch_next ();
2162: addcycles000 (2);
2163: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
2164: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2165: break;
2166: case i_EXT:
2167: // confirmed
2168: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
2169: fill_prefetch_next ();
2170: start_brace ();
2171: switch (curi->size) {
2172: case sz_byte: printf ("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
2173: case sz_word: printf ("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
2174: case sz_long: printf ("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
2175: default: abort ();
2176: }
2177: genflags (flag_logical,
2178: curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
2179: genastore ("dst", curi->smode, "srcreg",
2180: curi->size == sz_word ? sz_word : sz_long, "src");
2181: break;
2182: case i_MVMEL:
2183: // confirmed
2184: if (using_ce)
2185: genmovemel_ce (opcode);
2186: else
2187: genmovemel (opcode);
2188: break;
2189: case i_MVMLE:
2190: // confirmed
2191: if (using_ce)
2192: genmovemle_ce (opcode);
2193: else
2194: genmovemle (opcode);
2195: break;
2196: case i_TRAP:
2197: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2198: gen_set_fault_pc ();
2199: sync_m68k_pc ();
2200: printf ("\tException (src + 32, 0 ,M68000_EXC_SRC_CPU);\n");
2201: did_prefetch = 1;
2202: m68k_pc_offset = 0;
2203: break;
2204: case i_MVR2USP:
2205: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2206: fill_prefetch_next ();
2207: printf ("\tregs.usp = src;\n");
2208: break;
2209: case i_MVUSP2R:
2210: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0, 0);
2211: fill_prefetch_next ();
2212: genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
2213: break;
2214: case i_RESET:
2215: fill_prefetch_next ();
2216: printf ("\tcpureset ();\n");
2217: addcycles000 (128);
2218: if (using_prefetch)
2219: printf ("\tregs.irc = get_iword (4);\n");
2220: break;
2221: case i_NOP:
2222: fill_prefetch_next ();
2223: break;
2224: case i_STOP:
2225: if (using_prefetch) {
2226: printf ("\tregs.sr = regs.irc;\n");
2227: m68k_pc_offset += 2;
2228: } else {
2229: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2230: printf ("\tregs.sr = src;\n");
2231: }
2232: printf ("\tMakeFromSR ();\n");
2233: printf ("\tm68k_setstopped ();\n");
2234: sync_m68k_pc ();
2235: // STOP does not prefetch anything
2236: did_prefetch = -1;
2237: break;
2238: case i_LPSTOP: /* 68060 */
2239: printf ("\tuae_u16 sw = get_iword (2);\n");
2240: printf ("\tuae_u16 sr;\n");
2241: printf ("\tif (sw != (0x100|0x80|0x40)) { Exception (4, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
2242: printf ("\tsr = get_iword (4);\n");
2243: printf ("\tif (!(sr & 0x8000)) { Exception (8, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
2244: printf ("\tregs.sr = sr;\n");
2245: printf ("\tMakeFromSR ();\n");
2246: printf ("\tm68k_setstopped();\n");
2247: m68k_pc_offset += 4;
2248: sync_m68k_pc ();
2249: fill_prefetch_full ();
2250: break;
2251: case i_RTE:
2252: if (cpu_level == 0) {
2253: genamode (Aipi, "7", sz_word, "sr", 1, 0, GF_NOREFILL);
2254: genamode (Aipi, "7", sz_long, "pc", 1, 0, GF_NOREFILL);
2255: printf ("\tregs.sr = sr;\n");
2256: setpc ("pc");
2257: printf ("\tMakeFromSR ();\n");
2258: } else {
2259: int old_brace_level = n_braces;
2260: if (next_cpu_level < 0)
2261: next_cpu_level = 0;
2262: printf ("\tuae_u16 newsr; uae_u32 newpc;\n");
2263: printf ("\tfor (;;) {\n");
2264: printf ("\t\tuaecptr a = m68k_areg (regs, 7);\n");
2265: printf ("\t\tuae_s16 sr = %s (a);\n", srcw);
2266: printf ("\t\tuae_s32 pc = %s (a + 2);\n", srcl);
2267: printf ("\t\tuae_s16 format = %s (a + 2 + 4);\n", srcw);
2268: printf ("\t\tint frame = format >> 12;\n");
2269: printf ("\t\tint offset = 8;\n");
2270: printf ("\t\tnewsr = sr; newpc = pc;\n");
2271: printf ("\t\tif (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }\n");
2272: printf ("\t\telse if (frame == 0x1) { m68k_areg (regs, 7) += offset; }\n");
2273: printf ("\t\telse if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }\n");
2274: printf ("\t\telse if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }\n");
2275: if (using_mmu)
2276: printf ("\t\telse if (frame == 0x7) { m68k_do_rte_mmu (a); m68k_areg (regs, 7) += offset + 52; break; }\n");
2277: printf ("\t\telse if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }\n");
2278: printf ("\t\telse if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }\n");
2279: printf ("\t\telse if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }\n");
2280: printf ("\t\telse if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }\n");
2281: printf ("\t\telse { m68k_areg (regs, 7) += offset; Exception (14, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
2282: printf ("\t\tregs.sr = newsr; MakeFromSR ();\n}\n");
2283: pop_braces (old_brace_level);
2284: printf ("\tregs.sr = newsr; MakeFromSR ();\n");
2285: printf ("\tif (newpc & 1) {\n");
2286: printf ("\t\texception3i (0x%04X, m68k_getpc (), newpc);\n", opcode);
2287: printf ("\t\tgoto %s;\n", endlabelstr);
2288: printf ("\t}\n");
2289: printf ("\t\tm68k_setpc (newpc);\n");
2290: printf ("\tipl_fetch ();\n");
2291: need_endlabel = 1;
2292: }
1.1.1.2 root 2293: instr_table = TABLE_FALCON_CYCLES_RTE;
2294: instr_table_index = 0;
1.1 root 2295: /* PC is set and prefetch filled. */
2296: m68k_pc_offset = 0;
2297: fill_prefetch_full ();
2298: break;
2299: case i_RTD:
2300: if (using_mmu) {
2301: genamode (curi->smode, "srcreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2302: genamode (Aipi, "7", sz_long, "pc", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2303: printf ("\tm68k_areg(regs, 7) += offs;\n");
2304: } else {
2305: genamode (Aipi, "7", sz_long, "pc", 1, 0, 0);
2306: genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0, 0);
2307: printf ("\tm68k_areg (regs, 7) += offs;\n");
2308: printf ("\tif (pc & 1) {\n");
2309: printf ("\t\texception3i (0x%04X, m68k_getpc (), pc);\n", opcode);
2310: printf ("\t\tgoto %s;\n", endlabelstr);
2311: printf ("\t}\n");
2312: }
2313: printf ("\tif (pc & 1) {\n");
2314: printf ("\t\texception3i (0x%04X, m68k_getpc(), pc);\n", opcode);
2315: printf ("\t\tgoto %s;\n", endlabelstr);
2316: printf ("\t}\n");
2317: setpc ("pc");
2318: /* PC is set and prefetch filled. */
2319: m68k_pc_offset = 0;
2320: fill_prefetch_full ();
2321: need_endlabel = 1;
2322: break;
2323: case i_LINK:
2324: // ce confirmed
2325: if (using_mmu) {
2326: genamode (curi->dmode, "dstreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2327: genamode (Apdi, "7", sz_long, "old", GENA_GETV_FETCH_ALIGN, GENA_MOVEM_DO_INC, 0);
2328: genamode (curi->smode, "srcreg", sz_long, "src", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2329: genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
2330: printf ("\tm68k_areg(regs, 7) += offs;\n");
2331: genastore ("src", Apdi, "7", sz_long, "old");
2332: } else {
2333: genamode (Apdi, "7", sz_long, "old", 2, 0, GF_AA);
2334: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0, GF_AA);
2335: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0, 0);
2336: genastore ("src", Apdi, "7", sz_long, "old");
2337: genastore ("m68k_areg (regs, 7)", curi->smode, "srcreg", sz_long, "src");
2338: printf ("\tm68k_areg (regs, 7) += offs;\n");
2339: fill_prefetch_next ();
2340: }
2341: break;
2342: case i_UNLK:
2343: // ce confirmed
2344: if (using_mmu) {
2345: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2346: printf ("\tuae_s32 old = get_long_mmu (src);\n");
2347: printf ("\tm68k_areg (regs, 7) = src + 4;\n");
2348: printf ("\tm68k_areg (regs, srcreg) = old;\n");
2349: } else {
2350: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2351: printf ("\tm68k_areg (regs, 7) = src;\n");
2352: genamode (Aipi, "7", sz_long, "old", 1, 0, 0);
2353: fill_prefetch_next ();
2354: genastore ("old", curi->smode, "srcreg", curi->size, "src");
2355: }
2356: break;
2357: case i_RTS:
2358: printf ("\tuaecptr pc = m68k_getpc ();\n");
2359: if (using_ce020 == 1)
2360: printf ("\tm68k_do_rts_ce020 ();\n");
2361: else if (using_ce020 == 2)
2362: printf ("\tm68k_do_rts_ce030 ();\n");
2363: else if (using_ce)
2364: printf ("\tm68k_do_rts_ce ();\n");
2365: else if (using_indirect)
2366: printf ("\tm68k_do_rtsi ();\n");
2367: else if (using_mmu)
2368: printf ("\tm68k_do_rts_mmu ();\n");
2369: else
2370: printf ("\tm68k_do_rts ();\n");
2371: printf ("\tif (m68k_getpc () & 1) {\n");
2372: printf ("\t\tuaecptr faultpc = m68k_getpc ();\n");
2373: printf ("\t\tm68k_setpc (pc);\n");
2374: printf ("\t\texception3i (0x%04X, pc, faultpc);\n", opcode);
2375: printf ("\t\tgoto %s;\n", endlabelstr);
2376: printf ("\t}\n");
2377: count_read += 2;
2378: m68k_pc_offset = 0;
2379: fill_prefetch_full ();
2380: need_endlabel = 1;
2381: break;
2382: case i_TRAPV:
2383: sync_m68k_pc ();
2384: fill_prefetch_next ();
2385: printf ("\tif (GET_VFLG ()) {\n");
2386: printf ("\t\tException (7, m68k_getpc () ,M68000_EXC_SRC_CPU);\n");
2387: printf ("\t\tgoto %s;\n", endlabelstr);
2388: printf ("\t}\n");
2389: need_endlabel = 1;
2390: break;
2391: case i_RTR:
2392: printf ("\tMakeSR ();\n");
2393: genamode_pre (Aipi, "7", sz_word, "sr", 1, 0, 0);
2394: genamode (Aipi, "7", sz_long, "pc", 1, 0, 0);
2395: genamode_post (Aipi, "7", sz_word, "sr", 1, 0, 0);
2396: printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
2397: printf ("\tregs.sr |= sr;\n");
2398: setpc ("pc");
2399: printf ("\tMakeFromSR ();\n");
2400: m68k_pc_offset = 0;
2401: fill_prefetch_full ();
2402: break;
2403: case i_JSR: // TODO: check stack write order
2404: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA|GF_NOREFILL);
2405: start_brace ();
2406: printf ("\tuaecptr oldpc = m68k_getpc () + %d;\n", m68k_pc_offset);
2407: if (using_exception_3) {
2408: printf ("\tif (srca & 1) {\n");
2409: printf ("\t\texception3i (opcode, oldpc, srca);\n");
2410: printf ("\t\tgoto %s;\n", endlabelstr);
2411: printf ("\t}\n");
2412: need_endlabel = 1;
2413: }
2414: if (using_mmu) {
2415: printf ("\t%s (m68k_areg (regs, 7) - 4, oldpc);\n", dstl);
2416: printf ("\tm68k_areg (regs, 7) -= 4;\n");
2417: setpc ("srca");
2418: m68k_pc_offset = 0;
2419: } else {
2420: if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16)
2421: addcycles000 (2);
2422: setpc ("srca");
2423: m68k_pc_offset = 0;
2424: fill_prefetch_1 (0);
2425: if (curi->smode == Ad8r || curi->smode == PC8r)
2426: addcycles000 (6);
2427: printf ("\tm68k_areg (regs, 7) -= 4;\n");
2428: if (using_ce) {
2429: printf ("\tput_word_ce (m68k_areg (regs, 7), oldpc >> 16);\n");
2430: printf ("\tput_word_ce (m68k_areg (regs, 7) + 2, oldpc);\n");
2431: } else {
2432: printf ("\t%s (m68k_areg (regs, 7), oldpc);\n", dstl);
2433: }
2434: }
2435: count_write += 2;
2436: fill_prefetch_next ();
2437: break;
2438: case i_JMP:
2439: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA | ((curi->smode == Ad8r || curi->smode == PC8r) ? 0 : GF_NOREFILL));
2440: if (using_exception_3) {
2441: printf ("\tif (srca & 1) {\n");
2442: printf ("\t\texception3i (opcode, m68k_getpc () + 6, srca);\n");
2443: printf ("\t\tgoto %s;\n", endlabelstr);
2444: printf ("\t}\n");
2445: need_endlabel = 1;
2446: }
2447: if (curi->smode == Ad16 || curi->smode == Ad8r || curi->smode == absw || curi->smode == PC16 || curi->smode == PC8r)
2448: addcycles000 (2);
2449: setpc ("srca");
2450: m68k_pc_offset = 0;
2451: fill_prefetch_full ();
2452: break;
2453: case i_BSR:
2454: // .b and .w confirmed
2455: printf ("\tuae_s32 s;\n");
2456: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA|GF_NOREFILL);
2457: printf ("\ts = (uae_s32)src + 2;\n");
2458: if (using_exception_3) {
2459: printf ("\tif (src & 1) {\n");
2460: printf ("\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + s);\n");
2461: printf ("\t\tgoto %s;\n", endlabelstr);
2462: printf ("\t}\n");
2463: need_endlabel = 1;
2464: }
2465: addcycles000 (2);
2466: if (using_ce020 == 1) {
2467: printf ("\tm68k_do_bsr_ce020 (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2468: } else if (using_ce020 == 2) {
2469: printf ("\tm68k_do_bsr_ce030 (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2470: } else if (using_ce) {
2471: printf ("\tm68k_do_bsr_ce (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2472: } else if (using_indirect) {
2473: printf ("\tm68k_do_bsri (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2474: } else if (using_mmu) {
2475: printf ("\tm68k_do_bsr_mmu (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2476: } else {
2477: printf ("\tm68k_do_bsr (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2478: }
2479: count_write += 2;
2480: m68k_pc_offset = 0;
2481: fill_prefetch_full ();
2482: break;
2483: case i_Bcc:
2484: // bcc.b branch: idle cycle, prefetch, prefetch
2485: // bcc.b not branch: 2 idle cycles, prefetch
1.1.1.2 root 2486:
2487: instr_table = TABLE_FALCON_CYCLES_BCC;
2488:
1.1 root 2489: if (curi->size == sz_long) {
2490: if (cpu_level < 2) {
2491: addcycles000 (2);
2492: printf ("\tif (cctrue (%d)) {\n", curi->cc);
2493: printf ("\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + 1);\n");
2494: printf ("\t\tgoto %s;\n", endlabelstr);
2495: printf ("\t}\n");
2496: sync_m68k_pc ();
2497: irc2ir ();
2498: fill_prefetch_2 ();
2499: printf ("\tgoto %s;\n", endlabelstr);
2500: need_endlabel = 1;
2501: } else {
2502: if (next_cpu_level < 1)
2503: next_cpu_level = 1;
2504: }
2505: }
2506: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_NOREFILL);
2507: addcycles000 (2);
2508: printf ("\tif (!cctrue (%d)) goto didnt_jump;\n", curi->cc);
2509: if (using_exception_3) {
2510: printf ("\tif (src & 1) {\n");
2511: printf ("\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + 2 + (uae_s32)src);\n");
2512: printf ("\t\tgoto %s;\n", endlabelstr);
2513: printf ("\t}\n");
2514: need_endlabel = 1;
2515: }
2516: if (using_prefetch) {
2517: incpc ("(uae_s32)src + 2");
2518: fill_prefetch_full ();
2519: if (using_ce)
2520: printf ("\treturn;\n");
2521: else
2522: printf ("\treturn 10 * CYCLE_UNIT / 2;\n");
2523: } else {
2524: incpc ("(uae_s32)src + 2");
1.1.1.2 root 2525: instr_table_index = 0;
2526: returncycles ("", 10);
1.1 root 2527: }
2528: printf ("didnt_jump:;\n");
2529: need_endlabel = 1;
2530: sync_m68k_pc ();
2531: if (curi->size == sz_byte) {
2532: addcycles000 (2);
2533: irc2ir ();
2534: fill_prefetch_2 ();
2535: } else if (curi->size == sz_word) {
2536: addcycles000 (2);
2537: fill_prefetch_full ();
2538: } else {
2539: fill_prefetch_full ();
2540: }
1.1.1.3 ! root 2541: if (using_ce020 == 2) { /* For Falcon cycle exact timings only (CPU_EMU_21) */
1.1.1.2 root 2542: if (curi->size == sz_byte)
2543: instr_table_index = 1;
2544: else if (curi->size == sz_word)
2545: instr_table_index = 2;
2546: else
2547: instr_table_index = 3;
2548: }
1.1 root 2549: insn_n_cycles = curi->size == sz_byte ? 8 : 12;
2550: break;
2551: case i_LEA:
2552: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA);
2553: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, GF_AA);
2554: if (curi->smode == Ad8r || curi->smode == PC8r)
2555: addcycles000 (2);
2556: fill_prefetch_next ();
2557: if (curi->smode == Ad8r || curi->smode == PC8r)
2558: addcycles000 (2);
2559: genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
2560: break;
2561: case i_PEA:
2562: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA);
2563: genamode (Apdi, "7", sz_long, "dst", 2, 0, GF_AA);
2564: if (curi->smode == Ad8r || curi->smode == PC8r)
2565: addcycles000 (2);
2566: if (!(curi->smode == absw || curi->smode == absl))
2567: fill_prefetch_next ();
2568: if (curi->smode == Ad8r || curi->smode == PC8r)
2569: addcycles000 (2);
2570: genastore ("srca", Apdi, "7", sz_long, "dst");
2571: if ((curi->smode == absw || curi->smode == absl))
2572: fill_prefetch_next ();
2573: break;
2574: case i_DBcc:
1.1.1.3 ! root 2575: no_return_cycles = true;
1.1 root 2576: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_NOREFILL);
2577: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0, GF_AA | GF_NOREFILL);
2578: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2579: addcycles000 (2);
2580: printf ("\tif (!cctrue (%d)) {\n", curi->cc);
1.1.1.3 ! root 2581: printf ("\t");incpc ("(uae_s32)offs + 2");
! 2582: fill_prefetch_1 (0);
! 2583: printf ("\t");genastore ("(src - 1)", curi->smode, "srcreg", curi->size, "src");
1.1 root 2584:
2585: printf ("\t\tif (src) {\n");
1.1.1.3 ! root 2586: if (using_ce020 == 2)
! 2587: printf ("\t\t\tregs.ce030_instr_cycles = table_falcon_cycles_DBcc[0];\n");
! 2588:
1.1 root 2589: if (using_exception_3) {
2590: printf ("\t\t\tif (offs & 1) {\n");
2591: printf ("\t\t\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + 2 + (uae_s32)offs + 2);\n");
2592: printf ("\t\t\t\tgoto %s;\n", endlabelstr);
2593: printf ("\t\t\t}\n");
2594: need_endlabel = 1;
2595: }
2596: irc2ir ();
2597: fill_prefetch_1 (2);
2598: returncycles ("\t\t\t", 12);
1.1.1.3 ! root 2599: if (using_ce || using_ce020 == 2)
1.1 root 2600: printf ("\t\t\treturn;\n");
2601: printf ("\t\t}\n");
1.1.1.3 ! root 2602: if (using_ce020 == 2)
! 2603: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_DBcc[1];\n");
1.1 root 2604: printf ("\t} else {\n");
1.1.1.3 ! root 2605: if (using_ce020 == 2)
! 2606: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_DBcc[2];\n");
! 2607:
1.1 root 2608: addcycles000_2 ("\t\t", 2);
2609: printf ("\t}\n");
2610: setpc ("oldpc + %d", m68k_pc_offset);
2611: m68k_pc_offset = 0;
2612: fill_prefetch_full ();
2613: insn_n_cycles = 12;
2614: need_endlabel = 1;
2615: break;
2616: case i_Scc:
2617: // confirmed
2618: genamode (curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, 0);
2619: start_brace ();
2620: fill_prefetch_next();
2621: start_brace ();
2622: printf ("\tint val = cctrue (%d) ? 0xff : 0;\n", curi->cc);
2623: if (using_ce) {
2624: printf ("\tint cycles = 0;\n");
2625: if (isreg (curi->smode))
2626: printf ("\tif (val) cycles += 2;\n");
2627: addcycles000_3 ("\t");
2628: }
2629: genastore ("val", curi->smode, "srcreg", curi->size, "src");
2630: break;
2631: case i_DIVU:
2632: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2633: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2634: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
2635: printf ("\tCLEAR_CZNV ();\n");
2636: printf ("\tif (src == 0) {\n");
2637: if (cpu_level > 0) {
2638: /* 68020 sets V when dividing by zero and N if dst is negative
2639: * 68000 clears both
2640: */
2641: printf("\t\tSET_VFLG (1);\n");
2642: printf("\t\tif (dst < 0) SET_NFLG (1);\n");
2643: }
2644: incpc ("%d", m68k_pc_offset);
2645: printf ("\t\tException (5, oldpc ,M68000_EXC_SRC_CPU);\n");
2646: printf ("\t\tgoto %s;\n", endlabelstr);
2647: printf ("\t} else {\n");
2648: printf ("\t\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
2649: printf ("\t\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
2650: fill_prefetch_next ();
2651: if (using_ce) {
2652: start_brace ();
2653: printf ("\t\tint cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src));\n");
2654: addcycles000_3 ("\t\t");
2655: }
2656: /* The N flag appears to be set each time there is an overflow.
2657: * Weird. but 68020 only sets N when dst is negative.. */
2658: printf ("\t\tif (newv > 0xffff) {\n");
2659: printf ("\t\t\tSET_VFLG (1);\n");
2660: #ifdef UNDEF68020
2661: if (cpu_level >= 2)
2662: printf ("\t\t\tif (currprefs.cpu_level == 0 || dst < 0) SET_NFLG (®s, 1);\n");
2663: else /* ??? some 68000 revisions may not set NFLG when overflow happens.. */
2664: #endif
2665: printf ("\t\t\tSET_NFLG (1);\n");
2666: printf ("\t\t} else {\n");
2667: printf ("\t\t"); genflags (flag_logical, sz_word, "newv", "", "");
2668: printf ("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
2669: printf ("\t\t"); genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2670: printf ("\t\t}\n");
2671: sync_m68k_pc ();
2672: printf ("\t}\n");
2673: count_ncycles++;
2674: insn_n_cycles += 136 - (136 - 76) / 2; /* average */
2675: need_endlabel = 1;
2676: break;
2677: case i_DIVS:
2678: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2679: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2680: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
2681: printf ("\tCLEAR_CZNV ();\n");
2682: printf ("\tif (src == 0) {\n");
2683: if (cpu_level > 0) {
2684: /* 68020 sets V when dividing by zero. Z is also set.
2685: * 68000 clears both
2686: */
2687: printf("\t\tSET_VFLG (1);\n");
2688: printf("\t\tSET_ZFLG (1);\n");
2689: }
2690: incpc ("%d", m68k_pc_offset);
2691: printf ("\t\tException (5, oldpc ,M68000_EXC_SRC_CPU);\n");
2692: printf ("\t\tgoto %s;\n", endlabelstr);
2693: printf ("\t} else {\n");
2694: printf ("\t\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
2695: printf ("\t\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
2696: fill_prefetch_next ();
2697: if (using_ce) {
2698: start_brace ();
2699: printf ("\t\tint cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src));\n");
2700: addcycles000_3 ("\t\t");
2701: }
2702: printf ("\t\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {\n");
2703: printf ("\t\t\tSET_VFLG (1);\n");
2704: #ifdef UNDEF68020
2705: if (cpu_level > 0)
2706: printf ("\t\t\tif (currprefs.cpu_level == 0) SET_NFLG (®s, 1);\n");
2707: else
2708: #endif
2709: printf ("\t\t\tSET_NFLG (1);\n");
2710: printf ("\t\t} else {\n");
2711: printf ("\t\t\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
2712: genflags (flag_logical, sz_word, "newv", "", "");
2713: printf ("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
2714: printf ("\t\t"); genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2715: printf ("\t\t}\n");
2716: sync_m68k_pc ();
2717: printf ("\t}\n");
2718: count_ncycles++;
2719: insn_n_cycles += 156 - (156 - 120) / 2; /* average */
2720: need_endlabel = 1;
2721: break;
2722: case i_MULU:
2723: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2724: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0, 0);
2725: fill_prefetch_next();
2726: start_brace ();
2727: printf ("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
2728: if (using_ce)
2729: printf ("\tint cycles = 38 - 4, bits;\n");
2730: genflags (flag_logical, sz_long, "newv", "", "");
2731: if (using_ce) {
2732: printf ("\tfor(bits = 0; bits < 16 && src; bits++, src >>= 1)\n");
2733: printf ("\t\tif (src & 1) cycles += 2;\n");
2734: addcycles000_3 ("\t");
2735: }
2736: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2737: sync_m68k_pc ();
2738: count_cycles += 38 - 4;
2739: count_ncycles++;
2740: insn_n_cycles += (70 - 38) / 2 + 38; /* average */
2741: break;
2742: case i_MULS:
2743: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2744: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0, 0);
2745: fill_prefetch_next();
2746: start_brace ();
2747: printf ("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
2748: if (using_ce) {
2749: printf ("\tint cycles = 38 - 4, bits;\n");
2750: printf ("\tuae_u32 usrc;\n");
2751: }
2752: genflags (flag_logical, sz_long, "newv", "", "");
2753: if (using_ce) {
2754: printf ("\tusrc = ((uae_u32)src) << 1;\n");
2755: printf ("\tfor(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)\n");
2756: printf ("\t\tif ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;\n");
2757: addcycles000_3 ("\t");
2758: }
2759: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2760: count_cycles += 38 - 4;
2761: count_ncycles++;
2762: insn_n_cycles += (70 - 38) / 2 + 38; /* average */
2763: break;
2764: case i_CHK:
2765: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2766: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2767: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2768: sync_m68k_pc ();
2769: addcycles000 (4);
2770: printf ("\tif (dst > src) {\n");
2771: printf ("\t\tSET_NFLG (0);\n");
2772: printf ("\t\tException (6, oldpc ,M68000_EXC_SRC_CPU);\n");
2773: printf ("\t\tgoto %s;\n", endlabelstr);
2774: printf ("\t}\n");
2775: addcycles000 (2);
2776: printf ("\tif ((uae_s32)dst < 0) {\n");
2777: printf ("\t\tSET_NFLG (1);\n");
2778: printf ("\t\tException (6, oldpc ,M68000_EXC_SRC_CPU);\n");
2779: printf ("\t\tgoto %s;\n", endlabelstr);
2780: printf ("\t}\n");
2781: fill_prefetch_next ();
2782: need_endlabel = 1;
2783: break;
2784: case i_CHK2:
2785: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2786: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
2787: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
2788: fill_prefetch_0 ();
2789: printf ("\t{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
2790: switch (curi->size) {
2791: case sz_byte:
2792: printf ("\tlower = (uae_s32)(uae_s8)%s (dsta); upper = (uae_s32)(uae_s8)%s (dsta + 1);\n", srcb, srcb);
2793: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
1.1.1.2 root 2794: if (using_ce020 == 2) {
2795: instr_table = TABLE_FALCON_CYCLES_CHK2_BW;
2796: instr_table_index = chk2_b_index * 2;
2797: chk2_b_index ++;
2798: }
1.1 root 2799: break;
2800: case sz_word:
2801: printf ("\tlower = (uae_s32)(uae_s16)%s (dsta); upper = (uae_s32)(uae_s16)%s (dsta + 2);\n", srcw, srcw);
2802: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
1.1.1.2 root 2803: if (using_ce020 == 2) {
2804: instr_table = TABLE_FALCON_CYCLES_CHK2_BW;
2805: instr_table_index = chk2_w_index * 2;
2806: chk2_w_index ++;
2807: }
1.1 root 2808: break;
2809: case sz_long:
2810: printf ("\tlower = %s (dsta); upper = %s (dsta + 4);\n", srcl, srcl);
1.1.1.2 root 2811: if (using_ce020 == 2) {
2812: instr_table = TABLE_FALCON_CYCLES_CHK2_L;
2813: instr_table_index = chk2_l_index * 2;
2814: chk2_l_index ++;
2815: }
1.1 root 2816: break;
2817: default:
2818: abort ();
2819: }
2820: printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
2821: printf ("\tSET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1.1.1.2 root 2822: printf ("\tif ((extra & 0x800) && GET_CFLG ()) {\n");
2823: printf ("\t\tException (6, oldpc ,M68000_EXC_SRC_CPU);\n");
2824: instr_table_index ++; /* take the Exception cycle value in the CHK2 table */
2825: returncycles ("\t", 0);
2826: printf ("\t}\n}\n");
2827: instr_table_index --; /* take the No Exception cycle value in the CHK2 table */
1.1 root 2828: break;
2829:
2830: case i_ASR:
2831: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2832: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2833: fill_prefetch_next();
2834: start_brace ();
2835: switch (curi->size) {
2836: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2837: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2838: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2839: default: abort ();
2840: }
2841: printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
2842: printf ("\tint ccnt = cnt & 63;\n");
2843: printf ("\tcnt &= 63;\n");
2844: printf ("\tCLEAR_CZNV ();\n");
2845: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2846: printf ("\t\tval = %s & (uae_u32)-sign;\n", bit_mask (curi->size));
2847: printf ("\t\tSET_CFLG (sign);\n");
2848: duplicate_carry (1);
2849: if (source_is_imm1_8 (curi))
2850: printf ("\t} else {\n");
1.1.1.3 ! root 2851: else {
! 2852: if (using_ce020 == 2){
! 2853: no_return_cycles = true;
! 2854: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_ASR[1];\n");
! 2855: }
1.1 root 2856: printf ("\t} else if (cnt > 0) {\n");
1.1.1.3 ! root 2857: if (using_ce020 == 2)
! 2858: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_ASR[0];\n");
! 2859: }
1.1 root 2860: printf ("\t\tval >>= cnt - 1;\n");
2861: printf ("\t\tSET_CFLG (val & 1);\n");
2862: duplicate_carry (1);
2863: printf ("\t\tval >>= 1;\n");
2864: printf ("\t\tval |= (%s << (%d - cnt)) & (uae_u32)-sign;\n",
2865: bit_mask (curi->size),
2866: bit_size (curi->size));
2867: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
2868: printf ("\t}\n");
2869: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2870: shift_ce (curi->dmode, curi->size);
2871: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2872: break;
2873: case i_ASL:
2874: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2875: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2876: fill_prefetch_next();
2877: start_brace ();
2878: switch (curi->size) {
2879: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2880: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2881: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2882: default: abort ();
2883: }
2884: printf ("\tint ccnt = cnt & 63;\n");
2885: printf ("\tcnt &= 63;\n");
2886: printf ("\tCLEAR_CZNV ();\n");
2887: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2888: printf ("\t\tSET_VFLG (val != 0);\n");
2889: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
2890: bit_size (curi->size));
2891: duplicate_carry (1);
2892: printf ("\t\tval = 0;\n");
2893: if (source_is_imm1_8 (curi))
2894: printf ("\t} else {\n");
2895: else
2896: printf ("\t} else if (cnt > 0) {\n");
2897: printf ("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
2898: bit_mask (curi->size),
2899: bit_size (curi->size) - 1,
2900: bit_mask (curi->size));
2901: printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
2902: printf ("\t\tval <<= cnt - 1;\n");
2903: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
2904: duplicate_carry (1);
2905: printf ("\t\tval <<= 1;\n");
2906: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
2907: printf ("\t}\n");
2908: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2909: shift_ce (curi->dmode, curi->size);
2910: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2911: break;
2912: case i_LSR:
2913: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2914: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2915: fill_prefetch_next();
2916: start_brace ();
2917: switch (curi->size) {
2918: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2919: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2920: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2921: default: abort ();
2922: }
2923: printf ("\tint ccnt = cnt & 63;\n");
2924: printf ("\tcnt &= 63;\n");
2925: printf ("\tCLEAR_CZNV ();\n");
2926: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2927: printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
2928: bit_size (curi->size), bit_size (curi->size) - 1);
2929: duplicate_carry (1);
2930: printf ("\t\tval = 0;\n");
2931: if (source_is_imm1_8 (curi))
2932: printf ("\t} else {\n");
1.1.1.3 ! root 2933: else {
! 2934: if (using_ce020 == 2){
! 2935: no_return_cycles = true;
! 2936: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_LSD[1];\n");
! 2937: }
1.1 root 2938: printf ("\t} else if (cnt > 0) {\n");
1.1.1.3 ! root 2939: if (using_ce020 == 2)
! 2940: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_LSD[0];\n");
! 2941: }
1.1 root 2942: printf ("\t\tval >>= cnt - 1;\n");
2943: printf ("\t\tSET_CFLG (val & 1);\n");
2944: duplicate_carry (1);
2945: printf ("\t\tval >>= 1;\n");
2946: printf ("\t}\n");
2947: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2948: shift_ce (curi->dmode, curi->size);
2949: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2950: break;
2951: case i_LSL:
2952: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2953: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2954: fill_prefetch_next();
2955: start_brace ();
2956: switch (curi->size) {
2957: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2958: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2959: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2960: default: abort ();
2961: }
2962: printf ("\tint ccnt = cnt & 63;\n");
2963: printf ("\tcnt &= 63;\n");
2964: printf ("\tCLEAR_CZNV ();\n");
2965: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2966: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n", bit_size (curi->size));
2967: duplicate_carry (1);
2968: printf ("\t\tval = 0;\n");
2969: if (source_is_imm1_8 (curi))
2970: printf ("\t} else {\n");
1.1.1.3 ! root 2971: else {
! 2972: if (using_ce020 == 2){
! 2973: no_return_cycles = true;
! 2974: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_LSD[1];\n");
! 2975: }
1.1 root 2976: printf ("\t} else if (cnt > 0) {\n");
1.1.1.3 ! root 2977: if (using_ce020 == 2)
! 2978: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_LSD[0];\n");
! 2979: }
1.1 root 2980: printf ("\t\tval <<= (cnt - 1);\n");
2981: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
2982: duplicate_carry (1);
2983: printf ("\t\tval <<= 1;\n");
2984: printf ("\tval &= %s;\n", bit_mask (curi->size));
2985: printf ("\t}\n");
2986: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2987: shift_ce (curi->dmode, curi->size);
2988: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2989: break;
2990: case i_ROL:
2991: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2992: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2993: fill_prefetch_next ();
2994: start_brace ();
2995: switch (curi->size) {
2996: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2997: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2998: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2999: default: abort ();
3000: }
3001: printf ("\tint ccnt = cnt & 63;\n");
3002: printf ("\tcnt &= 63;\n");
3003: printf ("\tCLEAR_CZNV ();\n");
3004: if (source_is_imm1_8 (curi))
3005: printf ("{");
3006: else
3007: printf ("\tif (cnt > 0) {\n");
3008: printf ("\tuae_u32 loval;\n");
3009: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
3010: printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
3011: printf ("\tval <<= cnt;\n");
3012: printf ("\tval |= loval;\n");
3013: printf ("\tval &= %s;\n", bit_mask (curi->size));
3014: printf ("\tSET_CFLG (val & 1);\n");
3015: printf ("}\n");
3016: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3017: shift_ce (curi->dmode, curi->size);
3018: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3019: break;
3020: case i_ROR:
3021: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3022: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3023: fill_prefetch_next ();
3024: start_brace ();
3025: switch (curi->size) {
3026: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3027: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3028: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3029: default: abort ();
3030: }
3031: printf ("\tint ccnt = cnt & 63;\n");
3032: printf ("\tcnt &= 63;\n");
3033: printf ("\tCLEAR_CZNV ();\n");
3034: if (source_is_imm1_8 (curi))
3035: printf ("{");
3036: else
3037: printf ("\tif (cnt > 0) {");
3038: printf ("\tuae_u32 hival;\n");
3039: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
3040: printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
3041: printf ("\tval >>= cnt;\n");
3042: printf ("\tval |= hival;\n");
3043: printf ("\tval &= %s;\n", bit_mask (curi->size));
3044: printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
3045: printf ("\t}\n");
3046: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3047: shift_ce (curi->dmode, curi->size);
3048: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3049: break;
3050: case i_ROXL:
3051: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3052: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3053: fill_prefetch_next ();
3054: start_brace ();
3055: switch (curi->size) {
3056: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3057: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3058: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3059: default: abort ();
3060: }
3061: printf ("\tint ccnt = cnt & 63;\n");
3062: printf ("\tcnt &= 63;\n");
3063: printf ("\tCLEAR_CZNV ();\n");
3064: if (source_is_imm1_8 (curi))
3065: printf ("{");
3066: else {
3067: force_range_for_rox ("cnt", curi->size);
3068: printf ("\tif (cnt > 0) {\n");
3069: }
3070: printf ("\tcnt--;\n");
3071: printf ("\t{\n\tuae_u32 carry;\n");
3072: printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
3073: printf ("\tcarry = loval & 1;\n");
3074: printf ("\tval = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);\n");
3075: printf ("\tSET_XFLG (carry);\n");
3076: printf ("\tval &= %s;\n", bit_mask (curi->size));
3077: printf ("\t} }\n");
3078: printf ("\tSET_CFLG (GET_XFLG ());\n");
3079: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3080: shift_ce (curi->dmode, curi->size);
3081: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3082: break;
3083: case i_ROXR:
3084: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3085: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3086: fill_prefetch_next ();
3087: start_brace ();
3088: switch (curi->size) {
3089: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3090: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3091: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3092: default: abort ();
3093: }
3094: printf ("\tint ccnt = cnt & 63;\n");
3095: printf ("\tcnt &= 63;\n");
3096: printf ("\tCLEAR_CZNV ();\n");
3097: if (source_is_imm1_8 (curi))
3098: printf ("{");
3099: else {
3100: force_range_for_rox ("cnt", curi->size);
3101: printf ("\tif (cnt > 0) {\n");
3102: }
3103: printf ("\tcnt--;\n");
3104: printf ("\t{\n\tuae_u32 carry;\n");
3105: printf ("\tuae_u32 hival = (val << 1) | GET_XFLG ();\n");
3106: printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
3107: printf ("\tval >>= cnt;\n");
3108: printf ("\tcarry = val & 1;\n");
3109: printf ("\tval >>= 1;\n");
3110: printf ("\tval |= hival;\n");
3111: printf ("\tSET_XFLG (carry);\n");
3112: printf ("\tval &= %s;\n", bit_mask (curi->size));
3113: printf ("\t} }\n");
3114: printf ("\tSET_CFLG (GET_XFLG ());\n");
3115: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3116: shift_ce (curi->dmode, curi->size);
3117: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3118: break;
3119: case i_ASRW:
3120: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3121: fill_prefetch_next ();
3122: start_brace ();
3123: switch (curi->size) {
3124: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3125: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3126: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3127: default: abort ();
3128: }
3129: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
3130: printf ("\tuae_u32 cflg = val & 1;\n");
3131: printf ("\tval = (val >> 1) | sign;\n");
3132: genflags (flag_logical, curi->size, "val", "", "");
3133: printf ("\tSET_CFLG (cflg);\n");
3134: duplicate_carry (0);
3135: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3136: break;
3137: case i_ASLW:
3138: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3139: fill_prefetch_next ();
3140: start_brace ();
3141: switch (curi->size) {
3142: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3143: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3144: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3145: default: abort ();
3146: }
3147: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
3148: printf ("\tuae_u32 sign2;\n");
3149: printf ("\tval <<= 1;\n");
3150: genflags (flag_logical, curi->size, "val", "", "");
3151: printf ("\tsign2 = %s & val;\n", cmask (curi->size));
3152: printf ("\tSET_CFLG (sign != 0);\n");
3153: duplicate_carry (0);
3154:
3155: printf ("\tSET_VFLG (GET_VFLG () | (sign2 != sign));\n");
3156: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3157: break;
3158: case i_LSRW:
3159: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3160: fill_prefetch_next ();
3161: start_brace ();
3162: switch (curi->size) {
3163: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3164: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3165: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3166: default: abort ();
3167: }
3168: printf ("\tuae_u32 carry = val & 1;\n");
3169: printf ("\tval >>= 1;\n");
3170: genflags (flag_logical, curi->size, "val", "", "");
3171: printf ("\tSET_CFLG (carry);\n");
3172: duplicate_carry (0);
3173: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3174: break;
3175: case i_LSLW:
3176: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3177: fill_prefetch_next ();
3178: start_brace ();
3179: switch (curi->size) {
3180: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3181: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3182: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3183: default: abort ();
3184: }
3185: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
3186: printf ("\tval <<= 1;\n");
3187: genflags (flag_logical, curi->size, "val", "", "");
3188: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
3189: duplicate_carry (0);
3190: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3191: break;
3192: case i_ROLW:
3193: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3194: fill_prefetch_next ();
3195: start_brace ();
3196: switch (curi->size) {
3197: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3198: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3199: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3200: default: abort ();
3201: }
3202: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
3203: printf ("\tval <<= 1;\n");
3204: printf ("\tif (carry) val |= 1;\n");
3205: genflags (flag_logical, curi->size, "val", "", "");
3206: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
3207: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3208: break;
3209: case i_RORW:
3210: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3211: fill_prefetch_next ();
3212: start_brace ();
3213: switch (curi->size) {
3214: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3215: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3216: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3217: default: abort ();
3218: }
3219: printf ("\tuae_u32 carry = val & 1;\n");
3220: printf ("\tval >>= 1;\n");
3221: printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
3222: genflags (flag_logical, curi->size, "val", "", "");
3223: printf ("\tSET_CFLG (carry);\n");
3224: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3225: break;
3226: case i_ROXLW:
3227: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3228: fill_prefetch_next ();
3229: start_brace ();
3230: switch (curi->size) {
3231: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3232: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3233: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3234: default: abort ();
3235: }
3236: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
3237: printf ("\tval <<= 1;\n");
3238: printf ("\tif (GET_XFLG ()) val |= 1;\n");
3239: genflags (flag_logical, curi->size, "val", "", "");
3240: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
3241: duplicate_carry (0);
3242: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3243: break;
3244: case i_ROXRW:
3245: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3246: fill_prefetch_next ();
3247: start_brace ();
3248: switch (curi->size) {
3249: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3250: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3251: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3252: default: abort ();
3253: }
3254: printf ("\tuae_u32 carry = val & 1;\n");
3255: printf ("\tval >>= 1;\n");
3256: printf ("\tif (GET_XFLG ()) val |= %s;\n", cmask (curi->size));
3257: genflags (flag_logical, curi->size, "val", "", "");
3258: printf ("\tSET_CFLG (carry);\n");
3259: duplicate_carry (0);
3260: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3261: break;
3262: case i_MOVEC2:
3263: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3264: fill_prefetch_next ();
3265: start_brace ();
3266: printf ("\tint regno = (src >> 12) & 15;\n");
3267: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
3268: printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
3269: break;
3270: case i_MOVE2C:
3271: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3272: fill_prefetch_next ();
3273: start_brace ();
3274: printf ("\tint regno = (src >> 12) & 15;\n");
3275: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
3276: printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
1.1.1.3 ! root 3277: if (using_ce020 == 2) {
! 3278: no_return_cycles = true;
! 3279: printf ("\tif((src & 0xFFF) < 3)\n");
! 3280: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_MOVEC[1];\n");
! 3281: printf ("\telse\n");
! 3282: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_MOVEC[0];\n");
! 3283: }
1.1 root 3284: break;
3285: case i_CAS:
3286: {
1.1.1.2 root 3287: if (using_ce020 == 2) {
3288: no_return_cycles = true;
3289: if (curi->size == sz_byte) {
3290: instr_table = TABLE_FALCON_CYCLES_CAS_BW;
3291: instr_table_index = cas_b_index * 2;
3292: cas_b_index ++;
3293: }
3294: else if (curi->size == sz_word) {
3295: instr_table = TABLE_FALCON_CYCLES_CAS_BW;
3296: instr_table_index = cas_w_index * 2;
3297: cas_w_index ++;
3298: }
3299: else {
3300: instr_table = TABLE_FALCON_CYCLES_CAS_L;
3301: instr_table_index = cas_l_index * 2;
3302: cas_l_index ++;
3303: }
3304: }
1.1 root 3305: int old_brace_level;
3306: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3307: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3308: fill_prefetch_0 ();
3309: start_brace ();
3310: printf ("\tint ru = (src >> 6) & 7;\n");
3311: printf ("\tint rc = src & 7;\n");
3312: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, rc)", "dst");
3313: printf ("\tif (GET_ZFLG ())");
3314: old_brace_level = n_braces;
3315: start_brace ();
3316: genastore ("(m68k_dreg (regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
1.1.1.2 root 3317: if (using_ce020 == 2)
3318: printf ("\tregs.ce030_instr_cycles = %s[%d];\n", falcon_cycles_tables[instr_table], instr_table_index);
1.1 root 3319: pop_braces (old_brace_level);
3320: printf ("else");
3321: start_brace ();
3322: printf ("m68k_dreg (regs, rc) = dst;\n");
1.1.1.2 root 3323: if (using_ce020 == 2)
3324: printf ("\tregs.ce030_instr_cycles = %s[%d];\n", falcon_cycles_tables[instr_table], instr_table_index + 1);
1.1 root 3325: pop_braces (old_brace_level);
3326: }
3327: break;
3328: case i_CAS2:
3329: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3330: printf ("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
3331: printf ("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
3332: if (curi->size == sz_word) {
3333: int old_brace_level = n_braces;
3334: printf ("\tuae_u16 dst1 = %s (rn1), dst2 = %s (rn2);\n", srcw, srcw);
3335: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, (extra >> 16) & 7)", "dst1");
3336: printf ("\tif (GET_ZFLG ()) {\n");
3337: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, extra & 7)", "dst2");
3338: printf ("\tif (GET_ZFLG ()) {\n");
3339: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 22) & 7));\n", dstw);
3340: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 6) & 7));\n", dstw);
3341: printf ("\t}}\n");
3342: pop_braces (old_brace_level);
3343: printf ("\tif (! GET_ZFLG ()) {\n");
3344: printf ("\tm68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
3345: printf ("\tm68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
3346: printf ("\t}\n");
3347: } else {
3348: int old_brace_level = n_braces;
3349: printf ("\tuae_u32 dst1 = %s (rn1), dst2 = %s (rn2);\n", srcl, srcl);
3350: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, (extra >> 16) & 7)", "dst1");
3351: printf ("\tif (GET_ZFLG ()) {\n");
3352: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, extra & 7)", "dst2");
3353: printf ("\tif (GET_ZFLG ()) {\n");
3354: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 22) & 7));\n", dstl);
3355: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 6) & 7));\n", dstl);
3356: printf ("\t}}\n");
3357: pop_braces (old_brace_level);
3358: printf ("\tif (! GET_ZFLG ()) {\n");
3359: printf ("\tm68k_dreg (regs, (extra >> 22) & 7) = dst1;\n");
3360: printf ("\tm68k_dreg (regs, (extra >> 6) & 7) = dst2;\n");
3361: printf ("\t}\n");
3362: }
3363: break;
3364: case i_MOVES: /* ignore DFC and SFC when using_mmu == false */
3365: {
3366: int old_brace_level;
3367: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3368: printf ("\tif (extra & 0x800)\n");
3369: {
3370: int old_m68k_pc_offset = m68k_pc_offset;
3371: old_brace_level = n_braces;
3372: start_brace ();
3373: printf ("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
3374: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
3375: genastore_fc ("src", curi->dmode, "dstreg", curi->size, "dst");
3376: pop_braces (old_brace_level);
3377: m68k_pc_offset = old_m68k_pc_offset;
3378: }
3379: printf ("else");
3380: {
3381: start_brace ();
3382: genamode (curi->dmode, "dstreg", curi->size, "src", 1, 0, GF_FC);
3383: printf ("\tif (extra & 0x8000) {\n");
3384: switch (curi->size) {
3385: case sz_byte: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
3386: case sz_word: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
3387: case sz_long: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = src;\n"); break;
3388: default: abort ();
3389: }
3390: printf ("\t} else {\n");
3391: genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
3392: printf ("\t}\n");
3393: sync_m68k_pc ();
3394: pop_braces (old_brace_level);
3395: }
3396: }
3397: break;
3398: case i_BKPT: /* only needed for hardware emulators */
3399: sync_m68k_pc ();
3400: printf ("\top_illg (opcode);\n");
3401: break;
3402: case i_CALLM: /* not present in 68030 */
3403: sync_m68k_pc ();
3404: printf ("\top_illg (opcode);\n");
3405: break;
3406: case i_RTM: /* not present in 68030 */
3407: sync_m68k_pc ();
3408: printf ("\top_illg (opcode);\n");
3409: break;
3410: case i_TRAPcc:
3411: if (curi->smode != am_unknown && curi->smode != am_illg)
3412: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
3413: fill_prefetch_0 ();
3414: printf ("\tif (cctrue (%d)) { Exception (7, m68k_getpc () ,M68000_EXC_SRC_CPU); goto %s; }\n", curi->cc, endlabelstr);
3415: need_endlabel = 1;
3416: break;
3417: case i_DIVL:
3418: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
3419: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3420: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3421: sync_m68k_pc ();
3422: printf ("\tm68k_divl(opcode, dst, extra, oldpc);\n");
1.1.1.3 ! root 3423: if (using_ce020 == 2) {
! 3424: no_return_cycles = true;
! 3425: printf ("\tif (extra & 0x800)\n");
! 3426: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_DIVS_L[%d];\n", divl_index);
! 3427: printf ("\telse\n");
! 3428: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_DIVU_L[%d];\n", divl_index);
! 3429: divl_index ++;
! 3430: }
1.1 root 3431: break;
3432: case i_MULL:
3433: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3434: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3435: sync_m68k_pc ();
3436: printf ("\tm68k_mull(opcode, dst, extra);\n");
3437: break;
3438: case i_BFTST:
3439: case i_BFEXTU:
3440: case i_BFCHG:
3441: case i_BFEXTS:
3442: case i_BFCLR:
3443: case i_BFFFO:
3444: case i_BFSET:
3445: case i_BFINS:
3446: {
3447: const char *getb, *putb;
3448:
3449: if (using_mmu || using_ce020) {
3450: getb = "x_get_bitfield";
3451: putb = "x_put_bitfield";
3452: } else {
3453: getb = "get_bitfield";
3454: putb = "put_bitfield";
3455: }
3456:
3457: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3458: genamode (curi->dmode, "dstreg", sz_long, "dst", 2, 0, 0);
3459: start_brace ();
3460: printf ("\tuae_u32 bdata[2];\n");
3461: printf ("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
3462: printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
3463: if (curi->dmode == Dreg) {
3464: printf ("\tuae_u32 tmp = m68k_dreg(regs, dstreg);\n");
3465: printf ("\toffset &= 0x1f;\n");
3466: printf ("\ttmp = (tmp << offset) | (tmp >> (32 - offset));\n");
3467: printf ("\tbdata[0] = tmp & ((1 << (32 - width)) - 1);\n");
3468: } else {
3469: printf ("\tuae_u32 tmp;\n");
3470: printf ("\tdsta += offset >> 3;\n");
3471: printf ("\ttmp = %s (dsta, bdata, offset, width);\n", getb);
3472: }
3473: printf ("\tSET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);\n");
3474: if (curi->mnemo == i_BFEXTS)
3475: printf ("\ttmp = (uae_s32)tmp >> (32 - width);\n");
3476: else
3477: printf ("\ttmp >>= (32 - width);\n");
3478: printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
3479: switch (curi->mnemo) {
3480: case i_BFTST:
3481: break;
3482: case i_BFEXTU:
3483: case i_BFEXTS:
3484: printf ("\tm68k_dreg (regs, (extra >> 12) & 7) = tmp;\n");
3485: break;
3486: case i_BFCHG:
3487: printf ("\ttmp = tmp ^ (0xffffffffu >> (32 - width));\n");
3488: break;
3489: case i_BFCLR:
3490: printf ("\ttmp = 0;\n");
3491: break;
3492: case i_BFFFO:
3493: printf ("\t{ uae_u32 mask = 1 << (width - 1);\n");
3494: printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n");
3495: printf ("\tm68k_dreg (regs, (extra >> 12) & 7) = offset;\n");
3496: break;
3497: case i_BFSET:
3498: printf ("\ttmp = 0xffffffffu >> (32 - width);\n");
3499: break;
3500: case i_BFINS:
3501: printf ("\ttmp = m68k_dreg (regs, (extra >> 12) & 7);\n");
3502: printf ("\ttmp = tmp & (0xffffffffu >> (32 - width));\n");
3503: printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
3504: printf ("\tSET_ZFLG (tmp == 0);\n");
3505: break;
3506: default:
3507: break;
3508: }
3509: if (curi->mnemo == i_BFCHG
3510: || curi->mnemo == i_BFCLR
3511: || curi->mnemo == i_BFSET
3512: || curi->mnemo == i_BFINS) {
3513: if (curi->dmode == Dreg) {
3514: printf ("\ttmp = bdata[0] | (tmp << (32 - width));\n");
3515: printf ("\tm68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));\n");
3516: } else {
3517: printf ("\t%s(dsta, bdata, tmp, offset, width);\n", putb);
3518: }
3519: }
3520: }
3521: break;
3522: case i_PACK:
3523: if (curi->smode == Dreg) {
3524: printf ("\tuae_u16 val = m68k_dreg (regs, srcreg) + %s;\n", gen_nextiword (0));
3525: printf ("\tm68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
3526: } else {
3527: printf ("\tuae_u16 val;\n");
3528: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
3529: printf ("\tval = (uae_u16)%s (m68k_areg (regs, srcreg));\n", srcb);
3530: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
3531: printf ("\tval = (val | ((uae_u16)%s (m68k_areg (regs, srcreg)) << 8)) + %s;\n", srcb, gen_nextiword (0));
3532: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
3533: gen_set_fault_pc ();
3534: printf ("\t%s (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n", dstb);
3535: }
3536: break;
3537: case i_UNPK:
3538: if (curi->smode == Dreg) {
3539: printf ("\tuae_u16 val = m68k_dreg (regs, srcreg);\n");
3540: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
3541: printf ("\tm68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
3542: } else {
3543: printf ("\tuae_u16 val;\n");
3544: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
3545: printf ("\tval = (uae_u16)%s (m68k_areg (regs, srcreg));\n", srcb);
3546: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
3547: if (cpu_level >= 2) {
3548: printf ("\tm68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];\n");
3549: printf ("\t%s (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);\n", dstb);
3550: printf ("\t%s (m68k_areg (regs, dstreg), val >> 8);\n", dstb);
3551: } else {
3552: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
3553: printf ("\t%s (m68k_areg (regs, dstreg),val);\n", dstb);
3554: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
3555: gen_set_fault_pc ();
3556: printf ("\t%s (m68k_areg (regs, dstreg),val >> 8);\n", dstb);
3557: }
3558: }
3559: break;
3560: case i_TAS:
3561: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3562: genflags (flag_logical, curi->size, "src", "", "");
3563: if (!isreg (curi->smode))
3564: addcycles000 (2);
3565: fill_prefetch_next ();
3566: printf ("\tsrc |= 0x80;\n");
3567: if (cpu_level >= 2 || curi->smode == Dreg || !using_ce) {
3568: if (next_cpu_level < 2)
3569: next_cpu_level = 2 - 1;
3570: genastore ("src", curi->smode, "srcreg", curi->size, "src");
3571: } else {
3572: printf ("\tif (!is_cycle_ce ()) {\n");
3573: genastore ("src", curi->smode, "srcreg", curi->size, "src");
3574: printf ("\t} else {\n");
3575: printf ("\t\tdo_cycles_ce000 (4);\n");
3576: printf ("\t}\n");
3577: }
3578: break;
3579: case i_FPP:
3580: fpulimit();
3581: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3582: sync_m68k_pc ();
3583: printf ("\tfpuop_arithmetic(opcode, extra);\n");
3584: break;
3585: case i_FDBcc:
3586: fpulimit();
3587: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3588: sync_m68k_pc ();
3589: printf ("\tfpuop_dbcc (opcode, extra);\n");
3590: break;
3591: case i_FScc:
3592: fpulimit();
3593: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3594: sync_m68k_pc ();
3595: printf ("\tfpuop_scc (opcode, extra);\n");
3596: break;
3597: case i_FTRAPcc:
3598: fpulimit();
3599: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
3600: printf ("\tuae_u16 extra = %s;\n", gen_nextiword (0));
3601: if (curi->smode != am_unknown && curi->smode != am_illg)
3602: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
3603: sync_m68k_pc ();
3604: printf ("\tfpuop_trapcc (opcode, oldpc, extra);\n");
3605: break;
3606: case i_FBcc:
3607: fpulimit();
3608: sync_m68k_pc ();
3609: start_brace ();
3610: printf ("\tuaecptr pc = m68k_getpc ();\n");
3611: genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0, 0);
3612: sync_m68k_pc ();
3613: printf ("\tfpuop_bcc (opcode, pc,extra);\n");
3614: break;
3615: case i_FSAVE:
3616: fpulimit();
3617: sync_m68k_pc ();
3618: printf ("\tfpuop_save (opcode);\n");
3619: break;
3620: case i_FRESTORE:
3621: fpulimit();
3622: sync_m68k_pc ();
3623: printf ("\tfpuop_restore (opcode);\n");
3624: break;
3625:
3626: case i_CINVL:
3627: case i_CINVP:
3628: case i_CINVA:
3629: case i_CPUSHL:
3630: case i_CPUSHP:
3631: case i_CPUSHA:
3632: if (using_mmu)
3633: printf ("\tflush_mmu(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);\n");
3634: printf ("\tif (opcode & 0x80)\n");
3635: printf ("\t\tflush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);\n");
3636: break;
3637:
3638: case i_MOVE16:
3639: {
3640: if ((opcode & 0xfff8) == 0xf620) {
3641: /* MOVE16 (Ax)+,(Ay)+ */
3642: printf ("\tuae_u32 v1, v2, v3, v4;\n");
3643: printf ("\tuaecptr mems = m68k_areg (regs, srcreg) & ~15, memd;\n");
3644: printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword (0));
3645: printf ("\tmemd = m68k_areg (regs, dstreg) & ~15;\n");
3646: printf ("\tv1 = %s (mems);\n", srcl);
3647: printf ("\tv2 = %s (mems + 4);\n", srcl);
3648: printf ("\tv3 = %s (mems + 8);\n", srcl);
3649: printf ("\tv4 = %s (mems + 12);\n", srcl);
3650: printf ("\t%s (memd , v1);\n", dstl);
3651: printf ("\t%s (memd + 4, v2);\n", dstl);
3652: printf ("\t%s (memd + 8, v3);\n", dstl);
3653: printf ("\t%s (memd + 12, v4);\n", dstl);
3654: printf ("\tif (srcreg != dstreg)\n");
3655: printf ("\t\tm68k_areg (regs, srcreg) += 16;\n");
3656: printf ("\tm68k_areg (regs, dstreg) += 16;\n");
3657: } else {
3658: /* Other variants */
3659: printf ("\tuae_u32 v1, v2, v3, v4;\n");
3660: genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2, 0);
3661: genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2, 0);
3662: printf ("\tmemsa &= ~15;\n");
3663: printf ("\tmemda &= ~15;\n");
3664: printf ("\tv1 = %s (memsa);\n", srcl);
3665: printf ("\tv2 = %s (memsa + 4);\n", srcl);
3666: printf ("\tv3 = %s (memsa + 8);\n", srcl);
3667: printf ("\tv4 = %s (memsa + 12);\n", srcl);
3668: printf ("\t%s (memda , v1);\n", dstl);
3669: printf ("\t%s (memda + 4, v2);\n", dstl);
3670: printf ("\t%s (memda + 8, v3);\n", dstl);
3671: printf ("\t%s (memda + 12, v4);\n", dstl);
3672: if ((opcode & 0xfff8) == 0xf600)
3673: printf ("\tm68k_areg (regs, srcreg) += 16;\n");
3674: else if ((opcode & 0xfff8) == 0xf608)
3675: printf ("\tm68k_areg (regs, dstreg) += 16;\n");
3676: }
3677: }
3678: break;
3679:
3680: case i_PFLUSHN:
3681: case i_PFLUSH:
3682: case i_PFLUSHAN:
3683: case i_PFLUSHA:
3684: case i_PLPAR:
3685: case i_PLPAW:
3686: case i_PTESTR:
3687: case i_PTESTW:
3688: sync_m68k_pc ();
3689: printf ("\tmmu_op (opcode, 0);\n");
3690: break;
3691: case i_MMUOP030:
3692: printf ("\tuaecptr pc = m68k_getpc ();\n");
3693: printf ("\tuae_u16 extra = x_get_word (pc + 2);\n");
3694: m68k_pc_offset += 2;
3695: sync_m68k_pc ();
3696: if (curi->smode == Areg || curi->smode == Dreg)
3697: printf("\tuae_u16 extraa = 0;\n");
3698: else
3699: genamode (curi->smode, "srcreg", curi->size, "extra", 0, 0, 0);
3700: sync_m68k_pc ();
3701: printf ("\tmmu_op30 (pc, opcode, extra, extraa);\n");
3702: break;
3703: default:
3704: abort ();
3705: break;
3706: }
3707: finish_braces ();
3708: if (limit_braces) {
3709: printf ("\n#endif\n");
3710: n_braces = limit_braces;
3711: limit_braces = 0;
3712: finish_braces ();
3713: }
3714: if (did_prefetch >= 0)
3715: fill_prefetch_finish ();
3716: if (!count_cycles)
1.1.1.2 root 3717: addcycles_ce020 (0, 0, 2, 2);
1.1 root 3718: sync_m68k_pc ();
3719: did_prefetch = 0;
3720: }
3721:
3722: static void generate_includes (FILE * f)
3723: {
1.1.1.2 root 3724: /* fprintf (f, "#include \"sysconfig.h\"\n");
1.1 root 3725: fprintf (f, "#include \"sysdeps.h\"\n");
3726: fprintf (f, "#include \"options_cpu.h\"\n");
3727: fprintf (f, "#include \"memory.h\"\n");
3728: fprintf (f, "#include \"custom.h\"\n");
3729: fprintf (f, "#include \"events.h\"\n");
3730: fprintf (f, "#include \"newcpu.h\"\n");
3731: fprintf (f, "#include \"cpu_prefetch.h\"\n");
3732: fprintf (f, "#include \"cputbl.h\"\n");
3733: fprintf (f, "#include \"main.h\"\n");
3734: fprintf (f, "#include \"cpummu.h\"\n");
1.1.1.2 root 3735: */
3736: fprintf (f, "#include \"sysdeps.h\"\n");
3737: fprintf (f, "#include \"hatari-glue.h\"\n");
3738: fprintf (f, "#include \"maccess.h\"\n");
3739: fprintf (f, "#include \"memory.h\"\n");
3740: fprintf (f, "#include \"custom.h\"\n");
3741: fprintf (f, "#include \"newcpu.h\"\n");
3742: fprintf (f, "#include \"cpu_prefetch.h\"\n");
3743: fprintf (f, "#include \"cputbl.h\"\n");
3744: fprintf (f, "#include \"main.h\"\n");
3745: fprintf (f, "#include \"cpummu.h\"\n");
1.1 root 3746:
3747: fprintf (f, "#define CPUFUNC(x) x##_ff\n"
3748: "#define SET_CFLG_ALWAYS(x) SET_CFLG(x)\n"
3749: "#define SET_NFLG_ALWAYS(x) SET_NFLG(x)\n"
3750: "#ifdef NOFLAGS\n"
3751: "#include \"noflags.h\"\n"
3752: "#endif\n");
3753: }
3754:
3755: static int postfix;
3756:
3757:
3758: static char *decodeEA (amodes mode, wordsizes size)
3759: {
3760: static char buffer[80];
3761:
3762: buffer[0] = 0;
3763: switch (mode){
3764: case Dreg:
3765: strcpy (buffer,"Dn");
3766: break;
3767: case Areg:
3768: strcpy (buffer,"An");
3769: break;
3770: case Aind:
3771: strcpy (buffer,"(An)");
3772: break;
3773: case Aipi:
3774: strcpy (buffer,"(An)+");
3775: break;
3776: case Apdi:
3777: strcpy (buffer,"-(An)");
3778: break;
3779: case Ad16:
3780: strcpy (buffer,"(d16,An)");
3781: break;
3782: case Ad8r:
3783: strcpy (buffer,"(d8,An,Xn)");
3784: break;
3785: case PC16:
3786: strcpy (buffer,"(d16,PC)");
3787: break;
3788: case PC8r:
3789: strcpy (buffer,"(d8,PC,Xn)");
3790: break;
3791: case absw:
3792: strcpy (buffer,"(xxx).W");
3793: break;
3794: case absl:
3795: strcpy (buffer,"(xxx).L");
3796: break;
3797: case imm:
3798: switch (size){
3799: case sz_byte:
3800: strcpy (buffer,"#<data>.B");
3801: break;
3802: case sz_word:
3803: strcpy (buffer,"#<data>.W");
3804: break;
3805: case sz_long:
3806: strcpy (buffer,"#<data>.L");
3807: break;
3808: default:
3809: break;
3810: }
3811: break;
3812: case imm0:
3813: strcpy (buffer,"#<data>.B");
3814: break;
3815: case imm1:
3816: strcpy (buffer,"#<data>.W");
3817: break;
3818: case imm2:
3819: strcpy (buffer,"#<data>.L");
3820: break;
3821: case immi:
3822: strcpy (buffer,"#<data>");
3823: break;
3824:
3825: default:
3826: break;
3827: }
3828: return buffer;
3829: }
3830:
3831: static char *outopcode (int opcode)
3832: {
3833: static char out[100];
3834: struct instr *ins;
3835: int i;
3836:
3837: ins = &table68k[opcode];
3838: for (i = 0; lookuptab[i].name[0]; i++) {
3839: if (ins->mnemo == lookuptab[i].mnemo)
3840: break;
3841: }
3842: {
3843: // char *s = ua (lookuptab[i].name);
3844: const char *s = lookuptab[i].name;
3845: strcpy (out, s);
3846: //xfree (s);
3847: }
3848: if (ins->smode == immi)
3849: strcat (out, "Q");
3850: if (ins->size == sz_byte)
3851: strcat (out,".B");
3852: if (ins->size == sz_word)
3853: strcat (out,".W");
3854: if (ins->size == sz_long)
3855: strcat (out,".L");
3856: strcat (out," ");
3857: if (ins->suse)
3858: strcat (out, decodeEA (ins->smode, ins->size));
3859: if (ins->duse) {
3860: if (ins->suse) strcat (out,",");
3861: strcat (out, decodeEA (ins->dmode, ins->size));
3862: }
3863: return out;
3864: }
3865:
3866: static void generate_one_opcode (int rp)
3867: {
3868: int idx;
3869: uae_u16 smsk, dmsk;
3870: long int opcode = opcode_map[rp];
3871: int i68000 = table68k[opcode].clev > 0;
3872:
3873: if (table68k[opcode].mnemo == i_ILLG
3874: || table68k[opcode].clev > cpu_level)
3875: return;
3876:
3877: for (idx = 0; lookuptab[idx].name[0]; idx++) {
3878: if (table68k[opcode].mnemo == lookuptab[idx].mnemo)
3879: break;
3880: }
3881:
3882: if (table68k[opcode].handler != -1)
3883: return;
3884:
3885: if (opcode_next_clev[rp] != cpu_level) {
3886: //char *name = ua (lookuptab[idx].name);
3887: const char *name = lookuptab[idx].name;
3888: if (generate_stbl)
3889: fprintf (stblfile, "{ %sCPUFUNC(op_%04x_%d), %d }, /* %s */\n",
3890: (using_ce || using_ce020) ? "(cpuop_func*)" : "",
3891: opcode, opcode_last_postfix[rp],
3892: opcode, name);
3893: //xfree (name);
3894: return;
3895: }
3896: fprintf (headerfile, "extern %s op_%04lx_%d_nf;\n",
3897: (using_ce || using_ce020) ? "cpuop_func_ce" : "cpuop_func", opcode, postfix);
3898: fprintf (headerfile, "extern %s op_%04lx_%d_ff;\n",
3899: (using_ce || using_ce020) ? "cpuop_func_ce" : "cpuop_func", opcode, postfix);
3900: printf ("/* %s */\n", outopcode (opcode));
3901: if (i68000)
3902: printf("#ifndef CPUEMU_68000_ONLY\n");
3903: printf ("%s REGPARAM2 CPUFUNC(op_%04lx_%d)(uae_u32 opcode)\n{\n", (using_ce || using_ce020) ? "void" : "unsigned long", opcode, postfix);
3904:
3905: switch (table68k[opcode].stype) {
3906: case 0: smsk = 7; break;
3907: case 1: smsk = 255; break;
3908: case 2: smsk = 15; break;
3909: case 3: smsk = 7; break;
3910: case 4: smsk = 7; break;
3911: case 5: smsk = 63; break;
3912: case 7: smsk = 3; break;
3913: default: abort ();
3914: }
3915: dmsk = 7;
3916:
3917: next_cpu_level = -1;
3918: if (table68k[opcode].suse
3919: && table68k[opcode].smode != imm && table68k[opcode].smode != imm0
3920: && table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
3921: && table68k[opcode].smode != absw && table68k[opcode].smode != absl
3922: && table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
3923: {
3924: if (table68k[opcode].spos == -1) {
3925: if (((int) table68k[opcode].sreg) >= 128)
3926: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
3927: else
3928: printf ("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
3929: } else {
3930: char source[100];
3931: int pos = table68k[opcode].spos;
3932:
3933: if (pos)
3934: sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
3935: else
3936: sprintf (source, "(opcode & %d)", smsk);
3937:
3938: if (table68k[opcode].stype == 3)
3939: printf ("\tuae_u32 srcreg = imm8_table[%s];\n", source);
3940: else if (table68k[opcode].stype == 1)
3941: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
3942: else
3943: printf ("\tuae_u32 srcreg = %s;\n", source);
3944: }
3945: }
3946: if (table68k[opcode].duse
3947: /* Yes, the dmode can be imm, in case of LINK or DBcc */
3948: && table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
3949: && table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
3950: && table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
3951: {
3952: if (table68k[opcode].dpos == -1) {
3953: if (((int) table68k[opcode].dreg) >= 128)
3954: printf ("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
3955: else
3956: printf ("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
3957: } else {
3958: int pos = table68k[opcode].dpos;
3959: if (pos)
3960: printf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
3961: pos, dmsk);
3962: else
3963: printf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
3964: }
3965: }
3966: need_endlabel = 0;
3967: endlabelno++;
3968: sprintf (endlabelstr, "endlabel%d", endlabelno);
3969: count_read = count_write = count_ncycles = count_cycles = 0;
3970: count_read_ea = count_write_ea = count_cycles_ea = 0;
3971: gen_opcode (opcode);
3972: if (need_endlabel)
3973: printf ("%s: ;\n", endlabelstr);
1.1.1.2 root 3974:
1.1 root 3975: returncycles ("", insn_n_cycles);
1.1.1.2 root 3976:
1.1 root 3977: printf ("}");
3978: if (using_ce || using_prefetch) {
3979: if (count_read + count_write + count_cycles == 0)
3980: count_cycles = 4;
3981: printf (" /* %d%s (%d/%d)",
3982: (count_read + count_write) * 4 + count_cycles, count_ncycles ? "+" : "", count_read, count_write);
3983: printf (" */\n");
3984: } else {
3985: printf("\n");
3986: }
3987: printf ("\n");
3988: if (i68000)
3989: printf("#endif\n");
3990: opcode_next_clev[rp] = next_cpu_level;
3991: opcode_last_postfix[rp] = postfix;
3992:
1.1.1.2 root 3993: /* Hatari only : Now patch in the instruction cycles at the beginning of the function: */
3994: if (!using_ce020) {
3995: fseek(stdout, nCurInstrCycPos, SEEK_SET);
3996: printf("%d;", insn_n_cycles);
3997: fseek(stdout, 0, SEEK_END);
3998: }
3999:
4000: /* Hatari only : inc instruction index for cycle exact 68030 cpu */
4001: if (using_ce020 == 2)
4002: instr_index += 1;
4003:
1.1 root 4004: if (generate_stbl) {
4005: // char *name = ua (lookuptab[idx].name);
4006: const char *name = lookuptab[idx].name;
4007: if (i68000)
4008: fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
4009: fprintf (stblfile, "{ %sCPUFUNC(op_%04x_%d), %d }, /* %s */\n",
4010: (using_ce || using_ce020) ? "(cpuop_func*)" : "",
4011: opcode, postfix, opcode, name);
4012: if (i68000)
4013: fprintf (stblfile, "#endif\n");
4014: //xfree (name);
4015: }
4016: }
4017:
4018: static void generate_func (void)
4019: {
4020: int j, rp;
4021:
4022: /* sam: this is for people with low memory (eg. me :)) */
4023: printf ("\n"
4024: "#if !defined(PART_1) && !defined(PART_2) && "
4025: "!defined(PART_3) && !defined(PART_4) && "
4026: "!defined(PART_5) && !defined(PART_6) && "
4027: "!defined(PART_7) && !defined(PART_8)"
4028: "\n"
4029: "#define PART_1 1\n"
4030: "#define PART_2 1\n"
4031: "#define PART_3 1\n"
4032: "#define PART_4 1\n"
4033: "#define PART_5 1\n"
4034: "#define PART_6 1\n"
4035: "#define PART_7 1\n"
4036: "#define PART_8 1\n"
4037: "#endif\n\n");
4038:
4039: rp = 0;
4040: for(j = 1; j <= 8; ++j) {
4041: int k = (j * nr_cpuop_funcs) / 8;
4042: printf ("#ifdef PART_%d\n",j);
4043: for (; rp < k; rp++)
4044: generate_one_opcode (rp);
4045: printf ("#endif\n\n");
4046: }
4047:
4048: if (generate_stbl)
4049: fprintf (stblfile, "{ 0, 0 }};\n");
4050: }
4051:
4052: int main (int argc, char **argv)
4053: {
4054: int i, rp, postfix2;
4055: char fname[100];
4056:
4057: read_table68k ();
4058: do_merges ();
4059:
4060: opcode_map = xmalloc (int, nr_cpuop_funcs);
4061: opcode_last_postfix = xmalloc (int, nr_cpuop_funcs);
4062: opcode_next_clev = xmalloc (int, nr_cpuop_funcs);
4063: counts = xmalloc (unsigned long, 65536);
4064: read_counts ();
4065:
4066: /* It would be a lot nicer to put all in one file (we'd also get rid of
4067: * cputbl.h that way), but cpuopti can't cope. That could be fixed, but
4068: * I don't dare to touch the 68k version. */
4069:
4070: headerfile = fopen ("cputbl.h", "wb");
4071:
4072: stblfile = fopen ("cpustbl.c", "wb");
4073: generate_includes (stblfile);
4074:
4075: using_prefetch = 0;
4076: using_indirect = 0;
4077: using_exception_3 = 1;
4078: using_ce = 0;
4079:
4080: postfix2 = -1;
4081: for (i = 0; i < 32; i++) {
4082: postfix = i;
4083: if ((i >= 6 && i < 11) || (i > 12 && i < 20) || (i > 23 && i < 31))
4084: continue;
4085: generate_stbl = 1;
4086: if (i == 0 || i == 11 || i == 12 || i == 20 || i == 21 || i == 31) {
4087: if (generate_stbl)
4088: fprintf (stblfile, "#ifdef CPUEMU_%d\n", postfix);
4089: postfix2 = postfix;
4090: sprintf (fname, "cpuemu_%d.c", postfix);
4091: if (freopen (fname, "wb", stdout) == NULL) {
4092: perror(fname);
4093: return -1;
4094: }
4095: generate_includes (stdout);
4096: }
4097: using_mmu = 0;
4098: using_prefetch = 0;
4099: using_ce = 0;
4100: using_ce020 = 0;
4101: using_mmu = 0;
4102: cpu_level = 5 - i;
4103: if (i == 11 || i == 12) {
4104: cpu_level = 0;
4105: using_prefetch = 1;
4106: using_exception_3 = 1;
4107: if (i == 12)
4108: using_ce = 1;
4109: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4110: opcode_next_clev[rp] = 0;
4111: } else if (i == 20) {
4112: cpu_level = 2;
4113: using_ce020 = 1;
4114: read_counts ();
4115: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4116: opcode_next_clev[rp] = cpu_level;
4117: } else if (i == 21 || i == 22 || i == 23) {
4118: cpu_level = 3 + (23 - i);
4119: using_ce020 = 2;
4120: if (i == 21) {
4121: read_counts ();
4122: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4123: opcode_next_clev[rp] = cpu_level;
4124: }
4125: } else if (i >= 31 && i < 40) {
4126: cpu_level = 4;
4127: using_mmu = 1;
4128: if (i == 31)
4129: read_counts ();
4130: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4131: opcode_next_clev[rp] = cpu_level;
4132: }
4133:
4134: if (generate_stbl) {
4135: if ((i > 0 && i < 10) || (i >= 20))
4136: fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
4137: fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
4138: }
4139:
4140: generate_func ();
4141: if (generate_stbl) {
4142: if ((i > 0 && i < 10) || (i >= 20))
4143: fprintf (stblfile, "#endif /* CPUEMU_68000_ONLY */\n");
4144: if (postfix2 >= 0)
4145: fprintf (stblfile, "#endif /* CPUEMU_%d */\n", postfix2);
4146: }
4147: postfix2 = -1;
4148: }
4149:
4150: free (table68k);
4151: return 0;
4152: }
4153:
4154: void write_log (const TCHAR *format,...)
4155: {
4156: }
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