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1.1.1.4 root 1: /*
2: * UAE - The Un*x Amiga Emulator
3: *
4: * MC68000 emulation generator
5: *
6: * This is a fairly stupid program that generates a lot of case labels that
7: * can be #included in a switch statement.
8: * As an alternative, it can generate functions that handle specific
9: * MC68000 instructions, plus a prototype header file and a function pointer
10: * array to look up the function for an opcode.
11: * Error checking is bad, an illegal table68k file will cause the program to
12: * call abort().
13: * The generated code is sometimes sub-optimal, an optimizing compiler should
14: * take care of this.
15: *
16: * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
17: *
18: * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
19: */
20:
21: #include "sysconfig.h"
22: #include "sysdeps.h"
23: #include <ctype.h>
24: #include <string.h>
25:
26: #include "readcpu.h"
27: #include "falcon_cycle030.h"
28:
29: #define BOOL_TYPE "int"
30: /* Define the minimal 680x0 where NV flags are not affected by xBCD instructions. */
31: #define xBCD_KEEPS_NV_FLAGS 4
32:
33: static FILE *headerfile;
34: static FILE *stblfile;
35:
36: static int using_prefetch, using_indirect, using_mmu;
37: static int using_ce020;
38: static int using_exception_3;
39: static int using_ce;
40: static int cpu_level;
41: static int count_read, count_write, count_cycles, count_ncycles;
42: static int count_read_ea, count_write_ea, count_cycles_ea;
1.1.1.5 ! root 43: static const char *mmu_postfix;
1.1.1.4 root 44:
45: static int optimized_flags;
46:
47: long nCurInstrCycPos; /* Hatari only : Stores where we have to patch in the current cycles value */
48:
49: #define GF_APDI 1
50: #define GF_AD8R 2
51: #define GF_PC8R 4
52: #define GF_AA 7
53: #define GF_NOREFILL 8
54: #define GF_PREFETCH 16
55: #define GF_FC 32
56: #define GF_MOVE 64
57:
58: /* For the current opcode, the next lower level that will have different code.
59: * Initialized to -1 for each opcode. If it remains unchanged, indicates we
60: * are done with that opcode. */
61: static int next_cpu_level;
62:
63: static int *opcode_map;
64: static int *opcode_next_clev;
65: static int *opcode_last_postfix;
66: static unsigned long *counts;
67: static int generate_stbl;
68: static int fixupcnt;
69:
70: static int instr_index = 0; /* Hatari: Added to give a unique index to each 68030 cycle exact instruction (CPU_EMU_21) */
71: static int instr_table; /* Hatari: Used to know which cycle table to use (CPU_EMU_21) */
72: static int instr_table_index; /* Hatari: Used when the cycle table is not the generic one to set the line of the table (CPU_EMU_21) */
73:
74: /* used to disable the return cycles function call when there are more than one cycle to take into account for an instruction */
75: /* Falcon CPU only (CPUEMU_21)) */
76: static bool no_return_cycles;
77:
78: /* All the following indexes are useful to get the correct cycle index in the cycle tables for 68030 cycle exact CPU (CPU_21) */
79: /* Hatari only code */
80: static int chk_w_index = 0;
81: static int chk_l_index = 0;
82: static int chk2_b_index = 0;
83: static int chk2_w_index = 0;
84: static int chk2_l_index = 0;
85: static int cas_b_index = 0;
86: static int cas_w_index = 0;
87: static int cas_l_index = 0;
88: static int divl_index = 0;
89:
90: /* These defines describe the different tables used for 68030 Cycle exact (Hatari only) */
91: #define TABLE_FALCON_CYCLES 0
92: #define TABLE_FALCON_CYCLES_CHK2_BW 1
93: #define TABLE_FALCON_CYCLES_CHK2_L 2
94: #define TABLE_FALCON_CYCLES_CHK_L 3
95: #define TABLE_FALCON_CYCLES_CHK_W 4
96: #define TABLE_FALCON_CYCLES_CAS_BW 5
97: #define TABLE_FALCON_CYCLES_CAS_L 6
98: #define TABLE_FALCON_CYCLES_CAS2_W 7
99: #define TABLE_FALCON_CYCLES_CAS2_L 8
100: #define TABLE_FALCON_CYCLES_RTE 9
101: #define TABLE_FALCON_CYCLES_BCC 10
102: #define TABLE_FALCON_CYCLES_DBCC 11
103: #define TABLE_FALCON_CYCLES_TRAPCC 12
104: #define TABLE_FALCON_CYCLES_TRAPCC_W 13
105: #define TABLE_FALCON_CYCLES_TRAPCC_L 14
106: #define TABLE_FALCON_CYCLES_TRAPV 15
107: #define TABLE_FALCON_CYCLES_DIVU_L 16
108: #define TABLE_FALCON_CYCLES_DIVS_L 17
109: #define TABLE_FALCON_CYCLES_BFTST_MEM 18
110: #define TABLE_FALCON_CYCLES_BFEXTU_MEM 19
111: #define TABLE_FALCON_CYCLES_BFCHG_MEM 20
112: #define TABLE_FALCON_CYCLES_BFEXTS_MEM 21
113: #define TABLE_FALCON_CYCLES_BFCLR_MEM 22
114: #define TABLE_FALCON_CYCLES_BFFFO_MEM 23
115: #define TABLE_FALCON_CYCLES_BFSET_MEM 24
116: #define TABLE_FALCON_CYCLES_BFINS_MEM 25
117: #define TABLE_FALCON_CYCLES_LSD 26
118: #define TABLE_FALCON_CYCLES_ASR 27
119: #define TABLE_FALCON_CYCLES_MOVEC 28
120: #define TABLE_FALCON_CYCLES_MOVES_EA_RN 29
121: #define TABLE_FALCON_CYCLES_MOVES_RN_EA 30
122: #define TABLE_FALCON_CYCLES_68030_INTERNAL 31
123:
124:
125: #define GENA_GETV_NO_FETCH 0
126: #define GENA_GETV_FETCH 1
127: #define GENA_GETV_FETCH_ALIGN 2
128: #define GENA_MOVEM_DO_INC 0
129: #define GENA_MOVEM_NO_INC 1
130: #define GENA_MOVEM_MOVE16 2
131:
132: /**
133: Table_labels table for all case.
134: */
135: static const char* falcon_cycles_tables[] = {
136: "table_falcon_cycles",
137: "table_falcon_cycles_CHK2_BW",
138: "table_falcon_cycles_CHK2_L",
139: "table_falcon_cycles_CHK_L",
140: "table_falcon_cycles_CHK_W",
141: "table_falcon_cycles_CAS_BW",
142: "table_falcon_cycles_CAS_L",
143: "table_falcon_cycles_CAS2_W",
144: "table_falcon_cycles_CAS2_L",
145: "table_falcon_cycles_RTE",
146: "table_falcon_cycles_Bcc",
147: "table_falcon_cycles_DBcc",
148: "table_falcon_cycles_TRAPcc",
149: "table_falcon_cycles_TRAPcc_W",
150: "table_falcon_cycles_TRAPcc_L",
151: "table_falcon_cycles_TRAPV",
152: "table_falcon_cycles_DIVU_L",
153: "table_falcon_cycles_DIVS_L",
154: "table_falcon_cycles_BFTST_Mem",
155: "table_falcon_cycles_BFEXTU_Mem",
156: "table_falcon_cycles_BFCHG_Mem",
157: "table_falcon_cycles_BFEXTS_Mem",
158: "table_falcon_cycles_BFCLR_Mem",
159: "table_falcon_cycles_BFFFO_Mem",
160: "table_falcon_cycles_BFSET_Mem",
161: "table_falcon_cycles_BFINS_Mem",
162: "table_falcon_cycles_LSD",
163: "table_falcon_cycles_ASR",
164: "table_falcon_cycles_MOVEC",
165: "table_falcon_cycles_MOVES_EA_RN",
166: "table_falcon_cycles_MOVES_RN_EA",
167: "table_falcon_cycles_68030_internal"
168: };
169:
170: static void read_counts (void)
171: {
172: FILE *file;
173: unsigned long opcode, count, total;
174: char name[20];
175: int nr = 0;
176: int ret;
177: memset (counts, 0, 65536 * sizeof *counts);
178:
179: count = 0;
180: file = fopen ("frequent.68k", "r");
181: if (file) {
182: ret = fscanf (file, "Total: %lu\n", &total);
183: while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
184: opcode_next_clev[nr] = 5;
185: opcode_last_postfix[nr] = -1;
186: opcode_map[nr++] = opcode;
187: counts[opcode] = count;
188: }
189: fclose (file);
190: }
191: if (nr == nr_cpuop_funcs)
192: return;
193: for (opcode = 0; opcode < 0x10000; opcode++) {
194: if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
195: && counts[opcode] == 0)
196: {
197: opcode_next_clev[nr] = 5;
198: opcode_last_postfix[nr] = -1;
199: opcode_map[nr++] = opcode;
200: counts[opcode] = count;
201: }
202: }
203: if (nr != nr_cpuop_funcs)
204: abort ();
205: }
206:
207: static char endlabelstr[80];
208: static int endlabelno = 0;
209: static int need_endlabel;
210:
211: static int n_braces, limit_braces;
212: static int m68k_pc_offset;
213: static int insn_n_cycles, insn_n_cycles020;
214:
215: static void fpulimit (void)
216: {
217: if (limit_braces)
218: return;
219: printf ("\n#ifdef FPUEMU\n");
220: limit_braces = n_braces;
221: n_braces = 0;
222: }
223:
224: static void returncycles (const char *s, int cycles)
225: {
226: if (using_ce)
227: return;
228:
229: if (using_ce020 == 1)
230: printf ("%sreturn;\n", s);
231: else if (using_ce020 == 2) {
232: if (no_return_cycles == true)
233: return;
234: // TODO: This first if statement should be removed when all the cycles are correctly generated for the Falcon 68030 CPU
235: // The next "else" should be removed too and only the printf line should be keept.
236: if (instr_table == TABLE_FALCON_CYCLES && table_falcon_cycles[instr_index].cache_cycles == 0) {
237: // set a temporary false value for this instruction cycles timing.
238: printf ("\tregs.ce030_instr_cycles = table_falcon_cycles[0];\n");
239: }
240: else {
241: printf ("%s\tregs.ce030_instr_cycles = %s[%d];\n", s, falcon_cycles_tables[instr_table], instr_table_index);
242: }
243:
244: printf ("%s\treturn;\n", s);
245: }
246: else
247: printf ("%sreturn %d * CYCLE_UNIT / 2;\n", s, cycles);
248: }
249:
250: /* Todo : remove this function when all Falcon cycles are coded */
251: static void addcycles_ce020 (int head, int tail, int cache_cycles, int noncache_cycles)
252: {
253: if (!using_ce020)
254: return;
255: if (cache_cycles > 0 && noncache_cycles > 0) {
256: //not needed anymore
257: }
258: count_cycles += noncache_cycles;
259: }
260:
261: static void addcycles000 (int cycles)
262: {
263: if (!using_ce)
264: return;
265: printf ("\tdo_cycles_ce000 (%d);\n", cycles);
266: count_cycles += cycles;
267: }
268: static void addcycles000_2 (const char *s, int cycles)
269: {
270: if (!using_ce)
271: return;
272: printf ("%sdo_cycles_ce000 (%d);\n", s, cycles);
273: count_cycles += cycles;
274: }
275:
276: static void addcycles000_3 (const char *s)
277: {
278: if (!using_ce)
279: return;
280: printf ("%sif (cycles > 0) do_cycles_ce000 (cycles);\n", s);
281: count_ncycles++;
282: }
283:
284: static int isreg (amodes mode)
285: {
286: if (mode == Dreg || mode == Areg)
287: return 1;
288: return 0;
289: }
290:
291: static void start_brace (void)
292: {
293: n_braces++;
294: printf ("{");
295: }
296:
297: static void close_brace (void)
298: {
299: assert (n_braces > 0);
300: n_braces--;
301: printf ("}");
302: }
303:
304: static void finish_braces (void)
305: {
306: while (n_braces > 0)
307: close_brace ();
308: }
309:
310: static void pop_braces (int to)
311: {
312: while (n_braces > to)
313: close_brace ();
314: }
315:
316: static int bit_size (int size)
317: {
318: switch (size) {
319: case sz_byte: return 8;
320: case sz_word: return 16;
321: case sz_long: return 32;
322: default: abort ();
323: }
324: return 0;
325: }
326:
327: static const char *bit_mask (int size)
328: {
329: switch (size) {
330: case sz_byte: return "0xff";
331: case sz_word: return "0xffff";
332: case sz_long: return "0xffffffff";
333: default: abort ();
334: }
335: return 0;
336: }
337:
338: static const char *srcl, *dstl;
339: static const char *srcw, *dstw;
340: static const char *srcb, *dstb;
341: static const char *ce020_prefetch_long;
342: static const char *ce020_prefetch_word;
343:
344: static void gen_nextilong (const char *type, const char *name, int flags)
345: {
346: int r = m68k_pc_offset;
347: m68k_pc_offset += 4;
348:
349: if (using_ce020) {
350: printf ("\t%s %s = %s (%d);\n", type, name, ce020_prefetch_long, r);
351: count_read += 2;
352: } else if (using_ce) {
353: printf ("\t%s %s;\n", type, name);
354: /* we must do this because execution order of (something | something2) is not defined */
355: if (flags & GF_NOREFILL) {
356: printf ("\t%s = get_word_ce_prefetch (%d) << 16;\n", name, r + 2);
357: count_read++;
358: printf ("\t%s |= regs.irc;\n", name);
359: } else {
360: printf ("\t%s = get_word_ce_prefetch (%d) << 16;\n", name, r + 2);
361: count_read++;
362: printf ("\t%s |= get_word_ce_prefetch (%d);\n", name, r + 4);
363: count_read++;
364: }
365: } else {
366: if (using_prefetch) {
367: if (flags & GF_NOREFILL) {
368: printf ("\t%s %s;\n", type, name);
369: printf ("\t%s = get_word_prefetch (%d) << 16;\n", name, r + 2);
370: count_read++;
371: printf ("\t%s |= regs.irc;\n", name);
372: insn_n_cycles += 4;
373: } else {
374: printf ("\t%s %s = get_long_prefetch (%d);\n", type, name, r + 2);
375: count_read++;
376: count_read++;
377: insn_n_cycles += 8;
378: }
379: } else if (using_indirect) {
380: insn_n_cycles += 8;
381: printf ("\t%s %s = get_ilongi (%d);\n", type, name, r);
382: } else if (using_mmu) {
383: insn_n_cycles += 8;
1.1.1.5 ! root 384: printf ("\t%s %s = get_ilong_mmu%s (%d);\n", type, name,
! 385: mmu_postfix, r);
1.1.1.4 root 386: } else {
387: insn_n_cycles += 8;
388: printf ("\t%s %s = get_ilong (%d);\n", type, name, r);
389: }
390: }
391: }
392:
393: static const char *gen_nextiword (int flags)
394: {
395: static char buffer[80];
396: int r = m68k_pc_offset;
397: m68k_pc_offset += 2;
398:
399: if (using_ce020) {
400: sprintf (buffer, "%s (%d)", ce020_prefetch_word, r);
401: count_read++;
402: } else if (using_ce) {
403: if (flags & GF_NOREFILL) {
404: strcpy (buffer, "regs.irc");
405: } else {
406: sprintf (buffer, "get_word_ce_prefetch (%d)", r + 2);
407: count_read++;
408: }
409: } else {
410: if (using_prefetch) {
411: if (flags & GF_NOREFILL) {
412: sprintf (buffer, "regs.irc"/*, r*/);
413: } else {
414: sprintf (buffer, "get_word_prefetch (%d)", r + 2);
415: count_read++;
416: insn_n_cycles += 4;
417: }
418: } else if (using_indirect) {
419: sprintf (buffer, "get_iwordi(%d)", r);
420: insn_n_cycles += 4;
421: } else if (using_mmu) {
1.1.1.5 ! root 422: sprintf (buffer, "get_iword_mmu%s (%d)",
! 423: mmu_postfix, r);
1.1.1.4 root 424: insn_n_cycles += 4;
425: } else {
426: sprintf (buffer, "get_iword (%d)", r);
427: insn_n_cycles += 4;
428: }
429: }
430: return buffer;
431: }
432:
433: static const char *gen_nextibyte (int flags)
434: {
435: static char buffer[80];
436: int r = m68k_pc_offset;
437: m68k_pc_offset += 2;
438:
439: if (using_ce020) {
440: sprintf (buffer, "(uae_u8)%s (%d)", ce020_prefetch_word, r);
441: count_read++;
442: } else if (using_ce) {
443: if (flags & GF_NOREFILL) {
444: strcpy (buffer, "(uae_u8)regs.irc");
445: } else {
446: sprintf (buffer, "(uae_u8)get_word_ce_prefetch (%d)", r + 2);
447: count_read++;
448: }
449: } else {
450: insn_n_cycles += 4;
451: if (using_prefetch) {
452: if (flags & GF_NOREFILL) {
453: sprintf (buffer, "(uae_u8)regs.irc"/*, r*/);
454: } else {
455: sprintf (buffer, "(uae_u8)get_word_prefetch (%d)", r + 2);
456: insn_n_cycles += 4;
457: count_read++;
458: }
459: } else if (using_indirect) {
460: sprintf (buffer, "get_ibytei (%d)", r);
461: insn_n_cycles += 4;
462: } else if (using_mmu) {
1.1.1.5 ! root 463: sprintf (buffer, "get_ibyte_mmu%s (%d)",
! 464: mmu_postfix, r);
1.1.1.4 root 465: insn_n_cycles += 4;
466: } else {
467: sprintf (buffer, "get_ibyte (%d)", r);
468: insn_n_cycles += 4;
469: }
470: }
471: return buffer;
472: }
473:
474: static void irc2ir (void)
475: {
476: if (!using_prefetch)
477: return;
478: printf ("\tregs.ir = regs.irc;\n");
479: if (using_ce)
480: printf ("\tipl_fetch ();\n");
481: }
482:
483: static int did_prefetch;
484:
485: static void fill_prefetch_2 (void)
486: {
487: if (!using_prefetch)
488: return;
489: if (using_ce)
490: printf ("\tget_word_ce_prefetch (%d);\n", m68k_pc_offset + 2);
491: else
492: printf ("\tget_word_prefetch (%d);\n", m68k_pc_offset + 2);
493: did_prefetch = 1;
494: count_read++;
495: insn_n_cycles += 4;
496: }
497:
498: static void fill_prefetch_1 (int o)
499: {
500: if (!using_prefetch)
501: return;
502: if (using_ce) {
503: printf ("\tget_word_ce_prefetch (%d);\n", o);
504: } else {
505: printf ("\tget_word_prefetch (%d);\n", o);
506: }
507: did_prefetch = 1;
508: count_read++;
509: insn_n_cycles += 4;
510: }
511:
512: static void fill_prefetch_full (void)
513: {
514: fill_prefetch_1 (0);
515: irc2ir ();
516: fill_prefetch_1 (2);
517: }
518:
519: static void fill_prefetch_0 (void)
520: {
521: if (!using_prefetch)
522: return;
523: if (using_ce)
524: printf ("\tget_word_ce_prefetch (0);\n");
525: else
526: printf ("\tget_word_prefetch (0);\n");
527: did_prefetch = 1;
528: count_read++;
529: insn_n_cycles += 4;
530: }
531:
532: static void dummy_prefetch (void)
533: {
534: int o = m68k_pc_offset + 2;
535: if (!using_prefetch)
536: return;
537: if (using_ce) {
538: printf ("\tget_wordi_ce (m68k_getpc () + %d);\n", o);
539: } else {
540: printf ("\tget_wordi (m68k_getpc () + %d);\n", o);
541: }
542: count_read++;
543: insn_n_cycles += 4;
544: }
545:
546: static void fill_prefetch_next_1 (void)
547: {
548: irc2ir ();
549: fill_prefetch_1 (m68k_pc_offset + 2);
550: }
551:
552: static void fill_prefetch_next (void)
553: {
554: fill_prefetch_next_1 ();
555: }
556:
557: #if 0
558: static void fill_prefetch_next_delay (int extracycles)
559: {
560: if (!using_prefetch)
561: return;
562: if (using_ce) {
563: if (extracycles > 0) {
564: printf("\t{\n");
565: fill_prefetch_next ();
566: printf("\tif (%d > 0) do_cycles(%d * CYCLE_UNIT / 2);\n",
567: extracycles, extracycles);
568: printf("\t}\n");
569: } else {
570: fill_prefetch_next ();
571: }
572: } else {
573: fill_prefetch_next ();
574: }
575: }
576: #endif
577:
578: static void fill_prefetch_finish (void)
579: {
580: if (did_prefetch || !using_prefetch)
581: return;
582: fill_prefetch_1 (m68k_pc_offset);
583: }
584:
585: static void setpc (const char *format, ...)
586: {
587: va_list parms;
588: char buffer[1000];
589:
590: va_start (parms, format);
591: _vsnprintf (buffer, 1000 - 1, format, parms);
592: va_end (parms);
593:
594: if (using_mmu)
595: printf ("\tm68k_setpc_mmu (%s);\n", buffer);
596: else
597: printf ("\tm68k_setpc (%s);\n", buffer);
598: }
599:
600: static void incpc (const char *format, ...)
601: {
602: va_list parms;
603: char buffer[1000];
604:
605: va_start (parms, format);
606: _vsnprintf (buffer, 1000 - 1, format, parms);
607: va_end (parms);
608:
609: if (using_mmu)
610: printf ("\tm68k_incpci (%s);\n", buffer);
611: else
612: printf ("\tm68k_incpc (%s);\n", buffer);
613: }
614:
615: static void sync_m68k_pc (void)
616: {
617: if (m68k_pc_offset == 0)
618: return;
619: incpc ("%d", m68k_pc_offset);
620: m68k_pc_offset = 0;
621: }
622:
623: static void gen_set_fault_pc (void)
624: {
625: if (!using_mmu)
626: return;
627: sync_m68k_pc ();
628: printf ("\tregs.fault_pc = m68k_getpci ();\n");
629: m68k_pc_offset = 0;
630: }
631:
632: static void syncmovepc (int getv, int flags)
633: {
634: #if 0
635: if (!(flags & GF_MOVE))
636: return;
637: if (getv == 1) {
638: sync_m68k_pc ();
639: //fill_prefetch_next ();
640: }
641: #endif
642: }
643:
644: /* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
645: * the calling routine handles Apdi and Aipi modes.
646: * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
647:
648: /* fixup indicates if we want to fix up adress registers in pre decrement
649: * or post increment mode now (0) or later (1). A value of 2 will then be
650: * used to do the actual fix up. This allows to do all memory readings
651: * before any register is modified, and so to rerun operation without
652: * side effect in case a bus fault is generated by any memory access.
653: * XJ - 2006/11/13 */
654:
655: static void genamode2 (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags, int fixup)
656: {
657: char namea[100];
658: int m68k_pc_offset_last = m68k_pc_offset;
659:
660: sprintf (namea, "%sa", name);
661:
662: start_brace ();
663: switch (mode) {
664: case Dreg:
665: if (movem)
666: abort ();
667: if (getv == 1)
668: switch (size) {
669: case sz_byte:
670: #ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
671: /* This causes the target compiler to generate better code on few systems */
672: printf ("\tuae_s8 %s = ((uae_u8*)&m68k_dreg (regs, %s))[3];\n", name, reg);
673: #else
674: printf ("\tuae_s8 %s = m68k_dreg (regs, %s);\n", name, reg);
675: #endif
676: break;
677: case sz_word:
678: #ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
679: printf ("\tuae_s16 %s = ((uae_s16*)&m68k_dreg (regs, %s))[1];\n", name, reg);
680: #else
681: printf ("\tuae_s16 %s = m68k_dreg (regs, %s);\n", name, reg);
682: #endif
683: break;
684: case sz_long:
685: printf ("\tuae_s32 %s = m68k_dreg (regs, %s);\n", name, reg);
686: break;
687: default:
688: abort ();
689: }
690: syncmovepc (getv, flags);
691: return;
692: case Areg:
693: if (movem)
694: abort ();
695: if (getv == 1)
696: switch (size) {
697: case sz_word:
698: printf ("\tuae_s16 %s = m68k_areg (regs, %s);\n", name, reg);
699: break;
700: case sz_long:
701: printf ("\tuae_s32 %s = m68k_areg (regs, %s);\n", name, reg);
702: break;
703: default:
704: abort ();
705: }
706: syncmovepc (getv, flags);
707: return;
708: case Aind: // (An)
709: printf ("\tuaecptr %sa = m68k_areg (regs, %s);\n", name, reg);
710: break;
711: case Aipi: // (An)+
712: printf ("\tuaecptr %sa = m68k_areg (regs, %s);\n", name, reg);
713: break;
714: case Apdi: // -(An)
715: printf ("\tuaecptr %sa;\n", name);
716: switch (size) {
717: case sz_byte:
718: if (movem)
719: printf ("\t%sa = m68k_areg (regs, %s);\n", name, reg);
720: else
721: printf ("\t%sa = m68k_areg (regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
722: break;
723: case sz_word:
724: printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
725: break;
726: case sz_long:
727: printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
728: break;
729: default:
730: abort ();
731: }
732: if (!(flags & GF_APDI)) {
733: addcycles000 (2);
734: insn_n_cycles += 2;
735: count_cycles_ea += 2;
736: }
737: break;
738: case Ad16: // (d16,An)
739: printf ("\tuaecptr %sa = m68k_areg (regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword (flags));
740: count_read_ea++;
741: break;
742: case Ad8r: // (d8,An,Xn)
743: printf ("\tuaecptr %sa;\n", name);
744: if (cpu_level > 1) {
745: if (next_cpu_level < 1)
746: next_cpu_level = 1;
747: sync_m68k_pc ();
748: start_brace ();
749: /* This would ordinarily be done in gen_nextiword, which we bypass. */
750: insn_n_cycles += 4;
751: if (using_ce020 || using_mmu)
752: printf ("\t%sa = x_get_disp_ea_020 (m68k_areg (regs, %s), x_next_iword ());\n", name, reg);
753: else
754: printf ("\t%sa = get_disp_ea_020 (m68k_areg (regs, %s), next_iword ());\n", name, reg);
755: } else {
756: if (!(flags & GF_AD8R)) {
757: addcycles000 (2);
758: insn_n_cycles += 2;
759: count_cycles_ea += 2;
760: }
761: printf ("\t%sa = get_disp_ea_000 (m68k_areg (regs, %s), %s);\n", name, reg, gen_nextiword (flags));
762: count_read_ea++;
763: }
764: break;
765: case PC16: // (d16,PC,Xn)
766: printf ("\tuaecptr %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset);
767: printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
768: break;
769: case PC8r: // (d8,PC,Xn)
770: printf ("\tuaecptr tmppc;\n");
771: printf ("\tuaecptr %sa;\n", name);
772: if (cpu_level > 1) {
773: if (next_cpu_level < 1)
774: next_cpu_level = 1;
775: sync_m68k_pc ();
776: start_brace ();
777: /* This would ordinarily be done in gen_nextiword, which we bypass. */
778: insn_n_cycles += 4;
779: printf ("\ttmppc = m68k_getpc ();\n");
780: if (using_ce020 || using_mmu)
781: printf ("\t%sa = x_get_disp_ea_020 (tmppc, x_next_iword ());\n", name);
782: else
783: printf ("\t%sa = get_disp_ea_020 (tmppc, next_iword ());\n", name);
784: } else {
785: printf ("\ttmppc = m68k_getpc () + %d;\n", m68k_pc_offset);
786: if (!(flags & GF_PC8R)) {
787: addcycles000 (2);
788: insn_n_cycles += 2;
789: count_cycles_ea += 2;
790: }
791: printf ("\t%sa = get_disp_ea_000 (tmppc, %s);\n", name, gen_nextiword (flags));
792: }
793:
794: break;
795: case absw:
796: printf ("\tuaecptr %sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
797: break;
798: case absl:
799: gen_nextilong ("uaecptr", namea, flags);
800: count_read_ea += 2;
801: break;
802: case imm:
803: if (getv != 1)
804: abort ();
805: insn_n_cycles020++;
806: switch (size) {
807: case sz_byte:
808: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
809: count_read_ea++;
810: break;
811: case sz_word:
812: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
813: count_read_ea++;
814: break;
815: case sz_long:
816: gen_nextilong ("uae_s32", name, flags);
817: count_read_ea += 2;
818: break;
819: default:
820: abort ();
821: }
822: syncmovepc (getv, flags);
823: return;
824: case imm0:
825: if (getv != 1)
826: abort ();
827: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
828: count_read_ea++;
829: syncmovepc (getv, flags);
830: return;
831: case imm1:
832: if (getv != 1)
833: abort ();
834: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
835: count_read_ea++;
836: syncmovepc (getv, flags);
837: return;
838: case imm2:
839: if (getv != 1)
840: abort ();
841: gen_nextilong ("uae_s32", name, flags);
842: count_read_ea += 2;
843: syncmovepc (getv, flags);
844: return;
845: case immi:
846: if (getv != 1)
847: abort ();
848: printf ("\tuae_u32 %s = %s;\n", name, reg);
849: syncmovepc (getv, flags);
850: return;
851: default:
852: abort ();
853: }
854:
855: syncmovepc (getv, flags);
856:
857: /* We get here for all non-reg non-immediate addressing modes to
858: * actually fetch the value. */
859:
860: if ((using_prefetch || using_ce) && using_exception_3 && getv != 0 && size != sz_byte) {
861: int offset = 0;
862: if (flags & GF_MOVE) {
863: offset = m68k_pc_offset;
864: if (getv == 2)
865: offset += 2;
866: } else {
867: offset = m68k_pc_offset_last;
868: }
869: printf ("\tif (%sa & 1) {\n", name);
870: printf ("\t\texception3 (opcode, m68k_getpc () + %d, %sa);\n",
871: offset, name);
872: printf ("\t\tgoto %s;\n", endlabelstr);
873: printf ("\t}\n");
874: need_endlabel = 1;
875: start_brace ();
876: }
877:
878: if (flags & GF_PREFETCH)
879: fill_prefetch_next ();
880:
881: if (getv == 1) {
882: start_brace ();
883: if (using_ce020) {
884: switch (size) {
885: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, srcb, name); count_read++; break;
886: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, srcw, name); count_read++; break;
887: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = %s (%sa);\n", name, srcl, name); count_read += 2; break;
888: default: abort ();
889: }
890: } else if (using_ce) {
891: switch (size) {
892: case sz_byte: printf ("\tuae_s8 %s = get_byte_ce (%sa);\n", name, name); count_read++; break;
893: case sz_word: printf ("\tuae_s16 %s = get_word_ce (%sa);\n", name, name); count_read++; break;
894: case sz_long: printf ("\tuae_s32 %s = get_word_ce (%sa) << 16; %s |= get_word_ce (%sa + 2);\n", name, name, name, name); count_read += 2; break;
895: default: abort ();
896: }
897: } else if (using_mmu) {
898: if (flags & GF_FC) {
899: switch (size) {
1.1.1.5 ! root 900: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = sfc%s_get_byte (%sa);\n", name, mmu_postfix, name); break;
! 901: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = sfc%s_get_word (%sa);\n", name, mmu_postfix, name); break;
! 902: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = sfc%s_get_long (%sa);\n", name, mmu_postfix, name); break;
1.1.1.4 root 903: default: abort ();
904: }
905: } else {
906: switch (size) {
1.1.1.5 ! root 907: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = get_byte_mmu%s (%sa);\n", name, mmu_postfix, name); break;
! 908: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = get_word_mmu%s (%sa);\n", name, mmu_postfix, name); break;
! 909: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = get_long_mmu%s (%sa);\n", name, mmu_postfix, name); break;
1.1.1.4 root 910: default: abort ();
911: }
912: }
913: } else {
914: switch (size) {
915: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = get_byte (%sa);\n", name, name); count_read++; break;
916: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = get_word (%sa);\n", name, name); count_read++; break;
917: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = get_long (%sa);\n", name, name); count_read += 2; break;
918: default: abort ();
919: }
920: }
921: }
922:
923: /* We now might have to fix up the register for pre-dec or post-inc
924: * addressing modes. */
925: if (!movem)
926: switch (mode) {
927: case Aipi:
928: if (fixup == 1) {
929: printf ("\tmmufixup[%d].reg = %s;\n", fixupcnt, reg);
930: printf ("\tmmufixup[%d].value = m68k_areg (regs, %s);\n", fixupcnt, reg);
931: }
932: switch (size) {
933: case sz_byte:
934: printf ("\tm68k_areg (regs, %s) += areg_byteinc[%s];\n", reg, reg);
935: break;
936: case sz_word:
937: printf ("\tm68k_areg (regs, %s) += 2;\n", reg);
938: break;
939: case sz_long:
940: printf ("\tm68k_areg (regs, %s) += 4;\n", reg);
941: break;
942: default:
943: abort ();
944: }
945: break;
946: case Apdi:
947: if (fixup == 1) {
948: printf ("\tmmufixup[%d].reg = %s;\n", fixupcnt, reg);
949: printf ("\tmmufixup[%d].value = m68k_areg (regs, %s);\n", fixupcnt, reg);
950: }
951: printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
952: break;
953: default:
954: break;
955: }
956: }
957:
958: static void genamode_fixup (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags, int fixup)
959: {
960: if (fixup != 2) {
961: genamode2 (mode, reg, size, name, getv, movem, flags, fixup);
962: } else {
963: if (!movem) {
964: switch ((int)mode)
965: {
966: case Aipi:
967: case Apdi:
968: printf ("\tmmufixup[0].reg = -1;\n"/*, fixupcnt*/);
969: break;
970: }
971: }
972: }
973: }
974:
975: static void genamode (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
976: {
977: genamode2 (mode, reg, size, name, getv, movem, flags, 0);
978: }
979: static void genamode_pre (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
980: {
981: genamode_fixup (mode, reg, size, name, getv, movem, flags, using_mmu ? 1 : 0);
982: }
983: static void genamode_post (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
984: {
985: if (using_mmu)
986: genamode_fixup (mode, reg, size, name, getv, movem, flags, 2);
987: }
988:
989: static void genastore_2 (const char *from, amodes mode, const char *reg, wordsizes size, const char *to, int store_dir, int flags)
990: {
991: switch (mode) {
992: case Dreg:
993: switch (size) {
994: case sz_byte:
995: printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
996: break;
997: case sz_word:
998: printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
999: break;
1000: case sz_long:
1001: printf ("\tm68k_dreg (regs, %s) = (%s);\n", reg, from);
1002: break;
1003: default:
1004: abort ();
1005: }
1006: break;
1007: case Areg:
1008: switch (size) {
1009: case sz_word:
1010: printf ("\tm68k_areg (regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
1011: break;
1012: case sz_long:
1013: printf ("\tm68k_areg (regs, %s) = (%s);\n", reg, from);
1014: break;
1015: default:
1016: abort ();
1017: }
1018: break;
1019: case Aind:
1020: case Aipi:
1021: case Apdi:
1022: case Ad16:
1023: case Ad8r:
1024: case absw:
1025: case absl:
1026: case PC16:
1027: case PC8r:
1028: gen_set_fault_pc ();
1029: if (using_ce020) {
1030: switch (size) {
1031: case sz_byte:
1032: printf ("\t%s (%sa, %s);\n", dstb, to, from);
1033: count_write++;
1034: break;
1035: case sz_word:
1036: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1037: abort ();
1038: printf ("\t%s (%sa, %s);\n", dstw, to, from);
1039: count_write++;
1040: break;
1041: case sz_long:
1042: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1043: abort ();
1044: printf ("\t%s (%sa, %s);\n", dstl, to, from);
1045: count_write += 2;
1046: break;
1047: default:
1048: abort ();
1049: }
1050: } else if (using_ce) {
1051: switch (size) {
1052: case sz_byte:
1053: printf ("\tput_byte_ce (%sa, %s);\n", to, from);
1054: count_write++;
1055: break;
1056: case sz_word:
1057: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1058: abort ();
1059: printf ("\tput_word_ce (%sa, %s);\n", to, from);
1060: count_write++;
1061: break;
1062: case sz_long:
1063: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1064: abort ();
1065: if (store_dir)
1066: printf ("\tput_word_ce (%sa + 2, %s); put_word_ce (%sa, %s >> 16);\n", to, from, to, from);
1067: else
1068: printf ("\tput_word_ce (%sa, %s >> 16); put_word_ce (%sa + 2, %s);\n", to, from, to, from);
1069: count_write += 2;
1070: break;
1071: default:
1072: abort ();
1073: }
1074: } else if (using_mmu) {
1075: switch (size) {
1076: case sz_byte:
1077: insn_n_cycles += 4;
1078: if (flags & GF_FC)
1.1.1.5 ! root 1079: printf ("\tdfc%s_put_byte (%sa, %s);\n", mmu_postfix, to, from);
1.1.1.4 root 1080: else
1.1.1.5 ! root 1081: printf ("\tput_byte_mmu%s (%sa, %s);\n", mmu_postfix, to, from);
1.1.1.4 root 1082: break;
1083: case sz_word:
1084: insn_n_cycles += 4;
1085: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1086: abort ();
1087: if (flags & GF_FC)
1.1.1.5 ! root 1088: printf ("\tdfc%s_put_word (%sa, %s);\n", mmu_postfix, to, from);
1.1.1.4 root 1089: else
1.1.1.5 ! root 1090: printf ("\tput_word_mmu%s (%sa, %s);\n", mmu_postfix, to, from);
1.1.1.4 root 1091: break;
1092: case sz_long:
1093: insn_n_cycles += 8;
1094: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1095: abort ();
1096: if (flags & GF_FC)
1.1.1.5 ! root 1097: printf ("\tdfc%s_put_long (%sa, %s);\n", mmu_postfix, to, from);
1.1.1.4 root 1098: else
1.1.1.5 ! root 1099: printf ("\tput_long_mmu%s (%sa, %s);\n", mmu_postfix, to, from);
1.1.1.4 root 1100: break;
1101: default:
1102: abort ();
1103: }
1104: } else {
1105: switch (size) {
1106: case sz_byte:
1107: insn_n_cycles += 4;
1108: printf ("\tput_byte (%sa, %s);\n", to, from);
1109: count_write++;
1110: break;
1111: case sz_word:
1112: insn_n_cycles += 4;
1113: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1114: abort ();
1115: printf ("\tput_word (%sa, %s);\n", to, from);
1116: count_write++;
1117: break;
1118: case sz_long:
1119: insn_n_cycles += 8;
1120: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1121: abort ();
1122: printf ("\tput_long (%sa, %s);\n", to, from);
1123: count_write += 2;
1124: break;
1125: default:
1126: abort ();
1127: }
1128: }
1129: break;
1130: case imm:
1131: case imm0:
1132: case imm1:
1133: case imm2:
1134: case immi:
1135: abort ();
1136: break;
1137: default:
1138: abort ();
1139: }
1140: }
1141:
1142: static void genastore (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1143: {
1144: genastore_2 (from, mode, reg, size, to, 0, 0);
1145: }
1146: static void genastore_rev (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1147: {
1148: genastore_2 (from, mode, reg, size, to, 1, 0);
1149: }
1150: static void genastore_fc (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1151: {
1152: genastore_2 (from, mode, reg, size, to, 1, GF_FC);
1153: }
1154:
1155: static void genmovemel (uae_u16 opcode)
1156: {
1157: char getcode[100];
1158: int size = table68k[opcode].size == sz_long ? 4 : 2;
1159:
1160: if (table68k[opcode].size == sz_long) {
1161: sprintf (getcode, "%s (srca)", srcl);
1162: } else {
1163: sprintf (getcode, "(uae_s32)(uae_s16)%s (srca)", srcw);
1164: }
1165: count_read += table68k[opcode].size == sz_long ? 2 : 1;
1166: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1167: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1168: printf ("\tuae_u16 regs_number = 0;\n");
1169: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, 0);
1170: start_brace ();
1171: printf ("\twhile (dmask) { m68k_dreg (regs, movem_index1[dmask]) = %s; srca += %d; dmask = movem_next[dmask]; regs_number++; }\n",
1172: getcode, size);
1173: printf ("\twhile (amask) { m68k_areg (regs, movem_index1[amask]) = %s; srca += %d; amask = movem_next[amask]; regs_number++; }\n",
1174: getcode, size);
1175:
1176: if (table68k[opcode].dmode == Aipi) {
1177: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1178: count_read++;
1179: }
1180: count_ncycles++;
1181:
1182: if (using_ce020 == 2) {
1183: if (table68k[opcode].size == sz_long)
1184: printf ("\tregs.ce030_instr_addcycles = regs_number * 8;\n");
1185: else
1186: printf ("\tregs.ce030_instr_addcycles = regs_number * 4;\n");
1187: }
1188:
1189: fill_prefetch_next ();
1190: }
1191:
1192: static void genmovemel_ce (uae_u16 opcode)
1193: {
1194: int size = table68k[opcode].size == sz_long ? 4 : 2;
1195: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1196: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1197: printf ("\tuae_u32 v;\n");
1198: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA);
1199: if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
1200: addcycles000 (2);
1201: start_brace ();
1202: if (table68k[opcode].size == sz_long) {
1203: printf ("\twhile (dmask) { v = get_word_ce(srca) << 16; v |= get_word_ce(srca + 2); m68k_dreg (regs, movem_index1[dmask]) = v; srca += %d; dmask = movem_next[dmask]; }\n",
1204: size);
1205: printf ("\twhile (amask) { v = get_word_ce(srca) << 16; v |= get_word_ce(srca + 2); m68k_areg (regs, movem_index1[amask]) = v; srca += %d; amask = movem_next[amask]; }\n",
1206: size);
1207: } else {
1208: printf ("\twhile (dmask) { m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_ce(srca); srca += %d; dmask = movem_next[dmask]; }\n",
1209: size);
1210: printf ("\twhile (amask) { m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_ce(srca); srca += %d; amask = movem_next[amask]; }\n",
1211: size);
1212: }
1213: printf ("\tget_word_ce (srca);\n"); // and final extra word fetch that goes nowhere..
1214: count_read++;
1215: if (table68k[opcode].dmode == Aipi)
1216: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1217:
1218: count_ncycles++;
1219: fill_prefetch_next ();
1220: }
1221:
1222: static void genmovemle (uae_u16 opcode)
1223: {
1224: char putcode[100];
1225: int size = table68k[opcode].size == sz_long ? 4 : 2;
1226:
1227: if (table68k[opcode].size == sz_long) {
1228: sprintf (putcode, "%s (srca", dstl);
1229: } else {
1230: sprintf (putcode, "%s (srca", dstw);
1231: }
1232: count_write += table68k[opcode].size == sz_long ? 2 : 1;
1233:
1234: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1235: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, 0);
1236: start_brace ();
1237: printf ("\tuae_u16 regs_number = 0;\n");
1238: if (table68k[opcode].dmode == Apdi) {
1239: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
1240: if (!using_mmu)
1241: printf ("\tint type = get_cpu_model() >= 68020;\n");
1242: printf ("\twhile (amask) {\n");
1243: printf ("\t\tsrca -= %d;\n", size);
1244: if (!using_mmu)
1245: printf ("\t\tif (type) m68k_areg (regs, dstreg) = srca;\n");
1246: printf ("\t\t%s, m68k_areg (regs, movem_index2[amask]));\n", putcode);
1247: printf ("\t\tamask = movem_next[amask];\n");
1248: printf ("\t\tregs_number++;\n");
1249: printf ("\t}\n");
1250: printf ("\twhile (dmask) { srca -= %d; %s, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; regs_number++; }\n",
1251: size, putcode);
1252: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1253: } else {
1254: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1255: printf ("\twhile (dmask) { %s, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; regs_number++; }\n",
1256: putcode, size);
1257: printf ("\twhile (amask) { %s, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; regs_number++; }\n",
1258: putcode, size);
1259: }
1260:
1261: count_ncycles++;
1262: if (using_ce020 == 2) {
1263: if (table68k[opcode].size == sz_long)
1264: printf ("\tregs.ce030_instr_addcycles = regs_number * 8;\n");
1265: else
1266: printf ("\tregs.ce030_instr_addcycles = regs_number * 4;\n");
1267: }
1268: fill_prefetch_next ();
1269: }
1270:
1271: static void genmovemle_ce (uae_u16 opcode)
1272: {
1273: int size = table68k[opcode].size == sz_long ? 4 : 2;
1274: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1275: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA);
1276:
1277: if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r) {
1278: addcycles000 (2);
1279: }
1280: start_brace ();
1281: if (table68k[opcode].size == sz_long) {
1282: if (table68k[opcode].dmode == Apdi) {
1283: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
1284: printf ("\twhile (amask) { srca -= %d; put_word_ce (srca, m68k_areg (regs, movem_index2[amask]) >> 16); put_word_ce (srca + 2, m68k_areg (regs, movem_index2[amask])); amask = movem_next[amask]; }\n",
1285: size);
1286: printf ("\twhile (dmask) { srca -= %d; put_word_ce (srca, m68k_dreg (regs, movem_index2[dmask]) >> 16); put_word_ce (srca + 2, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask];}\n",
1287: size);
1288: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1289: } else {
1290: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1291: printf ("\twhile (dmask) { put_word_ce (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16); put_word_ce (srca + 2, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
1292: size);
1293: printf ("\twhile (amask) { put_word_ce (srca, m68k_areg (regs, movem_index1[amask]) >> 16); put_word_ce (srca + 2, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask];}\n",
1294: size);
1295: }
1296: } else {
1297: if (table68k[opcode].dmode == Apdi) {
1298: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
1299: printf ("\twhile (amask) { srca -= %d; put_word_ce (srca, m68k_areg (regs, movem_index2[amask])); amask = movem_next[amask]; }\n",
1300: size);
1301: printf ("\twhile (dmask) { srca -= %d; put_word_ce (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }\n",
1302: size);
1303: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1304: } else {
1305: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1306: printf ("\twhile (dmask) { put_word_ce (srca, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
1307: size);
1308: printf ("\twhile (amask) { put_word_ce (srca, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; }\n",
1309: size);
1310: }
1311: }
1312:
1313: count_ncycles++;
1314: fill_prefetch_next ();
1315: }
1316:
1317: static void duplicate_carry (int n)
1318: {
1319: int i;
1320: for (i = 0; i <= n; i++)
1321: printf ("\t");
1322: printf ("COPY_CARRY ();\n");
1323: }
1324:
1325: typedef enum
1326: {
1327: flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_z, flag_zn,
1328: flag_av, flag_sv
1329: }
1330: flagtypes;
1331:
1332: static void genflags_normal (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
1333: {
1334: char vstr[100], sstr[100], dstr[100];
1335: char usstr[100], udstr[100];
1336: char unsstr[100], undstr[100];
1337:
1338: switch (size) {
1339: case sz_byte:
1340: strcpy (vstr, "((uae_s8)(");
1341: strcpy (usstr, "((uae_u8)(");
1342: break;
1343: case sz_word:
1344: strcpy (vstr, "((uae_s16)(");
1345: strcpy (usstr, "((uae_u16)(");
1346: break;
1347: case sz_long:
1348: strcpy (vstr, "((uae_s32)(");
1349: strcpy (usstr, "((uae_u32)(");
1350: break;
1351: default:
1352: abort ();
1353: }
1354: strcpy (unsstr, usstr);
1355:
1356: strcpy (sstr, vstr);
1357: strcpy (dstr, vstr);
1358: strcat (vstr, value);
1359: strcat (vstr, "))");
1360: strcat (dstr, dst);
1361: strcat (dstr, "))");
1362: strcat (sstr, src);
1363: strcat (sstr, "))");
1364:
1365: strcpy (udstr, usstr);
1366: strcat (udstr, dst);
1367: strcat (udstr, "))");
1368: strcat (usstr, src);
1369: strcat (usstr, "))");
1370:
1371: strcpy (undstr, unsstr);
1372: strcat (unsstr, "-");
1373: strcat (undstr, "~");
1374: strcat (undstr, dst);
1375: strcat (undstr, "))");
1376: strcat (unsstr, src);
1377: strcat (unsstr, "))");
1378:
1379: switch (type) {
1380: case flag_logical_noclobber:
1381: case flag_logical:
1382: case flag_z:
1383: case flag_zn:
1384: case flag_av:
1385: case flag_sv:
1386: case flag_addx:
1387: case flag_subx:
1388: break;
1389:
1390: case flag_add:
1391: start_brace ();
1392: printf ("uae_u32 %s = %s + %s;\n", value, dstr, sstr);
1393: break;
1394: case flag_sub:
1395: case flag_cmp:
1396: start_brace ();
1397: printf ("uae_u32 %s = %s - %s;\n", value, dstr, sstr);
1398: break;
1399: }
1400:
1401: switch ((int)type) {
1402: case flag_logical_noclobber:
1403: case flag_logical:
1404: case flag_zn:
1405: break;
1406:
1407: case flag_add:
1408: case flag_sub:
1409: case flag_addx:
1410: case flag_subx:
1411: case flag_cmp:
1412: case flag_av:
1413: case flag_sv:
1414: start_brace ();
1415: printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
1416: printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
1417: printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
1418: break;
1419: }
1420:
1421: switch (type) {
1422: case flag_logical:
1423: printf ("\tCLEAR_CZNV ();\n");
1424: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1425: printf ("\tSET_NFLG (%s < 0);\n", vstr);
1426: break;
1427: case flag_logical_noclobber:
1428: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1429: printf ("\tSET_NFLG (%s < 0);\n", vstr);
1430: break;
1431: case flag_av:
1432: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
1433: break;
1434: case flag_sv:
1435: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
1436: break;
1437: case flag_z:
1438: printf ("\tSET_ZFLG (GET_ZFLG () & (%s == 0));\n", vstr);
1439: break;
1440: case flag_zn:
1441: printf ("\tSET_ZFLG (GET_ZFLG () & (%s == 0));\n", vstr);
1442: printf ("\tSET_NFLG (%s < 0);\n", vstr);
1443: break;
1444: case flag_add:
1445: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1446: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
1447: printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
1448: duplicate_carry (0);
1449: printf ("\tSET_NFLG (flgn != 0);\n");
1450: break;
1451: case flag_sub:
1452: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1453: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
1454: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
1455: duplicate_carry (0);
1456: printf ("\tSET_NFLG (flgn != 0);\n");
1457: break;
1458: case flag_addx:
1459: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
1460: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
1461: duplicate_carry (0);
1462: break;
1463: case flag_subx:
1464: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
1465: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
1466: duplicate_carry (0);
1467: break;
1468: case flag_cmp:
1469: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1470: printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
1471: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
1472: printf ("\tSET_NFLG (flgn != 0);\n");
1473: break;
1474: }
1475: }
1476:
1477: static void genflags (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
1478: {
1479: /* Temporarily deleted 68k/ARM flag optimizations. I'd prefer to have
1480: them in the appropriate m68k.h files and use just one copy of this
1481: code here. The API can be changed if necessary. */
1482: if (optimized_flags) {
1483: switch (type) {
1484: case flag_add:
1485: case flag_sub:
1486: start_brace ();
1487: printf ("\tuae_u32 %s;\n", value);
1488: break;
1489:
1490: default:
1491: break;
1492: }
1493:
1494: /* At least some of those casts are fairly important! */
1495: switch (type) {
1496: case flag_logical_noclobber:
1497: printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
1498: if (strcmp (value, "0") == 0) {
1499: printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
1500: } else {
1501: switch (size) {
1502: case sz_byte: printf ("\toptflag_testb (regs, (uae_s8)(%s));\n", value); break;
1503: case sz_word: printf ("\toptflag_testw (regs, (uae_s16)(%s));\n", value); break;
1504: case sz_long: printf ("\toptflag_testl (regs, (uae_s32)(%s));\n", value); break;
1505: }
1506: printf ("\tIOR_CZNV (oldcznv);\n");
1507: }
1508: printf ("\t}\n");
1509: return;
1510: case flag_logical:
1511: if (strcmp (value, "0") == 0) {
1512: printf ("\tSET_CZNV (FLAGVAL_Z);\n");
1513: } else {
1514: switch (size) {
1515: case sz_byte: printf ("\toptflag_testb (regs, (uae_s8)(%s));\n", value); break;
1516: case sz_word: printf ("\toptflag_testw (regs, (uae_s16)(%s));\n", value); break;
1517: case sz_long: printf ("\toptflag_testl (regs, (uae_s32)(%s));\n", value); break;
1518: }
1519: }
1520: return;
1521:
1522: case flag_add:
1523: switch (size) {
1524: case sz_byte: printf ("\toptflag_addb (regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
1525: case sz_word: printf ("\toptflag_addw (regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
1526: case sz_long: printf ("\toptflag_addl (regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
1527: }
1528: return;
1529:
1530: case flag_sub:
1531: switch (size) {
1532: case sz_byte: printf ("\toptflag_subb (regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
1533: case sz_word: printf ("\toptflag_subw (regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
1534: case sz_long: printf ("\toptflag_subl (regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
1535: }
1536: return;
1537:
1538: case flag_cmp:
1539: switch (size) {
1540: case sz_byte: printf ("\toptflag_cmpb (regs, (uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
1541: case sz_word: printf ("\toptflag_cmpw (regs, (uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
1542: case sz_long: printf ("\toptflag_cmpl (regs, (uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
1543: }
1544: return;
1545:
1546: default:
1547: break;
1548: }
1549: }
1550:
1551: genflags_normal (type, size, value, src, dst);
1552: }
1553:
1554: static void force_range_for_rox (const char *var, wordsizes size)
1555: {
1556: /* Could do a modulo operation here... which one is faster? */
1557: switch (size) {
1558: case sz_long:
1559: printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
1560: break;
1561: case sz_word:
1562: printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
1563: printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
1564: break;
1565: case sz_byte:
1566: printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
1567: printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
1568: printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
1569: break;
1570: }
1571: }
1572:
1573: static const char *cmask (wordsizes size)
1574: {
1575: switch (size) {
1576: case sz_byte: return "0x80";
1577: case sz_word: return "0x8000";
1578: case sz_long: return "0x80000000";
1579: default: abort ();
1580: }
1581: }
1582:
1583: static int source_is_imm1_8 (struct instr *i)
1584: {
1585: return i->stype == 3;
1586: }
1587:
1588: static void shift_ce (amodes dmode, int size)
1589: {
1590: if (using_ce && isreg (dmode)) {
1591: int c = size == sz_long ? 4 : 2;
1592: printf ("\t{\n");
1593: printf ("\t\tint cycles = %d;\n", c);
1594: printf ("\t\tcycles += 2 * ccnt;\n");
1595: addcycles000_3 ("\t\t");
1596: printf ("\t}\n");
1597: count_cycles += c;
1598: }
1599: }
1600:
1601: // BCHG/BSET/BCLR Dx,Dx or #xx,Dx adds 2 cycles if bit number > 15
1602: static void bsetcycles (struct instr *curi)
1603: {
1604: if (curi->size == sz_byte) {
1605: printf ("\tsrc &= 7;\n");
1606: } else {
1607: printf ("\tsrc &= 31;\n");
1608: if (isreg (curi->dmode)) {
1609: addcycles000 (2);
1610: if (curi->mnemo != i_BTST && using_ce) {
1611: printf ("\tif (src > 15) do_cycles_ce000 (2);\n");
1612: count_ncycles++;
1613: }
1614: }
1615: }
1616: }
1617:
1618: static int islongimm (struct instr *curi)
1619: {
1620: return (curi->size == sz_long && (curi->smode == Dreg || curi->smode == imm));
1621: }
1622:
1623: static void gen_opcode (unsigned long int opcode)
1624: {
1625: struct instr *curi = table68k + opcode;
1626:
1627: insn_n_cycles = using_prefetch ? 0 : 4;
1628:
1.1.1.5 ! root 1629: /* Store the family of the instruction (used to check for pairing on ST,
! 1630: * for non-CPU cycles calculation and profiling)
! 1631: */
! 1632: printf ("\tOpcodeFamily = %d;\n", curi->mnemo);
! 1633: /* leave some space for patching in the current cycles later */
1.1.1.4 root 1634: if (!using_ce020) {
1.1.1.5 ! root 1635: printf("\tCurrentInstrCycles = \n");
1.1.1.4 root 1636: nCurInstrCycPos = ftell(stdout) - 5;
1637: }
1638: else if (using_ce020 == 2) {
1639: /* Initialize the cycle table to the general table by default */
1640: instr_table = TABLE_FALCON_CYCLES;
1641: instr_table_index = instr_index;
1642: no_return_cycles = false;
1643: }
1644:
1645: if (using_ce020) {
1646: if (using_ce020 == 2) {
1647: ce020_prefetch_long = "get_long_ce030_prefetch";
1648: ce020_prefetch_word = "get_word_ce030_prefetch";
1649: srcl = "get_long_ce030";
1650: dstl = "put_long_ce030";
1651: srcw = "get_word_ce030";
1652: dstw = "put_word_ce030";
1653: srcb = "get_byte_ce030";
1654: dstb = "put_byte_ce030";
1655: } else {
1656: ce020_prefetch_long = "get_long_ce020_prefetch";
1657: ce020_prefetch_word = "get_word_ce020_prefetch";
1658: srcl = "get_long_ce020";
1659: dstl = "put_long_ce020";
1660: srcw = "get_word_ce020";
1661: dstw = "put_word_ce020";
1662: srcb = "get_byte_ce020";
1663: dstb = "put_byte_ce020";
1664: }
1.1.1.5 ! root 1665: } else if (using_mmu && cpu_level == 3) {
! 1666: srcl = "get_long_mmu030";
! 1667: dstl = "put_long_mmu030";
! 1668: srcw = "get_word_mmu030";
! 1669: dstw = "put_word_mmu030";
! 1670: srcb = "get_byte_mmu030";
! 1671: dstb = "put_byte_mmu030";
1.1.1.4 root 1672: } else if (using_mmu) {
1673: srcl = "get_long_mmu";
1674: dstl = "put_long_mmu";
1675: srcw = "get_word_mmu";
1676: dstw = "put_word_mmu";
1677: srcb = "get_byte_mmu";
1678: dstb = "put_byte_mmu";
1679: } else if (using_ce) {
1680: srcl = "get_long_ce";
1681: dstl = "put_long_ce";
1682: srcw = "get_word_ce";
1683: dstw = "put_word_ce";
1684: srcb = "get_byte_ce";
1685: dstb = "put_byte_ce";
1686: } else {
1687: srcl = "get_long";
1688: dstl = "put_long";
1689: srcw = "get_word";
1690: dstw = "put_word";
1691: srcb = "get_byte";
1692: dstb = "put_byte";
1693: }
1694:
1695: insn_n_cycles020 = 0;
1696:
1697: start_brace ();
1698: m68k_pc_offset = 2;
1699: switch (curi->plev) {
1700: case 0: /* not privileged */
1701: break;
1702: case 1: /* unprivileged only on 68000 */
1703: if (cpu_level == 0)
1704: break;
1705: if (next_cpu_level < 0)
1706: next_cpu_level = 0;
1707:
1708: /* fall through */
1709: case 2: /* priviledged */
1710: printf ("if (!regs.s) { Exception (8, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1711: need_endlabel = 1;
1712: start_brace ();
1713: break;
1714: case 3: /* privileged if size == word */
1715: if (curi->size == sz_byte)
1716: break;
1717: printf ("if (!regs.s) { Exception (8, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1718: need_endlabel = 1;
1719: start_brace ();
1720: break;
1721: }
1722: switch (curi->mnemo) {
1723: case i_OR:
1724: case i_AND:
1725: case i_EOR:
1726: {
1727: int c = 0;
1728: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1729: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
1730: printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
1731: genflags (flag_logical, curi->size, "src", "", "");
1732: if (curi->dmode == Dreg && curi->size == sz_long) {
1733: c += 2;
1734: if (curi->smode == imm || curi->smode == Dreg)
1735: c += 2;
1736: }
1737: fill_prefetch_next ();
1738: if (c > 0)
1739: addcycles000 (c);
1740: genastore_rev ("src", curi->dmode, "dstreg", curi->size, "dst");
1741: break;
1742: }
1743: // all SR/CCR modifications have dummy read access
1744: case i_ORSR:
1745: case i_EORSR:
1746: printf ("\tMakeSR ();\n");
1747: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1748: dummy_prefetch ();
1749: if (curi->size == sz_byte) {
1750: printf ("\tsrc &= 0xFF;\n");
1751: }
1752: addcycles000 (8);
1753: fill_prefetch_next ();
1754: printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
1755: printf ("\tMakeFromSR ();\n");
1756: break;
1757: case i_ANDSR:
1758: printf ("\tMakeSR ();\n");
1759: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1760: dummy_prefetch ();
1761: if (curi->size == sz_byte) {
1762: printf ("\tsrc |= 0xFF00;\n");
1763: }
1764: addcycles000 (8);
1765: fill_prefetch_next ();
1766: printf ("\tregs.sr &= src;\n");
1767: printf ("\tMakeFromSR ();\n");
1768: break;
1769: case i_SUB:
1770: {
1771: int c = 0;
1772: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1773: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
1774: if (curi->dmode == Dreg) {
1775: if (curi->size == sz_long) {
1776: c += 2;
1777: if (curi->smode == imm || curi->smode == immi || curi->smode == Dreg)
1778: c += 2;
1779: }
1780: }
1781: fill_prefetch_next ();
1782: if (c > 0)
1783: addcycles000 (c);
1784: start_brace ();
1785: genflags (flag_sub, curi->size, "newv", "src", "dst");
1786: genastore_rev ("newv", curi->dmode, "dstreg", curi->size, "dst");
1787: break;
1788: }
1789: case i_SUBA:
1790: {
1791: int c = 0;
1792: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1793: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
1794: if (curi->smode == immi) {
1795: // SUBAQ.x is always 8 cycles
1796: c += 4;
1797: } else {
1798: c = curi->size == sz_long ? 2 : 4;
1799: if (islongimm (curi))
1800: c += 2;
1801: }
1802: fill_prefetch_next ();
1803: if (c > 0)
1804: addcycles000 (c);
1805: start_brace ();
1806: printf ("\tuae_u32 newv = dst - src;\n");
1807: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1808: break;
1809: }
1810: case i_SUBX:
1811: if (!isreg (curi->smode))
1812: addcycles000 (2);
1813: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1814: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1815: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1816: fill_prefetch_next ();
1817: if (curi->size == sz_long && isreg (curi->smode))
1818: addcycles000 (4);
1819: start_brace ();
1820: printf ("\tuae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);\n");
1821: genflags (flag_subx, curi->size, "newv", "src", "dst");
1822: genflags (flag_zn, curi->size, "newv", "", "");
1823: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1824: break;
1825: case i_SBCD:
1826: if (!isreg (curi->smode))
1827: addcycles000 (2);
1828: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1829: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1830: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1831: fill_prefetch_next ();
1832: start_brace ();
1833: printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
1834: printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
1835: printf ("\tuae_u16 newv, tmp_newv;\n");
1836: printf ("\tint bcd = 0;\n");
1837: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
1838: printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
1839: printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
1840: printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);\n");
1841: duplicate_carry (0);
1842: /* Manual says bits NV are undefined though a real 68040/060 don't change them */
1843: if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1844: if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1845: next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1846: genflags (flag_z, curi->size, "newv", "", "");
1847: } else {
1848: genflags (flag_zn, curi->size, "newv", "", "");
1849: printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
1850: }
1851: if (isreg (curi->smode))
1852: addcycles000 (2);
1853: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1854: break;
1855: case i_ADD:
1856: {
1857: int c = 0;
1858: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1859: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
1860: if (curi->dmode == Dreg) {
1861: if (curi->size == sz_long) {
1862: c += 2;
1863: if (curi->smode == imm || curi->smode == immi || curi->smode == Dreg)
1864: c += 2;
1865: }
1866: }
1867: fill_prefetch_next ();
1868: if (c > 0)
1869: addcycles000 (c);
1870: start_brace ();
1871: genflags (flag_add, curi->size, "newv", "src", "dst");
1872: genastore_rev ("newv", curi->dmode, "dstreg", curi->size, "dst");
1873: break;
1874: }
1875: case i_ADDA:
1876: {
1877: int c = 0;
1878: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1879: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
1880: if (curi->smode == immi) {
1881: // ADDAQ.x is always 8 cycles
1882: c += 4;
1883: } else {
1884: c = curi->size == sz_long ? 2 : 4;
1885: if (islongimm (curi))
1886: c += 2;
1887: }
1888: fill_prefetch_next ();
1889: if (c > 0)
1890: addcycles000 (c);
1891: start_brace ();
1892: printf ("\tuae_u32 newv = dst + src;\n");
1893: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1894: break;
1895: }
1896: case i_ADDX:
1897: if (!isreg (curi->smode))
1898: addcycles000 (2);
1899: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1900: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1901: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1902: fill_prefetch_next ();
1903: if (curi->size == sz_long && isreg (curi->smode))
1904: addcycles000 (4);
1905: start_brace ();
1906: printf ("\tuae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);\n");
1907: genflags (flag_addx, curi->size, "newv", "src", "dst");
1908: genflags (flag_zn, curi->size, "newv", "", "");
1909: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1910: break;
1911: case i_ABCD:
1912: if (!isreg (curi->smode))
1913: addcycles000 (2);
1914: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1915: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1916: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1917: fill_prefetch_next ();
1918: start_brace ();
1919: printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);\n");
1920: printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
1921: printf ("\tuae_u16 newv, tmp_newv;\n");
1922: printf ("\tint cflg;\n");
1923: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
1924: printf ("\tif (newv_lo > 9) { newv += 6; }\n");
1925: printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
1926: printf ("\tif (cflg) newv += 0x60;\n");
1927: printf ("\tSET_CFLG (cflg);\n");
1928: duplicate_carry (0);
1929: /* Manual says bits NV are undefined though a real 68040 don't change them */
1930: if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1931: if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1932: next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1933: genflags (flag_z, curi->size, "newv", "", "");
1934: }
1935: else {
1936: genflags (flag_zn, curi->size, "newv", "", "");
1937: printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
1938: }
1939: if (isreg (curi->smode))
1940: addcycles000 (2);
1941: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1942: break;
1943: case i_NEG:
1944: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1945: fill_prefetch_next ();
1946: if (isreg (curi->smode) && curi->size == sz_long)
1947: addcycles000 (2);
1948: start_brace ();
1949: genflags (flag_sub, curi->size, "dst", "src", "0");
1950: genastore_rev ("dst", curi->smode, "srcreg", curi->size, "src");
1951: break;
1952: case i_NEGX:
1953: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1954: fill_prefetch_next ();
1955: if (isreg (curi->smode) && curi->size == sz_long)
1956: addcycles000 (2);
1957: start_brace ();
1958: printf ("\tuae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);\n");
1959: genflags (flag_subx, curi->size, "newv", "src", "0");
1960: genflags (flag_zn, curi->size, "newv", "", "");
1961: genastore_rev ("newv", curi->smode, "srcreg", curi->size, "src");
1962: break;
1963: case i_NBCD:
1964: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1965: if (isreg (curi->smode))
1966: addcycles000 (2);
1967: fill_prefetch_next ();
1968: start_brace ();
1969: printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
1970: printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1971: printf ("\tuae_u16 newv;\n");
1972: printf ("\tint cflg;\n");
1973: printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1974: printf ("\tnewv = newv_hi + newv_lo;");
1975: printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1976: printf ("\tif (cflg) newv -= 0x60;\n");
1977: printf ("\tSET_CFLG (cflg);\n");
1978: duplicate_carry(0);
1979: /* Manual says bits NV are undefined though a real 68040 don't change them */
1980: if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1981: if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1982: next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1983: genflags (flag_z, curi->size, "newv", "", "");
1984: }
1985: else {
1986: genflags (flag_zn, curi->size, "newv", "", "");
1987: }
1988: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1989: break;
1990: case i_CLR:
1991: genamode (curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, 0);
1992: fill_prefetch_next ();
1993: if (isreg (curi->smode) && curi->size == sz_long)
1994: addcycles000 (2);
1995: genflags (flag_logical, curi->size, "0", "", "");
1996: genastore_rev ("0", curi->smode, "srcreg", curi->size, "src");
1997: break;
1998: case i_NOT:
1999: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2000: fill_prefetch_next ();
2001: if (isreg (curi->smode) && curi->size == sz_long)
2002: addcycles000 (2);
2003: start_brace ();
2004: printf ("\tuae_u32 dst = ~src;\n");
2005: genflags (flag_logical, curi->size, "dst", "", "");
2006: genastore_rev ("dst", curi->smode, "srcreg", curi->size, "src");
2007: break;
2008: case i_TST:
2009: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2010: fill_prefetch_next ();
2011: genflags (flag_logical, curi->size, "src", "", "");
2012: break;
2013: case i_BTST:
2014: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2015: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2016: fill_prefetch_next ();
2017: bsetcycles (curi);
2018: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
2019: break;
2020: case i_BCHG:
2021: case i_BCLR:
2022: case i_BSET:
2023: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2024: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2025: fill_prefetch_next ();
2026: bsetcycles (curi);
2027: // bclr needs 1 extra cycle
2028: if (curi->mnemo == i_BCLR && curi->dmode == Dreg)
2029: addcycles000 (2);
2030: if (curi->mnemo == i_BCHG) {
2031: printf ("\tdst ^= (1 << src);\n");
2032: printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
2033: } else if (curi->mnemo == i_BCLR) {
2034: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
2035: printf ("\tdst &= ~(1 << src);\n");
2036: } else if (curi->mnemo == i_BSET) {
2037: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
2038: printf ("\tdst |= (1 << src);\n");
2039: }
2040: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
2041: break;
2042: case i_CMPM:
2043: // confirmed
2044: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
2045: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
2046: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
2047: fill_prefetch_next ();
2048: start_brace ();
2049: genflags (flag_cmp, curi->size, "newv", "src", "dst");
2050: break;
2051: case i_CMP:
2052: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2053: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2054: fill_prefetch_next ();
2055: if (curi->dmode == Dreg && curi->size == sz_long)
2056: addcycles000 (2);
2057: start_brace ();
2058: genflags (flag_cmp, curi->size, "newv", "src", "dst");
2059: break;
2060: case i_CMPA:
2061: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2062: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
2063: fill_prefetch_next ();
2064: addcycles000 (2);
2065: start_brace ();
2066: genflags (flag_cmp, sz_long, "newv", "src", "dst");
2067: break;
2068: /* The next two are coded a little unconventional, but they are doing
2069: * weird things... */
2070: case i_MVPRM: // MOVEP R->M
2071: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2072: printf ("\tuaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
1.1.1.5 ! root 2073: /* [NP] Use MovepByteNbr to keep track of each access inside a movep */
1.1.1.4 root 2074: if (curi->size == sz_word) {
2075: printf ("\tMovepByteNbr=1; %s (memp, src >> 8); MovepByteNbr=2; %s (memp + 2, src);\n", dstb, dstb);
2076: count_write += 2;
2077: } else {
2078: printf ("\tMovepByteNbr=1; %s (memp, src >> 24); MovepByteNbr=2; %s (memp + 2, src >> 16);\n", dstb, dstb);
2079: printf ("\tMovepByteNbr=3; %s (memp + 4, src >> 8); MovepByteNbr=4; %s (memp + 6, src);\n", dstb, dstb);
2080: count_write += 4;
2081: }
1.1.1.5 ! root 2082: printf ("\tMovepByteNbr=0;\n");
1.1.1.4 root 2083: fill_prefetch_next ();
2084: break;
2085: case i_MVPMR: // MOVEP M->R
2086: printf ("\tuaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
2087: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
1.1.1.5 ! root 2088: /* [NP] Use MovepByteNbr to keep track of each access inside a movep */
1.1.1.4 root 2089: if (curi->size == sz_word) {
1.1.1.5 ! root 2090: //printf ("\tuae_u16 val = (%s (memp) << 8) + %s (memp + 2);\n", srcb, srcb);
! 2091: printf ("\tuae_u16 val;\n");
! 2092: printf ("\tMovepByteNbr=1; val = (%s (memp) << 8);\n", srcb);
! 2093: printf ("\tMovepByteNbr=2; val += %s (memp + 2);\n", srcb);
1.1.1.4 root 2094: count_read += 2;
2095: } else {
1.1.1.5 ! root 2096: //printf ("\tuae_u32 val = (%s (memp) << 24) + (%s (memp + 2) << 16)\n", srcb, srcb);
! 2097: //printf (" + (%s (memp + 4) << 8) + %s (memp + 6);\n", srcb, srcb);
! 2098: printf ("\tuae_u32 val;\n");
! 2099: printf ("\tMovepByteNbr=1; val = (%s (memp) << 24);\n", srcb);
! 2100: printf ("\tMovepByteNbr=2; val += (%s (memp + 2) << 16);\n", srcb);
! 2101: printf ("\tMovepByteNbr=2; val += (%s (memp + 4) << 8);\n", srcb);
! 2102: printf ("\tMovepByteNbr=4; val += %s (memp + 6);\n", srcb);
1.1.1.4 root 2103: count_read += 4;
2104: }
1.1.1.5 ! root 2105: printf ("\tMovepByteNbr=0;\n");
1.1.1.4 root 2106: fill_prefetch_next ();
2107: genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
2108: break;
2109: case i_MOVE:
2110: case i_MOVEA:
2111: {
2112: /* 2 MOVE instruction variants have special prefetch sequence:
2113: * - MOVE <ea>,-(An) = prefetch is before writes (Apdi)
2114: * - MOVE memory,(xxx).L = 2 prefetches after write
2115: * - all others = prefetch is done after writes
2116: *
2117: * - move.x xxx,[at least 1 extension word here] = fetch 1 extension word before (xxx)
2118: *
2119: */
2120: int prefetch_done = 0, flags;
2121: int dualprefetch = curi->dmode == absl && (curi->smode != Dreg && curi->smode != Areg && curi->smode != imm);
2122: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_MOVE);
2123: flags = 1 | (dualprefetch ? GF_NOREFILL : 0);
2124: genamode2 (curi->dmode, "dstreg", curi->size, "dst", 2, 0, flags | GF_MOVE, 0);
2125: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2126: if (curi->mnemo == i_MOVEA && curi->size == sz_word)
2127: printf ("\tsrc = (uae_s32)(uae_s16)src;\n");
2128: if (curi->dmode == Apdi) {
2129: fill_prefetch_next ();
2130: prefetch_done = 1;
2131: }
2132: if (curi->mnemo == i_MOVE)
2133: genflags (flag_logical, curi->size, "src", "", "");
2134: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2135: sync_m68k_pc ();
2136: if (dualprefetch) {
2137: fill_prefetch_full ();
2138: prefetch_done = 1;
2139: }
2140: if (!prefetch_done)
2141: fill_prefetch_next ();
2142: }
2143: break;
2144: case i_MVSR2: // MOVE FROM SR
2145: genamode (curi->smode, "srcreg", sz_word, "src", 2, 0, 0);
2146: fill_prefetch_next ();
2147: if (isreg (curi->smode))
2148: addcycles000 (2);
2149: printf ("\tMakeSR ();\n");
2150: if (curi->size == sz_byte)
2151: genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
2152: else
2153: genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
2154: break;
2155: case i_MV2SR: // MOVE TO SR
2156: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2157: if (curi->size == sz_byte) {
2158: // MOVE TO CCR
2159: dummy_prefetch ();
2160: addcycles000 (4);
2161: printf ("\tMakeSR ();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
2162: } else {
2163: // MOVE TO SR
2164: dummy_prefetch ();
2165: addcycles000 (4);
2166: printf ("\tregs.sr = src;\n");
2167: }
2168: printf ("\tMakeFromSR ();\n");
2169: fill_prefetch_next ();
2170: break;
2171: case i_SWAP:
2172: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
2173: fill_prefetch_next ();
2174: start_brace ();
2175: printf ("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
2176: genflags (flag_logical, sz_long, "dst", "", "");
2177: genastore ("dst", curi->smode, "srcreg", sz_long, "src");
2178: break;
2179: case i_EXG:
2180: // confirmed
2181: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2182: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2183: fill_prefetch_next ();
2184: addcycles000 (2);
2185: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
2186: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2187: break;
2188: case i_EXT:
2189: // confirmed
2190: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
2191: fill_prefetch_next ();
2192: start_brace ();
2193: switch (curi->size) {
2194: case sz_byte: printf ("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
2195: case sz_word: printf ("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
2196: case sz_long: printf ("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
2197: default: abort ();
2198: }
2199: genflags (flag_logical,
2200: curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
2201: genastore ("dst", curi->smode, "srcreg",
2202: curi->size == sz_word ? sz_word : sz_long, "src");
2203: break;
2204: case i_MVMEL:
2205: // confirmed
2206: if (using_ce)
2207: genmovemel_ce (opcode);
2208: else
2209: genmovemel (opcode);
2210: break;
2211: case i_MVMLE:
2212: // confirmed
2213: if (using_ce)
2214: genmovemle_ce (opcode);
2215: else
2216: genmovemle (opcode);
2217: break;
2218: case i_TRAP:
2219: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2220: gen_set_fault_pc ();
2221: sync_m68k_pc ();
2222: printf ("\tException (src + 32, 0 ,M68000_EXC_SRC_CPU);\n");
2223: did_prefetch = 1;
2224: m68k_pc_offset = 0;
2225: break;
2226: case i_MVR2USP:
2227: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2228: fill_prefetch_next ();
2229: printf ("\tregs.usp = src;\n");
2230: break;
2231: case i_MVUSP2R:
2232: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0, 0);
2233: fill_prefetch_next ();
2234: genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
2235: break;
2236: case i_RESET:
2237: fill_prefetch_next ();
2238: printf ("\tcpureset ();\n");
2239: addcycles000 (128);
2240: if (using_prefetch)
2241: printf ("\tregs.irc = get_iword (4);\n");
2242: break;
2243: case i_NOP:
2244: fill_prefetch_next ();
2245: break;
2246: case i_STOP:
2247: if (using_prefetch) {
2248: printf ("\tregs.sr = regs.irc;\n");
2249: m68k_pc_offset += 2;
2250: } else {
2251: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2252: printf ("\tregs.sr = src;\n");
2253: }
2254: printf ("\tMakeFromSR ();\n");
2255: printf ("\tm68k_setstopped ();\n");
2256: sync_m68k_pc ();
2257: // STOP does not prefetch anything
2258: did_prefetch = -1;
2259: break;
2260: case i_LPSTOP: /* 68060 */
2261: printf ("\tuae_u16 sw = get_iword (2);\n");
2262: printf ("\tuae_u16 sr;\n");
2263: printf ("\tif (sw != (0x100|0x80|0x40)) { Exception (4, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
2264: printf ("\tsr = get_iword (4);\n");
2265: printf ("\tif (!(sr & 0x8000)) { Exception (8, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
2266: printf ("\tregs.sr = sr;\n");
2267: printf ("\tMakeFromSR ();\n");
2268: printf ("\tm68k_setstopped();\n");
2269: m68k_pc_offset += 4;
2270: sync_m68k_pc ();
2271: fill_prefetch_full ();
2272: break;
2273: case i_RTE:
2274: if (cpu_level == 0) {
2275: genamode (Aipi, "7", sz_word, "sr", 1, 0, GF_NOREFILL);
2276: genamode (Aipi, "7", sz_long, "pc", 1, 0, GF_NOREFILL);
2277: printf ("\tregs.sr = sr;\n");
2278: setpc ("pc");
2279: printf ("\tMakeFromSR ();\n");
2280: } else {
1.1 root 2281: int old_brace_level = n_braces;
2282: if (next_cpu_level < 0)
2283: next_cpu_level = 0;
2284: printf ("\tuae_u16 newsr; uae_u32 newpc;\n");
2285: printf ("\tfor (;;) {\n");
2286: printf ("\t\tuaecptr a = m68k_areg (regs, 7);\n");
1.1.1.5 ! root 2287: printf ("\t\tuae_u16 sr = %s (a);\n", srcw);
! 2288: printf ("\t\tuae_u32 pc = %s (a + 2);\n", srcl);
! 2289: printf ("\t\tuae_u16 format = %s (a + 2 + 4);\n", srcw);
1.1 root 2290: printf ("\t\tint frame = format >> 12;\n");
2291: printf ("\t\tint offset = 8;\n");
2292: printf ("\t\tnewsr = sr; newpc = pc;\n");
2293: printf ("\t\tif (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }\n");
2294: printf ("\t\telse if (frame == 0x1) { m68k_areg (regs, 7) += offset; }\n");
2295: printf ("\t\telse if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }\n");
2296: printf ("\t\telse if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }\n");
2297: if (using_mmu)
1.1.1.5 ! root 2298: printf ("\t\telse if (frame == 0x7) { m68k_do_rte_mmu%s (a); m68k_areg (regs, 7) += offset + 52; break; }\n", mmu_postfix);
1.1 root 2299: printf ("\t\telse if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }\n");
2300: printf ("\t\telse if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }\n");
2301: printf ("\t\telse if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }\n");
2302: printf ("\t\telse if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }\n");
2303: printf ("\t\telse { m68k_areg (regs, 7) += offset; Exception (14, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
2304: printf ("\t\tregs.sr = newsr; MakeFromSR ();\n}\n");
2305: pop_braces (old_brace_level);
2306: printf ("\tregs.sr = newsr; MakeFromSR ();\n");
2307: printf ("\tif (newpc & 1) {\n");
1.1.1.4 root 2308: printf ("\t\texception3i (0x%04lX, m68k_getpc (), newpc);\n", opcode);
1.1 root 2309: printf ("\t\tgoto %s;\n", endlabelstr);
2310: printf ("\t}\n");
2311: printf ("\t\tm68k_setpc (newpc);\n");
2312: printf ("\tipl_fetch ();\n");
2313: need_endlabel = 1;
1.1.1.4 root 2314: }
2315: instr_table = TABLE_FALCON_CYCLES_RTE;
2316: instr_table_index = 0;
2317: /* PC is set and prefetch filled. */
2318: m68k_pc_offset = 0;
2319: fill_prefetch_full ();
2320: break;
2321: case i_RTD:
2322: if (using_mmu) {
2323: genamode (curi->smode, "srcreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2324: genamode (Aipi, "7", sz_long, "pc", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2325: printf ("\tm68k_areg(regs, 7) += offs;\n");
2326: } else {
2327: genamode (Aipi, "7", sz_long, "pc", 1, 0, 0);
2328: genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0, 0);
2329: printf ("\tm68k_areg (regs, 7) += offs;\n");
2330: printf ("\tif (pc & 1) {\n");
2331: printf ("\t\texception3i (0x%04lX, m68k_getpc (), pc);\n", opcode);
1.1 root 2332: printf ("\t\tgoto %s;\n", endlabelstr);
1.1.1.4 root 2333: printf ("\t}\n");
2334: }
1.1 root 2335: printf ("\tif (pc & 1) {\n");
1.1.1.4 root 2336: printf ("\t\texception3i (0x%04lX, m68k_getpc(), pc);\n", opcode);
1.1 root 2337: printf ("\t\tgoto %s;\n", endlabelstr);
2338: printf ("\t}\n");
1.1.1.4 root 2339: setpc ("pc");
2340: /* PC is set and prefetch filled. */
2341: m68k_pc_offset = 0;
2342: fill_prefetch_full ();
1.1 root 2343: need_endlabel = 1;
1.1.1.4 root 2344: break;
2345: case i_LINK:
2346: // ce confirmed
2347: if (using_mmu) {
2348: genamode (curi->dmode, "dstreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2349: genamode (Apdi, "7", sz_long, "old", GENA_GETV_FETCH_ALIGN, GENA_MOVEM_DO_INC, 0);
2350: genamode (curi->smode, "srcreg", sz_long, "src", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2351: genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
2352: printf ("\tm68k_areg(regs, 7) += offs;\n");
2353: genastore ("src", Apdi, "7", sz_long, "old");
2354: } else {
2355: genamode (Apdi, "7", sz_long, "old", 2, 0, GF_AA);
2356: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0, GF_AA);
2357: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0, 0);
2358: genastore ("src", Apdi, "7", sz_long, "old");
2359: genastore ("m68k_areg (regs, 7)", curi->smode, "srcreg", sz_long, "src");
2360: printf ("\tm68k_areg (regs, 7) += offs;\n");
2361: fill_prefetch_next ();
2362: }
2363: break;
2364: case i_UNLK:
2365: // ce confirmed
2366: if (using_mmu) {
2367: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1.1.1.5 ! root 2368: printf ("\tuae_s32 old = get_long_mmu%s (src);\n", mmu_postfix);
1.1 root 2369: printf ("\tm68k_areg (regs, 7) = src + 4;\n");
2370: printf ("\tm68k_areg (regs, srcreg) = old;\n");
1.1.1.4 root 2371: } else {
2372: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2373: printf ("\tm68k_areg (regs, 7) = src;\n");
2374: genamode (Aipi, "7", sz_long, "old", 1, 0, 0);
2375: fill_prefetch_next ();
2376: genastore ("old", curi->smode, "srcreg", curi->size, "src");
2377: }
2378: break;
2379: case i_RTS:
2380: printf ("\tuaecptr pc = m68k_getpc ();\n");
2381: if (using_ce020 == 1)
2382: printf ("\tm68k_do_rts_ce020 ();\n");
2383: else if (using_ce020 == 2)
2384: printf ("\tm68k_do_rts_ce030 ();\n");
2385: else if (using_ce)
2386: printf ("\tm68k_do_rts_ce ();\n");
2387: else if (using_indirect)
2388: printf ("\tm68k_do_rtsi ();\n");
2389: else if (using_mmu)
1.1.1.5 ! root 2390: printf ("\tm68k_do_rts_mmu%s ();\n", mmu_postfix);
1.1.1.4 root 2391: else
2392: printf ("\tm68k_do_rts ();\n");
1.1 root 2393: printf ("\tif (m68k_getpc () & 1) {\n");
2394: printf ("\t\tuaecptr faultpc = m68k_getpc ();\n");
2395: printf ("\t\tm68k_setpc (pc);\n");
1.1.1.4 root 2396: printf ("\t\texception3i (0x%04lX, pc, faultpc);\n", opcode);
1.1 root 2397: printf ("\t\tgoto %s;\n", endlabelstr);
2398: printf ("\t}\n");
1.1.1.4 root 2399: count_read += 2;
2400: m68k_pc_offset = 0;
2401: fill_prefetch_full ();
1.1 root 2402: need_endlabel = 1;
1.1.1.4 root 2403: break;
2404: case i_TRAPV:
2405: sync_m68k_pc ();
2406: fill_prefetch_next ();
2407: printf ("\tif (GET_VFLG ()) {\n");
2408: printf ("\t\tException (7, m68k_getpc () ,M68000_EXC_SRC_CPU);\n");
2409: printf ("\t\tgoto %s;\n", endlabelstr);
2410: printf ("\t}\n");
2411: need_endlabel = 1;
2412: break;
2413: case i_RTR:
2414: printf ("\tMakeSR ();\n");
2415: genamode_pre (Aipi, "7", sz_word, "sr", 1, 0, 0);
2416: genamode (Aipi, "7", sz_long, "pc", 1, 0, 0);
2417: genamode_post (Aipi, "7", sz_word, "sr", 1, 0, 0);
2418: printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
2419: printf ("\tregs.sr |= sr;\n");
2420: setpc ("pc");
2421: printf ("\tMakeFromSR ();\n");
2422: m68k_pc_offset = 0;
2423: fill_prefetch_full ();
2424: break;
2425: case i_JSR: // TODO: check stack write order
2426: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA|GF_NOREFILL);
2427: start_brace ();
2428: printf ("\tuaecptr oldpc = m68k_getpc () + %d;\n", m68k_pc_offset);
2429: if (using_exception_3) {
2430: printf ("\tif (srca & 1) {\n");
2431: printf ("\t\texception3i (opcode, oldpc, srca);\n");
2432: printf ("\t\tgoto %s;\n", endlabelstr);
2433: printf ("\t}\n");
2434: need_endlabel = 1;
2435: }
2436: if (using_mmu) {
2437: printf ("\t%s (m68k_areg (regs, 7) - 4, oldpc);\n", dstl);
2438: printf ("\tm68k_areg (regs, 7) -= 4;\n");
2439: setpc ("srca");
2440: m68k_pc_offset = 0;
2441: } else {
2442: if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16)
2443: addcycles000 (2);
2444: setpc ("srca");
2445: m68k_pc_offset = 0;
2446: fill_prefetch_1 (0);
2447: if (curi->smode == Ad8r || curi->smode == PC8r)
2448: addcycles000 (6);
2449: printf ("\tm68k_areg (regs, 7) -= 4;\n");
2450: if (using_ce) {
2451: printf ("\tput_word_ce (m68k_areg (regs, 7), oldpc >> 16);\n");
2452: printf ("\tput_word_ce (m68k_areg (regs, 7) + 2, oldpc);\n");
2453: } else {
2454: printf ("\t%s (m68k_areg (regs, 7), oldpc);\n", dstl);
2455: }
2456: }
2457: count_write += 2;
2458: fill_prefetch_next ();
2459: break;
2460: case i_JMP:
2461: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA | ((curi->smode == Ad8r || curi->smode == PC8r) ? 0 : GF_NOREFILL));
2462: if (using_exception_3) {
2463: printf ("\tif (srca & 1) {\n");
2464: printf ("\t\texception3i (opcode, m68k_getpc () + 6, srca);\n");
2465: printf ("\t\tgoto %s;\n", endlabelstr);
2466: printf ("\t}\n");
2467: need_endlabel = 1;
2468: }
2469: if (curi->smode == Ad16 || curi->smode == Ad8r || curi->smode == absw || curi->smode == PC16 || curi->smode == PC8r)
2470: addcycles000 (2);
2471: setpc ("srca");
2472: m68k_pc_offset = 0;
2473: fill_prefetch_full ();
2474: break;
2475: case i_BSR:
2476: // .b and .w confirmed
2477: printf ("\tuae_s32 s;\n");
2478: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA|GF_NOREFILL);
2479: printf ("\ts = (uae_s32)src + 2;\n");
2480: if (using_exception_3) {
2481: printf ("\tif (src & 1) {\n");
2482: printf ("\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + s);\n");
2483: printf ("\t\tgoto %s;\n", endlabelstr);
2484: printf ("\t}\n");
2485: need_endlabel = 1;
2486: }
2487: addcycles000 (2);
2488: if (using_ce020 == 1) {
2489: printf ("\tm68k_do_bsr_ce020 (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2490: } else if (using_ce020 == 2) {
2491: printf ("\tm68k_do_bsr_ce030 (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2492: } else if (using_ce) {
2493: printf ("\tm68k_do_bsr_ce (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2494: } else if (using_indirect) {
2495: printf ("\tm68k_do_bsri (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2496: } else if (using_mmu) {
1.1.1.5 ! root 2497: printf ("\tm68k_do_bsr_mmu%s (m68k_getpc () + %d, s);\n", mmu_postfix, m68k_pc_offset);
1.1.1.4 root 2498: } else {
2499: printf ("\tm68k_do_bsr (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2500: }
2501: count_write += 2;
2502: m68k_pc_offset = 0;
2503: fill_prefetch_full ();
2504: break;
2505: case i_Bcc:
2506: // bcc.b branch: idle cycle, prefetch, prefetch
2507: // bcc.b not branch: 2 idle cycles, prefetch
2508:
2509: instr_table = TABLE_FALCON_CYCLES_BCC;
2510:
2511: if (curi->size == sz_long) {
2512: if (cpu_level < 2) {
2513: addcycles000 (2);
2514: printf ("\tif (cctrue (%d)) {\n", curi->cc);
2515: printf ("\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + 1);\n");
2516: printf ("\t\tgoto %s;\n", endlabelstr);
2517: printf ("\t}\n");
2518: sync_m68k_pc ();
2519: irc2ir ();
2520: fill_prefetch_2 ();
2521: printf ("\tgoto %s;\n", endlabelstr);
2522: need_endlabel = 1;
2523: } else {
2524: if (next_cpu_level < 1)
2525: next_cpu_level = 1;
2526: }
2527: }
2528: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_NOREFILL);
2529: addcycles000 (2);
2530: printf ("\tif (!cctrue (%d)) goto didnt_jump;\n", curi->cc);
2531: if (using_exception_3) {
2532: printf ("\tif (src & 1) {\n");
2533: printf ("\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + 2 + (uae_s32)src);\n");
2534: printf ("\t\tgoto %s;\n", endlabelstr);
2535: printf ("\t}\n");
2536: need_endlabel = 1;
2537: }
2538: if (using_prefetch) {
2539: incpc ("(uae_s32)src + 2");
2540: fill_prefetch_full ();
2541: if (using_ce)
2542: printf ("\treturn;\n");
2543: else
2544: printf ("\treturn 10 * CYCLE_UNIT / 2;\n");
2545: } else {
2546: incpc ("(uae_s32)src + 2");
2547: instr_table_index = 0;
2548: returncycles ("", 10);
2549: }
2550: printf ("didnt_jump:;\n");
2551: need_endlabel = 1;
2552: sync_m68k_pc ();
2553: if (curi->size == sz_byte) {
2554: addcycles000 (2);
2555: irc2ir ();
2556: fill_prefetch_2 ();
2557: } else if (curi->size == sz_word) {
2558: addcycles000 (2);
2559: fill_prefetch_full ();
2560: } else {
2561: fill_prefetch_full ();
2562: }
2563: if (using_ce020 == 2) { /* For Falcon cycle exact timings only (CPU_EMU_21) */
2564: if (curi->size == sz_byte)
2565: instr_table_index = 1;
2566: else if (curi->size == sz_word)
2567: instr_table_index = 2;
2568: else
2569: instr_table_index = 3;
2570: }
2571: insn_n_cycles = curi->size == sz_byte ? 8 : 12;
2572: break;
2573: case i_LEA:
2574: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA);
2575: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, GF_AA);
2576: if (curi->smode == Ad8r || curi->smode == PC8r)
2577: addcycles000 (2);
2578: fill_prefetch_next ();
2579: if (curi->smode == Ad8r || curi->smode == PC8r)
2580: addcycles000 (2);
2581: genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
2582: break;
2583: case i_PEA:
2584: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA);
2585: genamode (Apdi, "7", sz_long, "dst", 2, 0, GF_AA);
2586: if (curi->smode == Ad8r || curi->smode == PC8r)
2587: addcycles000 (2);
2588: if (!(curi->smode == absw || curi->smode == absl))
2589: fill_prefetch_next ();
2590: if (curi->smode == Ad8r || curi->smode == PC8r)
2591: addcycles000 (2);
2592: genastore ("srca", Apdi, "7", sz_long, "dst");
2593: if ((curi->smode == absw || curi->smode == absl))
2594: fill_prefetch_next ();
2595: break;
2596: case i_DBcc:
2597: no_return_cycles = true;
2598: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_NOREFILL);
2599: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0, GF_AA | GF_NOREFILL);
2600: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2601: addcycles000 (2);
2602: printf ("\tif (!cctrue (%d)) {\n", curi->cc);
2603: printf ("\t");incpc ("(uae_s32)offs + 2");
2604: fill_prefetch_1 (0);
2605: printf ("\t");genastore ("(src - 1)", curi->smode, "srcreg", curi->size, "src");
2606:
2607: printf ("\t\tif (src) {\n");
2608: if (using_ce020 == 2)
2609: printf ("\t\t\tregs.ce030_instr_cycles = table_falcon_cycles_DBcc[0];\n");
2610:
2611: if (using_exception_3) {
2612: printf ("\t\t\tif (offs & 1) {\n");
2613: printf ("\t\t\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + 2 + (uae_s32)offs + 2);\n");
2614: printf ("\t\t\t\tgoto %s;\n", endlabelstr);
2615: printf ("\t\t\t}\n");
2616: need_endlabel = 1;
2617: }
2618: irc2ir ();
2619: fill_prefetch_1 (2);
2620: returncycles ("\t\t\t", 12);
2621: if (using_ce || using_ce020 == 2)
2622: printf ("\t\t\treturn;\n");
2623: printf ("\t\t}\n");
2624: if (using_ce020 == 2)
2625: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_DBcc[1];\n");
2626: printf ("\t} else {\n");
2627: if (using_ce020 == 2)
2628: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_DBcc[2];\n");
2629:
2630: addcycles000_2 ("\t\t", 2);
2631: printf ("\t}\n");
2632: setpc ("oldpc + %d", m68k_pc_offset);
2633: m68k_pc_offset = 0;
2634: fill_prefetch_full ();
2635: insn_n_cycles = 12;
2636: need_endlabel = 1;
2637: break;
2638: case i_Scc:
2639: // confirmed
2640: genamode (curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, 0);
2641: start_brace ();
2642: fill_prefetch_next();
2643: start_brace ();
2644: printf ("\tint val = cctrue (%d) ? 0xff : 0;\n", curi->cc);
2645: if (using_ce) {
2646: printf ("\tint cycles = 0;\n");
2647: if (isreg (curi->smode))
2648: printf ("\tif (val) cycles += 2;\n");
2649: addcycles000_3 ("\t");
2650: }
2651: genastore ("val", curi->smode, "srcreg", curi->size, "src");
2652: break;
2653: case i_DIVU:
2654: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2655: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2656: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
2657: printf ("\tCLEAR_CZNV ();\n");
2658: printf ("\tif (src == 0) {\n");
2659: if (cpu_level > 0) {
2660: /* 68020 sets V when dividing by zero and N if dst is negative
2661: * 68000 clears both
2662: */
2663: printf("\t\tSET_VFLG (1);\n");
2664: printf("\t\tif (dst < 0) SET_NFLG (1);\n");
2665: }
2666: incpc ("%d", m68k_pc_offset);
2667: printf ("\t\tException (5, oldpc ,M68000_EXC_SRC_CPU);\n");
2668: printf ("\t\tgoto %s;\n", endlabelstr);
2669: printf ("\t} else {\n");
2670: printf ("\t\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
2671: printf ("\t\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
2672: fill_prefetch_next ();
2673: if (using_ce) {
2674: start_brace ();
2675: printf ("\t\tint cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src));\n");
2676: addcycles000_3 ("\t\t");
2677: }
2678: /* The N flag appears to be set each time there is an overflow.
2679: * Weird. but 68020 only sets N when dst is negative.. */
2680: printf ("\t\tif (newv > 0xffff) {\n");
2681: printf ("\t\t\tSET_VFLG (1);\n");
2682: #ifdef UNDEF68020
2683: if (cpu_level >= 2)
2684: printf ("\t\t\tif (currprefs.cpu_level == 0 || dst < 0) SET_NFLG (®s, 1);\n");
2685: else /* ??? some 68000 revisions may not set NFLG when overflow happens.. */
2686: #endif
2687: printf ("\t\t\tSET_NFLG (1);\n");
2688: printf ("\t\t} else {\n");
2689: printf ("\t\t"); genflags (flag_logical, sz_word, "newv", "", "");
2690: printf ("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
2691: printf ("\t\t"); genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2692: printf ("\t\t}\n");
2693: sync_m68k_pc ();
2694: printf ("\t}\n");
2695: count_ncycles++;
2696: insn_n_cycles += 136 - (136 - 76) / 2; /* average */
2697: need_endlabel = 1;
2698: break;
2699: case i_DIVS:
2700: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2701: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2702: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
2703: printf ("\tCLEAR_CZNV ();\n");
2704: printf ("\tif (src == 0) {\n");
2705: if (cpu_level > 0) {
2706: /* 68020 sets V when dividing by zero. Z is also set.
2707: * 68000 clears both
2708: */
2709: printf("\t\tSET_VFLG (1);\n");
2710: printf("\t\tSET_ZFLG (1);\n");
2711: }
2712: incpc ("%d", m68k_pc_offset);
2713: printf ("\t\tException (5, oldpc ,M68000_EXC_SRC_CPU);\n");
2714: printf ("\t\tgoto %s;\n", endlabelstr);
2715: printf ("\t} else {\n");
2716: printf ("\t\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
2717: printf ("\t\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
2718: fill_prefetch_next ();
2719: if (using_ce) {
2720: start_brace ();
2721: printf ("\t\tint cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src));\n");
2722: addcycles000_3 ("\t\t");
2723: }
2724: printf ("\t\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {\n");
2725: printf ("\t\t\tSET_VFLG (1);\n");
2726: #ifdef UNDEF68020
2727: if (cpu_level > 0)
2728: printf ("\t\t\tif (currprefs.cpu_level == 0) SET_NFLG (®s, 1);\n");
2729: else
2730: #endif
2731: printf ("\t\t\tSET_NFLG (1);\n");
2732: printf ("\t\t} else {\n");
2733: printf ("\t\t\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
2734: genflags (flag_logical, sz_word, "newv", "", "");
2735: printf ("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
2736: printf ("\t\t"); genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2737: printf ("\t\t}\n");
2738: sync_m68k_pc ();
2739: printf ("\t}\n");
2740: count_ncycles++;
2741: insn_n_cycles += 156 - (156 - 120) / 2; /* average */
2742: need_endlabel = 1;
2743: break;
2744: case i_MULU:
2745: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2746: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0, 0);
2747: fill_prefetch_next();
2748: start_brace ();
2749: printf ("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
2750: if (using_ce)
2751: printf ("\tint cycles = 38 - 4, bits;\n");
2752: genflags (flag_logical, sz_long, "newv", "", "");
2753: if (using_ce) {
2754: printf ("\tfor(bits = 0; bits < 16 && src; bits++, src >>= 1)\n");
2755: printf ("\t\tif (src & 1) cycles += 2;\n");
2756: addcycles000_3 ("\t");
2757: }
2758: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2759: sync_m68k_pc ();
2760: count_cycles += 38 - 4;
2761: count_ncycles++;
2762: insn_n_cycles += (70 - 38) / 2 + 38; /* average */
2763: break;
2764: case i_MULS:
2765: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2766: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0, 0);
2767: fill_prefetch_next();
2768: start_brace ();
2769: printf ("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
2770: if (using_ce) {
2771: printf ("\tint cycles = 38 - 4, bits;\n");
2772: printf ("\tuae_u32 usrc;\n");
2773: }
2774: genflags (flag_logical, sz_long, "newv", "", "");
2775: if (using_ce) {
2776: printf ("\tusrc = ((uae_u32)src) << 1;\n");
2777: printf ("\tfor(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)\n");
2778: printf ("\t\tif ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;\n");
2779: addcycles000_3 ("\t");
2780: }
2781: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2782: count_cycles += 38 - 4;
2783: count_ncycles++;
2784: insn_n_cycles += (70 - 38) / 2 + 38; /* average */
2785: break;
2786: case i_CHK:
2787: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2788: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2789: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2790: sync_m68k_pc ();
2791: addcycles000 (4);
2792: printf ("\tif (dst > src) {\n");
2793: printf ("\t\tSET_NFLG (0);\n");
2794: printf ("\t\tException (6, oldpc ,M68000_EXC_SRC_CPU);\n");
2795: printf ("\t\tgoto %s;\n", endlabelstr);
2796: printf ("\t}\n");
2797: addcycles000 (2);
2798: printf ("\tif ((uae_s32)dst < 0) {\n");
2799: printf ("\t\tSET_NFLG (1);\n");
2800: printf ("\t\tException (6, oldpc ,M68000_EXC_SRC_CPU);\n");
2801: printf ("\t\tgoto %s;\n", endlabelstr);
2802: printf ("\t}\n");
2803: fill_prefetch_next ();
2804: need_endlabel = 1;
2805: break;
2806: case i_CHK2:
2807: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2808: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
2809: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
2810: fill_prefetch_0 ();
2811: printf ("\t{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
2812: switch (curi->size) {
2813: case sz_byte:
2814: printf ("\tlower = (uae_s32)(uae_s8)%s (dsta); upper = (uae_s32)(uae_s8)%s (dsta + 1);\n", srcb, srcb);
2815: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
2816: if (using_ce020 == 2) {
2817: instr_table = TABLE_FALCON_CYCLES_CHK2_BW;
2818: instr_table_index = chk2_b_index * 2;
2819: chk2_b_index ++;
2820: }
2821: break;
2822: case sz_word:
2823: printf ("\tlower = (uae_s32)(uae_s16)%s (dsta); upper = (uae_s32)(uae_s16)%s (dsta + 2);\n", srcw, srcw);
2824: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
2825: if (using_ce020 == 2) {
2826: instr_table = TABLE_FALCON_CYCLES_CHK2_BW;
2827: instr_table_index = chk2_w_index * 2;
2828: chk2_w_index ++;
2829: }
2830: break;
2831: case sz_long:
2832: printf ("\tlower = %s (dsta); upper = %s (dsta + 4);\n", srcl, srcl);
2833: if (using_ce020 == 2) {
2834: instr_table = TABLE_FALCON_CYCLES_CHK2_L;
2835: instr_table_index = chk2_l_index * 2;
2836: chk2_l_index ++;
2837: }
2838: break;
2839: default:
2840: abort ();
2841: }
2842: printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
2843: printf ("\tSET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
2844: printf ("\tif ((extra & 0x800) && GET_CFLG ()) {\n");
2845: printf ("\t\tException (6, oldpc ,M68000_EXC_SRC_CPU);\n");
2846: instr_table_index ++; /* take the Exception cycle value in the CHK2 table */
2847: returncycles ("\t", 0);
2848: printf ("\t}\n}\n");
2849: instr_table_index --; /* take the No Exception cycle value in the CHK2 table */
2850: break;
2851:
2852: case i_ASR:
2853: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2854: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2855: fill_prefetch_next();
2856: start_brace ();
2857: switch (curi->size) {
2858: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2859: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2860: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2861: default: abort ();
2862: }
2863: printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
2864: printf ("\tint ccnt = cnt & 63;\n");
2865: printf ("\tcnt &= 63;\n");
2866: printf ("\tCLEAR_CZNV ();\n");
2867: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2868: printf ("\t\tval = %s & (uae_u32)-sign;\n", bit_mask (curi->size));
2869: printf ("\t\tSET_CFLG (sign);\n");
2870: duplicate_carry (1);
2871: if (source_is_imm1_8 (curi))
2872: printf ("\t} else {\n");
2873: else {
2874: if (using_ce020 == 2){
2875: no_return_cycles = true;
2876: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_ASR[1];\n");
2877: }
2878: printf ("\t} else if (cnt > 0) {\n");
2879: if (using_ce020 == 2)
2880: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_ASR[0];\n");
2881: }
2882: printf ("\t\tval >>= cnt - 1;\n");
2883: printf ("\t\tSET_CFLG (val & 1);\n");
2884: duplicate_carry (1);
2885: printf ("\t\tval >>= 1;\n");
2886: printf ("\t\tval |= (%s << (%d - cnt)) & (uae_u32)-sign;\n",
2887: bit_mask (curi->size),
2888: bit_size (curi->size));
2889: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
2890: printf ("\t}\n");
2891: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2892: shift_ce (curi->dmode, curi->size);
2893: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2894: break;
2895: case i_ASL:
2896: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2897: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2898: fill_prefetch_next();
2899: start_brace ();
2900: switch (curi->size) {
2901: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2902: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2903: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2904: default: abort ();
2905: }
2906: printf ("\tint ccnt = cnt & 63;\n");
2907: printf ("\tcnt &= 63;\n");
2908: printf ("\tCLEAR_CZNV ();\n");
2909: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2910: printf ("\t\tSET_VFLG (val != 0);\n");
2911: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
2912: bit_size (curi->size));
2913: duplicate_carry (1);
2914: printf ("\t\tval = 0;\n");
2915: if (source_is_imm1_8 (curi))
2916: printf ("\t} else {\n");
2917: else
2918: printf ("\t} else if (cnt > 0) {\n");
2919: printf ("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
2920: bit_mask (curi->size),
2921: bit_size (curi->size) - 1,
2922: bit_mask (curi->size));
2923: printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
2924: printf ("\t\tval <<= cnt - 1;\n");
2925: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
2926: duplicate_carry (1);
2927: printf ("\t\tval <<= 1;\n");
2928: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
2929: printf ("\t}\n");
2930: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2931: shift_ce (curi->dmode, curi->size);
2932: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2933: break;
2934: case i_LSR:
2935: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2936: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2937: fill_prefetch_next();
2938: start_brace ();
2939: switch (curi->size) {
2940: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2941: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2942: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2943: default: abort ();
2944: }
2945: printf ("\tint ccnt = cnt & 63;\n");
2946: printf ("\tcnt &= 63;\n");
2947: printf ("\tCLEAR_CZNV ();\n");
2948: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2949: printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
2950: bit_size (curi->size), bit_size (curi->size) - 1);
2951: duplicate_carry (1);
2952: printf ("\t\tval = 0;\n");
2953: if (source_is_imm1_8 (curi))
2954: printf ("\t} else {\n");
2955: else {
2956: if (using_ce020 == 2){
2957: no_return_cycles = true;
2958: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_LSD[1];\n");
2959: }
2960: printf ("\t} else if (cnt > 0) {\n");
2961: if (using_ce020 == 2)
2962: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_LSD[0];\n");
2963: }
2964: printf ("\t\tval >>= cnt - 1;\n");
2965: printf ("\t\tSET_CFLG (val & 1);\n");
2966: duplicate_carry (1);
2967: printf ("\t\tval >>= 1;\n");
2968: printf ("\t}\n");
2969: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2970: shift_ce (curi->dmode, curi->size);
2971: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2972: break;
2973: case i_LSL:
2974: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2975: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2976: fill_prefetch_next();
2977: start_brace ();
2978: switch (curi->size) {
2979: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2980: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2981: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2982: default: abort ();
2983: }
2984: printf ("\tint ccnt = cnt & 63;\n");
2985: printf ("\tcnt &= 63;\n");
2986: printf ("\tCLEAR_CZNV ();\n");
2987: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2988: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n", bit_size (curi->size));
2989: duplicate_carry (1);
2990: printf ("\t\tval = 0;\n");
2991: if (source_is_imm1_8 (curi))
2992: printf ("\t} else {\n");
2993: else {
2994: if (using_ce020 == 2){
2995: no_return_cycles = true;
2996: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_LSD[1];\n");
2997: }
2998: printf ("\t} else if (cnt > 0) {\n");
2999: if (using_ce020 == 2)
3000: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_LSD[0];\n");
3001: }
3002: printf ("\t\tval <<= (cnt - 1);\n");
3003: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
3004: duplicate_carry (1);
3005: printf ("\t\tval <<= 1;\n");
3006: printf ("\tval &= %s;\n", bit_mask (curi->size));
3007: printf ("\t}\n");
3008: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3009: shift_ce (curi->dmode, curi->size);
3010: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3011: break;
3012: case i_ROL:
3013: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3014: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3015: fill_prefetch_next ();
3016: start_brace ();
3017: switch (curi->size) {
3018: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3019: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3020: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3021: default: abort ();
3022: }
3023: printf ("\tint ccnt = cnt & 63;\n");
3024: printf ("\tcnt &= 63;\n");
3025: printf ("\tCLEAR_CZNV ();\n");
3026: if (source_is_imm1_8 (curi))
3027: printf ("{");
3028: else
3029: printf ("\tif (cnt > 0) {\n");
3030: printf ("\tuae_u32 loval;\n");
3031: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
3032: printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
3033: printf ("\tval <<= cnt;\n");
3034: printf ("\tval |= loval;\n");
3035: printf ("\tval &= %s;\n", bit_mask (curi->size));
3036: printf ("\tSET_CFLG (val & 1);\n");
3037: printf ("}\n");
3038: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3039: shift_ce (curi->dmode, curi->size);
3040: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3041: break;
3042: case i_ROR:
3043: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3044: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3045: fill_prefetch_next ();
3046: start_brace ();
3047: switch (curi->size) {
3048: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3049: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3050: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3051: default: abort ();
3052: }
3053: printf ("\tint ccnt = cnt & 63;\n");
3054: printf ("\tcnt &= 63;\n");
3055: printf ("\tCLEAR_CZNV ();\n");
3056: if (source_is_imm1_8 (curi))
3057: printf ("{");
3058: else
3059: printf ("\tif (cnt > 0) {");
3060: printf ("\tuae_u32 hival;\n");
3061: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
3062: printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
3063: printf ("\tval >>= cnt;\n");
3064: printf ("\tval |= hival;\n");
3065: printf ("\tval &= %s;\n", bit_mask (curi->size));
3066: printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
3067: printf ("\t}\n");
3068: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3069: shift_ce (curi->dmode, curi->size);
3070: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3071: break;
3072: case i_ROXL:
3073: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3074: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3075: fill_prefetch_next ();
3076: start_brace ();
3077: switch (curi->size) {
3078: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3079: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3080: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3081: default: abort ();
3082: }
3083: printf ("\tint ccnt = cnt & 63;\n");
3084: printf ("\tcnt &= 63;\n");
3085: printf ("\tCLEAR_CZNV ();\n");
3086: if (source_is_imm1_8 (curi))
3087: printf ("{");
3088: else {
3089: force_range_for_rox ("cnt", curi->size);
3090: printf ("\tif (cnt > 0) {\n");
3091: }
3092: printf ("\tcnt--;\n");
3093: printf ("\t{\n\tuae_u32 carry;\n");
3094: printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
3095: printf ("\tcarry = loval & 1;\n");
3096: printf ("\tval = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);\n");
3097: printf ("\tSET_XFLG (carry);\n");
3098: printf ("\tval &= %s;\n", bit_mask (curi->size));
3099: printf ("\t} }\n");
3100: printf ("\tSET_CFLG (GET_XFLG ());\n");
3101: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3102: shift_ce (curi->dmode, curi->size);
3103: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3104: break;
3105: case i_ROXR:
3106: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3107: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3108: fill_prefetch_next ();
3109: start_brace ();
3110: switch (curi->size) {
3111: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3112: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3113: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3114: default: abort ();
3115: }
3116: printf ("\tint ccnt = cnt & 63;\n");
3117: printf ("\tcnt &= 63;\n");
3118: printf ("\tCLEAR_CZNV ();\n");
3119: if (source_is_imm1_8 (curi))
3120: printf ("{");
3121: else {
3122: force_range_for_rox ("cnt", curi->size);
3123: printf ("\tif (cnt > 0) {\n");
3124: }
3125: printf ("\tcnt--;\n");
3126: printf ("\t{\n\tuae_u32 carry;\n");
3127: printf ("\tuae_u32 hival = (val << 1) | GET_XFLG ();\n");
3128: printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
3129: printf ("\tval >>= cnt;\n");
3130: printf ("\tcarry = val & 1;\n");
3131: printf ("\tval >>= 1;\n");
3132: printf ("\tval |= hival;\n");
3133: printf ("\tSET_XFLG (carry);\n");
3134: printf ("\tval &= %s;\n", bit_mask (curi->size));
3135: printf ("\t} }\n");
3136: printf ("\tSET_CFLG (GET_XFLG ());\n");
3137: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3138: shift_ce (curi->dmode, curi->size);
3139: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3140: break;
3141: case i_ASRW:
3142: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3143: fill_prefetch_next ();
3144: start_brace ();
3145: switch (curi->size) {
3146: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3147: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3148: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3149: default: abort ();
3150: }
3151: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
3152: printf ("\tuae_u32 cflg = val & 1;\n");
3153: printf ("\tval = (val >> 1) | sign;\n");
3154: genflags (flag_logical, curi->size, "val", "", "");
3155: printf ("\tSET_CFLG (cflg);\n");
3156: duplicate_carry (0);
3157: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3158: break;
3159: case i_ASLW:
3160: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3161: fill_prefetch_next ();
3162: start_brace ();
3163: switch (curi->size) {
3164: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3165: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3166: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3167: default: abort ();
3168: }
3169: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
3170: printf ("\tuae_u32 sign2;\n");
3171: printf ("\tval <<= 1;\n");
3172: genflags (flag_logical, curi->size, "val", "", "");
3173: printf ("\tsign2 = %s & val;\n", cmask (curi->size));
3174: printf ("\tSET_CFLG (sign != 0);\n");
3175: duplicate_carry (0);
3176:
3177: printf ("\tSET_VFLG (GET_VFLG () | (sign2 != sign));\n");
3178: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3179: break;
3180: case i_LSRW:
3181: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3182: fill_prefetch_next ();
3183: start_brace ();
3184: switch (curi->size) {
3185: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3186: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3187: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3188: default: abort ();
3189: }
3190: printf ("\tuae_u32 carry = val & 1;\n");
3191: printf ("\tval >>= 1;\n");
3192: genflags (flag_logical, curi->size, "val", "", "");
3193: printf ("\tSET_CFLG (carry);\n");
3194: duplicate_carry (0);
3195: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3196: break;
3197: case i_LSLW:
3198: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3199: fill_prefetch_next ();
3200: start_brace ();
3201: switch (curi->size) {
3202: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3203: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3204: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3205: default: abort ();
3206: }
3207: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
3208: printf ("\tval <<= 1;\n");
3209: genflags (flag_logical, curi->size, "val", "", "");
3210: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
3211: duplicate_carry (0);
3212: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3213: break;
3214: case i_ROLW:
3215: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3216: fill_prefetch_next ();
3217: start_brace ();
3218: switch (curi->size) {
3219: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3220: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3221: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3222: default: abort ();
3223: }
3224: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
3225: printf ("\tval <<= 1;\n");
3226: printf ("\tif (carry) val |= 1;\n");
3227: genflags (flag_logical, curi->size, "val", "", "");
3228: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
3229: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3230: break;
3231: case i_RORW:
3232: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3233: fill_prefetch_next ();
3234: start_brace ();
3235: switch (curi->size) {
3236: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3237: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3238: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3239: default: abort ();
3240: }
3241: printf ("\tuae_u32 carry = val & 1;\n");
3242: printf ("\tval >>= 1;\n");
3243: printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
3244: genflags (flag_logical, curi->size, "val", "", "");
3245: printf ("\tSET_CFLG (carry);\n");
3246: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3247: break;
3248: case i_ROXLW:
3249: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3250: fill_prefetch_next ();
3251: start_brace ();
3252: switch (curi->size) {
3253: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3254: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3255: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3256: default: abort ();
3257: }
3258: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
3259: printf ("\tval <<= 1;\n");
3260: printf ("\tif (GET_XFLG ()) val |= 1;\n");
3261: genflags (flag_logical, curi->size, "val", "", "");
3262: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
3263: duplicate_carry (0);
3264: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3265: break;
3266: case i_ROXRW:
3267: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3268: fill_prefetch_next ();
3269: start_brace ();
3270: switch (curi->size) {
3271: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3272: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3273: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3274: default: abort ();
3275: }
3276: printf ("\tuae_u32 carry = val & 1;\n");
3277: printf ("\tval >>= 1;\n");
3278: printf ("\tif (GET_XFLG ()) val |= %s;\n", cmask (curi->size));
3279: genflags (flag_logical, curi->size, "val", "", "");
3280: printf ("\tSET_CFLG (carry);\n");
3281: duplicate_carry (0);
3282: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3283: break;
3284: case i_MOVEC2:
3285: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3286: fill_prefetch_next ();
3287: start_brace ();
3288: printf ("\tint regno = (src >> 12) & 15;\n");
3289: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
3290: printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
3291: break;
3292: case i_MOVE2C:
3293: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3294: fill_prefetch_next ();
3295: start_brace ();
3296: printf ("\tint regno = (src >> 12) & 15;\n");
3297: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
3298: printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
3299: if (using_ce020 == 2) {
3300: no_return_cycles = true;
3301: printf ("\tif((src & 0xFFF) < 3)\n");
3302: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_MOVEC[1];\n");
3303: printf ("\telse\n");
3304: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_MOVEC[0];\n");
3305: }
3306: break;
3307: case i_CAS:
3308: {
3309: if (using_ce020 == 2) {
3310: no_return_cycles = true;
3311: if (curi->size == sz_byte) {
3312: instr_table = TABLE_FALCON_CYCLES_CAS_BW;
3313: instr_table_index = cas_b_index * 2;
3314: cas_b_index ++;
3315: }
3316: else if (curi->size == sz_word) {
3317: instr_table = TABLE_FALCON_CYCLES_CAS_BW;
3318: instr_table_index = cas_w_index * 2;
3319: cas_w_index ++;
3320: }
3321: else {
3322: instr_table = TABLE_FALCON_CYCLES_CAS_L;
3323: instr_table_index = cas_l_index * 2;
3324: cas_l_index ++;
3325: }
3326: }
3327: int old_brace_level;
3328: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3329: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3330: fill_prefetch_0 ();
3331: start_brace ();
3332: printf ("\tint ru = (src >> 6) & 7;\n");
3333: printf ("\tint rc = src & 7;\n");
3334: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, rc)", "dst");
3335: printf ("\tif (GET_ZFLG ())");
3336: old_brace_level = n_braces;
3337: start_brace ();
3338: genastore ("(m68k_dreg (regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
3339: if (using_ce020 == 2)
3340: printf ("\tregs.ce030_instr_cycles = %s[%d];\n", falcon_cycles_tables[instr_table], instr_table_index);
3341: pop_braces (old_brace_level);
3342: printf ("else");
3343: start_brace ();
3344: printf ("m68k_dreg (regs, rc) = dst;\n");
3345: if (using_ce020 == 2)
3346: printf ("\tregs.ce030_instr_cycles = %s[%d];\n", falcon_cycles_tables[instr_table], instr_table_index + 1);
3347: pop_braces (old_brace_level);
3348: }
3349: break;
3350: case i_CAS2:
3351: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3352: printf ("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
3353: printf ("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
3354: if (curi->size == sz_word) {
3355: int old_brace_level = n_braces;
3356: printf ("\tuae_u16 dst1 = %s (rn1), dst2 = %s (rn2);\n", srcw, srcw);
3357: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, (extra >> 16) & 7)", "dst1");
3358: printf ("\tif (GET_ZFLG ()) {\n");
3359: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, extra & 7)", "dst2");
3360: printf ("\tif (GET_ZFLG ()) {\n");
3361: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 22) & 7));\n", dstw);
3362: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 6) & 7));\n", dstw);
3363: printf ("\t}}\n");
3364: pop_braces (old_brace_level);
3365: printf ("\tif (! GET_ZFLG ()) {\n");
3366: printf ("\tm68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
3367: printf ("\tm68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
3368: printf ("\t}\n");
3369: } else {
3370: int old_brace_level = n_braces;
3371: printf ("\tuae_u32 dst1 = %s (rn1), dst2 = %s (rn2);\n", srcl, srcl);
3372: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, (extra >> 16) & 7)", "dst1");
3373: printf ("\tif (GET_ZFLG ()) {\n");
3374: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, extra & 7)", "dst2");
3375: printf ("\tif (GET_ZFLG ()) {\n");
3376: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 22) & 7));\n", dstl);
3377: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 6) & 7));\n", dstl);
3378: printf ("\t}}\n");
3379: pop_braces (old_brace_level);
3380: printf ("\tif (! GET_ZFLG ()) {\n");
3381: printf ("\tm68k_dreg (regs, (extra >> 22) & 7) = dst1;\n");
3382: printf ("\tm68k_dreg (regs, (extra >> 6) & 7) = dst2;\n");
3383: printf ("\t}\n");
3384: }
3385: break;
3386: case i_MOVES: /* ignore DFC and SFC when using_mmu == false */
3387: {
3388: int old_brace_level;
3389: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3390: printf ("\tif (extra & 0x800)\n");
3391: {
3392: int old_m68k_pc_offset = m68k_pc_offset;
3393: old_brace_level = n_braces;
3394: start_brace ();
3395: printf ("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
3396: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
3397: genastore_fc ("src", curi->dmode, "dstreg", curi->size, "dst");
3398: pop_braces (old_brace_level);
3399: m68k_pc_offset = old_m68k_pc_offset;
3400: }
3401: printf ("else");
3402: {
3403: start_brace ();
3404: genamode (curi->dmode, "dstreg", curi->size, "src", 1, 0, GF_FC);
3405: printf ("\tif (extra & 0x8000) {\n");
3406: switch (curi->size) {
3407: case sz_byte: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
3408: case sz_word: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
3409: case sz_long: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = src;\n"); break;
3410: default: abort ();
3411: }
3412: printf ("\t} else {\n");
3413: genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
3414: printf ("\t}\n");
3415: sync_m68k_pc ();
3416: pop_braces (old_brace_level);
3417: }
3418: }
3419: break;
3420: case i_BKPT: /* only needed for hardware emulators */
3421: sync_m68k_pc ();
3422: printf ("\top_illg (opcode);\n");
3423: break;
3424: case i_CALLM: /* not present in 68030 */
3425: sync_m68k_pc ();
3426: printf ("\top_illg (opcode);\n");
3427: break;
3428: case i_RTM: /* not present in 68030 */
3429: sync_m68k_pc ();
3430: printf ("\top_illg (opcode);\n");
3431: break;
3432: case i_TRAPcc:
3433: if (curi->smode != am_unknown && curi->smode != am_illg)
3434: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
3435: fill_prefetch_0 ();
3436: printf ("\tif (cctrue (%d)) { Exception (7, m68k_getpc () ,M68000_EXC_SRC_CPU); goto %s; }\n", curi->cc, endlabelstr);
3437: need_endlabel = 1;
3438: break;
3439: case i_DIVL:
3440: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
3441: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3442: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3443: sync_m68k_pc ();
3444: printf ("\tm68k_divl(opcode, dst, extra, oldpc);\n");
3445: if (using_ce020 == 2) {
3446: no_return_cycles = true;
3447: printf ("\tif (extra & 0x800)\n");
3448: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_DIVS_L[%d];\n", divl_index);
3449: printf ("\telse\n");
3450: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_DIVU_L[%d];\n", divl_index);
3451: divl_index ++;
3452: }
3453: break;
3454: case i_MULL:
3455: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3456: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3457: sync_m68k_pc ();
3458: printf ("\tm68k_mull(opcode, dst, extra);\n");
3459: break;
3460: case i_BFTST:
3461: case i_BFEXTU:
3462: case i_BFCHG:
3463: case i_BFEXTS:
3464: case i_BFCLR:
3465: case i_BFFFO:
3466: case i_BFSET:
3467: case i_BFINS:
3468: {
3469: const char *getb, *putb;
3470:
3471: if (using_mmu || using_ce020) {
3472: getb = "x_get_bitfield";
3473: putb = "x_put_bitfield";
3474: } else {
3475: getb = "get_bitfield";
3476: putb = "put_bitfield";
3477: }
3478:
3479: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3480: genamode (curi->dmode, "dstreg", sz_long, "dst", 2, 0, 0);
3481: start_brace ();
3482: printf ("\tuae_u32 bdata[2];\n");
3483: printf ("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
3484: printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
3485: if (curi->dmode == Dreg) {
3486: printf ("\tuae_u32 tmp = m68k_dreg(regs, dstreg);\n");
3487: printf ("\toffset &= 0x1f;\n");
3488: printf ("\ttmp = (tmp << offset) | (tmp >> (32 - offset));\n");
3489: printf ("\tbdata[0] = tmp & ((1 << (32 - width)) - 1);\n");
3490: } else {
3491: printf ("\tuae_u32 tmp;\n");
3492: printf ("\tdsta += offset >> 3;\n");
3493: printf ("\ttmp = %s (dsta, bdata, offset, width);\n", getb);
3494: }
3495: printf ("\tSET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);\n");
3496: if (curi->mnemo == i_BFEXTS)
3497: printf ("\ttmp = (uae_s32)tmp >> (32 - width);\n");
3498: else
3499: printf ("\ttmp >>= (32 - width);\n");
3500: printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
3501: switch (curi->mnemo) {
3502: case i_BFTST:
3503: break;
3504: case i_BFEXTU:
3505: case i_BFEXTS:
3506: printf ("\tm68k_dreg (regs, (extra >> 12) & 7) = tmp;\n");
3507: break;
3508: case i_BFCHG:
3509: printf ("\ttmp = tmp ^ (0xffffffffu >> (32 - width));\n");
3510: break;
3511: case i_BFCLR:
3512: printf ("\ttmp = 0;\n");
3513: break;
3514: case i_BFFFO:
3515: printf ("\t{ uae_u32 mask = 1 << (width - 1);\n");
3516: printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n");
3517: printf ("\tm68k_dreg (regs, (extra >> 12) & 7) = offset;\n");
3518: break;
3519: case i_BFSET:
3520: printf ("\ttmp = 0xffffffffu >> (32 - width);\n");
3521: break;
3522: case i_BFINS:
3523: printf ("\ttmp = m68k_dreg (regs, (extra >> 12) & 7);\n");
3524: printf ("\ttmp = tmp & (0xffffffffu >> (32 - width));\n");
3525: printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
3526: printf ("\tSET_ZFLG (tmp == 0);\n");
3527: break;
3528: default:
3529: break;
3530: }
3531: if (curi->mnemo == i_BFCHG
3532: || curi->mnemo == i_BFCLR
3533: || curi->mnemo == i_BFSET
3534: || curi->mnemo == i_BFINS) {
3535: if (curi->dmode == Dreg) {
3536: printf ("\ttmp = bdata[0] | (tmp << (32 - width));\n");
3537: printf ("\tm68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));\n");
3538: } else {
3539: printf ("\t%s(dsta, bdata, tmp, offset, width);\n", putb);
3540: }
3541: }
3542: }
3543: break;
3544: case i_PACK:
3545: if (curi->smode == Dreg) {
3546: printf ("\tuae_u16 val = m68k_dreg (regs, srcreg) + %s;\n", gen_nextiword (0));
3547: printf ("\tm68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
3548: } else {
3549: printf ("\tuae_u16 val;\n");
3550: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
3551: printf ("\tval = (uae_u16)%s (m68k_areg (regs, srcreg));\n", srcb);
3552: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
3553: printf ("\tval = (val | ((uae_u16)%s (m68k_areg (regs, srcreg)) << 8)) + %s;\n", srcb, gen_nextiword (0));
3554: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
3555: gen_set_fault_pc ();
3556: printf ("\t%s (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n", dstb);
3557: }
3558: break;
3559: case i_UNPK:
3560: if (curi->smode == Dreg) {
3561: printf ("\tuae_u16 val = m68k_dreg (regs, srcreg);\n");
3562: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
3563: printf ("\tm68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
3564: } else {
3565: printf ("\tuae_u16 val;\n");
3566: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
3567: printf ("\tval = (uae_u16)%s (m68k_areg (regs, srcreg));\n", srcb);
3568: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
3569: if (cpu_level >= 2) {
3570: printf ("\tm68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];\n");
3571: printf ("\t%s (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);\n", dstb);
3572: printf ("\t%s (m68k_areg (regs, dstreg), val >> 8);\n", dstb);
3573: } else {
3574: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
3575: printf ("\t%s (m68k_areg (regs, dstreg),val);\n", dstb);
3576: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
3577: gen_set_fault_pc ();
3578: printf ("\t%s (m68k_areg (regs, dstreg),val >> 8);\n", dstb);
3579: }
3580: }
3581: break;
3582: case i_TAS:
3583: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3584: genflags (flag_logical, curi->size, "src", "", "");
3585: if (!isreg (curi->smode))
3586: addcycles000 (2);
3587: fill_prefetch_next ();
3588: printf ("\tsrc |= 0x80;\n");
3589: if (cpu_level >= 2 || curi->smode == Dreg || !using_ce) {
3590: if (next_cpu_level < 2)
3591: next_cpu_level = 2 - 1;
3592: genastore ("src", curi->smode, "srcreg", curi->size, "src");
3593: } else {
3594: printf ("\tif (!is_cycle_ce ()) {\n");
3595: genastore ("src", curi->smode, "srcreg", curi->size, "src");
3596: printf ("\t} else {\n");
3597: printf ("\t\tdo_cycles_ce000 (4);\n");
3598: printf ("\t}\n");
3599: }
3600: break;
3601: case i_FPP:
3602: fpulimit();
3603: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3604: sync_m68k_pc ();
3605: printf ("\tfpuop_arithmetic(opcode, extra);\n");
3606: break;
3607: case i_FDBcc:
3608: fpulimit();
3609: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3610: sync_m68k_pc ();
3611: printf ("\tfpuop_dbcc (opcode, extra);\n");
3612: break;
3613: case i_FScc:
3614: fpulimit();
3615: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3616: sync_m68k_pc ();
3617: printf ("\tfpuop_scc (opcode, extra);\n");
3618: break;
3619: case i_FTRAPcc:
3620: fpulimit();
3621: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
3622: printf ("\tuae_u16 extra = %s;\n", gen_nextiword (0));
3623: if (curi->smode != am_unknown && curi->smode != am_illg)
3624: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
3625: sync_m68k_pc ();
3626: printf ("\tfpuop_trapcc (opcode, oldpc, extra);\n");
3627: break;
3628: case i_FBcc:
3629: fpulimit();
3630: sync_m68k_pc ();
3631: start_brace ();
3632: printf ("\tuaecptr pc = m68k_getpc ();\n");
3633: genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0, 0);
3634: sync_m68k_pc ();
3635: printf ("\tfpuop_bcc (opcode, pc,extra);\n");
3636: break;
3637: case i_FSAVE:
3638: fpulimit();
3639: sync_m68k_pc ();
3640: printf ("\tfpuop_save (opcode);\n");
3641: break;
3642: case i_FRESTORE:
3643: fpulimit();
3644: sync_m68k_pc ();
3645: printf ("\tfpuop_restore (opcode);\n");
3646: break;
3647:
3648: case i_CINVL:
3649: case i_CINVP:
3650: case i_CINVA:
3651: case i_CPUSHL:
3652: case i_CPUSHP:
3653: case i_CPUSHA:
3654: if (using_mmu)
1.1.1.5 ! root 3655: printf ("\tflush_mmu%s(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);\n", mmu_postfix);
1.1.1.4 root 3656: printf ("\tif (opcode & 0x80)\n");
3657: printf ("\t\tflush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);\n");
3658: break;
3659:
3660: case i_MOVE16:
3661: {
3662: if ((opcode & 0xfff8) == 0xf620) {
3663: /* MOVE16 (Ax)+,(Ay)+ */
3664: printf ("\tuae_u32 v1, v2, v3, v4;\n");
3665: printf ("\tuaecptr mems = m68k_areg (regs, srcreg) & ~15, memd;\n");
3666: printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword (0));
3667: printf ("\tmemd = m68k_areg (regs, dstreg) & ~15;\n");
3668: printf ("\tv1 = %s (mems);\n", srcl);
3669: printf ("\tv2 = %s (mems + 4);\n", srcl);
3670: printf ("\tv3 = %s (mems + 8);\n", srcl);
3671: printf ("\tv4 = %s (mems + 12);\n", srcl);
3672: printf ("\t%s (memd , v1);\n", dstl);
3673: printf ("\t%s (memd + 4, v2);\n", dstl);
3674: printf ("\t%s (memd + 8, v3);\n", dstl);
3675: printf ("\t%s (memd + 12, v4);\n", dstl);
3676: printf ("\tif (srcreg != dstreg)\n");
3677: printf ("\t\tm68k_areg (regs, srcreg) += 16;\n");
3678: printf ("\tm68k_areg (regs, dstreg) += 16;\n");
3679: } else {
3680: /* Other variants */
3681: printf ("\tuae_u32 v1, v2, v3, v4;\n");
3682: genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2, 0);
3683: genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2, 0);
3684: printf ("\tmemsa &= ~15;\n");
3685: printf ("\tmemda &= ~15;\n");
3686: printf ("\tv1 = %s (memsa);\n", srcl);
3687: printf ("\tv2 = %s (memsa + 4);\n", srcl);
3688: printf ("\tv3 = %s (memsa + 8);\n", srcl);
3689: printf ("\tv4 = %s (memsa + 12);\n", srcl);
3690: printf ("\t%s (memda , v1);\n", dstl);
3691: printf ("\t%s (memda + 4, v2);\n", dstl);
3692: printf ("\t%s (memda + 8, v3);\n", dstl);
3693: printf ("\t%s (memda + 12, v4);\n", dstl);
3694: if ((opcode & 0xfff8) == 0xf600)
3695: printf ("\tm68k_areg (regs, srcreg) += 16;\n");
3696: else if ((opcode & 0xfff8) == 0xf608)
3697: printf ("\tm68k_areg (regs, dstreg) += 16;\n");
3698: }
3699: }
3700: break;
3701:
3702: case i_PFLUSHN:
3703: case i_PFLUSH:
3704: case i_PFLUSHAN:
3705: case i_PFLUSHA:
3706: case i_PLPAR:
3707: case i_PLPAW:
3708: case i_PTESTR:
3709: case i_PTESTW:
3710: sync_m68k_pc ();
3711: printf ("\tmmu_op (opcode, 0);\n");
3712: break;
3713: case i_MMUOP030:
3714: printf ("\tuaecptr pc = m68k_getpc ();\n");
3715: printf ("\tuae_u16 extra = x_get_word (pc + 2);\n");
3716: m68k_pc_offset += 2;
3717: sync_m68k_pc ();
3718: if (curi->smode == Areg || curi->smode == Dreg)
3719: printf("\tuae_u16 extraa = 0;\n");
3720: else
3721: genamode (curi->smode, "srcreg", curi->size, "extra", 0, 0, 0);
3722: sync_m68k_pc ();
3723: printf ("\tmmu_op30 (pc, opcode, extra, extraa);\n");
3724: break;
3725: default:
3726: abort ();
3727: break;
3728: }
3729: finish_braces ();
3730: if (limit_braces) {
3731: printf ("\n#endif\n");
3732: n_braces = limit_braces;
3733: limit_braces = 0;
3734: finish_braces ();
3735: }
3736: if (did_prefetch >= 0)
3737: fill_prefetch_finish ();
3738: if (!count_cycles)
3739: addcycles_ce020 (0, 0, 2, 2);
3740: sync_m68k_pc ();
3741: did_prefetch = 0;
3742: }
3743:
3744: static void generate_includes (FILE * f)
3745: {
3746: fprintf (f, "#include \"main.h\"\n");
3747: fprintf (f, "#include \"sysdeps.h\"\n");
3748: fprintf (f, "#include \"hatari-glue.h\"\n");
3749: fprintf (f, "#include \"maccess.h\"\n");
3750: fprintf (f, "#include \"memory.h\"\n");
3751: fprintf (f, "#include \"custom.h\"\n");
3752: fprintf (f, "#include \"newcpu.h\"\n");
3753: fprintf (f, "#include \"cpu_prefetch.h\"\n");
3754: fprintf (f, "#include \"cputbl.h\"\n");
3755:
3756: fprintf (f, "#define CPUFUNC(x) x##_ff\n"
3757: "#define SET_CFLG_ALWAYS(x) SET_CFLG(x)\n"
3758: "#define SET_NFLG_ALWAYS(x) SET_NFLG(x)\n"
3759: "#ifdef NOFLAGS\n"
3760: "#include \"noflags.h\"\n"
3761: "#endif\n");
3762: }
3763:
3764: static int postfix;
3765:
3766:
3767: static char *decodeEA (amodes mode, wordsizes size)
3768: {
3769: static char buffer[80];
3770:
3771: buffer[0] = 0;
3772: switch (mode){
3773: case Dreg:
3774: strcpy (buffer,"Dn");
3775: break;
3776: case Areg:
3777: strcpy (buffer,"An");
3778: break;
3779: case Aind:
3780: strcpy (buffer,"(An)");
3781: break;
3782: case Aipi:
3783: strcpy (buffer,"(An)+");
3784: break;
3785: case Apdi:
3786: strcpy (buffer,"-(An)");
3787: break;
3788: case Ad16:
3789: strcpy (buffer,"(d16,An)");
3790: break;
3791: case Ad8r:
3792: strcpy (buffer,"(d8,An,Xn)");
3793: break;
3794: case PC16:
3795: strcpy (buffer,"(d16,PC)");
3796: break;
3797: case PC8r:
3798: strcpy (buffer,"(d8,PC,Xn)");
3799: break;
3800: case absw:
3801: strcpy (buffer,"(xxx).W");
3802: break;
3803: case absl:
3804: strcpy (buffer,"(xxx).L");
3805: break;
3806: case imm:
3807: switch (size){
3808: case sz_byte:
3809: strcpy (buffer,"#<data>.B");
3810: break;
3811: case sz_word:
3812: strcpy (buffer,"#<data>.W");
3813: break;
3814: case sz_long:
3815: strcpy (buffer,"#<data>.L");
3816: break;
3817: default:
3818: break;
3819: }
3820: break;
3821: case imm0:
3822: strcpy (buffer,"#<data>.B");
3823: break;
3824: case imm1:
3825: strcpy (buffer,"#<data>.W");
3826: break;
3827: case imm2:
3828: strcpy (buffer,"#<data>.L");
3829: break;
3830: case immi:
3831: strcpy (buffer,"#<data>");
3832: break;
3833:
3834: default:
3835: break;
3836: }
3837: return buffer;
3838: }
3839:
3840: static char *outopcode (int opcode)
3841: {
3842: static char out[100];
3843: struct instr *ins;
3844: int i;
3845:
3846: ins = &table68k[opcode];
3847: for (i = 0; lookuptab[i].name[0]; i++) {
3848: if (ins->mnemo == lookuptab[i].mnemo)
3849: break;
3850: }
3851: {
3852: // char *s = ua (lookuptab[i].name);
3853: const char *s = lookuptab[i].name;
3854: strcpy (out, s);
3855: //xfree (s);
3856: }
3857: if (ins->smode == immi)
3858: strcat (out, "Q");
3859: if (ins->size == sz_byte)
3860: strcat (out,".B");
3861: if (ins->size == sz_word)
3862: strcat (out,".W");
3863: if (ins->size == sz_long)
3864: strcat (out,".L");
3865: strcat (out," ");
3866: if (ins->suse)
3867: strcat (out, decodeEA (ins->smode, ins->size));
3868: if (ins->duse) {
3869: if (ins->suse) strcat (out,",");
3870: strcat (out, decodeEA (ins->dmode, ins->size));
3871: }
3872: return out;
3873: }
3874:
3875: static void generate_one_opcode (int rp)
3876: {
3877: int idx;
3878: uae_u16 smsk, dmsk;
3879: long int opcode = opcode_map[rp];
3880: int i68000 = table68k[opcode].clev > 0;
3881:
3882: if (table68k[opcode].mnemo == i_ILLG
3883: || table68k[opcode].clev > cpu_level)
3884: return;
3885:
3886: for (idx = 0; lookuptab[idx].name[0]; idx++) {
3887: if (table68k[opcode].mnemo == lookuptab[idx].mnemo)
3888: break;
3889: }
3890:
3891: if (table68k[opcode].handler != -1)
3892: return;
3893:
3894: if (opcode_next_clev[rp] != cpu_level) {
3895: //char *name = ua (lookuptab[idx].name);
3896: const char *name = lookuptab[idx].name;
3897: if (generate_stbl)
3898: fprintf (stblfile, "{ %sCPUFUNC(op_%04lx_%d), %ld }, /* %s */\n",
3899: (using_ce || using_ce020) ? "(cpuop_func*)" : "",
3900: opcode, opcode_last_postfix[rp],
3901: opcode, name);
3902: //xfree (name);
3903: return;
3904: }
3905: fprintf (headerfile, "extern %s op_%04lx_%d_nf;\n",
3906: (using_ce || using_ce020) ? "cpuop_func_ce" : "cpuop_func", opcode, postfix);
3907: fprintf (headerfile, "extern %s op_%04lx_%d_ff;\n",
3908: (using_ce || using_ce020) ? "cpuop_func_ce" : "cpuop_func", opcode, postfix);
3909: printf ("/* %s */\n", outopcode (opcode));
3910: if (i68000)
3911: printf("#ifndef CPUEMU_68000_ONLY\n");
3912: printf ("%s REGPARAM2 CPUFUNC(op_%04lx_%d)(uae_u32 opcode)\n{\n", (using_ce || using_ce020) ? "void" : "unsigned long", opcode, postfix);
3913:
3914: switch (table68k[opcode].stype) {
3915: case 0: smsk = 7; break;
3916: case 1: smsk = 255; break;
3917: case 2: smsk = 15; break;
3918: case 3: smsk = 7; break;
3919: case 4: smsk = 7; break;
3920: case 5: smsk = 63; break;
3921: case 7: smsk = 3; break;
3922: default: abort ();
3923: }
3924: dmsk = 7;
3925:
3926: next_cpu_level = -1;
3927: if (table68k[opcode].suse
3928: && table68k[opcode].smode != imm && table68k[opcode].smode != imm0
3929: && table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
3930: && table68k[opcode].smode != absw && table68k[opcode].smode != absl
3931: && table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
3932: {
3933: if (table68k[opcode].spos == -1) {
3934: if (((int) table68k[opcode].sreg) >= 128)
3935: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
3936: else
3937: printf ("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
3938: } else {
3939: char source[100];
3940: int pos = table68k[opcode].spos;
3941:
3942: if (pos)
3943: sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
3944: else
3945: sprintf (source, "(opcode & %d)", smsk);
3946:
3947: if (table68k[opcode].stype == 3)
3948: printf ("\tuae_u32 srcreg = imm8_table[%s];\n", source);
3949: else if (table68k[opcode].stype == 1)
3950: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
3951: else
3952: printf ("\tuae_u32 srcreg = %s;\n", source);
3953: }
3954: }
3955: if (table68k[opcode].duse
3956: /* Yes, the dmode can be imm, in case of LINK or DBcc */
3957: && table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
3958: && table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
3959: && table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
3960: {
3961: if (table68k[opcode].dpos == -1) {
3962: if (((int) table68k[opcode].dreg) >= 128)
3963: printf ("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
3964: else
3965: printf ("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
3966: } else {
3967: int pos = table68k[opcode].dpos;
3968: if (pos)
3969: printf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
3970: pos, dmsk);
3971: else
3972: printf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
3973: }
3974: }
3975: need_endlabel = 0;
3976: endlabelno++;
3977: sprintf (endlabelstr, "endlabel%d", endlabelno);
3978: count_read = count_write = count_ncycles = count_cycles = 0;
3979: count_read_ea = count_write_ea = count_cycles_ea = 0;
3980: gen_opcode (opcode);
3981: if (need_endlabel)
3982: printf ("%s: ;\n", endlabelstr);
3983:
3984: returncycles ("", insn_n_cycles);
3985:
3986: printf ("}");
3987: if (using_ce || using_prefetch) {
3988: if (count_read + count_write + count_cycles == 0)
3989: count_cycles = 4;
3990: printf (" /* %d%s (%d/%d)",
3991: (count_read + count_write) * 4 + count_cycles, count_ncycles ? "+" : "", count_read, count_write);
3992: printf (" */\n");
3993: } else {
3994: printf("\n");
3995: }
3996: printf ("\n");
3997: if (i68000)
3998: printf("#endif\n");
3999: opcode_next_clev[rp] = next_cpu_level;
4000: opcode_last_postfix[rp] = postfix;
4001:
4002: /* Hatari only : Now patch in the instruction cycles at the beginning of the function: */
4003: if (!using_ce020) {
4004: fseek(stdout, nCurInstrCycPos, SEEK_SET);
4005: printf("%d;", insn_n_cycles);
4006: fseek(stdout, 0, SEEK_END);
4007: }
4008:
4009: /* Hatari only : inc instruction index for cycle exact 68030 cpu */
4010: if (using_ce020 == 2)
4011: instr_index += 1;
4012:
4013: if (generate_stbl) {
4014: // char *name = ua (lookuptab[idx].name);
4015: const char *name = lookuptab[idx].name;
4016: if (i68000)
4017: fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
4018: fprintf (stblfile, "{ %sCPUFUNC(op_%04lx_%d), %ld }, /* %s */\n",
4019: (using_ce || using_ce020) ? "(cpuop_func*)" : "",
4020: opcode, postfix, opcode, name);
4021: if (i68000)
4022: fprintf (stblfile, "#endif\n");
4023: //xfree (name);
4024: }
4025: }
4026:
4027: static void generate_func (void)
4028: {
4029: int j, rp;
4030:
4031: /* sam: this is for people with low memory (eg. me :)) */
4032: printf ("\n"
4033: "#if !defined(PART_1) && !defined(PART_2) && "
4034: "!defined(PART_3) && !defined(PART_4) && "
4035: "!defined(PART_5) && !defined(PART_6) && "
4036: "!defined(PART_7) && !defined(PART_8)"
4037: "\n"
4038: "#define PART_1 1\n"
4039: "#define PART_2 1\n"
4040: "#define PART_3 1\n"
4041: "#define PART_4 1\n"
4042: "#define PART_5 1\n"
4043: "#define PART_6 1\n"
4044: "#define PART_7 1\n"
4045: "#define PART_8 1\n"
4046: "#endif\n\n");
4047:
4048: rp = 0;
4049: for(j = 1; j <= 8; ++j) {
4050: int k = (j * nr_cpuop_funcs) / 8;
4051: printf ("#ifdef PART_%d\n",j);
4052: for (; rp < k; rp++)
4053: generate_one_opcode (rp);
4054: printf ("#endif\n\n");
4055: }
4056:
4057: if (generate_stbl)
4058: fprintf (stblfile, "{ 0, 0 }};\n");
4059: }
4060:
4061: int main (int argc, char **argv)
4062: {
4063: int i, rp, postfix2;
4064: char fname[100];
4065:
4066: read_table68k ();
4067: do_merges ();
4068:
4069: opcode_map = xmalloc (int, nr_cpuop_funcs);
4070: opcode_last_postfix = xmalloc (int, nr_cpuop_funcs);
4071: opcode_next_clev = xmalloc (int, nr_cpuop_funcs);
4072: counts = xmalloc (unsigned long, 65536);
4073: read_counts ();
4074:
4075: /* It would be a lot nicer to put all in one file (we'd also get rid of
4076: * cputbl.h that way), but cpuopti can't cope. That could be fixed, but
4077: * I don't dare to touch the 68k version. */
4078:
4079: headerfile = fopen ("cputbl.h", "wb");
4080:
4081: stblfile = fopen ("cpustbl.c", "wb");
4082: generate_includes (stblfile);
4083:
4084: using_prefetch = 0;
4085: using_indirect = 0;
4086: using_exception_3 = 1;
4087: using_ce = 0;
4088:
4089: postfix2 = -1;
1.1.1.5 ! root 4090: for (i = 0; i <= 32; i++) {
1.1.1.4 root 4091: postfix = i;
4092: if ((i >= 6 && i < 11) || (i > 12 && i < 20) || (i > 23 && i < 31))
4093: continue;
4094: generate_stbl = 1;
1.1.1.5 ! root 4095: if (i == 0 || i == 11 || i == 12 || i == 20 || i == 21
! 4096: || i == 31 || i == 32) {
1.1.1.4 root 4097: if (generate_stbl)
4098: fprintf (stblfile, "#ifdef CPUEMU_%d\n", postfix);
4099: postfix2 = postfix;
4100: sprintf (fname, "cpuemu_%d.c", postfix);
4101: if (freopen (fname, "wb", stdout) == NULL) {
4102: perror(fname);
4103: return -1;
4104: }
4105: generate_includes (stdout);
4106: }
4107: using_mmu = 0;
4108: using_prefetch = 0;
4109: using_ce = 0;
4110: using_ce020 = 0;
4111: using_mmu = 0;
4112: cpu_level = 5 - i;
4113: if (i == 11 || i == 12) {
4114: cpu_level = 0;
4115: using_prefetch = 1;
4116: using_exception_3 = 1;
4117: if (i == 12)
4118: using_ce = 1;
4119: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4120: opcode_next_clev[rp] = 0;
4121: } else if (i == 20) {
4122: cpu_level = 2;
4123: using_ce020 = 1;
4124: read_counts ();
4125: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4126: opcode_next_clev[rp] = cpu_level;
4127: } else if (i == 21 || i == 22 || i == 23) {
4128: cpu_level = 3 + (23 - i);
4129: using_ce020 = 2;
4130: if (i == 21) {
4131: read_counts ();
4132: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4133: opcode_next_clev[rp] = cpu_level;
4134: }
4135: } else if (i >= 31 && i < 40) {
1.1.1.5 ! root 4136: cpu_level = 3 + 32 - i;
1.1.1.4 root 4137: using_mmu = 1;
1.1.1.5 ! root 4138: if (cpu_level == 3) {
! 4139: fprintf (stdout, "#include \"cpummu030.h\"\n");
! 4140: mmu_postfix = "030";
! 4141: }
! 4142: else {
! 4143: fprintf (stdout, "#include \"cpummu.h\"\n");
! 4144: mmu_postfix = "";
! 4145: }
! 4146:
1.1.1.4 root 4147: if (i == 31)
4148: read_counts ();
4149: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4150: opcode_next_clev[rp] = cpu_level;
4151: }
4152:
4153: if (generate_stbl) {
4154: if ((i > 0 && i < 10) || (i >= 20))
4155: fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
4156: fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
4157: }
4158:
4159: generate_func ();
4160: if (generate_stbl) {
4161: if ((i > 0 && i < 10) || (i >= 20))
4162: fprintf (stblfile, "#endif /* CPUEMU_68000_ONLY */\n");
4163: if (postfix2 >= 0)
4164: fprintf (stblfile, "#endif /* CPUEMU_%d */\n", postfix2);
4165: }
4166: postfix2 = -1;
4167: }
4168:
4169: free (table68k);
4170: return 0;
4171: }
4172:
4173: void write_log (const TCHAR *format,...)
4174: {
4175: }
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