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1.1.1.4 root 1: /*
2: * UAE - The Un*x Amiga Emulator
3: *
4: * MC68000 emulation generator
5: *
6: * This is a fairly stupid program that generates a lot of case labels that
7: * can be #included in a switch statement.
8: * As an alternative, it can generate functions that handle specific
9: * MC68000 instructions, plus a prototype header file and a function pointer
10: * array to look up the function for an opcode.
11: * Error checking is bad, an illegal table68k file will cause the program to
12: * call abort().
13: * The generated code is sometimes sub-optimal, an optimizing compiler should
14: * take care of this.
15: *
16: * The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
17: *
18: * Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
19: */
20:
21: #include "sysconfig.h"
22: #include "sysdeps.h"
23: #include <ctype.h>
24: #include <string.h>
25:
26: #include "readcpu.h"
27: #include "falcon_cycle030.h"
28:
29: #define BOOL_TYPE "int"
30: /* Define the minimal 680x0 where NV flags are not affected by xBCD instructions. */
31: #define xBCD_KEEPS_NV_FLAGS 4
32:
33: static FILE *headerfile;
34: static FILE *stblfile;
35:
36: static int using_prefetch, using_indirect, using_mmu;
37: static int using_ce020;
38: static int using_exception_3;
39: static int using_ce;
40: static int cpu_level;
41: static int count_read, count_write, count_cycles, count_ncycles;
42: static int count_read_ea, count_write_ea, count_cycles_ea;
1.1.1.5 root 43: static const char *mmu_postfix;
1.1.1.4 root 44:
45: static int optimized_flags;
46:
47: long nCurInstrCycPos; /* Hatari only : Stores where we have to patch in the current cycles value */
48:
49: #define GF_APDI 1
50: #define GF_AD8R 2
51: #define GF_PC8R 4
52: #define GF_AA 7
53: #define GF_NOREFILL 8
54: #define GF_PREFETCH 16
55: #define GF_FC 32
56: #define GF_MOVE 64
57:
58: /* For the current opcode, the next lower level that will have different code.
59: * Initialized to -1 for each opcode. If it remains unchanged, indicates we
60: * are done with that opcode. */
61: static int next_cpu_level;
62:
63: static int *opcode_map;
64: static int *opcode_next_clev;
65: static int *opcode_last_postfix;
66: static unsigned long *counts;
67: static int generate_stbl;
68: static int fixupcnt;
69:
70: static int instr_index = 0; /* Hatari: Added to give a unique index to each 68030 cycle exact instruction (CPU_EMU_21) */
71: static int instr_table; /* Hatari: Used to know which cycle table to use (CPU_EMU_21) */
72: static int instr_table_index; /* Hatari: Used when the cycle table is not the generic one to set the line of the table (CPU_EMU_21) */
73:
74: /* used to disable the return cycles function call when there are more than one cycle to take into account for an instruction */
75: /* Falcon CPU only (CPUEMU_21)) */
76: static bool no_return_cycles;
77:
78: /* All the following indexes are useful to get the correct cycle index in the cycle tables for 68030 cycle exact CPU (CPU_21) */
79: /* Hatari only code */
80: static int chk_w_index = 0;
81: static int chk_l_index = 0;
82: static int chk2_b_index = 0;
83: static int chk2_w_index = 0;
84: static int chk2_l_index = 0;
85: static int cas_b_index = 0;
86: static int cas_w_index = 0;
87: static int cas_l_index = 0;
88: static int divl_index = 0;
89:
90: /* These defines describe the different tables used for 68030 Cycle exact (Hatari only) */
91: #define TABLE_FALCON_CYCLES 0
92: #define TABLE_FALCON_CYCLES_CHK2_BW 1
93: #define TABLE_FALCON_CYCLES_CHK2_L 2
94: #define TABLE_FALCON_CYCLES_CHK_L 3
95: #define TABLE_FALCON_CYCLES_CHK_W 4
96: #define TABLE_FALCON_CYCLES_CAS_BW 5
97: #define TABLE_FALCON_CYCLES_CAS_L 6
98: #define TABLE_FALCON_CYCLES_CAS2_W 7
99: #define TABLE_FALCON_CYCLES_CAS2_L 8
100: #define TABLE_FALCON_CYCLES_RTE 9
101: #define TABLE_FALCON_CYCLES_BCC 10
102: #define TABLE_FALCON_CYCLES_DBCC 11
103: #define TABLE_FALCON_CYCLES_TRAPCC 12
104: #define TABLE_FALCON_CYCLES_TRAPCC_W 13
105: #define TABLE_FALCON_CYCLES_TRAPCC_L 14
106: #define TABLE_FALCON_CYCLES_TRAPV 15
107: #define TABLE_FALCON_CYCLES_DIVU_L 16
108: #define TABLE_FALCON_CYCLES_DIVS_L 17
109: #define TABLE_FALCON_CYCLES_BFTST_MEM 18
110: #define TABLE_FALCON_CYCLES_BFEXTU_MEM 19
111: #define TABLE_FALCON_CYCLES_BFCHG_MEM 20
112: #define TABLE_FALCON_CYCLES_BFEXTS_MEM 21
113: #define TABLE_FALCON_CYCLES_BFCLR_MEM 22
114: #define TABLE_FALCON_CYCLES_BFFFO_MEM 23
115: #define TABLE_FALCON_CYCLES_BFSET_MEM 24
116: #define TABLE_FALCON_CYCLES_BFINS_MEM 25
117: #define TABLE_FALCON_CYCLES_LSD 26
118: #define TABLE_FALCON_CYCLES_ASR 27
119: #define TABLE_FALCON_CYCLES_MOVEC 28
120: #define TABLE_FALCON_CYCLES_MOVES_EA_RN 29
121: #define TABLE_FALCON_CYCLES_MOVES_RN_EA 30
122: #define TABLE_FALCON_CYCLES_68030_INTERNAL 31
123:
124:
125: #define GENA_GETV_NO_FETCH 0
126: #define GENA_GETV_FETCH 1
127: #define GENA_GETV_FETCH_ALIGN 2
128: #define GENA_MOVEM_DO_INC 0
129: #define GENA_MOVEM_NO_INC 1
130: #define GENA_MOVEM_MOVE16 2
131:
132: /**
133: Table_labels table for all case.
134: */
135: static const char* falcon_cycles_tables[] = {
136: "table_falcon_cycles",
137: "table_falcon_cycles_CHK2_BW",
138: "table_falcon_cycles_CHK2_L",
139: "table_falcon_cycles_CHK_L",
140: "table_falcon_cycles_CHK_W",
141: "table_falcon_cycles_CAS_BW",
142: "table_falcon_cycles_CAS_L",
143: "table_falcon_cycles_CAS2_W",
144: "table_falcon_cycles_CAS2_L",
145: "table_falcon_cycles_RTE",
146: "table_falcon_cycles_Bcc",
147: "table_falcon_cycles_DBcc",
148: "table_falcon_cycles_TRAPcc",
149: "table_falcon_cycles_TRAPcc_W",
150: "table_falcon_cycles_TRAPcc_L",
151: "table_falcon_cycles_TRAPV",
152: "table_falcon_cycles_DIVU_L",
153: "table_falcon_cycles_DIVS_L",
154: "table_falcon_cycles_BFTST_Mem",
155: "table_falcon_cycles_BFEXTU_Mem",
156: "table_falcon_cycles_BFCHG_Mem",
157: "table_falcon_cycles_BFEXTS_Mem",
158: "table_falcon_cycles_BFCLR_Mem",
159: "table_falcon_cycles_BFFFO_Mem",
160: "table_falcon_cycles_BFSET_Mem",
161: "table_falcon_cycles_BFINS_Mem",
162: "table_falcon_cycles_LSD",
163: "table_falcon_cycles_ASR",
164: "table_falcon_cycles_MOVEC",
165: "table_falcon_cycles_MOVES_EA_RN",
166: "table_falcon_cycles_MOVES_RN_EA",
167: "table_falcon_cycles_68030_internal"
168: };
169:
170: static void read_counts (void)
171: {
172: FILE *file;
173: unsigned long opcode, count, total;
174: char name[20];
175: int nr = 0;
176: memset (counts, 0, 65536 * sizeof *counts);
177:
178: count = 0;
179: file = fopen ("frequent.68k", "r");
180: if (file) {
1.1.1.6 ! root 181: if (fscanf (file, "Total: %lu\n", &total) == EOF) {
! 182: perror("read_counts");
! 183: }
1.1.1.4 root 184: while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
185: opcode_next_clev[nr] = 5;
186: opcode_last_postfix[nr] = -1;
187: opcode_map[nr++] = opcode;
188: counts[opcode] = count;
189: }
190: fclose (file);
191: }
192: if (nr == nr_cpuop_funcs)
193: return;
194: for (opcode = 0; opcode < 0x10000; opcode++) {
195: if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
196: && counts[opcode] == 0)
197: {
198: opcode_next_clev[nr] = 5;
199: opcode_last_postfix[nr] = -1;
200: opcode_map[nr++] = opcode;
201: counts[opcode] = count;
202: }
203: }
204: if (nr != nr_cpuop_funcs)
205: abort ();
206: }
207:
208: static char endlabelstr[80];
209: static int endlabelno = 0;
210: static int need_endlabel;
211:
212: static int n_braces, limit_braces;
213: static int m68k_pc_offset;
214: static int insn_n_cycles, insn_n_cycles020;
215:
216: static void fpulimit (void)
217: {
218: if (limit_braces)
219: return;
220: printf ("\n#ifdef FPUEMU\n");
221: limit_braces = n_braces;
222: n_braces = 0;
223: }
224:
225: static void returncycles (const char *s, int cycles)
226: {
227: if (using_ce)
228: return;
229:
230: if (using_ce020 == 1)
231: printf ("%sreturn;\n", s);
232: else if (using_ce020 == 2) {
233: if (no_return_cycles == true)
234: return;
235: // TODO: This first if statement should be removed when all the cycles are correctly generated for the Falcon 68030 CPU
236: // The next "else" should be removed too and only the printf line should be keept.
237: if (instr_table == TABLE_FALCON_CYCLES && table_falcon_cycles[instr_index].cache_cycles == 0) {
238: // set a temporary false value for this instruction cycles timing.
239: printf ("\tregs.ce030_instr_cycles = table_falcon_cycles[0];\n");
240: }
241: else {
242: printf ("%s\tregs.ce030_instr_cycles = %s[%d];\n", s, falcon_cycles_tables[instr_table], instr_table_index);
243: }
244:
245: printf ("%s\treturn;\n", s);
246: }
247: else
248: printf ("%sreturn %d * CYCLE_UNIT / 2;\n", s, cycles);
249: }
250:
251: /* Todo : remove this function when all Falcon cycles are coded */
252: static void addcycles_ce020 (int head, int tail, int cache_cycles, int noncache_cycles)
253: {
254: if (!using_ce020)
255: return;
256: if (cache_cycles > 0 && noncache_cycles > 0) {
257: //not needed anymore
258: }
259: count_cycles += noncache_cycles;
260: }
261:
262: static void addcycles000 (int cycles)
263: {
264: if (!using_ce)
265: return;
266: printf ("\tdo_cycles_ce000 (%d);\n", cycles);
267: count_cycles += cycles;
268: }
269: static void addcycles000_2 (const char *s, int cycles)
270: {
271: if (!using_ce)
272: return;
273: printf ("%sdo_cycles_ce000 (%d);\n", s, cycles);
274: count_cycles += cycles;
275: }
276:
277: static void addcycles000_3 (const char *s)
278: {
279: if (!using_ce)
280: return;
281: printf ("%sif (cycles > 0) do_cycles_ce000 (cycles);\n", s);
282: count_ncycles++;
283: }
284:
285: static int isreg (amodes mode)
286: {
287: if (mode == Dreg || mode == Areg)
288: return 1;
289: return 0;
290: }
291:
292: static void start_brace (void)
293: {
294: n_braces++;
295: printf ("{");
296: }
297:
298: static void close_brace (void)
299: {
300: assert (n_braces > 0);
301: n_braces--;
302: printf ("}");
303: }
304:
305: static void finish_braces (void)
306: {
307: while (n_braces > 0)
308: close_brace ();
309: }
310:
311: static void pop_braces (int to)
312: {
313: while (n_braces > to)
314: close_brace ();
315: }
316:
317: static int bit_size (int size)
318: {
319: switch (size) {
320: case sz_byte: return 8;
321: case sz_word: return 16;
322: case sz_long: return 32;
323: default: abort ();
324: }
325: return 0;
326: }
327:
328: static const char *bit_mask (int size)
329: {
330: switch (size) {
331: case sz_byte: return "0xff";
332: case sz_word: return "0xffff";
333: case sz_long: return "0xffffffff";
334: default: abort ();
335: }
336: return 0;
337: }
338:
339: static const char *srcl, *dstl;
340: static const char *srcw, *dstw;
341: static const char *srcb, *dstb;
342: static const char *ce020_prefetch_long;
343: static const char *ce020_prefetch_word;
344:
345: static void gen_nextilong (const char *type, const char *name, int flags)
346: {
347: int r = m68k_pc_offset;
348: m68k_pc_offset += 4;
349:
350: if (using_ce020) {
351: printf ("\t%s %s = %s (%d);\n", type, name, ce020_prefetch_long, r);
352: count_read += 2;
353: } else if (using_ce) {
354: printf ("\t%s %s;\n", type, name);
355: /* we must do this because execution order of (something | something2) is not defined */
356: if (flags & GF_NOREFILL) {
357: printf ("\t%s = get_word_ce_prefetch (%d) << 16;\n", name, r + 2);
358: count_read++;
359: printf ("\t%s |= regs.irc;\n", name);
360: } else {
361: printf ("\t%s = get_word_ce_prefetch (%d) << 16;\n", name, r + 2);
362: count_read++;
363: printf ("\t%s |= get_word_ce_prefetch (%d);\n", name, r + 4);
364: count_read++;
365: }
366: } else {
367: if (using_prefetch) {
368: if (flags & GF_NOREFILL) {
369: printf ("\t%s %s;\n", type, name);
370: printf ("\t%s = get_word_prefetch (%d) << 16;\n", name, r + 2);
371: count_read++;
372: printf ("\t%s |= regs.irc;\n", name);
373: insn_n_cycles += 4;
374: } else {
375: printf ("\t%s %s = get_long_prefetch (%d);\n", type, name, r + 2);
376: count_read++;
377: count_read++;
378: insn_n_cycles += 8;
379: }
380: } else if (using_indirect) {
381: insn_n_cycles += 8;
382: printf ("\t%s %s = get_ilongi (%d);\n", type, name, r);
383: } else if (using_mmu) {
384: insn_n_cycles += 8;
1.1.1.5 root 385: printf ("\t%s %s = get_ilong_mmu%s (%d);\n", type, name,
386: mmu_postfix, r);
1.1.1.4 root 387: } else {
388: insn_n_cycles += 8;
389: printf ("\t%s %s = get_ilong (%d);\n", type, name, r);
390: }
391: }
392: }
393:
394: static const char *gen_nextiword (int flags)
395: {
396: static char buffer[80];
397: int r = m68k_pc_offset;
398: m68k_pc_offset += 2;
399:
400: if (using_ce020) {
401: sprintf (buffer, "%s (%d)", ce020_prefetch_word, r);
402: count_read++;
403: } else if (using_ce) {
404: if (flags & GF_NOREFILL) {
405: strcpy (buffer, "regs.irc");
406: } else {
407: sprintf (buffer, "get_word_ce_prefetch (%d)", r + 2);
408: count_read++;
409: }
410: } else {
411: if (using_prefetch) {
412: if (flags & GF_NOREFILL) {
413: sprintf (buffer, "regs.irc"/*, r*/);
414: } else {
415: sprintf (buffer, "get_word_prefetch (%d)", r + 2);
416: count_read++;
417: insn_n_cycles += 4;
418: }
419: } else if (using_indirect) {
420: sprintf (buffer, "get_iwordi(%d)", r);
421: insn_n_cycles += 4;
422: } else if (using_mmu) {
1.1.1.5 root 423: sprintf (buffer, "get_iword_mmu%s (%d)",
424: mmu_postfix, r);
1.1.1.4 root 425: insn_n_cycles += 4;
426: } else {
427: sprintf (buffer, "get_iword (%d)", r);
428: insn_n_cycles += 4;
429: }
430: }
431: return buffer;
432: }
433:
434: static const char *gen_nextibyte (int flags)
435: {
436: static char buffer[80];
437: int r = m68k_pc_offset;
438: m68k_pc_offset += 2;
439:
440: if (using_ce020) {
441: sprintf (buffer, "(uae_u8)%s (%d)", ce020_prefetch_word, r);
442: count_read++;
443: } else if (using_ce) {
444: if (flags & GF_NOREFILL) {
445: strcpy (buffer, "(uae_u8)regs.irc");
446: } else {
447: sprintf (buffer, "(uae_u8)get_word_ce_prefetch (%d)", r + 2);
448: count_read++;
449: }
450: } else {
451: insn_n_cycles += 4;
452: if (using_prefetch) {
453: if (flags & GF_NOREFILL) {
454: sprintf (buffer, "(uae_u8)regs.irc"/*, r*/);
455: } else {
456: sprintf (buffer, "(uae_u8)get_word_prefetch (%d)", r + 2);
457: insn_n_cycles += 4;
458: count_read++;
459: }
460: } else if (using_indirect) {
461: sprintf (buffer, "get_ibytei (%d)", r);
462: insn_n_cycles += 4;
463: } else if (using_mmu) {
1.1.1.5 root 464: sprintf (buffer, "get_ibyte_mmu%s (%d)",
465: mmu_postfix, r);
1.1.1.4 root 466: insn_n_cycles += 4;
467: } else {
468: sprintf (buffer, "get_ibyte (%d)", r);
469: insn_n_cycles += 4;
470: }
471: }
472: return buffer;
473: }
474:
475: static void irc2ir (void)
476: {
477: if (!using_prefetch)
478: return;
479: printf ("\tregs.ir = regs.irc;\n");
480: if (using_ce)
481: printf ("\tipl_fetch ();\n");
482: }
483:
484: static int did_prefetch;
485:
486: static void fill_prefetch_2 (void)
487: {
488: if (!using_prefetch)
489: return;
490: if (using_ce)
491: printf ("\tget_word_ce_prefetch (%d);\n", m68k_pc_offset + 2);
492: else
493: printf ("\tget_word_prefetch (%d);\n", m68k_pc_offset + 2);
494: did_prefetch = 1;
495: count_read++;
496: insn_n_cycles += 4;
497: }
498:
499: static void fill_prefetch_1 (int o)
500: {
501: if (!using_prefetch)
502: return;
503: if (using_ce) {
504: printf ("\tget_word_ce_prefetch (%d);\n", o);
505: } else {
506: printf ("\tget_word_prefetch (%d);\n", o);
507: }
508: did_prefetch = 1;
509: count_read++;
510: insn_n_cycles += 4;
511: }
512:
513: static void fill_prefetch_full (void)
514: {
515: fill_prefetch_1 (0);
516: irc2ir ();
517: fill_prefetch_1 (2);
518: }
519:
520: static void fill_prefetch_0 (void)
521: {
522: if (!using_prefetch)
523: return;
524: if (using_ce)
525: printf ("\tget_word_ce_prefetch (0);\n");
526: else
527: printf ("\tget_word_prefetch (0);\n");
528: did_prefetch = 1;
529: count_read++;
530: insn_n_cycles += 4;
531: }
532:
533: static void dummy_prefetch (void)
534: {
535: int o = m68k_pc_offset + 2;
536: if (!using_prefetch)
537: return;
538: if (using_ce) {
539: printf ("\tget_wordi_ce (m68k_getpc () + %d);\n", o);
540: } else {
541: printf ("\tget_wordi (m68k_getpc () + %d);\n", o);
542: }
543: count_read++;
544: insn_n_cycles += 4;
545: }
546:
547: static void fill_prefetch_next_1 (void)
548: {
549: irc2ir ();
550: fill_prefetch_1 (m68k_pc_offset + 2);
551: }
552:
553: static void fill_prefetch_next (void)
554: {
555: fill_prefetch_next_1 ();
556: }
557:
558: #if 0
559: static void fill_prefetch_next_delay (int extracycles)
560: {
561: if (!using_prefetch)
562: return;
563: if (using_ce) {
564: if (extracycles > 0) {
565: printf("\t{\n");
566: fill_prefetch_next ();
567: printf("\tif (%d > 0) do_cycles(%d * CYCLE_UNIT / 2);\n",
568: extracycles, extracycles);
569: printf("\t}\n");
570: } else {
571: fill_prefetch_next ();
572: }
573: } else {
574: fill_prefetch_next ();
575: }
576: }
577: #endif
578:
579: static void fill_prefetch_finish (void)
580: {
581: if (did_prefetch || !using_prefetch)
582: return;
583: fill_prefetch_1 (m68k_pc_offset);
584: }
585:
586: static void setpc (const char *format, ...)
587: {
588: va_list parms;
589: char buffer[1000];
590:
591: va_start (parms, format);
592: _vsnprintf (buffer, 1000 - 1, format, parms);
593: va_end (parms);
594:
595: if (using_mmu)
596: printf ("\tm68k_setpc_mmu (%s);\n", buffer);
597: else
598: printf ("\tm68k_setpc (%s);\n", buffer);
599: }
600:
601: static void incpc (const char *format, ...)
602: {
603: va_list parms;
604: char buffer[1000];
605:
606: va_start (parms, format);
607: _vsnprintf (buffer, 1000 - 1, format, parms);
608: va_end (parms);
609:
610: if (using_mmu)
611: printf ("\tm68k_incpci (%s);\n", buffer);
612: else
613: printf ("\tm68k_incpc (%s);\n", buffer);
614: }
615:
616: static void sync_m68k_pc (void)
617: {
618: if (m68k_pc_offset == 0)
619: return;
620: incpc ("%d", m68k_pc_offset);
621: m68k_pc_offset = 0;
622: }
623:
624: static void gen_set_fault_pc (void)
625: {
626: if (!using_mmu)
627: return;
628: sync_m68k_pc ();
629: printf ("\tregs.fault_pc = m68k_getpci ();\n");
630: m68k_pc_offset = 0;
631: }
632:
633: static void syncmovepc (int getv, int flags)
634: {
635: #if 0
636: if (!(flags & GF_MOVE))
637: return;
638: if (getv == 1) {
639: sync_m68k_pc ();
640: //fill_prefetch_next ();
641: }
642: #endif
643: }
644:
645: /* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
646: * the calling routine handles Apdi and Aipi modes.
647: * gb-- movem == 2 means the same thing but for a MOVE16 instruction */
648:
1.1.1.6 ! root 649: /* fixup indicates if we want to fix up address registers in pre decrement
1.1.1.4 root 650: * or post increment mode now (0) or later (1). A value of 2 will then be
651: * used to do the actual fix up. This allows to do all memory readings
652: * before any register is modified, and so to rerun operation without
653: * side effect in case a bus fault is generated by any memory access.
654: * XJ - 2006/11/13 */
655:
656: static void genamode2 (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags, int fixup)
657: {
658: char namea[100];
659: int m68k_pc_offset_last = m68k_pc_offset;
660:
661: sprintf (namea, "%sa", name);
662:
663: start_brace ();
664: switch (mode) {
665: case Dreg:
666: if (movem)
667: abort ();
668: if (getv == 1)
669: switch (size) {
670: case sz_byte:
671: #ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
672: /* This causes the target compiler to generate better code on few systems */
673: printf ("\tuae_s8 %s = ((uae_u8*)&m68k_dreg (regs, %s))[3];\n", name, reg);
674: #else
675: printf ("\tuae_s8 %s = m68k_dreg (regs, %s);\n", name, reg);
676: #endif
677: break;
678: case sz_word:
679: #ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
680: printf ("\tuae_s16 %s = ((uae_s16*)&m68k_dreg (regs, %s))[1];\n", name, reg);
681: #else
682: printf ("\tuae_s16 %s = m68k_dreg (regs, %s);\n", name, reg);
683: #endif
684: break;
685: case sz_long:
686: printf ("\tuae_s32 %s = m68k_dreg (regs, %s);\n", name, reg);
687: break;
688: default:
689: abort ();
690: }
691: syncmovepc (getv, flags);
692: return;
693: case Areg:
694: if (movem)
695: abort ();
696: if (getv == 1)
697: switch (size) {
698: case sz_word:
699: printf ("\tuae_s16 %s = m68k_areg (regs, %s);\n", name, reg);
700: break;
701: case sz_long:
702: printf ("\tuae_s32 %s = m68k_areg (regs, %s);\n", name, reg);
703: break;
704: default:
705: abort ();
706: }
707: syncmovepc (getv, flags);
708: return;
709: case Aind: // (An)
710: printf ("\tuaecptr %sa = m68k_areg (regs, %s);\n", name, reg);
711: break;
712: case Aipi: // (An)+
713: printf ("\tuaecptr %sa = m68k_areg (regs, %s);\n", name, reg);
714: break;
715: case Apdi: // -(An)
716: printf ("\tuaecptr %sa;\n", name);
717: switch (size) {
718: case sz_byte:
719: if (movem)
720: printf ("\t%sa = m68k_areg (regs, %s);\n", name, reg);
721: else
722: printf ("\t%sa = m68k_areg (regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
723: break;
724: case sz_word:
725: printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
726: break;
727: case sz_long:
728: printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
729: break;
730: default:
731: abort ();
732: }
733: if (!(flags & GF_APDI)) {
734: addcycles000 (2);
735: insn_n_cycles += 2;
736: count_cycles_ea += 2;
737: }
738: break;
739: case Ad16: // (d16,An)
740: printf ("\tuaecptr %sa = m68k_areg (regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword (flags));
741: count_read_ea++;
742: break;
743: case Ad8r: // (d8,An,Xn)
744: printf ("\tuaecptr %sa;\n", name);
745: if (cpu_level > 1) {
746: if (next_cpu_level < 1)
747: next_cpu_level = 1;
748: sync_m68k_pc ();
749: start_brace ();
750: /* This would ordinarily be done in gen_nextiword, which we bypass. */
751: insn_n_cycles += 4;
752: if (using_ce020 || using_mmu)
753: printf ("\t%sa = x_get_disp_ea_020 (m68k_areg (regs, %s), x_next_iword ());\n", name, reg);
754: else
755: printf ("\t%sa = get_disp_ea_020 (m68k_areg (regs, %s), next_iword ());\n", name, reg);
756: } else {
757: if (!(flags & GF_AD8R)) {
758: addcycles000 (2);
759: insn_n_cycles += 2;
760: count_cycles_ea += 2;
761: }
762: printf ("\t%sa = get_disp_ea_000 (m68k_areg (regs, %s), %s);\n", name, reg, gen_nextiword (flags));
763: count_read_ea++;
764: }
765: break;
766: case PC16: // (d16,PC,Xn)
767: printf ("\tuaecptr %sa = m68k_getpc () + %d;\n", name, m68k_pc_offset);
768: printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
769: break;
770: case PC8r: // (d8,PC,Xn)
771: printf ("\tuaecptr tmppc;\n");
772: printf ("\tuaecptr %sa;\n", name);
773: if (cpu_level > 1) {
774: if (next_cpu_level < 1)
775: next_cpu_level = 1;
776: sync_m68k_pc ();
777: start_brace ();
778: /* This would ordinarily be done in gen_nextiword, which we bypass. */
779: insn_n_cycles += 4;
780: printf ("\ttmppc = m68k_getpc ();\n");
781: if (using_ce020 || using_mmu)
782: printf ("\t%sa = x_get_disp_ea_020 (tmppc, x_next_iword ());\n", name);
783: else
784: printf ("\t%sa = get_disp_ea_020 (tmppc, next_iword ());\n", name);
785: } else {
786: printf ("\ttmppc = m68k_getpc () + %d;\n", m68k_pc_offset);
787: if (!(flags & GF_PC8R)) {
788: addcycles000 (2);
789: insn_n_cycles += 2;
790: count_cycles_ea += 2;
791: }
792: printf ("\t%sa = get_disp_ea_000 (tmppc, %s);\n", name, gen_nextiword (flags));
793: }
794:
795: break;
796: case absw:
797: printf ("\tuaecptr %sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
798: break;
799: case absl:
800: gen_nextilong ("uaecptr", namea, flags);
801: count_read_ea += 2;
802: break;
803: case imm:
804: if (getv != 1)
805: abort ();
806: insn_n_cycles020++;
807: switch (size) {
808: case sz_byte:
809: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
810: count_read_ea++;
811: break;
812: case sz_word:
813: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
814: count_read_ea++;
815: break;
816: case sz_long:
817: gen_nextilong ("uae_s32", name, flags);
818: count_read_ea += 2;
819: break;
820: default:
821: abort ();
822: }
823: syncmovepc (getv, flags);
824: return;
825: case imm0:
826: if (getv != 1)
827: abort ();
828: printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
829: count_read_ea++;
830: syncmovepc (getv, flags);
831: return;
832: case imm1:
833: if (getv != 1)
834: abort ();
835: printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
836: count_read_ea++;
837: syncmovepc (getv, flags);
838: return;
839: case imm2:
840: if (getv != 1)
841: abort ();
842: gen_nextilong ("uae_s32", name, flags);
843: count_read_ea += 2;
844: syncmovepc (getv, flags);
845: return;
846: case immi:
847: if (getv != 1)
848: abort ();
849: printf ("\tuae_u32 %s = %s;\n", name, reg);
850: syncmovepc (getv, flags);
851: return;
852: default:
853: abort ();
854: }
855:
856: syncmovepc (getv, flags);
857:
858: /* We get here for all non-reg non-immediate addressing modes to
859: * actually fetch the value. */
860:
861: if ((using_prefetch || using_ce) && using_exception_3 && getv != 0 && size != sz_byte) {
862: int offset = 0;
863: if (flags & GF_MOVE) {
864: offset = m68k_pc_offset;
865: if (getv == 2)
866: offset += 2;
867: } else {
868: offset = m68k_pc_offset_last;
869: }
870: printf ("\tif (%sa & 1) {\n", name);
871: printf ("\t\texception3 (opcode, m68k_getpc () + %d, %sa);\n",
872: offset, name);
873: printf ("\t\tgoto %s;\n", endlabelstr);
874: printf ("\t}\n");
875: need_endlabel = 1;
876: start_brace ();
877: }
878:
879: if (flags & GF_PREFETCH)
880: fill_prefetch_next ();
881:
882: if (getv == 1) {
883: start_brace ();
884: if (using_ce020) {
885: switch (size) {
886: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = %s (%sa);\n", name, srcb, name); count_read++; break;
887: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = %s (%sa);\n", name, srcw, name); count_read++; break;
888: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = %s (%sa);\n", name, srcl, name); count_read += 2; break;
889: default: abort ();
890: }
891: } else if (using_ce) {
892: switch (size) {
893: case sz_byte: printf ("\tuae_s8 %s = get_byte_ce (%sa);\n", name, name); count_read++; break;
894: case sz_word: printf ("\tuae_s16 %s = get_word_ce (%sa);\n", name, name); count_read++; break;
895: case sz_long: printf ("\tuae_s32 %s = get_word_ce (%sa) << 16; %s |= get_word_ce (%sa + 2);\n", name, name, name, name); count_read += 2; break;
896: default: abort ();
897: }
898: } else if (using_mmu) {
899: if (flags & GF_FC) {
900: switch (size) {
1.1.1.5 root 901: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = sfc%s_get_byte (%sa);\n", name, mmu_postfix, name); break;
902: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = sfc%s_get_word (%sa);\n", name, mmu_postfix, name); break;
903: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = sfc%s_get_long (%sa);\n", name, mmu_postfix, name); break;
1.1.1.4 root 904: default: abort ();
905: }
906: } else {
907: switch (size) {
1.1.1.5 root 908: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = get_byte_mmu%s (%sa);\n", name, mmu_postfix, name); break;
909: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = get_word_mmu%s (%sa);\n", name, mmu_postfix, name); break;
910: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = get_long_mmu%s (%sa);\n", name, mmu_postfix, name); break;
1.1.1.4 root 911: default: abort ();
912: }
913: }
914: } else {
915: switch (size) {
916: case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = get_byte (%sa);\n", name, name); count_read++; break;
917: case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = get_word (%sa);\n", name, name); count_read++; break;
918: case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = get_long (%sa);\n", name, name); count_read += 2; break;
919: default: abort ();
920: }
921: }
922: }
923:
924: /* We now might have to fix up the register for pre-dec or post-inc
925: * addressing modes. */
926: if (!movem)
927: switch (mode) {
928: case Aipi:
929: if (fixup == 1) {
930: printf ("\tmmufixup[%d].reg = %s;\n", fixupcnt, reg);
931: printf ("\tmmufixup[%d].value = m68k_areg (regs, %s);\n", fixupcnt, reg);
932: }
933: switch (size) {
934: case sz_byte:
935: printf ("\tm68k_areg (regs, %s) += areg_byteinc[%s];\n", reg, reg);
936: break;
937: case sz_word:
938: printf ("\tm68k_areg (regs, %s) += 2;\n", reg);
939: break;
940: case sz_long:
941: printf ("\tm68k_areg (regs, %s) += 4;\n", reg);
942: break;
943: default:
944: abort ();
945: }
946: break;
947: case Apdi:
948: if (fixup == 1) {
949: printf ("\tmmufixup[%d].reg = %s;\n", fixupcnt, reg);
950: printf ("\tmmufixup[%d].value = m68k_areg (regs, %s);\n", fixupcnt, reg);
951: }
952: printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
953: break;
954: default:
955: break;
956: }
957: }
958:
959: static void genamode_fixup (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags, int fixup)
960: {
961: if (fixup != 2) {
962: genamode2 (mode, reg, size, name, getv, movem, flags, fixup);
963: } else {
964: if (!movem) {
965: switch ((int)mode)
966: {
967: case Aipi:
968: case Apdi:
969: printf ("\tmmufixup[0].reg = -1;\n"/*, fixupcnt*/);
970: break;
971: }
972: }
973: }
974: }
975:
976: static void genamode (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
977: {
978: genamode2 (mode, reg, size, name, getv, movem, flags, 0);
979: }
980: static void genamode_pre (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
981: {
982: genamode_fixup (mode, reg, size, name, getv, movem, flags, using_mmu ? 1 : 0);
983: }
984: static void genamode_post (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
985: {
986: if (using_mmu)
987: genamode_fixup (mode, reg, size, name, getv, movem, flags, 2);
988: }
989:
990: static void genastore_2 (const char *from, amodes mode, const char *reg, wordsizes size, const char *to, int store_dir, int flags)
991: {
992: switch (mode) {
993: case Dreg:
994: switch (size) {
995: case sz_byte:
996: printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
997: break;
998: case sz_word:
999: printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
1000: break;
1001: case sz_long:
1002: printf ("\tm68k_dreg (regs, %s) = (%s);\n", reg, from);
1003: break;
1004: default:
1005: abort ();
1006: }
1007: break;
1008: case Areg:
1009: switch (size) {
1010: case sz_word:
1011: printf ("\tm68k_areg (regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
1012: break;
1013: case sz_long:
1014: printf ("\tm68k_areg (regs, %s) = (%s);\n", reg, from);
1015: break;
1016: default:
1017: abort ();
1018: }
1019: break;
1020: case Aind:
1021: case Aipi:
1022: case Apdi:
1023: case Ad16:
1024: case Ad8r:
1025: case absw:
1026: case absl:
1027: case PC16:
1028: case PC8r:
1029: gen_set_fault_pc ();
1030: if (using_ce020) {
1031: switch (size) {
1032: case sz_byte:
1033: printf ("\t%s (%sa, %s);\n", dstb, to, from);
1034: count_write++;
1035: break;
1036: case sz_word:
1037: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1038: abort ();
1039: printf ("\t%s (%sa, %s);\n", dstw, to, from);
1040: count_write++;
1041: break;
1042: case sz_long:
1043: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1044: abort ();
1045: printf ("\t%s (%sa, %s);\n", dstl, to, from);
1046: count_write += 2;
1047: break;
1048: default:
1049: abort ();
1050: }
1051: } else if (using_ce) {
1052: switch (size) {
1053: case sz_byte:
1054: printf ("\tput_byte_ce (%sa, %s);\n", to, from);
1055: count_write++;
1056: break;
1057: case sz_word:
1058: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1059: abort ();
1060: printf ("\tput_word_ce (%sa, %s);\n", to, from);
1061: count_write++;
1062: break;
1063: case sz_long:
1064: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1065: abort ();
1066: if (store_dir)
1067: printf ("\tput_word_ce (%sa + 2, %s); put_word_ce (%sa, %s >> 16);\n", to, from, to, from);
1068: else
1069: printf ("\tput_word_ce (%sa, %s >> 16); put_word_ce (%sa + 2, %s);\n", to, from, to, from);
1070: count_write += 2;
1071: break;
1072: default:
1073: abort ();
1074: }
1075: } else if (using_mmu) {
1076: switch (size) {
1077: case sz_byte:
1078: insn_n_cycles += 4;
1079: if (flags & GF_FC)
1.1.1.5 root 1080: printf ("\tdfc%s_put_byte (%sa, %s);\n", mmu_postfix, to, from);
1.1.1.4 root 1081: else
1.1.1.5 root 1082: printf ("\tput_byte_mmu%s (%sa, %s);\n", mmu_postfix, to, from);
1.1.1.4 root 1083: break;
1084: case sz_word:
1085: insn_n_cycles += 4;
1086: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1087: abort ();
1088: if (flags & GF_FC)
1.1.1.5 root 1089: printf ("\tdfc%s_put_word (%sa, %s);\n", mmu_postfix, to, from);
1.1.1.4 root 1090: else
1.1.1.5 root 1091: printf ("\tput_word_mmu%s (%sa, %s);\n", mmu_postfix, to, from);
1.1.1.4 root 1092: break;
1093: case sz_long:
1094: insn_n_cycles += 8;
1095: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1096: abort ();
1097: if (flags & GF_FC)
1.1.1.5 root 1098: printf ("\tdfc%s_put_long (%sa, %s);\n", mmu_postfix, to, from);
1.1.1.4 root 1099: else
1.1.1.5 root 1100: printf ("\tput_long_mmu%s (%sa, %s);\n", mmu_postfix, to, from);
1.1.1.4 root 1101: break;
1102: default:
1103: abort ();
1104: }
1105: } else {
1106: switch (size) {
1107: case sz_byte:
1108: insn_n_cycles += 4;
1109: printf ("\tput_byte (%sa, %s);\n", to, from);
1110: count_write++;
1111: break;
1112: case sz_word:
1113: insn_n_cycles += 4;
1114: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1115: abort ();
1116: printf ("\tput_word (%sa, %s);\n", to, from);
1117: count_write++;
1118: break;
1119: case sz_long:
1120: insn_n_cycles += 8;
1121: if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
1122: abort ();
1123: printf ("\tput_long (%sa, %s);\n", to, from);
1124: count_write += 2;
1125: break;
1126: default:
1127: abort ();
1128: }
1129: }
1130: break;
1131: case imm:
1132: case imm0:
1133: case imm1:
1134: case imm2:
1135: case immi:
1136: abort ();
1137: break;
1138: default:
1139: abort ();
1140: }
1141: }
1142:
1143: static void genastore (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1144: {
1145: genastore_2 (from, mode, reg, size, to, 0, 0);
1146: }
1147: static void genastore_rev (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1148: {
1149: genastore_2 (from, mode, reg, size, to, 1, 0);
1150: }
1151: static void genastore_fc (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
1152: {
1153: genastore_2 (from, mode, reg, size, to, 1, GF_FC);
1154: }
1155:
1156: static void genmovemel (uae_u16 opcode)
1157: {
1158: char getcode[100];
1159: int size = table68k[opcode].size == sz_long ? 4 : 2;
1160:
1161: if (table68k[opcode].size == sz_long) {
1162: sprintf (getcode, "%s (srca)", srcl);
1163: } else {
1164: sprintf (getcode, "(uae_s32)(uae_s16)%s (srca)", srcw);
1165: }
1166: count_read += table68k[opcode].size == sz_long ? 2 : 1;
1167: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1168: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1169: printf ("\tuae_u16 regs_number = 0;\n");
1170: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, 0);
1171: start_brace ();
1172: printf ("\twhile (dmask) { m68k_dreg (regs, movem_index1[dmask]) = %s; srca += %d; dmask = movem_next[dmask]; regs_number++; }\n",
1173: getcode, size);
1174: printf ("\twhile (amask) { m68k_areg (regs, movem_index1[amask]) = %s; srca += %d; amask = movem_next[amask]; regs_number++; }\n",
1175: getcode, size);
1176:
1177: if (table68k[opcode].dmode == Aipi) {
1178: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1179: count_read++;
1180: }
1181: count_ncycles++;
1182:
1183: if (using_ce020 == 2) {
1184: if (table68k[opcode].size == sz_long)
1185: printf ("\tregs.ce030_instr_addcycles = regs_number * 8;\n");
1186: else
1187: printf ("\tregs.ce030_instr_addcycles = regs_number * 4;\n");
1188: }
1189:
1190: fill_prefetch_next ();
1191: }
1192:
1193: static void genmovemel_ce (uae_u16 opcode)
1194: {
1195: int size = table68k[opcode].size == sz_long ? 4 : 2;
1196: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1197: printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1198: printf ("\tuae_u32 v;\n");
1199: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA);
1200: if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
1201: addcycles000 (2);
1202: start_brace ();
1203: if (table68k[opcode].size == sz_long) {
1204: printf ("\twhile (dmask) { v = get_word_ce(srca) << 16; v |= get_word_ce(srca + 2); m68k_dreg (regs, movem_index1[dmask]) = v; srca += %d; dmask = movem_next[dmask]; }\n",
1205: size);
1206: printf ("\twhile (amask) { v = get_word_ce(srca) << 16; v |= get_word_ce(srca + 2); m68k_areg (regs, movem_index1[amask]) = v; srca += %d; amask = movem_next[amask]; }\n",
1207: size);
1208: } else {
1209: printf ("\twhile (dmask) { m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_ce(srca); srca += %d; dmask = movem_next[dmask]; }\n",
1210: size);
1211: printf ("\twhile (amask) { m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_ce(srca); srca += %d; amask = movem_next[amask]; }\n",
1212: size);
1213: }
1214: printf ("\tget_word_ce (srca);\n"); // and final extra word fetch that goes nowhere..
1215: count_read++;
1216: if (table68k[opcode].dmode == Aipi)
1217: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1218:
1219: count_ncycles++;
1220: fill_prefetch_next ();
1221: }
1222:
1223: static void genmovemle (uae_u16 opcode)
1224: {
1225: char putcode[100];
1226: int size = table68k[opcode].size == sz_long ? 4 : 2;
1227:
1228: if (table68k[opcode].size == sz_long) {
1229: sprintf (putcode, "%s (srca", dstl);
1230: } else {
1231: sprintf (putcode, "%s (srca", dstw);
1232: }
1233: count_write += table68k[opcode].size == sz_long ? 2 : 1;
1234:
1235: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1236: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, 0);
1237: start_brace ();
1238: printf ("\tuae_u16 regs_number = 0;\n");
1239: if (table68k[opcode].dmode == Apdi) {
1240: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
1241: if (!using_mmu)
1242: printf ("\tint type = get_cpu_model() >= 68020;\n");
1243: printf ("\twhile (amask) {\n");
1244: printf ("\t\tsrca -= %d;\n", size);
1245: if (!using_mmu)
1246: printf ("\t\tif (type) m68k_areg (regs, dstreg) = srca;\n");
1247: printf ("\t\t%s, m68k_areg (regs, movem_index2[amask]));\n", putcode);
1248: printf ("\t\tamask = movem_next[amask];\n");
1249: printf ("\t\tregs_number++;\n");
1250: printf ("\t}\n");
1251: printf ("\twhile (dmask) { srca -= %d; %s, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; regs_number++; }\n",
1252: size, putcode);
1253: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1254: } else {
1255: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1256: printf ("\twhile (dmask) { %s, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; regs_number++; }\n",
1257: putcode, size);
1258: printf ("\twhile (amask) { %s, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; regs_number++; }\n",
1259: putcode, size);
1260: }
1261:
1262: count_ncycles++;
1263: if (using_ce020 == 2) {
1264: if (table68k[opcode].size == sz_long)
1265: printf ("\tregs.ce030_instr_addcycles = regs_number * 8;\n");
1266: else
1267: printf ("\tregs.ce030_instr_addcycles = regs_number * 4;\n");
1268: }
1269: fill_prefetch_next ();
1270: }
1271:
1272: static void genmovemle_ce (uae_u16 opcode)
1273: {
1274: int size = table68k[opcode].size == sz_long ? 4 : 2;
1275: printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
1276: genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA);
1277:
1278: if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r) {
1279: addcycles000 (2);
1280: }
1281: start_brace ();
1282: if (table68k[opcode].size == sz_long) {
1283: if (table68k[opcode].dmode == Apdi) {
1284: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
1285: printf ("\twhile (amask) { srca -= %d; put_word_ce (srca, m68k_areg (regs, movem_index2[amask]) >> 16); put_word_ce (srca + 2, m68k_areg (regs, movem_index2[amask])); amask = movem_next[amask]; }\n",
1286: size);
1287: printf ("\twhile (dmask) { srca -= %d; put_word_ce (srca, m68k_dreg (regs, movem_index2[dmask]) >> 16); put_word_ce (srca + 2, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask];}\n",
1288: size);
1289: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1290: } else {
1291: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1292: printf ("\twhile (dmask) { put_word_ce (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16); put_word_ce (srca + 2, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
1293: size);
1294: printf ("\twhile (amask) { put_word_ce (srca, m68k_areg (regs, movem_index1[amask]) >> 16); put_word_ce (srca + 2, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask];}\n",
1295: size);
1296: }
1297: } else {
1298: if (table68k[opcode].dmode == Apdi) {
1299: printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
1300: printf ("\twhile (amask) { srca -= %d; put_word_ce (srca, m68k_areg (regs, movem_index2[amask])); amask = movem_next[amask]; }\n",
1301: size);
1302: printf ("\twhile (dmask) { srca -= %d; put_word_ce (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }\n",
1303: size);
1304: printf ("\tm68k_areg (regs, dstreg) = srca;\n");
1305: } else {
1306: printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
1307: printf ("\twhile (dmask) { put_word_ce (srca, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
1308: size);
1309: printf ("\twhile (amask) { put_word_ce (srca, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; }\n",
1310: size);
1311: }
1312: }
1313:
1314: count_ncycles++;
1315: fill_prefetch_next ();
1316: }
1317:
1318: static void duplicate_carry (int n)
1319: {
1320: int i;
1321: for (i = 0; i <= n; i++)
1322: printf ("\t");
1323: printf ("COPY_CARRY ();\n");
1324: }
1325:
1326: typedef enum
1327: {
1328: flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_z, flag_zn,
1329: flag_av, flag_sv
1330: }
1331: flagtypes;
1332:
1333: static void genflags_normal (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
1334: {
1335: char vstr[100], sstr[100], dstr[100];
1336: char usstr[100], udstr[100];
1337: char unsstr[100], undstr[100];
1338:
1339: switch (size) {
1340: case sz_byte:
1341: strcpy (vstr, "((uae_s8)(");
1342: strcpy (usstr, "((uae_u8)(");
1343: break;
1344: case sz_word:
1345: strcpy (vstr, "((uae_s16)(");
1346: strcpy (usstr, "((uae_u16)(");
1347: break;
1348: case sz_long:
1349: strcpy (vstr, "((uae_s32)(");
1350: strcpy (usstr, "((uae_u32)(");
1351: break;
1352: default:
1353: abort ();
1354: }
1355: strcpy (unsstr, usstr);
1356:
1357: strcpy (sstr, vstr);
1358: strcpy (dstr, vstr);
1359: strcat (vstr, value);
1360: strcat (vstr, "))");
1361: strcat (dstr, dst);
1362: strcat (dstr, "))");
1363: strcat (sstr, src);
1364: strcat (sstr, "))");
1365:
1366: strcpy (udstr, usstr);
1367: strcat (udstr, dst);
1368: strcat (udstr, "))");
1369: strcat (usstr, src);
1370: strcat (usstr, "))");
1371:
1372: strcpy (undstr, unsstr);
1373: strcat (unsstr, "-");
1374: strcat (undstr, "~");
1375: strcat (undstr, dst);
1376: strcat (undstr, "))");
1377: strcat (unsstr, src);
1378: strcat (unsstr, "))");
1379:
1380: switch (type) {
1381: case flag_logical_noclobber:
1382: case flag_logical:
1383: case flag_z:
1384: case flag_zn:
1385: case flag_av:
1386: case flag_sv:
1387: case flag_addx:
1388: case flag_subx:
1389: break;
1390:
1391: case flag_add:
1392: start_brace ();
1393: printf ("uae_u32 %s = %s + %s;\n", value, dstr, sstr);
1394: break;
1395: case flag_sub:
1396: case flag_cmp:
1397: start_brace ();
1398: printf ("uae_u32 %s = %s - %s;\n", value, dstr, sstr);
1399: break;
1400: }
1401:
1402: switch ((int)type) {
1403: case flag_logical_noclobber:
1404: case flag_logical:
1405: case flag_zn:
1406: break;
1407:
1408: case flag_add:
1409: case flag_sub:
1410: case flag_addx:
1411: case flag_subx:
1412: case flag_cmp:
1413: case flag_av:
1414: case flag_sv:
1415: start_brace ();
1416: printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
1417: printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
1418: printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
1419: break;
1420: }
1421:
1422: switch (type) {
1423: case flag_logical:
1424: printf ("\tCLEAR_CZNV ();\n");
1425: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1426: printf ("\tSET_NFLG (%s < 0);\n", vstr);
1427: break;
1428: case flag_logical_noclobber:
1429: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1430: printf ("\tSET_NFLG (%s < 0);\n", vstr);
1431: break;
1432: case flag_av:
1433: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
1434: break;
1435: case flag_sv:
1436: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
1437: break;
1438: case flag_z:
1439: printf ("\tSET_ZFLG (GET_ZFLG () & (%s == 0));\n", vstr);
1440: break;
1441: case flag_zn:
1442: printf ("\tSET_ZFLG (GET_ZFLG () & (%s == 0));\n", vstr);
1443: printf ("\tSET_NFLG (%s < 0);\n", vstr);
1444: break;
1445: case flag_add:
1446: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1447: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n");
1448: printf ("\tSET_CFLG (%s < %s);\n", undstr, usstr);
1449: duplicate_carry (0);
1450: printf ("\tSET_NFLG (flgn != 0);\n");
1451: break;
1452: case flag_sub:
1453: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1454: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
1455: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
1456: duplicate_carry (0);
1457: printf ("\tSET_NFLG (flgn != 0);\n");
1458: break;
1459: case flag_addx:
1460: printf ("\tSET_VFLG ((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
1461: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
1462: duplicate_carry (0);
1463: break;
1464: case flag_subx:
1465: printf ("\tSET_VFLG ((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
1466: printf ("\tSET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
1467: duplicate_carry (0);
1468: break;
1469: case flag_cmp:
1470: printf ("\tSET_ZFLG (%s == 0);\n", vstr);
1471: printf ("\tSET_VFLG ((flgs != flgo) && (flgn != flgo));\n");
1472: printf ("\tSET_CFLG (%s > %s);\n", usstr, udstr);
1473: printf ("\tSET_NFLG (flgn != 0);\n");
1474: break;
1475: }
1476: }
1477:
1478: static void genflags (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
1479: {
1480: /* Temporarily deleted 68k/ARM flag optimizations. I'd prefer to have
1481: them in the appropriate m68k.h files and use just one copy of this
1482: code here. The API can be changed if necessary. */
1483: if (optimized_flags) {
1484: switch (type) {
1485: case flag_add:
1486: case flag_sub:
1487: start_brace ();
1488: printf ("\tuae_u32 %s;\n", value);
1489: break;
1490:
1491: default:
1492: break;
1493: }
1494:
1495: /* At least some of those casts are fairly important! */
1496: switch (type) {
1497: case flag_logical_noclobber:
1498: printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
1499: if (strcmp (value, "0") == 0) {
1500: printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
1501: } else {
1502: switch (size) {
1503: case sz_byte: printf ("\toptflag_testb (regs, (uae_s8)(%s));\n", value); break;
1504: case sz_word: printf ("\toptflag_testw (regs, (uae_s16)(%s));\n", value); break;
1505: case sz_long: printf ("\toptflag_testl (regs, (uae_s32)(%s));\n", value); break;
1506: }
1507: printf ("\tIOR_CZNV (oldcznv);\n");
1508: }
1509: printf ("\t}\n");
1510: return;
1511: case flag_logical:
1512: if (strcmp (value, "0") == 0) {
1513: printf ("\tSET_CZNV (FLAGVAL_Z);\n");
1514: } else {
1515: switch (size) {
1516: case sz_byte: printf ("\toptflag_testb (regs, (uae_s8)(%s));\n", value); break;
1517: case sz_word: printf ("\toptflag_testw (regs, (uae_s16)(%s));\n", value); break;
1518: case sz_long: printf ("\toptflag_testl (regs, (uae_s32)(%s));\n", value); break;
1519: }
1520: }
1521: return;
1522:
1523: case flag_add:
1524: switch (size) {
1525: case sz_byte: printf ("\toptflag_addb (regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
1526: case sz_word: printf ("\toptflag_addw (regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
1527: case sz_long: printf ("\toptflag_addl (regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
1528: }
1529: return;
1530:
1531: case flag_sub:
1532: switch (size) {
1533: case sz_byte: printf ("\toptflag_subb (regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
1534: case sz_word: printf ("\toptflag_subw (regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
1535: case sz_long: printf ("\toptflag_subl (regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
1536: }
1537: return;
1538:
1539: case flag_cmp:
1540: switch (size) {
1541: case sz_byte: printf ("\toptflag_cmpb (regs, (uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
1542: case sz_word: printf ("\toptflag_cmpw (regs, (uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
1543: case sz_long: printf ("\toptflag_cmpl (regs, (uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
1544: }
1545: return;
1546:
1547: default:
1548: break;
1549: }
1550: }
1551:
1552: genflags_normal (type, size, value, src, dst);
1553: }
1554:
1555: static void force_range_for_rox (const char *var, wordsizes size)
1556: {
1557: /* Could do a modulo operation here... which one is faster? */
1558: switch (size) {
1559: case sz_long:
1560: printf ("\tif (%s >= 33) %s -= 33;\n", var, var);
1561: break;
1562: case sz_word:
1563: printf ("\tif (%s >= 34) %s -= 34;\n", var, var);
1564: printf ("\tif (%s >= 17) %s -= 17;\n", var, var);
1565: break;
1566: case sz_byte:
1567: printf ("\tif (%s >= 36) %s -= 36;\n", var, var);
1568: printf ("\tif (%s >= 18) %s -= 18;\n", var, var);
1569: printf ("\tif (%s >= 9) %s -= 9;\n", var, var);
1570: break;
1571: }
1572: }
1573:
1574: static const char *cmask (wordsizes size)
1575: {
1576: switch (size) {
1577: case sz_byte: return "0x80";
1578: case sz_word: return "0x8000";
1579: case sz_long: return "0x80000000";
1580: default: abort ();
1581: }
1582: }
1583:
1584: static int source_is_imm1_8 (struct instr *i)
1585: {
1586: return i->stype == 3;
1587: }
1588:
1589: static void shift_ce (amodes dmode, int size)
1590: {
1591: if (using_ce && isreg (dmode)) {
1592: int c = size == sz_long ? 4 : 2;
1593: printf ("\t{\n");
1594: printf ("\t\tint cycles = %d;\n", c);
1595: printf ("\t\tcycles += 2 * ccnt;\n");
1596: addcycles000_3 ("\t\t");
1597: printf ("\t}\n");
1598: count_cycles += c;
1599: }
1600: }
1601:
1602: // BCHG/BSET/BCLR Dx,Dx or #xx,Dx adds 2 cycles if bit number > 15
1603: static void bsetcycles (struct instr *curi)
1604: {
1605: if (curi->size == sz_byte) {
1606: printf ("\tsrc &= 7;\n");
1607: } else {
1608: printf ("\tsrc &= 31;\n");
1609: if (isreg (curi->dmode)) {
1610: addcycles000 (2);
1611: if (curi->mnemo != i_BTST && using_ce) {
1612: printf ("\tif (src > 15) do_cycles_ce000 (2);\n");
1613: count_ncycles++;
1614: }
1615: }
1616: }
1617: }
1618:
1619: static int islongimm (struct instr *curi)
1620: {
1621: return (curi->size == sz_long && (curi->smode == Dreg || curi->smode == imm));
1622: }
1623:
1624: static void gen_opcode (unsigned long int opcode)
1625: {
1626: struct instr *curi = table68k + opcode;
1627:
1628: insn_n_cycles = using_prefetch ? 0 : 4;
1629:
1.1.1.5 root 1630: /* Store the family of the instruction (used to check for pairing on ST,
1631: * for non-CPU cycles calculation and profiling)
1632: */
1633: printf ("\tOpcodeFamily = %d;\n", curi->mnemo);
1634: /* leave some space for patching in the current cycles later */
1.1.1.4 root 1635: if (!using_ce020) {
1.1.1.5 root 1636: printf("\tCurrentInstrCycles = \n");
1.1.1.4 root 1637: nCurInstrCycPos = ftell(stdout) - 5;
1638: }
1639: else if (using_ce020 == 2) {
1640: /* Initialize the cycle table to the general table by default */
1641: instr_table = TABLE_FALCON_CYCLES;
1642: instr_table_index = instr_index;
1643: no_return_cycles = false;
1644: }
1645:
1646: if (using_ce020) {
1647: if (using_ce020 == 2) {
1648: ce020_prefetch_long = "get_long_ce030_prefetch";
1649: ce020_prefetch_word = "get_word_ce030_prefetch";
1650: srcl = "get_long_ce030";
1651: dstl = "put_long_ce030";
1652: srcw = "get_word_ce030";
1653: dstw = "put_word_ce030";
1654: srcb = "get_byte_ce030";
1655: dstb = "put_byte_ce030";
1656: } else {
1657: ce020_prefetch_long = "get_long_ce020_prefetch";
1658: ce020_prefetch_word = "get_word_ce020_prefetch";
1659: srcl = "get_long_ce020";
1660: dstl = "put_long_ce020";
1661: srcw = "get_word_ce020";
1662: dstw = "put_word_ce020";
1663: srcb = "get_byte_ce020";
1664: dstb = "put_byte_ce020";
1665: }
1.1.1.5 root 1666: } else if (using_mmu && cpu_level == 3) {
1667: srcl = "get_long_mmu030";
1668: dstl = "put_long_mmu030";
1669: srcw = "get_word_mmu030";
1670: dstw = "put_word_mmu030";
1671: srcb = "get_byte_mmu030";
1672: dstb = "put_byte_mmu030";
1.1.1.4 root 1673: } else if (using_mmu) {
1674: srcl = "get_long_mmu";
1675: dstl = "put_long_mmu";
1676: srcw = "get_word_mmu";
1677: dstw = "put_word_mmu";
1678: srcb = "get_byte_mmu";
1679: dstb = "put_byte_mmu";
1680: } else if (using_ce) {
1681: srcl = "get_long_ce";
1682: dstl = "put_long_ce";
1683: srcw = "get_word_ce";
1684: dstw = "put_word_ce";
1685: srcb = "get_byte_ce";
1686: dstb = "put_byte_ce";
1687: } else {
1688: srcl = "get_long";
1689: dstl = "put_long";
1690: srcw = "get_word";
1691: dstw = "put_word";
1692: srcb = "get_byte";
1693: dstb = "put_byte";
1694: }
1695:
1696: insn_n_cycles020 = 0;
1697:
1698: start_brace ();
1699: m68k_pc_offset = 2;
1700: switch (curi->plev) {
1701: case 0: /* not privileged */
1702: break;
1703: case 1: /* unprivileged only on 68000 */
1704: if (cpu_level == 0)
1705: break;
1706: if (next_cpu_level < 0)
1707: next_cpu_level = 0;
1708:
1709: /* fall through */
1710: case 2: /* priviledged */
1711: printf ("if (!regs.s) { Exception (8, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1712: need_endlabel = 1;
1713: start_brace ();
1714: break;
1715: case 3: /* privileged if size == word */
1716: if (curi->size == sz_byte)
1717: break;
1718: printf ("if (!regs.s) { Exception (8, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
1719: need_endlabel = 1;
1720: start_brace ();
1721: break;
1722: }
1723: switch (curi->mnemo) {
1724: case i_OR:
1725: case i_AND:
1726: case i_EOR:
1727: {
1728: int c = 0;
1729: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1730: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
1731: printf ("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
1732: genflags (flag_logical, curi->size, "src", "", "");
1733: if (curi->dmode == Dreg && curi->size == sz_long) {
1734: c += 2;
1735: if (curi->smode == imm || curi->smode == Dreg)
1736: c += 2;
1737: }
1738: fill_prefetch_next ();
1739: if (c > 0)
1740: addcycles000 (c);
1741: genastore_rev ("src", curi->dmode, "dstreg", curi->size, "dst");
1742: break;
1743: }
1744: // all SR/CCR modifications have dummy read access
1745: case i_ORSR:
1746: case i_EORSR:
1747: printf ("\tMakeSR ();\n");
1748: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1749: dummy_prefetch ();
1750: if (curi->size == sz_byte) {
1751: printf ("\tsrc &= 0xFF;\n");
1752: }
1753: addcycles000 (8);
1754: fill_prefetch_next ();
1755: printf ("\tregs.sr %c= src;\n", curi->mnemo == i_EORSR ? '^' : '|');
1756: printf ("\tMakeFromSR ();\n");
1757: break;
1758: case i_ANDSR:
1759: printf ("\tMakeSR ();\n");
1760: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1761: dummy_prefetch ();
1762: if (curi->size == sz_byte) {
1763: printf ("\tsrc |= 0xFF00;\n");
1764: }
1765: addcycles000 (8);
1766: fill_prefetch_next ();
1767: printf ("\tregs.sr &= src;\n");
1768: printf ("\tMakeFromSR ();\n");
1769: break;
1770: case i_SUB:
1771: {
1772: int c = 0;
1773: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1774: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
1775: if (curi->dmode == Dreg) {
1776: if (curi->size == sz_long) {
1777: c += 2;
1778: if (curi->smode == imm || curi->smode == immi || curi->smode == Dreg)
1779: c += 2;
1780: }
1781: }
1782: fill_prefetch_next ();
1783: if (c > 0)
1784: addcycles000 (c);
1785: start_brace ();
1786: genflags (flag_sub, curi->size, "newv", "src", "dst");
1787: genastore_rev ("newv", curi->dmode, "dstreg", curi->size, "dst");
1788: break;
1789: }
1790: case i_SUBA:
1791: {
1792: int c = 0;
1793: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1794: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
1795: if (curi->smode == immi) {
1796: // SUBAQ.x is always 8 cycles
1797: c += 4;
1798: } else {
1799: c = curi->size == sz_long ? 2 : 4;
1800: if (islongimm (curi))
1801: c += 2;
1802: }
1803: fill_prefetch_next ();
1804: if (c > 0)
1805: addcycles000 (c);
1806: start_brace ();
1807: printf ("\tuae_u32 newv = dst - src;\n");
1808: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1809: break;
1810: }
1811: case i_SUBX:
1812: if (!isreg (curi->smode))
1813: addcycles000 (2);
1814: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1815: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1816: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1817: fill_prefetch_next ();
1818: if (curi->size == sz_long && isreg (curi->smode))
1819: addcycles000 (4);
1820: start_brace ();
1821: printf ("\tuae_u32 newv = dst - src - (GET_XFLG () ? 1 : 0);\n");
1822: genflags (flag_subx, curi->size, "newv", "src", "dst");
1823: genflags (flag_zn, curi->size, "newv", "", "");
1824: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1825: break;
1826: case i_SBCD:
1827: if (!isreg (curi->smode))
1828: addcycles000 (2);
1829: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1830: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1831: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1832: fill_prefetch_next ();
1833: start_brace ();
1834: printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
1835: printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
1836: printf ("\tuae_u16 newv, tmp_newv;\n");
1837: printf ("\tint bcd = 0;\n");
1838: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
1839: printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
1840: printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
1841: printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);\n");
1842: duplicate_carry (0);
1843: /* Manual says bits NV are undefined though a real 68040/060 don't change them */
1844: if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1845: if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1846: next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1847: genflags (flag_z, curi->size, "newv", "", "");
1848: } else {
1849: genflags (flag_zn, curi->size, "newv", "", "");
1850: printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
1851: }
1852: if (isreg (curi->smode))
1853: addcycles000 (2);
1854: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1855: break;
1856: case i_ADD:
1857: {
1858: int c = 0;
1859: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1860: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
1861: if (curi->dmode == Dreg) {
1862: if (curi->size == sz_long) {
1863: c += 2;
1864: if (curi->smode == imm || curi->smode == immi || curi->smode == Dreg)
1865: c += 2;
1866: }
1867: }
1868: fill_prefetch_next ();
1869: if (c > 0)
1870: addcycles000 (c);
1871: start_brace ();
1872: genflags (flag_add, curi->size, "newv", "src", "dst");
1873: genastore_rev ("newv", curi->dmode, "dstreg", curi->size, "dst");
1874: break;
1875: }
1876: case i_ADDA:
1877: {
1878: int c = 0;
1879: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1880: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
1881: if (curi->smode == immi) {
1882: // ADDAQ.x is always 8 cycles
1883: c += 4;
1884: } else {
1885: c = curi->size == sz_long ? 2 : 4;
1886: if (islongimm (curi))
1887: c += 2;
1888: }
1889: fill_prefetch_next ();
1890: if (c > 0)
1891: addcycles000 (c);
1892: start_brace ();
1893: printf ("\tuae_u32 newv = dst + src;\n");
1894: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
1895: break;
1896: }
1897: case i_ADDX:
1898: if (!isreg (curi->smode))
1899: addcycles000 (2);
1900: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1901: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1902: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1903: fill_prefetch_next ();
1904: if (curi->size == sz_long && isreg (curi->smode))
1905: addcycles000 (4);
1906: start_brace ();
1907: printf ("\tuae_u32 newv = dst + src + (GET_XFLG () ? 1 : 0);\n");
1908: genflags (flag_addx, curi->size, "newv", "src", "dst");
1909: genflags (flag_zn, curi->size, "newv", "", "");
1910: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1911: break;
1912: case i_ABCD:
1913: if (!isreg (curi->smode))
1914: addcycles000 (2);
1915: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1916: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
1917: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
1918: fill_prefetch_next ();
1919: start_brace ();
1920: printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);\n");
1921: printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
1922: printf ("\tuae_u16 newv, tmp_newv;\n");
1923: printf ("\tint cflg;\n");
1924: printf ("\tnewv = tmp_newv = newv_hi + newv_lo;");
1925: printf ("\tif (newv_lo > 9) { newv += 6; }\n");
1926: printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
1927: printf ("\tif (cflg) newv += 0x60;\n");
1928: printf ("\tSET_CFLG (cflg);\n");
1929: duplicate_carry (0);
1930: /* Manual says bits NV are undefined though a real 68040 don't change them */
1931: if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1932: if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1933: next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1934: genflags (flag_z, curi->size, "newv", "", "");
1935: }
1936: else {
1937: genflags (flag_zn, curi->size, "newv", "", "");
1938: printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
1939: }
1940: if (isreg (curi->smode))
1941: addcycles000 (2);
1942: genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
1943: break;
1944: case i_NEG:
1945: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1946: fill_prefetch_next ();
1947: if (isreg (curi->smode) && curi->size == sz_long)
1948: addcycles000 (2);
1949: start_brace ();
1950: genflags (flag_sub, curi->size, "dst", "src", "0");
1951: genastore_rev ("dst", curi->smode, "srcreg", curi->size, "src");
1952: break;
1953: case i_NEGX:
1954: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1955: fill_prefetch_next ();
1956: if (isreg (curi->smode) && curi->size == sz_long)
1957: addcycles000 (2);
1958: start_brace ();
1959: printf ("\tuae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);\n");
1960: genflags (flag_subx, curi->size, "newv", "src", "0");
1961: genflags (flag_zn, curi->size, "newv", "", "");
1962: genastore_rev ("newv", curi->smode, "srcreg", curi->size, "src");
1963: break;
1964: case i_NBCD:
1965: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1966: if (isreg (curi->smode))
1967: addcycles000 (2);
1968: fill_prefetch_next ();
1969: start_brace ();
1970: printf ("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
1971: printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1972: printf ("\tuae_u16 newv;\n");
1973: printf ("\tint cflg;\n");
1974: printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1975: printf ("\tnewv = newv_hi + newv_lo;");
1976: printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1977: printf ("\tif (cflg) newv -= 0x60;\n");
1978: printf ("\tSET_CFLG (cflg);\n");
1979: duplicate_carry(0);
1980: /* Manual says bits NV are undefined though a real 68040 don't change them */
1981: if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1982: if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1983: next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1984: genflags (flag_z, curi->size, "newv", "", "");
1985: }
1986: else {
1987: genflags (flag_zn, curi->size, "newv", "", "");
1988: }
1989: genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1990: break;
1991: case i_CLR:
1992: genamode (curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, 0);
1993: fill_prefetch_next ();
1994: if (isreg (curi->smode) && curi->size == sz_long)
1995: addcycles000 (2);
1996: genflags (flag_logical, curi->size, "0", "", "");
1997: genastore_rev ("0", curi->smode, "srcreg", curi->size, "src");
1998: break;
1999: case i_NOT:
2000: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2001: fill_prefetch_next ();
2002: if (isreg (curi->smode) && curi->size == sz_long)
2003: addcycles000 (2);
2004: start_brace ();
2005: printf ("\tuae_u32 dst = ~src;\n");
2006: genflags (flag_logical, curi->size, "dst", "", "");
2007: genastore_rev ("dst", curi->smode, "srcreg", curi->size, "src");
2008: break;
2009: case i_TST:
2010: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2011: fill_prefetch_next ();
2012: genflags (flag_logical, curi->size, "src", "", "");
2013: break;
2014: case i_BTST:
2015: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2016: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2017: fill_prefetch_next ();
2018: bsetcycles (curi);
2019: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
2020: break;
2021: case i_BCHG:
2022: case i_BCLR:
2023: case i_BSET:
2024: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2025: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2026: fill_prefetch_next ();
2027: bsetcycles (curi);
2028: // bclr needs 1 extra cycle
2029: if (curi->mnemo == i_BCLR && curi->dmode == Dreg)
2030: addcycles000 (2);
2031: if (curi->mnemo == i_BCHG) {
2032: printf ("\tdst ^= (1 << src);\n");
2033: printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
2034: } else if (curi->mnemo == i_BCLR) {
2035: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
2036: printf ("\tdst &= ~(1 << src);\n");
2037: } else if (curi->mnemo == i_BSET) {
2038: printf ("\tSET_ZFLG (1 ^ ((dst >> src) & 1));\n");
2039: printf ("\tdst |= (1 << src);\n");
2040: }
2041: genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
2042: break;
2043: case i_CMPM:
2044: // confirmed
2045: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
2046: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA);
2047: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
2048: fill_prefetch_next ();
2049: start_brace ();
2050: genflags (flag_cmp, curi->size, "newv", "src", "dst");
2051: break;
2052: case i_CMP:
2053: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2054: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2055: fill_prefetch_next ();
2056: if (curi->dmode == Dreg && curi->size == sz_long)
2057: addcycles000 (2);
2058: start_brace ();
2059: genflags (flag_cmp, curi->size, "newv", "src", "dst");
2060: break;
2061: case i_CMPA:
2062: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2063: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
2064: fill_prefetch_next ();
2065: addcycles000 (2);
2066: start_brace ();
2067: genflags (flag_cmp, sz_long, "newv", "src", "dst");
2068: break;
2069: /* The next two are coded a little unconventional, but they are doing
2070: * weird things... */
2071: case i_MVPRM: // MOVEP R->M
2072: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2073: printf ("\tuaecptr memp = m68k_areg (regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
1.1.1.5 root 2074: /* [NP] Use MovepByteNbr to keep track of each access inside a movep */
1.1.1.4 root 2075: if (curi->size == sz_word) {
2076: printf ("\tMovepByteNbr=1; %s (memp, src >> 8); MovepByteNbr=2; %s (memp + 2, src);\n", dstb, dstb);
2077: count_write += 2;
2078: } else {
2079: printf ("\tMovepByteNbr=1; %s (memp, src >> 24); MovepByteNbr=2; %s (memp + 2, src >> 16);\n", dstb, dstb);
2080: printf ("\tMovepByteNbr=3; %s (memp + 4, src >> 8); MovepByteNbr=4; %s (memp + 6, src);\n", dstb, dstb);
2081: count_write += 4;
2082: }
1.1.1.5 root 2083: printf ("\tMovepByteNbr=0;\n");
1.1.1.4 root 2084: fill_prefetch_next ();
2085: break;
2086: case i_MVPMR: // MOVEP M->R
2087: printf ("\tuaecptr memp = m68k_areg (regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
2088: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
1.1.1.5 root 2089: /* [NP] Use MovepByteNbr to keep track of each access inside a movep */
1.1.1.4 root 2090: if (curi->size == sz_word) {
1.1.1.5 root 2091: //printf ("\tuae_u16 val = (%s (memp) << 8) + %s (memp + 2);\n", srcb, srcb);
2092: printf ("\tuae_u16 val;\n");
2093: printf ("\tMovepByteNbr=1; val = (%s (memp) << 8);\n", srcb);
2094: printf ("\tMovepByteNbr=2; val += %s (memp + 2);\n", srcb);
1.1.1.4 root 2095: count_read += 2;
2096: } else {
1.1.1.5 root 2097: //printf ("\tuae_u32 val = (%s (memp) << 24) + (%s (memp + 2) << 16)\n", srcb, srcb);
2098: //printf (" + (%s (memp + 4) << 8) + %s (memp + 6);\n", srcb, srcb);
2099: printf ("\tuae_u32 val;\n");
2100: printf ("\tMovepByteNbr=1; val = (%s (memp) << 24);\n", srcb);
2101: printf ("\tMovepByteNbr=2; val += (%s (memp + 2) << 16);\n", srcb);
2102: printf ("\tMovepByteNbr=2; val += (%s (memp + 4) << 8);\n", srcb);
2103: printf ("\tMovepByteNbr=4; val += %s (memp + 6);\n", srcb);
1.1.1.4 root 2104: count_read += 4;
2105: }
1.1.1.5 root 2106: printf ("\tMovepByteNbr=0;\n");
1.1.1.4 root 2107: fill_prefetch_next ();
2108: genastore ("val", curi->dmode, "dstreg", curi->size, "dst");
2109: break;
2110: case i_MOVE:
2111: case i_MOVEA:
2112: {
2113: /* 2 MOVE instruction variants have special prefetch sequence:
2114: * - MOVE <ea>,-(An) = prefetch is before writes (Apdi)
2115: * - MOVE memory,(xxx).L = 2 prefetches after write
2116: * - all others = prefetch is done after writes
2117: *
2118: * - move.x xxx,[at least 1 extension word here] = fetch 1 extension word before (xxx)
2119: *
2120: */
2121: int prefetch_done = 0, flags;
2122: int dualprefetch = curi->dmode == absl && (curi->smode != Dreg && curi->smode != Areg && curi->smode != imm);
2123: genamode_pre (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_MOVE);
2124: flags = 1 | (dualprefetch ? GF_NOREFILL : 0);
2125: genamode2 (curi->dmode, "dstreg", curi->size, "dst", 2, 0, flags | GF_MOVE, 0);
2126: genamode_post (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2127: if (curi->mnemo == i_MOVEA && curi->size == sz_word)
2128: printf ("\tsrc = (uae_s32)(uae_s16)src;\n");
2129: if (curi->dmode == Apdi) {
2130: fill_prefetch_next ();
2131: prefetch_done = 1;
2132: }
2133: if (curi->mnemo == i_MOVE)
2134: genflags (flag_logical, curi->size, "src", "", "");
2135: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2136: sync_m68k_pc ();
2137: if (dualprefetch) {
2138: fill_prefetch_full ();
2139: prefetch_done = 1;
2140: }
2141: if (!prefetch_done)
2142: fill_prefetch_next ();
2143: }
2144: break;
2145: case i_MVSR2: // MOVE FROM SR
2146: genamode (curi->smode, "srcreg", sz_word, "src", 2, 0, 0);
2147: fill_prefetch_next ();
2148: if (isreg (curi->smode))
2149: addcycles000 (2);
2150: printf ("\tMakeSR ();\n");
2151: if (curi->size == sz_byte)
2152: genastore ("regs.sr & 0xff", curi->smode, "srcreg", sz_word, "src");
2153: else
2154: genastore ("regs.sr", curi->smode, "srcreg", sz_word, "src");
2155: break;
2156: case i_MV2SR: // MOVE TO SR
2157: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2158: if (curi->size == sz_byte) {
2159: // MOVE TO CCR
2160: dummy_prefetch ();
2161: addcycles000 (4);
2162: printf ("\tMakeSR ();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
2163: } else {
2164: // MOVE TO SR
2165: dummy_prefetch ();
2166: addcycles000 (4);
2167: printf ("\tregs.sr = src;\n");
2168: }
2169: printf ("\tMakeFromSR ();\n");
2170: fill_prefetch_next ();
2171: break;
2172: case i_SWAP:
2173: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
2174: fill_prefetch_next ();
2175: start_brace ();
2176: printf ("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
2177: genflags (flag_logical, sz_long, "dst", "", "");
2178: genastore ("dst", curi->smode, "srcreg", sz_long, "src");
2179: break;
2180: case i_EXG:
2181: // confirmed
2182: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2183: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2184: fill_prefetch_next ();
2185: addcycles000 (2);
2186: genastore ("dst", curi->smode, "srcreg", curi->size, "src");
2187: genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
2188: break;
2189: case i_EXT:
2190: // confirmed
2191: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
2192: fill_prefetch_next ();
2193: start_brace ();
2194: switch (curi->size) {
2195: case sz_byte: printf ("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
2196: case sz_word: printf ("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
2197: case sz_long: printf ("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
2198: default: abort ();
2199: }
2200: genflags (flag_logical,
2201: curi->size == sz_word ? sz_word : sz_long, "dst", "", "");
2202: genastore ("dst", curi->smode, "srcreg",
2203: curi->size == sz_word ? sz_word : sz_long, "src");
2204: break;
2205: case i_MVMEL:
2206: // confirmed
2207: if (using_ce)
2208: genmovemel_ce (opcode);
2209: else
2210: genmovemel (opcode);
2211: break;
2212: case i_MVMLE:
2213: // confirmed
2214: if (using_ce)
2215: genmovemle_ce (opcode);
2216: else
2217: genmovemle (opcode);
2218: break;
2219: case i_TRAP:
2220: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2221: gen_set_fault_pc ();
2222: sync_m68k_pc ();
2223: printf ("\tException (src + 32, 0 ,M68000_EXC_SRC_CPU);\n");
2224: did_prefetch = 1;
2225: m68k_pc_offset = 0;
2226: break;
2227: case i_MVR2USP:
2228: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2229: fill_prefetch_next ();
2230: printf ("\tregs.usp = src;\n");
2231: break;
2232: case i_MVUSP2R:
2233: genamode (curi->smode, "srcreg", curi->size, "src", 2, 0, 0);
2234: fill_prefetch_next ();
2235: genastore ("regs.usp", curi->smode, "srcreg", curi->size, "src");
2236: break;
2237: case i_RESET:
2238: fill_prefetch_next ();
2239: printf ("\tcpureset ();\n");
2240: addcycles000 (128);
2241: if (using_prefetch)
2242: printf ("\tregs.irc = get_iword (4);\n");
2243: break;
2244: case i_NOP:
2245: fill_prefetch_next ();
2246: break;
2247: case i_STOP:
2248: if (using_prefetch) {
2249: printf ("\tregs.sr = regs.irc;\n");
2250: m68k_pc_offset += 2;
2251: } else {
2252: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2253: printf ("\tregs.sr = src;\n");
2254: }
2255: printf ("\tMakeFromSR ();\n");
2256: printf ("\tm68k_setstopped ();\n");
2257: sync_m68k_pc ();
2258: // STOP does not prefetch anything
2259: did_prefetch = -1;
2260: break;
2261: case i_LPSTOP: /* 68060 */
2262: printf ("\tuae_u16 sw = get_iword (2);\n");
2263: printf ("\tuae_u16 sr;\n");
2264: printf ("\tif (sw != (0x100|0x80|0x40)) { Exception (4, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
2265: printf ("\tsr = get_iword (4);\n");
2266: printf ("\tif (!(sr & 0x8000)) { Exception (8, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
2267: printf ("\tregs.sr = sr;\n");
2268: printf ("\tMakeFromSR ();\n");
2269: printf ("\tm68k_setstopped();\n");
2270: m68k_pc_offset += 4;
2271: sync_m68k_pc ();
2272: fill_prefetch_full ();
2273: break;
2274: case i_RTE:
2275: if (cpu_level == 0) {
2276: genamode (Aipi, "7", sz_word, "sr", 1, 0, GF_NOREFILL);
2277: genamode (Aipi, "7", sz_long, "pc", 1, 0, GF_NOREFILL);
2278: printf ("\tregs.sr = sr;\n");
2279: setpc ("pc");
2280: printf ("\tMakeFromSR ();\n");
2281: } else {
1.1 root 2282: int old_brace_level = n_braces;
2283: if (next_cpu_level < 0)
2284: next_cpu_level = 0;
2285: printf ("\tuae_u16 newsr; uae_u32 newpc;\n");
2286: printf ("\tfor (;;) {\n");
2287: printf ("\t\tuaecptr a = m68k_areg (regs, 7);\n");
1.1.1.5 root 2288: printf ("\t\tuae_u16 sr = %s (a);\n", srcw);
2289: printf ("\t\tuae_u32 pc = %s (a + 2);\n", srcl);
2290: printf ("\t\tuae_u16 format = %s (a + 2 + 4);\n", srcw);
1.1 root 2291: printf ("\t\tint frame = format >> 12;\n");
2292: printf ("\t\tint offset = 8;\n");
2293: printf ("\t\tnewsr = sr; newpc = pc;\n");
2294: printf ("\t\tif (frame == 0x0) { m68k_areg (regs, 7) += offset; break; }\n");
2295: printf ("\t\telse if (frame == 0x1) { m68k_areg (regs, 7) += offset; }\n");
2296: printf ("\t\telse if (frame == 0x2) { m68k_areg (regs, 7) += offset + 4; break; }\n");
2297: printf ("\t\telse if (frame == 0x4) { m68k_areg (regs, 7) += offset + 8; break; }\n");
2298: if (using_mmu)
1.1.1.5 root 2299: printf ("\t\telse if (frame == 0x7) { m68k_do_rte_mmu%s (a); m68k_areg (regs, 7) += offset + 52; break; }\n", mmu_postfix);
1.1 root 2300: printf ("\t\telse if (frame == 0x8) { m68k_areg (regs, 7) += offset + 50; break; }\n");
2301: printf ("\t\telse if (frame == 0x9) { m68k_areg (regs, 7) += offset + 12; break; }\n");
2302: printf ("\t\telse if (frame == 0xa) { m68k_areg (regs, 7) += offset + 24; break; }\n");
2303: printf ("\t\telse if (frame == 0xb) { m68k_areg (regs, 7) += offset + 84; break; }\n");
2304: printf ("\t\telse { m68k_areg (regs, 7) += offset; Exception (14, 0 ,M68000_EXC_SRC_CPU); goto %s; }\n", endlabelstr);
2305: printf ("\t\tregs.sr = newsr; MakeFromSR ();\n}\n");
2306: pop_braces (old_brace_level);
2307: printf ("\tregs.sr = newsr; MakeFromSR ();\n");
2308: printf ("\tif (newpc & 1) {\n");
1.1.1.4 root 2309: printf ("\t\texception3i (0x%04lX, m68k_getpc (), newpc);\n", opcode);
1.1 root 2310: printf ("\t\tgoto %s;\n", endlabelstr);
2311: printf ("\t}\n");
2312: printf ("\t\tm68k_setpc (newpc);\n");
2313: printf ("\tipl_fetch ();\n");
2314: need_endlabel = 1;
1.1.1.4 root 2315: }
2316: instr_table = TABLE_FALCON_CYCLES_RTE;
2317: instr_table_index = 0;
2318: /* PC is set and prefetch filled. */
2319: m68k_pc_offset = 0;
2320: fill_prefetch_full ();
2321: break;
2322: case i_RTD:
2323: if (using_mmu) {
2324: genamode (curi->smode, "srcreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2325: genamode (Aipi, "7", sz_long, "pc", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2326: printf ("\tm68k_areg(regs, 7) += offs;\n");
2327: } else {
2328: genamode (Aipi, "7", sz_long, "pc", 1, 0, 0);
2329: genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0, 0);
2330: printf ("\tm68k_areg (regs, 7) += offs;\n");
2331: printf ("\tif (pc & 1) {\n");
2332: printf ("\t\texception3i (0x%04lX, m68k_getpc (), pc);\n", opcode);
1.1 root 2333: printf ("\t\tgoto %s;\n", endlabelstr);
1.1.1.4 root 2334: printf ("\t}\n");
2335: }
1.1 root 2336: printf ("\tif (pc & 1) {\n");
1.1.1.4 root 2337: printf ("\t\texception3i (0x%04lX, m68k_getpc(), pc);\n", opcode);
1.1 root 2338: printf ("\t\tgoto %s;\n", endlabelstr);
2339: printf ("\t}\n");
1.1.1.4 root 2340: setpc ("pc");
2341: /* PC is set and prefetch filled. */
2342: m68k_pc_offset = 0;
2343: fill_prefetch_full ();
1.1 root 2344: need_endlabel = 1;
1.1.1.4 root 2345: break;
2346: case i_LINK:
2347: // ce confirmed
2348: if (using_mmu) {
2349: genamode (curi->dmode, "dstreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2350: genamode (Apdi, "7", sz_long, "old", GENA_GETV_FETCH_ALIGN, GENA_MOVEM_DO_INC, 0);
2351: genamode (curi->smode, "srcreg", sz_long, "src", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
2352: genastore ("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
2353: printf ("\tm68k_areg(regs, 7) += offs;\n");
2354: genastore ("src", Apdi, "7", sz_long, "old");
2355: } else {
2356: genamode (Apdi, "7", sz_long, "old", 2, 0, GF_AA);
2357: genamode (curi->smode, "srcreg", sz_long, "src", 1, 0, GF_AA);
2358: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0, 0);
2359: genastore ("src", Apdi, "7", sz_long, "old");
2360: genastore ("m68k_areg (regs, 7)", curi->smode, "srcreg", sz_long, "src");
2361: printf ("\tm68k_areg (regs, 7) += offs;\n");
2362: fill_prefetch_next ();
2363: }
2364: break;
2365: case i_UNLK:
2366: // ce confirmed
2367: if (using_mmu) {
2368: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
1.1.1.5 root 2369: printf ("\tuae_s32 old = get_long_mmu%s (src);\n", mmu_postfix);
1.1 root 2370: printf ("\tm68k_areg (regs, 7) = src + 4;\n");
2371: printf ("\tm68k_areg (regs, srcreg) = old;\n");
1.1.1.4 root 2372: } else {
2373: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2374: printf ("\tm68k_areg (regs, 7) = src;\n");
2375: genamode (Aipi, "7", sz_long, "old", 1, 0, 0);
2376: fill_prefetch_next ();
2377: genastore ("old", curi->smode, "srcreg", curi->size, "src");
2378: }
2379: break;
2380: case i_RTS:
2381: printf ("\tuaecptr pc = m68k_getpc ();\n");
2382: if (using_ce020 == 1)
2383: printf ("\tm68k_do_rts_ce020 ();\n");
2384: else if (using_ce020 == 2)
2385: printf ("\tm68k_do_rts_ce030 ();\n");
2386: else if (using_ce)
2387: printf ("\tm68k_do_rts_ce ();\n");
2388: else if (using_indirect)
2389: printf ("\tm68k_do_rtsi ();\n");
2390: else if (using_mmu)
1.1.1.5 root 2391: printf ("\tm68k_do_rts_mmu%s ();\n", mmu_postfix);
1.1.1.4 root 2392: else
2393: printf ("\tm68k_do_rts ();\n");
1.1 root 2394: printf ("\tif (m68k_getpc () & 1) {\n");
2395: printf ("\t\tuaecptr faultpc = m68k_getpc ();\n");
2396: printf ("\t\tm68k_setpc (pc);\n");
1.1.1.4 root 2397: printf ("\t\texception3i (0x%04lX, pc, faultpc);\n", opcode);
1.1 root 2398: printf ("\t\tgoto %s;\n", endlabelstr);
2399: printf ("\t}\n");
1.1.1.4 root 2400: count_read += 2;
2401: m68k_pc_offset = 0;
2402: fill_prefetch_full ();
1.1 root 2403: need_endlabel = 1;
1.1.1.4 root 2404: break;
2405: case i_TRAPV:
2406: sync_m68k_pc ();
2407: fill_prefetch_next ();
2408: printf ("\tif (GET_VFLG ()) {\n");
2409: printf ("\t\tException (7, m68k_getpc () ,M68000_EXC_SRC_CPU);\n");
2410: printf ("\t\tgoto %s;\n", endlabelstr);
2411: printf ("\t}\n");
2412: need_endlabel = 1;
2413: break;
2414: case i_RTR:
2415: printf ("\tMakeSR ();\n");
2416: genamode_pre (Aipi, "7", sz_word, "sr", 1, 0, 0);
2417: genamode (Aipi, "7", sz_long, "pc", 1, 0, 0);
2418: genamode_post (Aipi, "7", sz_word, "sr", 1, 0, 0);
2419: printf ("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
2420: printf ("\tregs.sr |= sr;\n");
2421: setpc ("pc");
2422: printf ("\tMakeFromSR ();\n");
2423: m68k_pc_offset = 0;
2424: fill_prefetch_full ();
2425: break;
2426: case i_JSR: // TODO: check stack write order
2427: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA|GF_NOREFILL);
2428: start_brace ();
2429: printf ("\tuaecptr oldpc = m68k_getpc () + %d;\n", m68k_pc_offset);
2430: if (using_exception_3) {
2431: printf ("\tif (srca & 1) {\n");
2432: printf ("\t\texception3i (opcode, oldpc, srca);\n");
2433: printf ("\t\tgoto %s;\n", endlabelstr);
2434: printf ("\t}\n");
2435: need_endlabel = 1;
2436: }
2437: if (using_mmu) {
2438: printf ("\t%s (m68k_areg (regs, 7) - 4, oldpc);\n", dstl);
2439: printf ("\tm68k_areg (regs, 7) -= 4;\n");
2440: setpc ("srca");
2441: m68k_pc_offset = 0;
2442: } else {
2443: if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16)
2444: addcycles000 (2);
2445: setpc ("srca");
2446: m68k_pc_offset = 0;
2447: fill_prefetch_1 (0);
2448: if (curi->smode == Ad8r || curi->smode == PC8r)
2449: addcycles000 (6);
2450: printf ("\tm68k_areg (regs, 7) -= 4;\n");
2451: if (using_ce) {
2452: printf ("\tput_word_ce (m68k_areg (regs, 7), oldpc >> 16);\n");
2453: printf ("\tput_word_ce (m68k_areg (regs, 7) + 2, oldpc);\n");
2454: } else {
2455: printf ("\t%s (m68k_areg (regs, 7), oldpc);\n", dstl);
2456: }
2457: }
2458: count_write += 2;
2459: fill_prefetch_next ();
2460: break;
2461: case i_JMP:
2462: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA | ((curi->smode == Ad8r || curi->smode == PC8r) ? 0 : GF_NOREFILL));
2463: if (using_exception_3) {
2464: printf ("\tif (srca & 1) {\n");
2465: printf ("\t\texception3i (opcode, m68k_getpc () + 6, srca);\n");
2466: printf ("\t\tgoto %s;\n", endlabelstr);
2467: printf ("\t}\n");
2468: need_endlabel = 1;
2469: }
2470: if (curi->smode == Ad16 || curi->smode == Ad8r || curi->smode == absw || curi->smode == PC16 || curi->smode == PC8r)
2471: addcycles000 (2);
2472: setpc ("srca");
2473: m68k_pc_offset = 0;
2474: fill_prefetch_full ();
2475: break;
2476: case i_BSR:
2477: // .b and .w confirmed
2478: printf ("\tuae_s32 s;\n");
2479: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA|GF_NOREFILL);
2480: printf ("\ts = (uae_s32)src + 2;\n");
2481: if (using_exception_3) {
2482: printf ("\tif (src & 1) {\n");
2483: printf ("\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + s);\n");
2484: printf ("\t\tgoto %s;\n", endlabelstr);
2485: printf ("\t}\n");
2486: need_endlabel = 1;
2487: }
2488: addcycles000 (2);
2489: if (using_ce020 == 1) {
2490: printf ("\tm68k_do_bsr_ce020 (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2491: } else if (using_ce020 == 2) {
2492: printf ("\tm68k_do_bsr_ce030 (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2493: } else if (using_ce) {
2494: printf ("\tm68k_do_bsr_ce (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2495: } else if (using_indirect) {
2496: printf ("\tm68k_do_bsri (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2497: } else if (using_mmu) {
1.1.1.5 root 2498: printf ("\tm68k_do_bsr_mmu%s (m68k_getpc () + %d, s);\n", mmu_postfix, m68k_pc_offset);
1.1.1.4 root 2499: } else {
2500: printf ("\tm68k_do_bsr (m68k_getpc () + %d, s);\n", m68k_pc_offset);
2501: }
2502: count_write += 2;
2503: m68k_pc_offset = 0;
2504: fill_prefetch_full ();
2505: break;
2506: case i_Bcc:
2507: // bcc.b branch: idle cycle, prefetch, prefetch
2508: // bcc.b not branch: 2 idle cycles, prefetch
2509:
2510: instr_table = TABLE_FALCON_CYCLES_BCC;
2511:
2512: if (curi->size == sz_long) {
2513: if (cpu_level < 2) {
2514: addcycles000 (2);
2515: printf ("\tif (cctrue (%d)) {\n", curi->cc);
2516: printf ("\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + 1);\n");
2517: printf ("\t\tgoto %s;\n", endlabelstr);
2518: printf ("\t}\n");
2519: sync_m68k_pc ();
2520: irc2ir ();
2521: fill_prefetch_2 ();
2522: printf ("\tgoto %s;\n", endlabelstr);
2523: need_endlabel = 1;
2524: } else {
2525: if (next_cpu_level < 1)
2526: next_cpu_level = 1;
2527: }
2528: }
2529: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_NOREFILL);
2530: addcycles000 (2);
2531: printf ("\tif (!cctrue (%d)) goto didnt_jump;\n", curi->cc);
2532: if (using_exception_3) {
2533: printf ("\tif (src & 1) {\n");
2534: printf ("\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + 2 + (uae_s32)src);\n");
2535: printf ("\t\tgoto %s;\n", endlabelstr);
2536: printf ("\t}\n");
2537: need_endlabel = 1;
2538: }
2539: if (using_prefetch) {
2540: incpc ("(uae_s32)src + 2");
2541: fill_prefetch_full ();
2542: if (using_ce)
2543: printf ("\treturn;\n");
2544: else
2545: printf ("\treturn 10 * CYCLE_UNIT / 2;\n");
2546: } else {
2547: incpc ("(uae_s32)src + 2");
2548: instr_table_index = 0;
2549: returncycles ("", 10);
2550: }
2551: printf ("didnt_jump:;\n");
2552: need_endlabel = 1;
2553: sync_m68k_pc ();
2554: if (curi->size == sz_byte) {
2555: addcycles000 (2);
2556: irc2ir ();
2557: fill_prefetch_2 ();
2558: } else if (curi->size == sz_word) {
2559: addcycles000 (2);
2560: fill_prefetch_full ();
2561: } else {
2562: fill_prefetch_full ();
2563: }
2564: if (using_ce020 == 2) { /* For Falcon cycle exact timings only (CPU_EMU_21) */
2565: if (curi->size == sz_byte)
2566: instr_table_index = 1;
2567: else if (curi->size == sz_word)
2568: instr_table_index = 2;
2569: else
2570: instr_table_index = 3;
2571: }
2572: insn_n_cycles = curi->size == sz_byte ? 8 : 12;
2573: break;
2574: case i_LEA:
2575: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA);
2576: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, GF_AA);
2577: if (curi->smode == Ad8r || curi->smode == PC8r)
2578: addcycles000 (2);
2579: fill_prefetch_next ();
2580: if (curi->smode == Ad8r || curi->smode == PC8r)
2581: addcycles000 (2);
2582: genastore ("srca", curi->dmode, "dstreg", curi->size, "dst");
2583: break;
2584: case i_PEA:
2585: genamode (curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA);
2586: genamode (Apdi, "7", sz_long, "dst", 2, 0, GF_AA);
2587: if (curi->smode == Ad8r || curi->smode == PC8r)
2588: addcycles000 (2);
2589: if (!(curi->smode == absw || curi->smode == absl))
2590: fill_prefetch_next ();
2591: if (curi->smode == Ad8r || curi->smode == PC8r)
2592: addcycles000 (2);
2593: genastore ("srca", Apdi, "7", sz_long, "dst");
2594: if ((curi->smode == absw || curi->smode == absl))
2595: fill_prefetch_next ();
2596: break;
2597: case i_DBcc:
2598: no_return_cycles = true;
2599: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_NOREFILL);
2600: genamode (curi->dmode, "dstreg", curi->size, "offs", 1, 0, GF_AA | GF_NOREFILL);
2601: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2602: addcycles000 (2);
2603: printf ("\tif (!cctrue (%d)) {\n", curi->cc);
2604: printf ("\t");incpc ("(uae_s32)offs + 2");
2605: fill_prefetch_1 (0);
2606: printf ("\t");genastore ("(src - 1)", curi->smode, "srcreg", curi->size, "src");
2607:
2608: printf ("\t\tif (src) {\n");
2609: if (using_ce020 == 2)
2610: printf ("\t\t\tregs.ce030_instr_cycles = table_falcon_cycles_DBcc[0];\n");
2611:
2612: if (using_exception_3) {
2613: printf ("\t\t\tif (offs & 1) {\n");
2614: printf ("\t\t\t\texception3i (opcode, m68k_getpc () + 2, m68k_getpc () + 2 + (uae_s32)offs + 2);\n");
2615: printf ("\t\t\t\tgoto %s;\n", endlabelstr);
2616: printf ("\t\t\t}\n");
2617: need_endlabel = 1;
2618: }
2619: irc2ir ();
2620: fill_prefetch_1 (2);
2621: returncycles ("\t\t\t", 12);
2622: if (using_ce || using_ce020 == 2)
2623: printf ("\t\t\treturn;\n");
2624: printf ("\t\t}\n");
2625: if (using_ce020 == 2)
2626: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_DBcc[1];\n");
2627: printf ("\t} else {\n");
2628: if (using_ce020 == 2)
2629: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_DBcc[2];\n");
2630:
2631: addcycles000_2 ("\t\t", 2);
2632: printf ("\t}\n");
2633: setpc ("oldpc + %d", m68k_pc_offset);
2634: m68k_pc_offset = 0;
2635: fill_prefetch_full ();
2636: insn_n_cycles = 12;
2637: need_endlabel = 1;
2638: break;
2639: case i_Scc:
2640: // confirmed
2641: genamode (curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, 0);
2642: start_brace ();
2643: fill_prefetch_next();
2644: start_brace ();
2645: printf ("\tint val = cctrue (%d) ? 0xff : 0;\n", curi->cc);
2646: if (using_ce) {
2647: printf ("\tint cycles = 0;\n");
2648: if (isreg (curi->smode))
2649: printf ("\tif (val) cycles += 2;\n");
2650: addcycles000_3 ("\t");
2651: }
2652: genastore ("val", curi->smode, "srcreg", curi->size, "src");
2653: break;
2654: case i_DIVU:
2655: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2656: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2657: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
2658: printf ("\tCLEAR_CZNV ();\n");
2659: printf ("\tif (src == 0) {\n");
2660: if (cpu_level > 0) {
2661: /* 68020 sets V when dividing by zero and N if dst is negative
2662: * 68000 clears both
2663: */
2664: printf("\t\tSET_VFLG (1);\n");
2665: printf("\t\tif (dst < 0) SET_NFLG (1);\n");
2666: }
2667: incpc ("%d", m68k_pc_offset);
2668: printf ("\t\tException (5, oldpc ,M68000_EXC_SRC_CPU);\n");
2669: printf ("\t\tgoto %s;\n", endlabelstr);
2670: printf ("\t} else {\n");
2671: printf ("\t\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
2672: printf ("\t\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
2673: fill_prefetch_next ();
2674: if (using_ce) {
2675: start_brace ();
2676: printf ("\t\tint cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src));\n");
2677: addcycles000_3 ("\t\t");
2678: }
2679: /* The N flag appears to be set each time there is an overflow.
2680: * Weird. but 68020 only sets N when dst is negative.. */
2681: printf ("\t\tif (newv > 0xffff) {\n");
2682: printf ("\t\t\tSET_VFLG (1);\n");
2683: #ifdef UNDEF68020
2684: if (cpu_level >= 2)
2685: printf ("\t\t\tif (currprefs.cpu_level == 0 || dst < 0) SET_NFLG (®s, 1);\n");
2686: else /* ??? some 68000 revisions may not set NFLG when overflow happens.. */
2687: #endif
2688: printf ("\t\t\tSET_NFLG (1);\n");
2689: printf ("\t\t} else {\n");
2690: printf ("\t\t"); genflags (flag_logical, sz_word, "newv", "", "");
2691: printf ("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
2692: printf ("\t\t"); genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2693: printf ("\t\t}\n");
2694: sync_m68k_pc ();
2695: printf ("\t}\n");
2696: count_ncycles++;
2697: insn_n_cycles += 136 - (136 - 76) / 2; /* average */
2698: need_endlabel = 1;
2699: break;
2700: case i_DIVS:
2701: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2702: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2703: genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0, 0);
2704: printf ("\tCLEAR_CZNV ();\n");
2705: printf ("\tif (src == 0) {\n");
2706: if (cpu_level > 0) {
2707: /* 68020 sets V when dividing by zero. Z is also set.
2708: * 68000 clears both
2709: */
2710: printf("\t\tSET_VFLG (1);\n");
2711: printf("\t\tSET_ZFLG (1);\n");
2712: }
2713: incpc ("%d", m68k_pc_offset);
2714: printf ("\t\tException (5, oldpc ,M68000_EXC_SRC_CPU);\n");
2715: printf ("\t\tgoto %s;\n", endlabelstr);
2716: printf ("\t} else {\n");
2717: printf ("\t\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
2718: printf ("\t\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
2719: fill_prefetch_next ();
2720: if (using_ce) {
2721: start_brace ();
2722: printf ("\t\tint cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src));\n");
2723: addcycles000_3 ("\t\t");
2724: }
2725: printf ("\t\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {\n");
2726: printf ("\t\t\tSET_VFLG (1);\n");
2727: #ifdef UNDEF68020
2728: if (cpu_level > 0)
2729: printf ("\t\t\tif (currprefs.cpu_level == 0) SET_NFLG (®s, 1);\n");
2730: else
2731: #endif
2732: printf ("\t\t\tSET_NFLG (1);\n");
2733: printf ("\t\t} else {\n");
2734: printf ("\t\t\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
2735: genflags (flag_logical, sz_word, "newv", "", "");
2736: printf ("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
2737: printf ("\t\t"); genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2738: printf ("\t\t}\n");
2739: sync_m68k_pc ();
2740: printf ("\t}\n");
2741: count_ncycles++;
2742: insn_n_cycles += 156 - (156 - 120) / 2; /* average */
2743: need_endlabel = 1;
2744: break;
2745: case i_MULU:
2746: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2747: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0, 0);
2748: fill_prefetch_next();
2749: start_brace ();
2750: printf ("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
2751: if (using_ce)
2752: printf ("\tint cycles = 38 - 4, bits;\n");
2753: genflags (flag_logical, sz_long, "newv", "", "");
2754: if (using_ce) {
2755: printf ("\tfor(bits = 0; bits < 16 && src; bits++, src >>= 1)\n");
2756: printf ("\t\tif (src & 1) cycles += 2;\n");
2757: addcycles000_3 ("\t");
2758: }
2759: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2760: sync_m68k_pc ();
2761: count_cycles += 38 - 4;
2762: count_ncycles++;
2763: insn_n_cycles += (70 - 38) / 2 + 38; /* average */
2764: break;
2765: case i_MULS:
2766: genamode (curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
2767: genamode (curi->dmode, "dstreg", sz_word, "dst", 1, 0, 0);
2768: fill_prefetch_next();
2769: start_brace ();
2770: printf ("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
2771: if (using_ce) {
2772: printf ("\tint cycles = 38 - 4, bits;\n");
2773: printf ("\tuae_u32 usrc;\n");
2774: }
2775: genflags (flag_logical, sz_long, "newv", "", "");
2776: if (using_ce) {
2777: printf ("\tusrc = ((uae_u32)src) << 1;\n");
2778: printf ("\tfor(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)\n");
2779: printf ("\t\tif ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;\n");
2780: addcycles000_3 ("\t");
2781: }
2782: genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
2783: count_cycles += 38 - 4;
2784: count_ncycles++;
2785: insn_n_cycles += (70 - 38) / 2 + 38; /* average */
2786: break;
2787: case i_CHK:
2788: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2789: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
2790: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
2791: sync_m68k_pc ();
2792: addcycles000 (4);
2793: printf ("\tif (dst > src) {\n");
2794: printf ("\t\tSET_NFLG (0);\n");
2795: printf ("\t\tException (6, oldpc ,M68000_EXC_SRC_CPU);\n");
2796: printf ("\t\tgoto %s;\n", endlabelstr);
2797: printf ("\t}\n");
2798: addcycles000 (2);
2799: printf ("\tif ((uae_s32)dst < 0) {\n");
2800: printf ("\t\tSET_NFLG (1);\n");
2801: printf ("\t\tException (6, oldpc ,M68000_EXC_SRC_CPU);\n");
2802: printf ("\t\tgoto %s;\n", endlabelstr);
2803: printf ("\t}\n");
2804: fill_prefetch_next ();
2805: need_endlabel = 1;
2806: break;
2807: case i_CHK2:
2808: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
2809: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
2810: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
2811: fill_prefetch_0 ();
2812: printf ("\t{uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
2813: switch (curi->size) {
2814: case sz_byte:
2815: printf ("\tlower = (uae_s32)(uae_s8)%s (dsta); upper = (uae_s32)(uae_s8)%s (dsta + 1);\n", srcb, srcb);
2816: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
2817: if (using_ce020 == 2) {
2818: instr_table = TABLE_FALCON_CYCLES_CHK2_BW;
2819: instr_table_index = chk2_b_index * 2;
2820: chk2_b_index ++;
2821: }
2822: break;
2823: case sz_word:
2824: printf ("\tlower = (uae_s32)(uae_s16)%s (dsta); upper = (uae_s32)(uae_s16)%s (dsta + 2);\n", srcw, srcw);
2825: printf ("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
2826: if (using_ce020 == 2) {
2827: instr_table = TABLE_FALCON_CYCLES_CHK2_BW;
2828: instr_table_index = chk2_w_index * 2;
2829: chk2_w_index ++;
2830: }
2831: break;
2832: case sz_long:
2833: printf ("\tlower = %s (dsta); upper = %s (dsta + 4);\n", srcl, srcl);
2834: if (using_ce020 == 2) {
2835: instr_table = TABLE_FALCON_CYCLES_CHK2_L;
2836: instr_table_index = chk2_l_index * 2;
2837: chk2_l_index ++;
2838: }
2839: break;
2840: default:
2841: abort ();
2842: }
2843: printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
2844: printf ("\tSET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
2845: printf ("\tif ((extra & 0x800) && GET_CFLG ()) {\n");
2846: printf ("\t\tException (6, oldpc ,M68000_EXC_SRC_CPU);\n");
2847: instr_table_index ++; /* take the Exception cycle value in the CHK2 table */
2848: returncycles ("\t", 0);
2849: printf ("\t}\n}\n");
2850: instr_table_index --; /* take the No Exception cycle value in the CHK2 table */
2851: break;
2852:
2853: case i_ASR:
2854: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2855: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2856: fill_prefetch_next();
2857: start_brace ();
2858: switch (curi->size) {
2859: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2860: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2861: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2862: default: abort ();
2863: }
2864: printf ("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
2865: printf ("\tint ccnt = cnt & 63;\n");
2866: printf ("\tcnt &= 63;\n");
2867: printf ("\tCLEAR_CZNV ();\n");
2868: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2869: printf ("\t\tval = %s & (uae_u32)-sign;\n", bit_mask (curi->size));
2870: printf ("\t\tSET_CFLG (sign);\n");
2871: duplicate_carry (1);
2872: if (source_is_imm1_8 (curi))
2873: printf ("\t} else {\n");
2874: else {
2875: if (using_ce020 == 2){
2876: no_return_cycles = true;
2877: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_ASR[1];\n");
2878: }
2879: printf ("\t} else if (cnt > 0) {\n");
2880: if (using_ce020 == 2)
2881: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_ASR[0];\n");
2882: }
2883: printf ("\t\tval >>= cnt - 1;\n");
2884: printf ("\t\tSET_CFLG (val & 1);\n");
2885: duplicate_carry (1);
2886: printf ("\t\tval >>= 1;\n");
2887: printf ("\t\tval |= (%s << (%d - cnt)) & (uae_u32)-sign;\n",
2888: bit_mask (curi->size),
2889: bit_size (curi->size));
2890: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
2891: printf ("\t}\n");
2892: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2893: shift_ce (curi->dmode, curi->size);
2894: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2895: break;
2896: case i_ASL:
2897: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2898: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2899: fill_prefetch_next();
2900: start_brace ();
2901: switch (curi->size) {
2902: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2903: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2904: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2905: default: abort ();
2906: }
2907: printf ("\tint ccnt = cnt & 63;\n");
2908: printf ("\tcnt &= 63;\n");
2909: printf ("\tCLEAR_CZNV ();\n");
2910: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2911: printf ("\t\tSET_VFLG (val != 0);\n");
2912: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
2913: bit_size (curi->size));
2914: duplicate_carry (1);
2915: printf ("\t\tval = 0;\n");
2916: if (source_is_imm1_8 (curi))
2917: printf ("\t} else {\n");
2918: else
2919: printf ("\t} else if (cnt > 0) {\n");
2920: printf ("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
2921: bit_mask (curi->size),
2922: bit_size (curi->size) - 1,
2923: bit_mask (curi->size));
2924: printf ("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
2925: printf ("\t\tval <<= cnt - 1;\n");
2926: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
2927: duplicate_carry (1);
2928: printf ("\t\tval <<= 1;\n");
2929: printf ("\t\tval &= %s;\n", bit_mask (curi->size));
2930: printf ("\t}\n");
2931: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2932: shift_ce (curi->dmode, curi->size);
2933: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2934: break;
2935: case i_LSR:
2936: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2937: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2938: fill_prefetch_next();
2939: start_brace ();
2940: switch (curi->size) {
2941: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2942: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2943: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2944: default: abort ();
2945: }
2946: printf ("\tint ccnt = cnt & 63;\n");
2947: printf ("\tcnt &= 63;\n");
2948: printf ("\tCLEAR_CZNV ();\n");
2949: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2950: printf ("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
2951: bit_size (curi->size), bit_size (curi->size) - 1);
2952: duplicate_carry (1);
2953: printf ("\t\tval = 0;\n");
2954: if (source_is_imm1_8 (curi))
2955: printf ("\t} else {\n");
2956: else {
2957: if (using_ce020 == 2){
2958: no_return_cycles = true;
2959: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_LSD[1];\n");
2960: }
2961: printf ("\t} else if (cnt > 0) {\n");
2962: if (using_ce020 == 2)
2963: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_LSD[0];\n");
2964: }
2965: printf ("\t\tval >>= cnt - 1;\n");
2966: printf ("\t\tSET_CFLG (val & 1);\n");
2967: duplicate_carry (1);
2968: printf ("\t\tval >>= 1;\n");
2969: printf ("\t}\n");
2970: genflags (flag_logical_noclobber, curi->size, "val", "", "");
2971: shift_ce (curi->dmode, curi->size);
2972: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
2973: break;
2974: case i_LSL:
2975: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
2976: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
2977: fill_prefetch_next();
2978: start_brace ();
2979: switch (curi->size) {
2980: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
2981: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
2982: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
2983: default: abort ();
2984: }
2985: printf ("\tint ccnt = cnt & 63;\n");
2986: printf ("\tcnt &= 63;\n");
2987: printf ("\tCLEAR_CZNV ();\n");
2988: printf ("\tif (cnt >= %d) {\n", bit_size (curi->size));
2989: printf ("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n", bit_size (curi->size));
2990: duplicate_carry (1);
2991: printf ("\t\tval = 0;\n");
2992: if (source_is_imm1_8 (curi))
2993: printf ("\t} else {\n");
2994: else {
2995: if (using_ce020 == 2){
2996: no_return_cycles = true;
2997: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_LSD[1];\n");
2998: }
2999: printf ("\t} else if (cnt > 0) {\n");
3000: if (using_ce020 == 2)
3001: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_LSD[0];\n");
3002: }
3003: printf ("\t\tval <<= (cnt - 1);\n");
3004: printf ("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
3005: duplicate_carry (1);
3006: printf ("\t\tval <<= 1;\n");
3007: printf ("\tval &= %s;\n", bit_mask (curi->size));
3008: printf ("\t}\n");
3009: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3010: shift_ce (curi->dmode, curi->size);
3011: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3012: break;
3013: case i_ROL:
3014: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3015: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3016: fill_prefetch_next ();
3017: start_brace ();
3018: switch (curi->size) {
3019: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3020: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3021: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3022: default: abort ();
3023: }
3024: printf ("\tint ccnt = cnt & 63;\n");
3025: printf ("\tcnt &= 63;\n");
3026: printf ("\tCLEAR_CZNV ();\n");
3027: if (source_is_imm1_8 (curi))
3028: printf ("{");
3029: else
3030: printf ("\tif (cnt > 0) {\n");
3031: printf ("\tuae_u32 loval;\n");
3032: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
3033: printf ("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
3034: printf ("\tval <<= cnt;\n");
3035: printf ("\tval |= loval;\n");
3036: printf ("\tval &= %s;\n", bit_mask (curi->size));
3037: printf ("\tSET_CFLG (val & 1);\n");
3038: printf ("}\n");
3039: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3040: shift_ce (curi->dmode, curi->size);
3041: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3042: break;
3043: case i_ROR:
3044: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3045: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3046: fill_prefetch_next ();
3047: start_brace ();
3048: switch (curi->size) {
3049: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3050: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3051: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3052: default: abort ();
3053: }
3054: printf ("\tint ccnt = cnt & 63;\n");
3055: printf ("\tcnt &= 63;\n");
3056: printf ("\tCLEAR_CZNV ();\n");
3057: if (source_is_imm1_8 (curi))
3058: printf ("{");
3059: else
3060: printf ("\tif (cnt > 0) {");
3061: printf ("\tuae_u32 hival;\n");
3062: printf ("\tcnt &= %d;\n", bit_size (curi->size) - 1);
3063: printf ("\thival = val << (%d - cnt);\n", bit_size (curi->size));
3064: printf ("\tval >>= cnt;\n");
3065: printf ("\tval |= hival;\n");
3066: printf ("\tval &= %s;\n", bit_mask (curi->size));
3067: printf ("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
3068: printf ("\t}\n");
3069: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3070: shift_ce (curi->dmode, curi->size);
3071: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3072: break;
3073: case i_ROXL:
3074: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3075: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3076: fill_prefetch_next ();
3077: start_brace ();
3078: switch (curi->size) {
3079: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3080: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3081: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3082: default: abort ();
3083: }
3084: printf ("\tint ccnt = cnt & 63;\n");
3085: printf ("\tcnt &= 63;\n");
3086: printf ("\tCLEAR_CZNV ();\n");
3087: if (source_is_imm1_8 (curi))
3088: printf ("{");
3089: else {
3090: force_range_for_rox ("cnt", curi->size);
3091: printf ("\tif (cnt > 0) {\n");
3092: }
3093: printf ("\tcnt--;\n");
3094: printf ("\t{\n\tuae_u32 carry;\n");
3095: printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
3096: printf ("\tcarry = loval & 1;\n");
3097: printf ("\tval = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);\n");
3098: printf ("\tSET_XFLG (carry);\n");
3099: printf ("\tval &= %s;\n", bit_mask (curi->size));
3100: printf ("\t} }\n");
3101: printf ("\tSET_CFLG (GET_XFLG ());\n");
3102: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3103: shift_ce (curi->dmode, curi->size);
3104: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3105: break;
3106: case i_ROXR:
3107: genamode (curi->smode, "srcreg", curi->size, "cnt", 1, 0, 0);
3108: genamode (curi->dmode, "dstreg", curi->size, "data", 1, 0, 0);
3109: fill_prefetch_next ();
3110: start_brace ();
3111: switch (curi->size) {
3112: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3113: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3114: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3115: default: abort ();
3116: }
3117: printf ("\tint ccnt = cnt & 63;\n");
3118: printf ("\tcnt &= 63;\n");
3119: printf ("\tCLEAR_CZNV ();\n");
3120: if (source_is_imm1_8 (curi))
3121: printf ("{");
3122: else {
3123: force_range_for_rox ("cnt", curi->size);
3124: printf ("\tif (cnt > 0) {\n");
3125: }
3126: printf ("\tcnt--;\n");
3127: printf ("\t{\n\tuae_u32 carry;\n");
3128: printf ("\tuae_u32 hival = (val << 1) | GET_XFLG ();\n");
3129: printf ("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
3130: printf ("\tval >>= cnt;\n");
3131: printf ("\tcarry = val & 1;\n");
3132: printf ("\tval >>= 1;\n");
3133: printf ("\tval |= hival;\n");
3134: printf ("\tSET_XFLG (carry);\n");
3135: printf ("\tval &= %s;\n", bit_mask (curi->size));
3136: printf ("\t} }\n");
3137: printf ("\tSET_CFLG (GET_XFLG ());\n");
3138: genflags (flag_logical_noclobber, curi->size, "val", "", "");
3139: shift_ce (curi->dmode, curi->size);
3140: genastore ("val", curi->dmode, "dstreg", curi->size, "data");
3141: break;
3142: case i_ASRW:
3143: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3144: fill_prefetch_next ();
3145: start_brace ();
3146: switch (curi->size) {
3147: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3148: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3149: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3150: default: abort ();
3151: }
3152: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
3153: printf ("\tuae_u32 cflg = val & 1;\n");
3154: printf ("\tval = (val >> 1) | sign;\n");
3155: genflags (flag_logical, curi->size, "val", "", "");
3156: printf ("\tSET_CFLG (cflg);\n");
3157: duplicate_carry (0);
3158: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3159: break;
3160: case i_ASLW:
3161: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3162: fill_prefetch_next ();
3163: start_brace ();
3164: switch (curi->size) {
3165: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3166: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3167: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3168: default: abort ();
3169: }
3170: printf ("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
3171: printf ("\tuae_u32 sign2;\n");
3172: printf ("\tval <<= 1;\n");
3173: genflags (flag_logical, curi->size, "val", "", "");
3174: printf ("\tsign2 = %s & val;\n", cmask (curi->size));
3175: printf ("\tSET_CFLG (sign != 0);\n");
3176: duplicate_carry (0);
3177:
3178: printf ("\tSET_VFLG (GET_VFLG () | (sign2 != sign));\n");
3179: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3180: break;
3181: case i_LSRW:
3182: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3183: fill_prefetch_next ();
3184: start_brace ();
3185: switch (curi->size) {
3186: case sz_byte: printf ("\tuae_u32 val = (uae_u8)data;\n"); break;
3187: case sz_word: printf ("\tuae_u32 val = (uae_u16)data;\n"); break;
3188: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3189: default: abort ();
3190: }
3191: printf ("\tuae_u32 carry = val & 1;\n");
3192: printf ("\tval >>= 1;\n");
3193: genflags (flag_logical, curi->size, "val", "", "");
3194: printf ("\tSET_CFLG (carry);\n");
3195: duplicate_carry (0);
3196: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3197: break;
3198: case i_LSLW:
3199: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3200: fill_prefetch_next ();
3201: start_brace ();
3202: switch (curi->size) {
3203: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3204: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3205: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3206: default: abort ();
3207: }
3208: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
3209: printf ("\tval <<= 1;\n");
3210: genflags (flag_logical, curi->size, "val", "", "");
3211: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
3212: duplicate_carry (0);
3213: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3214: break;
3215: case i_ROLW:
3216: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3217: fill_prefetch_next ();
3218: start_brace ();
3219: switch (curi->size) {
3220: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3221: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3222: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3223: default: abort ();
3224: }
3225: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
3226: printf ("\tval <<= 1;\n");
3227: printf ("\tif (carry) val |= 1;\n");
3228: genflags (flag_logical, curi->size, "val", "", "");
3229: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
3230: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3231: break;
3232: case i_RORW:
3233: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3234: fill_prefetch_next ();
3235: start_brace ();
3236: switch (curi->size) {
3237: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3238: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3239: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3240: default: abort ();
3241: }
3242: printf ("\tuae_u32 carry = val & 1;\n");
3243: printf ("\tval >>= 1;\n");
3244: printf ("\tif (carry) val |= %s;\n", cmask (curi->size));
3245: genflags (flag_logical, curi->size, "val", "", "");
3246: printf ("\tSET_CFLG (carry);\n");
3247: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3248: break;
3249: case i_ROXLW:
3250: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3251: fill_prefetch_next ();
3252: start_brace ();
3253: switch (curi->size) {
3254: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3255: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3256: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3257: default: abort ();
3258: }
3259: printf ("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
3260: printf ("\tval <<= 1;\n");
3261: printf ("\tif (GET_XFLG ()) val |= 1;\n");
3262: genflags (flag_logical, curi->size, "val", "", "");
3263: printf ("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
3264: duplicate_carry (0);
3265: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3266: break;
3267: case i_ROXRW:
3268: genamode (curi->smode, "srcreg", curi->size, "data", 1, 0, 0);
3269: fill_prefetch_next ();
3270: start_brace ();
3271: switch (curi->size) {
3272: case sz_byte: printf ("\tuae_u8 val = data;\n"); break;
3273: case sz_word: printf ("\tuae_u16 val = data;\n"); break;
3274: case sz_long: printf ("\tuae_u32 val = data;\n"); break;
3275: default: abort ();
3276: }
3277: printf ("\tuae_u32 carry = val & 1;\n");
3278: printf ("\tval >>= 1;\n");
3279: printf ("\tif (GET_XFLG ()) val |= %s;\n", cmask (curi->size));
3280: genflags (flag_logical, curi->size, "val", "", "");
3281: printf ("\tSET_CFLG (carry);\n");
3282: duplicate_carry (0);
3283: genastore ("val", curi->smode, "srcreg", curi->size, "data");
3284: break;
3285: case i_MOVEC2:
3286: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3287: fill_prefetch_next ();
3288: start_brace ();
3289: printf ("\tint regno = (src >> 12) & 15;\n");
3290: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
3291: printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
3292: break;
3293: case i_MOVE2C:
3294: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3295: fill_prefetch_next ();
3296: start_brace ();
3297: printf ("\tint regno = (src >> 12) & 15;\n");
3298: printf ("\tuae_u32 *regp = regs.regs + regno;\n");
3299: printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
3300: if (using_ce020 == 2) {
3301: no_return_cycles = true;
3302: printf ("\tif((src & 0xFFF) < 3)\n");
3303: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_MOVEC[1];\n");
3304: printf ("\telse\n");
3305: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_MOVEC[0];\n");
3306: }
3307: break;
3308: case i_CAS:
3309: {
3310: if (using_ce020 == 2) {
3311: no_return_cycles = true;
3312: if (curi->size == sz_byte) {
3313: instr_table = TABLE_FALCON_CYCLES_CAS_BW;
3314: instr_table_index = cas_b_index * 2;
3315: cas_b_index ++;
3316: }
3317: else if (curi->size == sz_word) {
3318: instr_table = TABLE_FALCON_CYCLES_CAS_BW;
3319: instr_table_index = cas_w_index * 2;
3320: cas_w_index ++;
3321: }
3322: else {
3323: instr_table = TABLE_FALCON_CYCLES_CAS_L;
3324: instr_table_index = cas_l_index * 2;
3325: cas_l_index ++;
3326: }
3327: }
3328: int old_brace_level;
3329: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3330: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3331: fill_prefetch_0 ();
3332: start_brace ();
3333: printf ("\tint ru = (src >> 6) & 7;\n");
3334: printf ("\tint rc = src & 7;\n");
3335: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, rc)", "dst");
3336: printf ("\tif (GET_ZFLG ())");
3337: old_brace_level = n_braces;
3338: start_brace ();
3339: genastore ("(m68k_dreg (regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
3340: if (using_ce020 == 2)
3341: printf ("\tregs.ce030_instr_cycles = %s[%d];\n", falcon_cycles_tables[instr_table], instr_table_index);
3342: pop_braces (old_brace_level);
3343: printf ("else");
3344: start_brace ();
3345: printf ("m68k_dreg (regs, rc) = dst;\n");
3346: if (using_ce020 == 2)
3347: printf ("\tregs.ce030_instr_cycles = %s[%d];\n", falcon_cycles_tables[instr_table], instr_table_index + 1);
3348: pop_braces (old_brace_level);
3349: }
3350: break;
3351: case i_CAS2:
3352: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3353: printf ("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
3354: printf ("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
3355: if (curi->size == sz_word) {
3356: int old_brace_level = n_braces;
3357: printf ("\tuae_u16 dst1 = %s (rn1), dst2 = %s (rn2);\n", srcw, srcw);
3358: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, (extra >> 16) & 7)", "dst1");
3359: printf ("\tif (GET_ZFLG ()) {\n");
3360: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, extra & 7)", "dst2");
3361: printf ("\tif (GET_ZFLG ()) {\n");
3362: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 22) & 7));\n", dstw);
3363: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 6) & 7));\n", dstw);
3364: printf ("\t}}\n");
3365: pop_braces (old_brace_level);
3366: printf ("\tif (! GET_ZFLG ()) {\n");
3367: printf ("\tm68k_dreg (regs, (extra >> 22) & 7) = (m68k_dreg (regs, (extra >> 22) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
3368: printf ("\tm68k_dreg (regs, (extra >> 6) & 7) = (m68k_dreg (regs, (extra >> 6) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
3369: printf ("\t}\n");
3370: } else {
3371: int old_brace_level = n_braces;
3372: printf ("\tuae_u32 dst1 = %s (rn1), dst2 = %s (rn2);\n", srcl, srcl);
3373: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, (extra >> 16) & 7)", "dst1");
3374: printf ("\tif (GET_ZFLG ()) {\n");
3375: genflags (flag_cmp, curi->size, "newv", "m68k_dreg (regs, extra & 7)", "dst2");
3376: printf ("\tif (GET_ZFLG ()) {\n");
3377: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 22) & 7));\n", dstl);
3378: printf ("\t%s (rn1, m68k_dreg (regs, (extra >> 6) & 7));\n", dstl);
3379: printf ("\t}}\n");
3380: pop_braces (old_brace_level);
3381: printf ("\tif (! GET_ZFLG ()) {\n");
3382: printf ("\tm68k_dreg (regs, (extra >> 22) & 7) = dst1;\n");
3383: printf ("\tm68k_dreg (regs, (extra >> 6) & 7) = dst2;\n");
3384: printf ("\t}\n");
3385: }
3386: break;
3387: case i_MOVES: /* ignore DFC and SFC when using_mmu == false */
3388: {
3389: int old_brace_level;
3390: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3391: printf ("\tif (extra & 0x800)\n");
3392: {
3393: int old_m68k_pc_offset = m68k_pc_offset;
3394: old_brace_level = n_braces;
3395: start_brace ();
3396: printf ("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
3397: genamode (curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
3398: genastore_fc ("src", curi->dmode, "dstreg", curi->size, "dst");
3399: pop_braces (old_brace_level);
3400: m68k_pc_offset = old_m68k_pc_offset;
3401: }
3402: printf ("else");
3403: {
3404: start_brace ();
3405: genamode (curi->dmode, "dstreg", curi->size, "src", 1, 0, GF_FC);
3406: printf ("\tif (extra & 0x8000) {\n");
3407: switch (curi->size) {
3408: case sz_byte: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
3409: case sz_word: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
3410: case sz_long: printf ("\tm68k_areg (regs, (extra >> 12) & 7) = src;\n"); break;
3411: default: abort ();
3412: }
3413: printf ("\t} else {\n");
3414: genastore ("src", Dreg, "(extra >> 12) & 7", curi->size, "");
3415: printf ("\t}\n");
3416: sync_m68k_pc ();
3417: pop_braces (old_brace_level);
3418: }
3419: }
3420: break;
3421: case i_BKPT: /* only needed for hardware emulators */
3422: sync_m68k_pc ();
3423: printf ("\top_illg (opcode);\n");
3424: break;
3425: case i_CALLM: /* not present in 68030 */
3426: sync_m68k_pc ();
3427: printf ("\top_illg (opcode);\n");
3428: break;
3429: case i_RTM: /* not present in 68030 */
3430: sync_m68k_pc ();
3431: printf ("\top_illg (opcode);\n");
3432: break;
3433: case i_TRAPcc:
3434: if (curi->smode != am_unknown && curi->smode != am_illg)
3435: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
3436: fill_prefetch_0 ();
3437: printf ("\tif (cctrue (%d)) { Exception (7, m68k_getpc () ,M68000_EXC_SRC_CPU); goto %s; }\n", curi->cc, endlabelstr);
3438: need_endlabel = 1;
3439: break;
3440: case i_DIVL:
3441: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
3442: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3443: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3444: sync_m68k_pc ();
3445: printf ("\tm68k_divl(opcode, dst, extra, oldpc);\n");
3446: if (using_ce020 == 2) {
3447: no_return_cycles = true;
3448: printf ("\tif (extra & 0x800)\n");
3449: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_DIVS_L[%d];\n", divl_index);
3450: printf ("\telse\n");
3451: printf ("\t\tregs.ce030_instr_cycles = table_falcon_cycles_DIVU_L[%d];\n", divl_index);
3452: divl_index ++;
3453: }
3454: break;
3455: case i_MULL:
3456: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3457: genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
3458: sync_m68k_pc ();
3459: printf ("\tm68k_mull(opcode, dst, extra);\n");
3460: break;
3461: case i_BFTST:
3462: case i_BFEXTU:
3463: case i_BFCHG:
3464: case i_BFEXTS:
3465: case i_BFCLR:
3466: case i_BFFFO:
3467: case i_BFSET:
3468: case i_BFINS:
3469: {
3470: const char *getb, *putb;
3471:
3472: if (using_mmu || using_ce020) {
3473: getb = "x_get_bitfield";
3474: putb = "x_put_bitfield";
3475: } else {
3476: getb = "get_bitfield";
3477: putb = "put_bitfield";
3478: }
3479:
3480: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3481: genamode (curi->dmode, "dstreg", sz_long, "dst", 2, 0, 0);
3482: start_brace ();
3483: printf ("\tuae_u32 bdata[2];\n");
3484: printf ("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
3485: printf ("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
3486: if (curi->dmode == Dreg) {
3487: printf ("\tuae_u32 tmp = m68k_dreg(regs, dstreg);\n");
3488: printf ("\toffset &= 0x1f;\n");
3489: printf ("\ttmp = (tmp << offset) | (tmp >> (32 - offset));\n");
3490: printf ("\tbdata[0] = tmp & ((1 << (32 - width)) - 1);\n");
3491: } else {
3492: printf ("\tuae_u32 tmp;\n");
3493: printf ("\tdsta += offset >> 3;\n");
3494: printf ("\ttmp = %s (dsta, bdata, offset, width);\n", getb);
3495: }
3496: printf ("\tSET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);\n");
3497: if (curi->mnemo == i_BFEXTS)
3498: printf ("\ttmp = (uae_s32)tmp >> (32 - width);\n");
3499: else
3500: printf ("\ttmp >>= (32 - width);\n");
3501: printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
3502: switch (curi->mnemo) {
3503: case i_BFTST:
3504: break;
3505: case i_BFEXTU:
3506: case i_BFEXTS:
3507: printf ("\tm68k_dreg (regs, (extra >> 12) & 7) = tmp;\n");
3508: break;
3509: case i_BFCHG:
3510: printf ("\ttmp = tmp ^ (0xffffffffu >> (32 - width));\n");
3511: break;
3512: case i_BFCLR:
3513: printf ("\ttmp = 0;\n");
3514: break;
3515: case i_BFFFO:
3516: printf ("\t{ uae_u32 mask = 1 << (width - 1);\n");
3517: printf ("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset++; }}\n");
3518: printf ("\tm68k_dreg (regs, (extra >> 12) & 7) = offset;\n");
3519: break;
3520: case i_BFSET:
3521: printf ("\ttmp = 0xffffffffu >> (32 - width);\n");
3522: break;
3523: case i_BFINS:
3524: printf ("\ttmp = m68k_dreg (regs, (extra >> 12) & 7);\n");
3525: printf ("\ttmp = tmp & (0xffffffffu >> (32 - width));\n");
3526: printf ("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
3527: printf ("\tSET_ZFLG (tmp == 0);\n");
3528: break;
3529: default:
3530: break;
3531: }
3532: if (curi->mnemo == i_BFCHG
3533: || curi->mnemo == i_BFCLR
3534: || curi->mnemo == i_BFSET
3535: || curi->mnemo == i_BFINS) {
3536: if (curi->dmode == Dreg) {
3537: printf ("\ttmp = bdata[0] | (tmp << (32 - width));\n");
3538: printf ("\tm68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));\n");
3539: } else {
3540: printf ("\t%s(dsta, bdata, tmp, offset, width);\n", putb);
3541: }
3542: }
3543: }
3544: break;
3545: case i_PACK:
3546: if (curi->smode == Dreg) {
3547: printf ("\tuae_u16 val = m68k_dreg (regs, srcreg) + %s;\n", gen_nextiword (0));
3548: printf ("\tm68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
3549: } else {
3550: printf ("\tuae_u16 val;\n");
3551: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
3552: printf ("\tval = (uae_u16)%s (m68k_areg (regs, srcreg));\n", srcb);
3553: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
3554: printf ("\tval = (val | ((uae_u16)%s (m68k_areg (regs, srcreg)) << 8)) + %s;\n", srcb, gen_nextiword (0));
3555: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
3556: gen_set_fault_pc ();
3557: printf ("\t%s (m68k_areg (regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n", dstb);
3558: }
3559: break;
3560: case i_UNPK:
3561: if (curi->smode == Dreg) {
3562: printf ("\tuae_u16 val = m68k_dreg (regs, srcreg);\n");
3563: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
3564: printf ("\tm68k_dreg (regs, dstreg) = (m68k_dreg (regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
3565: } else {
3566: printf ("\tuae_u16 val;\n");
3567: printf ("\tm68k_areg (regs, srcreg) -= areg_byteinc[srcreg];\n");
3568: printf ("\tval = (uae_u16)%s (m68k_areg (regs, srcreg));\n", srcb);
3569: printf ("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
3570: if (cpu_level >= 2) {
3571: printf ("\tm68k_areg (regs, dstreg) -= 2 * areg_byteinc[dstreg];\n");
3572: printf ("\t%s (m68k_areg (regs, dstreg) + areg_byteinc[dstreg], val);\n", dstb);
3573: printf ("\t%s (m68k_areg (regs, dstreg), val >> 8);\n", dstb);
3574: } else {
3575: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
3576: printf ("\t%s (m68k_areg (regs, dstreg),val);\n", dstb);
3577: printf ("\tm68k_areg (regs, dstreg) -= areg_byteinc[dstreg];\n");
3578: gen_set_fault_pc ();
3579: printf ("\t%s (m68k_areg (regs, dstreg),val >> 8);\n", dstb);
3580: }
3581: }
3582: break;
3583: case i_TAS:
3584: genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
3585: genflags (flag_logical, curi->size, "src", "", "");
3586: if (!isreg (curi->smode))
3587: addcycles000 (2);
3588: fill_prefetch_next ();
3589: printf ("\tsrc |= 0x80;\n");
3590: if (cpu_level >= 2 || curi->smode == Dreg || !using_ce) {
3591: if (next_cpu_level < 2)
3592: next_cpu_level = 2 - 1;
3593: genastore ("src", curi->smode, "srcreg", curi->size, "src");
3594: } else {
3595: printf ("\tif (!is_cycle_ce ()) {\n");
3596: genastore ("src", curi->smode, "srcreg", curi->size, "src");
3597: printf ("\t} else {\n");
3598: printf ("\t\tdo_cycles_ce000 (4);\n");
3599: printf ("\t}\n");
3600: }
3601: break;
3602: case i_FPP:
3603: fpulimit();
3604: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3605: sync_m68k_pc ();
3606: printf ("\tfpuop_arithmetic(opcode, extra);\n");
3607: break;
3608: case i_FDBcc:
3609: fpulimit();
3610: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3611: sync_m68k_pc ();
3612: printf ("\tfpuop_dbcc (opcode, extra);\n");
3613: break;
3614: case i_FScc:
3615: fpulimit();
3616: genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
3617: sync_m68k_pc ();
3618: printf ("\tfpuop_scc (opcode, extra);\n");
3619: break;
3620: case i_FTRAPcc:
3621: fpulimit();
3622: printf ("\tuaecptr oldpc = m68k_getpc ();\n");
3623: printf ("\tuae_u16 extra = %s;\n", gen_nextiword (0));
3624: if (curi->smode != am_unknown && curi->smode != am_illg)
3625: genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
3626: sync_m68k_pc ();
3627: printf ("\tfpuop_trapcc (opcode, oldpc, extra);\n");
3628: break;
3629: case i_FBcc:
3630: fpulimit();
3631: sync_m68k_pc ();
3632: start_brace ();
3633: printf ("\tuaecptr pc = m68k_getpc ();\n");
3634: genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0, 0);
3635: sync_m68k_pc ();
3636: printf ("\tfpuop_bcc (opcode, pc,extra);\n");
3637: break;
3638: case i_FSAVE:
3639: fpulimit();
3640: sync_m68k_pc ();
3641: printf ("\tfpuop_save (opcode);\n");
3642: break;
3643: case i_FRESTORE:
3644: fpulimit();
3645: sync_m68k_pc ();
3646: printf ("\tfpuop_restore (opcode);\n");
3647: break;
3648:
3649: case i_CINVL:
3650: case i_CINVP:
3651: case i_CINVA:
3652: case i_CPUSHL:
3653: case i_CPUSHP:
3654: case i_CPUSHA:
3655: if (using_mmu)
1.1.1.5 root 3656: printf ("\tflush_mmu%s(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);\n", mmu_postfix);
1.1.1.4 root 3657: printf ("\tif (opcode & 0x80)\n");
3658: printf ("\t\tflush_icache(m68k_areg (regs, opcode & 3), (opcode >> 6) & 3);\n");
3659: break;
3660:
3661: case i_MOVE16:
3662: {
3663: if ((opcode & 0xfff8) == 0xf620) {
3664: /* MOVE16 (Ax)+,(Ay)+ */
3665: printf ("\tuae_u32 v1, v2, v3, v4;\n");
3666: printf ("\tuaecptr mems = m68k_areg (regs, srcreg) & ~15, memd;\n");
3667: printf ("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword (0));
3668: printf ("\tmemd = m68k_areg (regs, dstreg) & ~15;\n");
3669: printf ("\tv1 = %s (mems);\n", srcl);
3670: printf ("\tv2 = %s (mems + 4);\n", srcl);
3671: printf ("\tv3 = %s (mems + 8);\n", srcl);
3672: printf ("\tv4 = %s (mems + 12);\n", srcl);
3673: printf ("\t%s (memd , v1);\n", dstl);
3674: printf ("\t%s (memd + 4, v2);\n", dstl);
3675: printf ("\t%s (memd + 8, v3);\n", dstl);
3676: printf ("\t%s (memd + 12, v4);\n", dstl);
3677: printf ("\tif (srcreg != dstreg)\n");
3678: printf ("\t\tm68k_areg (regs, srcreg) += 16;\n");
3679: printf ("\tm68k_areg (regs, dstreg) += 16;\n");
3680: } else {
3681: /* Other variants */
3682: printf ("\tuae_u32 v1, v2, v3, v4;\n");
3683: genamode (curi->smode, "srcreg", curi->size, "mems", 0, 2, 0);
3684: genamode (curi->dmode, "dstreg", curi->size, "memd", 0, 2, 0);
3685: printf ("\tmemsa &= ~15;\n");
3686: printf ("\tmemda &= ~15;\n");
3687: printf ("\tv1 = %s (memsa);\n", srcl);
3688: printf ("\tv2 = %s (memsa + 4);\n", srcl);
3689: printf ("\tv3 = %s (memsa + 8);\n", srcl);
3690: printf ("\tv4 = %s (memsa + 12);\n", srcl);
3691: printf ("\t%s (memda , v1);\n", dstl);
3692: printf ("\t%s (memda + 4, v2);\n", dstl);
3693: printf ("\t%s (memda + 8, v3);\n", dstl);
3694: printf ("\t%s (memda + 12, v4);\n", dstl);
3695: if ((opcode & 0xfff8) == 0xf600)
3696: printf ("\tm68k_areg (regs, srcreg) += 16;\n");
3697: else if ((opcode & 0xfff8) == 0xf608)
3698: printf ("\tm68k_areg (regs, dstreg) += 16;\n");
3699: }
3700: }
3701: break;
3702:
3703: case i_PFLUSHN:
3704: case i_PFLUSH:
3705: case i_PFLUSHAN:
3706: case i_PFLUSHA:
3707: case i_PLPAR:
3708: case i_PLPAW:
3709: case i_PTESTR:
3710: case i_PTESTW:
3711: sync_m68k_pc ();
3712: printf ("\tmmu_op (opcode, 0);\n");
3713: break;
3714: case i_MMUOP030:
3715: printf ("\tuaecptr pc = m68k_getpc ();\n");
3716: printf ("\tuae_u16 extra = x_get_word (pc + 2);\n");
3717: m68k_pc_offset += 2;
3718: sync_m68k_pc ();
3719: if (curi->smode == Areg || curi->smode == Dreg)
3720: printf("\tuae_u16 extraa = 0;\n");
3721: else
3722: genamode (curi->smode, "srcreg", curi->size, "extra", 0, 0, 0);
3723: sync_m68k_pc ();
3724: printf ("\tmmu_op30 (pc, opcode, extra, extraa);\n");
3725: break;
3726: default:
3727: abort ();
3728: break;
3729: }
3730: finish_braces ();
3731: if (limit_braces) {
3732: printf ("\n#endif\n");
3733: n_braces = limit_braces;
3734: limit_braces = 0;
3735: finish_braces ();
3736: }
3737: if (did_prefetch >= 0)
3738: fill_prefetch_finish ();
3739: if (!count_cycles)
3740: addcycles_ce020 (0, 0, 2, 2);
3741: sync_m68k_pc ();
3742: did_prefetch = 0;
3743: }
3744:
3745: static void generate_includes (FILE * f)
3746: {
3747: fprintf (f, "#include \"main.h\"\n");
3748: fprintf (f, "#include \"sysdeps.h\"\n");
3749: fprintf (f, "#include \"hatari-glue.h\"\n");
3750: fprintf (f, "#include \"maccess.h\"\n");
3751: fprintf (f, "#include \"memory.h\"\n");
3752: fprintf (f, "#include \"custom.h\"\n");
3753: fprintf (f, "#include \"newcpu.h\"\n");
3754: fprintf (f, "#include \"cpu_prefetch.h\"\n");
3755: fprintf (f, "#include \"cputbl.h\"\n");
3756:
3757: fprintf (f, "#define CPUFUNC(x) x##_ff\n"
3758: "#define SET_CFLG_ALWAYS(x) SET_CFLG(x)\n"
3759: "#define SET_NFLG_ALWAYS(x) SET_NFLG(x)\n"
3760: "#ifdef NOFLAGS\n"
3761: "#include \"noflags.h\"\n"
3762: "#endif\n");
3763: }
3764:
3765: static int postfix;
3766:
3767:
3768: static char *decodeEA (amodes mode, wordsizes size)
3769: {
3770: static char buffer[80];
3771:
3772: buffer[0] = 0;
3773: switch (mode){
3774: case Dreg:
3775: strcpy (buffer,"Dn");
3776: break;
3777: case Areg:
3778: strcpy (buffer,"An");
3779: break;
3780: case Aind:
3781: strcpy (buffer,"(An)");
3782: break;
3783: case Aipi:
3784: strcpy (buffer,"(An)+");
3785: break;
3786: case Apdi:
3787: strcpy (buffer,"-(An)");
3788: break;
3789: case Ad16:
3790: strcpy (buffer,"(d16,An)");
3791: break;
3792: case Ad8r:
3793: strcpy (buffer,"(d8,An,Xn)");
3794: break;
3795: case PC16:
3796: strcpy (buffer,"(d16,PC)");
3797: break;
3798: case PC8r:
3799: strcpy (buffer,"(d8,PC,Xn)");
3800: break;
3801: case absw:
3802: strcpy (buffer,"(xxx).W");
3803: break;
3804: case absl:
3805: strcpy (buffer,"(xxx).L");
3806: break;
3807: case imm:
3808: switch (size){
3809: case sz_byte:
3810: strcpy (buffer,"#<data>.B");
3811: break;
3812: case sz_word:
3813: strcpy (buffer,"#<data>.W");
3814: break;
3815: case sz_long:
3816: strcpy (buffer,"#<data>.L");
3817: break;
3818: default:
3819: break;
3820: }
3821: break;
3822: case imm0:
3823: strcpy (buffer,"#<data>.B");
3824: break;
3825: case imm1:
3826: strcpy (buffer,"#<data>.W");
3827: break;
3828: case imm2:
3829: strcpy (buffer,"#<data>.L");
3830: break;
3831: case immi:
3832: strcpy (buffer,"#<data>");
3833: break;
3834:
3835: default:
3836: break;
3837: }
3838: return buffer;
3839: }
3840:
3841: static char *outopcode (int opcode)
3842: {
3843: static char out[100];
3844: struct instr *ins;
3845: int i;
3846:
3847: ins = &table68k[opcode];
3848: for (i = 0; lookuptab[i].name[0]; i++) {
3849: if (ins->mnemo == lookuptab[i].mnemo)
3850: break;
3851: }
3852: {
3853: // char *s = ua (lookuptab[i].name);
3854: const char *s = lookuptab[i].name;
3855: strcpy (out, s);
3856: //xfree (s);
3857: }
3858: if (ins->smode == immi)
3859: strcat (out, "Q");
3860: if (ins->size == sz_byte)
3861: strcat (out,".B");
3862: if (ins->size == sz_word)
3863: strcat (out,".W");
3864: if (ins->size == sz_long)
3865: strcat (out,".L");
3866: strcat (out," ");
3867: if (ins->suse)
3868: strcat (out, decodeEA (ins->smode, ins->size));
3869: if (ins->duse) {
3870: if (ins->suse) strcat (out,",");
3871: strcat (out, decodeEA (ins->dmode, ins->size));
3872: }
3873: return out;
3874: }
3875:
3876: static void generate_one_opcode (int rp)
3877: {
3878: int idx;
3879: uae_u16 smsk, dmsk;
3880: long int opcode = opcode_map[rp];
3881: int i68000 = table68k[opcode].clev > 0;
3882:
3883: if (table68k[opcode].mnemo == i_ILLG
3884: || table68k[opcode].clev > cpu_level)
3885: return;
3886:
3887: for (idx = 0; lookuptab[idx].name[0]; idx++) {
3888: if (table68k[opcode].mnemo == lookuptab[idx].mnemo)
3889: break;
3890: }
3891:
3892: if (table68k[opcode].handler != -1)
3893: return;
3894:
3895: if (opcode_next_clev[rp] != cpu_level) {
3896: //char *name = ua (lookuptab[idx].name);
3897: const char *name = lookuptab[idx].name;
3898: if (generate_stbl)
3899: fprintf (stblfile, "{ %sCPUFUNC(op_%04lx_%d), %ld }, /* %s */\n",
3900: (using_ce || using_ce020) ? "(cpuop_func*)" : "",
3901: opcode, opcode_last_postfix[rp],
3902: opcode, name);
3903: //xfree (name);
3904: return;
3905: }
3906: fprintf (headerfile, "extern %s op_%04lx_%d_nf;\n",
3907: (using_ce || using_ce020) ? "cpuop_func_ce" : "cpuop_func", opcode, postfix);
3908: fprintf (headerfile, "extern %s op_%04lx_%d_ff;\n",
3909: (using_ce || using_ce020) ? "cpuop_func_ce" : "cpuop_func", opcode, postfix);
3910: printf ("/* %s */\n", outopcode (opcode));
3911: if (i68000)
3912: printf("#ifndef CPUEMU_68000_ONLY\n");
3913: printf ("%s REGPARAM2 CPUFUNC(op_%04lx_%d)(uae_u32 opcode)\n{\n", (using_ce || using_ce020) ? "void" : "unsigned long", opcode, postfix);
3914:
3915: switch (table68k[opcode].stype) {
3916: case 0: smsk = 7; break;
3917: case 1: smsk = 255; break;
3918: case 2: smsk = 15; break;
3919: case 3: smsk = 7; break;
3920: case 4: smsk = 7; break;
3921: case 5: smsk = 63; break;
3922: case 7: smsk = 3; break;
3923: default: abort ();
3924: }
3925: dmsk = 7;
3926:
3927: next_cpu_level = -1;
3928: if (table68k[opcode].suse
3929: && table68k[opcode].smode != imm && table68k[opcode].smode != imm0
3930: && table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
3931: && table68k[opcode].smode != absw && table68k[opcode].smode != absl
3932: && table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
3933: {
3934: if (table68k[opcode].spos == -1) {
3935: if (((int) table68k[opcode].sreg) >= 128)
3936: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
3937: else
3938: printf ("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
3939: } else {
3940: char source[100];
3941: int pos = table68k[opcode].spos;
3942:
3943: if (pos)
3944: sprintf (source, "((opcode >> %d) & %d)", pos, smsk);
3945: else
3946: sprintf (source, "(opcode & %d)", smsk);
3947:
3948: if (table68k[opcode].stype == 3)
3949: printf ("\tuae_u32 srcreg = imm8_table[%s];\n", source);
3950: else if (table68k[opcode].stype == 1)
3951: printf ("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
3952: else
3953: printf ("\tuae_u32 srcreg = %s;\n", source);
3954: }
3955: }
3956: if (table68k[opcode].duse
3957: /* Yes, the dmode can be imm, in case of LINK or DBcc */
3958: && table68k[opcode].dmode != imm && table68k[opcode].dmode != imm0
3959: && table68k[opcode].dmode != imm1 && table68k[opcode].dmode != imm2
3960: && table68k[opcode].dmode != absw && table68k[opcode].dmode != absl)
3961: {
3962: if (table68k[opcode].dpos == -1) {
3963: if (((int) table68k[opcode].dreg) >= 128)
3964: printf ("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
3965: else
3966: printf ("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
3967: } else {
3968: int pos = table68k[opcode].dpos;
3969: if (pos)
3970: printf ("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
3971: pos, dmsk);
3972: else
3973: printf ("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
3974: }
3975: }
3976: need_endlabel = 0;
3977: endlabelno++;
3978: sprintf (endlabelstr, "endlabel%d", endlabelno);
3979: count_read = count_write = count_ncycles = count_cycles = 0;
3980: count_read_ea = count_write_ea = count_cycles_ea = 0;
3981: gen_opcode (opcode);
3982: if (need_endlabel)
3983: printf ("%s: ;\n", endlabelstr);
3984:
3985: returncycles ("", insn_n_cycles);
3986:
3987: printf ("}");
3988: if (using_ce || using_prefetch) {
3989: if (count_read + count_write + count_cycles == 0)
3990: count_cycles = 4;
3991: printf (" /* %d%s (%d/%d)",
3992: (count_read + count_write) * 4 + count_cycles, count_ncycles ? "+" : "", count_read, count_write);
3993: printf (" */\n");
3994: } else {
3995: printf("\n");
3996: }
3997: printf ("\n");
3998: if (i68000)
3999: printf("#endif\n");
4000: opcode_next_clev[rp] = next_cpu_level;
4001: opcode_last_postfix[rp] = postfix;
4002:
4003: /* Hatari only : Now patch in the instruction cycles at the beginning of the function: */
4004: if (!using_ce020) {
4005: fseek(stdout, nCurInstrCycPos, SEEK_SET);
4006: printf("%d;", insn_n_cycles);
4007: fseek(stdout, 0, SEEK_END);
4008: }
4009:
4010: /* Hatari only : inc instruction index for cycle exact 68030 cpu */
4011: if (using_ce020 == 2)
4012: instr_index += 1;
4013:
4014: if (generate_stbl) {
4015: // char *name = ua (lookuptab[idx].name);
4016: const char *name = lookuptab[idx].name;
4017: if (i68000)
4018: fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
4019: fprintf (stblfile, "{ %sCPUFUNC(op_%04lx_%d), %ld }, /* %s */\n",
4020: (using_ce || using_ce020) ? "(cpuop_func*)" : "",
4021: opcode, postfix, opcode, name);
4022: if (i68000)
4023: fprintf (stblfile, "#endif\n");
4024: //xfree (name);
4025: }
4026: }
4027:
4028: static void generate_func (void)
4029: {
4030: int j, rp;
4031:
4032: /* sam: this is for people with low memory (eg. me :)) */
4033: printf ("\n"
4034: "#if !defined(PART_1) && !defined(PART_2) && "
4035: "!defined(PART_3) && !defined(PART_4) && "
4036: "!defined(PART_5) && !defined(PART_6) && "
4037: "!defined(PART_7) && !defined(PART_8)"
4038: "\n"
4039: "#define PART_1 1\n"
4040: "#define PART_2 1\n"
4041: "#define PART_3 1\n"
4042: "#define PART_4 1\n"
4043: "#define PART_5 1\n"
4044: "#define PART_6 1\n"
4045: "#define PART_7 1\n"
4046: "#define PART_8 1\n"
4047: "#endif\n\n");
4048:
4049: rp = 0;
4050: for(j = 1; j <= 8; ++j) {
4051: int k = (j * nr_cpuop_funcs) / 8;
4052: printf ("#ifdef PART_%d\n",j);
4053: for (; rp < k; rp++)
4054: generate_one_opcode (rp);
4055: printf ("#endif\n\n");
4056: }
4057:
4058: if (generate_stbl)
4059: fprintf (stblfile, "{ 0, 0 }};\n");
4060: }
4061:
4062: int main (int argc, char **argv)
4063: {
4064: int i, rp, postfix2;
4065: char fname[100];
4066:
4067: read_table68k ();
4068: do_merges ();
4069:
4070: opcode_map = xmalloc (int, nr_cpuop_funcs);
4071: opcode_last_postfix = xmalloc (int, nr_cpuop_funcs);
4072: opcode_next_clev = xmalloc (int, nr_cpuop_funcs);
4073: counts = xmalloc (unsigned long, 65536);
4074: read_counts ();
4075:
4076: /* It would be a lot nicer to put all in one file (we'd also get rid of
4077: * cputbl.h that way), but cpuopti can't cope. That could be fixed, but
4078: * I don't dare to touch the 68k version. */
4079:
4080: headerfile = fopen ("cputbl.h", "wb");
4081:
4082: stblfile = fopen ("cpustbl.c", "wb");
4083: generate_includes (stblfile);
4084:
4085: using_prefetch = 0;
4086: using_indirect = 0;
4087: using_exception_3 = 1;
4088: using_ce = 0;
4089:
4090: postfix2 = -1;
1.1.1.5 root 4091: for (i = 0; i <= 32; i++) {
1.1.1.4 root 4092: postfix = i;
4093: if ((i >= 6 && i < 11) || (i > 12 && i < 20) || (i > 23 && i < 31))
4094: continue;
4095: generate_stbl = 1;
1.1.1.5 root 4096: if (i == 0 || i == 11 || i == 12 || i == 20 || i == 21
4097: || i == 31 || i == 32) {
1.1.1.4 root 4098: if (generate_stbl)
4099: fprintf (stblfile, "#ifdef CPUEMU_%d\n", postfix);
4100: postfix2 = postfix;
4101: sprintf (fname, "cpuemu_%d.c", postfix);
4102: if (freopen (fname, "wb", stdout) == NULL) {
4103: perror(fname);
4104: return -1;
4105: }
4106: generate_includes (stdout);
4107: }
4108: using_mmu = 0;
4109: using_prefetch = 0;
4110: using_ce = 0;
4111: using_ce020 = 0;
4112: using_mmu = 0;
4113: cpu_level = 5 - i;
4114: if (i == 11 || i == 12) {
4115: cpu_level = 0;
4116: using_prefetch = 1;
4117: using_exception_3 = 1;
4118: if (i == 12)
4119: using_ce = 1;
4120: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4121: opcode_next_clev[rp] = 0;
4122: } else if (i == 20) {
4123: cpu_level = 2;
4124: using_ce020 = 1;
4125: read_counts ();
4126: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4127: opcode_next_clev[rp] = cpu_level;
4128: } else if (i == 21 || i == 22 || i == 23) {
4129: cpu_level = 3 + (23 - i);
4130: using_ce020 = 2;
4131: if (i == 21) {
4132: read_counts ();
4133: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4134: opcode_next_clev[rp] = cpu_level;
4135: }
4136: } else if (i >= 31 && i < 40) {
1.1.1.5 root 4137: cpu_level = 3 + 32 - i;
1.1.1.4 root 4138: using_mmu = 1;
1.1.1.5 root 4139: if (cpu_level == 3) {
4140: fprintf (stdout, "#include \"cpummu030.h\"\n");
4141: mmu_postfix = "030";
4142: }
4143: else {
4144: fprintf (stdout, "#include \"cpummu.h\"\n");
4145: mmu_postfix = "";
4146: }
4147:
1.1.1.4 root 4148: if (i == 31)
4149: read_counts ();
4150: for (rp = 0; rp < nr_cpuop_funcs; rp++)
4151: opcode_next_clev[rp] = cpu_level;
4152: }
4153:
4154: if (generate_stbl) {
4155: if ((i > 0 && i < 10) || (i >= 20))
4156: fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
4157: fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
4158: }
4159:
4160: generate_func ();
4161: if (generate_stbl) {
4162: if ((i > 0 && i < 10) || (i >= 20))
4163: fprintf (stblfile, "#endif /* CPUEMU_68000_ONLY */\n");
4164: if (postfix2 >= 0)
4165: fprintf (stblfile, "#endif /* CPUEMU_%d */\n", postfix2);
4166: }
4167: postfix2 = -1;
4168: }
4169:
4170: free (table68k);
4171: return 0;
4172: }
4173:
4174: void write_log (const TCHAR *format,...)
4175: {
4176: }
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