![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to compemu.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [HATARI the Atari ST Emulator] / hatari / src / cpu / jit|
Return to compemu.h CVS log | Up to [HATARI the Atari ST Emulator] / hatari / src / cpu / jit |
1.1 root 1:
2: #include "flags_x86.h"
3:
4: #ifdef CPU_64_BIT
5: typedef uae_u64 uintptr;
6: #else
7: typedef uae_u32 uintptr;
8: #endif
9:
10: /* Flags for Bernie during development/debugging. Should go away eventually */
11: #define DISTRUST_CONSISTENT_MEM 0
12: #define TAGMASK 0x000fffff
13: #define TAGSIZE (TAGMASK+1)
14: #define MAXRUN 1024
15:
16: extern uae_u8* start_pc_p;
17: extern uae_u32 start_pc;
18:
19: #define cacheline(x) (((uae_u32)x)&TAGMASK)
20:
21: typedef struct {
22: uae_u16* location;
23: uae_u8 cycles;
24: uae_u8 specmem;
25: uae_u8 dummy2;
26: uae_u8 dummy3;
27: } cpu_history;
28:
29: struct blockinfo_t;
30:
31: typedef union {
32: cpuop_func* handler;
33: struct blockinfo_t* bi;
34: } cacheline;
35:
36: extern signed long pissoff;
37:
38: #define USE_OPTIMIZER 0
39: #define USE_LOW_OPTIMIZER 0
40: #define USE_ALIAS 1
41: #define USE_F_ALIAS 1
42: #define USE_SOFT_FLUSH 1
43: #define USE_OFFSET 1
44: #define COMP_DEBUG 1
45:
46: #if COMP_DEBUG
47: #define Dif(x) if (x)
48: #else
49: #define Dif(x) if (0)
50: #endif
51:
52: #define SCALE 2
53: #define MAXCYCLES (1000 * CYCLE_UNIT)
54: #define MAXREGOPT 65536
55:
56: #define BYTES_PER_INST 10240 /* paranoid ;-) */
57: #define LONGEST_68K_INST 16 /* The number of bytes the longest possible
58: 68k instruction takes */
59: #define MAX_CHECKSUM_LEN 2048 /* The maximum size we calculate checksums
60: for. Anything larger will be flushed
61: unconditionally even with SOFT_FLUSH */
62: #define MAX_HOLD_BI 3 /* One for the current block, and up to two
63: for jump targets */
64:
65: #define INDIVIDUAL_INST 0
66: #define FLAG_C 0x0010
67: #define FLAG_V 0x0008
68: #define FLAG_Z 0x0004
69: #define FLAG_N 0x0002
70: #define FLAG_X 0x0001
71: #define FLAG_CZNV (FLAG_C | FLAG_Z | FLAG_N | FLAG_V)
72: #define FLAG_ZNV (FLAG_Z | FLAG_N | FLAG_V)
73:
74: #define KILLTHERAT 1 /* Set to 1 to avoid some partial_rat_stalls */
75:
76: /* Whether to preserve registers across calls to JIT compiled routines */
77: #if defined X86_ASSEMBLY
78: #define USE_PUSH_POP 0
79: #else
80: #define USE_PUSH_POP 1
81: #endif
82:
83: #define N_REGS 8 /* really only 7, but they are numbered 0,1,2,3,5,6,7 */
84: #define N_FREGS 6 /* That leaves us two positions on the stack to play with */
85:
86: /* Functions exposed to newcpu, or to what was moved from newcpu.c to
87: * compemu_support.c */
88: extern void init_comp(void);
89: extern void flush(int save_regs);
90: extern void small_flush(int save_regs);
91: extern void set_target(uae_u8* t);
92: extern void freescratch(void);
93: extern void build_comp(void);
94: extern void set_cache_state(int enabled);
95: extern int get_cache_state(void);
96: extern uae_u32 get_jitted_size(void);
97: #ifdef JIT
98: extern void flush_icache(uaecptr ptr, int n);
99: #endif
100: extern void alloc_cache(void);
101: extern void compile_block(cpu_history* pc_hist, int blocklen, int totcyles);
102: extern int check_for_cache_miss(void);
103:
104:
105: #define scaled_cycles(x) (currprefs.m68k_speed==-1?(((x)/SCALE)?(((x)/SCALE<MAXCYCLES?((x)/SCALE):MAXCYCLES)):1):(x))
106:
107:
108: extern uae_u32 needed_flags;
109: extern cacheline cache_tags[];
110: extern uae_u8* comp_pc_p;
111: extern void* pushall_call_handler;
112:
113: #define VREGS 32
114: #define VFREGS 16
115:
116: #define INMEM 1
117: #define CLEAN 2
118: #define DIRTY 3
119: #define UNDEF 4
120: #define ISCONST 5
121:
122: typedef struct {
123: uae_u32* mem;
124: uae_u32 val;
125: uae_u8 is_swapped;
126: uae_u8 status;
127: uae_u8 realreg;
128: uae_u8 realind; /* The index in the holds[] array */
129: uae_u8 needflush;
130: uae_u8 validsize;
131: uae_u8 dirtysize;
132: uae_u8 dummy;
133: } reg_status;
134:
135: typedef struct {
136: uae_u32* mem;
137: double val;
138: uae_u8 status;
139: uae_u8 realreg;
140: uae_u8 realind;
141: uae_u8 needflush;
142: } freg_status;
143:
144: typedef struct {
145: uae_u8 use_flags;
146: uae_u8 set_flags;
147: uae_u8 is_jump;
148: uae_u8 is_addx;
149: uae_u8 is_const_jump;
150: } op_properties;
151:
152: extern op_properties prop[65536];
153:
154: STATIC_INLINE int end_block(uae_u16 opcode)
155: {
156: return prop[opcode].is_jump ||
157: (prop[opcode].is_const_jump && !currprefs.comp_constjump);
158: }
159:
160: #define PC_P 16
161: #define FLAGX 17
162: #define FLAGTMP 18
163: #define NEXT_HANDLER 19
164: #define S1 20
165: #define S2 21
166: #define S3 22
167: #define S4 23
168: #define S5 24
169: #define S6 25
170: #define S7 26
171: #define S8 27
172: #define S9 28
173: #define S10 29
174: #define S11 30
175: #define S12 31
176:
177: #define FP_RESULT 8
178: #define FS1 9
179: #define FS2 10
180: #define FS3 11
181:
182: typedef struct {
183: uae_u32 touched;
184: uae_s8 holds[VREGS];
185: uae_u8 nholds;
186: uae_u8 canbyte;
187: uae_u8 canword;
188: uae_u8 locked;
189: } n_status;
190:
191: typedef struct {
192: uae_s8 holds;
193: uae_u8 validsize;
194: uae_u8 dirtysize;
195: } n_smallstatus;
196:
197: typedef struct {
198: uae_u32 touched;
199: uae_s8 holds[VFREGS];
200: uae_u8 nholds;
201: uae_u8 locked;
202: } fn_status;
203:
204: /* For flag handling */
205: #define NADA 1
206: #define TRASH 2
207: #define VALID 3
208:
209: /* needflush values */
210: #define NF_SCRATCH 0
211: #define NF_TOMEM 1
212: #define NF_HANDLER 2
213:
214: typedef struct {
215: /* Integer part */
216: reg_status state[VREGS];
217: n_status nat[N_REGS];
218: uae_u32 flags_on_stack;
219: uae_u32 flags_in_flags;
220: uae_u32 flags_are_important;
221: /* FPU part */
222: freg_status fate[VFREGS];
223: fn_status fat[N_FREGS];
224:
225: /* x86 FPU part */
226: uae_s8 spos[N_FREGS];
227: uae_s8 onstack[6];
228: uae_s8 tos;
229: } bigstate;
230:
231: typedef struct {
232: /* Integer part */
233: n_smallstatus nat[N_REGS];
234: } smallstate;
235:
236: extern bigstate live;
237: extern int touchcnt;
238:
239:
240: #define IMMS uae_s32
241: #define IMM uae_u32
242: #define R1 uae_u32
243: #define R2 uae_u32
244: #define R4 uae_u32
245: #define W1 uae_u32
246: #define W2 uae_u32
247: #define W4 uae_u32
248: #define RW1 uae_u32
249: #define RW2 uae_u32
250: #define RW4 uae_u32
251: #define MEMR uae_u32
252: #define MEMW uae_u32
253: #define MEMRW uae_u32
254:
255: #define FW uae_u32
256: #define FR uae_u32
257: #define FRW uae_u32
258:
259: #define MIDFUNC(nargs,func,args) void func args
260: #define MENDFUNC(nargs,func,args)
261: #define COMPCALL(func) func
262:
263: #define LOWFUNC(flags,mem,nargs,func,args) STATIC_INLINE void func args
264: #define LENDFUNC(flags,mem,nargs,func,args)
265:
266: #if USE_OPTIMIZER
267: #define REGALLOC_O 2
268: #define PEEPHOLE_O 3 /* Has to be >= REGALLOC */
269: #define DECLARE(func) extern void func; extern void do_##func
270: #else
271: #define REGALLOC_O 2000000
272: #define PEEPHOLE_O 2000000
273: #define DECLARE(func) extern void func
274: #endif
275:
276:
277: /* What we expose to the outside */
278: DECLARE(bt_l_ri(R4 r, IMM i));
279: DECLARE(bt_l_rr(R4 r, R4 b));
280: DECLARE(btc_l_ri(RW4 r, IMM i));
281: DECLARE(btc_l_rr(RW4 r, R4 b));
282: DECLARE(bts_l_ri(RW4 r, IMM i));
283: DECLARE(bts_l_rr(RW4 r, R4 b));
284: DECLARE(btr_l_ri(RW4 r, IMM i));
285: DECLARE(btr_l_rr(RW4 r, R4 b));
286: DECLARE(mov_l_rm(W4 d, IMM s));
287: DECLARE(call_r(R4 r));
288: DECLARE(sub_l_mi(IMM d, IMM s));
289: DECLARE(mov_l_mi(IMM d, IMM s));
290: DECLARE(mov_w_mi(IMM d, IMM s));
291: DECLARE(mov_b_mi(IMM d, IMM s));
292: DECLARE(rol_b_ri(RW1 r, IMM i));
293: DECLARE(rol_w_ri(RW2 r, IMM i));
294: DECLARE(rol_l_ri(RW4 r, IMM i));
295: DECLARE(rol_l_rr(RW4 d, R1 r));
296: DECLARE(rol_w_rr(RW2 d, R1 r));
297: DECLARE(rol_b_rr(RW1 d, R1 r));
298: DECLARE(shll_l_rr(RW4 d, R1 r));
299: DECLARE(shll_w_rr(RW2 d, R1 r));
300: DECLARE(shll_b_rr(RW1 d, R1 r));
301: DECLARE(ror_b_ri(R1 r, IMM i));
302: DECLARE(ror_w_ri(R2 r, IMM i));
303: DECLARE(ror_l_ri(R4 r, IMM i));
304: DECLARE(ror_l_rr(R4 d, R1 r));
305: DECLARE(ror_w_rr(R2 d, R1 r));
306: DECLARE(ror_b_rr(R1 d, R1 r));
307: DECLARE(shrl_l_rr(RW4 d, R1 r));
308: DECLARE(shrl_w_rr(RW2 d, R1 r));
309: DECLARE(shrl_b_rr(RW1 d, R1 r));
310: DECLARE(shra_l_rr(RW4 d, R1 r));
311: DECLARE(shra_w_rr(RW2 d, R1 r));
312: DECLARE(shra_b_rr(RW1 d, R1 r));
313: DECLARE(shll_l_ri(RW4 r, IMM i));
314: DECLARE(shll_w_ri(RW2 r, IMM i));
315: DECLARE(shll_b_ri(RW1 r, IMM i));
316: DECLARE(shrl_l_ri(RW4 r, IMM i));
317: DECLARE(shrl_w_ri(RW2 r, IMM i));
318: DECLARE(shrl_b_ri(RW1 r, IMM i));
319: DECLARE(shra_l_ri(RW4 r, IMM i));
320: DECLARE(shra_w_ri(RW2 r, IMM i));
321: DECLARE(shra_b_ri(RW1 r, IMM i));
322: DECLARE(setcc(W1 d, IMM cc));
323: DECLARE(setcc_m(IMM d, IMM cc));
324: DECLARE(cmov_b_rr(RW1 d, R1 s, IMM cc));
325: DECLARE(cmov_w_rr(RW2 d, R2 s, IMM cc));
326: DECLARE(cmov_l_rr(RW4 d, R4 s, IMM cc));
327: DECLARE(cmov_l_rm(RW4 d, IMM s, IMM cc));
328: DECLARE(bsf_l_rr(W4 d, R4 s));
329: DECLARE(pop_m(IMM d));
330: DECLARE(push_m(IMM d));
331: DECLARE(pop_l(W4 d));
332: DECLARE(push_l_i(IMM i));
333: DECLARE(push_l(R4 s));
334: DECLARE(clear_16(RW4 r));
335: DECLARE(clear_8(RW4 r));
336: DECLARE(sign_extend_16_rr(W4 d, R2 s));
337: DECLARE(sign_extend_8_rr(W4 d, R1 s));
338: DECLARE(zero_extend_16_rr(W4 d, R2 s));
339: DECLARE(zero_extend_8_rr(W4 d, R1 s));
340: DECLARE(imul_64_32(RW4 d, RW4 s));
341: DECLARE(mul_64_32(RW4 d, RW4 s));
342: DECLARE(imul_32_32(RW4 d, R4 s));
343: DECLARE(mov_b_rr(W1 d, R1 s));
344: DECLARE(mov_w_rr(W2 d, R2 s));
345: DECLARE(mov_l_rrm_indexed(W4 d, R4 baser, R4 index));
346: DECLARE(mov_w_rrm_indexed(W2 d, R4 baser, R4 index));
347: DECLARE(mov_b_rrm_indexed(W1 d, R4 baser, R4 index));
348: DECLARE(mov_l_mrr_indexed(R4 baser, R4 index, R4 s));
349: DECLARE(mov_w_mrr_indexed(R4 baser, R4 index, R2 s));
350: DECLARE(mov_b_mrr_indexed(R4 baser, R4 index, R1 s));
351: DECLARE(mov_l_rm_indexed(W4 d, IMM base, R4 index));
352: DECLARE(mov_l_rR(W4 d, R4 s, IMM offset));
353: DECLARE(mov_w_rR(W2 d, R4 s, IMM offset));
354: DECLARE(mov_b_rR(W1 d, R4 s, IMM offset));
355: DECLARE(mov_l_brR(W4 d, R4 s, IMM offset));
356: DECLARE(mov_w_brR(W2 d, R4 s, IMM offset));
357: DECLARE(mov_b_brR(W1 d, R4 s, IMM offset));
358: DECLARE(mov_l_Ri(R4 d, IMM i, IMM offset));
359: DECLARE(mov_w_Ri(R4 d, IMM i, IMM offset));
360: DECLARE(mov_b_Ri(R4 d, IMM i, IMM offset));
361: DECLARE(mov_l_Rr(R4 d, R4 s, IMM offset));
362: DECLARE(mov_w_Rr(R4 d, R2 s, IMM offset));
363: DECLARE(mov_b_Rr(R4 d, R1 s, IMM offset));
364: DECLARE(lea_l_brr(W4 d, R4 s, IMM offset));
365: DECLARE(lea_l_brr_indexed(W4 d, R4 s, R4 index, IMM factor, IMM offset));
366: DECLARE(mov_l_bRr(R4 d, R4 s, IMM offset));
367: DECLARE(mov_w_bRr(R4 d, R2 s, IMM offset));
368: DECLARE(mov_b_bRr(R4 d, R1 s, IMM offset));
369: DECLARE(gen_bswap_32(RW4 r));
370: DECLARE(gen_bswap_16(RW2 r));
371: DECLARE(mov_l_rr(W4 d, R4 s));
372: DECLARE(mov_l_mr(IMM d, R4 s));
373: DECLARE(mov_w_mr(IMM d, R2 s));
374: DECLARE(mov_w_rm(W2 d, IMM s));
375: DECLARE(mov_b_mr(IMM d, R1 s));
376: DECLARE(mov_b_rm(W1 d, IMM s));
377: DECLARE(mov_l_ri(W4 d, IMM s));
378: DECLARE(mov_w_ri(W2 d, IMM s));
379: DECLARE(mov_b_ri(W1 d, IMM s));
380: DECLARE(add_l_mi(IMM d, IMM s) );
381: DECLARE(add_w_mi(IMM d, IMM s) );
382: DECLARE(add_b_mi(IMM d, IMM s) );
383: DECLARE(test_l_ri(R4 d, IMM i));
384: DECLARE(test_l_rr(R4 d, R4 s));
385: DECLARE(test_w_rr(R2 d, R2 s));
386: DECLARE(test_b_rr(R1 d, R1 s));
387: DECLARE(and_l_ri(RW4 d, IMM i));
388: DECLARE(and_l(RW4 d, R4 s));
389: DECLARE(and_w(RW2 d, R2 s));
390: DECLARE(and_b(RW1 d, R1 s));
391: DECLARE(or_l_ri(RW4 d, IMM i));
392: DECLARE(or_l(RW4 d, R4 s));
393: DECLARE(or_w(RW2 d, R2 s));
394: DECLARE(or_b(RW1 d, R1 s));
395: DECLARE(adc_l(RW4 d, R4 s));
396: DECLARE(adc_w(RW2 d, R2 s));
397: DECLARE(adc_b(RW1 d, R1 s));
398: DECLARE(add_l(RW4 d, R4 s));
399: DECLARE(add_w(RW2 d, R2 s));
400: DECLARE(add_b(RW1 d, R1 s));
401: DECLARE(sub_l_ri(RW4 d, IMM i));
402: DECLARE(sub_w_ri(RW2 d, IMM i));
403: DECLARE(sub_b_ri(RW1 d, IMM i));
404: DECLARE(add_l_ri(RW4 d, IMM i));
405: DECLARE(add_w_ri(RW2 d, IMM i));
406: DECLARE(add_b_ri(RW1 d, IMM i));
407: DECLARE(sbb_l(RW4 d, R4 s));
408: DECLARE(sbb_w(RW2 d, R2 s));
409: DECLARE(sbb_b(RW1 d, R1 s));
410: DECLARE(sub_l(RW4 d, R4 s));
411: DECLARE(sub_w(RW2 d, R2 s));
412: DECLARE(sub_b(RW1 d, R1 s));
413: DECLARE(cmp_l(R4 d, R4 s));
414: DECLARE(cmp_l_ri(R4 r, IMM i));
415: DECLARE(cmp_w(R2 d, R2 s));
416: DECLARE(cmp_b(R1 d, R1 s));
417: DECLARE(xor_l(RW4 d, R4 s));
418: DECLARE(xor_w(RW2 d, R2 s));
419: DECLARE(xor_b(RW1 d, R1 s));
420: DECLARE(live_flags(void));
421: DECLARE(dont_care_flags(void));
422: DECLARE(duplicate_carry(void));
423: DECLARE(restore_carry(void));
424: DECLARE(start_needflags(void));
425: DECLARE(end_needflags(void));
426: DECLARE(make_flags_live(void));
427: DECLARE(call_r_11(R4 r, W4 out1, R4 in1, IMM osize, IMM isize));
428: DECLARE(call_r_02(R4 r, R4 in1, R4 in2, IMM isize1, IMM isize2));
429: DECLARE(readmem_new(R4 address, W4 dest, IMM offset, IMM size, W4 tmp));
430: DECLARE(writemem_new(R4 address, R4 source, IMM offset, IMM size, W4 tmp));
431: DECLARE(forget_about(W4 r));
432: DECLARE(nop(void));
433:
434: DECLARE(f_forget_about(FW r));
435: DECLARE(fmov_pi(FW r));
436: DECLARE(fmov_log10_2(FW r));
437: DECLARE(fmov_log2_e(FW r));
438: DECLARE(fmov_loge_2(FW r));
439: DECLARE(fmov_1(FW r));
440: DECLARE(fmov_0(FW r));
441: DECLARE(fmov_rm(FW r, MEMR m));
442: DECLARE(fmov_mr(MEMW m, FR r));
443: DECLARE(fmovi_rm(FW r, MEMR m));
444: DECLARE(fmovi_mrb(MEMW m, FR r, double *bounds));
445: DECLARE(fmovs_rm(FW r, MEMR m));
446: DECLARE(fmovs_mr(MEMW m, FR r));
447: DECLARE(fcuts_r(FRW r));
448: DECLARE(fcut_r(FRW r));
449: DECLARE(fmovl_ri(FW r, IMMS i));
450: DECLARE(fmovs_ri(FW r, IMM i));
451: DECLARE(fmov_ri(FW r, IMM i1, IMM i2));
452: DECLARE(fmov_ext_ri(FW r, IMM i1, IMM i2, IMM i3));
453: DECLARE(fmov_ext_mr(MEMW m, FR r));
454: DECLARE(fmov_ext_rm(FW r, MEMR m));
455: DECLARE(fmov_rr(FW d, FR s));
456: DECLARE(fldcw_m_indexed(R4 index, IMM base));
457: DECLARE(ftst_r(FR r));
458: DECLARE(dont_care_fflags(void));
459: DECLARE(fsqrt_rr(FW d, FR s));
460: DECLARE(fabs_rr(FW d, FR s));
461: DECLARE(frndint_rr(FW d, FR s));
462: DECLARE(fgetexp_rr(FW d, FR s));
463: DECLARE(fgetman_rr(FW d, FR s));
464: DECLARE(fsin_rr(FW d, FR s));
465: DECLARE(fcos_rr(FW d, FR s));
466: DECLARE(ftan_rr(FW d, FR s));
467: DECLARE(fsincos_rr(FW d, FW c, FR s));
468: DECLARE(fscale_rr(FRW d, FR s));
469: DECLARE(ftwotox_rr(FW d, FR s));
470: DECLARE(fetox_rr(FW d, FR s));
471: DECLARE(fetoxM1_rr(FW d, FR s));
472: DECLARE(ftentox_rr(FW d, FR s));
473: DECLARE(flog2_rr(FW d, FR s));
474: DECLARE(flogN_rr(FW d, FR s));
475: DECLARE(flogNP1_rr(FW d, FR s));
476: DECLARE(flog10_rr(FW d, FR s));
477: DECLARE(fasin_rr(FW d, FR s));
478: DECLARE(facos_rr(FW d, FR s));
479: DECLARE(fatan_rr(FW d, FR s));
480: DECLARE(fatanh_rr(FW d, FR s));
481: DECLARE(fsinh_rr(FW d, FR s));
482: DECLARE(fcosh_rr(FW d, FR s));
483: DECLARE(ftanh_rr(FW d, FR s));
484: DECLARE(fneg_rr(FW d, FR s));
485: DECLARE(fadd_rr(FRW d, FR s));
486: DECLARE(fsub_rr(FRW d, FR s));
487: DECLARE(fmul_rr(FRW d, FR s));
488: DECLARE(frem_rr(FRW d, FR s));
489: DECLARE(frem1_rr(FRW d, FR s));
490: DECLARE(fdiv_rr(FRW d, FR s));
491: DECLARE(fcmp_rr(FR d, FR s));
492: DECLARE(fflags_into_flags(W2 tmp));
493:
494: extern int failure;
495: #define FAIL(x) do { failure|=x; } while (0)
496:
497: /* Convenience functions exposed to gencomp */
498: extern uae_u32 m68k_pc_offset;
499: extern void readbyte(int address, int dest, int tmp);
500: extern void readword(int address, int dest, int tmp);
501: extern void readlong(int address, int dest, int tmp);
502: extern void writebyte(int address, int source, int tmp);
503: extern void writeword(int address, int source, int tmp);
504: extern void writelong(int address, int source, int tmp);
505: extern void writeword_clobber(int address, int source, int tmp);
506: extern void writelong_clobber(int address, int source, int tmp);
507: extern void get_n_addr(int address, int dest, int tmp);
508: extern void get_n_addr_jmp(int address, int dest, int tmp);
509: extern void calc_disp_ea_020(int base, uae_u32 dp, int target, int tmp);
510: extern int kill_rodent(int r);
511: extern void sync_m68k_pc(void);
512: extern uae_u32 get_const(int r);
513: extern int is_const(int r);
514: extern void register_branch(uae_u32 not_taken, uae_u32 taken, uae_u8 cond);
515: extern void empty_optimizer(void);
516:
517: #define comp_get_ibyte(o) do_get_mem_byte((uae_u8 *)(comp_pc_p + (o) + 1))
518: #define comp_get_iword(o) do_get_mem_word((uae_u16 *)(comp_pc_p + (o)))
519: #define comp_get_ilong(o) do_get_mem_long((uae_u32 *)(comp_pc_p + (o)))
520:
521: struct blockinfo_t;
522:
523: typedef struct dep_t {
524: uae_u32* jmp_off;
525: struct blockinfo_t* target;
526: struct dep_t** prev_p;
527: struct dep_t* next;
528: } dependency;
529:
530: typedef struct blockinfo_t {
531: uae_s32 count;
532: cpuop_func* direct_handler_to_use;
533: cpuop_func* handler_to_use;
534: /* The direct handler does not check for the correct address */
535:
536: cpuop_func* handler;
537: cpuop_func* direct_handler;
538:
539: cpuop_func* direct_pen;
540: cpuop_func* direct_pcc;
541:
542: uae_u8* nexthandler;
543: uae_u8* pc_p;
544:
545: uae_u32 c1;
546: uae_u32 c2;
547: uae_u32 len;
548:
549: struct blockinfo_t* next_same_cl;
550: struct blockinfo_t** prev_same_cl_p;
551: struct blockinfo_t* next;
552: struct blockinfo_t** prev_p;
553:
554: uae_u32 min_pcp;
555: uae_u8 optlevel;
556: uae_u8 needed_flags;
557: uae_u8 status;
558: uae_u8 havestate;
559:
560: dependency dep[2]; /* Holds things we depend on */
561: dependency* deplist; /* List of things that depend on this */
562: smallstate env;
563: } blockinfo;
564:
565: #define BI_NEW 0
566: #define BI_COUNTING 1
567: #define BI_TARGETTED 2
568:
569: typedef struct {
570: uae_u8 type;
571: uae_u8 reg;
572: uae_u32 next;
573: } regacc;
574:
575: void execute_normal(void);
576: void exec_nostats(void);
577: void do_nothing(void);
578:
579: void comp_fdbcc_opp (uae_u32 opcode, uae_u16 extra);
580: void comp_fscc_opp (uae_u32 opcode, uae_u16 extra);
581: void comp_ftrapcc_opp (uae_u32 opcode, uaecptr oldpc);
582: void comp_fbcc_opp (uae_u32 opcode);
583: void comp_fsave_opp (uae_u32 opcode);
584: void comp_frestore_opp (uae_u32 opcode);
585: void comp_fpp_opp (uae_u32 opcode, uae_u16 extra);
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.