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1.1.1.3 root 1: /*
2: * UAE - The Un*x Amiga Emulator
3: *
4: * MC68000 emulation
5: *
6: * Copyright 1995 Bernd Schmidt
7: */
8:
1.1.1.6 ! root 9: #ifndef UAE_NEWCPU_H
! 10: #define UAE_NEWCPU_H
1.1.1.3 root 11:
1.1.1.6 ! root 12: #include "uae/types.h"
1.1.1.3 root 13: #include "readcpu.h"
1.1.1.6 ! root 14: #include "machdep/m68k.h"
1.1.1.3 root 15: #include "compat.h"
16: #include "maccess.h"
17: #include "events.h"
18: #include "memory.h"
19: #include "custom.h"
20:
21: /* Possible exceptions sources for M68000_Exception() and Exception() */
1.1.1.5 root 22: // TODO : remove when not used anymore in m68000.c
23: #define M68000_EXC_SRC_CPU 1 /* Direct CPU exception */
24: #define M68000_EXC_SRC_AUTOVEC 2 /* Auto-vector exception (e.g. VBL) */
25: #define M68000_EXC_SRC_INT_MFP 3 /* MFP interrupt exception */
26: #define M68000_EXC_SRC_INT_DSP 4 /* DSP interrupt exception */
1.1.1.3 root 27:
28:
29: /* Special flags */
30: #define SPCFLAG_DEBUGGER 1
31: #define SPCFLAG_STOP 2
32: #define SPCFLAG_BUSERROR 4
33: #define SPCFLAG_INT 8
34: #define SPCFLAG_BRK 0x10
35: #define SPCFLAG_EXTRA_CYCLES 0x20
36: #define SPCFLAG_TRACE 0x40
37: #define SPCFLAG_DOTRACE 0x80
38: #define SPCFLAG_DOINT 0x100
39: #define SPCFLAG_MFP 0x200
40: #define SPCFLAG_EXEC 0x400
41: #define SPCFLAG_MODE_CHANGE 0x800
1.1.1.4 root 42: #define SPCFLAG_DSP 0x1000
1.1.1.3 root 43:
1.1.1.5 root 44: #ifdef WITH_SOFTFLOAT
45: #include <softfloat.h>
46: #endif
47:
1.1.1.3 root 48: #ifndef SET_CFLG
49:
50: #define SET_CFLG(x) (CFLG() = (x))
51: #define SET_NFLG(x) (NFLG() = (x))
52: #define SET_VFLG(x) (VFLG() = (x))
53: #define SET_ZFLG(x) (ZFLG() = (x))
54: #define SET_XFLG(x) (XFLG() = (x))
55:
56: #define GET_CFLG() CFLG()
57: #define GET_NFLG() NFLG()
58: #define GET_VFLG() VFLG()
59: #define GET_ZFLG() ZFLG()
60: #define GET_XFLG() XFLG()
61:
62: #define CLEAR_CZNV() do { \
63: SET_CFLG (0); \
64: SET_ZFLG (0); \
65: SET_NFLG (0); \
66: SET_VFLG (0); \
67: } while (0)
68:
69: #define COPY_CARRY() (SET_XFLG (GET_CFLG ()))
70: #endif
71:
72: extern const int areg_byteinc[];
73: extern const int imm8_table[];
74:
75: extern int movem_index1[256];
76: extern int movem_index2[256];
77: extern int movem_next[256];
78:
79: #ifdef FPUEMU
80: extern int fpp_movem_index1[256];
81: extern int fpp_movem_index2[256];
82: extern int fpp_movem_next[256];
83: #endif
84:
1.1.1.5 root 85: extern int bus_error_offset;
1.1.1.3 root 86:
1.1.1.5 root 87: typedef uae_u32 REGPARAM3 cpuop_func (uae_u32) REGPARAM;
1.1.1.3 root 88: typedef void REGPARAM3 cpuop_func_ce (uae_u32) REGPARAM;
89:
90: struct cputbl {
91: cpuop_func *handler;
92: uae_u16 opcode;
1.1.1.5 root 93: uae_s8 length;
94: uae_s8 disp020[2];
95: uae_u8 branch;
1.1.1.3 root 96: };
97:
98: #ifdef JIT
1.1.1.6 ! root 99: #define MAX_JIT_CACHE 16384
1.1.1.5 root 100: typedef uae_u32 REGPARAM3 compop_func (uae_u32) REGPARAM;
1.1.1.3 root 101:
1.1.1.6 ! root 102: #define COMP_OPCODE_ISJUMP 0x0001
! 103: #define COMP_OPCODE_LONG_OPCODE 0x0002
! 104: #define COMP_OPCODE_CMOV 0x0004
! 105: #define COMP_OPCODE_ISADDX 0x0008
! 106: #define COMP_OPCODE_ISCJUMP 0x0010
! 107: #define COMP_OPCODE_USES_FPU 0x0020
! 108:
1.1.1.3 root 109: struct comptbl {
110: compop_func *handler;
111: uae_u32 opcode;
112: int specific;
113: };
114: #endif
115:
1.1.1.5 root 116: extern uae_u32 REGPARAM3 op_illg (uae_u32) REGPARAM;
117: extern void REGPARAM3 op_unimpl (uae_u16) REGPARAM;
1.1.1.3 root 118:
119: typedef uae_u8 flagtype;
120:
121: #ifdef FPUEMU
122:
1.1.1.5 root 123: #ifdef USE_LONG_DOUBLE
1.1.1.3 root 124: typedef long double fptype;
125: #define LDPTR tbyte ptr
126: #else
127: typedef double fptype;
128: #define LDPTR qword ptr
129: #endif
130: #endif
131:
1.1.1.5 root 132: #define MAX68020CYCLES 4
133:
134: #define CPU_PIPELINE_MAX 4
1.1.1.3 root 135: #define CPU000_MEM_CYCLE 4
136: #define CPU000_CLOCK_MULT 2
137: #define CPU020_MEM_CYCLE 3
138: #define CPU020_CLOCK_MULT 4
139:
140: #define CACHELINES020 64
141: struct cache020
142: {
143: uae_u32 data;
144: uae_u32 tag;
145: bool valid;
146: };
147:
148: #define CACHELINES030 16
149: struct cache030
150: {
151: uae_u32 data[4];
152: bool valid[4];
153: uae_u32 tag;
154: };
155:
156: #define CACHESETS040 64
157: #define CACHELINES040 4
158: struct cache040
159: {
160: uae_u32 data[CACHELINES040][4];
1.1.1.5 root 161: bool dirty[CACHELINES040][4];
1.1.1.3 root 162: bool valid[CACHELINES040];
163: uae_u32 tag[CACHELINES040];
164: };
165:
1.1.1.4 root 166: struct mmufixup
167: {
168: int reg;
169: uae_u32 value;
170: };
171: extern struct mmufixup mmufixup[2];
1.1.1.3 root 172:
1.1.1.5 root 173: typedef struct
174: {
175: fptype fp;
176: #ifdef WITH_SOFTFLOAT
177: floatx80 fpx;
178: #endif
179: } fpdata;
180:
1.1.1.3 root 181: struct regstruct
182: {
183: uae_u32 regs[16];
184:
185: uae_u32 pc;
186: uae_u8 *pc_p;
187: uae_u8 *pc_oldp;
1.1.1.5 root 188: uae_u16 opcode;
189: uae_u32 instruction_pc;
1.1.1.3 root 190:
1.1.1.5 root 191: uae_u16 irc, ir, db;
1.1.1.6 ! root 192: volatile uae_atomic spcflags;
1.1.1.5 root 193: uae_u32 last_prefetch;
194: uae_u32 chipset_latch_rw;
195: uae_u32 chipset_latch_read;
196: uae_u32 chipset_latch_write;
1.1.1.3 root 197:
198: uaecptr usp, isp, msp;
199: uae_u16 sr;
200: flagtype t1;
201: flagtype t0;
202: flagtype s;
203: flagtype m;
204: flagtype x;
205: flagtype stopped;
1.1.1.5 root 206: int halted;
207: int exception;
1.1.1.3 root 208: int intmask;
209: int ipl, ipl_pin;
210:
211: uae_u32 vbr, sfc, dfc;
212:
213: #ifdef FPUEMU
1.1.1.5 root 214: fpdata fp[8];
215: fpdata fp_result;
216: uae_u32 fp_result_status;
1.1.1.3 root 217: uae_u32 fpcr, fpsr, fpiar;
1.1.1.5 root 218: uae_u32 fpu_state;
219: uae_u32 fpu_exp_state;
220: fpdata exp_src1, exp_src2;
221: uae_u32 exp_pack[3];
222: uae_u16 exp_opcode, exp_extra, exp_type;
223: uae_u16 exp_size;
224: bool fp_exception;
225: bool fp_branch;
1.1.1.3 root 226: #endif
227: #ifndef CPUEMU_68000_ONLY
228: uae_u32 cacr, caar;
229: uae_u32 itt0, itt1, dtt0, dtt1;
230: uae_u32 tcr, mmusr, urp, srp, buscr;
1.1.1.5 root 231: uae_u32 mmu_fslw;
232: uae_u32 mmu_fault_addr, mmu_effective_addr;
1.1.1.3 root 233: uae_u16 mmu_ssw;
1.1.1.5 root 234: uae_u32 wb2_address;
1.1.1.3 root 235: uae_u32 wb3_data;
1.1.1.5 root 236: uae_u8 wb3_status, wb2_status;
1.1.1.3 root 237: int mmu_enabled;
1.1.1.5 root 238: int mmu_page_size;
1.1.1.3 root 239: #endif
240:
241: uae_u32 pcr;
242: uae_u32 address_space_mask;
243:
1.1.1.5 root 244: uae_u32 prefetch020[CPU_PIPELINE_MAX];
245: uae_u32 prefetch020addr;
246: uae_u32 cacheholdingdata020;
247: uae_u32 cacheholdingaddr020;
248: int pipeline_pos;
249: int pipeline_r8[2];
250: int pipeline_stop;
1.1.1.3 root 251: int ce020memcycles;
1.1.1.5 root 252: int ce020extracycles;
253: bool ce020memcycle_data;
254: int ce020_tail;
255: frame_time_t ce020_tail_cycles;
256: int memory_waitstate_cycles;
1.1.1.3 root 257: };
258:
259: extern struct regstruct regs;
260:
1.1.1.5 root 261: #define MAX_CPUTRACESIZE 128
262: struct cputracememory
263: {
264: uae_u32 addr;
265: uae_u32 data;
266: int mode;
267: };
268:
269: struct cputracestruct
270: {
271: uae_u32 regs[16];
272: uae_u32 usp, isp, pc;
273: uae_u16 ir, irc, sr, opcode;
274: int intmask, stopped, state;
275:
276: uae_u32 msp, vbr;
277: uae_u32 cacr, caar;
278: uae_u32 prefetch020[CPU_PIPELINE_MAX];
279: uae_u32 prefetch020addr;
280: uae_u32 cacheholdingdata020;
281: uae_u32 cacheholdingaddr020;
282: struct cache020 caches020[CACHELINES020];
283:
284: uae_u32 startcycles;
285: int needendcycles;
286: int memoryoffset;
287: int cyclecounter, cyclecounter_pre, cyclecounter_post;
288: int readcounter, writecounter;
289: struct cputracememory ctm[MAX_CPUTRACESIZE];
290: };
291:
1.1.1.3 root 292: STATIC_INLINE uae_u32 munge24 (uae_u32 x)
293: {
294: return x & regs.address_space_mask;
295: }
296:
297: extern int mmu_enabled, mmu_triggered;
298: extern int cpu_cycles;
299: extern int cpucycleunit;
1.1.1.5 root 300: extern int m68k_pc_indirect;
1.1.1.6 ! root 301:
! 302: #ifndef WINUAE_FOR_HATARI
! 303: STATIC_INLINE void set_special_exter(uae_u32 x)
! 304: {
! 305: atomic_or(®s.spcflags, x);
! 306: }
! 307: STATIC_INLINE void set_special (uae_u32 x)
! 308: {
! 309: atomic_or(®s.spcflags, x);
! 310: cycles_do_special ();
! 311: }
! 312:
! 313: STATIC_INLINE void unset_special (uae_u32 x)
! 314: {
! 315: atomic_and(®s.spcflags, ~x);
! 316: }
! 317: #else
1.1.1.3 root 318: STATIC_INLINE void set_special (uae_u32 x)
319: {
320: regs.spcflags |= x;
321: cycles_do_special ();
322: }
323:
324: STATIC_INLINE void unset_special (uae_u32 x)
325: {
326: regs.spcflags &= ~x;
327: }
328:
1.1.1.6 ! root 329: #endif
! 330:
1.1.1.3 root 331: #define m68k_dreg(r,num) ((r).regs[(num)])
332: #define m68k_areg(r,num) (((r).regs + 8)[(num)])
333:
1.1.1.5 root 334: extern uae_u32(*x_prefetch)(int);
335: extern uae_u32(*x_get_byte)(uaecptr addr);
336: extern uae_u32(*x_get_word)(uaecptr addr);
337: extern uae_u32(*x_get_long)(uaecptr addr);
338: extern void(*x_put_byte)(uaecptr addr, uae_u32 v);
339: extern void(*x_put_word)(uaecptr addr, uae_u32 v);
340: extern void(*x_put_long)(uaecptr addr, uae_u32 v);
341: extern uae_u32(*x_next_iword)(void);
342: extern uae_u32(*x_next_ilong)(void);
343: extern uae_u32(*x_get_ilong)(int);
344: extern uae_u32(*x_get_iword)(int);
345: extern uae_u32(*x_get_ibyte)(int);
346:
347: extern uae_u32(*x_cp_get_byte)(uaecptr addr);
348: extern uae_u32(*x_cp_get_word)(uaecptr addr);
349: extern uae_u32(*x_cp_get_long)(uaecptr addr);
350: extern void(*x_cp_put_byte)(uaecptr addr, uae_u32 v);
351: extern void(*x_cp_put_word)(uaecptr addr, uae_u32 v);
352: extern void(*x_cp_put_long)(uaecptr addr, uae_u32 v);
353: extern uae_u32(*x_cp_next_iword)(void);
354: extern uae_u32(*x_cp_next_ilong)(void);
355:
356: extern uae_u32(REGPARAM3 *x_cp_get_disp_ea_020)(uae_u32 base, int idx) REGPARAM;
357:
358: /* direct (regs.pc_p) access */
359:
360: STATIC_INLINE void m68k_setpc(uaecptr newpc)
1.1.1.3 root 361: {
1.1.1.5 root 362: regs.pc_p = regs.pc_oldp = get_real_address(newpc);
363: regs.instruction_pc = regs.pc = newpc;
1.1.1.3 root 364: }
1.1.1.5 root 365: STATIC_INLINE uaecptr m68k_getpc(void)
1.1.1.3 root 366: {
367: return (uaecptr)(regs.pc + ((uae_u8*)regs.pc_p - (uae_u8*)regs.pc_oldp));
368: }
369: #define M68K_GETPC m68k_getpc()
1.1.1.5 root 370: STATIC_INLINE uaecptr m68k_getpc_p(uae_u8 *p)
1.1.1.3 root 371: {
372: return (uaecptr)(regs.pc + ((uae_u8*)p - (uae_u8*)regs.pc_oldp));
373: }
1.1.1.5 root 374: STATIC_INLINE void m68k_incpc(int o)
1.1.1.3 root 375: {
376: regs.pc_p += o;
377: }
378:
1.1.1.5 root 379: STATIC_INLINE uae_u32 get_dibyte(int o)
1.1.1.3 root 380: {
1.1.1.5 root 381: return do_get_mem_byte((uae_u8 *)((regs).pc_p + (o) + 1));
1.1.1.3 root 382: }
1.1.1.5 root 383: STATIC_INLINE uae_u32 get_diword(int o)
1.1.1.3 root 384: {
1.1.1.5 root 385: return do_get_mem_word((uae_u16 *)((regs).pc_p + (o)));
1.1.1.3 root 386: }
1.1.1.5 root 387: STATIC_INLINE uae_u32 get_dilong(int o)
1.1.1.3 root 388: {
1.1.1.5 root 389: return do_get_mem_long((uae_u32 *)((regs).pc_p + (o)));
1.1.1.3 root 390: }
1.1.1.5 root 391: STATIC_INLINE uae_u32 next_diword(void)
1.1.1.3 root 392: {
1.1.1.5 root 393: uae_u32 r = do_get_mem_word((uae_u16 *)((regs).pc_p));
394: m68k_incpc(2);
395: return r;
396: }
397: STATIC_INLINE uae_u32 next_dilong(void)
398: {
399: uae_u32 r = do_get_mem_long((uae_u32 *)((regs).pc_p));
400: m68k_incpc(4);
401: return r;
1.1.1.3 root 402: }
403:
1.1.1.5 root 404: STATIC_INLINE void m68k_do_bsr(uaecptr oldpc, uae_s32 offset)
1.1.1.3 root 405: {
1.1.1.5 root 406: m68k_areg(regs, 7) -= 4;
407: put_long(m68k_areg(regs, 7), oldpc);
408: m68k_incpc(offset);
1.1.1.3 root 409: }
1.1.1.5 root 410: STATIC_INLINE void m68k_do_rts(void)
1.1.1.3 root 411: {
1.1.1.5 root 412: uae_u32 newpc = get_long(m68k_areg(regs, 7));
413: m68k_setpc(newpc);
414: m68k_areg(regs, 7) += 4;
1.1.1.3 root 415: }
416:
1.1.1.5 root 417: /* indirect (regs.pc) access */
418:
419: STATIC_INLINE void m68k_setpci(uaecptr newpc)
1.1.1.3 root 420: {
1.1.1.5 root 421: regs.instruction_pc = regs.pc = newpc;
1.1.1.3 root 422: }
1.1.1.5 root 423: STATIC_INLINE uaecptr m68k_getpci(void)
1.1.1.3 root 424: {
1.1.1.5 root 425: return regs.pc;
426: }
427: STATIC_INLINE void m68k_incpci(int o)
428: {
429: regs.pc += o;
1.1.1.3 root 430: }
431:
1.1.1.5 root 432: STATIC_INLINE uae_u32 get_iibyte(int o)
1.1.1.3 root 433: {
1.1.1.5 root 434: return get_wordi(m68k_getpci() + (o)) & 0xff;
1.1.1.3 root 435: }
1.1.1.5 root 436: STATIC_INLINE uae_u32 get_iiword(int o)
1.1.1.3 root 437: {
1.1.1.5 root 438: return get_wordi(m68k_getpci() + (o));
1.1.1.3 root 439: }
1.1.1.5 root 440: STATIC_INLINE uae_u32 get_iilong(int o)
1.1.1.3 root 441: {
1.1.1.5 root 442: return get_longi(m68k_getpci () + (o));
1.1.1.3 root 443: }
444:
1.1.1.5 root 445: STATIC_INLINE uae_u32 next_iibyte (void)
1.1.1.3 root 446: {
1.1.1.5 root 447: uae_u32 r = get_iibyte (0);
448: m68k_incpci (2);
1.1.1.3 root 449: return r;
450: }
1.1.1.5 root 451: STATIC_INLINE uae_u32 next_iiword (void)
1.1.1.3 root 452: {
1.1.1.5 root 453: uae_u32 r = get_iiword (0);
454: m68k_incpci (2);
1.1.1.3 root 455: return r;
456: }
1.1.1.5 root 457: STATIC_INLINE uae_u32 next_iiwordi (void)
1.1.1.3 root 458: {
1.1.1.5 root 459: uae_u32 r = get_wordi(m68k_getpci());
460: m68k_incpci (2);
1.1.1.3 root 461: return r;
462: }
1.1.1.5 root 463: STATIC_INLINE uae_u32 next_iilong (void)
1.1.1.3 root 464: {
1.1.1.5 root 465: uae_u32 r = get_iilong(0);
466: m68k_incpci (4);
1.1.1.3 root 467: return r;
468: }
1.1.1.5 root 469: STATIC_INLINE uae_u32 next_iilongi (void)
1.1.1.3 root 470: {
1.1.1.5 root 471: uae_u32 r = get_longi (m68k_getpci ());
472: m68k_incpci (4);
1.1.1.3 root 473: return r;
474: }
475:
1.1.1.5 root 476: STATIC_INLINE void m68k_do_bsri(uaecptr oldpc, uae_s32 offset)
477: {
478: m68k_areg(regs, 7) -= 4;
479: put_long(m68k_areg(regs, 7), oldpc);
480: m68k_incpci(offset);
481: }
482: STATIC_INLINE void m68k_do_rtsi(void)
483: {
484: uae_u32 newpc = get_long(m68k_areg(regs, 7));
485: m68k_setpci(newpc);
486: m68k_areg(regs, 7) += 4;
487: }
488:
489: /* indirect jit friendly versions */
1.1.1.3 root 490:
1.1.1.5 root 491: STATIC_INLINE uae_u32 get_iibyte_jit(int o)
492: {
493: return get_wordi(m68k_getpc() + (o)) & 0xff;
494: }
495: STATIC_INLINE uae_u32 get_iiword_jit(int o)
496: {
497: return get_wordi(m68k_getpc() + (o));
498: }
499: STATIC_INLINE uae_u32 get_iilong_jit(int o)
500: {
501: return get_longi(m68k_getpc() + (o));
502: }
503: STATIC_INLINE uae_u32 next_iiword_jit(void)
504: {
505: uae_u32 r = get_wordi(m68k_getpc());
506: m68k_incpc(2);
507: return r;
508: }
509: STATIC_INLINE uae_u32 next_iilong_jit(void)
510: {
511: uae_u32 r = get_longi(m68k_getpc());
512: m68k_incpc(4);
513: return r;
514: }
515: STATIC_INLINE void m68k_do_bsri_jit(uaecptr oldpc, uae_s32 offset)
516: {
517: m68k_areg(regs, 7) -= 4;
518: x_put_long(m68k_areg(regs, 7), oldpc);
519: m68k_incpc(offset);
520: }
521: STATIC_INLINE void m68k_do_rtsi_jit(void)
522: {
523: uae_u32 newpc = x_get_long(m68k_areg(regs, 7));
524: m68k_setpc(newpc);
525: m68k_areg(regs, 7) += 4;
526: }
527:
528: /* common access */
529:
530: STATIC_INLINE void m68k_incpc_normal(int o)
531: {
532: if (m68k_pc_indirect > 0)
533: m68k_incpci(o);
534: else
535: m68k_incpc(o);
536: }
537:
538: STATIC_INLINE void m68k_setpc_normal(uaecptr pc)
539: {
540: if (m68k_pc_indirect > 0) {
541: regs.pc_p = regs.pc_oldp = 0;
542: m68k_setpci(pc);
543: } else {
544: m68k_setpc(pc);
545: }
546: }
547:
548: extern void write_dcache030(uaecptr, uae_u32, int);
549: extern uae_u32 read_dcache030(uaecptr, int);
550: extern uae_u32 get_word_icache030(uaecptr addr);
551: extern uae_u32 get_long_icache030(uaecptr addr);
552:
553: uae_u32 fill_icache040(uae_u32 addr);
554: extern void put_long_cache_040(uaecptr, uae_u32);
555: extern void put_word_cache_040(uaecptr, uae_u32);
556: extern void put_byte_cache_040(uaecptr, uae_u32);
557: extern uae_u32 get_ilong_cache_040(int);
558: extern uae_u32 get_iword_cache_040(int);
559: extern uae_u32 get_long_cache_040(uaecptr);
560: extern uae_u32 get_word_cache_040(uaecptr);
561: extern uae_u32 get_byte_cache_040(uaecptr);
562: extern uae_u32 next_iword_cache040(void);
563: extern uae_u32 next_ilong_cache040(void);
564: extern uae_u32 get_word_icache040(uaecptr addr);
565: extern uae_u32 get_long_icache040(uaecptr addr);
566:
567: extern void (*x_do_cycles)(unsigned long);
568: extern void (*x_do_cycles_pre)(unsigned long);
569: extern void (*x_do_cycles_post)(unsigned long, uae_u32);
570:
571: extern uae_u32 REGPARAM3 x_get_disp_ea_020 (uae_u32 base, int idx) REGPARAM;
572: extern uae_u32 REGPARAM3 x_get_disp_ea_ce020 (uae_u32 base, int idx) REGPARAM;
573: extern uae_u32 REGPARAM3 x_get_disp_ea_ce030 (uae_u32 base, int idx) REGPARAM;
574: extern uae_u32 REGPARAM3 x_get_disp_ea_040(uae_u32 base, int idx) REGPARAM;
1.1.1.3 root 575: extern uae_u32 REGPARAM3 x_get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
576: extern void REGPARAM3 x_put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;
577:
578: extern void m68k_setstopped (void);
579: extern void m68k_resumestopped (void);
580:
1.1.1.5 root 581: extern uae_u32 REGPARAM3 get_disp_ea_020 (uae_u32 base, int idx) REGPARAM;
1.1.1.3 root 582: extern uae_u32 REGPARAM3 get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
583: extern void REGPARAM3 put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;
584:
1.1.1.5 root 585: extern void m68k_disasm_ea (uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr);
586: extern void m68k_disasm (uaecptr addr, uaecptr *nextpc, int cnt);
587: extern void m68k_disasm_2 (TCHAR *buf, int bufsize, uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr, int safemode);
588: extern void sm68k_disasm (TCHAR*, TCHAR*, uaecptr addr, uaecptr *nextpc);
1.1.1.3 root 589: extern int get_cpu_model (void);
1.1.1.5 root 590: #ifdef WINUAE_FOR_HATARI
591: extern void m68k_disasm_file (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt);
592: #endif
1.1.1.3 root 593:
1.1.1.5 root 594: extern void set_cpu_caches (bool flush);
595: extern void flush_cpu_caches(bool flush);
596: extern void flush_cpu_caches_040(uae_u16 opcode);
1.1.1.3 root 597: extern void REGPARAM3 MakeSR (void) REGPARAM;
598: extern void REGPARAM3 MakeFromSR (void) REGPARAM;
1.1.1.5 root 599: extern void REGPARAM3 Exception (int) REGPARAM;
600: extern void REGPARAM3 ExceptionL (int, uaecptr) REGPARAM;
1.1.1.3 root 601: extern void NMI (void);
602: extern void NMI_delayed (void);
603: extern void prepare_interrupt (uae_u32);
604: extern void doint (void);
605: extern void dump_counts (void);
606: extern int m68k_move2c (int, uae_u32 *);
607: extern int m68k_movec2 (int, uae_u32 *);
1.1.1.5 root 608: extern bool m68k_divl (uae_u32, uae_u32, uae_u16);
609: extern bool m68k_mull (uae_u32, uae_u32, uae_u16);
1.1.1.3 root 610: extern void init_m68k (void);
611: extern void init_m68k_full (void);
612: extern void m68k_go (int);
1.1.1.5 root 613: extern void m68k_dumpstate (uaecptr *);
614: extern void m68k_dumpstate_2 (uaecptr, uaecptr *);
615: extern void m68k_dumpstate_file (FILE *f, uaecptr *);
616: extern void m68k_dumpcache (void);
1.1.1.3 root 617: extern int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor);
618: extern int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor);
1.1.1.5 root 619: extern void divbyzero_special (bool issigned, uae_s32 dst);
1.1.1.3 root 620: extern void m68k_do_rte (void);
1.1.1.5 root 621: extern void protect_roms (bool);
622: extern void unprotect_maprom (void);
623: extern bool is_hardreset(void);
624: extern bool is_keyboardreset(void);
1.1.1.3 root 625:
626: extern void mmu_op (uae_u32, uae_u32);
1.1.1.5 root 627: extern bool mmu_op30 (uaecptr, uae_u32, uae_u16, uaecptr);
1.1.1.3 root 628:
629: extern void fpuop_arithmetic(uae_u32, uae_u16);
630: extern void fpuop_dbcc(uae_u32, uae_u16);
631: extern void fpuop_scc(uae_u32, uae_u16);
632: extern void fpuop_trapcc(uae_u32, uaecptr, uae_u16);
633: extern void fpuop_bcc(uae_u32, uaecptr, uae_u32);
634: extern void fpuop_save(uae_u32);
635: extern void fpuop_restore(uae_u32);
636: extern uae_u32 fpp_get_fpsr (void);
637: extern void fpu_reset (void);
638: extern void fpux_save (int*);
639: extern void fpux_restore (int*);
1.1.1.5 root 640: extern bool fpu_get_constant(fpdata *fp, int cr);
641: extern int fpp_cond(int condition);
1.1.1.3 root 642:
1.1.1.6 ! root 643: extern void exception3_read(uae_u32 opcode, uaecptr addr);
! 644: extern void exception3_write(uae_u32 opcode, uaecptr addr);
1.1.1.5 root 645: extern void exception3_notinstruction(uae_u32 opcode, uaecptr addr);
646: extern void exception3i (uae_u32 opcode, uaecptr addr);
647: extern void exception3b (uae_u32 opcode, uaecptr addr, bool w, bool i, uaecptr pc);
648: extern void exception2 (uaecptr addr, bool read, int size, uae_u32 fc);
649: extern void m68k_reset (void);
1.1.1.3 root 650: extern void cpureset (void);
1.1.1.5 root 651: extern void cpu_halt (int id);
1.1.1.6 ! root 652: extern int cpu_sleep_millis(int ms);
! 653: extern void cpu_change(int newmodel);
! 654: extern void cpu_fallback(int mode);
1.1.1.3 root 655:
1.1.1.5 root 656: extern void fill_prefetch (void);
657: extern void fill_prefetch_020 (void);
658: extern void fill_prefetch_030 (void);
659:
660: #ifdef WINUAE_FOR_HATARI
661: //extern void m68k_reset (bool hardreset); // TODO remove
662: #endif
1.1.1.3 root 663:
664: #define CPU_OP_NAME(a) op ## a
665:
666: /* 68060 */
667: extern const struct cputbl op_smalltbl_0_ff[];
1.1.1.5 root 668: extern const struct cputbl op_smalltbl_40_ff[];
1.1.1.6 ! root 669: extern const struct cputbl op_smalltbl_50_ff[];
1.1.1.5 root 670: extern const struct cputbl op_smalltbl_24_ff[]; // CE
671: extern const struct cputbl op_smalltbl_33_ff[]; // MMU
1.1.1.3 root 672: /* 68040 */
673: extern const struct cputbl op_smalltbl_1_ff[];
1.1.1.5 root 674: extern const struct cputbl op_smalltbl_41_ff[];
1.1.1.6 ! root 675: extern const struct cputbl op_smalltbl_51_ff[];
1.1.1.5 root 676: extern const struct cputbl op_smalltbl_25_ff[]; // CE
1.1.1.3 root 677: extern const struct cputbl op_smalltbl_31_ff[]; // MMU
678: /* 68030 */
679: extern const struct cputbl op_smalltbl_2_ff[];
1.1.1.5 root 680: extern const struct cputbl op_smalltbl_42_ff[];
1.1.1.6 ! root 681: extern const struct cputbl op_smalltbl_52_ff[];
1.1.1.5 root 682: extern const struct cputbl op_smalltbl_22_ff[]; // prefetch
683: extern const struct cputbl op_smalltbl_23_ff[]; // CE
1.1.1.4 root 684: extern const struct cputbl op_smalltbl_32_ff[]; // MMU
1.1.1.3 root 685: /* 68020 */
686: extern const struct cputbl op_smalltbl_3_ff[];
1.1.1.5 root 687: extern const struct cputbl op_smalltbl_43_ff[];
1.1.1.6 ! root 688: extern const struct cputbl op_smalltbl_53_ff[];
1.1.1.5 root 689: extern const struct cputbl op_smalltbl_20_ff[]; // prefetch
690: extern const struct cputbl op_smalltbl_21_ff[]; // CE
1.1.1.3 root 691: /* 68010 */
692: extern const struct cputbl op_smalltbl_4_ff[];
1.1.1.5 root 693: extern const struct cputbl op_smalltbl_44_ff[];
1.1.1.6 ! root 694: extern const struct cputbl op_smalltbl_54_ff[];
1.1.1.5 root 695: extern const struct cputbl op_smalltbl_11_ff[]; // prefetch
696: extern const struct cputbl op_smalltbl_13_ff[]; // CE
1.1.1.3 root 697: /* 68000 */
698: extern const struct cputbl op_smalltbl_5_ff[];
1.1.1.5 root 699: extern const struct cputbl op_smalltbl_45_ff[];
1.1.1.6 ! root 700: extern const struct cputbl op_smalltbl_55_ff[];
1.1.1.5 root 701: extern const struct cputbl op_smalltbl_12_ff[]; // prefetch
702: extern const struct cputbl op_smalltbl_14_ff[]; // CE
1.1.1.3 root 703:
704: extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl");
705:
706: #ifdef JIT
1.1.1.5 root 707: extern void flush_icache(uaecptr, int);
708: extern void flush_icache_hard(uaecptr, int);
709: extern void compemu_reset(void);
1.1.1.3 root 710: #else
711: #define flush_icache(uaecptr, int) do {} while (0)
1.1.1.5 root 712: #define flush_icache_hard(uaecptr, int) do {} while (0)
1.1.1.3 root 713: #endif
1.1.1.6 ! root 714: bool check_prefs_changed_comp (bool);
1.1.1.3 root 715: extern void flush_dcache (uaecptr, int);
1.1.1.5 root 716: #ifdef WINUAE_FOR_HATARI
717: extern void flush_instr_cache (uaecptr, int);
718: #endif
1.1.1.3 root 719: extern void flush_mmu (uaecptr, int);
720:
721: extern int movec_illg (int regno);
722: extern uae_u32 val_move2c (int regno);
723: extern void val_move2c2 (int regno, uae_u32 val);
724: struct cpum2c {
725: int regno;
726: const TCHAR *regname;
727: };
728: extern struct cpum2c m2cregs[];
729:
1.1.1.5 root 730: extern bool is_cpu_tracer (void);
731: extern bool set_cpu_tracer (bool force);
732: extern bool can_cpu_tracer (void);
733:
1.1.1.6 ! root 734: #define CPU_HALT_PPC_ONLY -1
! 735: #define CPU_HALT_BUS_ERROR_DOUBLE_FAULT 1
! 736: #define CPU_HALT_DOUBLE_FAULT 2
! 737: #define CPU_HALT_OPCODE_FETCH_FROM_NON_EXISTING_ADDRESS 3
! 738: #define CPU_HALT_ACCELERATOR_CPU_FALLBACK 4
! 739: #define CPU_HALT_ALL_CPUS_STOPPED 5
! 740: #define CPU_HALT_FAKE_DMA 6
! 741: #define CPU_HALT_AUTOCONFIG_CONFLICT 7
! 742: #define CPU_HALT_PCI_CONFLICT 8
! 743: #define CPU_HALT_CPU_STUCK 9
! 744: #define CPU_HALT_SSP_IN_NON_EXISTING_ADDRESS 10
! 745:
! 746: void cpu_semaphore_get(void);
! 747: void cpu_semaphore_release(void);
! 748: bool execute_other_cpu(int until);
! 749: void execute_other_cpu_single(void);
! 750:
1.1.1.5 root 751: #ifdef WINUAE_FOR_HATARI
752: /*** Hatari ***/
753:
1.1.1.3 root 754: /* Family of the latest instruction executed (to check for pairing) */
755: extern int OpcodeFamily; /* see instrmnem in readcpu.h */
756:
1.1.1.6 ! root 757: /* How many cycles to add to the current instruction in case a "misaligned" bus access is made */
1.1.1.5 root 758: /* (e.g. used when addressing mode is d8(an,ix)) */
1.1.1.3 root 759: extern int BusCyclePenalty;
760:
1.1.1.5 root 761: /* To redirect WinUAE's prints to our own file */
762: extern FILE *console_out_FILE;
763:
764: /*** Hatari ***/
765: #endif
766:
1.1.1.6 ! root 767: #endif /* UAE_NEWCPU_H */
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