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1.1.1.3 root 1: /*
2: * UAE - The Un*x Amiga Emulator
3: *
4: * MC68000 emulation
5: *
6: * Copyright 1995 Bernd Schmidt
7: */
8:
1.1.1.6 root 9: #ifndef UAE_NEWCPU_H
10: #define UAE_NEWCPU_H
1.1.1.3 root 11:
1.1.1.6 root 12: #include "uae/types.h"
1.1.1.3 root 13: #include "readcpu.h"
1.1.1.6 root 14: #include "machdep/m68k.h"
1.1.1.3 root 15: #include "compat.h"
16: #include "maccess.h"
17: #include "events.h"
18: #include "memory.h"
19: #include "custom.h"
20:
21: /* Possible exceptions sources for M68000_Exception() and Exception() */
1.1.1.5 root 22: // TODO : remove when not used anymore in m68000.c
23: #define M68000_EXC_SRC_CPU 1 /* Direct CPU exception */
24: #define M68000_EXC_SRC_AUTOVEC 2 /* Auto-vector exception (e.g. VBL) */
25: #define M68000_EXC_SRC_INT_MFP 3 /* MFP interrupt exception */
26: #define M68000_EXC_SRC_INT_DSP 4 /* DSP interrupt exception */
1.1.1.3 root 27:
28:
1.1.1.7 ! root 29: /* Special flags (from custom.h) */
1.1.1.3 root 30: #define SPCFLAG_DEBUGGER 1
31: #define SPCFLAG_STOP 2
32: #define SPCFLAG_BUSERROR 4
33: #define SPCFLAG_INT 8
34: #define SPCFLAG_BRK 0x10
35: #define SPCFLAG_EXTRA_CYCLES 0x20
36: #define SPCFLAG_TRACE 0x40
37: #define SPCFLAG_DOTRACE 0x80
38: #define SPCFLAG_DOINT 0x100
39: #define SPCFLAG_MFP 0x200
40: #define SPCFLAG_EXEC 0x400
41: #define SPCFLAG_MODE_CHANGE 0x800
1.1.1.4 root 42: #define SPCFLAG_DSP 0x1000
1.1.1.3 root 43:
1.1.1.7 ! root 44: #include <softfloat/softfloat.h>
1.1.1.5 root 45:
1.1.1.3 root 46: #ifndef SET_CFLG
47:
48: #define SET_CFLG(x) (CFLG() = (x))
49: #define SET_NFLG(x) (NFLG() = (x))
50: #define SET_VFLG(x) (VFLG() = (x))
51: #define SET_ZFLG(x) (ZFLG() = (x))
52: #define SET_XFLG(x) (XFLG() = (x))
53:
54: #define GET_CFLG() CFLG()
55: #define GET_NFLG() NFLG()
56: #define GET_VFLG() VFLG()
57: #define GET_ZFLG() ZFLG()
58: #define GET_XFLG() XFLG()
59:
60: #define CLEAR_CZNV() do { \
61: SET_CFLG (0); \
62: SET_ZFLG (0); \
63: SET_NFLG (0); \
64: SET_VFLG (0); \
65: } while (0)
66:
67: #define COPY_CARRY() (SET_XFLG (GET_CFLG ()))
68: #endif
69:
70: extern const int areg_byteinc[];
71: extern const int imm8_table[];
72:
73: extern int movem_index1[256];
74: extern int movem_index2[256];
75: extern int movem_next[256];
76:
77: #ifdef FPUEMU
78: extern int fpp_movem_index1[256];
79: extern int fpp_movem_index2[256];
80: extern int fpp_movem_next[256];
81: #endif
82:
1.1.1.5 root 83: extern int bus_error_offset;
1.1.1.3 root 84:
1.1.1.5 root 85: typedef uae_u32 REGPARAM3 cpuop_func (uae_u32) REGPARAM;
1.1.1.3 root 86: typedef void REGPARAM3 cpuop_func_ce (uae_u32) REGPARAM;
87:
88: struct cputbl {
89: cpuop_func *handler;
90: uae_u16 opcode;
1.1.1.5 root 91: uae_s8 length;
92: uae_s8 disp020[2];
93: uae_u8 branch;
1.1.1.3 root 94: };
95:
96: #ifdef JIT
1.1.1.6 root 97: #define MAX_JIT_CACHE 16384
1.1.1.5 root 98: typedef uae_u32 REGPARAM3 compop_func (uae_u32) REGPARAM;
1.1.1.3 root 99:
1.1.1.6 root 100: #define COMP_OPCODE_ISJUMP 0x0001
101: #define COMP_OPCODE_LONG_OPCODE 0x0002
102: #define COMP_OPCODE_CMOV 0x0004
103: #define COMP_OPCODE_ISADDX 0x0008
104: #define COMP_OPCODE_ISCJUMP 0x0010
105: #define COMP_OPCODE_USES_FPU 0x0020
106:
1.1.1.3 root 107: struct comptbl {
108: compop_func *handler;
109: uae_u32 opcode;
110: int specific;
111: };
112: #endif
113:
1.1.1.5 root 114: extern uae_u32 REGPARAM3 op_illg (uae_u32) REGPARAM;
115: extern void REGPARAM3 op_unimpl (uae_u16) REGPARAM;
1.1.1.3 root 116:
117: typedef uae_u8 flagtype;
118:
119: #ifdef FPUEMU
120:
1.1.1.5 root 121: #ifdef USE_LONG_DOUBLE
1.1.1.3 root 122: typedef long double fptype;
123: #define LDPTR tbyte ptr
124: #else
125: typedef double fptype;
126: #define LDPTR qword ptr
127: #endif
128: #endif
129:
1.1.1.5 root 130: #define MAX68020CYCLES 4
131:
132: #define CPU_PIPELINE_MAX 4
1.1.1.3 root 133: #define CPU000_MEM_CYCLE 4
134: #define CPU000_CLOCK_MULT 2
135: #define CPU020_MEM_CYCLE 3
136: #define CPU020_CLOCK_MULT 4
137:
138: #define CACHELINES020 64
139: struct cache020
140: {
141: uae_u32 data;
142: uae_u32 tag;
143: bool valid;
144: };
145:
146: #define CACHELINES030 16
147: struct cache030
148: {
149: uae_u32 data[4];
150: bool valid[4];
151: uae_u32 tag;
1.1.1.7 ! root 152: uae_u8 fc;
1.1.1.3 root 153: };
154:
155: #define CACHESETS040 64
1.1.1.7 ! root 156: #define CACHESETS060 128
1.1.1.3 root 157: #define CACHELINES040 4
158: struct cache040
159: {
160: uae_u32 data[CACHELINES040][4];
1.1.1.5 root 161: bool dirty[CACHELINES040][4];
1.1.1.7 ! root 162: bool gdirty[CACHELINES040];
1.1.1.3 root 163: bool valid[CACHELINES040];
164: uae_u32 tag[CACHELINES040];
165: };
166:
1.1.1.4 root 167: struct mmufixup
168: {
169: int reg;
170: uae_u32 value;
171: };
172: extern struct mmufixup mmufixup[2];
1.1.1.3 root 173:
1.1.1.5 root 174: typedef struct
175: {
176: floatx80 fpx;
1.1.1.7 ! root 177: fptype fp;
1.1.1.5 root 178: } fpdata;
179:
1.1.1.3 root 180: struct regstruct
181: {
182: uae_u32 regs[16];
183:
184: uae_u32 pc;
185: uae_u8 *pc_p;
186: uae_u8 *pc_oldp;
1.1.1.5 root 187: uae_u16 opcode;
188: uae_u32 instruction_pc;
1.1.1.3 root 189:
1.1.1.5 root 190: uae_u16 irc, ir, db;
1.1.1.6 root 191: volatile uae_atomic spcflags;
1.1.1.5 root 192: uae_u32 last_prefetch;
193: uae_u32 chipset_latch_rw;
194: uae_u32 chipset_latch_read;
195: uae_u32 chipset_latch_write;
1.1.1.3 root 196:
197: uaecptr usp, isp, msp;
198: uae_u16 sr;
199: flagtype t1;
200: flagtype t0;
201: flagtype s;
202: flagtype m;
203: flagtype x;
204: flagtype stopped;
1.1.1.5 root 205: int halted;
206: int exception;
1.1.1.3 root 207: int intmask;
208: int ipl, ipl_pin;
209:
210: uae_u32 vbr, sfc, dfc;
211:
212: #ifdef FPUEMU
1.1.1.5 root 213: fpdata fp[8];
1.1.1.7 ! root 214: #ifdef JIT
1.1.1.5 root 215: fpdata fp_result;
1.1.1.7 ! root 216: #endif
1.1.1.3 root 217: uae_u32 fpcr, fpsr, fpiar;
1.1.1.5 root 218: uae_u32 fpu_state;
219: uae_u32 fpu_exp_state;
1.1.1.7 ! root 220: uae_u16 fp_opword;
! 221: uaecptr fp_ea;
! 222: uae_u32 fp_exp_pend, fp_unimp_pend;
! 223: bool fpu_exp_pre;
! 224: bool fp_unimp_ins;
1.1.1.5 root 225: bool fp_exception;
226: bool fp_branch;
1.1.1.3 root 227: #endif
228: #ifndef CPUEMU_68000_ONLY
229: uae_u32 cacr, caar;
230: uae_u32 itt0, itt1, dtt0, dtt1;
231: uae_u32 tcr, mmusr, urp, srp, buscr;
1.1.1.5 root 232: uae_u32 mmu_fslw;
233: uae_u32 mmu_fault_addr, mmu_effective_addr;
1.1.1.3 root 234: uae_u16 mmu_ssw;
1.1.1.5 root 235: uae_u32 wb2_address;
1.1.1.3 root 236: uae_u32 wb3_data;
1.1.1.5 root 237: uae_u8 wb3_status, wb2_status;
1.1.1.3 root 238: int mmu_enabled;
1.1.1.5 root 239: int mmu_page_size;
1.1.1.3 root 240: #endif
241:
242: uae_u32 pcr;
243: uae_u32 address_space_mask;
244:
1.1.1.7 ! root 245: uae_u16 prefetch020[CPU_PIPELINE_MAX];
! 246: uae_u8 prefetch020_valid[CPU_PIPELINE_MAX];
1.1.1.5 root 247: uae_u32 prefetch020addr;
248: uae_u32 cacheholdingdata020;
249: uae_u32 cacheholdingaddr020;
1.1.1.7 ! root 250: uae_u8 cacheholdingdata_valid;
1.1.1.5 root 251: int pipeline_pos;
252: int pipeline_r8[2];
253: int pipeline_stop;
1.1.1.7 ! root 254: uae_u8 fc030;
! 255:
! 256: uae_u32 prefetch040[CPU_PIPELINE_MAX];
! 257:
! 258: int ce020endcycle;
! 259: int ce020startcycle;
! 260: int ce020prefetchendcycle;
! 261:
1.1.1.5 root 262: int ce020extracycles;
263: bool ce020memcycle_data;
264: int ce020_tail;
265: frame_time_t ce020_tail_cycles;
266: int memory_waitstate_cycles;
1.1.1.3 root 267: };
268:
269: extern struct regstruct regs;
270:
1.1.1.5 root 271: #define MAX_CPUTRACESIZE 128
272: struct cputracememory
273: {
274: uae_u32 addr;
275: uae_u32 data;
276: int mode;
277: };
278:
279: struct cputracestruct
280: {
281: uae_u32 regs[16];
282: uae_u32 usp, isp, pc;
283: uae_u16 ir, irc, sr, opcode;
284: int intmask, stopped, state;
285:
286: uae_u32 msp, vbr;
287: uae_u32 cacr, caar;
1.1.1.7 ! root 288: uae_u16 prefetch020[CPU_PIPELINE_MAX];
! 289: uae_u8 prefetch020_valid[CPU_PIPELINE_MAX];
1.1.1.5 root 290: uae_u32 prefetch020addr;
291: uae_u32 cacheholdingdata020;
292: uae_u32 cacheholdingaddr020;
293: struct cache020 caches020[CACHELINES020];
1.1.1.7 ! root 294: int pipeline_pos;
! 295: int pipeline_r8[2];
! 296: int pipeline_stop;
1.1.1.5 root 297:
298: uae_u32 startcycles;
299: int needendcycles;
300: int memoryoffset;
301: int cyclecounter, cyclecounter_pre, cyclecounter_post;
302: int readcounter, writecounter;
303: struct cputracememory ctm[MAX_CPUTRACESIZE];
304: };
305:
1.1.1.3 root 306: STATIC_INLINE uae_u32 munge24 (uae_u32 x)
307: {
308: return x & regs.address_space_mask;
309: }
310:
311: extern int mmu_enabled, mmu_triggered;
312: extern int cpu_cycles;
313: extern int cpucycleunit;
1.1.1.5 root 314: extern int m68k_pc_indirect;
1.1.1.6 root 315:
316: #ifndef WINUAE_FOR_HATARI
317: STATIC_INLINE void set_special_exter(uae_u32 x)
318: {
319: atomic_or(®s.spcflags, x);
320: }
321: STATIC_INLINE void set_special (uae_u32 x)
322: {
323: atomic_or(®s.spcflags, x);
324: cycles_do_special ();
325: }
326:
327: STATIC_INLINE void unset_special (uae_u32 x)
328: {
329: atomic_and(®s.spcflags, ~x);
330: }
331: #else
1.1.1.3 root 332: STATIC_INLINE void set_special (uae_u32 x)
333: {
334: regs.spcflags |= x;
335: cycles_do_special ();
336: }
337:
338: STATIC_INLINE void unset_special (uae_u32 x)
339: {
340: regs.spcflags &= ~x;
341: }
342:
1.1.1.6 root 343: #endif
344:
1.1.1.3 root 345: #define m68k_dreg(r,num) ((r).regs[(num)])
346: #define m68k_areg(r,num) (((r).regs + 8)[(num)])
347:
1.1.1.5 root 348: extern uae_u32(*x_prefetch)(int);
349: extern uae_u32(*x_get_byte)(uaecptr addr);
350: extern uae_u32(*x_get_word)(uaecptr addr);
351: extern uae_u32(*x_get_long)(uaecptr addr);
352: extern void(*x_put_byte)(uaecptr addr, uae_u32 v);
353: extern void(*x_put_word)(uaecptr addr, uae_u32 v);
354: extern void(*x_put_long)(uaecptr addr, uae_u32 v);
355: extern uae_u32(*x_next_iword)(void);
356: extern uae_u32(*x_next_ilong)(void);
357: extern uae_u32(*x_get_ilong)(int);
358: extern uae_u32(*x_get_iword)(int);
359: extern uae_u32(*x_get_ibyte)(int);
360:
361: extern uae_u32(*x_cp_get_byte)(uaecptr addr);
362: extern uae_u32(*x_cp_get_word)(uaecptr addr);
363: extern uae_u32(*x_cp_get_long)(uaecptr addr);
364: extern void(*x_cp_put_byte)(uaecptr addr, uae_u32 v);
365: extern void(*x_cp_put_word)(uaecptr addr, uae_u32 v);
366: extern void(*x_cp_put_long)(uaecptr addr, uae_u32 v);
367: extern uae_u32(*x_cp_next_iword)(void);
368: extern uae_u32(*x_cp_next_ilong)(void);
369:
1.1.1.7 ! root 370: void mem_access_delay_long_write_ce020 (uaecptr addr, uae_u32 v);
! 371: void mem_access_delay_word_write_ce020 (uaecptr addr, uae_u32 v);
! 372: void mem_access_delay_byte_write_ce020 (uaecptr addr, uae_u32 v);
! 373: uae_u32 mem_access_delay_byte_read_ce020 (uaecptr addr);
! 374: uae_u32 mem_access_delay_word_read_ce020 (uaecptr addr);
! 375: uae_u32 mem_access_delay_long_read_ce020 (uaecptr addr);
! 376: uae_u32 mem_access_delay_longi_read_ce020 (uaecptr addr);
! 377: uae_u32 mem_access_delay_wordi_read_ce020 (uaecptr addr);
! 378:
! 379: void mem_access_delay_long_write_c040 (uaecptr addr, uae_u32 v);
! 380: void mem_access_delay_word_write_c040 (uaecptr addr, uae_u32 v);
! 381: void mem_access_delay_byte_write_c040 (uaecptr addr, uae_u32 v);
! 382: uae_u32 mem_access_delay_byte_read_c040 (uaecptr addr);
! 383: uae_u32 mem_access_delay_word_read_c040 (uaecptr addr);
! 384: uae_u32 mem_access_delay_long_read_c040 (uaecptr addr);
! 385: uae_u32 mem_access_delay_longi_read_c040 (uaecptr addr);
! 386:
1.1.1.5 root 387: extern uae_u32(REGPARAM3 *x_cp_get_disp_ea_020)(uae_u32 base, int idx) REGPARAM;
388:
389: /* direct (regs.pc_p) access */
390:
391: STATIC_INLINE void m68k_setpc(uaecptr newpc)
1.1.1.3 root 392: {
1.1.1.5 root 393: regs.pc_p = regs.pc_oldp = get_real_address(newpc);
394: regs.instruction_pc = regs.pc = newpc;
1.1.1.3 root 395: }
1.1.1.5 root 396: STATIC_INLINE uaecptr m68k_getpc(void)
1.1.1.3 root 397: {
398: return (uaecptr)(regs.pc + ((uae_u8*)regs.pc_p - (uae_u8*)regs.pc_oldp));
399: }
400: #define M68K_GETPC m68k_getpc()
1.1.1.5 root 401: STATIC_INLINE uaecptr m68k_getpc_p(uae_u8 *p)
1.1.1.3 root 402: {
403: return (uaecptr)(regs.pc + ((uae_u8*)p - (uae_u8*)regs.pc_oldp));
404: }
1.1.1.5 root 405: STATIC_INLINE void m68k_incpc(int o)
1.1.1.3 root 406: {
407: regs.pc_p += o;
408: }
409:
1.1.1.5 root 410: STATIC_INLINE uae_u32 get_dibyte(int o)
1.1.1.3 root 411: {
1.1.1.5 root 412: return do_get_mem_byte((uae_u8 *)((regs).pc_p + (o) + 1));
1.1.1.3 root 413: }
1.1.1.5 root 414: STATIC_INLINE uae_u32 get_diword(int o)
1.1.1.3 root 415: {
1.1.1.5 root 416: return do_get_mem_word((uae_u16 *)((regs).pc_p + (o)));
1.1.1.3 root 417: }
1.1.1.5 root 418: STATIC_INLINE uae_u32 get_dilong(int o)
1.1.1.3 root 419: {
1.1.1.5 root 420: return do_get_mem_long((uae_u32 *)((regs).pc_p + (o)));
1.1.1.3 root 421: }
1.1.1.5 root 422: STATIC_INLINE uae_u32 next_diword(void)
1.1.1.3 root 423: {
1.1.1.5 root 424: uae_u32 r = do_get_mem_word((uae_u16 *)((regs).pc_p));
425: m68k_incpc(2);
426: return r;
427: }
428: STATIC_INLINE uae_u32 next_dilong(void)
429: {
430: uae_u32 r = do_get_mem_long((uae_u32 *)((regs).pc_p));
431: m68k_incpc(4);
432: return r;
1.1.1.3 root 433: }
434:
1.1.1.5 root 435: STATIC_INLINE void m68k_do_bsr(uaecptr oldpc, uae_s32 offset)
1.1.1.3 root 436: {
1.1.1.5 root 437: m68k_areg(regs, 7) -= 4;
438: put_long(m68k_areg(regs, 7), oldpc);
439: m68k_incpc(offset);
1.1.1.3 root 440: }
1.1.1.5 root 441: STATIC_INLINE void m68k_do_rts(void)
1.1.1.3 root 442: {
1.1.1.5 root 443: uae_u32 newpc = get_long(m68k_areg(regs, 7));
444: m68k_setpc(newpc);
445: m68k_areg(regs, 7) += 4;
1.1.1.3 root 446: }
447:
1.1.1.5 root 448: /* indirect (regs.pc) access */
449:
450: STATIC_INLINE void m68k_setpci(uaecptr newpc)
1.1.1.3 root 451: {
1.1.1.5 root 452: regs.instruction_pc = regs.pc = newpc;
1.1.1.3 root 453: }
1.1.1.5 root 454: STATIC_INLINE uaecptr m68k_getpci(void)
1.1.1.3 root 455: {
1.1.1.5 root 456: return regs.pc;
457: }
458: STATIC_INLINE void m68k_incpci(int o)
459: {
460: regs.pc += o;
1.1.1.3 root 461: }
462:
1.1.1.5 root 463: STATIC_INLINE uae_u32 get_iibyte(int o)
1.1.1.3 root 464: {
1.1.1.5 root 465: return get_wordi(m68k_getpci() + (o)) & 0xff;
1.1.1.3 root 466: }
1.1.1.5 root 467: STATIC_INLINE uae_u32 get_iiword(int o)
1.1.1.3 root 468: {
1.1.1.5 root 469: return get_wordi(m68k_getpci() + (o));
1.1.1.3 root 470: }
1.1.1.5 root 471: STATIC_INLINE uae_u32 get_iilong(int o)
1.1.1.3 root 472: {
1.1.1.5 root 473: return get_longi(m68k_getpci () + (o));
1.1.1.3 root 474: }
475:
1.1.1.5 root 476: STATIC_INLINE uae_u32 next_iibyte (void)
1.1.1.3 root 477: {
1.1.1.5 root 478: uae_u32 r = get_iibyte (0);
479: m68k_incpci (2);
1.1.1.3 root 480: return r;
481: }
1.1.1.5 root 482: STATIC_INLINE uae_u32 next_iiword (void)
1.1.1.3 root 483: {
1.1.1.5 root 484: uae_u32 r = get_iiword (0);
485: m68k_incpci (2);
1.1.1.3 root 486: return r;
487: }
1.1.1.5 root 488: STATIC_INLINE uae_u32 next_iiwordi (void)
1.1.1.3 root 489: {
1.1.1.5 root 490: uae_u32 r = get_wordi(m68k_getpci());
491: m68k_incpci (2);
1.1.1.3 root 492: return r;
493: }
1.1.1.5 root 494: STATIC_INLINE uae_u32 next_iilong (void)
1.1.1.3 root 495: {
1.1.1.5 root 496: uae_u32 r = get_iilong(0);
497: m68k_incpci (4);
1.1.1.3 root 498: return r;
499: }
1.1.1.5 root 500: STATIC_INLINE uae_u32 next_iilongi (void)
1.1.1.3 root 501: {
1.1.1.5 root 502: uae_u32 r = get_longi (m68k_getpci ());
503: m68k_incpci (4);
1.1.1.3 root 504: return r;
505: }
506:
1.1.1.5 root 507: STATIC_INLINE void m68k_do_bsri(uaecptr oldpc, uae_s32 offset)
508: {
509: m68k_areg(regs, 7) -= 4;
1.1.1.7 ! root 510: x_put_long(m68k_areg(regs, 7), oldpc);
1.1.1.5 root 511: m68k_incpci(offset);
512: }
513: STATIC_INLINE void m68k_do_rtsi(void)
514: {
1.1.1.7 ! root 515: uae_u32 newpc = x_get_long(m68k_areg(regs, 7));
1.1.1.5 root 516: m68k_setpci(newpc);
517: m68k_areg(regs, 7) += 4;
518: }
519:
520: /* indirect jit friendly versions */
1.1.1.3 root 521:
1.1.1.5 root 522: STATIC_INLINE uae_u32 get_iibyte_jit(int o)
523: {
524: return get_wordi(m68k_getpc() + (o)) & 0xff;
525: }
526: STATIC_INLINE uae_u32 get_iiword_jit(int o)
527: {
528: return get_wordi(m68k_getpc() + (o));
529: }
530: STATIC_INLINE uae_u32 get_iilong_jit(int o)
531: {
532: return get_longi(m68k_getpc() + (o));
533: }
534: STATIC_INLINE uae_u32 next_iiword_jit(void)
535: {
536: uae_u32 r = get_wordi(m68k_getpc());
537: m68k_incpc(2);
538: return r;
539: }
540: STATIC_INLINE uae_u32 next_iilong_jit(void)
541: {
542: uae_u32 r = get_longi(m68k_getpc());
543: m68k_incpc(4);
544: return r;
545: }
546: STATIC_INLINE void m68k_do_bsri_jit(uaecptr oldpc, uae_s32 offset)
547: {
548: m68k_areg(regs, 7) -= 4;
549: x_put_long(m68k_areg(regs, 7), oldpc);
550: m68k_incpc(offset);
551: }
552: STATIC_INLINE void m68k_do_rtsi_jit(void)
553: {
554: uae_u32 newpc = x_get_long(m68k_areg(regs, 7));
555: m68k_setpc(newpc);
556: m68k_areg(regs, 7) += 4;
557: }
558:
559: /* common access */
560:
561: STATIC_INLINE void m68k_incpc_normal(int o)
562: {
563: if (m68k_pc_indirect > 0)
564: m68k_incpci(o);
565: else
566: m68k_incpc(o);
567: }
568:
569: STATIC_INLINE void m68k_setpc_normal(uaecptr pc)
570: {
571: if (m68k_pc_indirect > 0) {
572: regs.pc_p = regs.pc_oldp = 0;
573: m68k_setpci(pc);
574: } else {
575: m68k_setpc(pc);
576: }
577: }
578:
1.1.1.7 ! root 579: extern uae_u32(*read_data_030_bget)(uaecptr);
! 580: extern uae_u32(*read_data_030_wget)(uaecptr);
! 581: extern uae_u32(*read_data_030_lget)(uaecptr);
! 582: extern void(*write_data_030_bput)(uaecptr,uae_u32);
! 583: extern void(*write_data_030_wput)(uaecptr,uae_u32);
! 584: extern void(*write_data_030_lput)(uaecptr,uae_u32);
! 585:
! 586: extern uae_u32(*read_data_030_fc_bget)(uaecptr, uae_u32);
! 587: extern uae_u32(*read_data_030_fc_wget)(uaecptr, uae_u32);
! 588: extern uae_u32(*read_data_030_fc_lget)(uaecptr, uae_u32);
! 589: extern void(*write_data_030_fc_bput)(uaecptr, uae_u32, uae_u32);
! 590: extern void(*write_data_030_fc_wput)(uaecptr, uae_u32, uae_u32);
! 591: extern void(*write_data_030_fc_lput)(uaecptr, uae_u32, uae_u32);
! 592:
! 593: extern void write_dcache030_bput(uaecptr, uae_u32, uae_u32);
! 594: extern void write_dcache030_wput(uaecptr, uae_u32, uae_u32);
! 595: extern void write_dcache030_lput(uaecptr, uae_u32, uae_u32);
! 596: extern uae_u32 read_dcache030_bget(uaecptr, uae_u32);
! 597: extern uae_u32 read_dcache030_wget(uaecptr, uae_u32);
! 598: extern uae_u32 read_dcache030_lget(uaecptr, uae_u32);
! 599:
! 600: extern void write_dcache030_mmu_bput(uaecptr, uae_u32);
! 601: extern void write_dcache030_mmu_wput(uaecptr, uae_u32);
! 602: extern void write_dcache030_mmu_lput(uaecptr, uae_u32);
! 603: extern uae_u32 read_dcache030_mmu_bget(uaecptr);
! 604: extern uae_u32 read_dcache030_mmu_wget(uaecptr);
! 605: extern uae_u32 read_dcache030_mmu_lget(uaecptr);
! 606: extern void write_dcache030_lrmw_mmu(uaecptr, uae_u32, uae_u32);
! 607: extern uae_u32 read_dcache030_lrmw_mmu(uaecptr, uae_u32);
! 608:
! 609: extern void check_t0_trace(void);
1.1.1.5 root 610: extern uae_u32 get_word_icache030(uaecptr addr);
611: extern uae_u32 get_long_icache030(uaecptr addr);
612:
613: uae_u32 fill_icache040(uae_u32 addr);
614: extern void put_long_cache_040(uaecptr, uae_u32);
615: extern void put_word_cache_040(uaecptr, uae_u32);
616: extern void put_byte_cache_040(uaecptr, uae_u32);
617: extern uae_u32 get_ilong_cache_040(int);
618: extern uae_u32 get_iword_cache_040(int);
619: extern uae_u32 get_long_cache_040(uaecptr);
620: extern uae_u32 get_word_cache_040(uaecptr);
621: extern uae_u32 get_byte_cache_040(uaecptr);
622: extern uae_u32 next_iword_cache040(void);
623: extern uae_u32 next_ilong_cache040(void);
624: extern uae_u32 get_word_icache040(uaecptr addr);
625: extern uae_u32 get_long_icache040(uaecptr addr);
626:
627: extern void (*x_do_cycles)(unsigned long);
628: extern void (*x_do_cycles_pre)(unsigned long);
629: extern void (*x_do_cycles_post)(unsigned long, uae_u32);
1.1.1.7 ! root 630: #ifdef WINUAE_FOR_HATARI
! 631: void set_x_funcs_hatari_blitter (int flag);
! 632: #endif
1.1.1.5 root 633:
634: extern uae_u32 REGPARAM3 x_get_disp_ea_020 (uae_u32 base, int idx) REGPARAM;
635: extern uae_u32 REGPARAM3 x_get_disp_ea_ce020 (uae_u32 base, int idx) REGPARAM;
636: extern uae_u32 REGPARAM3 x_get_disp_ea_ce030 (uae_u32 base, int idx) REGPARAM;
637: extern uae_u32 REGPARAM3 x_get_disp_ea_040(uae_u32 base, int idx) REGPARAM;
1.1.1.3 root 638: extern uae_u32 REGPARAM3 x_get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
639: extern void REGPARAM3 x_put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;
640:
641: extern void m68k_setstopped (void);
642: extern void m68k_resumestopped (void);
1.1.1.7 ! root 643: extern void m68k_cancel_idle(void);
1.1.1.3 root 644:
1.1.1.5 root 645: extern uae_u32 REGPARAM3 get_disp_ea_020 (uae_u32 base, int idx) REGPARAM;
1.1.1.3 root 646: extern uae_u32 REGPARAM3 get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
647: extern void REGPARAM3 put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;
648:
1.1.1.5 root 649: extern void m68k_disasm_ea (uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr);
650: extern void m68k_disasm (uaecptr addr, uaecptr *nextpc, int cnt);
651: extern void m68k_disasm_2 (TCHAR *buf, int bufsize, uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr, int safemode);
652: extern void sm68k_disasm (TCHAR*, TCHAR*, uaecptr addr, uaecptr *nextpc);
1.1.1.7 ! root 653: extern int m68k_asm(TCHAR *buf, uae_u16 *out, uaecptr pc);
1.1.1.3 root 654: extern int get_cpu_model (void);
1.1.1.5 root 655: #ifdef WINUAE_FOR_HATARI
656: extern void m68k_disasm_file (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt);
657: #endif
1.1.1.3 root 658:
1.1.1.5 root 659: extern void set_cpu_caches (bool flush);
1.1.1.7 ! root 660: #ifdef WINUAE_FOR_HATARI
! 661: extern void invalidate_cpu_data_caches(void);
! 662: #endif
1.1.1.5 root 663: extern void flush_cpu_caches(bool flush);
664: extern void flush_cpu_caches_040(uae_u16 opcode);
1.1.1.3 root 665: extern void REGPARAM3 MakeSR (void) REGPARAM;
1.1.1.7 ! root 666: extern void REGPARAM3 MakeFromSR(void) REGPARAM;
! 667: extern void REGPARAM3 MakeFromSR_T0(void) REGPARAM;
1.1.1.5 root 668: extern void REGPARAM3 Exception (int) REGPARAM;
1.1.1.7 ! root 669: extern void REGPARAM3 Exception_cpu(int) REGPARAM;
1.1.1.5 root 670: extern void REGPARAM3 ExceptionL (int, uaecptr) REGPARAM;
1.1.1.3 root 671: extern void NMI (void);
672: extern void NMI_delayed (void);
673: extern void prepare_interrupt (uae_u32);
674: extern void doint (void);
675: extern void dump_counts (void);
676: extern int m68k_move2c (int, uae_u32 *);
677: extern int m68k_movec2 (int, uae_u32 *);
1.1.1.5 root 678: extern bool m68k_divl (uae_u32, uae_u32, uae_u16);
679: extern bool m68k_mull (uae_u32, uae_u32, uae_u16);
1.1.1.3 root 680: extern void init_m68k (void);
681: extern void m68k_go (int);
1.1.1.5 root 682: extern void m68k_dumpstate (uaecptr *);
683: extern void m68k_dumpstate_2 (uaecptr, uaecptr *);
684: extern void m68k_dumpstate_file (FILE *f, uaecptr *);
1.1.1.7 ! root 685: extern void m68k_dumpcache (bool);
1.1.1.3 root 686: extern int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor);
687: extern int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor);
1.1.1.7 ! root 688: extern void divbyzero_special(bool issigned, uae_s32 dst);
! 689: extern void setdivuoverflowflags(uae_u32 dividend, uae_u16 divisor);
! 690: extern void setdivsoverflowflags(uae_s32 dividend, uae_s16 divisor);
1.1.1.5 root 691: extern void protect_roms (bool);
692: extern void unprotect_maprom (void);
693: extern bool is_hardreset(void);
694: extern bool is_keyboardreset(void);
1.1.1.3 root 695:
696: extern void mmu_op (uae_u32, uae_u32);
1.1.1.5 root 697: extern bool mmu_op30 (uaecptr, uae_u32, uae_u16, uaecptr);
1.1.1.3 root 698:
699: extern void fpuop_arithmetic(uae_u32, uae_u16);
700: extern void fpuop_dbcc(uae_u32, uae_u16);
701: extern void fpuop_scc(uae_u32, uae_u16);
702: extern void fpuop_trapcc(uae_u32, uaecptr, uae_u16);
703: extern void fpuop_bcc(uae_u32, uaecptr, uae_u32);
704: extern void fpuop_save(uae_u32);
705: extern void fpuop_restore(uae_u32);
706: extern uae_u32 fpp_get_fpsr (void);
707: extern void fpu_reset (void);
708: extern void fpux_save (int*);
709: extern void fpux_restore (int*);
1.1.1.5 root 710: extern bool fpu_get_constant(fpdata *fp, int cr);
711: extern int fpp_cond(int condition);
1.1.1.3 root 712:
1.1.1.6 root 713: extern void exception3_read(uae_u32 opcode, uaecptr addr);
714: extern void exception3_write(uae_u32 opcode, uaecptr addr);
1.1.1.5 root 715: extern void exception3_notinstruction(uae_u32 opcode, uaecptr addr);
716: extern void exception3i (uae_u32 opcode, uaecptr addr);
717: extern void exception3b (uae_u32 opcode, uaecptr addr, bool w, bool i, uaecptr pc);
718: extern void exception2 (uaecptr addr, bool read, int size, uae_u32 fc);
719: extern void m68k_reset (void);
1.1.1.3 root 720: extern void cpureset (void);
1.1.1.5 root 721: extern void cpu_halt (int id);
1.1.1.6 root 722: extern int cpu_sleep_millis(int ms);
723: extern void cpu_change(int newmodel);
724: extern void cpu_fallback(int mode);
1.1.1.3 root 725:
1.1.1.5 root 726: extern void fill_prefetch (void);
1.1.1.7 ! root 727: extern void fill_prefetch_020_ntx(void);
! 728: extern void fill_prefetch_030_ntx(void);
! 729: extern void fill_prefetch_030_ntx_continue(void);
! 730: extern void fill_prefetch_020(void);
! 731: extern void fill_prefetch_030(void);
1.1.1.3 root 732:
733: #define CPU_OP_NAME(a) op ## a
734:
735: /* 68060 */
736: extern const struct cputbl op_smalltbl_0_ff[];
1.1.1.5 root 737: extern const struct cputbl op_smalltbl_40_ff[];
1.1.1.6 root 738: extern const struct cputbl op_smalltbl_50_ff[];
1.1.1.5 root 739: extern const struct cputbl op_smalltbl_24_ff[]; // CE
740: extern const struct cputbl op_smalltbl_33_ff[]; // MMU
1.1.1.3 root 741: /* 68040 */
742: extern const struct cputbl op_smalltbl_1_ff[];
1.1.1.5 root 743: extern const struct cputbl op_smalltbl_41_ff[];
1.1.1.6 root 744: extern const struct cputbl op_smalltbl_51_ff[];
1.1.1.5 root 745: extern const struct cputbl op_smalltbl_25_ff[]; // CE
1.1.1.3 root 746: extern const struct cputbl op_smalltbl_31_ff[]; // MMU
747: /* 68030 */
748: extern const struct cputbl op_smalltbl_2_ff[];
1.1.1.5 root 749: extern const struct cputbl op_smalltbl_42_ff[];
1.1.1.6 root 750: extern const struct cputbl op_smalltbl_52_ff[];
1.1.1.5 root 751: extern const struct cputbl op_smalltbl_22_ff[]; // prefetch
752: extern const struct cputbl op_smalltbl_23_ff[]; // CE
1.1.1.4 root 753: extern const struct cputbl op_smalltbl_32_ff[]; // MMU
1.1.1.7 ! root 754: extern const struct cputbl op_smalltbl_34_ff[]; // MMU + cache
! 755: extern const struct cputbl op_smalltbl_35_ff[]; // MMU + CE + cache
1.1.1.3 root 756: /* 68020 */
757: extern const struct cputbl op_smalltbl_3_ff[];
1.1.1.5 root 758: extern const struct cputbl op_smalltbl_43_ff[];
1.1.1.6 root 759: extern const struct cputbl op_smalltbl_53_ff[];
1.1.1.5 root 760: extern const struct cputbl op_smalltbl_20_ff[]; // prefetch
761: extern const struct cputbl op_smalltbl_21_ff[]; // CE
1.1.1.3 root 762: /* 68010 */
763: extern const struct cputbl op_smalltbl_4_ff[];
1.1.1.5 root 764: extern const struct cputbl op_smalltbl_44_ff[];
1.1.1.6 root 765: extern const struct cputbl op_smalltbl_54_ff[];
1.1.1.5 root 766: extern const struct cputbl op_smalltbl_11_ff[]; // prefetch
767: extern const struct cputbl op_smalltbl_13_ff[]; // CE
1.1.1.3 root 768: /* 68000 */
769: extern const struct cputbl op_smalltbl_5_ff[];
1.1.1.5 root 770: extern const struct cputbl op_smalltbl_45_ff[];
1.1.1.6 root 771: extern const struct cputbl op_smalltbl_55_ff[];
1.1.1.5 root 772: extern const struct cputbl op_smalltbl_12_ff[]; // prefetch
773: extern const struct cputbl op_smalltbl_14_ff[]; // CE
1.1.1.3 root 774:
775: extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl");
776:
777: #ifdef JIT
1.1.1.7 ! root 778: extern void flush_icache(int);
! 779: extern void flush_icache_hard(int);
1.1.1.5 root 780: extern void compemu_reset(void);
1.1.1.3 root 781: #else
1.1.1.7 ! root 782: #define flush_icache(int) do {} while (0)
! 783: #define flush_icache_hard(int) do {} while (0)
1.1.1.3 root 784: #endif
1.1.1.6 root 785: bool check_prefs_changed_comp (bool);
1.1.1.5 root 786: #ifdef WINUAE_FOR_HATARI
787: extern void flush_instr_cache (uaecptr, int);
788: #endif
1.1.1.3 root 789: extern void flush_mmu (uaecptr, int);
790:
791: extern int movec_illg (int regno);
792: extern uae_u32 val_move2c (int regno);
793: extern void val_move2c2 (int regno, uae_u32 val);
794: struct cpum2c {
795: int regno;
796: const TCHAR *regname;
797: };
798: extern struct cpum2c m2cregs[];
799:
1.1.1.5 root 800: extern bool is_cpu_tracer (void);
801: extern bool set_cpu_tracer (bool force);
802: extern bool can_cpu_tracer (void);
803:
1.1.1.6 root 804: #define CPU_HALT_PPC_ONLY -1
805: #define CPU_HALT_BUS_ERROR_DOUBLE_FAULT 1
806: #define CPU_HALT_DOUBLE_FAULT 2
807: #define CPU_HALT_OPCODE_FETCH_FROM_NON_EXISTING_ADDRESS 3
808: #define CPU_HALT_ACCELERATOR_CPU_FALLBACK 4
809: #define CPU_HALT_ALL_CPUS_STOPPED 5
810: #define CPU_HALT_FAKE_DMA 6
811: #define CPU_HALT_AUTOCONFIG_CONFLICT 7
812: #define CPU_HALT_PCI_CONFLICT 8
813: #define CPU_HALT_CPU_STUCK 9
814: #define CPU_HALT_SSP_IN_NON_EXISTING_ADDRESS 10
1.1.1.7 ! root 815: #define CPU_HALT_INVALID_START_ADDRESS 11
1.1.1.6 root 816:
817: void cpu_semaphore_get(void);
818: void cpu_semaphore_release(void);
819: bool execute_other_cpu(int until);
820: void execute_other_cpu_single(void);
821:
1.1.1.7 ! root 822:
! 823: /* From uae.h */
! 824: #define UAE_QUIT 1
! 825: #define UAE_RESET 2
! 826: #define UAE_RESET_KEYBOARD 3
! 827: #define UAE_RESET_HARD 4
! 828:
! 829: extern int uae_quit_program;
! 830: /* From uae.h */
! 831:
! 832:
! 833:
! 834:
1.1.1.5 root 835: #ifdef WINUAE_FOR_HATARI
836: /*** Hatari ***/
837:
1.1.1.3 root 838: /* Family of the latest instruction executed (to check for pairing) */
839: extern int OpcodeFamily; /* see instrmnem in readcpu.h */
840:
1.1.1.6 root 841: /* How many cycles to add to the current instruction in case a "misaligned" bus access is made */
1.1.1.5 root 842: /* (e.g. used when addressing mode is d8(an,ix)) */
1.1.1.3 root 843: extern int BusCyclePenalty;
844:
1.1.1.5 root 845: /* To redirect WinUAE's prints to our own file */
846: extern FILE *console_out_FILE;
847:
848: /*** Hatari ***/
849: #endif
850:
1.1.1.6 root 851: #endif /* UAE_NEWCPU_H */
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