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1.1.1.3 root 1: /*
2: * UAE - The Un*x Amiga Emulator
3: *
4: * MC68000 emulation
5: *
6: * Copyright 1995 Bernd Schmidt
7: */
8:
1.1.1.6 root 9: #ifndef UAE_NEWCPU_H
10: #define UAE_NEWCPU_H
1.1.1.3 root 11:
1.1.1.6 root 12: #include "uae/types.h"
1.1.1.3 root 13: #include "readcpu.h"
1.1.1.6 root 14: #include "machdep/m68k.h"
1.1.1.8 ! root 15: #include "events.h"
! 16: #include <softfloat/softfloat.h>
! 17:
! 18: #ifdef WINUAE_FOR_HATARI
1.1.1.3 root 19: #include "compat.h"
20: #include "maccess.h"
21: #include "memory.h"
22: #include "custom.h"
23:
24: /* Possible exceptions sources for M68000_Exception() and Exception() */
1.1.1.5 root 25: // TODO : remove when not used anymore in m68000.c
26: #define M68000_EXC_SRC_CPU 1 /* Direct CPU exception */
27: #define M68000_EXC_SRC_AUTOVEC 2 /* Auto-vector exception (e.g. VBL) */
28: #define M68000_EXC_SRC_INT_MFP 3 /* MFP interrupt exception */
29: #define M68000_EXC_SRC_INT_DSP 4 /* DSP interrupt exception */
1.1.1.3 root 30:
31:
1.1.1.7 root 32: /* Special flags (from custom.h) */
1.1.1.3 root 33: #define SPCFLAG_DEBUGGER 1
34: #define SPCFLAG_STOP 2
35: #define SPCFLAG_BUSERROR 4
36: #define SPCFLAG_INT 8
37: #define SPCFLAG_BRK 0x10
38: #define SPCFLAG_EXTRA_CYCLES 0x20
39: #define SPCFLAG_TRACE 0x40
40: #define SPCFLAG_DOTRACE 0x80
41: #define SPCFLAG_DOINT 0x100
42: #define SPCFLAG_MFP 0x200
43: #define SPCFLAG_EXEC 0x400
44: #define SPCFLAG_MODE_CHANGE 0x800
1.1.1.4 root 45: #define SPCFLAG_DSP 0x1000
1.1.1.8 ! root 46: #endif
1.1.1.5 root 47:
1.1.1.3 root 48: #ifndef SET_CFLG
49:
50: #define SET_CFLG(x) (CFLG() = (x))
51: #define SET_NFLG(x) (NFLG() = (x))
52: #define SET_VFLG(x) (VFLG() = (x))
53: #define SET_ZFLG(x) (ZFLG() = (x))
54: #define SET_XFLG(x) (XFLG() = (x))
55:
56: #define GET_CFLG() CFLG()
57: #define GET_NFLG() NFLG()
58: #define GET_VFLG() VFLG()
59: #define GET_ZFLG() ZFLG()
60: #define GET_XFLG() XFLG()
61:
62: #define CLEAR_CZNV() do { \
63: SET_CFLG (0); \
64: SET_ZFLG (0); \
65: SET_NFLG (0); \
66: SET_VFLG (0); \
67: } while (0)
68:
69: #define COPY_CARRY() (SET_XFLG (GET_CFLG ()))
70: #endif
71:
72: extern const int areg_byteinc[];
73: extern const int imm8_table[];
74:
75: extern int movem_index1[256];
76: extern int movem_index2[256];
77: extern int movem_next[256];
78:
79: #ifdef FPUEMU
80: extern int fpp_movem_index1[256];
81: extern int fpp_movem_index2[256];
82: extern int fpp_movem_next[256];
83: #endif
84:
1.1.1.5 root 85: extern int bus_error_offset;
1.1.1.3 root 86:
1.1.1.5 root 87: typedef uae_u32 REGPARAM3 cpuop_func (uae_u32) REGPARAM;
1.1.1.3 root 88: typedef void REGPARAM3 cpuop_func_ce (uae_u32) REGPARAM;
89:
90: struct cputbl {
91: cpuop_func *handler;
92: uae_u16 opcode;
1.1.1.5 root 93: uae_s8 length;
94: uae_s8 disp020[2];
95: uae_u8 branch;
1.1.1.3 root 96: };
97:
98: #ifdef JIT
1.1.1.8 ! root 99: #define MIN_JIT_CACHE 128
1.1.1.6 root 100: #define MAX_JIT_CACHE 16384
1.1.1.5 root 101: typedef uae_u32 REGPARAM3 compop_func (uae_u32) REGPARAM;
1.1.1.3 root 102:
1.1.1.6 root 103: #define COMP_OPCODE_ISJUMP 0x0001
104: #define COMP_OPCODE_LONG_OPCODE 0x0002
105: #define COMP_OPCODE_CMOV 0x0004
106: #define COMP_OPCODE_ISADDX 0x0008
107: #define COMP_OPCODE_ISCJUMP 0x0010
108: #define COMP_OPCODE_USES_FPU 0x0020
109:
1.1.1.3 root 110: struct comptbl {
111: compop_func *handler;
112: uae_u32 opcode;
113: int specific;
114: };
115: #endif
116:
1.1.1.5 root 117: extern uae_u32 REGPARAM3 op_illg (uae_u32) REGPARAM;
118: extern void REGPARAM3 op_unimpl (uae_u16) REGPARAM;
1.1.1.3 root 119:
120: typedef uae_u8 flagtype;
121:
122: #ifdef FPUEMU
123:
1.1.1.5 root 124: #ifdef USE_LONG_DOUBLE
1.1.1.3 root 125: typedef long double fptype;
126: #else
127: typedef double fptype;
128: #endif
129: #endif
130:
1.1.1.5 root 131: #define MAX68020CYCLES 4
132:
133: #define CPU_PIPELINE_MAX 4
1.1.1.3 root 134: #define CPU000_MEM_CYCLE 4
135: #define CPU000_CLOCK_MULT 2
136: #define CPU020_MEM_CYCLE 3
137: #define CPU020_CLOCK_MULT 4
138:
139: #define CACHELINES020 64
140: struct cache020
141: {
142: uae_u32 data;
143: uae_u32 tag;
144: bool valid;
145: };
146:
147: #define CACHELINES030 16
148: struct cache030
149: {
150: uae_u32 data[4];
151: bool valid[4];
152: uae_u32 tag;
1.1.1.7 root 153: uae_u8 fc;
1.1.1.3 root 154: };
155:
156: #define CACHESETS040 64
1.1.1.7 root 157: #define CACHESETS060 128
1.1.1.3 root 158: #define CACHELINES040 4
159: struct cache040
160: {
161: uae_u32 data[CACHELINES040][4];
1.1.1.5 root 162: bool dirty[CACHELINES040][4];
1.1.1.7 root 163: bool gdirty[CACHELINES040];
1.1.1.3 root 164: bool valid[CACHELINES040];
165: uae_u32 tag[CACHELINES040];
166: };
167:
1.1.1.4 root 168: struct mmufixup
169: {
170: int reg;
171: uae_u32 value;
172: };
173: extern struct mmufixup mmufixup[2];
1.1.1.3 root 174:
1.1.1.8 ! root 175: #ifdef MSVC_LONG_DOUBLE
! 176: typedef struct {
! 177: uae_u64 m;
! 178: uae_u16 e;
! 179: uae_u16 dummy;
! 180: } fprawtype;
! 181: #endif
! 182:
1.1.1.5 root 183: typedef struct
184: {
185: floatx80 fpx;
1.1.1.8 ! root 186: #ifdef MSVC_LONG_DOUBLE
! 187: union {
! 188: fptype fp;
! 189: fprawtype rfp;
! 190: };
! 191: #else
1.1.1.7 root 192: fptype fp;
1.1.1.8 ! root 193: #endif
1.1.1.5 root 194: } fpdata;
195:
1.1.1.3 root 196: struct regstruct
197: {
198: uae_u32 regs[16];
199:
200: uae_u32 pc;
201: uae_u8 *pc_p;
202: uae_u8 *pc_oldp;
1.1.1.5 root 203: uae_u16 opcode;
204: uae_u32 instruction_pc;
1.1.1.8 ! root 205: uae_u32 instruction_pc_user_exception;
1.1.1.3 root 206:
1.1.1.5 root 207: uae_u16 irc, ir, db;
1.1.1.6 root 208: volatile uae_atomic spcflags;
1.1.1.5 root 209: uae_u32 last_prefetch;
210: uae_u32 chipset_latch_rw;
211: uae_u32 chipset_latch_read;
212: uae_u32 chipset_latch_write;
1.1.1.3 root 213:
214: uaecptr usp, isp, msp;
215: uae_u16 sr;
216: flagtype t1;
217: flagtype t0;
218: flagtype s;
219: flagtype m;
220: flagtype x;
221: flagtype stopped;
1.1.1.5 root 222: int halted;
223: int exception;
1.1.1.3 root 224: int intmask;
225: int ipl, ipl_pin;
226:
227: uae_u32 vbr, sfc, dfc;
228:
229: #ifdef FPUEMU
1.1.1.5 root 230: fpdata fp[8];
1.1.1.7 root 231: #ifdef JIT
1.1.1.5 root 232: fpdata fp_result;
1.1.1.7 root 233: #endif
1.1.1.3 root 234: uae_u32 fpcr, fpsr, fpiar;
1.1.1.5 root 235: uae_u32 fpu_state;
236: uae_u32 fpu_exp_state;
1.1.1.7 root 237: uae_u16 fp_opword;
238: uaecptr fp_ea;
239: uae_u32 fp_exp_pend, fp_unimp_pend;
240: bool fpu_exp_pre;
241: bool fp_unimp_ins;
1.1.1.5 root 242: bool fp_exception;
243: bool fp_branch;
1.1.1.3 root 244: #endif
245: #ifndef CPUEMU_68000_ONLY
246: uae_u32 cacr, caar;
247: uae_u32 itt0, itt1, dtt0, dtt1;
248: uae_u32 tcr, mmusr, urp, srp, buscr;
1.1.1.5 root 249: uae_u32 mmu_fslw;
250: uae_u32 mmu_fault_addr, mmu_effective_addr;
1.1.1.3 root 251: uae_u16 mmu_ssw;
1.1.1.5 root 252: uae_u32 wb2_address;
1.1.1.3 root 253: uae_u32 wb3_data;
1.1.1.5 root 254: uae_u8 wb3_status, wb2_status;
1.1.1.3 root 255: int mmu_enabled;
1.1.1.5 root 256: int mmu_page_size;
1.1.1.3 root 257: #endif
258:
259: uae_u32 pcr;
260: uae_u32 address_space_mask;
261:
1.1.1.7 root 262: uae_u16 prefetch020[CPU_PIPELINE_MAX];
263: uae_u8 prefetch020_valid[CPU_PIPELINE_MAX];
1.1.1.5 root 264: uae_u32 prefetch020addr;
265: uae_u32 cacheholdingdata020;
266: uae_u32 cacheholdingaddr020;
1.1.1.7 root 267: uae_u8 cacheholdingdata_valid;
1.1.1.5 root 268: int pipeline_pos;
269: int pipeline_r8[2];
270: int pipeline_stop;
1.1.1.7 root 271: uae_u8 fc030;
272:
273: uae_u32 prefetch040[CPU_PIPELINE_MAX];
274:
275: int ce020endcycle;
276: int ce020startcycle;
277: int ce020prefetchendcycle;
278:
1.1.1.5 root 279: int ce020extracycles;
280: bool ce020memcycle_data;
281: int ce020_tail;
282: frame_time_t ce020_tail_cycles;
283: int memory_waitstate_cycles;
1.1.1.3 root 284: };
285:
286: extern struct regstruct regs;
287:
1.1.1.5 root 288: #define MAX_CPUTRACESIZE 128
289: struct cputracememory
290: {
291: uae_u32 addr;
292: uae_u32 data;
293: int mode;
294: };
295:
296: struct cputracestruct
297: {
298: uae_u32 regs[16];
299: uae_u32 usp, isp, pc;
300: uae_u16 ir, irc, sr, opcode;
301: int intmask, stopped, state;
302:
303: uae_u32 msp, vbr;
304: uae_u32 cacr, caar;
1.1.1.7 root 305: uae_u16 prefetch020[CPU_PIPELINE_MAX];
306: uae_u8 prefetch020_valid[CPU_PIPELINE_MAX];
1.1.1.5 root 307: uae_u32 prefetch020addr;
308: uae_u32 cacheholdingdata020;
309: uae_u32 cacheholdingaddr020;
310: struct cache020 caches020[CACHELINES020];
1.1.1.7 root 311: int pipeline_pos;
312: int pipeline_r8[2];
313: int pipeline_stop;
1.1.1.5 root 314:
315: uae_u32 startcycles;
316: int needendcycles;
317: int memoryoffset;
318: int cyclecounter, cyclecounter_pre, cyclecounter_post;
319: int readcounter, writecounter;
320: struct cputracememory ctm[MAX_CPUTRACESIZE];
321: };
322:
1.1.1.3 root 323: STATIC_INLINE uae_u32 munge24 (uae_u32 x)
324: {
325: return x & regs.address_space_mask;
326: }
327:
328: extern int mmu_enabled, mmu_triggered;
329: extern int cpu_cycles;
330: extern int cpucycleunit;
1.1.1.5 root 331: extern int m68k_pc_indirect;
1.1.1.6 root 332:
1.1.1.8 ! root 333: extern void safe_interrupt_set(int, int, bool);
! 334:
1.1.1.6 root 335: #ifndef WINUAE_FOR_HATARI
336: STATIC_INLINE void set_special_exter(uae_u32 x)
337: {
338: atomic_or(®s.spcflags, x);
339: }
340: STATIC_INLINE void set_special (uae_u32 x)
341: {
342: atomic_or(®s.spcflags, x);
343: cycles_do_special ();
344: }
345:
346: STATIC_INLINE void unset_special (uae_u32 x)
347: {
348: atomic_and(®s.spcflags, ~x);
349: }
350: #else
1.1.1.3 root 351: STATIC_INLINE void set_special (uae_u32 x)
352: {
353: regs.spcflags |= x;
354: cycles_do_special ();
355: }
356:
357: STATIC_INLINE void unset_special (uae_u32 x)
358: {
359: regs.spcflags &= ~x;
360: }
361:
1.1.1.6 root 362: #endif
363:
1.1.1.3 root 364: #define m68k_dreg(r,num) ((r).regs[(num)])
365: #define m68k_areg(r,num) (((r).regs + 8)[(num)])
366:
1.1.1.5 root 367: extern uae_u32(*x_prefetch)(int);
368: extern uae_u32(*x_get_byte)(uaecptr addr);
369: extern uae_u32(*x_get_word)(uaecptr addr);
370: extern uae_u32(*x_get_long)(uaecptr addr);
371: extern void(*x_put_byte)(uaecptr addr, uae_u32 v);
372: extern void(*x_put_word)(uaecptr addr, uae_u32 v);
373: extern void(*x_put_long)(uaecptr addr, uae_u32 v);
374: extern uae_u32(*x_next_iword)(void);
375: extern uae_u32(*x_next_ilong)(void);
376: extern uae_u32(*x_get_ilong)(int);
377: extern uae_u32(*x_get_iword)(int);
378: extern uae_u32(*x_get_ibyte)(int);
379:
380: extern uae_u32(*x_cp_get_byte)(uaecptr addr);
381: extern uae_u32(*x_cp_get_word)(uaecptr addr);
382: extern uae_u32(*x_cp_get_long)(uaecptr addr);
383: extern void(*x_cp_put_byte)(uaecptr addr, uae_u32 v);
384: extern void(*x_cp_put_word)(uaecptr addr, uae_u32 v);
385: extern void(*x_cp_put_long)(uaecptr addr, uae_u32 v);
386: extern uae_u32(*x_cp_next_iword)(void);
387: extern uae_u32(*x_cp_next_ilong)(void);
388:
1.1.1.7 root 389: void mem_access_delay_long_write_ce020 (uaecptr addr, uae_u32 v);
390: void mem_access_delay_word_write_ce020 (uaecptr addr, uae_u32 v);
391: void mem_access_delay_byte_write_ce020 (uaecptr addr, uae_u32 v);
392: uae_u32 mem_access_delay_byte_read_ce020 (uaecptr addr);
393: uae_u32 mem_access_delay_word_read_ce020 (uaecptr addr);
394: uae_u32 mem_access_delay_long_read_ce020 (uaecptr addr);
395: uae_u32 mem_access_delay_longi_read_ce020 (uaecptr addr);
396: uae_u32 mem_access_delay_wordi_read_ce020 (uaecptr addr);
397:
398: void mem_access_delay_long_write_c040 (uaecptr addr, uae_u32 v);
399: void mem_access_delay_word_write_c040 (uaecptr addr, uae_u32 v);
400: void mem_access_delay_byte_write_c040 (uaecptr addr, uae_u32 v);
401: uae_u32 mem_access_delay_byte_read_c040 (uaecptr addr);
402: uae_u32 mem_access_delay_word_read_c040 (uaecptr addr);
403: uae_u32 mem_access_delay_long_read_c040 (uaecptr addr);
404: uae_u32 mem_access_delay_longi_read_c040 (uaecptr addr);
405:
1.1.1.5 root 406: extern uae_u32(REGPARAM3 *x_cp_get_disp_ea_020)(uae_u32 base, int idx) REGPARAM;
407:
1.1.1.8 ! root 408: #ifndef WINUAE_FOR_HATARI
! 409: extern bool debugmem_trace;
! 410: extern void branch_stack_push(uaecptr, uaecptr);
! 411: extern void branch_stack_pop_rte(uaecptr);
! 412: extern void branch_stack_pop_rts(uaecptr);
! 413: #endif
! 414:
1.1.1.5 root 415: /* direct (regs.pc_p) access */
416:
417: STATIC_INLINE void m68k_setpc(uaecptr newpc)
1.1.1.3 root 418: {
1.1.1.5 root 419: regs.pc_p = regs.pc_oldp = get_real_address(newpc);
420: regs.instruction_pc = regs.pc = newpc;
1.1.1.3 root 421: }
1.1.1.8 ! root 422: STATIC_INLINE void m68k_setpc_j(uaecptr newpc)
! 423: {
! 424: regs.pc_p = regs.pc_oldp = get_real_address(newpc);
! 425: regs.pc = newpc;
! 426: }
1.1.1.5 root 427: STATIC_INLINE uaecptr m68k_getpc(void)
1.1.1.3 root 428: {
429: return (uaecptr)(regs.pc + ((uae_u8*)regs.pc_p - (uae_u8*)regs.pc_oldp));
430: }
431: #define M68K_GETPC m68k_getpc()
1.1.1.5 root 432: STATIC_INLINE uaecptr m68k_getpc_p(uae_u8 *p)
1.1.1.3 root 433: {
434: return (uaecptr)(regs.pc + ((uae_u8*)p - (uae_u8*)regs.pc_oldp));
435: }
1.1.1.5 root 436: STATIC_INLINE void m68k_incpc(int o)
1.1.1.3 root 437: {
438: regs.pc_p += o;
439: }
440:
1.1.1.5 root 441: STATIC_INLINE uae_u32 get_dibyte(int o)
1.1.1.3 root 442: {
1.1.1.5 root 443: return do_get_mem_byte((uae_u8 *)((regs).pc_p + (o) + 1));
1.1.1.3 root 444: }
1.1.1.5 root 445: STATIC_INLINE uae_u32 get_diword(int o)
1.1.1.3 root 446: {
1.1.1.5 root 447: return do_get_mem_word((uae_u16 *)((regs).pc_p + (o)));
1.1.1.3 root 448: }
1.1.1.5 root 449: STATIC_INLINE uae_u32 get_dilong(int o)
1.1.1.3 root 450: {
1.1.1.5 root 451: return do_get_mem_long((uae_u32 *)((regs).pc_p + (o)));
1.1.1.3 root 452: }
1.1.1.5 root 453: STATIC_INLINE uae_u32 next_diword(void)
1.1.1.3 root 454: {
1.1.1.5 root 455: uae_u32 r = do_get_mem_word((uae_u16 *)((regs).pc_p));
456: m68k_incpc(2);
457: return r;
458: }
459: STATIC_INLINE uae_u32 next_dilong(void)
460: {
461: uae_u32 r = do_get_mem_long((uae_u32 *)((regs).pc_p));
462: m68k_incpc(4);
463: return r;
1.1.1.3 root 464: }
465:
1.1.1.5 root 466: STATIC_INLINE void m68k_do_bsr(uaecptr oldpc, uae_s32 offset)
1.1.1.3 root 467: {
1.1.1.5 root 468: m68k_areg(regs, 7) -= 4;
469: put_long(m68k_areg(regs, 7), oldpc);
470: m68k_incpc(offset);
1.1.1.3 root 471: }
1.1.1.5 root 472: STATIC_INLINE void m68k_do_rts(void)
1.1.1.3 root 473: {
1.1.1.5 root 474: uae_u32 newpc = get_long(m68k_areg(regs, 7));
475: m68k_setpc(newpc);
476: m68k_areg(regs, 7) += 4;
1.1.1.3 root 477: }
478:
1.1.1.5 root 479: /* indirect (regs.pc) access */
480:
481: STATIC_INLINE void m68k_setpci(uaecptr newpc)
1.1.1.3 root 482: {
1.1.1.5 root 483: regs.instruction_pc = regs.pc = newpc;
1.1.1.3 root 484: }
1.1.1.8 ! root 485: STATIC_INLINE void m68k_setpci_j(uaecptr newpc)
! 486: {
! 487: regs.pc = newpc;
! 488: }
1.1.1.5 root 489: STATIC_INLINE uaecptr m68k_getpci(void)
1.1.1.3 root 490: {
1.1.1.5 root 491: return regs.pc;
492: }
493: STATIC_INLINE void m68k_incpci(int o)
494: {
495: regs.pc += o;
1.1.1.3 root 496: }
497:
1.1.1.5 root 498: STATIC_INLINE uae_u32 get_iibyte(int o)
1.1.1.3 root 499: {
1.1.1.5 root 500: return get_wordi(m68k_getpci() + (o)) & 0xff;
1.1.1.3 root 501: }
1.1.1.5 root 502: STATIC_INLINE uae_u32 get_iiword(int o)
1.1.1.3 root 503: {
1.1.1.5 root 504: return get_wordi(m68k_getpci() + (o));
1.1.1.3 root 505: }
1.1.1.5 root 506: STATIC_INLINE uae_u32 get_iilong(int o)
1.1.1.3 root 507: {
1.1.1.5 root 508: return get_longi(m68k_getpci () + (o));
1.1.1.3 root 509: }
510:
1.1.1.5 root 511: STATIC_INLINE uae_u32 next_iibyte (void)
1.1.1.3 root 512: {
1.1.1.5 root 513: uae_u32 r = get_iibyte (0);
514: m68k_incpci (2);
1.1.1.3 root 515: return r;
516: }
1.1.1.5 root 517: STATIC_INLINE uae_u32 next_iiword (void)
1.1.1.3 root 518: {
1.1.1.5 root 519: uae_u32 r = get_iiword (0);
520: m68k_incpci (2);
1.1.1.3 root 521: return r;
522: }
1.1.1.5 root 523: STATIC_INLINE uae_u32 next_iiwordi (void)
1.1.1.3 root 524: {
1.1.1.5 root 525: uae_u32 r = get_wordi(m68k_getpci());
526: m68k_incpci (2);
1.1.1.3 root 527: return r;
528: }
1.1.1.5 root 529: STATIC_INLINE uae_u32 next_iilong (void)
1.1.1.3 root 530: {
1.1.1.5 root 531: uae_u32 r = get_iilong(0);
532: m68k_incpci (4);
1.1.1.3 root 533: return r;
534: }
1.1.1.5 root 535: STATIC_INLINE uae_u32 next_iilongi (void)
1.1.1.3 root 536: {
1.1.1.5 root 537: uae_u32 r = get_longi (m68k_getpci ());
538: m68k_incpci (4);
1.1.1.3 root 539: return r;
540: }
541:
1.1.1.5 root 542: STATIC_INLINE void m68k_do_bsri(uaecptr oldpc, uae_s32 offset)
543: {
544: m68k_areg(regs, 7) -= 4;
1.1.1.7 root 545: x_put_long(m68k_areg(regs, 7), oldpc);
1.1.1.5 root 546: m68k_incpci(offset);
547: }
548: STATIC_INLINE void m68k_do_rtsi(void)
549: {
1.1.1.7 root 550: uae_u32 newpc = x_get_long(m68k_areg(regs, 7));
1.1.1.5 root 551: m68k_setpci(newpc);
552: m68k_areg(regs, 7) += 4;
553: }
554:
555: /* indirect jit friendly versions */
1.1.1.3 root 556:
1.1.1.5 root 557: STATIC_INLINE uae_u32 get_iibyte_jit(int o)
558: {
559: return get_wordi(m68k_getpc() + (o)) & 0xff;
560: }
561: STATIC_INLINE uae_u32 get_iiword_jit(int o)
562: {
563: return get_wordi(m68k_getpc() + (o));
564: }
565: STATIC_INLINE uae_u32 get_iilong_jit(int o)
566: {
567: return get_longi(m68k_getpc() + (o));
568: }
569: STATIC_INLINE uae_u32 next_iiword_jit(void)
570: {
571: uae_u32 r = get_wordi(m68k_getpc());
572: m68k_incpc(2);
573: return r;
574: }
575: STATIC_INLINE uae_u32 next_iilong_jit(void)
576: {
577: uae_u32 r = get_longi(m68k_getpc());
578: m68k_incpc(4);
579: return r;
580: }
581: STATIC_INLINE void m68k_do_bsri_jit(uaecptr oldpc, uae_s32 offset)
582: {
583: m68k_areg(regs, 7) -= 4;
584: x_put_long(m68k_areg(regs, 7), oldpc);
585: m68k_incpc(offset);
586: }
587: STATIC_INLINE void m68k_do_rtsi_jit(void)
588: {
589: uae_u32 newpc = x_get_long(m68k_areg(regs, 7));
590: m68k_setpc(newpc);
591: m68k_areg(regs, 7) += 4;
592: }
593:
594: /* common access */
595:
596: STATIC_INLINE void m68k_incpc_normal(int o)
597: {
598: if (m68k_pc_indirect > 0)
599: m68k_incpci(o);
600: else
601: m68k_incpc(o);
602: }
603:
604: STATIC_INLINE void m68k_setpc_normal(uaecptr pc)
605: {
606: if (m68k_pc_indirect > 0) {
607: regs.pc_p = regs.pc_oldp = 0;
608: m68k_setpci(pc);
609: } else {
610: m68k_setpc(pc);
611: }
612: }
613:
1.1.1.8 ! root 614: extern void cpu_invalidate_cache(uaecptr, int);
! 615:
1.1.1.7 root 616: extern uae_u32(*read_data_030_bget)(uaecptr);
617: extern uae_u32(*read_data_030_wget)(uaecptr);
618: extern uae_u32(*read_data_030_lget)(uaecptr);
619: extern void(*write_data_030_bput)(uaecptr,uae_u32);
620: extern void(*write_data_030_wput)(uaecptr,uae_u32);
621: extern void(*write_data_030_lput)(uaecptr,uae_u32);
622:
623: extern uae_u32(*read_data_030_fc_bget)(uaecptr, uae_u32);
624: extern uae_u32(*read_data_030_fc_wget)(uaecptr, uae_u32);
625: extern uae_u32(*read_data_030_fc_lget)(uaecptr, uae_u32);
626: extern void(*write_data_030_fc_bput)(uaecptr, uae_u32, uae_u32);
627: extern void(*write_data_030_fc_wput)(uaecptr, uae_u32, uae_u32);
628: extern void(*write_data_030_fc_lput)(uaecptr, uae_u32, uae_u32);
629:
630: extern void write_dcache030_bput(uaecptr, uae_u32, uae_u32);
631: extern void write_dcache030_wput(uaecptr, uae_u32, uae_u32);
632: extern void write_dcache030_lput(uaecptr, uae_u32, uae_u32);
1.1.1.8 ! root 633: extern void write_dcache030_retry(uaecptr addr, uae_u32 v, uae_u32 fc, int size, int flags);
1.1.1.7 root 634: extern uae_u32 read_dcache030_bget(uaecptr, uae_u32);
635: extern uae_u32 read_dcache030_wget(uaecptr, uae_u32);
636: extern uae_u32 read_dcache030_lget(uaecptr, uae_u32);
1.1.1.8 ! root 637: extern uae_u32 read_dcache030_retry(uaecptr addr, uae_u32 fc, int size, int flags);
1.1.1.7 root 638:
639: extern void write_dcache030_mmu_bput(uaecptr, uae_u32);
640: extern void write_dcache030_mmu_wput(uaecptr, uae_u32);
641: extern void write_dcache030_mmu_lput(uaecptr, uae_u32);
642: extern uae_u32 read_dcache030_mmu_bget(uaecptr);
643: extern uae_u32 read_dcache030_mmu_wget(uaecptr);
644: extern uae_u32 read_dcache030_mmu_lget(uaecptr);
645: extern void write_dcache030_lrmw_mmu(uaecptr, uae_u32, uae_u32);
1.1.1.8 ! root 646: extern void write_dcache030_lrmw_mmu_fcx(uaecptr, uae_u32, uae_u32, int);
1.1.1.7 root 647: extern uae_u32 read_dcache030_lrmw_mmu(uaecptr, uae_u32);
1.1.1.8 ! root 648: extern uae_u32 read_dcache030_lrmw_mmu_fcx(uaecptr, uae_u32, int);
1.1.1.7 root 649:
650: extern void check_t0_trace(void);
1.1.1.5 root 651: extern uae_u32 get_word_icache030(uaecptr addr);
652: extern uae_u32 get_long_icache030(uaecptr addr);
653:
654: uae_u32 fill_icache040(uae_u32 addr);
655: extern void put_long_cache_040(uaecptr, uae_u32);
656: extern void put_word_cache_040(uaecptr, uae_u32);
657: extern void put_byte_cache_040(uaecptr, uae_u32);
658: extern uae_u32 get_ilong_cache_040(int);
659: extern uae_u32 get_iword_cache_040(int);
660: extern uae_u32 get_long_cache_040(uaecptr);
661: extern uae_u32 get_word_cache_040(uaecptr);
662: extern uae_u32 get_byte_cache_040(uaecptr);
663: extern uae_u32 next_iword_cache040(void);
664: extern uae_u32 next_ilong_cache040(void);
665: extern uae_u32 get_word_icache040(uaecptr addr);
666: extern uae_u32 get_long_icache040(uaecptr addr);
667:
1.1.1.8 ! root 668: extern uae_u32 sfc_nommu_get_byte(uaecptr);
! 669: extern uae_u32 sfc_nommu_get_word(uaecptr);
! 670: extern uae_u32 sfc_nommu_get_long(uaecptr);
! 671: extern void dfc_nommu_put_byte(uaecptr, uae_u32);
! 672: extern void dfc_nommu_put_word(uaecptr, uae_u32);
! 673: extern void dfc_nommu_put_long(uaecptr, uae_u32);
! 674:
1.1.1.5 root 675: extern void (*x_do_cycles)(unsigned long);
676: extern void (*x_do_cycles_pre)(unsigned long);
677: extern void (*x_do_cycles_post)(unsigned long, uae_u32);
1.1.1.7 root 678: #ifdef WINUAE_FOR_HATARI
679: void set_x_funcs_hatari_blitter (int flag);
680: #endif
1.1.1.5 root 681:
682: extern uae_u32 REGPARAM3 x_get_disp_ea_020 (uae_u32 base, int idx) REGPARAM;
683: extern uae_u32 REGPARAM3 x_get_disp_ea_ce020 (uae_u32 base, int idx) REGPARAM;
684: extern uae_u32 REGPARAM3 x_get_disp_ea_ce030 (uae_u32 base, int idx) REGPARAM;
685: extern uae_u32 REGPARAM3 x_get_disp_ea_040(uae_u32 base, int idx) REGPARAM;
1.1.1.3 root 686: extern uae_u32 REGPARAM3 x_get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
687: extern void REGPARAM3 x_put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;
688:
689: extern void m68k_setstopped (void);
690: extern void m68k_resumestopped (void);
1.1.1.7 root 691: extern void m68k_cancel_idle(void);
1.1.1.3 root 692:
1.1.1.5 root 693: extern uae_u32 REGPARAM3 get_disp_ea_020 (uae_u32 base, int idx) REGPARAM;
1.1.1.3 root 694: extern uae_u32 REGPARAM3 get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
695: extern void REGPARAM3 put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;
696:
1.1.1.8 ! root 697: extern void m68k_disasm_ea (uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr, uaecptr lastpc);
! 698: extern void m68k_disasm (uaecptr addr, uaecptr *nextpc, uaecptr lastpc, int cnt);
! 699: extern void m68k_disasm_2 (TCHAR *buf, int bufsize, uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr, uaecptr lastpc, int safemode);
1.1.1.5 root 700: #ifdef WINUAE_FOR_HATARI
1.1.1.8 ! root 701: extern void m68k_disasm_file (FILE *f, uaecptr addr, uaecptr *nextpc, uaecptr lastpc, int cnt);
1.1.1.5 root 702: #endif
1.1.1.8 ! root 703: extern void sm68k_disasm (TCHAR*, TCHAR*, uaecptr addr, uaecptr *nextpc, uaecptr lastpc);
! 704: extern int m68k_asm(TCHAR *buf, uae_u16 *out, uaecptr pc);
! 705: extern int get_cpu_model (void);
1.1.1.3 root 706:
1.1.1.5 root 707: extern void set_cpu_caches (bool flush);
1.1.1.7 root 708: #ifdef WINUAE_FOR_HATARI
709: extern void invalidate_cpu_data_caches(void);
710: #endif
1.1.1.5 root 711: extern void flush_cpu_caches(bool flush);
712: extern void flush_cpu_caches_040(uae_u16 opcode);
1.1.1.3 root 713: extern void REGPARAM3 MakeSR (void) REGPARAM;
1.1.1.7 root 714: extern void REGPARAM3 MakeFromSR(void) REGPARAM;
715: extern void REGPARAM3 MakeFromSR_T0(void) REGPARAM;
1.1.1.5 root 716: extern void REGPARAM3 Exception (int) REGPARAM;
1.1.1.7 root 717: extern void REGPARAM3 Exception_cpu(int) REGPARAM;
1.1.1.5 root 718: extern void REGPARAM3 ExceptionL (int, uaecptr) REGPARAM;
1.1.1.3 root 719: extern void NMI (void);
720: extern void NMI_delayed (void);
721: extern void prepare_interrupt (uae_u32);
722: extern void doint (void);
723: extern void dump_counts (void);
724: extern int m68k_move2c (int, uae_u32 *);
725: extern int m68k_movec2 (int, uae_u32 *);
1.1.1.5 root 726: extern bool m68k_divl (uae_u32, uae_u32, uae_u16);
727: extern bool m68k_mull (uae_u32, uae_u32, uae_u16);
1.1.1.3 root 728: extern void init_m68k (void);
729: extern void m68k_go (int);
1.1.1.8 ! root 730: extern void m68k_dumpstate(uaecptr *, uaecptr);
! 731: #ifdef WINUAE_FOR_HATARI
! 732: extern void m68k_dumpstate_file (FILE *f, uaecptr *nextpc, uaecptr prevpc);
! 733: #endif
1.1.1.7 root 734: extern void m68k_dumpcache (bool);
1.1.1.3 root 735: extern int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor);
736: extern int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor);
1.1.1.7 root 737: extern void divbyzero_special(bool issigned, uae_s32 dst);
738: extern void setdivuoverflowflags(uae_u32 dividend, uae_u16 divisor);
739: extern void setdivsoverflowflags(uae_s32 dividend, uae_s16 divisor);
1.1.1.5 root 740: extern void protect_roms (bool);
741: extern void unprotect_maprom (void);
742: extern bool is_hardreset(void);
743: extern bool is_keyboardreset(void);
1.1.1.3 root 744:
745: extern void mmu_op (uae_u32, uae_u32);
1.1.1.5 root 746: extern bool mmu_op30 (uaecptr, uae_u32, uae_u16, uaecptr);
1.1.1.3 root 747:
748: extern void fpuop_arithmetic(uae_u32, uae_u16);
749: extern void fpuop_dbcc(uae_u32, uae_u16);
750: extern void fpuop_scc(uae_u32, uae_u16);
751: extern void fpuop_trapcc(uae_u32, uaecptr, uae_u16);
752: extern void fpuop_bcc(uae_u32, uaecptr, uae_u32);
753: extern void fpuop_save(uae_u32);
754: extern void fpuop_restore(uae_u32);
755: extern uae_u32 fpp_get_fpsr (void);
756: extern void fpu_reset (void);
757: extern void fpux_save (int*);
758: extern void fpux_restore (int*);
1.1.1.5 root 759: extern bool fpu_get_constant(fpdata *fp, int cr);
760: extern int fpp_cond(int condition);
1.1.1.3 root 761:
1.1.1.6 root 762: extern void exception3_read(uae_u32 opcode, uaecptr addr);
763: extern void exception3_write(uae_u32 opcode, uaecptr addr);
1.1.1.5 root 764: extern void exception3_notinstruction(uae_u32 opcode, uaecptr addr);
765: extern void exception3i (uae_u32 opcode, uaecptr addr);
766: extern void exception3b (uae_u32 opcode, uaecptr addr, bool w, bool i, uaecptr pc);
767: extern void exception2 (uaecptr addr, bool read, int size, uae_u32 fc);
1.1.1.8 ! root 768: extern void exception2_setup(uaecptr addr, bool read, int size, uae_u32 fc);
1.1.1.5 root 769: extern void m68k_reset (void);
1.1.1.3 root 770: extern void cpureset (void);
1.1.1.5 root 771: extern void cpu_halt (int id);
1.1.1.6 root 772: extern int cpu_sleep_millis(int ms);
773: extern void cpu_change(int newmodel);
774: extern void cpu_fallback(int mode);
1.1.1.3 root 775:
1.1.1.5 root 776: extern void fill_prefetch (void);
1.1.1.7 root 777: extern void fill_prefetch_020_ntx(void);
778: extern void fill_prefetch_030_ntx(void);
779: extern void fill_prefetch_030_ntx_continue(void);
780: extern void fill_prefetch_020(void);
781: extern void fill_prefetch_030(void);
1.1.1.3 root 782:
783: #define CPU_OP_NAME(a) op ## a
784:
785: /* 68060 */
786: extern const struct cputbl op_smalltbl_0_ff[];
1.1.1.5 root 787: extern const struct cputbl op_smalltbl_40_ff[];
1.1.1.6 root 788: extern const struct cputbl op_smalltbl_50_ff[];
1.1.1.5 root 789: extern const struct cputbl op_smalltbl_24_ff[]; // CE
790: extern const struct cputbl op_smalltbl_33_ff[]; // MMU
1.1.1.3 root 791: /* 68040 */
792: extern const struct cputbl op_smalltbl_1_ff[];
1.1.1.5 root 793: extern const struct cputbl op_smalltbl_41_ff[];
1.1.1.6 root 794: extern const struct cputbl op_smalltbl_51_ff[];
1.1.1.5 root 795: extern const struct cputbl op_smalltbl_25_ff[]; // CE
1.1.1.3 root 796: extern const struct cputbl op_smalltbl_31_ff[]; // MMU
797: /* 68030 */
798: extern const struct cputbl op_smalltbl_2_ff[];
1.1.1.5 root 799: extern const struct cputbl op_smalltbl_42_ff[];
1.1.1.6 root 800: extern const struct cputbl op_smalltbl_52_ff[];
1.1.1.5 root 801: extern const struct cputbl op_smalltbl_22_ff[]; // prefetch
802: extern const struct cputbl op_smalltbl_23_ff[]; // CE
1.1.1.4 root 803: extern const struct cputbl op_smalltbl_32_ff[]; // MMU
1.1.1.7 root 804: extern const struct cputbl op_smalltbl_34_ff[]; // MMU + cache
805: extern const struct cputbl op_smalltbl_35_ff[]; // MMU + CE + cache
1.1.1.3 root 806: /* 68020 */
807: extern const struct cputbl op_smalltbl_3_ff[];
1.1.1.5 root 808: extern const struct cputbl op_smalltbl_43_ff[];
1.1.1.6 root 809: extern const struct cputbl op_smalltbl_53_ff[];
1.1.1.5 root 810: extern const struct cputbl op_smalltbl_20_ff[]; // prefetch
811: extern const struct cputbl op_smalltbl_21_ff[]; // CE
1.1.1.3 root 812: /* 68010 */
813: extern const struct cputbl op_smalltbl_4_ff[];
1.1.1.5 root 814: extern const struct cputbl op_smalltbl_44_ff[];
1.1.1.6 root 815: extern const struct cputbl op_smalltbl_54_ff[];
1.1.1.5 root 816: extern const struct cputbl op_smalltbl_11_ff[]; // prefetch
817: extern const struct cputbl op_smalltbl_13_ff[]; // CE
1.1.1.3 root 818: /* 68000 */
819: extern const struct cputbl op_smalltbl_5_ff[];
1.1.1.5 root 820: extern const struct cputbl op_smalltbl_45_ff[];
1.1.1.6 root 821: extern const struct cputbl op_smalltbl_55_ff[];
1.1.1.5 root 822: extern const struct cputbl op_smalltbl_12_ff[]; // prefetch
823: extern const struct cputbl op_smalltbl_14_ff[]; // CE
1.1.1.3 root 824:
825: extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl");
826:
827: #ifdef JIT
1.1.1.7 root 828: extern void flush_icache(int);
829: extern void flush_icache_hard(int);
1.1.1.5 root 830: extern void compemu_reset(void);
1.1.1.3 root 831: #else
1.1.1.7 root 832: #define flush_icache(int) do {} while (0)
833: #define flush_icache_hard(int) do {} while (0)
1.1.1.3 root 834: #endif
1.1.1.6 root 835: bool check_prefs_changed_comp (bool);
1.1.1.5 root 836: #ifdef WINUAE_FOR_HATARI
837: extern void flush_instr_cache (uaecptr, int);
838: #endif
1.1.1.3 root 839: extern void flush_mmu (uaecptr, int);
840:
841: extern int movec_illg (int regno);
842: extern uae_u32 val_move2c (int regno);
843: extern void val_move2c2 (int regno, uae_u32 val);
844: struct cpum2c {
845: int regno;
846: const TCHAR *regname;
847: };
848: extern struct cpum2c m2cregs[];
849:
1.1.1.5 root 850: extern bool is_cpu_tracer (void);
851: extern bool set_cpu_tracer (bool force);
852: extern bool can_cpu_tracer (void);
853:
1.1.1.6 root 854: #define CPU_HALT_PPC_ONLY -1
855: #define CPU_HALT_BUS_ERROR_DOUBLE_FAULT 1
856: #define CPU_HALT_DOUBLE_FAULT 2
857: #define CPU_HALT_OPCODE_FETCH_FROM_NON_EXISTING_ADDRESS 3
858: #define CPU_HALT_ACCELERATOR_CPU_FALLBACK 4
859: #define CPU_HALT_ALL_CPUS_STOPPED 5
860: #define CPU_HALT_FAKE_DMA 6
861: #define CPU_HALT_AUTOCONFIG_CONFLICT 7
862: #define CPU_HALT_PCI_CONFLICT 8
863: #define CPU_HALT_CPU_STUCK 9
864: #define CPU_HALT_SSP_IN_NON_EXISTING_ADDRESS 10
1.1.1.7 root 865: #define CPU_HALT_INVALID_START_ADDRESS 11
1.1.1.6 root 866:
1.1.1.8 ! root 867: uae_u32 process_cpu_indirect_memory_read(uae_u32 addr, int size);
! 868: void process_cpu_indirect_memory_write(uae_u32 addr, uae_u32 data, int size);
1.1.1.6 root 869:
1.1.1.7 root 870:
871: /* From uae.h */
872: #define UAE_QUIT 1
873: #define UAE_RESET 2
874: #define UAE_RESET_KEYBOARD 3
875: #define UAE_RESET_HARD 4
876:
1.1.1.8 ! root 877: extern int quit_program;
1.1.1.7 root 878: /* From uae.h */
879:
880:
881:
882:
1.1.1.5 root 883: #ifdef WINUAE_FOR_HATARI
884: /*** Hatari ***/
885:
1.1.1.3 root 886: /* Family of the latest instruction executed (to check for pairing) */
887: extern int OpcodeFamily; /* see instrmnem in readcpu.h */
888:
1.1.1.6 root 889: /* How many cycles to add to the current instruction in case a "misaligned" bus access is made */
1.1.1.5 root 890: /* (e.g. used when addressing mode is d8(an,ix)) */
1.1.1.3 root 891: extern int BusCyclePenalty;
892:
1.1.1.5 root 893: /* To redirect WinUAE's prints to our own file */
894: extern FILE *console_out_FILE;
895:
896: /*** Hatari ***/
897: #endif
898:
1.1.1.6 root 899: #endif /* UAE_NEWCPU_H */
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